1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t AArch64RegDiffLists[] = {
12 /* 0 */ -18, 22, -20, -10, -285, 0,
13 /* 6 */ -10, 22, -20, -10, -285, 0,
14 /* 12 */ -18, 26, -20, -10, -285, 0,
15 /* 18 */ -10, 26, -20, -10, -285, 0,
16 /* 24 */ -18, 22, -18, -10, -285, 0,
17 /* 30 */ -10, 22, -18, -10, -285, 0,
18 /* 36 */ -18, 26, -18, -10, -285, 0,
19 /* 42 */ -10, 26, -18, -10, -285, 0,
20 /* 48 */ -18, 22, -20, -9, -285, 0,
21 /* 54 */ -10, 22, -20, -9, -285, 0,
22 /* 60 */ -18, 26, -20, -9, -285, 0,
23 /* 66 */ -10, 26, -20, -9, -285, 0,
24 /* 72 */ -18, 22, -18, -9, -285, 0,
25 /* 78 */ -10, 22, -18, -9, -285, 0,
26 /* 84 */ -18, 26, -18, -9, -285, 0,
27 /* 90 */ -10, 26, -18, -9, -285, 0,
28 /* 96 */ -505, -226, 0,
29 /* 99 */ -96, 128, -96, -64, 316, 64, 64, -96, 0,
30 /* 108 */ -523, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -251, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, 189, 64, -95, 30, 32, 32, 48, 64, -63, 64, -95, 0,
31 /* 156 */ -539, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -191, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 125, 64, -95, 30, 32, 32, 49, 64, -95, 30, 32, 32, 76, 64, -63, 64, -95, 0,
32 /* 218 */ -507, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -443, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, 92, 64, -63, 64, -95, 0,
33 /* 252 */ -523, -96, 128, -96, -64, 316, 64, 64, -96, -251, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, 157, 64, -63, 30, 32, 32, 48, 64, -95, 64, -63, 0,
34 /* 300 */ -539, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -191, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 93, 64, -63, 30, 32, 32, 17, 64, -63, 30, 32, 32, 76, 64, -95, 64, -63, 0,
35 /* 362 */ -507, 128, -96, -64, 316, 64, 64, -443, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, 92, 64, -95, 64, -63, 0,
36 /* 396 */ -523, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, 157, 64, -63, -2, 32, 32, 48, 64, -63, 64, -63, 0,
37 /* 444 */ -523, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -251, -96, 128, -96, -64, 316, 64, 64, -96, 189, 64, -63, -2, 32, 32, 48, 64, -63, 64, -63, 0,
38 /* 492 */ -507, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, 60, 64, -63, 64, -63, 0,
39 /* 526 */ -539, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 93, 64, -63, -2, 32, 32, 49, 64, -63, -2, 32, 32, 76, 64, -63, 64, -63, 0,
40 /* 588 */ -539, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -191, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 125, 64, -63, -2, 32, 32, 49, 64, -63, -2, 32, 32, 76, 64, -63, 64, -63, 0,
41 /* 650 */ -507, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -443, 128, -96, -64, 316, 64, 64, 92, 64, -63, 64, -63, 0,
42 /* 684 */ -555, -96, 128, -96, -64, 316, 64, 64, -96, -251, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, 158, 31, 64, 48, -31, 0,
43 /* 717 */ -571, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -191, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 94, 31, 64, 17, 31, 64, 76, -31, 0,
44 /* 759 */ -539, 128, -96, -64, 316, 64, 64, -443, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, 93, -31, 0,
45 /* 783 */ 31, 491, 2, -29, 0,
46 /* 788 */ -235, 756, 2, -29, 0,
47 /* 793 */ 31, 504, 17, -29, 0,
48 /* 798 */ 31, 505, 17, -29, 0,
49 /* 803 */ -253, 493, -29, 0,
50 /* 807 */ -253, 521, -29, 0,
51 /* 811 */ -253, 522, -29, 0,
52 /* 815 */ -519, 758, -29, 0,
53 /* 819 */ -3, 0,
54 /* 821 */ -2, 0,
55 /* 823 */ -483, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 235, 17, 1, 1, 1, -17, -1, -1, 0,
56 /* 856 */ -484, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 236, 17, 1, 1, 1, -17, -1, -1, 0,
57 /* 889 */ -485, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 237, 17, 1, 1, 1, -17, -1, -1, 0,
58 /* 922 */ -486, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 238, 17, 1, 1, 1, -17, -1, -1, 0,
59 /* 955 */ -487, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 239, 17, 1, 1, 1, -17, -1, -1, 0,
60 /* 988 */ -488, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 240, 17, 1, 1, 1, -17, -1, -1, 0,
61 /* 1021 */ -489, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 241, 17, 1, 1, 1, -17, -1, -1, 0,
62 /* 1054 */ -490, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 242, 17, 1, 1, 1, -17, -1, -1, 0,
63 /* 1087 */ -491, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 243, 17, 1, 1, 1, -17, -1, -1, 0,
64 /* 1120 */ -492, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 244, 17, 1, 1, 1, -17, -1, -1, 0,
65 /* 1153 */ -493, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, 245, 17, 1, 1, 1, -17, -1, -1, 0,
66 /* 1186 */ -470, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -252, -31, 284, -518, 235, 284, 234, 17, 1, 1, -14, -2, -1, -1, 0,
67 /* 1219 */ -536, 1, 0,
68 /* 1222 */ -535, 1, 0,
69 /* 1225 */ -534, 1, 0,
70 /* 1228 */ -533, 1, 0,
71 /* 1231 */ -532, 1, 0,
72 /* 1234 */ -531, 1, 0,
73 /* 1237 */ -530, 1, 0,
74 /* 1240 */ -529, 1, 0,
75 /* 1243 */ -528, 1, 0,
76 /* 1246 */ -527, 1, 0,
77 /* 1249 */ -526, 1, 0,
78 /* 1252 */ -525, 1, 0,
79 /* 1255 */ -524, 1, 0,
80 /* 1258 */ -523, 1, 0,
81 /* 1261 */ -522, 1, 0,
82 /* 1264 */ 63, -33, 34, -33, 1, 80, 63, -33, 34, -33, 1, 108, 63, -33, 34, -33, 1, 0,
83 /* 1282 */ 64, -32, 63, -33, 1, 49, 64, -32, 63, -33, 1, 77, 64, -32, 63, -33, 1, 0,
84 /* 1300 */ -33, 1, 144, -33, 1, 172, -33, 1, 0,
85 /* 1309 */ 31, 503, 17, -30, 1, 0,
86 /* 1315 */ 31, 504, 17, -30, 1, 0,
87 /* 1321 */ -253, 520, -30, 1, 0,
88 /* 1326 */ -253, 521, -30, 1, 0,
89 /* 1331 */ -2, 1, 0,
90 /* 1334 */ 31, 502, 17, -31, 1, 1, 0,
91 /* 1341 */ 31, 503, 17, -31, 1, 1, 0,
92 /* 1348 */ -253, 519, -31, 1, 1, 0,
93 /* 1354 */ -253, 520, -31, 1, 1, 0,
94 /* 1360 */ 31, 494, 17, -32, 1, 1, 1, 0,
95 /* 1368 */ 31, 495, 17, -32, 1, 1, 1, 0,
96 /* 1376 */ 31, 496, 17, -32, 1, 1, 1, 0,
97 /* 1384 */ 31, 497, 17, -32, 1, 1, 1, 0,
98 /* 1392 */ 31, 498, 17, -32, 1, 1, 1, 0,
99 /* 1400 */ 31, 499, 17, -32, 1, 1, 1, 0,
100 /* 1408 */ 31, 500, 17, -32, 1, 1, 1, 0,
101 /* 1416 */ 31, 501, 17, -32, 1, 1, 1, 0,
102 /* 1424 */ 31, 502, 17, -32, 1, 1, 1, 0,
103 /* 1432 */ -253, 511, -32, 1, 1, 1, 0,
104 /* 1439 */ -253, 512, -32, 1, 1, 1, 0,
105 /* 1446 */ -253, 513, -32, 1, 1, 1, 0,
106 /* 1453 */ -253, 514, -32, 1, 1, 1, 0,
107 /* 1460 */ -253, 515, -32, 1, 1, 1, 0,
108 /* 1467 */ -253, 516, -32, 1, 1, 1, 0,
109 /* 1474 */ -253, 517, -32, 1, 1, 1, 0,
110 /* 1481 */ -253, 518, -32, 1, 1, 1, 0,
111 /* 1488 */ -253, 519, -32, 1, 1, 1, 0,
112 /* 1495 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
113 /* 1511 */ 1, 1, 1, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
114 /* 1527 */ 1, 1, 1, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
115 /* 1543 */ 1, 1, 1, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
116 /* 1559 */ 1, 1, 1, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
117 /* 1575 */ 1, 1, 1, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
118 /* 1591 */ 1, 1, 1, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
119 /* 1607 */ 1, 1, 1, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
120 /* 1623 */ 1, 1, 1, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
121 /* 1639 */ 1, 1, 1, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
122 /* 1655 */ 1, 1, 1, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
123 /* 1671 */ 1, 1, 1, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
124 /* 1687 */ 1, 1, 1, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
125 /* 1703 */ 1, 1, 1, 53, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
126 /* 1719 */ 1, 1, 1, 55, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
127 /* 1735 */ 1, 1, 1, 57, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
128 /* 1751 */ 1, 1, 1, 59, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
129 /* 1767 */ 1, 1, 1, 61, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
130 /* 1783 */ 1, 1, 1, 63, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
131 /* 1799 */ 1, 1, 1, 65, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
132 /* 1815 */ 1, 1, 1, 67, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
133 /* 1831 */ 1, 1, 1, 69, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
134 /* 1847 */ 1, 1, 1, 71, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
135 /* 1863 */ 1, 1, 1, 73, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
136 /* 1879 */ 1, 1, 1, 75, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
137 /* 1895 */ 1, 1, 1, 77, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
138 /* 1911 */ 1, 1, 1, 79, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
139 /* 1927 */ 1, 1, 1, 81, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
140 /* 1943 */ 1, 1, 1, 83, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
141 /* 1959 */ 1, 1, 1, 85, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
142 /* 1975 */ 1, 1, 30, 1, 1, 1, 1, 1, 1, 1, 1, 0,
143 /* 1987 */ 1, 1, 32, 1, 1, 1, 1, 1, 1, 1, 1, 0,
144 /* 1999 */ 1, 1, 34, 1, 1, 1, 1, 1, 1, 1, 1, 0,
145 /* 2011 */ 1, 1, 36, 1, 1, 1, 1, 1, 1, 1, 1, 0,
146 /* 2023 */ 1, 1, 38, 1, 1, 1, 1, 1, 1, 1, 1, 0,
147 /* 2035 */ 1, 1, 40, 1, 1, 1, 1, 1, 1, 1, 1, 0,
148 /* 2047 */ 1, 1, 42, 1, 1, 1, 1, 1, 1, 1, 1, 0,
149 /* 2059 */ 1, 1, 44, 1, 1, 1, 1, 1, 1, 1, 1, 0,
150 /* 2071 */ 1, 1, 46, 1, 1, 1, 1, 1, 1, 1, 1, 0,
151 /* 2083 */ 1, 1, 48, 1, 1, 1, 1, 1, 1, 1, 1, 0,
152 /* 2095 */ 1, 1, 50, 1, 1, 1, 1, 1, 1, 1, 1, 0,
153 /* 2107 */ 1, 1, 52, 1, 1, 1, 1, 1, 1, 1, 1, 0,
154 /* 2119 */ 1, 1, 54, 1, 1, 1, 1, 1, 1, 1, 1, 0,
155 /* 2131 */ 1, 1, 56, 1, 1, 1, 1, 1, 1, 1, 1, 0,
156 /* 2143 */ 1, 1, 58, 1, 1, 1, 1, 1, 1, 1, 1, 0,
157 /* 2155 */ 1, 1, 60, 1, 1, 1, 1, 1, 1, 1, 1, 0,
158 /* 2167 */ 1, 1, 62, 1, 1, 1, 1, 1, 1, 1, 1, 0,
159 /* 2179 */ 1, 1, 64, 1, 1, 1, 1, 1, 1, 1, 1, 0,
160 /* 2191 */ 1, 1, 66, 1, 1, 1, 1, 1, 1, 1, 1, 0,
161 /* 2203 */ 1, 1, 68, 1, 1, 1, 1, 1, 1, 1, 1, 0,
162 /* 2215 */ 1, 1, 70, 1, 1, 1, 1, 1, 1, 1, 1, 0,
163 /* 2227 */ 1, 1, 72, 1, 1, 1, 1, 1, 1, 1, 1, 0,
164 /* 2239 */ 1, 1, 74, 1, 1, 1, 1, 1, 1, 1, 1, 0,
165 /* 2251 */ 1, 1, 76, 1, 1, 1, 1, 1, 1, 1, 1, 0,
166 /* 2263 */ 1, 1, 78, 1, 1, 1, 1, 1, 1, 1, 1, 0,
167 /* 2275 */ 1, 1, 80, 1, 1, 1, 1, 1, 1, 1, 1, 0,
168 /* 2287 */ 1, 1, 82, 1, 1, 1, 1, 1, 1, 1, 1, 0,
169 /* 2299 */ 1, 1, 84, 1, 1, 1, 1, 1, 1, 1, 1, 0,
170 /* 2311 */ 29, 1, 1, 1, 1, 1, 85, 1, 1, 1, 1, 1, 1, 1, 1, 0,
171 /* 2327 */ 1, 1, 86, 1, 1, 1, 1, 1, 1, 1, 1, 0,
172 /* 2339 */ 1, 1, 88, 1, 1, 1, 1, 1, 1, 1, 1, 0,
173 /* 2351 */ 1, 1, 1, 1, 1, 1, 1, 22, 1, 1, 1, 1, 1, 1, 1, 0,
174 /* 2367 */ 1, 226, 1, 1, 1, 1, 1, 1, 23, 1, 1, 1, 1, 1, 1, 0,
175 /* 2383 */ 1, 31, 1, 1, 1, 1, 1, 0,
176 /* 2391 */ 1, 33, 1, 1, 1, 1, 1, 0,
177 /* 2399 */ 1, 35, 1, 1, 1, 1, 1, 0,
178 /* 2407 */ 1, 37, 1, 1, 1, 1, 1, 0,
179 /* 2415 */ 1, 39, 1, 1, 1, 1, 1, 0,
180 /* 2423 */ 1, 41, 1, 1, 1, 1, 1, 0,
181 /* 2431 */ 1, 43, 1, 1, 1, 1, 1, 0,
182 /* 2439 */ 1, 45, 1, 1, 1, 1, 1, 0,
183 /* 2447 */ 1, 47, 1, 1, 1, 1, 1, 0,
184 /* 2455 */ 1, 49, 1, 1, 1, 1, 1, 0,
185 /* 2463 */ 1, 51, 1, 1, 1, 1, 1, 0,
186 /* 2471 */ 1, 53, 1, 1, 1, 1, 1, 0,
187 /* 2479 */ 1, 55, 1, 1, 1, 1, 1, 0,
188 /* 2487 */ 1, 57, 1, 1, 1, 1, 1, 0,
189 /* 2495 */ 1, 59, 1, 1, 1, 1, 1, 0,
190 /* 2503 */ 1, 61, 1, 1, 1, 1, 1, 0,
191 /* 2511 */ 1, 63, 1, 1, 1, 1, 1, 0,
192 /* 2519 */ 1, 65, 1, 1, 1, 1, 1, 0,
193 /* 2527 */ 1, 67, 1, 1, 1, 1, 1, 0,
194 /* 2535 */ 1, 69, 1, 1, 1, 1, 1, 0,
195 /* 2543 */ 1, 71, 1, 1, 1, 1, 1, 0,
196 /* 2551 */ 1, 73, 1, 1, 1, 1, 1, 0,
197 /* 2559 */ 1, 75, 1, 1, 1, 1, 1, 0,
198 /* 2567 */ 1, 77, 1, 1, 1, 1, 1, 0,
199 /* 2575 */ 1, 79, 1, 1, 1, 1, 1, 0,
200 /* 2583 */ 1, 81, 1, 1, 1, 1, 1, 0,
201 /* 2591 */ 1, 83, 1, 1, 1, 1, 1, 0,
202 /* 2599 */ 1, 29, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 1, 1, 1, 0,
203 /* 2615 */ 1, 87, 1, 1, 1, 1, 1, 0,
204 /* 2623 */ 30, 1, 1, 1, 1, 88, 1, 1, 1, 1, 1, 0,
205 /* 2635 */ 1, 89, 1, 1, 1, 1, 1, 0,
206 /* 2643 */ 1, 91, 1, 1, 1, 1, 1, 0,
207 /* 2651 */ 1, 1, 1, 85, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 45, 1, 1, 1, 0,
208 /* 2671 */ 1, 1, 1, 83, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 47, 1, 1, 1, 0,
209 /* 2691 */ 1, 1, 1, 81, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 49, 1, 1, 1, 0,
210 /* 2711 */ 1, 1, 1, 79, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 51, 1, 1, 1, 0,
211 /* 2731 */ 1, 1, 1, 77, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 53, 1, 1, 1, 0,
212 /* 2751 */ 1, 1, 1, 75, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 55, 1, 1, 1, 0,
213 /* 2771 */ 1, 1, 1, 73, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 57, 1, 1, 1, 0,
214 /* 2791 */ 1, 1, 1, 71, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 59, 1, 1, 1, 0,
215 /* 2811 */ 1, 1, 1, 69, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 61, 1, 1, 1, 0,
216 /* 2831 */ 1, 1, 1, 67, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 63, 1, 1, 1, 0,
217 /* 2851 */ 1, 1, 1, 65, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 65, 1, 1, 1, 0,
218 /* 2871 */ 1, 1, 1, 63, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 67, 1, 1, 1, 0,
219 /* 2891 */ 1, 1, 1, 61, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 69, 1, 1, 1, 0,
220 /* 2911 */ 1, 1, 1, 59, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 71, 1, 1, 1, 0,
221 /* 2931 */ 1, 1, 1, 57, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 73, 1, 1, 1, 0,
222 /* 2951 */ 1, 1, 1, 55, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 75, 1, 1, 1, 0,
223 /* 2971 */ 1, 1, 1, 53, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 77, 1, 1, 1, 0,
224 /* 2991 */ 1, 1, 1, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 79, 1, 1, 1, 0,
225 /* 3011 */ 1, 1, 1, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 81, 1, 1, 1, 0,
226 /* 3031 */ 1, 1, 1, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 83, 1, 1, 1, 0,
227 /* 3051 */ 1, 1, 1, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 1, 0,
228 /* 3071 */ 1, 1, 1, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 87, 1, 1, 1, 0,
229 /* 3091 */ 1, 1, 1, 85, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 45, 1, 1, 1, 87, 1, 1, 1, 0,
230 /* 3115 */ 1, 1, 1, 83, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 47, 1, 1, 1, 87, 1, 1, 1, 0,
231 /* 3139 */ 1, 1, 1, 81, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 49, 1, 1, 1, 87, 1, 1, 1, 0,
232 /* 3163 */ 1, 1, 1, 79, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 51, 1, 1, 1, 87, 1, 1, 1, 0,
233 /* 3187 */ 1, 1, 1, 77, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 53, 1, 1, 1, 87, 1, 1, 1, 0,
234 /* 3211 */ 1, 1, 1, 75, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 55, 1, 1, 1, 87, 1, 1, 1, 0,
235 /* 3235 */ 1, 1, 1, 73, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 57, 1, 1, 1, 87, 1, 1, 1, 0,
236 /* 3259 */ 1, 1, 1, 71, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 59, 1, 1, 1, 87, 1, 1, 1, 0,
237 /* 3283 */ 1, 1, 1, 69, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 61, 1, 1, 1, 87, 1, 1, 1, 0,
238 /* 3307 */ 1, 1, 1, 67, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 63, 1, 1, 1, 87, 1, 1, 1, 0,
239 /* 3331 */ 1, 1, 1, 65, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 65, 1, 1, 1, 87, 1, 1, 1, 0,
240 /* 3355 */ 1, 1, 1, 63, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 67, 1, 1, 1, 87, 1, 1, 1, 0,
241 /* 3379 */ 1, 1, 1, 61, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 69, 1, 1, 1, 87, 1, 1, 1, 0,
242 /* 3403 */ 1, 1, 1, 59, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 71, 1, 1, 1, 87, 1, 1, 1, 0,
243 /* 3427 */ 1, 1, 1, 57, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 73, 1, 1, 1, 87, 1, 1, 1, 0,
244 /* 3451 */ 1, 1, 1, 55, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 75, 1, 1, 1, 87, 1, 1, 1, 0,
245 /* 3475 */ 1, 1, 1, 53, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 77, 1, 1, 1, 87, 1, 1, 1, 0,
246 /* 3499 */ 1, 1, 1, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 79, 1, 1, 1, 87, 1, 1, 1, 0,
247 /* 3523 */ 1, 1, 1, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 81, 1, 1, 1, 87, 1, 1, 1, 0,
248 /* 3547 */ 1, 1, 1, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 83, 1, 1, 1, 87, 1, 1, 1, 0,
249 /* 3571 */ 1, 1, 1, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 1, 87, 1, 1, 1, 0,
250 /* 3595 */ 1, 1, 1, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 87, 1, 1, 1, 87, 1, 1, 1, 0,
251 /* 3619 */ 1, 1, 1, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 89, 1, 1, 1, 87, 1, 1, 1, 0,
252 /* 3643 */ 1, 1, 1, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 91, 1, 1, 1, 87, 1, 1, 1, 0,
253 /* 3667 */ 1, 1, 1, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 93, 1, 1, 1, 87, 1, 1, 1, 0,
254 /* 3691 */ 1, 1, 1, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 95, 1, 1, 1, 87, 1, 1, 1, 0,
255 /* 3715 */ 1, 1, 1, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 97, 1, 1, 1, 87, 1, 1, 1, 0,
256 /* 3739 */ 1, 1, 1, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 99, 1, 1, 1, 87, 1, 1, 1, 0,
257 /* 3763 */ 1, 1, 1, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 101, 1, 1, 1, 87, 1, 1, 1, 0,
258 /* 3787 */ 1, 1, 1, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 89, 1, 1, 1, 0,
259 /* 3807 */ 1, 1, 1, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 91, 1, 1, 1, 0,
260 /* 3827 */ 1, 1, 1, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 93, 1, 1, 1, 0,
261 /* 3847 */ 1, 1, 1, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 95, 1, 1, 1, 0,
262 /* 3867 */ 1, 1, 1, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 97, 1, 1, 1, 0,
263 /* 3887 */ 1, 1, 1, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 99, 1, 1, 1, 0,
264 /* 3907 */ 1, 1, 1, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 101, 1, 1, 1, 0,
265 /* 3927 */ 31, 493, 17, -41, 9, 1, 1, 0,
266 /* 3935 */ 31, 494, 17, -41, 9, 1, 1, 0,
267 /* 3943 */ -253, 510, -41, 9, 1, 1, 0,
268 /* 3950 */ -253, 511, -41, 9, 1, 1, 0,
269 /* 3957 */ 29, 1, 1, 1, 1, 1, 85, 1, 1, 1, 1, 1, 1, 1, 1, 17, 29, 1, 1, 0,
270 /* 3977 */ 29, 1, 1, 1, 1, 1, 85, 1, 1, 1, 1, 1, 1, 1, 1, 17, 29, 1, 1, 59, 29, 1, 1, 0,
271 /* 4001 */ 32, 1, 1, 0,
272 /* 4005 */ 34, 1, 1, 0,
273 /* 4009 */ 36, 1, 1, 0,
274 /* 4013 */ 38, 1, 1, 0,
275 /* 4017 */ 40, 1, 1, 0,
276 /* 4021 */ 42, 1, 1, 0,
277 /* 4025 */ 44, 1, 1, 0,
278 /* 4029 */ 1, 1, 88, 1, 1, 1, 1, 1, 1, 1, 1, 46, 1, 1, 0,
279 /* 4044 */ 1, 1, 86, 1, 1, 1, 1, 1, 1, 1, 1, 48, 1, 1, 0,
280 /* 4059 */ 1, 1, 84, 1, 1, 1, 1, 1, 1, 1, 1, 50, 1, 1, 0,
281 /* 4074 */ 1, 1, 82, 1, 1, 1, 1, 1, 1, 1, 1, 52, 1, 1, 0,
282 /* 4089 */ 1, 1, 80, 1, 1, 1, 1, 1, 1, 1, 1, 54, 1, 1, 0,
283 /* 4104 */ 1, 1, 78, 1, 1, 1, 1, 1, 1, 1, 1, 56, 1, 1, 0,
284 /* 4119 */ 1, 1, 76, 1, 1, 1, 1, 1, 1, 1, 1, 58, 1, 1, 0,
285 /* 4134 */ 1, 1, 74, 1, 1, 1, 1, 1, 1, 1, 1, 60, 1, 1, 0,
286 /* 4149 */ 1, 1, 72, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 1, 0,
287 /* 4164 */ 1, 1, 70, 1, 1, 1, 1, 1, 1, 1, 1, 64, 1, 1, 0,
288 /* 4179 */ 1, 1, 68, 1, 1, 1, 1, 1, 1, 1, 1, 66, 1, 1, 0,
289 /* 4194 */ 1, 1, 66, 1, 1, 1, 1, 1, 1, 1, 1, 68, 1, 1, 0,
290 /* 4209 */ 1, 1, 64, 1, 1, 1, 1, 1, 1, 1, 1, 70, 1, 1, 0,
291 /* 4224 */ 1, 1, 62, 1, 1, 1, 1, 1, 1, 1, 1, 72, 1, 1, 0,
292 /* 4239 */ 1, 1, 60, 1, 1, 1, 1, 1, 1, 1, 1, 74, 1, 1, 0,
293 /* 4254 */ 1, 1, 58, 1, 1, 1, 1, 1, 1, 1, 1, 76, 1, 1, 0,
294 /* 4269 */ 1, 1, 56, 1, 1, 1, 1, 1, 1, 1, 1, 78, 1, 1, 0,
295 /* 4284 */ 1, 1, 54, 1, 1, 1, 1, 1, 1, 1, 1, 80, 1, 1, 0,
296 /* 4299 */ 1, 1, 52, 1, 1, 1, 1, 1, 1, 1, 1, 82, 1, 1, 0,
297 /* 4314 */ 1, 1, 50, 1, 1, 1, 1, 1, 1, 1, 1, 84, 1, 1, 0,
298 /* 4329 */ 1, 1, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 0,
299 /* 4345 */ 1, 1, 48, 1, 1, 1, 1, 1, 1, 1, 1, 86, 1, 1, 0,
300 /* 4360 */ 1, 1, 46, 1, 1, 1, 1, 1, 1, 1, 1, 88, 1, 1, 0,
301 /* 4375 */ 1, 30, 1, 1, 1, 1, 1, 1, 88, 1, 1, 0,
302 /* 4387 */ 1, 1, 88, 1, 1, 1, 1, 1, 1, 1, 1, 46, 1, 1, 88, 1, 1, 0,
303 /* 4405 */ 1, 1, 86, 1, 1, 1, 1, 1, 1, 1, 1, 48, 1, 1, 88, 1, 1, 0,
304 /* 4423 */ 1, 1, 84, 1, 1, 1, 1, 1, 1, 1, 1, 50, 1, 1, 88, 1, 1, 0,
305 /* 4441 */ 1, 1, 82, 1, 1, 1, 1, 1, 1, 1, 1, 52, 1, 1, 88, 1, 1, 0,
306 /* 4459 */ 1, 1, 80, 1, 1, 1, 1, 1, 1, 1, 1, 54, 1, 1, 88, 1, 1, 0,
307 /* 4477 */ 1, 1, 78, 1, 1, 1, 1, 1, 1, 1, 1, 56, 1, 1, 88, 1, 1, 0,
308 /* 4495 */ 1, 1, 76, 1, 1, 1, 1, 1, 1, 1, 1, 58, 1, 1, 88, 1, 1, 0,
309 /* 4513 */ 1, 1, 74, 1, 1, 1, 1, 1, 1, 1, 1, 60, 1, 1, 88, 1, 1, 0,
310 /* 4531 */ 1, 1, 72, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 1, 88, 1, 1, 0,
311 /* 4549 */ 1, 1, 70, 1, 1, 1, 1, 1, 1, 1, 1, 64, 1, 1, 88, 1, 1, 0,
312 /* 4567 */ 1, 1, 68, 1, 1, 1, 1, 1, 1, 1, 1, 66, 1, 1, 88, 1, 1, 0,
313 /* 4585 */ 1, 1, 66, 1, 1, 1, 1, 1, 1, 1, 1, 68, 1, 1, 88, 1, 1, 0,
314 /* 4603 */ 1, 1, 64, 1, 1, 1, 1, 1, 1, 1, 1, 70, 1, 1, 88, 1, 1, 0,
315 /* 4621 */ 1, 1, 62, 1, 1, 1, 1, 1, 1, 1, 1, 72, 1, 1, 88, 1, 1, 0,
316 /* 4639 */ 1, 1, 60, 1, 1, 1, 1, 1, 1, 1, 1, 74, 1, 1, 88, 1, 1, 0,
317 /* 4657 */ 1, 1, 58, 1, 1, 1, 1, 1, 1, 1, 1, 76, 1, 1, 88, 1, 1, 0,
318 /* 4675 */ 1, 1, 56, 1, 1, 1, 1, 1, 1, 1, 1, 78, 1, 1, 88, 1, 1, 0,
319 /* 4693 */ 1, 1, 54, 1, 1, 1, 1, 1, 1, 1, 1, 80, 1, 1, 88, 1, 1, 0,
320 /* 4711 */ 1, 1, 52, 1, 1, 1, 1, 1, 1, 1, 1, 82, 1, 1, 88, 1, 1, 0,
321 /* 4729 */ 1, 1, 50, 1, 1, 1, 1, 1, 1, 1, 1, 84, 1, 1, 88, 1, 1, 0,
322 /* 4747 */ 1, 1, 48, 1, 1, 1, 1, 1, 1, 1, 1, 86, 1, 1, 88, 1, 1, 0,
323 /* 4765 */ 1, 1, 46, 1, 1, 1, 1, 1, 1, 1, 1, 88, 1, 1, 88, 1, 1, 0,
324 /* 4783 */ 1, 1, 44, 1, 1, 1, 1, 1, 1, 1, 1, 90, 1, 1, 88, 1, 1, 0,
325 /* 4801 */ 1, 1, 42, 1, 1, 1, 1, 1, 1, 1, 1, 92, 1, 1, 88, 1, 1, 0,
326 /* 4819 */ 1, 1, 40, 1, 1, 1, 1, 1, 1, 1, 1, 94, 1, 1, 88, 1, 1, 0,
327 /* 4837 */ 1, 1, 38, 1, 1, 1, 1, 1, 1, 1, 1, 96, 1, 1, 88, 1, 1, 0,
328 /* 4855 */ 1, 1, 36, 1, 1, 1, 1, 1, 1, 1, 1, 98, 1, 1, 88, 1, 1, 0,
329 /* 4873 */ 1, 1, 34, 1, 1, 1, 1, 1, 1, 1, 1, 100, 1, 1, 88, 1, 1, 0,
330 /* 4891 */ 1, 1, 32, 1, 1, 1, 1, 1, 1, 1, 1, 102, 1, 1, 88, 1, 1, 0,
331 /* 4909 */ 1, 1, 30, 1, 1, 1, 1, 1, 1, 1, 1, 104, 1, 1, 88, 1, 1, 0,
332 /* 4927 */ 1, 1, 44, 1, 1, 1, 1, 1, 1, 1, 1, 90, 1, 1, 0,
333 /* 4942 */ 31, 1, 1, 1, 91, 1, 1, 0,
334 /* 4950 */ 1, 1, 42, 1, 1, 1, 1, 1, 1, 1, 1, 92, 1, 1, 0,
335 /* 4965 */ 1, 1, 40, 1, 1, 1, 1, 1, 1, 1, 1, 94, 1, 1, 0,
336 /* 4980 */ 1, 1, 38, 1, 1, 1, 1, 1, 1, 1, 1, 96, 1, 1, 0,
337 /* 4995 */ 1, 1, 36, 1, 1, 1, 1, 1, 1, 1, 1, 98, 1, 1, 0,
338 /* 5010 */ 1, 1, 34, 1, 1, 1, 1, 1, 1, 1, 1, 100, 1, 1, 0,
339 /* 5025 */ 1, 1, 32, 1, 1, 1, 1, 1, 1, 1, 1, 102, 1, 1, 0,
340 /* 5040 */ 1, 1, 30, 1, 1, 1, 1, 1, 1, 1, 1, 104, 1, 1, 0,
341 /* 5055 */ 2, 1, 0,
342 /* 5058 */ 1, 5, 1, 0,
343 /* 5062 */ 31, 492, 17, -42, 10, 1, 0,
344 /* 5069 */ 31, 493, 17, -42, 10, 1, 0,
345 /* 5076 */ -253, 509, -42, 10, 1, 0,
346 /* 5082 */ -253, 510, -42, 10, 1, 0,
347 /* 5088 */ 1, 28, 1, 0,
348 /* 5092 */ 1, 29, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 1, 1, 1, 17, 1, 29, 1, 0,
349 /* 5112 */ 1, 29, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 1, 1, 1, 17, 1, 29, 1, 59, 1, 29, 1, 0,
350 /* 5136 */ 30, 1, 1, 1, 1, 88, 1, 1, 1, 1, 1, 17, 30, 1, 0,
351 /* 5151 */ 30, 1, 1, 1, 1, 88, 1, 1, 1, 1, 1, 17, 30, 1, 59, 30, 1, 0,
352 /* 5169 */ 32, 1, 0,
353 /* 5172 */ 34, 1, 0,
354 /* 5175 */ 36, 1, 0,
355 /* 5178 */ 38, 1, 0,
356 /* 5181 */ 40, 1, 0,
357 /* 5184 */ 42, 1, 0,
358 /* 5187 */ 44, 1, 0,
359 /* 5190 */ 46, 1, 0,
360 /* 5193 */ 1, 91, 1, 1, 1, 1, 1, 47, 1, 0,
361 /* 5203 */ -555, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, 158, -1, 64, 48, 1, 0,
362 /* 5236 */ -555, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, -251, -96, 128, -96, -64, 316, 64, 64, -96, 190, -1, 64, 48, 1, 0,
363 /* 5269 */ 1, 89, 1, 1, 1, 1, 1, 49, 1, 0,
364 /* 5279 */ 50, 1, 0,
365 /* 5282 */ 1, 87, 1, 1, 1, 1, 1, 51, 1, 0,
366 /* 5292 */ 52, 1, 0,
367 /* 5295 */ 1, 85, 1, 1, 1, 1, 1, 53, 1, 0,
368 /* 5305 */ 54, 1, 0,
369 /* 5308 */ 1, 83, 1, 1, 1, 1, 1, 55, 1, 0,
370 /* 5318 */ 56, 1, 0,
371 /* 5321 */ 1, 81, 1, 1, 1, 1, 1, 57, 1, 0,
372 /* 5331 */ 58, 1, 0,
373 /* 5334 */ 1, 79, 1, 1, 1, 1, 1, 59, 1, 0,
374 /* 5344 */ 60, 1, 0,
375 /* 5347 */ 1, 77, 1, 1, 1, 1, 1, 61, 1, 0,
376 /* 5357 */ -539, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, 61, 1, 0,
377 /* 5381 */ 62, 1, 0,
378 /* 5384 */ 1, 75, 1, 1, 1, 1, 1, 63, 1, 0,
379 /* 5394 */ 64, 1, 0,
380 /* 5397 */ 1, 73, 1, 1, 1, 1, 1, 65, 1, 0,
381 /* 5407 */ 66, 1, 0,
382 /* 5410 */ 1, 71, 1, 1, 1, 1, 1, 67, 1, 0,
383 /* 5420 */ 68, 1, 0,
384 /* 5423 */ 1, 69, 1, 1, 1, 1, 1, 69, 1, 0,
385 /* 5433 */ 70, 1, 0,
386 /* 5436 */ 1, 67, 1, 1, 1, 1, 1, 71, 1, 0,
387 /* 5446 */ 72, 1, 0,
388 /* 5449 */ 1, 65, 1, 1, 1, 1, 1, 73, 1, 0,
389 /* 5459 */ 74, 1, 0,
390 /* 5462 */ 1, 63, 1, 1, 1, 1, 1, 75, 1, 0,
391 /* 5472 */ -571, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 94, -1, 64, 49, -1, 64, 76, 1, 0,
392 /* 5514 */ -571, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -191, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 126, -1, 64, 49, -1, 64, 76, 1, 0,
393 /* 5556 */ 1, 61, 1, 1, 1, 1, 1, 77, 1, 0,
394 /* 5566 */ 78, 1, 0,
395 /* 5569 */ 1, 59, 1, 1, 1, 1, 1, 79, 1, 0,
396 /* 5579 */ 80, 1, 0,
397 /* 5582 */ 1, 57, 1, 1, 1, 1, 1, 81, 1, 0,
398 /* 5592 */ 82, 1, 0,
399 /* 5595 */ 1, 55, 1, 1, 1, 1, 1, 83, 1, 0,
400 /* 5605 */ 84, 1, 0,
401 /* 5608 */ 1, 53, 1, 1, 1, 1, 1, 85, 1, 0,
402 /* 5618 */ 86, 1, 0,
403 /* 5621 */ 1, 51, 1, 1, 1, 1, 1, 87, 1, 0,
404 /* 5631 */ 88, 1, 0,
405 /* 5634 */ 1, 49, 1, 1, 1, 1, 1, 89, 1, 0,
406 /* 5644 */ 1, 91, 1, 1, 1, 1, 1, 47, 1, 89, 1, 0,
407 /* 5656 */ 1, 89, 1, 1, 1, 1, 1, 49, 1, 89, 1, 0,
408 /* 5668 */ 1, 87, 1, 1, 1, 1, 1, 51, 1, 89, 1, 0,
409 /* 5680 */ 1, 85, 1, 1, 1, 1, 1, 53, 1, 89, 1, 0,
410 /* 5692 */ 1, 83, 1, 1, 1, 1, 1, 55, 1, 89, 1, 0,
411 /* 5704 */ 1, 81, 1, 1, 1, 1, 1, 57, 1, 89, 1, 0,
412 /* 5716 */ 1, 79, 1, 1, 1, 1, 1, 59, 1, 89, 1, 0,
413 /* 5728 */ 1, 77, 1, 1, 1, 1, 1, 61, 1, 89, 1, 0,
414 /* 5740 */ 1, 75, 1, 1, 1, 1, 1, 63, 1, 89, 1, 0,
415 /* 5752 */ 1, 73, 1, 1, 1, 1, 1, 65, 1, 89, 1, 0,
416 /* 5764 */ 1, 71, 1, 1, 1, 1, 1, 67, 1, 89, 1, 0,
417 /* 5776 */ 1, 69, 1, 1, 1, 1, 1, 69, 1, 89, 1, 0,
418 /* 5788 */ 1, 67, 1, 1, 1, 1, 1, 71, 1, 89, 1, 0,
419 /* 5800 */ 1, 65, 1, 1, 1, 1, 1, 73, 1, 89, 1, 0,
420 /* 5812 */ 1, 63, 1, 1, 1, 1, 1, 75, 1, 89, 1, 0,
421 /* 5824 */ 1, 61, 1, 1, 1, 1, 1, 77, 1, 89, 1, 0,
422 /* 5836 */ 1, 59, 1, 1, 1, 1, 1, 79, 1, 89, 1, 0,
423 /* 5848 */ 1, 57, 1, 1, 1, 1, 1, 81, 1, 89, 1, 0,
424 /* 5860 */ 1, 55, 1, 1, 1, 1, 1, 83, 1, 89, 1, 0,
425 /* 5872 */ 1, 53, 1, 1, 1, 1, 1, 85, 1, 89, 1, 0,
426 /* 5884 */ 1, 51, 1, 1, 1, 1, 1, 87, 1, 89, 1, 0,
427 /* 5896 */ 1, 49, 1, 1, 1, 1, 1, 89, 1, 89, 1, 0,
428 /* 5908 */ 1, 47, 1, 1, 1, 1, 1, 91, 1, 89, 1, 0,
429 /* 5920 */ 1, 45, 1, 1, 1, 1, 1, 93, 1, 89, 1, 0,
430 /* 5932 */ 1, 43, 1, 1, 1, 1, 1, 95, 1, 89, 1, 0,
431 /* 5944 */ 1, 41, 1, 1, 1, 1, 1, 97, 1, 89, 1, 0,
432 /* 5956 */ 1, 39, 1, 1, 1, 1, 1, 99, 1, 89, 1, 0,
433 /* 5968 */ 1, 37, 1, 1, 1, 1, 1, 101, 1, 89, 1, 0,
434 /* 5980 */ 1, 35, 1, 1, 1, 1, 1, 103, 1, 89, 1, 0,
435 /* 5992 */ 1, 33, 1, 1, 1, 1, 1, 105, 1, 89, 1, 0,
436 /* 6004 */ 1, 31, 1, 1, 1, 1, 1, 107, 1, 89, 1, 0,
437 /* 6016 */ 90, 1, 0,
438 /* 6019 */ 1, 47, 1, 1, 1, 1, 1, 91, 1, 0,
439 /* 6029 */ 92, 1, 0,
440 /* 6032 */ 1, 45, 1, 1, 1, 1, 1, 93, 1, 0,
441 /* 6042 */ -539, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, -443, 128, -96, -64, 316, 64, 64, 93, 1, 0,
442 /* 6066 */ 94, 1, 0,
443 /* 6069 */ 1, 43, 1, 1, 1, 1, 1, 95, 1, 0,
444 /* 6079 */ 1, 41, 1, 1, 1, 1, 1, 97, 1, 0,
445 /* 6089 */ 1, 39, 1, 1, 1, 1, 1, 99, 1, 0,
446 /* 6099 */ 1, 37, 1, 1, 1, 1, 1, 101, 1, 0,
447 /* 6109 */ 1, 35, 1, 1, 1, 1, 1, 103, 1, 0,
448 /* 6119 */ 1, 33, 1, 1, 1, 1, 1, 105, 1, 0,
449 /* 6129 */ 1, 31, 1, 1, 1, 1, 1, 107, 1, 0,
450 /* 6139 */ -16, 506, 1, 0,
451 /* 6143 */ 4, 4, 4, 58, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 36, 4, 4, 4, 78, 4, 4, 4, 0,
452 /* 6167 */ 4, 4, 4, 56, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 38, 4, 4, 4, 78, 4, 4, 4, 0,
453 /* 6191 */ 4, 4, 4, 54, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 40, 4, 4, 4, 78, 4, 4, 4, 0,
454 /* 6215 */ 4, 4, 4, 52, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 42, 4, 4, 4, 78, 4, 4, 4, 0,
455 /* 6239 */ 4, 4, 4, 26, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 68, 4, 4, 4, 78, 4, 4, 4, 0,
456 /* 6263 */ 4, 4, 4, 24, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 70, 4, 4, 4, 78, 4, 4, 4, 0,
457 /* 6287 */ 4, 4, 4, 22, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 72, 4, 4, 4, 78, 4, 4, 4, 0,
458 /* 6311 */ 4, 4, 4, 20, 1, 1, 10, 1, 1, 10, 1, 1, 10, 1, 1, 74, 4, 4, 4, 78, 4, 4, 4, 0,
459 /* 6335 */ -603, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -156, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -156, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -156, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 415, 4, 0,
460 /* 6382 */ -623, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -156, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -156, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -156, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 439, 4, 0,
461 /* 6429 */ 6, 0,
462 /* 6431 */ 285, 9, 18, -26, 10, 8, -14, 10, 8, 6, -26, 10, 8, -14, 10, 8, -15, 18, -26, 10, 8, -14, 10, 8, 6, -26, 10, 8, -14, 10, 8, 0,
463 /* 6463 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 8, 0,
464 /* 6496 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 8, 0,
465 /* 6530 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 8, 0,
466 /* 6565 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 8, 0,
467 /* 6600 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 8, 0,
468 /* 6623 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 64, 8, 0,
469 /* 6636 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 8, 0,
470 /* 6669 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 8, 0,
471 /* 6703 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 8, 0,
472 /* 6738 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 8, 0,
473 /* 6773 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 8, 0,
474 /* 6796 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 72, 8, 0,
475 /* 6809 */ 8, 70, 1, 1, 22, 1, 1, 40, 8, 82, 8, 0,
476 /* 6821 */ 8, 68, 1, 1, 22, 1, 1, 42, 8, 82, 8, 0,
477 /* 6833 */ 8, 66, 1, 1, 22, 1, 1, 44, 8, 82, 8, 0,
478 /* 6845 */ 8, 64, 1, 1, 22, 1, 1, 46, 8, 82, 8, 0,
479 /* 6857 */ 8, 62, 1, 1, 22, 1, 1, 48, 8, 82, 8, 0,
480 /* 6869 */ 8, 60, 1, 1, 22, 1, 1, 50, 8, 82, 8, 0,
481 /* 6881 */ 8, 58, 1, 1, 22, 1, 1, 52, 8, 82, 8, 0,
482 /* 6893 */ 8, 56, 1, 1, 22, 1, 1, 54, 8, 82, 8, 0,
483 /* 6905 */ 8, 38, 1, 1, 22, 1, 1, 72, 8, 82, 8, 0,
484 /* 6917 */ 8, 36, 1, 1, 22, 1, 1, 74, 8, 82, 8, 0,
485 /* 6929 */ 8, 34, 1, 1, 22, 1, 1, 76, 8, 82, 8, 0,
486 /* 6941 */ 8, 32, 1, 1, 22, 1, 1, 78, 8, 82, 8, 0,
487 /* 6953 */ 8, 30, 1, 1, 22, 1, 1, 80, 8, 82, 8, 0,
488 /* 6965 */ 8, 28, 1, 1, 22, 1, 1, 82, 8, 82, 8, 0,
489 /* 6977 */ 8, 26, 1, 1, 22, 1, 1, 84, 8, 82, 8, 0,
490 /* 6989 */ 8, 24, 1, 1, 22, 1, 1, 86, 8, 82, 8, 0,
491 /* 7001 */ 31, 491, 17, -43, 11, 0,
492 /* 7007 */ 31, 492, 17, -43, 11, 0,
493 /* 7013 */ -253, 508, -43, 11, 0,
494 /* 7018 */ -253, 509, -43, 11, 0,
495 /* 7023 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 12, 0,
496 /* 7056 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 12, 0,
497 /* 7090 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 12, 0,
498 /* 7125 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 12, 0,
499 /* 7160 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 12, 0,
500 /* 7183 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 40, 12, 0,
501 /* 7196 */ -412, 96, 124, 255, 31, 33, -32, 62, -33, 34, -33, 1, 49, 31, 33, -32, 62, -33, 34, -33, 1, 77, 31, 33, -32, 62, -33, 34, -33, 1, 41, 12, 0,
502 /* 7229 */ -220, -128, 96, 124, 255, 31, 33, -32, 62, -33, 34, -33, 1, 49, 31, 33, -32, 62, -33, 34, -33, 1, 77, 31, 33, -32, 62, -33, 34, -33, 1, 41, 12, 0,
503 /* 7263 */ -252, 96, -128, 96, 124, 255, 31, 33, -32, 62, -33, 34, -33, 1, 49, 31, 33, -32, 62, -33, 34, -33, 1, 77, 31, 33, -32, 62, -33, 34, -33, 1, 41, 12, 0,
504 /* 7298 */ 64, 96, -128, 96, 124, 255, 31, 33, -32, 62, -33, 34, -33, 1, 49, 31, 33, -32, 62, -33, 34, -33, 1, 77, 31, 33, -32, 62, -33, 34, -33, 1, 41, 12, 0,
505 /* 7333 */ -220, 124, 367, 31, 33, -32, 62, -33, 34, -33, 1, 77, 31, 33, -32, 62, -33, 34, -33, 1, 41, 12, 0,
506 /* 7356 */ -160, 507, 31, 33, -32, 62, -33, 34, -33, 1, 41, 12, 0,
507 /* 7369 */ -412, 96, 124, 254, 1, 63, 1, -33, 1, 62, -33, 1, 49, 1, 63, 1, -33, 1, 62, -33, 1, 77, 1, 63, 1, -33, 1, 62, -33, 1, 42, 12, 0,
508 /* 7402 */ -220, -128, 96, 124, 254, 1, 63, 1, -33, 1, 62, -33, 1, 49, 1, 63, 1, -33, 1, 62, -33, 1, 77, 1, 63, 1, -33, 1, 62, -33, 1, 42, 12, 0,
509 /* 7436 */ -252, 96, -128, 96, 124, 254, 1, 63, 1, -33, 1, 62, -33, 1, 49, 1, 63, 1, -33, 1, 62, -33, 1, 77, 1, 63, 1, -33, 1, 62, -33, 1, 42, 12, 0,
510 /* 7471 */ 64, 96, -128, 96, 124, 254, 1, 63, 1, -33, 1, 62, -33, 1, 49, 1, 63, 1, -33, 1, 62, -33, 1, 77, 1, 63, 1, -33, 1, 62, -33, 1, 42, 12, 0,
511 /* 7506 */ -220, 124, 366, 1, 63, 1, -33, 1, 62, -33, 1, 77, 1, 63, 1, -33, 1, 62, -33, 1, 42, 12, 0,
512 /* 7529 */ -160, 506, 1, 63, 1, -33, 1, 62, -33, 1, 42, 12, 0,
513 /* 7542 */ -412, 96, 124, 254, 1, 62, 1, -33, 34, -33, 1, 29, 50, 1, 62, 1, -33, 34, -33, 1, 29, 78, 1, 62, 1, -33, 34, -33, 1, 29, 43, 12, 0,
514 /* 7575 */ -220, -128, 96, 124, 254, 1, 62, 1, -33, 34, -33, 1, 29, 50, 1, 62, 1, -33, 34, -33, 1, 29, 78, 1, 62, 1, -33, 34, -33, 1, 29, 43, 12, 0,
515 /* 7609 */ -252, 96, -128, 96, 124, 254, 1, 62, 1, -33, 34, -33, 1, 29, 50, 1, 62, 1, -33, 34, -33, 1, 29, 78, 1, 62, 1, -33, 34, -33, 1, 29, 43, 12, 0,
516 /* 7644 */ 64, 96, -128, 96, 124, 254, 1, 62, 1, -33, 34, -33, 1, 29, 50, 1, 62, 1, -33, 34, -33, 1, 29, 78, 1, 62, 1, -33, 34, -33, 1, 29, 43, 12, 0,
517 /* 7679 */ -220, 124, 366, 1, 62, 1, -33, 34, -33, 1, 29, 78, 1, 62, 1, -33, 34, -33, 1, 29, 43, 12, 0,
518 /* 7702 */ -160, 506, 1, 62, 1, -33, 34, -33, 1, 29, 43, 12, 0,
519 /* 7715 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 12, 0,
520 /* 7748 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 12, 0,
521 /* 7782 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 12, 0,
522 /* 7817 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 12, 0,
523 /* 7852 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 12, 0,
524 /* 7875 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 48, 12, 0,
525 /* 7888 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 12, 0,
526 /* 7921 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 12, 0,
527 /* 7955 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 12, 0,
528 /* 7990 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 12, 0,
529 /* 8025 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 64, 12, 0,
530 /* 8048 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 64, 12, 0,
531 /* 8061 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 12, 0,
532 /* 8094 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 12, 0,
533 /* 8128 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 12, 0,
534 /* 8163 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 12, 0,
535 /* 8198 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 72, 12, 0,
536 /* 8221 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 72, 12, 0,
537 /* 8234 */ -16, 507, 15, 0,
538 /* 8238 */ -507, 16, -31, 16, 0,
539 /* 8243 */ -507, 16, -15, 16, 0,
540 /* 8248 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 16, 0,
541 /* 8281 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 16, 0,
542 /* 8315 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 16, 0,
543 /* 8350 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 16, 0,
544 /* 8385 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 40, 16, 0,
545 /* 8408 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 40, 16, 0,
546 /* 8421 */ -412, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 16, 0,
547 /* 8454 */ -220, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 16, 0,
548 /* 8488 */ -252, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 16, 0,
549 /* 8523 */ 64, 96, -128, 96, 124, 254, 1, 62, -33, 34, -33, 34, -33, 1, 79, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 16, 0,
550 /* 8558 */ -220, 124, 366, 1, 62, -33, 34, -33, 34, -33, 1, 107, 1, 62, -33, 34, -33, 34, -33, 1, 48, 16, 0,
551 /* 8581 */ -160, 506, 1, 62, -33, 34, -33, 34, -33, 1, 48, 16, 0,
552 /* 8594 */ 2, 729, 16, 0,
553 /* 8598 */ -232, 737, 16, 0,
554 /* 8602 */ 1, 1, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 17, 1, 1, 29, 0,
555 /* 8622 */ 1, 1, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 85, 1, 1, 17, 1, 1, 29, 59, 1, 1, 29, 0,
556 /* 8646 */ 1, 232, 29, 0,
557 /* 8650 */ 63, 1, -33, 1, 30, 50, 63, 1, -33, 1, 30, 78, 63, 1, -33, 1, 30, 0,
558 /* 8668 */ 1, 30, 1, 1, 1, 1, 1, 1, 88, 1, 1, 17, 1, 30, 0,
559 /* 8683 */ 1, 30, 1, 1, 1, 1, 1, 1, 88, 1, 1, 17, 1, 30, 59, 1, 30, 0,
560 /* 8701 */ -32, 31, 113, -32, 31, 141, -32, 31, 0,
561 /* 8710 */ 31, 1, 1, 1, 91, 1, 1, 17, 31, 0,
562 /* 8720 */ 31, 1, 1, 1, 91, 1, 1, 17, 31, 59, 31, 0,
563 /* 8732 */ 32, 0,
564 /* 8734 */ 34, 0,
565 /* 8736 */ 36, 0,
566 /* 8738 */ 38, 0,
567 /* 8740 */ 40, 0,
568 /* 8742 */ 42, 0,
569 /* 8744 */ 44, 0,
570 /* 8746 */ 46, 0,
571 /* 8748 */ 94, 1, 1, 48, 0,
572 /* 8753 */ 92, 1, 1, 50, 0,
573 /* 8758 */ 90, 1, 1, 52, 0,
574 /* 8763 */ 88, 1, 1, 54, 0,
575 /* 8768 */ 86, 1, 1, 56, 0,
576 /* 8773 */ 84, 1, 1, 58, 0,
577 /* 8778 */ 82, 1, 1, 60, 0,
578 /* 8783 */ 80, 1, 1, 62, 0,
579 /* 8788 */ -611, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -152, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 0,
580 /* 8811 */ -587, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -152, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 0,
581 /* 8834 */ 78, 1, 1, 64, 0,
582 /* 8839 */ -475, 128, -96, -64, 316, 64, 64, -443, 128, -96, -64, 316, 64, 64, 0,
583 /* 8854 */ -475, 128, -96, -64, 316, 64, 64, -411, 128, -96, -64, 316, 64, 64, 0,
584 /* 8869 */ -96, -64, 316, 64, 0,
585 /* 8874 */ 76, 1, 1, 66, 0,
586 /* 8879 */ 74, 1, 1, 68, 0,
587 /* 8884 */ 72, 1, 1, 70, 0,
588 /* 8889 */ 70, 1, 1, 72, 0,
589 /* 8894 */ 68, 1, 1, 74, 0,
590 /* 8899 */ 66, 1, 1, 76, 0,
591 /* 8904 */ 64, 1, 1, 78, 0,
592 /* 8909 */ 62, 1, 1, 80, 0,
593 /* 8914 */ 60, 1, 1, 82, 0,
594 /* 8919 */ 58, 1, 1, 84, 0,
595 /* 8924 */ 56, 1, 1, 86, 0,
596 /* 8929 */ 54, 1, 1, 88, 0,
597 /* 8934 */ 52, 1, 1, 90, 0,
598 /* 8939 */ 94, 1, 1, 48, 90, 0,
599 /* 8945 */ 92, 1, 1, 50, 90, 0,
600 /* 8951 */ 90, 1, 1, 52, 90, 0,
601 /* 8957 */ 88, 1, 1, 54, 90, 0,
602 /* 8963 */ 86, 1, 1, 56, 90, 0,
603 /* 8969 */ 84, 1, 1, 58, 90, 0,
604 /* 8975 */ 82, 1, 1, 60, 90, 0,
605 /* 8981 */ 80, 1, 1, 62, 90, 0,
606 /* 8987 */ 78, 1, 1, 64, 90, 0,
607 /* 8993 */ 76, 1, 1, 66, 90, 0,
608 /* 8999 */ 74, 1, 1, 68, 90, 0,
609 /* 9005 */ 72, 1, 1, 70, 90, 0,
610 /* 9011 */ 70, 1, 1, 72, 90, 0,
611 /* 9017 */ 68, 1, 1, 74, 90, 0,
612 /* 9023 */ 66, 1, 1, 76, 90, 0,
613 /* 9029 */ 64, 1, 1, 78, 90, 0,
614 /* 9035 */ 62, 1, 1, 80, 90, 0,
615 /* 9041 */ 60, 1, 1, 82, 90, 0,
616 /* 9047 */ 58, 1, 1, 84, 90, 0,
617 /* 9053 */ 56, 1, 1, 86, 90, 0,
618 /* 9059 */ 54, 1, 1, 88, 90, 0,
619 /* 9065 */ 52, 1, 1, 90, 90, 0,
620 /* 9071 */ 50, 1, 1, 92, 90, 0,
621 /* 9077 */ 48, 1, 1, 94, 90, 0,
622 /* 9083 */ 46, 1, 1, 96, 90, 0,
623 /* 9089 */ 44, 1, 1, 98, 90, 0,
624 /* 9095 */ 42, 1, 1, 100, 90, 0,
625 /* 9101 */ 40, 1, 1, 102, 90, 0,
626 /* 9107 */ 38, 1, 1, 104, 90, 0,
627 /* 9113 */ 36, 1, 1, 106, 90, 0,
628 /* 9119 */ 34, 1, 1, 108, 90, 0,
629 /* 9125 */ 32, 1, 1, 110, 90, 0,
630 /* 9131 */ 50, 1, 1, 92, 0,
631 /* 9136 */ 48, 1, 1, 94, 0,
632 /* 9141 */ 46, 1, 1, 96, 0,
633 /* 9146 */ 44, 1, 1, 98, 0,
634 /* 9151 */ 42, 1, 1, 100, 0,
635 /* 9156 */ 40, 1, 1, 102, 0,
636 /* 9161 */ 38, 1, 1, 104, 0,
637 /* 9166 */ 36, 1, 1, 106, 0,
638 /* 9171 */ 34, 1, 1, 108, 0,
639 /* 9176 */ 32, 1, 1, 110, 0,
640 /* 9181 */ -507, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -159, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 94, 112, 0,
641 /* 9206 */ -507, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, -191, -124, -96, 128, -96, -64, 316, 64, 64, -96, 64, 126, 112, 0,
642 /* 9231 */ 112, 140, 0,
643 /* 9234 */ -491, -96, 128, -96, -64, 316, 64, 64, -96, -219, -96, 128, -96, -64, 316, 64, 64, -96, 158, 0,
644 /* 9254 */ -491, -96, 128, -96, -64, 316, 64, 64, -96, -251, -96, 128, -96, -64, 316, 64, 64, -96, 190, 0,
645 /* 9274 */ 233, 0,
646 /* 9276 */ -493, -31, 284, -518, 235, 284, 237, 0,
647 /* 9284 */ -509, -31, 284, -252, -31, 284, 238, 0,
648 /* 9292 */ -510, -31, 284, -252, -31, 284, 239, 0,
649 /* 9300 */ -511, -31, 284, -252, -31, 284, 240, 0,
650 /* 9308 */ -512, -31, 284, -252, -31, 284, 241, 0,
651 /* 9316 */ -513, -31, 284, -252, -31, 284, 242, 0,
652 /* 9324 */ -514, -31, 284, -252, -31, 284, 243, 0,
653 /* 9332 */ -515, -31, 284, -252, -31, 284, 244, 0,
654 /* 9340 */ -516, -31, 284, -252, -31, 284, 245, 0,
655 /* 9348 */ -517, -31, 284, -252, -31, 284, 246, 0,
656 /* 9356 */ -518, -31, 284, -252, -31, 284, 247, 0,
657 /* 9364 */ -519, -31, 284, -252, -31, 284, 248, 0,
658 /* 9372 */ -520, -31, 284, -252, -31, 284, 249, 0,
659 /* 9380 */ -521, -31, 284, -252, -31, 284, 250, 0,
660 /* 9388 */ -522, -31, 284, -252, -31, 284, 251, 0,
661 /* 9396 */ -31, 284, 0,
662 /* 9399 */ 232, 284, 0,
663 /* 9402 */ 235, 284, 0,
664 /* 9405 */ -64, 316, 0,
665 /* 9408 */ -753, 232, 284, -508, -2, 1, 730, 0,
666 /* 9416 */ 1, 745, 0,
667 /* 9419 */ -516, 753, 0,
668};
669
670extern const LaneBitmask AArch64LaneMaskLists[] = {
671 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
672 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000004),
673 /* 7 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000000000000004),
674 /* 17 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000020000000000), LaneBitmask(0x0000000000000004),
675 /* 37 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000000000000004),
676 /* 52 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008),
677 /* 55 */ LaneBitmask(0x0000008000000000), LaneBitmask(0x0000000000000010),
678 /* 57 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020),
679 /* 61 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020),
680 /* 69 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020),
681 /* 85 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020),
682 /* 97 */ LaneBitmask(0x0200000000000000), LaneBitmask(0x0400000000000000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
683 /* 101 */ LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000100),
684 /* 103 */ LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200),
685 /* 105 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800),
686 /* 107 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000001000),
687 /* 113 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0800000000000000), LaneBitmask(0x0000000000001000),
688 /* 125 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000020000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0800000000000000), LaneBitmask(0x2000000000000000), LaneBitmask(0x1000000000000000), LaneBitmask(0x0000000000001000),
689 /* 149 */ LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0800000000000000), LaneBitmask(0x2000000000000000), LaneBitmask(0x0000000000001000),
690 /* 167 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000),
691 /* 171 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000040000),
692 /* 179 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000001000000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000004000000),
693 /* 195 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000),
694 /* 203 */ LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000),
695 /* 219 */ LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000),
696 /* 231 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000),
697 /* 247 */ LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000),
698 /* 263 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000),
699 /* 275 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000008000000000),
700 /* 277 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000),
701 /* 287 */ LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000020000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000),
702 /* 307 */ LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000),
703 /* 322 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000020000000000),
704 /* 342 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000),
705 /* 357 */ LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000020000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000),
706 /* 377 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0080000000000000), LaneBitmask(0x0020000000000000), LaneBitmask(0x0008000000000000), LaneBitmask(0x0002000000000000), LaneBitmask(0x0000800000000000), LaneBitmask(0x0000200000000000), LaneBitmask(0x0000080000000000), LaneBitmask(0x0000000000000080), LaneBitmask(0x0100000000000000), LaneBitmask(0x0040000000000000), LaneBitmask(0x0010000000000000), LaneBitmask(0x0004000000000000), LaneBitmask(0x0001000000000000), LaneBitmask(0x0000400000000000), LaneBitmask(0x0000100000000000),
707 /* 393 */ LaneBitmask(0x0000080000000000), LaneBitmask(0x0000100000000000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0080000000000000), LaneBitmask(0x0020000000000000), LaneBitmask(0x0008000000000000), LaneBitmask(0x0002000000000000), LaneBitmask(0x0000800000000000), LaneBitmask(0x0000200000000000), LaneBitmask(0x0000000000000080), LaneBitmask(0x0100000000000000), LaneBitmask(0x0040000000000000), LaneBitmask(0x0010000000000000), LaneBitmask(0x0004000000000000), LaneBitmask(0x0001000000000000), LaneBitmask(0x0000400000000000),
708 /* 409 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0200000000000000), LaneBitmask(0x0000000000000080), LaneBitmask(0x0400000000000000),
709 /* 413 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0200000000000000), LaneBitmask(0x0400000000000000),
710 /* 417 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000000000001000), LaneBitmask(0x0800000000000000),
711 /* 429 */ LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000020000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x2000000000000000), LaneBitmask(0x1000000000000000), LaneBitmask(0x0000000000001000), LaneBitmask(0x0800000000000000),
712 /* 453 */ LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x2000000000000000), LaneBitmask(0x0000000000001000), LaneBitmask(0x0800000000000000),
713 /* 471 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000020000000000), LaneBitmask(0x0000000000001000), LaneBitmask(0x0800000000000000), LaneBitmask(0x2000000000000000), LaneBitmask(0x1000000000000000),
714 /* 495 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x0000000000001000), LaneBitmask(0x0800000000000000), LaneBitmask(0x2000000000000000),
715 /* 513 */ LaneBitmask(0x0000000080000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000800000000), LaneBitmask(0x0000000100000000), LaneBitmask(0x0000000200000000), LaneBitmask(0x0000000400000000), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000001000000000), LaneBitmask(0x0000002000000000), LaneBitmask(0x0000004000000000), LaneBitmask(0x0000020000000000), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000010000000000), LaneBitmask(0x0000040000000000), LaneBitmask(0x1000000000000000), LaneBitmask(0x0000000000001000), LaneBitmask(0x0800000000000000), LaneBitmask(0x2000000000000000),
716 /* 537 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
717};
718
719extern const uint16_t AArch64SubRegIdxLists[] = {
720 /* 0 */ 1, 2,
721 /* 2 */ 3, 18, 9, 1, 2, 10, 19, 8,
722 /* 10 */ 9, 1, 2, 10,
723 /* 14 */ 11,
724 /* 15 */ 18, 9, 1, 2, 10, 19,
725 /* 21 */ 20, 21,
726 /* 23 */ 22, 24,
727 /* 25 */ 39, 40,
728 /* 27 */ 43, 3, 18, 9, 1, 2, 10, 19, 8, 48,
729 /* 37 */ 35, 39, 40, 36, 49, 50,
730 /* 43 */ 41, 35, 39, 40, 36, 49, 50, 42, 51, 53, 54, 52, 55, 56,
731 /* 57 */ 34, 37, 41, 35, 39, 40, 36, 49, 50, 42, 51, 53, 54, 52, 55, 56, 38, 61, 57, 59, 60, 58, 63, 64, 62, 65, 67, 68, 66, 69, 70,
732 /* 88 */ 4, 18, 9, 1, 2, 10, 19, 5, 75, 73, 71, 72, 74, 76,
733 /* 102 */ 12, 11, 13, 89,
734 /* 106 */ 44, 43, 3, 18, 9, 1, 2, 10, 19, 8, 48, 45, 15, 5, 75, 73, 71, 72, 74, 76, 90, 109,
735 /* 128 */ 4, 18, 9, 1, 2, 10, 19, 5, 75, 73, 71, 72, 74, 76, 6, 87, 85, 83, 84, 86, 88, 112, 114,
736 /* 151 */ 4, 18, 9, 1, 2, 10, 19, 5, 75, 73, 71, 72, 74, 76, 6, 87, 85, 83, 84, 86, 88, 7, 81, 79, 77, 78, 80, 82, 112, 113, 114, 115, 116,
737 /* 184 */ 14, 3, 18, 9, 1, 2, 10, 19, 8, 15, 5, 75, 73, 71, 72, 74, 76, 90, 117,
738 /* 203 */ 14, 3, 18, 9, 1, 2, 10, 19, 8, 15, 5, 75, 73, 71, 72, 74, 76, 90, 16, 6, 87, 85, 83, 84, 86, 88, 92, 114, 117, 119, 120, 122,
739 /* 235 */ 14, 3, 18, 9, 1, 2, 10, 19, 8, 15, 5, 75, 73, 71, 72, 74, 76, 90, 16, 6, 87, 85, 83, 84, 86, 88, 92, 17, 7, 81, 79, 77, 78, 80, 82, 91, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124,
740 /* 282 */ 26, 20, 21, 27, 105, 106, 28, 103, 104, 29, 101, 102, 30, 99, 100, 31, 97, 98, 32, 95, 96, 33, 93, 94, 125, 126, 127, 128, 129, 130, 131, 132,
741 /* 314 */ 23, 20, 21, 25, 107, 108, 133,
742 /* 321 */ 44, 43, 3, 18, 9, 1, 2, 10, 19, 8, 48, 45, 15, 5, 75, 73, 71, 72, 74, 76, 90, 109, 117, 134,
743 /* 345 */ 44, 43, 3, 18, 9, 1, 2, 10, 19, 8, 48, 45, 15, 5, 75, 73, 71, 72, 74, 76, 90, 109, 46, 16, 6, 87, 85, 83, 84, 86, 88, 92, 111, 114, 117, 119, 122, 134, 136, 137, 139,
744 /* 386 */ 44, 43, 3, 18, 9, 1, 2, 10, 19, 8, 48, 45, 15, 5, 75, 73, 71, 72, 74, 76, 90, 109, 46, 16, 6, 87, 85, 83, 84, 86, 88, 92, 111, 47, 17, 7, 81, 79, 77, 78, 80, 82, 91, 110, 114, 115, 116, 117, 118, 119, 122, 123, 124, 134, 135, 136, 137, 138, 139, 140, 141,
745 /* 447 */ 44, 43, 3, 18, 9, 1, 2, 10, 19, 8, 48, 45, 15, 5, 75, 73, 71, 72, 74, 76, 90, 109, 46, 16, 6, 87, 85, 83, 84, 86, 88, 92, 111, 47, 17, 7, 81, 79, 77, 78, 80, 82, 91, 110, 142, 143,
746};
747
748
749#ifdef __GNUC__
750#pragma GCC diagnostic push
751#pragma GCC diagnostic ignored "-Woverlength-strings"
752#endif
753extern const char AArch64RegStrings[] = {
754 /* 0 */ "B10\000"
755 /* 4 */ "D7_D8_D9_D10\000"
756 /* 17 */ "H10\000"
757 /* 21 */ "PN10\000"
758 /* 26 */ "P9_P10\000"
759 /* 33 */ "ZAQ10\000"
760 /* 39 */ "Q7_Q8_Q9_Q10\000"
761 /* 52 */ "S10\000"
762 /* 56 */ "W10\000"
763 /* 60 */ "X10\000"
764 /* 64 */ "Z2_Z10\000"
765 /* 71 */ "Z7_Z8_Z9_Z10\000"
766 /* 84 */ "B20\000"
767 /* 88 */ "D17_D18_D19_D20\000"
768 /* 104 */ "H20\000"
769 /* 108 */ "Q17_Q18_Q19_Q20\000"
770 /* 124 */ "S20\000"
771 /* 128 */ "W20\000"
772 /* 132 */ "X20\000"
773 /* 136 */ "Z17_Z18_Z19_Z20\000"
774 /* 152 */ "B30\000"
775 /* 156 */ "D27_D28_D29_D30\000"
776 /* 172 */ "H30\000"
777 /* 176 */ "Q27_Q28_Q29_Q30\000"
778 /* 192 */ "S30\000"
779 /* 196 */ "W30\000"
780 /* 200 */ "Z22_Z30\000"
781 /* 208 */ "Z18_Z22_Z26_Z30\000"
782 /* 224 */ "Z27_Z28_Z29_Z30\000"
783 /* 240 */ "ZAB0\000"
784 /* 245 */ "ZAD0\000"
785 /* 250 */ "D29_D30_D31_D0\000"
786 /* 265 */ "ZAH0\000"
787 /* 270 */ "PN0\000"
788 /* 274 */ "P15_P0\000"
789 /* 281 */ "ZAQ0\000"
790 /* 286 */ "Q29_Q30_Q31_Q0\000"
791 /* 301 */ "ZAS0\000"
792 /* 306 */ "ZT0\000"
793 /* 310 */ "W0\000"
794 /* 313 */ "X0\000"
795 /* 316 */ "Z29_Z30_Z31_Z0\000"
796 /* 331 */ "B11\000"
797 /* 335 */ "D8_D9_D10_D11\000"
798 /* 349 */ "H11\000"
799 /* 353 */ "PN11\000"
800 /* 358 */ "P10_P11\000"
801 /* 366 */ "ZAQ11\000"
802 /* 372 */ "Q8_Q9_Q10_Q11\000"
803 /* 386 */ "S11\000"
804 /* 390 */ "W10_W11\000"
805 /* 398 */ "X4_X5_X6_X7_X8_X9_X10_X11\000"
806 /* 424 */ "Z8_Z9_Z10_Z11\000"
807 /* 438 */ "Z3_Z11\000"
808 /* 445 */ "B21\000"
809 /* 449 */ "D18_D19_D20_D21\000"
810 /* 465 */ "H21\000"
811 /* 469 */ "Q18_Q19_Q20_Q21\000"
812 /* 485 */ "S21\000"
813 /* 489 */ "W20_W21\000"
814 /* 497 */ "X14_X15_X16_X17_X18_X19_X20_X21\000"
815 /* 529 */ "Z18_Z19_Z20_Z21\000"
816 /* 545 */ "B31\000"
817 /* 549 */ "D28_D29_D30_D31\000"
818 /* 565 */ "H31\000"
819 /* 569 */ "Q28_Q29_Q30_Q31\000"
820 /* 585 */ "S31\000"
821 /* 589 */ "Z28_Z29_Z30_Z31\000"
822 /* 605 */ "Z23_Z31\000"
823 /* 613 */ "Z19_Z23_Z27_Z31\000"
824 /* 629 */ "B1\000"
825 /* 632 */ "ZAD1\000"
826 /* 637 */ "D30_D31_D0_D1\000"
827 /* 651 */ "ZAH1\000"
828 /* 656 */ "PN1\000"
829 /* 660 */ "P0_P1\000"
830 /* 666 */ "ZAQ1\000"
831 /* 671 */ "Q30_Q31_Q0_Q1\000"
832 /* 685 */ "ZAS1\000"
833 /* 690 */ "W0_W1\000"
834 /* 696 */ "X0_X1\000"
835 /* 702 */ "Z30_Z31_Z0_Z1\000"
836 /* 716 */ "B12\000"
837 /* 720 */ "D9_D10_D11_D12\000"
838 /* 735 */ "H12\000"
839 /* 739 */ "PN12\000"
840 /* 744 */ "P11_P12\000"
841 /* 752 */ "ZAQ12\000"
842 /* 758 */ "Q9_Q10_Q11_Q12\000"
843 /* 773 */ "S12\000"
844 /* 777 */ "W12\000"
845 /* 781 */ "X12\000"
846 /* 785 */ "Z9_Z10_Z11_Z12\000"
847 /* 800 */ "Z4_Z12\000"
848 /* 807 */ "Z0_Z4_Z8_Z12\000"
849 /* 820 */ "B22\000"
850 /* 824 */ "D19_D20_D21_D22\000"
851 /* 840 */ "H22\000"
852 /* 844 */ "Q19_Q20_Q21_Q22\000"
853 /* 860 */ "S22\000"
854 /* 864 */ "W22\000"
855 /* 868 */ "X22\000"
856 /* 872 */ "Z19_Z20_Z21_Z22\000"
857 /* 888 */ "B2\000"
858 /* 891 */ "ZAD2\000"
859 /* 896 */ "D31_D0_D1_D2\000"
860 /* 909 */ "H2\000"
861 /* 912 */ "PN2\000"
862 /* 916 */ "P1_P2\000"
863 /* 922 */ "ZAQ2\000"
864 /* 927 */ "Q31_Q0_Q1_Q2\000"
865 /* 940 */ "ZAS2\000"
866 /* 945 */ "W2\000"
867 /* 948 */ "X2\000"
868 /* 951 */ "Z31_Z0_Z1_Z2\000"
869 /* 964 */ "B13\000"
870 /* 968 */ "D10_D11_D12_D13\000"
871 /* 984 */ "H13\000"
872 /* 988 */ "PN13\000"
873 /* 993 */ "P12_P13\000"
874 /* 1001 */ "ZAQ13\000"
875 /* 1007 */ "Q10_Q11_Q12_Q13\000"
876 /* 1023 */ "S13\000"
877 /* 1027 */ "W12_W13\000"
878 /* 1035 */ "X6_X7_X8_X9_X10_X11_X12_X13\000"
879 /* 1063 */ "Z10_Z11_Z12_Z13\000"
880 /* 1079 */ "Z5_Z13\000"
881 /* 1086 */ "Z1_Z5_Z9_Z13\000"
882 /* 1099 */ "B23\000"
883 /* 1103 */ "D20_D21_D22_D23\000"
884 /* 1119 */ "H23\000"
885 /* 1123 */ "Q20_Q21_Q22_Q23\000"
886 /* 1139 */ "S23\000"
887 /* 1143 */ "W22_W23\000"
888 /* 1151 */ "X16_X17_X18_X19_X20_X21_X22_X23\000"
889 /* 1183 */ "Z20_Z21_Z22_Z23\000"
890 /* 1199 */ "B3\000"
891 /* 1202 */ "ZAD3\000"
892 /* 1207 */ "D0_D1_D2_D3\000"
893 /* 1219 */ "H3\000"
894 /* 1222 */ "PN3\000"
895 /* 1226 */ "P2_P3\000"
896 /* 1232 */ "ZAQ3\000"
897 /* 1237 */ "Q0_Q1_Q2_Q3\000"
898 /* 1249 */ "ZAS3\000"
899 /* 1254 */ "W2_W3\000"
900 /* 1260 */ "X2_X3\000"
901 /* 1266 */ "Z0_Z1_Z2_Z3\000"
902 /* 1278 */ "B14\000"
903 /* 1282 */ "D11_D12_D13_D14\000"
904 /* 1298 */ "H14\000"
905 /* 1302 */ "PN14\000"
906 /* 1307 */ "P13_P14\000"
907 /* 1315 */ "ZAQ14\000"
908 /* 1321 */ "Q11_Q12_Q13_Q14\000"
909 /* 1337 */ "S14\000"
910 /* 1341 */ "W14\000"
911 /* 1345 */ "X14\000"
912 /* 1349 */ "Z2_Z6_Z10_Z14\000"
913 /* 1363 */ "Z11_Z12_Z13_Z14\000"
914 /* 1379 */ "Z6_Z14\000"
915 /* 1386 */ "B24\000"
916 /* 1390 */ "D21_D22_D23_D24\000"
917 /* 1406 */ "H24\000"
918 /* 1410 */ "Q21_Q22_Q23_Q24\000"
919 /* 1426 */ "S24\000"
920 /* 1430 */ "W24\000"
921 /* 1434 */ "X24\000"
922 /* 1438 */ "Z21_Z22_Z23_Z24\000"
923 /* 1454 */ "Z16_Z24\000"
924 /* 1462 */ "B4\000"
925 /* 1465 */ "ZAD4\000"
926 /* 1470 */ "D1_D2_D3_D4\000"
927 /* 1482 */ "H4\000"
928 /* 1485 */ "PN4\000"
929 /* 1489 */ "P3_P4\000"
930 /* 1495 */ "ZAQ4\000"
931 /* 1500 */ "Q1_Q2_Q3_Q4\000"
932 /* 1512 */ "S4\000"
933 /* 1515 */ "W4\000"
934 /* 1518 */ "X4\000"
935 /* 1521 */ "Z1_Z2_Z3_Z4\000"
936 /* 1533 */ "B15\000"
937 /* 1537 */ "D12_D13_D14_D15\000"
938 /* 1553 */ "H15\000"
939 /* 1557 */ "PN15\000"
940 /* 1562 */ "P14_P15\000"
941 /* 1570 */ "ZAQ15\000"
942 /* 1576 */ "Q12_Q13_Q14_Q15\000"
943 /* 1592 */ "S15\000"
944 /* 1596 */ "W14_W15\000"
945 /* 1604 */ "X8_X9_X10_X11_X12_X13_X14_X15\000"
946 /* 1634 */ "Z3_Z7_Z11_Z15\000"
947 /* 1648 */ "Z12_Z13_Z14_Z15\000"
948 /* 1664 */ "Z7_Z15\000"
949 /* 1671 */ "B25\000"
950 /* 1675 */ "D22_D23_D24_D25\000"
951 /* 1691 */ "H25\000"
952 /* 1695 */ "Q22_Q23_Q24_Q25\000"
953 /* 1711 */ "S25\000"
954 /* 1715 */ "W24_W25\000"
955 /* 1723 */ "X18_X19_X20_X21_X22_X23_X24_X25\000"
956 /* 1755 */ "Z22_Z23_Z24_Z25\000"
957 /* 1771 */ "Z17_Z25\000"
958 /* 1779 */ "B5\000"
959 /* 1782 */ "ZAD5\000"
960 /* 1787 */ "D2_D3_D4_D5\000"
961 /* 1799 */ "H5\000"
962 /* 1802 */ "PN5\000"
963 /* 1806 */ "P4_P5\000"
964 /* 1812 */ "ZAQ5\000"
965 /* 1817 */ "Q2_Q3_Q4_Q5\000"
966 /* 1829 */ "S5\000"
967 /* 1832 */ "W4_W5\000"
968 /* 1838 */ "X4_X5\000"
969 /* 1844 */ "Z2_Z3_Z4_Z5\000"
970 /* 1856 */ "B16\000"
971 /* 1860 */ "D13_D14_D15_D16\000"
972 /* 1876 */ "H16\000"
973 /* 1880 */ "Q13_Q14_Q15_Q16\000"
974 /* 1896 */ "S16\000"
975 /* 1900 */ "W16\000"
976 /* 1904 */ "X16\000"
977 /* 1908 */ "Z13_Z14_Z15_Z16\000"
978 /* 1924 */ "B26\000"
979 /* 1928 */ "D23_D24_D25_D26\000"
980 /* 1944 */ "H26\000"
981 /* 1948 */ "Q23_Q24_Q25_Q26\000"
982 /* 1964 */ "S26\000"
983 /* 1968 */ "W26\000"
984 /* 1972 */ "X26\000"
985 /* 1976 */ "Z23_Z24_Z25_Z26\000"
986 /* 1992 */ "Z18_Z26\000"
987 /* 2000 */ "B6\000"
988 /* 2003 */ "ZAD6\000"
989 /* 2008 */ "D3_D4_D5_D6\000"
990 /* 2020 */ "H6\000"
991 /* 2023 */ "PN6\000"
992 /* 2027 */ "P5_P6\000"
993 /* 2033 */ "ZAQ6\000"
994 /* 2038 */ "Q3_Q4_Q5_Q6\000"
995 /* 2050 */ "S6\000"
996 /* 2053 */ "W6\000"
997 /* 2056 */ "X6\000"
998 /* 2059 */ "Z3_Z4_Z5_Z6\000"
999 /* 2071 */ "B17\000"
1000 /* 2075 */ "D14_D15_D16_D17\000"
1001 /* 2091 */ "H17\000"
1002 /* 2095 */ "Q14_Q15_Q16_Q17\000"
1003 /* 2111 */ "S17\000"
1004 /* 2115 */ "W16_W17\000"
1005 /* 2123 */ "X10_X11_X12_X13_X14_X15_X16_X17\000"
1006 /* 2155 */ "Z14_Z15_Z16_Z17\000"
1007 /* 2171 */ "B27\000"
1008 /* 2175 */ "D24_D25_D26_D27\000"
1009 /* 2191 */ "H27\000"
1010 /* 2195 */ "Q24_Q25_Q26_Q27\000"
1011 /* 2211 */ "S27\000"
1012 /* 2215 */ "W26_W27\000"
1013 /* 2223 */ "X20_X21_X22_X23_X24_X25_X26_X27\000"
1014 /* 2255 */ "Z24_Z25_Z26_Z27\000"
1015 /* 2271 */ "Z19_Z27\000"
1016 /* 2279 */ "B7\000"
1017 /* 2282 */ "ZAD7\000"
1018 /* 2287 */ "D4_D5_D6_D7\000"
1019 /* 2299 */ "H7\000"
1020 /* 2302 */ "PN7\000"
1021 /* 2306 */ "P6_P7\000"
1022 /* 2312 */ "ZAQ7\000"
1023 /* 2317 */ "Q4_Q5_Q6_Q7\000"
1024 /* 2329 */ "S7\000"
1025 /* 2332 */ "W6_W7\000"
1026 /* 2338 */ "X0_X1_X2_X3_X4_X5_X6_X7\000"
1027 /* 2362 */ "Z4_Z5_Z6_Z7\000"
1028 /* 2374 */ "B18\000"
1029 /* 2378 */ "D15_D16_D17_D18\000"
1030 /* 2394 */ "H18\000"
1031 /* 2398 */ "Q15_Q16_Q17_Q18\000"
1032 /* 2414 */ "S18\000"
1033 /* 2418 */ "W18\000"
1034 /* 2422 */ "X18\000"
1035 /* 2426 */ "Z15_Z16_Z17_Z18\000"
1036 /* 2442 */ "B28\000"
1037 /* 2446 */ "D25_D26_D27_D28\000"
1038 /* 2462 */ "H28\000"
1039 /* 2466 */ "Q25_Q26_Q27_Q28\000"
1040 /* 2482 */ "S28\000"
1041 /* 2486 */ "W28\000"
1042 /* 2490 */ "X28\000"
1043 /* 2494 */ "Z20_Z28\000"
1044 /* 2502 */ "Z16_Z20_Z24_Z28\000"
1045 /* 2518 */ "Z25_Z26_Z27_Z28\000"
1046 /* 2534 */ "B8\000"
1047 /* 2537 */ "D5_D6_D7_D8\000"
1048 /* 2549 */ "H8\000"
1049 /* 2552 */ "PN8\000"
1050 /* 2556 */ "P7_P8\000"
1051 /* 2562 */ "ZAQ8\000"
1052 /* 2567 */ "Q5_Q6_Q7_Q8\000"
1053 /* 2579 */ "S8\000"
1054 /* 2582 */ "W8\000"
1055 /* 2585 */ "X8\000"
1056 /* 2588 */ "Z0_Z8\000"
1057 /* 2594 */ "Z5_Z6_Z7_Z8\000"
1058 /* 2606 */ "B19\000"
1059 /* 2610 */ "D16_D17_D18_D19\000"
1060 /* 2626 */ "H19\000"
1061 /* 2630 */ "Q16_Q17_Q18_Q19\000"
1062 /* 2646 */ "S19\000"
1063 /* 2650 */ "W18_W19\000"
1064 /* 2658 */ "X12_X13_X14_X15_X16_X17_X18_X19\000"
1065 /* 2690 */ "Z16_Z17_Z18_Z19\000"
1066 /* 2706 */ "B29\000"
1067 /* 2710 */ "D26_D27_D28_D29\000"
1068 /* 2726 */ "H29\000"
1069 /* 2730 */ "Q26_Q27_Q28_Q29\000"
1070 /* 2746 */ "S29\000"
1071 /* 2750 */ "W28_W29\000"
1072 /* 2758 */ "Z21_Z29\000"
1073 /* 2766 */ "Z17_Z21_Z25_Z29\000"
1074 /* 2782 */ "Z26_Z27_Z28_Z29\000"
1075 /* 2798 */ "B9\000"
1076 /* 2801 */ "D6_D7_D8_D9\000"
1077 /* 2813 */ "H9\000"
1078 /* 2816 */ "PN9\000"
1079 /* 2820 */ "P8_P9\000"
1080 /* 2826 */ "ZAQ9\000"
1081 /* 2831 */ "Q6_Q7_Q8_Q9\000"
1082 /* 2843 */ "S9\000"
1083 /* 2846 */ "W8_W9\000"
1084 /* 2852 */ "X2_X3_X4_X5_X6_X7_X8_X9\000"
1085 /* 2876 */ "Z1_Z9\000"
1086 /* 2882 */ "Z6_Z7_Z8_Z9\000"
1087 /* 2894 */ "ZA\000"
1088 /* 2897 */ "VG\000"
1089 /* 2900 */ "B10_HI\000"
1090 /* 2907 */ "D10_HI\000"
1091 /* 2914 */ "H10_HI\000"
1092 /* 2921 */ "Q10_HI\000"
1093 /* 2928 */ "S10_HI\000"
1094 /* 2935 */ "W10_HI\000"
1095 /* 2942 */ "B20_HI\000"
1096 /* 2949 */ "D20_HI\000"
1097 /* 2956 */ "H20_HI\000"
1098 /* 2963 */ "Q20_HI\000"
1099 /* 2970 */ "S20_HI\000"
1100 /* 2977 */ "W20_HI\000"
1101 /* 2984 */ "B30_HI\000"
1102 /* 2991 */ "D30_HI\000"
1103 /* 2998 */ "H30_HI\000"
1104 /* 3005 */ "Q30_HI\000"
1105 /* 3012 */ "S30_HI\000"
1106 /* 3019 */ "W30_HI\000"
1107 /* 3026 */ "B0_HI\000"
1108 /* 3032 */ "D0_HI\000"
1109 /* 3038 */ "H0_HI\000"
1110 /* 3044 */ "Q0_HI\000"
1111 /* 3050 */ "S0_HI\000"
1112 /* 3056 */ "W0_HI\000"
1113 /* 3062 */ "B11_HI\000"
1114 /* 3069 */ "D11_HI\000"
1115 /* 3076 */ "H11_HI\000"
1116 /* 3083 */ "Q11_HI\000"
1117 /* 3090 */ "S11_HI\000"
1118 /* 3097 */ "W11_HI\000"
1119 /* 3104 */ "B21_HI\000"
1120 /* 3111 */ "D21_HI\000"
1121 /* 3118 */ "H21_HI\000"
1122 /* 3125 */ "Q21_HI\000"
1123 /* 3132 */ "S21_HI\000"
1124 /* 3139 */ "W21_HI\000"
1125 /* 3146 */ "B31_HI\000"
1126 /* 3153 */ "D31_HI\000"
1127 /* 3160 */ "H31_HI\000"
1128 /* 3167 */ "Q31_HI\000"
1129 /* 3174 */ "S31_HI\000"
1130 /* 3181 */ "B1_HI\000"
1131 /* 3187 */ "D1_HI\000"
1132 /* 3193 */ "H1_HI\000"
1133 /* 3199 */ "Q1_HI\000"
1134 /* 3205 */ "S1_HI\000"
1135 /* 3211 */ "W1_HI\000"
1136 /* 3217 */ "B12_HI\000"
1137 /* 3224 */ "D12_HI\000"
1138 /* 3231 */ "H12_HI\000"
1139 /* 3238 */ "Q12_HI\000"
1140 /* 3245 */ "S12_HI\000"
1141 /* 3252 */ "W12_HI\000"
1142 /* 3259 */ "B22_HI\000"
1143 /* 3266 */ "D22_HI\000"
1144 /* 3273 */ "H22_HI\000"
1145 /* 3280 */ "Q22_HI\000"
1146 /* 3287 */ "S22_HI\000"
1147 /* 3294 */ "W22_HI\000"
1148 /* 3301 */ "B2_HI\000"
1149 /* 3307 */ "D2_HI\000"
1150 /* 3313 */ "H2_HI\000"
1151 /* 3319 */ "Q2_HI\000"
1152 /* 3325 */ "S2_HI\000"
1153 /* 3331 */ "W2_HI\000"
1154 /* 3337 */ "B13_HI\000"
1155 /* 3344 */ "D13_HI\000"
1156 /* 3351 */ "H13_HI\000"
1157 /* 3358 */ "Q13_HI\000"
1158 /* 3365 */ "S13_HI\000"
1159 /* 3372 */ "W13_HI\000"
1160 /* 3379 */ "B23_HI\000"
1161 /* 3386 */ "D23_HI\000"
1162 /* 3393 */ "H23_HI\000"
1163 /* 3400 */ "Q23_HI\000"
1164 /* 3407 */ "S23_HI\000"
1165 /* 3414 */ "W23_HI\000"
1166 /* 3421 */ "B3_HI\000"
1167 /* 3427 */ "D3_HI\000"
1168 /* 3433 */ "H3_HI\000"
1169 /* 3439 */ "Q3_HI\000"
1170 /* 3445 */ "S3_HI\000"
1171 /* 3451 */ "W3_HI\000"
1172 /* 3457 */ "B14_HI\000"
1173 /* 3464 */ "D14_HI\000"
1174 /* 3471 */ "H14_HI\000"
1175 /* 3478 */ "Q14_HI\000"
1176 /* 3485 */ "S14_HI\000"
1177 /* 3492 */ "W14_HI\000"
1178 /* 3499 */ "B24_HI\000"
1179 /* 3506 */ "D24_HI\000"
1180 /* 3513 */ "H24_HI\000"
1181 /* 3520 */ "Q24_HI\000"
1182 /* 3527 */ "S24_HI\000"
1183 /* 3534 */ "W24_HI\000"
1184 /* 3541 */ "B4_HI\000"
1185 /* 3547 */ "D4_HI\000"
1186 /* 3553 */ "H4_HI\000"
1187 /* 3559 */ "Q4_HI\000"
1188 /* 3565 */ "S4_HI\000"
1189 /* 3571 */ "W4_HI\000"
1190 /* 3577 */ "B15_HI\000"
1191 /* 3584 */ "D15_HI\000"
1192 /* 3591 */ "H15_HI\000"
1193 /* 3598 */ "Q15_HI\000"
1194 /* 3605 */ "S15_HI\000"
1195 /* 3612 */ "W15_HI\000"
1196 /* 3619 */ "B25_HI\000"
1197 /* 3626 */ "D25_HI\000"
1198 /* 3633 */ "H25_HI\000"
1199 /* 3640 */ "Q25_HI\000"
1200 /* 3647 */ "S25_HI\000"
1201 /* 3654 */ "W25_HI\000"
1202 /* 3661 */ "B5_HI\000"
1203 /* 3667 */ "D5_HI\000"
1204 /* 3673 */ "H5_HI\000"
1205 /* 3679 */ "Q5_HI\000"
1206 /* 3685 */ "S5_HI\000"
1207 /* 3691 */ "W5_HI\000"
1208 /* 3697 */ "B16_HI\000"
1209 /* 3704 */ "D16_HI\000"
1210 /* 3711 */ "H16_HI\000"
1211 /* 3718 */ "Q16_HI\000"
1212 /* 3725 */ "S16_HI\000"
1213 /* 3732 */ "W16_HI\000"
1214 /* 3739 */ "B26_HI\000"
1215 /* 3746 */ "D26_HI\000"
1216 /* 3753 */ "H26_HI\000"
1217 /* 3760 */ "Q26_HI\000"
1218 /* 3767 */ "S26_HI\000"
1219 /* 3774 */ "W26_HI\000"
1220 /* 3781 */ "B6_HI\000"
1221 /* 3787 */ "D6_HI\000"
1222 /* 3793 */ "H6_HI\000"
1223 /* 3799 */ "Q6_HI\000"
1224 /* 3805 */ "S6_HI\000"
1225 /* 3811 */ "W6_HI\000"
1226 /* 3817 */ "B17_HI\000"
1227 /* 3824 */ "D17_HI\000"
1228 /* 3831 */ "H17_HI\000"
1229 /* 3838 */ "Q17_HI\000"
1230 /* 3845 */ "S17_HI\000"
1231 /* 3852 */ "W17_HI\000"
1232 /* 3859 */ "B27_HI\000"
1233 /* 3866 */ "D27_HI\000"
1234 /* 3873 */ "H27_HI\000"
1235 /* 3880 */ "Q27_HI\000"
1236 /* 3887 */ "S27_HI\000"
1237 /* 3894 */ "W27_HI\000"
1238 /* 3901 */ "B7_HI\000"
1239 /* 3907 */ "D7_HI\000"
1240 /* 3913 */ "H7_HI\000"
1241 /* 3919 */ "Q7_HI\000"
1242 /* 3925 */ "S7_HI\000"
1243 /* 3931 */ "W7_HI\000"
1244 /* 3937 */ "B18_HI\000"
1245 /* 3944 */ "D18_HI\000"
1246 /* 3951 */ "H18_HI\000"
1247 /* 3958 */ "Q18_HI\000"
1248 /* 3965 */ "S18_HI\000"
1249 /* 3972 */ "W18_HI\000"
1250 /* 3979 */ "B28_HI\000"
1251 /* 3986 */ "D28_HI\000"
1252 /* 3993 */ "H28_HI\000"
1253 /* 4000 */ "Q28_HI\000"
1254 /* 4007 */ "S28_HI\000"
1255 /* 4014 */ "W28_HI\000"
1256 /* 4021 */ "B8_HI\000"
1257 /* 4027 */ "D8_HI\000"
1258 /* 4033 */ "H8_HI\000"
1259 /* 4039 */ "Q8_HI\000"
1260 /* 4045 */ "S8_HI\000"
1261 /* 4051 */ "W8_HI\000"
1262 /* 4057 */ "B19_HI\000"
1263 /* 4064 */ "D19_HI\000"
1264 /* 4071 */ "H19_HI\000"
1265 /* 4078 */ "Q19_HI\000"
1266 /* 4085 */ "S19_HI\000"
1267 /* 4092 */ "W19_HI\000"
1268 /* 4099 */ "B29_HI\000"
1269 /* 4106 */ "D29_HI\000"
1270 /* 4113 */ "H29_HI\000"
1271 /* 4120 */ "Q29_HI\000"
1272 /* 4127 */ "S29_HI\000"
1273 /* 4134 */ "W29_HI\000"
1274 /* 4141 */ "B9_HI\000"
1275 /* 4147 */ "D9_HI\000"
1276 /* 4153 */ "H9_HI\000"
1277 /* 4159 */ "Q9_HI\000"
1278 /* 4165 */ "S9_HI\000"
1279 /* 4171 */ "W9_HI\000"
1280 /* 4177 */ "WSP_HI\000"
1281 /* 4184 */ "WZR_HI\000"
1282 /* 4191 */ "X22_X23_X24_X25_X26_X27_X28_FP\000"
1283 /* 4222 */ "WSP\000"
1284 /* 4226 */ "FPCR\000"
1285 /* 4231 */ "FFR\000"
1286 /* 4235 */ "LR\000"
1287 /* 4238 */ "FPMR\000"
1288 /* 4243 */ "FPSR\000"
1289 /* 4248 */ "W30_WZR\000"
1290 /* 4256 */ "LR_XZR\000"
1291 /* 4263 */ "NZCV\000"
1292};
1293#ifdef __GNUC__
1294#pragma GCC diagnostic pop
1295#endif
1296
1297extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
1298 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1299 { .Name: 4231, .SubRegs: 5, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 20480, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1300 { .Name: 4219, .SubRegs: 9402, .SuperRegs: 816, .SubRegIndices: 21, .RegUnits: 4997121, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1301 { .Name: 4226, .SubRegs: 5, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 20483, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1302 { .Name: 4238, .SubRegs: 5, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 20484, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1303 { .Name: 4243, .SubRegs: 5, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 20485, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1304 { .Name: 4235, .SubRegs: 9399, .SuperRegs: 9420, .SubRegIndices: 21, .RegUnits: 4997126, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1305 { .Name: 4263, .SubRegs: 5, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 20488, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1306 { .Name: 4223, .SubRegs: 5055, .SuperRegs: 5, .SubRegIndices: 21, .RegUnits: 4997129, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1307 { .Name: 2897, .SubRegs: 5, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 20491, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1308 { .Name: 4222, .SubRegs: 5, .SuperRegs: 821, .SubRegIndices: 2, .RegUnits: 20489, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1309 { .Name: 4177, .SubRegs: 5, .SuperRegs: 819, .SubRegIndices: 2, .RegUnits: 20490, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1310 { .Name: 4252, .SubRegs: 5, .SuperRegs: 8594, .SubRegIndices: 2, .RegUnits: 20492, .RegUnitLaneMasks: 537, .IsConstant: 1, .IsArtificial: 0 },
1311 { .Name: 4184, .SubRegs: 5, .SuperRegs: 9416, .SubRegIndices: 2, .RegUnits: 20493, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1312 { .Name: 4259, .SubRegs: 1331, .SuperRegs: 9417, .SubRegIndices: 21, .RegUnits: 4997132, .RegUnitLaneMasks: 99, .IsConstant: 1, .IsArtificial: 0 },
1313 { .Name: 2894, .SubRegs: 6431, .SuperRegs: 5, .SubRegIndices: 57, .RegUnits: 6123534, .RegUnitLaneMasks: 179, .IsConstant: 0, .IsArtificial: 0 },
1314 { .Name: 242, .SubRegs: 5, .SuperRegs: 7298, .SubRegIndices: 2, .RegUnits: 20510, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1315 { .Name: 629, .SubRegs: 5, .SuperRegs: 7471, .SubRegIndices: 2, .RegUnits: 20511, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1316 { .Name: 888, .SubRegs: 5, .SuperRegs: 7644, .SubRegIndices: 2, .RegUnits: 20512, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1317 { .Name: 1199, .SubRegs: 5, .SuperRegs: 8163, .SubRegIndices: 2, .RegUnits: 20513, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1318 { .Name: 1462, .SubRegs: 5, .SuperRegs: 6738, .SubRegIndices: 2, .RegUnits: 20514, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1319 { .Name: 1779, .SubRegs: 5, .SuperRegs: 6738, .SubRegIndices: 2, .RegUnits: 20515, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1320 { .Name: 2000, .SubRegs: 5, .SuperRegs: 6738, .SubRegIndices: 2, .RegUnits: 20516, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1321 { .Name: 2279, .SubRegs: 5, .SuperRegs: 6738, .SubRegIndices: 2, .RegUnits: 20517, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1322 { .Name: 2534, .SubRegs: 5, .SuperRegs: 7990, .SubRegIndices: 2, .RegUnits: 20518, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1323 { .Name: 2798, .SubRegs: 5, .SuperRegs: 7990, .SubRegIndices: 2, .RegUnits: 20519, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1324 { .Name: 0, .SubRegs: 5, .SuperRegs: 7990, .SubRegIndices: 2, .RegUnits: 20520, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1325 { .Name: 331, .SubRegs: 5, .SuperRegs: 7990, .SubRegIndices: 2, .RegUnits: 20521, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1326 { .Name: 716, .SubRegs: 5, .SuperRegs: 6565, .SubRegIndices: 2, .RegUnits: 20522, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1327 { .Name: 964, .SubRegs: 5, .SuperRegs: 6565, .SubRegIndices: 2, .RegUnits: 20523, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1328 { .Name: 1278, .SubRegs: 5, .SuperRegs: 6565, .SubRegIndices: 2, .RegUnits: 20524, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1329 { .Name: 1533, .SubRegs: 5, .SuperRegs: 6565, .SubRegIndices: 2, .RegUnits: 20525, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1330 { .Name: 1856, .SubRegs: 5, .SuperRegs: 8523, .SubRegIndices: 2, .RegUnits: 20526, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1331 { .Name: 2071, .SubRegs: 5, .SuperRegs: 8523, .SubRegIndices: 2, .RegUnits: 20527, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1332 { .Name: 2374, .SubRegs: 5, .SuperRegs: 8523, .SubRegIndices: 2, .RegUnits: 20528, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1333 { .Name: 2606, .SubRegs: 5, .SuperRegs: 8523, .SubRegIndices: 2, .RegUnits: 20529, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1334 { .Name: 84, .SubRegs: 5, .SuperRegs: 7817, .SubRegIndices: 2, .RegUnits: 20530, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1335 { .Name: 445, .SubRegs: 5, .SuperRegs: 7817, .SubRegIndices: 2, .RegUnits: 20531, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1336 { .Name: 820, .SubRegs: 5, .SuperRegs: 7817, .SubRegIndices: 2, .RegUnits: 20532, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1337 { .Name: 1099, .SubRegs: 5, .SuperRegs: 7817, .SubRegIndices: 2, .RegUnits: 20533, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1338 { .Name: 1386, .SubRegs: 5, .SuperRegs: 8350, .SubRegIndices: 2, .RegUnits: 20534, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1339 { .Name: 1671, .SubRegs: 5, .SuperRegs: 8350, .SubRegIndices: 2, .RegUnits: 20535, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1340 { .Name: 1924, .SubRegs: 5, .SuperRegs: 8350, .SubRegIndices: 2, .RegUnits: 20536, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1341 { .Name: 2171, .SubRegs: 5, .SuperRegs: 8350, .SubRegIndices: 2, .RegUnits: 20537, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1342 { .Name: 2442, .SubRegs: 5, .SuperRegs: 7125, .SubRegIndices: 2, .RegUnits: 20538, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1343 { .Name: 2706, .SubRegs: 5, .SuperRegs: 7125, .SubRegIndices: 2, .RegUnits: 20539, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1344 { .Name: 152, .SubRegs: 5, .SuperRegs: 7125, .SubRegIndices: 2, .RegUnits: 20540, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1345 { .Name: 545, .SubRegs: 5, .SuperRegs: 7125, .SubRegIndices: 2, .RegUnits: 20541, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1346 { .Name: 247, .SubRegs: 8847, .SuperRegs: 7197, .SubRegIndices: 15, .RegUnits: 16388126, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1347 { .Name: 634, .SubRegs: 8847, .SuperRegs: 7370, .SubRegIndices: 15, .RegUnits: 16404511, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1348 { .Name: 893, .SubRegs: 8847, .SuperRegs: 7543, .SubRegIndices: 15, .RegUnits: 16420896, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1349 { .Name: 1204, .SubRegs: 8847, .SuperRegs: 8062, .SubRegIndices: 15, .RegUnits: 16437281, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1350 { .Name: 1467, .SubRegs: 8847, .SuperRegs: 6637, .SubRegIndices: 15, .RegUnits: 16453666, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1351 { .Name: 1784, .SubRegs: 8847, .SuperRegs: 6637, .SubRegIndices: 15, .RegUnits: 16470051, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1352 { .Name: 2005, .SubRegs: 8847, .SuperRegs: 6637, .SubRegIndices: 15, .RegUnits: 16486436, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1353 { .Name: 2284, .SubRegs: 8847, .SuperRegs: 6637, .SubRegIndices: 15, .RegUnits: 16547877, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1354 { .Name: 2546, .SubRegs: 8847, .SuperRegs: 7889, .SubRegIndices: 15, .RegUnits: 16609318, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1355 { .Name: 2810, .SubRegs: 8847, .SuperRegs: 7889, .SubRegIndices: 15, .RegUnits: 16670759, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1356 { .Name: 13, .SubRegs: 8847, .SuperRegs: 7889, .SubRegIndices: 15, .RegUnits: 16732200, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1357 { .Name: 345, .SubRegs: 8847, .SuperRegs: 7889, .SubRegIndices: 15, .RegUnits: 16793641, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1358 { .Name: 731, .SubRegs: 8847, .SuperRegs: 6464, .SubRegIndices: 15, .RegUnits: 16855082, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1359 { .Name: 980, .SubRegs: 8847, .SuperRegs: 6464, .SubRegIndices: 15, .RegUnits: 16916523, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1360 { .Name: 1294, .SubRegs: 8847, .SuperRegs: 6464, .SubRegIndices: 15, .RegUnits: 16977964, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1361 { .Name: 1549, .SubRegs: 8847, .SuperRegs: 6464, .SubRegIndices: 15, .RegUnits: 17039405, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1362 { .Name: 1872, .SubRegs: 8847, .SuperRegs: 8422, .SubRegIndices: 15, .RegUnits: 17100846, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1363 { .Name: 2087, .SubRegs: 8847, .SuperRegs: 8422, .SubRegIndices: 15, .RegUnits: 17162287, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1364 { .Name: 2390, .SubRegs: 8847, .SuperRegs: 8422, .SubRegIndices: 15, .RegUnits: 17223728, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1365 { .Name: 2622, .SubRegs: 8847, .SuperRegs: 8422, .SubRegIndices: 15, .RegUnits: 17285169, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1366 { .Name: 100, .SubRegs: 8847, .SuperRegs: 7716, .SubRegIndices: 15, .RegUnits: 17346610, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1367 { .Name: 461, .SubRegs: 8847, .SuperRegs: 7716, .SubRegIndices: 15, .RegUnits: 17408051, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1368 { .Name: 836, .SubRegs: 8847, .SuperRegs: 7716, .SubRegIndices: 15, .RegUnits: 17469492, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1369 { .Name: 1115, .SubRegs: 8847, .SuperRegs: 7716, .SubRegIndices: 15, .RegUnits: 17530933, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1370 { .Name: 1402, .SubRegs: 8847, .SuperRegs: 8249, .SubRegIndices: 15, .RegUnits: 17592374, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1371 { .Name: 1687, .SubRegs: 8847, .SuperRegs: 8249, .SubRegIndices: 15, .RegUnits: 17653815, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1372 { .Name: 1940, .SubRegs: 8847, .SuperRegs: 8249, .SubRegIndices: 15, .RegUnits: 17715256, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1373 { .Name: 2187, .SubRegs: 8847, .SuperRegs: 8249, .SubRegIndices: 15, .RegUnits: 17842233, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1374 { .Name: 2458, .SubRegs: 8847, .SuperRegs: 7024, .SubRegIndices: 15, .RegUnits: 17903674, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1375 { .Name: 2722, .SubRegs: 8847, .SuperRegs: 7024, .SubRegIndices: 15, .RegUnits: 20226107, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1376 { .Name: 168, .SubRegs: 8847, .SuperRegs: 7024, .SubRegIndices: 15, .RegUnits: 20320316, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1377 { .Name: 561, .SubRegs: 8847, .SuperRegs: 7024, .SubRegIndices: 15, .RegUnits: 20381757, .RegUnitLaneMasks: 57, .IsConstant: 0, .IsArtificial: 0 },
1378 { .Name: 267, .SubRegs: 9405, .SuperRegs: 7264, .SubRegIndices: 0, .RegUnits: 35766302, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1379 { .Name: 653, .SubRegs: 9405, .SuperRegs: 7437, .SubRegIndices: 0, .RegUnits: 35774495, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1380 { .Name: 909, .SubRegs: 9405, .SuperRegs: 7610, .SubRegIndices: 0, .RegUnits: 35782688, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1381 { .Name: 1219, .SubRegs: 9405, .SuperRegs: 8129, .SubRegIndices: 0, .RegUnits: 35790881, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1382 { .Name: 1482, .SubRegs: 9405, .SuperRegs: 6704, .SubRegIndices: 0, .RegUnits: 35799074, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1383 { .Name: 1799, .SubRegs: 9405, .SuperRegs: 6704, .SubRegIndices: 0, .RegUnits: 35807267, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1384 { .Name: 2020, .SubRegs: 9405, .SuperRegs: 6704, .SubRegIndices: 0, .RegUnits: 35815460, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1385 { .Name: 2299, .SubRegs: 9405, .SuperRegs: 6704, .SubRegIndices: 0, .RegUnits: 35823653, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1386 { .Name: 2549, .SubRegs: 9405, .SuperRegs: 7956, .SubRegIndices: 0, .RegUnits: 35844134, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1387 { .Name: 2813, .SubRegs: 9405, .SuperRegs: 7956, .SubRegIndices: 0, .RegUnits: 35864615, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1388 { .Name: 17, .SubRegs: 9405, .SuperRegs: 7956, .SubRegIndices: 0, .RegUnits: 35885096, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1389 { .Name: 349, .SubRegs: 9405, .SuperRegs: 7956, .SubRegIndices: 0, .RegUnits: 35905577, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1390 { .Name: 735, .SubRegs: 9405, .SuperRegs: 6531, .SubRegIndices: 0, .RegUnits: 35926058, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1391 { .Name: 984, .SubRegs: 9405, .SuperRegs: 6531, .SubRegIndices: 0, .RegUnits: 35946539, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1392 { .Name: 1298, .SubRegs: 9405, .SuperRegs: 6531, .SubRegIndices: 0, .RegUnits: 35967020, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1393 { .Name: 1553, .SubRegs: 9405, .SuperRegs: 6531, .SubRegIndices: 0, .RegUnits: 35987501, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1394 { .Name: 1876, .SubRegs: 9405, .SuperRegs: 8489, .SubRegIndices: 0, .RegUnits: 36081710, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1395 { .Name: 2091, .SubRegs: 9405, .SuperRegs: 8489, .SubRegIndices: 0, .RegUnits: 36360239, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1396 { .Name: 2394, .SubRegs: 9405, .SuperRegs: 8489, .SubRegIndices: 0, .RegUnits: 36380720, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1397 { .Name: 2626, .SubRegs: 9405, .SuperRegs: 8489, .SubRegIndices: 0, .RegUnits: 36401201, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1398 { .Name: 104, .SubRegs: 9405, .SuperRegs: 7783, .SubRegIndices: 0, .RegUnits: 36421682, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1399 { .Name: 465, .SubRegs: 9405, .SuperRegs: 7783, .SubRegIndices: 0, .RegUnits: 36442163, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1400 { .Name: 840, .SubRegs: 9405, .SuperRegs: 7783, .SubRegIndices: 0, .RegUnits: 36462644, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1401 { .Name: 1119, .SubRegs: 9405, .SuperRegs: 7783, .SubRegIndices: 0, .RegUnits: 36483125, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1402 { .Name: 1406, .SubRegs: 9405, .SuperRegs: 8316, .SubRegIndices: 0, .RegUnits: 36503606, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1403 { .Name: 1691, .SubRegs: 9405, .SuperRegs: 8316, .SubRegIndices: 0, .RegUnits: 36524087, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1404 { .Name: 1944, .SubRegs: 9405, .SuperRegs: 8316, .SubRegIndices: 0, .RegUnits: 36544568, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1405 { .Name: 2191, .SubRegs: 9405, .SuperRegs: 8316, .SubRegIndices: 0, .RegUnits: 36565049, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1406 { .Name: 2462, .SubRegs: 9405, .SuperRegs: 7091, .SubRegIndices: 0, .RegUnits: 36585530, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1407 { .Name: 2726, .SubRegs: 9405, .SuperRegs: 7091, .SubRegIndices: 0, .RegUnits: 36606011, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1408 { .Name: 172, .SubRegs: 9405, .SuperRegs: 7091, .SubRegIndices: 0, .RegUnits: 37412924, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1409 { .Name: 565, .SubRegs: 9405, .SuperRegs: 7091, .SubRegIndices: 0, .RegUnits: 37433405, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
1410 { .Name: 278, .SubRegs: 8241, .SuperRegs: 8235, .SubRegIndices: 14, .RegUnits: 20638, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1411 { .Name: 663, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20639, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1412 { .Name: 919, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20640, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1413 { .Name: 1229, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20641, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1414 { .Name: 1492, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20642, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1415 { .Name: 1809, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20643, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1416 { .Name: 2030, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20644, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1417 { .Name: 2309, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20645, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1418 { .Name: 2559, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20646, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1419 { .Name: 2823, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20647, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1420 { .Name: 29, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20648, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1421 { .Name: 362, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20649, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1422 { .Name: 748, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20650, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1423 { .Name: 997, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20651, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1424 { .Name: 1311, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20652, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1425 { .Name: 1566, .SubRegs: 8241, .SuperRegs: 6140, .SubRegIndices: 14, .RegUnits: 20653, .RegUnitLaneMasks: 56, .IsConstant: 0, .IsArtificial: 0 },
1426 { .Name: 270, .SubRegs: 5, .SuperRegs: 8234, .SubRegIndices: 2, .RegUnits: 20638, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1427 { .Name: 656, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20639, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1428 { .Name: 912, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20640, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1429 { .Name: 1222, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20641, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1430 { .Name: 1485, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20642, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1431 { .Name: 1802, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20643, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1432 { .Name: 2023, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20644, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1433 { .Name: 2302, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20645, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1434 { .Name: 2552, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20646, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1435 { .Name: 2816, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20647, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1436 { .Name: 21, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20648, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1437 { .Name: 353, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20649, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1438 { .Name: 739, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20650, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1439 { .Name: 988, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20651, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1440 { .Name: 1302, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20652, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1441 { .Name: 1557, .SubRegs: 5, .SuperRegs: 6139, .SubRegIndices: 2, .RegUnits: 20653, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1442 { .Name: 283, .SubRegs: 99, .SuperRegs: 7334, .SubRegIndices: 2, .RegUnits: 37584926, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1443 { .Name: 668, .SubRegs: 99, .SuperRegs: 7507, .SubRegIndices: 2, .RegUnits: 37564447, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1444 { .Name: 924, .SubRegs: 99, .SuperRegs: 7680, .SubRegIndices: 2, .RegUnits: 37543968, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1445 { .Name: 1234, .SubRegs: 99, .SuperRegs: 8199, .SubRegIndices: 2, .RegUnits: 37523489, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1446 { .Name: 1497, .SubRegs: 99, .SuperRegs: 6774, .SubRegIndices: 2, .RegUnits: 37503010, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1447 { .Name: 1814, .SubRegs: 99, .SuperRegs: 6774, .SubRegIndices: 2, .RegUnits: 37482531, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1448 { .Name: 2035, .SubRegs: 99, .SuperRegs: 6774, .SubRegIndices: 2, .RegUnits: 37462052, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1449 { .Name: 2314, .SubRegs: 99, .SuperRegs: 6774, .SubRegIndices: 2, .RegUnits: 37441573, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1450 { .Name: 2564, .SubRegs: 99, .SuperRegs: 8026, .SubRegIndices: 2, .RegUnits: 37421094, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1451 { .Name: 2828, .SubRegs: 99, .SuperRegs: 8026, .SubRegIndices: 2, .RegUnits: 37400615, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1452 { .Name: 35, .SubRegs: 99, .SuperRegs: 8026, .SubRegIndices: 2, .RegUnits: 36593704, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1453 { .Name: 368, .SubRegs: 99, .SuperRegs: 8026, .SubRegIndices: 2, .RegUnits: 36573225, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1454 { .Name: 754, .SubRegs: 99, .SuperRegs: 6601, .SubRegIndices: 2, .RegUnits: 36552746, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1455 { .Name: 1003, .SubRegs: 99, .SuperRegs: 6601, .SubRegIndices: 2, .RegUnits: 36532267, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1456 { .Name: 1317, .SubRegs: 99, .SuperRegs: 6601, .SubRegIndices: 2, .RegUnits: 36511788, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1457 { .Name: 1572, .SubRegs: 99, .SuperRegs: 6601, .SubRegIndices: 2, .RegUnits: 36491309, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1458 { .Name: 1892, .SubRegs: 99, .SuperRegs: 8559, .SubRegIndices: 2, .RegUnits: 36470830, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1459 { .Name: 2107, .SubRegs: 99, .SuperRegs: 8559, .SubRegIndices: 2, .RegUnits: 36450351, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1460 { .Name: 2410, .SubRegs: 99, .SuperRegs: 8559, .SubRegIndices: 2, .RegUnits: 36429872, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1461 { .Name: 2642, .SubRegs: 99, .SuperRegs: 8559, .SubRegIndices: 2, .RegUnits: 36409393, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1462 { .Name: 120, .SubRegs: 99, .SuperRegs: 7853, .SubRegIndices: 2, .RegUnits: 36388914, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1463 { .Name: 481, .SubRegs: 99, .SuperRegs: 7853, .SubRegIndices: 2, .RegUnits: 36368435, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1464 { .Name: 856, .SubRegs: 99, .SuperRegs: 7853, .SubRegIndices: 2, .RegUnits: 36347956, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1465 { .Name: 1135, .SubRegs: 99, .SuperRegs: 7853, .SubRegIndices: 2, .RegUnits: 36184117, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1466 { .Name: 1422, .SubRegs: 99, .SuperRegs: 8386, .SubRegIndices: 2, .RegUnits: 35975222, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1467 { .Name: 1707, .SubRegs: 99, .SuperRegs: 8386, .SubRegIndices: 2, .RegUnits: 35954743, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1468 { .Name: 1960, .SubRegs: 99, .SuperRegs: 8386, .SubRegIndices: 2, .RegUnits: 35934264, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1469 { .Name: 2207, .SubRegs: 99, .SuperRegs: 8386, .SubRegIndices: 2, .RegUnits: 35913785, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1470 { .Name: 2478, .SubRegs: 99, .SuperRegs: 7161, .SubRegIndices: 2, .RegUnits: 35893306, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1471 { .Name: 2742, .SubRegs: 99, .SuperRegs: 7161, .SubRegIndices: 2, .RegUnits: 35872827, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1472 { .Name: 188, .SubRegs: 99, .SuperRegs: 7161, .SubRegIndices: 2, .RegUnits: 35852348, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1473 { .Name: 581, .SubRegs: 99, .SuperRegs: 7161, .SubRegIndices: 2, .RegUnits: 35831869, .RegUnitLaneMasks: 2, .IsConstant: 0, .IsArtificial: 0 },
1474 { .Name: 303, .SubRegs: 8869, .SuperRegs: 7230, .SubRegIndices: 10, .RegUnits: 21172254, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1475 { .Name: 687, .SubRegs: 8869, .SuperRegs: 7403, .SubRegIndices: 10, .RegUnits: 21184543, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1476 { .Name: 942, .SubRegs: 8869, .SuperRegs: 7576, .SubRegIndices: 10, .RegUnits: 21196832, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1477 { .Name: 1251, .SubRegs: 8869, .SuperRegs: 8095, .SubRegIndices: 10, .RegUnits: 21209121, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1478 { .Name: 1512, .SubRegs: 8869, .SuperRegs: 6670, .SubRegIndices: 10, .RegUnits: 21221410, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1479 { .Name: 1829, .SubRegs: 8869, .SuperRegs: 6670, .SubRegIndices: 10, .RegUnits: 21233699, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1480 { .Name: 2050, .SubRegs: 8869, .SuperRegs: 6670, .SubRegIndices: 10, .RegUnits: 21245988, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1481 { .Name: 2329, .SubRegs: 8869, .SuperRegs: 6670, .SubRegIndices: 10, .RegUnits: 21258277, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1482 { .Name: 2579, .SubRegs: 8869, .SuperRegs: 7922, .SubRegIndices: 10, .RegUnits: 21434406, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1483 { .Name: 2843, .SubRegs: 8869, .SuperRegs: 7922, .SubRegIndices: 10, .RegUnits: 21622823, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1484 { .Name: 52, .SubRegs: 8869, .SuperRegs: 7922, .SubRegIndices: 10, .RegUnits: 21676072, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1485 { .Name: 386, .SubRegs: 8869, .SuperRegs: 7922, .SubRegIndices: 10, .RegUnits: 21729321, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1486 { .Name: 773, .SubRegs: 8869, .SuperRegs: 6497, .SubRegIndices: 10, .RegUnits: 21782570, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1487 { .Name: 1023, .SubRegs: 8869, .SuperRegs: 6497, .SubRegIndices: 10, .RegUnits: 21835819, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1488 { .Name: 1337, .SubRegs: 8869, .SuperRegs: 6497, .SubRegIndices: 10, .RegUnits: 21889068, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1489 { .Name: 1592, .SubRegs: 8869, .SuperRegs: 6497, .SubRegIndices: 10, .RegUnits: 22040621, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1490 { .Name: 1896, .SubRegs: 8869, .SuperRegs: 8455, .SubRegIndices: 10, .RegUnits: 22093870, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1491 { .Name: 2111, .SubRegs: 8869, .SuperRegs: 8455, .SubRegIndices: 10, .RegUnits: 22147119, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1492 { .Name: 2414, .SubRegs: 8869, .SuperRegs: 8455, .SubRegIndices: 10, .RegUnits: 22200368, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1493 { .Name: 2646, .SubRegs: 8869, .SuperRegs: 8455, .SubRegIndices: 10, .RegUnits: 22253617, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1494 { .Name: 124, .SubRegs: 8869, .SuperRegs: 7749, .SubRegIndices: 10, .RegUnits: 22306866, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1495 { .Name: 485, .SubRegs: 8869, .SuperRegs: 7749, .SubRegIndices: 10, .RegUnits: 22360115, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1496 { .Name: 860, .SubRegs: 8869, .SuperRegs: 7749, .SubRegIndices: 10, .RegUnits: 22573108, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1497 { .Name: 1139, .SubRegs: 8869, .SuperRegs: 7749, .SubRegIndices: 10, .RegUnits: 22798389, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1498 { .Name: 1426, .SubRegs: 8869, .SuperRegs: 8282, .SubRegIndices: 10, .RegUnits: 22851638, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1499 { .Name: 1711, .SubRegs: 8869, .SuperRegs: 8282, .SubRegIndices: 10, .RegUnits: 22904887, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1500 { .Name: 1964, .SubRegs: 8869, .SuperRegs: 8282, .SubRegIndices: 10, .RegUnits: 22958136, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1501 { .Name: 2211, .SubRegs: 8869, .SuperRegs: 8282, .SubRegIndices: 10, .RegUnits: 23011385, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1502 { .Name: 2482, .SubRegs: 8869, .SuperRegs: 7057, .SubRegIndices: 10, .RegUnits: 23064634, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1503 { .Name: 2746, .SubRegs: 8869, .SuperRegs: 7057, .SubRegIndices: 10, .RegUnits: 24641595, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1504 { .Name: 192, .SubRegs: 8869, .SuperRegs: 7057, .SubRegIndices: 10, .RegUnits: 24694844, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1505 { .Name: 585, .SubRegs: 8869, .SuperRegs: 7057, .SubRegIndices: 10, .RegUnits: 24846397, .RegUnitLaneMasks: 52, .IsConstant: 0, .IsArtificial: 0 },
1506 { .Name: 310, .SubRegs: 5, .SuperRegs: 798, .SubRegIndices: 2, .RegUnits: 20686, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1507 { .Name: 693, .SubRegs: 5, .SuperRegs: 793, .SubRegIndices: 2, .RegUnits: 20687, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1508 { .Name: 945, .SubRegs: 5, .SuperRegs: 1315, .SubRegIndices: 2, .RegUnits: 20688, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1509 { .Name: 1257, .SubRegs: 5, .SuperRegs: 1309, .SubRegIndices: 2, .RegUnits: 20689, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1510 { .Name: 1515, .SubRegs: 5, .SuperRegs: 1341, .SubRegIndices: 2, .RegUnits: 20690, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1511 { .Name: 1835, .SubRegs: 5, .SuperRegs: 1334, .SubRegIndices: 2, .RegUnits: 20691, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1512 { .Name: 2053, .SubRegs: 5, .SuperRegs: 1424, .SubRegIndices: 2, .RegUnits: 20692, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1513 { .Name: 2335, .SubRegs: 5, .SuperRegs: 1416, .SubRegIndices: 2, .RegUnits: 20693, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1514 { .Name: 2582, .SubRegs: 5, .SuperRegs: 1416, .SubRegIndices: 2, .RegUnits: 20694, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1515 { .Name: 2849, .SubRegs: 5, .SuperRegs: 1408, .SubRegIndices: 2, .RegUnits: 20695, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1516 { .Name: 56, .SubRegs: 5, .SuperRegs: 1408, .SubRegIndices: 2, .RegUnits: 20696, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1517 { .Name: 394, .SubRegs: 5, .SuperRegs: 1400, .SubRegIndices: 2, .RegUnits: 20697, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1518 { .Name: 777, .SubRegs: 5, .SuperRegs: 1400, .SubRegIndices: 2, .RegUnits: 20698, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1519 { .Name: 1031, .SubRegs: 5, .SuperRegs: 1392, .SubRegIndices: 2, .RegUnits: 20699, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1520 { .Name: 1341, .SubRegs: 5, .SuperRegs: 1392, .SubRegIndices: 2, .RegUnits: 20700, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1521 { .Name: 1600, .SubRegs: 5, .SuperRegs: 1384, .SubRegIndices: 2, .RegUnits: 20701, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1522 { .Name: 1900, .SubRegs: 5, .SuperRegs: 1384, .SubRegIndices: 2, .RegUnits: 20702, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1523 { .Name: 2119, .SubRegs: 5, .SuperRegs: 1376, .SubRegIndices: 2, .RegUnits: 20703, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1524 { .Name: 2418, .SubRegs: 5, .SuperRegs: 1376, .SubRegIndices: 2, .RegUnits: 20704, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1525 { .Name: 2654, .SubRegs: 5, .SuperRegs: 1368, .SubRegIndices: 2, .RegUnits: 20705, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1526 { .Name: 128, .SubRegs: 5, .SuperRegs: 1368, .SubRegIndices: 2, .RegUnits: 20706, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1527 { .Name: 493, .SubRegs: 5, .SuperRegs: 1360, .SubRegIndices: 2, .RegUnits: 20707, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1528 { .Name: 864, .SubRegs: 5, .SuperRegs: 3935, .SubRegIndices: 2, .RegUnits: 20708, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1529 { .Name: 1147, .SubRegs: 5, .SuperRegs: 3927, .SubRegIndices: 2, .RegUnits: 20709, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1530 { .Name: 1430, .SubRegs: 5, .SuperRegs: 5069, .SubRegIndices: 2, .RegUnits: 20710, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1531 { .Name: 1719, .SubRegs: 5, .SuperRegs: 5062, .SubRegIndices: 2, .RegUnits: 20711, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1532 { .Name: 1968, .SubRegs: 5, .SuperRegs: 7007, .SubRegIndices: 2, .RegUnits: 20712, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1533 { .Name: 2219, .SubRegs: 5, .SuperRegs: 7001, .SubRegIndices: 2, .RegUnits: 20713, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1534 { .Name: 2486, .SubRegs: 5, .SuperRegs: 783, .SubRegIndices: 2, .RegUnits: 20714, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1535 { .Name: 2754, .SubRegs: 5, .SuperRegs: 788, .SubRegIndices: 2, .RegUnits: 20481, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1536 { .Name: 196, .SubRegs: 5, .SuperRegs: 8598, .SubRegIndices: 2, .RegUnits: 20486, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1537 { .Name: 313, .SubRegs: 9396, .SuperRegs: 812, .SubRegIndices: 21, .RegUnits: 35307726, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1538 { .Name: 699, .SubRegs: 9396, .SuperRegs: 808, .SubRegIndices: 21, .RegUnits: 35307727, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1539 { .Name: 948, .SubRegs: 9396, .SuperRegs: 1327, .SubRegIndices: 21, .RegUnits: 35307728, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1540 { .Name: 1263, .SubRegs: 9396, .SuperRegs: 1322, .SubRegIndices: 21, .RegUnits: 35307729, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1541 { .Name: 1518, .SubRegs: 9396, .SuperRegs: 1355, .SubRegIndices: 21, .RegUnits: 35307730, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1542 { .Name: 1841, .SubRegs: 9396, .SuperRegs: 1349, .SubRegIndices: 21, .RegUnits: 35307731, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1543 { .Name: 2056, .SubRegs: 9396, .SuperRegs: 1489, .SubRegIndices: 21, .RegUnits: 35307732, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1544 { .Name: 2359, .SubRegs: 9396, .SuperRegs: 1482, .SubRegIndices: 21, .RegUnits: 35307733, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1545 { .Name: 2585, .SubRegs: 9396, .SuperRegs: 1482, .SubRegIndices: 21, .RegUnits: 35307734, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1546 { .Name: 2873, .SubRegs: 9396, .SuperRegs: 1475, .SubRegIndices: 21, .RegUnits: 35307735, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1547 { .Name: 60, .SubRegs: 9396, .SuperRegs: 1475, .SubRegIndices: 21, .RegUnits: 35307736, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1548 { .Name: 420, .SubRegs: 9396, .SuperRegs: 1468, .SubRegIndices: 21, .RegUnits: 35307737, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1549 { .Name: 781, .SubRegs: 9396, .SuperRegs: 1468, .SubRegIndices: 21, .RegUnits: 35307738, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1550 { .Name: 1059, .SubRegs: 9396, .SuperRegs: 1461, .SubRegIndices: 21, .RegUnits: 35307739, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1551 { .Name: 1345, .SubRegs: 9396, .SuperRegs: 1461, .SubRegIndices: 21, .RegUnits: 35307740, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1552 { .Name: 1630, .SubRegs: 9396, .SuperRegs: 1454, .SubRegIndices: 21, .RegUnits: 35307741, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1553 { .Name: 1904, .SubRegs: 9396, .SuperRegs: 1454, .SubRegIndices: 21, .RegUnits: 35307742, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1554 { .Name: 2151, .SubRegs: 9396, .SuperRegs: 1447, .SubRegIndices: 21, .RegUnits: 35307743, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1555 { .Name: 2422, .SubRegs: 9396, .SuperRegs: 1447, .SubRegIndices: 21, .RegUnits: 35307744, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1556 { .Name: 2686, .SubRegs: 9396, .SuperRegs: 1440, .SubRegIndices: 21, .RegUnits: 35307745, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1557 { .Name: 132, .SubRegs: 9396, .SuperRegs: 1440, .SubRegIndices: 21, .RegUnits: 35307746, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1558 { .Name: 525, .SubRegs: 9396, .SuperRegs: 1433, .SubRegIndices: 21, .RegUnits: 35307747, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1559 { .Name: 868, .SubRegs: 9396, .SuperRegs: 3951, .SubRegIndices: 21, .RegUnits: 35307748, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1560 { .Name: 1179, .SubRegs: 9396, .SuperRegs: 3944, .SubRegIndices: 21, .RegUnits: 35307749, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1561 { .Name: 1434, .SubRegs: 9396, .SuperRegs: 5083, .SubRegIndices: 21, .RegUnits: 35307750, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1562 { .Name: 1751, .SubRegs: 9396, .SuperRegs: 5077, .SubRegIndices: 21, .RegUnits: 35307751, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1563 { .Name: 1972, .SubRegs: 9396, .SuperRegs: 7019, .SubRegIndices: 21, .RegUnits: 35307752, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1564 { .Name: 2251, .SubRegs: 9396, .SuperRegs: 7014, .SubRegIndices: 21, .RegUnits: 35307753, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1565 { .Name: 2490, .SubRegs: 9396, .SuperRegs: 804, .SubRegIndices: 21, .RegUnits: 35307754, .RegUnitLaneMasks: 99, .IsConstant: 0, .IsArtificial: 0 },
1566 { .Name: 328, .SubRegs: 8800, .SuperRegs: 7357, .SubRegIndices: 27, .RegUnits: 37376030, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1567 { .Name: 713, .SubRegs: 8800, .SuperRegs: 7530, .SubRegIndices: 27, .RegUnits: 37351455, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1568 { .Name: 961, .SubRegs: 8800, .SuperRegs: 7703, .SubRegIndices: 27, .RegUnits: 37326880, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1569 { .Name: 1275, .SubRegs: 8800, .SuperRegs: 8222, .SubRegIndices: 27, .RegUnits: 37302305, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1570 { .Name: 1530, .SubRegs: 8800, .SuperRegs: 6797, .SubRegIndices: 27, .RegUnits: 37277730, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1571 { .Name: 1853, .SubRegs: 8800, .SuperRegs: 6797, .SubRegIndices: 27, .RegUnits: 37253155, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1572 { .Name: 2068, .SubRegs: 8800, .SuperRegs: 6797, .SubRegIndices: 27, .RegUnits: 37228580, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1573 { .Name: 2371, .SubRegs: 8800, .SuperRegs: 6797, .SubRegIndices: 27, .RegUnits: 37204005, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1574 { .Name: 2591, .SubRegs: 8800, .SuperRegs: 8049, .SubRegIndices: 27, .RegUnits: 37179430, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1575 { .Name: 2879, .SubRegs: 8800, .SuperRegs: 8049, .SubRegIndices: 27, .RegUnits: 37154855, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1576 { .Name: 67, .SubRegs: 8800, .SuperRegs: 8049, .SubRegIndices: 27, .RegUnits: 37130280, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1577 { .Name: 434, .SubRegs: 8800, .SuperRegs: 8049, .SubRegIndices: 27, .RegUnits: 37105705, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1578 { .Name: 796, .SubRegs: 8800, .SuperRegs: 6624, .SubRegIndices: 27, .RegUnits: 37081130, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1579 { .Name: 1075, .SubRegs: 8800, .SuperRegs: 6624, .SubRegIndices: 27, .RegUnits: 37056555, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1580 { .Name: 1359, .SubRegs: 8800, .SuperRegs: 6624, .SubRegIndices: 27, .RegUnits: 37031980, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1581 { .Name: 1644, .SubRegs: 8800, .SuperRegs: 6624, .SubRegIndices: 27, .RegUnits: 37007405, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1582 { .Name: 1920, .SubRegs: 8800, .SuperRegs: 8582, .SubRegIndices: 27, .RegUnits: 36982830, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1583 { .Name: 2167, .SubRegs: 8800, .SuperRegs: 8582, .SubRegIndices: 27, .RegUnits: 36958255, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1584 { .Name: 2438, .SubRegs: 8800, .SuperRegs: 8582, .SubRegIndices: 27, .RegUnits: 36933680, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1585 { .Name: 2702, .SubRegs: 8800, .SuperRegs: 8582, .SubRegIndices: 27, .RegUnits: 36909105, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1586 { .Name: 148, .SubRegs: 8800, .SuperRegs: 7876, .SubRegIndices: 27, .RegUnits: 36884530, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1587 { .Name: 541, .SubRegs: 8800, .SuperRegs: 7876, .SubRegIndices: 27, .RegUnits: 36859955, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1588 { .Name: 884, .SubRegs: 8800, .SuperRegs: 7876, .SubRegIndices: 27, .RegUnits: 36835380, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1589 { .Name: 1195, .SubRegs: 8800, .SuperRegs: 7876, .SubRegIndices: 27, .RegUnits: 36810805, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1590 { .Name: 1450, .SubRegs: 8800, .SuperRegs: 8409, .SubRegIndices: 27, .RegUnits: 36786230, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1591 { .Name: 1767, .SubRegs: 8800, .SuperRegs: 8409, .SubRegIndices: 27, .RegUnits: 36761655, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1592 { .Name: 1988, .SubRegs: 8800, .SuperRegs: 8409, .SubRegIndices: 27, .RegUnits: 36737080, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1593 { .Name: 2267, .SubRegs: 8800, .SuperRegs: 8409, .SubRegIndices: 27, .RegUnits: 36712505, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1594 { .Name: 2498, .SubRegs: 8800, .SuperRegs: 7184, .SubRegIndices: 27, .RegUnits: 36687930, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1595 { .Name: 2762, .SubRegs: 8800, .SuperRegs: 7184, .SubRegIndices: 27, .RegUnits: 36663355, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1596 { .Name: 204, .SubRegs: 8800, .SuperRegs: 7184, .SubRegIndices: 27, .RegUnits: 36638780, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1597 { .Name: 601, .SubRegs: 8800, .SuperRegs: 7184, .SubRegIndices: 27, .RegUnits: 36614205, .RegUnitLaneMasks: 107, .IsConstant: 0, .IsArtificial: 0 },
1598 { .Name: 240, .SubRegs: 6432, .SuperRegs: 4, .SubRegIndices: 58, .RegUnits: 6123534, .RegUnitLaneMasks: 179, .IsConstant: 0, .IsArtificial: 0 },
1599 { .Name: 245, .SubRegs: 6460, .SuperRegs: 85, .SubRegIndices: 25, .RegUnits: 4997134, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1600 { .Name: 632, .SubRegs: 6460, .SuperRegs: 37, .SubRegIndices: 25, .RegUnits: 4997142, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1601 { .Name: 891, .SubRegs: 6460, .SuperRegs: 61, .SubRegIndices: 25, .RegUnits: 4997138, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1602 { .Name: 1202, .SubRegs: 6460, .SuperRegs: 13, .SubRegIndices: 25, .RegUnits: 4997146, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1603 { .Name: 1465, .SubRegs: 6460, .SuperRegs: 73, .SubRegIndices: 25, .RegUnits: 4997136, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1604 { .Name: 1782, .SubRegs: 6460, .SuperRegs: 25, .SubRegIndices: 25, .RegUnits: 4997144, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1605 { .Name: 2003, .SubRegs: 6460, .SuperRegs: 49, .SubRegIndices: 25, .RegUnits: 4997140, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1606 { .Name: 2282, .SubRegs: 6460, .SuperRegs: 1, .SubRegIndices: 25, .RegUnits: 4997148, .RegUnitLaneMasks: 105, .IsConstant: 0, .IsArtificial: 0 },
1607 { .Name: 265, .SubRegs: 6448, .SuperRegs: 51, .SubRegIndices: 43, .RegUnits: 6156302, .RegUnitLaneMasks: 171, .IsConstant: 0, .IsArtificial: 0 },
1608 { .Name: 651, .SubRegs: 6448, .SuperRegs: 3, .SubRegIndices: 43, .RegUnits: 6156310, .RegUnitLaneMasks: 171, .IsConstant: 0, .IsArtificial: 0 },
1609 { .Name: 281, .SubRegs: 5, .SuperRegs: 90, .SubRegIndices: 2, .RegUnits: 20494, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1610 { .Name: 666, .SubRegs: 5, .SuperRegs: 42, .SubRegIndices: 2, .RegUnits: 20502, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1611 { .Name: 922, .SubRegs: 5, .SuperRegs: 66, .SubRegIndices: 2, .RegUnits: 20498, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1612 { .Name: 1232, .SubRegs: 5, .SuperRegs: 18, .SubRegIndices: 2, .RegUnits: 20506, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1613 { .Name: 1495, .SubRegs: 5, .SuperRegs: 78, .SubRegIndices: 2, .RegUnits: 20496, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1614 { .Name: 1812, .SubRegs: 5, .SuperRegs: 30, .SubRegIndices: 2, .RegUnits: 20504, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1615 { .Name: 2033, .SubRegs: 5, .SuperRegs: 54, .SubRegIndices: 2, .RegUnits: 20500, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1616 { .Name: 2312, .SubRegs: 5, .SuperRegs: 6, .SubRegIndices: 2, .RegUnits: 20508, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1617 { .Name: 2562, .SubRegs: 5, .SuperRegs: 84, .SubRegIndices: 2, .RegUnits: 20495, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1618 { .Name: 2826, .SubRegs: 5, .SuperRegs: 36, .SubRegIndices: 2, .RegUnits: 20503, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1619 { .Name: 33, .SubRegs: 5, .SuperRegs: 60, .SubRegIndices: 2, .RegUnits: 20499, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1620 { .Name: 366, .SubRegs: 5, .SuperRegs: 12, .SubRegIndices: 2, .RegUnits: 20507, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1621 { .Name: 752, .SubRegs: 5, .SuperRegs: 72, .SubRegIndices: 2, .RegUnits: 20497, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1622 { .Name: 1001, .SubRegs: 5, .SuperRegs: 24, .SubRegIndices: 2, .RegUnits: 20505, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1623 { .Name: 1315, .SubRegs: 5, .SuperRegs: 48, .SubRegIndices: 2, .RegUnits: 20501, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1624 { .Name: 1570, .SubRegs: 5, .SuperRegs: 0, .SubRegIndices: 2, .RegUnits: 20509, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1625 { .Name: 301, .SubRegs: 6456, .SuperRegs: 74, .SubRegIndices: 37, .RegUnits: 5586958, .RegUnitLaneMasks: 167, .IsConstant: 0, .IsArtificial: 0 },
1626 { .Name: 685, .SubRegs: 6456, .SuperRegs: 26, .SubRegIndices: 37, .RegUnits: 5586966, .RegUnitLaneMasks: 167, .IsConstant: 0, .IsArtificial: 0 },
1627 { .Name: 940, .SubRegs: 6456, .SuperRegs: 50, .SubRegIndices: 37, .RegUnits: 5586962, .RegUnitLaneMasks: 167, .IsConstant: 0, .IsArtificial: 0 },
1628 { .Name: 1249, .SubRegs: 6456, .SuperRegs: 2, .SubRegIndices: 37, .RegUnits: 5586970, .RegUnitLaneMasks: 167, .IsConstant: 0, .IsArtificial: 0 },
1629 { .Name: 306, .SubRegs: 5, .SuperRegs: 5, .SubRegIndices: 2, .RegUnits: 20776, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 0 },
1630 { .Name: 3026, .SubRegs: 5, .SuperRegs: 7263, .SubRegIndices: 2, .RegUnits: 20542, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1631 { .Name: 3181, .SubRegs: 5, .SuperRegs: 7436, .SubRegIndices: 2, .RegUnits: 20545, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1632 { .Name: 3301, .SubRegs: 5, .SuperRegs: 7609, .SubRegIndices: 2, .RegUnits: 20548, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1633 { .Name: 3421, .SubRegs: 5, .SuperRegs: 8128, .SubRegIndices: 2, .RegUnits: 20551, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1634 { .Name: 3541, .SubRegs: 5, .SuperRegs: 6703, .SubRegIndices: 2, .RegUnits: 20554, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1635 { .Name: 3661, .SubRegs: 5, .SuperRegs: 6703, .SubRegIndices: 2, .RegUnits: 20557, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1636 { .Name: 3781, .SubRegs: 5, .SuperRegs: 6703, .SubRegIndices: 2, .RegUnits: 20560, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1637 { .Name: 3901, .SubRegs: 5, .SuperRegs: 6703, .SubRegIndices: 2, .RegUnits: 20563, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1638 { .Name: 4021, .SubRegs: 5, .SuperRegs: 7955, .SubRegIndices: 2, .RegUnits: 20566, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1639 { .Name: 4141, .SubRegs: 5, .SuperRegs: 7955, .SubRegIndices: 2, .RegUnits: 20569, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1640 { .Name: 2900, .SubRegs: 5, .SuperRegs: 7955, .SubRegIndices: 2, .RegUnits: 20572, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1641 { .Name: 3062, .SubRegs: 5, .SuperRegs: 7955, .SubRegIndices: 2, .RegUnits: 20575, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1642 { .Name: 3217, .SubRegs: 5, .SuperRegs: 6530, .SubRegIndices: 2, .RegUnits: 20578, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1643 { .Name: 3337, .SubRegs: 5, .SuperRegs: 6530, .SubRegIndices: 2, .RegUnits: 20581, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1644 { .Name: 3457, .SubRegs: 5, .SuperRegs: 6530, .SubRegIndices: 2, .RegUnits: 20584, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1645 { .Name: 3577, .SubRegs: 5, .SuperRegs: 6530, .SubRegIndices: 2, .RegUnits: 20587, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1646 { .Name: 3697, .SubRegs: 5, .SuperRegs: 8488, .SubRegIndices: 2, .RegUnits: 20590, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1647 { .Name: 3817, .SubRegs: 5, .SuperRegs: 8488, .SubRegIndices: 2, .RegUnits: 20593, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1648 { .Name: 3937, .SubRegs: 5, .SuperRegs: 8488, .SubRegIndices: 2, .RegUnits: 20596, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1649 { .Name: 4057, .SubRegs: 5, .SuperRegs: 8488, .SubRegIndices: 2, .RegUnits: 20599, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1650 { .Name: 2942, .SubRegs: 5, .SuperRegs: 7782, .SubRegIndices: 2, .RegUnits: 20602, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1651 { .Name: 3104, .SubRegs: 5, .SuperRegs: 7782, .SubRegIndices: 2, .RegUnits: 20605, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1652 { .Name: 3259, .SubRegs: 5, .SuperRegs: 7782, .SubRegIndices: 2, .RegUnits: 20608, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1653 { .Name: 3379, .SubRegs: 5, .SuperRegs: 7782, .SubRegIndices: 2, .RegUnits: 20611, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1654 { .Name: 3499, .SubRegs: 5, .SuperRegs: 8315, .SubRegIndices: 2, .RegUnits: 20614, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1655 { .Name: 3619, .SubRegs: 5, .SuperRegs: 8315, .SubRegIndices: 2, .RegUnits: 20617, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1656 { .Name: 3739, .SubRegs: 5, .SuperRegs: 8315, .SubRegIndices: 2, .RegUnits: 20620, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1657 { .Name: 3859, .SubRegs: 5, .SuperRegs: 8315, .SubRegIndices: 2, .RegUnits: 20623, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1658 { .Name: 3979, .SubRegs: 5, .SuperRegs: 7090, .SubRegIndices: 2, .RegUnits: 20626, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1659 { .Name: 4099, .SubRegs: 5, .SuperRegs: 7090, .SubRegIndices: 2, .RegUnits: 20629, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1660 { .Name: 2984, .SubRegs: 5, .SuperRegs: 7090, .SubRegIndices: 2, .RegUnits: 20632, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1661 { .Name: 3146, .SubRegs: 5, .SuperRegs: 7090, .SubRegIndices: 2, .RegUnits: 20635, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1662 { .Name: 3032, .SubRegs: 5, .SuperRegs: 7333, .SubRegIndices: 2, .RegUnits: 20654, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1663 { .Name: 3187, .SubRegs: 5, .SuperRegs: 7506, .SubRegIndices: 2, .RegUnits: 20655, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1664 { .Name: 3307, .SubRegs: 5, .SuperRegs: 7679, .SubRegIndices: 2, .RegUnits: 20656, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1665 { .Name: 3427, .SubRegs: 5, .SuperRegs: 8198, .SubRegIndices: 2, .RegUnits: 20657, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1666 { .Name: 3547, .SubRegs: 5, .SuperRegs: 6773, .SubRegIndices: 2, .RegUnits: 20658, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1667 { .Name: 3667, .SubRegs: 5, .SuperRegs: 6773, .SubRegIndices: 2, .RegUnits: 20659, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1668 { .Name: 3787, .SubRegs: 5, .SuperRegs: 6773, .SubRegIndices: 2, .RegUnits: 20660, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1669 { .Name: 3907, .SubRegs: 5, .SuperRegs: 6773, .SubRegIndices: 2, .RegUnits: 20661, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1670 { .Name: 4027, .SubRegs: 5, .SuperRegs: 8025, .SubRegIndices: 2, .RegUnits: 20662, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1671 { .Name: 4147, .SubRegs: 5, .SuperRegs: 8025, .SubRegIndices: 2, .RegUnits: 20663, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1672 { .Name: 2907, .SubRegs: 5, .SuperRegs: 8025, .SubRegIndices: 2, .RegUnits: 20664, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1673 { .Name: 3069, .SubRegs: 5, .SuperRegs: 8025, .SubRegIndices: 2, .RegUnits: 20665, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1674 { .Name: 3224, .SubRegs: 5, .SuperRegs: 6600, .SubRegIndices: 2, .RegUnits: 20666, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1675 { .Name: 3344, .SubRegs: 5, .SuperRegs: 6600, .SubRegIndices: 2, .RegUnits: 20667, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1676 { .Name: 3464, .SubRegs: 5, .SuperRegs: 6600, .SubRegIndices: 2, .RegUnits: 20668, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1677 { .Name: 3584, .SubRegs: 5, .SuperRegs: 6600, .SubRegIndices: 2, .RegUnits: 20669, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1678 { .Name: 3704, .SubRegs: 5, .SuperRegs: 8558, .SubRegIndices: 2, .RegUnits: 20670, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1679 { .Name: 3824, .SubRegs: 5, .SuperRegs: 8558, .SubRegIndices: 2, .RegUnits: 20671, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1680 { .Name: 3944, .SubRegs: 5, .SuperRegs: 8558, .SubRegIndices: 2, .RegUnits: 20672, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1681 { .Name: 4064, .SubRegs: 5, .SuperRegs: 8558, .SubRegIndices: 2, .RegUnits: 20673, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1682 { .Name: 2949, .SubRegs: 5, .SuperRegs: 7852, .SubRegIndices: 2, .RegUnits: 20674, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1683 { .Name: 3111, .SubRegs: 5, .SuperRegs: 7852, .SubRegIndices: 2, .RegUnits: 20675, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1684 { .Name: 3266, .SubRegs: 5, .SuperRegs: 7852, .SubRegIndices: 2, .RegUnits: 20676, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1685 { .Name: 3386, .SubRegs: 5, .SuperRegs: 7852, .SubRegIndices: 2, .RegUnits: 20677, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1686 { .Name: 3506, .SubRegs: 5, .SuperRegs: 8385, .SubRegIndices: 2, .RegUnits: 20678, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1687 { .Name: 3626, .SubRegs: 5, .SuperRegs: 8385, .SubRegIndices: 2, .RegUnits: 20679, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1688 { .Name: 3746, .SubRegs: 5, .SuperRegs: 8385, .SubRegIndices: 2, .RegUnits: 20680, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1689 { .Name: 3866, .SubRegs: 5, .SuperRegs: 8385, .SubRegIndices: 2, .RegUnits: 20681, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1690 { .Name: 3986, .SubRegs: 5, .SuperRegs: 7160, .SubRegIndices: 2, .RegUnits: 20682, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1691 { .Name: 4106, .SubRegs: 5, .SuperRegs: 7160, .SubRegIndices: 2, .RegUnits: 20683, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1692 { .Name: 2991, .SubRegs: 5, .SuperRegs: 7160, .SubRegIndices: 2, .RegUnits: 20684, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1693 { .Name: 3153, .SubRegs: 5, .SuperRegs: 7160, .SubRegIndices: 2, .RegUnits: 20685, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1694 { .Name: 3038, .SubRegs: 5, .SuperRegs: 7229, .SubRegIndices: 2, .RegUnits: 20543, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1695 { .Name: 3193, .SubRegs: 5, .SuperRegs: 7402, .SubRegIndices: 2, .RegUnits: 20546, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1696 { .Name: 3313, .SubRegs: 5, .SuperRegs: 7575, .SubRegIndices: 2, .RegUnits: 20549, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1697 { .Name: 3433, .SubRegs: 5, .SuperRegs: 8094, .SubRegIndices: 2, .RegUnits: 20552, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1698 { .Name: 3553, .SubRegs: 5, .SuperRegs: 6669, .SubRegIndices: 2, .RegUnits: 20555, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1699 { .Name: 3673, .SubRegs: 5, .SuperRegs: 6669, .SubRegIndices: 2, .RegUnits: 20558, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1700 { .Name: 3793, .SubRegs: 5, .SuperRegs: 6669, .SubRegIndices: 2, .RegUnits: 20561, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1701 { .Name: 3913, .SubRegs: 5, .SuperRegs: 6669, .SubRegIndices: 2, .RegUnits: 20564, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1702 { .Name: 4033, .SubRegs: 5, .SuperRegs: 7921, .SubRegIndices: 2, .RegUnits: 20567, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1703 { .Name: 4153, .SubRegs: 5, .SuperRegs: 7921, .SubRegIndices: 2, .RegUnits: 20570, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1704 { .Name: 2914, .SubRegs: 5, .SuperRegs: 7921, .SubRegIndices: 2, .RegUnits: 20573, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1705 { .Name: 3076, .SubRegs: 5, .SuperRegs: 7921, .SubRegIndices: 2, .RegUnits: 20576, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1706 { .Name: 3231, .SubRegs: 5, .SuperRegs: 6496, .SubRegIndices: 2, .RegUnits: 20579, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1707 { .Name: 3351, .SubRegs: 5, .SuperRegs: 6496, .SubRegIndices: 2, .RegUnits: 20582, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1708 { .Name: 3471, .SubRegs: 5, .SuperRegs: 6496, .SubRegIndices: 2, .RegUnits: 20585, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1709 { .Name: 3591, .SubRegs: 5, .SuperRegs: 6496, .SubRegIndices: 2, .RegUnits: 20588, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1710 { .Name: 3711, .SubRegs: 5, .SuperRegs: 8454, .SubRegIndices: 2, .RegUnits: 20591, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1711 { .Name: 3831, .SubRegs: 5, .SuperRegs: 8454, .SubRegIndices: 2, .RegUnits: 20594, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1712 { .Name: 3951, .SubRegs: 5, .SuperRegs: 8454, .SubRegIndices: 2, .RegUnits: 20597, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1713 { .Name: 4071, .SubRegs: 5, .SuperRegs: 8454, .SubRegIndices: 2, .RegUnits: 20600, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1714 { .Name: 2956, .SubRegs: 5, .SuperRegs: 7748, .SubRegIndices: 2, .RegUnits: 20603, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1715 { .Name: 3118, .SubRegs: 5, .SuperRegs: 7748, .SubRegIndices: 2, .RegUnits: 20606, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1716 { .Name: 3273, .SubRegs: 5, .SuperRegs: 7748, .SubRegIndices: 2, .RegUnits: 20609, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1717 { .Name: 3393, .SubRegs: 5, .SuperRegs: 7748, .SubRegIndices: 2, .RegUnits: 20612, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1718 { .Name: 3513, .SubRegs: 5, .SuperRegs: 8281, .SubRegIndices: 2, .RegUnits: 20615, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1719 { .Name: 3633, .SubRegs: 5, .SuperRegs: 8281, .SubRegIndices: 2, .RegUnits: 20618, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1720 { .Name: 3753, .SubRegs: 5, .SuperRegs: 8281, .SubRegIndices: 2, .RegUnits: 20621, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1721 { .Name: 3873, .SubRegs: 5, .SuperRegs: 8281, .SubRegIndices: 2, .RegUnits: 20624, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1722 { .Name: 3993, .SubRegs: 5, .SuperRegs: 7056, .SubRegIndices: 2, .RegUnits: 20627, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1723 { .Name: 4113, .SubRegs: 5, .SuperRegs: 7056, .SubRegIndices: 2, .RegUnits: 20630, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1724 { .Name: 2998, .SubRegs: 5, .SuperRegs: 7056, .SubRegIndices: 2, .RegUnits: 20633, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1725 { .Name: 3160, .SubRegs: 5, .SuperRegs: 7056, .SubRegIndices: 2, .RegUnits: 20636, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1726 { .Name: 3044, .SubRegs: 5, .SuperRegs: 7356, .SubRegIndices: 2, .RegUnits: 20744, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1727 { .Name: 3199, .SubRegs: 5, .SuperRegs: 7529, .SubRegIndices: 2, .RegUnits: 20745, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1728 { .Name: 3319, .SubRegs: 5, .SuperRegs: 7702, .SubRegIndices: 2, .RegUnits: 20746, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1729 { .Name: 3439, .SubRegs: 5, .SuperRegs: 8221, .SubRegIndices: 2, .RegUnits: 20747, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1730 { .Name: 3559, .SubRegs: 5, .SuperRegs: 6796, .SubRegIndices: 2, .RegUnits: 20748, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1731 { .Name: 3679, .SubRegs: 5, .SuperRegs: 6796, .SubRegIndices: 2, .RegUnits: 20749, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1732 { .Name: 3799, .SubRegs: 5, .SuperRegs: 6796, .SubRegIndices: 2, .RegUnits: 20750, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1733 { .Name: 3919, .SubRegs: 5, .SuperRegs: 6796, .SubRegIndices: 2, .RegUnits: 20751, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1734 { .Name: 4039, .SubRegs: 5, .SuperRegs: 8048, .SubRegIndices: 2, .RegUnits: 20752, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1735 { .Name: 4159, .SubRegs: 5, .SuperRegs: 8048, .SubRegIndices: 2, .RegUnits: 20753, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1736 { .Name: 2921, .SubRegs: 5, .SuperRegs: 8048, .SubRegIndices: 2, .RegUnits: 20754, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1737 { .Name: 3083, .SubRegs: 5, .SuperRegs: 8048, .SubRegIndices: 2, .RegUnits: 20755, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1738 { .Name: 3238, .SubRegs: 5, .SuperRegs: 6623, .SubRegIndices: 2, .RegUnits: 20756, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1739 { .Name: 3358, .SubRegs: 5, .SuperRegs: 6623, .SubRegIndices: 2, .RegUnits: 20757, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1740 { .Name: 3478, .SubRegs: 5, .SuperRegs: 6623, .SubRegIndices: 2, .RegUnits: 20758, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1741 { .Name: 3598, .SubRegs: 5, .SuperRegs: 6623, .SubRegIndices: 2, .RegUnits: 20759, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1742 { .Name: 3718, .SubRegs: 5, .SuperRegs: 8581, .SubRegIndices: 2, .RegUnits: 20760, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1743 { .Name: 3838, .SubRegs: 5, .SuperRegs: 8581, .SubRegIndices: 2, .RegUnits: 20761, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1744 { .Name: 3958, .SubRegs: 5, .SuperRegs: 8581, .SubRegIndices: 2, .RegUnits: 20762, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1745 { .Name: 4078, .SubRegs: 5, .SuperRegs: 8581, .SubRegIndices: 2, .RegUnits: 20763, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1746 { .Name: 2963, .SubRegs: 5, .SuperRegs: 7875, .SubRegIndices: 2, .RegUnits: 20764, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1747 { .Name: 3125, .SubRegs: 5, .SuperRegs: 7875, .SubRegIndices: 2, .RegUnits: 20765, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1748 { .Name: 3280, .SubRegs: 5, .SuperRegs: 7875, .SubRegIndices: 2, .RegUnits: 20766, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1749 { .Name: 3400, .SubRegs: 5, .SuperRegs: 7875, .SubRegIndices: 2, .RegUnits: 20767, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1750 { .Name: 3520, .SubRegs: 5, .SuperRegs: 8408, .SubRegIndices: 2, .RegUnits: 20768, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1751 { .Name: 3640, .SubRegs: 5, .SuperRegs: 8408, .SubRegIndices: 2, .RegUnits: 20769, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1752 { .Name: 3760, .SubRegs: 5, .SuperRegs: 8408, .SubRegIndices: 2, .RegUnits: 20770, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1753 { .Name: 3880, .SubRegs: 5, .SuperRegs: 8408, .SubRegIndices: 2, .RegUnits: 20771, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1754 { .Name: 4000, .SubRegs: 5, .SuperRegs: 7183, .SubRegIndices: 2, .RegUnits: 20772, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1755 { .Name: 4120, .SubRegs: 5, .SuperRegs: 7183, .SubRegIndices: 2, .RegUnits: 20773, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1756 { .Name: 3005, .SubRegs: 5, .SuperRegs: 7183, .SubRegIndices: 2, .RegUnits: 20774, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1757 { .Name: 3167, .SubRegs: 5, .SuperRegs: 7183, .SubRegIndices: 2, .RegUnits: 20775, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1758 { .Name: 3050, .SubRegs: 5, .SuperRegs: 7196, .SubRegIndices: 2, .RegUnits: 20544, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1759 { .Name: 3205, .SubRegs: 5, .SuperRegs: 7369, .SubRegIndices: 2, .RegUnits: 20547, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1760 { .Name: 3325, .SubRegs: 5, .SuperRegs: 7542, .SubRegIndices: 2, .RegUnits: 20550, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1761 { .Name: 3445, .SubRegs: 5, .SuperRegs: 8061, .SubRegIndices: 2, .RegUnits: 20553, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1762 { .Name: 3565, .SubRegs: 5, .SuperRegs: 6636, .SubRegIndices: 2, .RegUnits: 20556, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1763 { .Name: 3685, .SubRegs: 5, .SuperRegs: 6636, .SubRegIndices: 2, .RegUnits: 20559, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1764 { .Name: 3805, .SubRegs: 5, .SuperRegs: 6636, .SubRegIndices: 2, .RegUnits: 20562, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1765 { .Name: 3925, .SubRegs: 5, .SuperRegs: 6636, .SubRegIndices: 2, .RegUnits: 20565, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1766 { .Name: 4045, .SubRegs: 5, .SuperRegs: 7888, .SubRegIndices: 2, .RegUnits: 20568, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1767 { .Name: 4165, .SubRegs: 5, .SuperRegs: 7888, .SubRegIndices: 2, .RegUnits: 20571, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1768 { .Name: 2928, .SubRegs: 5, .SuperRegs: 7888, .SubRegIndices: 2, .RegUnits: 20574, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1769 { .Name: 3090, .SubRegs: 5, .SuperRegs: 7888, .SubRegIndices: 2, .RegUnits: 20577, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1770 { .Name: 3245, .SubRegs: 5, .SuperRegs: 6463, .SubRegIndices: 2, .RegUnits: 20580, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1771 { .Name: 3365, .SubRegs: 5, .SuperRegs: 6463, .SubRegIndices: 2, .RegUnits: 20583, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1772 { .Name: 3485, .SubRegs: 5, .SuperRegs: 6463, .SubRegIndices: 2, .RegUnits: 20586, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1773 { .Name: 3605, .SubRegs: 5, .SuperRegs: 6463, .SubRegIndices: 2, .RegUnits: 20589, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1774 { .Name: 3725, .SubRegs: 5, .SuperRegs: 8421, .SubRegIndices: 2, .RegUnits: 20592, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1775 { .Name: 3845, .SubRegs: 5, .SuperRegs: 8421, .SubRegIndices: 2, .RegUnits: 20595, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1776 { .Name: 3965, .SubRegs: 5, .SuperRegs: 8421, .SubRegIndices: 2, .RegUnits: 20598, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1777 { .Name: 4085, .SubRegs: 5, .SuperRegs: 8421, .SubRegIndices: 2, .RegUnits: 20601, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1778 { .Name: 2970, .SubRegs: 5, .SuperRegs: 7715, .SubRegIndices: 2, .RegUnits: 20604, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1779 { .Name: 3132, .SubRegs: 5, .SuperRegs: 7715, .SubRegIndices: 2, .RegUnits: 20607, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1780 { .Name: 3287, .SubRegs: 5, .SuperRegs: 7715, .SubRegIndices: 2, .RegUnits: 20610, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1781 { .Name: 3407, .SubRegs: 5, .SuperRegs: 7715, .SubRegIndices: 2, .RegUnits: 20613, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1782 { .Name: 3527, .SubRegs: 5, .SuperRegs: 8248, .SubRegIndices: 2, .RegUnits: 20616, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1783 { .Name: 3647, .SubRegs: 5, .SuperRegs: 8248, .SubRegIndices: 2, .RegUnits: 20619, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1784 { .Name: 3767, .SubRegs: 5, .SuperRegs: 8248, .SubRegIndices: 2, .RegUnits: 20622, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1785 { .Name: 3887, .SubRegs: 5, .SuperRegs: 8248, .SubRegIndices: 2, .RegUnits: 20625, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1786 { .Name: 4007, .SubRegs: 5, .SuperRegs: 7023, .SubRegIndices: 2, .RegUnits: 20628, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1787 { .Name: 4127, .SubRegs: 5, .SuperRegs: 7023, .SubRegIndices: 2, .RegUnits: 20631, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1788 { .Name: 3012, .SubRegs: 5, .SuperRegs: 7023, .SubRegIndices: 2, .RegUnits: 20634, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1789 { .Name: 3174, .SubRegs: 5, .SuperRegs: 7023, .SubRegIndices: 2, .RegUnits: 20637, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1790 { .Name: 3056, .SubRegs: 5, .SuperRegs: 811, .SubRegIndices: 2, .RegUnits: 20715, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1791 { .Name: 3211, .SubRegs: 5, .SuperRegs: 807, .SubRegIndices: 2, .RegUnits: 20716, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1792 { .Name: 3331, .SubRegs: 5, .SuperRegs: 1326, .SubRegIndices: 2, .RegUnits: 20717, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1793 { .Name: 3451, .SubRegs: 5, .SuperRegs: 1321, .SubRegIndices: 2, .RegUnits: 20718, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1794 { .Name: 3571, .SubRegs: 5, .SuperRegs: 1354, .SubRegIndices: 2, .RegUnits: 20719, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1795 { .Name: 3691, .SubRegs: 5, .SuperRegs: 1348, .SubRegIndices: 2, .RegUnits: 20720, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1796 { .Name: 3811, .SubRegs: 5, .SuperRegs: 1488, .SubRegIndices: 2, .RegUnits: 20721, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1797 { .Name: 3931, .SubRegs: 5, .SuperRegs: 1481, .SubRegIndices: 2, .RegUnits: 20722, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1798 { .Name: 4051, .SubRegs: 5, .SuperRegs: 1481, .SubRegIndices: 2, .RegUnits: 20723, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1799 { .Name: 4171, .SubRegs: 5, .SuperRegs: 1474, .SubRegIndices: 2, .RegUnits: 20724, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1800 { .Name: 2935, .SubRegs: 5, .SuperRegs: 1474, .SubRegIndices: 2, .RegUnits: 20725, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1801 { .Name: 3097, .SubRegs: 5, .SuperRegs: 1467, .SubRegIndices: 2, .RegUnits: 20726, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1802 { .Name: 3252, .SubRegs: 5, .SuperRegs: 1467, .SubRegIndices: 2, .RegUnits: 20727, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1803 { .Name: 3372, .SubRegs: 5, .SuperRegs: 1460, .SubRegIndices: 2, .RegUnits: 20728, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1804 { .Name: 3492, .SubRegs: 5, .SuperRegs: 1460, .SubRegIndices: 2, .RegUnits: 20729, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1805 { .Name: 3612, .SubRegs: 5, .SuperRegs: 1453, .SubRegIndices: 2, .RegUnits: 20730, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1806 { .Name: 3732, .SubRegs: 5, .SuperRegs: 1453, .SubRegIndices: 2, .RegUnits: 20731, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1807 { .Name: 3852, .SubRegs: 5, .SuperRegs: 1446, .SubRegIndices: 2, .RegUnits: 20732, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1808 { .Name: 3972, .SubRegs: 5, .SuperRegs: 1446, .SubRegIndices: 2, .RegUnits: 20733, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1809 { .Name: 4092, .SubRegs: 5, .SuperRegs: 1439, .SubRegIndices: 2, .RegUnits: 20734, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1810 { .Name: 2977, .SubRegs: 5, .SuperRegs: 1439, .SubRegIndices: 2, .RegUnits: 20735, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1811 { .Name: 3139, .SubRegs: 5, .SuperRegs: 1432, .SubRegIndices: 2, .RegUnits: 20736, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1812 { .Name: 3294, .SubRegs: 5, .SuperRegs: 3950, .SubRegIndices: 2, .RegUnits: 20737, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1813 { .Name: 3414, .SubRegs: 5, .SuperRegs: 3943, .SubRegIndices: 2, .RegUnits: 20738, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1814 { .Name: 3534, .SubRegs: 5, .SuperRegs: 5082, .SubRegIndices: 2, .RegUnits: 20739, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1815 { .Name: 3654, .SubRegs: 5, .SuperRegs: 5076, .SubRegIndices: 2, .RegUnits: 20740, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1816 { .Name: 3774, .SubRegs: 5, .SuperRegs: 7018, .SubRegIndices: 2, .RegUnits: 20741, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1817 { .Name: 3894, .SubRegs: 5, .SuperRegs: 7013, .SubRegIndices: 2, .RegUnits: 20742, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1818 { .Name: 4014, .SubRegs: 5, .SuperRegs: 803, .SubRegIndices: 2, .RegUnits: 20743, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1819 { .Name: 4134, .SubRegs: 5, .SuperRegs: 815, .SubRegIndices: 2, .RegUnits: 20482, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1820 { .Name: 3019, .SubRegs: 5, .SuperRegs: 9419, .SubRegIndices: 2, .RegUnits: 20487, .RegUnitLaneMasks: 537, .IsConstant: 0, .IsArtificial: 1 },
1821 { .Name: 645, .SubRegs: 8854, .SuperRegs: 1282, .SubRegIndices: 88, .RegUnits: 9760798, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1822 { .Name: 903, .SubRegs: 8854, .SuperRegs: 8650, .SubRegIndices: 88, .RegUnits: 9793567, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1823 { .Name: 1213, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 9826336, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1824 { .Name: 1476, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 9859105, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1825 { .Name: 1793, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 9891874, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1826 { .Name: 2014, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 9924643, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1827 { .Name: 2293, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 9957412, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1828 { .Name: 2543, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 9990181, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1829 { .Name: 2807, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10022950, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1830 { .Name: 10, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10055719, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1831 { .Name: 341, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10088488, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1832 { .Name: 727, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10121257, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1833 { .Name: 976, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10154026, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1834 { .Name: 1290, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10186795, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1835 { .Name: 1545, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10219564, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1836 { .Name: 1868, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10252333, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1837 { .Name: 2083, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10285102, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1838 { .Name: 2386, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10317871, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1839 { .Name: 2618, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10350640, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1840 { .Name: 96, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10383409, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1841 { .Name: 457, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10416178, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1842 { .Name: 832, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10448947, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1843 { .Name: 1111, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10481716, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1844 { .Name: 1398, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10514485, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1845 { .Name: 1683, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10547254, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1846 { .Name: 1936, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10580023, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1847 { .Name: 2183, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10612792, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1848 { .Name: 2454, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10678329, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1849 { .Name: 2718, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10711098, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1850 { .Name: 164, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10793019, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1851 { .Name: 557, .SubRegs: 8854, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 10825788, .RegUnitLaneMasks: 195, .IsConstant: 0, .IsArtificial: 0 },
1852 { .Name: 258, .SubRegs: 8839, .SuperRegs: 1264, .SubRegIndices: 88, .RegUnits: 20242462, .RegUnitLaneMasks: 61, .IsConstant: 0, .IsArtificial: 0 },
1853 { .Name: 1207, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6189086, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1854 { .Name: 1470, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6254623, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1855 { .Name: 1787, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6320160, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1856 { .Name: 2008, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6385697, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1857 { .Name: 2287, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6451234, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1858 { .Name: 2537, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6516771, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1859 { .Name: 2801, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6582308, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1860 { .Name: 4, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6647845, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1861 { .Name: 335, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6713382, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1862 { .Name: 720, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6778919, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1863 { .Name: 968, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6844456, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1864 { .Name: 1282, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6909993, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1865 { .Name: 1537, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 6975530, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1866 { .Name: 1860, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7041067, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1867 { .Name: 2075, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7106604, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1868 { .Name: 2378, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7172141, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1869 { .Name: 2610, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7237678, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1870 { .Name: 88, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7303215, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1871 { .Name: 449, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7368752, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1872 { .Name: 824, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7434289, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1873 { .Name: 1103, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7499826, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1874 { .Name: 1390, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7565363, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1875 { .Name: 1675, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7630900, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1876 { .Name: 1928, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7696437, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1877 { .Name: 2175, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7761974, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1878 { .Name: 2446, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7827511, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1879 { .Name: 2710, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7893048, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1880 { .Name: 156, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 7958585, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1881 { .Name: 549, .SubRegs: 492, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 8024122, .RegUnitLaneMasks: 231, .IsConstant: 0, .IsArtificial: 0 },
1882 { .Name: 250, .SubRegs: 650, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 9465886, .RegUnitLaneMasks: 247, .IsConstant: 0, .IsArtificial: 0 },
1883 { .Name: 637, .SubRegs: 218, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 10645534, .RegUnitLaneMasks: 203, .IsConstant: 0, .IsArtificial: 0 },
1884 { .Name: 896, .SubRegs: 362, .SuperRegs: 9231, .SubRegIndices: 151, .RegUnits: 17731614, .RegUnitLaneMasks: 69, .IsConstant: 0, .IsArtificial: 0 },
1885 { .Name: 900, .SubRegs: 5357, .SuperRegs: 8701, .SubRegIndices: 128, .RegUnits: 8089630, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1886 { .Name: 1210, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8138783, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1887 { .Name: 1473, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8187936, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1888 { .Name: 1790, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8237089, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1889 { .Name: 2011, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8286242, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1890 { .Name: 2290, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8335395, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1891 { .Name: 2540, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8384548, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1892 { .Name: 2804, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8433701, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1893 { .Name: 7, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8482854, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1894 { .Name: 338, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8532007, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1895 { .Name: 723, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8581160, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1896 { .Name: 972, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8630313, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1897 { .Name: 1286, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8679466, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1898 { .Name: 1541, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8728619, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1899 { .Name: 1864, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8777772, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1900 { .Name: 2079, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8826925, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1901 { .Name: 2382, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8876078, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1902 { .Name: 2614, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8925231, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1903 { .Name: 92, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 8974384, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1904 { .Name: 453, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9023537, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1905 { .Name: 828, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9072690, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1906 { .Name: 1107, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9121843, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1907 { .Name: 1394, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9170996, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1908 { .Name: 1679, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9220149, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1909 { .Name: 1932, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9269302, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1910 { .Name: 2179, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9318455, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1911 { .Name: 2450, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9367608, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1912 { .Name: 2714, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9416761, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1913 { .Name: 160, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9531450, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1914 { .Name: 553, .SubRegs: 5357, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 9580603, .RegUnitLaneMasks: 263, .IsConstant: 0, .IsArtificial: 0 },
1915 { .Name: 254, .SubRegs: 6042, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 10743838, .RegUnitLaneMasks: 219, .IsConstant: 0, .IsArtificial: 0 },
1916 { .Name: 641, .SubRegs: 759, .SuperRegs: 1300, .SubRegIndices: 128, .RegUnits: 17920030, .RegUnitLaneMasks: 85, .IsConstant: 0, .IsArtificial: 0 },
1917 { .Name: 660, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997278, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1918 { .Name: 916, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997279, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1919 { .Name: 1226, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997280, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1920 { .Name: 1489, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997281, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1921 { .Name: 1806, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997282, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1922 { .Name: 2027, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997283, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1923 { .Name: 2306, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997284, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1924 { .Name: 2556, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997285, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1925 { .Name: 2820, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997286, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1926 { .Name: 26, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997287, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1927 { .Name: 358, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997288, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1928 { .Name: 744, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997289, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1929 { .Name: 993, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997290, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1930 { .Name: 1307, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997291, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1931 { .Name: 1562, .SubRegs: 8243, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 4997292, .RegUnitLaneMasks: 275, .IsConstant: 0, .IsArtificial: 0 },
1932 { .Name: 274, .SubRegs: 8238, .SuperRegs: 5, .SubRegIndices: 102, .RegUnits: 33734814, .RegUnitLaneMasks: 55, .IsConstant: 0, .IsArtificial: 0 },
1933 { .Name: 679, .SubRegs: 9234, .SuperRegs: 1288, .SubRegIndices: 184, .RegUnits: 25104414, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1934 { .Name: 934, .SubRegs: 9234, .SuperRegs: 8656, .SubRegIndices: 184, .RegUnits: 25063455, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1935 { .Name: 1243, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 25022496, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1936 { .Name: 1506, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 24981537, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1937 { .Name: 1823, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 24940578, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1938 { .Name: 2044, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 24899619, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1939 { .Name: 2323, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 24858660, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1940 { .Name: 2573, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 24707109, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1941 { .Name: 2837, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 24653862, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1942 { .Name: 45, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 23076903, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1943 { .Name: 378, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 23023656, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1944 { .Name: 765, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22970409, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1945 { .Name: 1015, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22917162, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1946 { .Name: 1329, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22863915, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1947 { .Name: 1584, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22810668, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1948 { .Name: 1888, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22757421, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1949 { .Name: 2103, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22372398, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1950 { .Name: 2406, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22319151, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1951 { .Name: 2638, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22265904, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1952 { .Name: 116, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22212657, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1953 { .Name: 477, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22159410, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1954 { .Name: 852, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22106163, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1955 { .Name: 1131, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 22052916, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1956 { .Name: 1418, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21901365, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1957 { .Name: 1703, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21848118, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1958 { .Name: 1956, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21794871, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1959 { .Name: 2203, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21741624, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1960 { .Name: 2474, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21688377, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1961 { .Name: 2738, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21635130, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1962 { .Name: 184, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21581883, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1963 { .Name: 577, .SubRegs: 9234, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 21270588, .RegUnitLaneMasks: 277, .IsConstant: 0, .IsArtificial: 0 },
1964 { .Name: 294, .SubRegs: 9254, .SuperRegs: 1270, .SubRegIndices: 184, .RegUnits: 35676190, .RegUnitLaneMasks: 7, .IsConstant: 0, .IsArtificial: 0 },
1965 { .Name: 1237, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 16003102, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1966 { .Name: 1500, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 15921183, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1967 { .Name: 1817, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 15839264, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1968 { .Name: 2038, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 15757345, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1969 { .Name: 2317, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 15675426, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1970 { .Name: 2567, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 15593507, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1971 { .Name: 2831, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 15511588, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1972 { .Name: 39, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12578853, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1973 { .Name: 372, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12496934, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1974 { .Name: 758, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12415015, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1975 { .Name: 1007, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12333096, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1976 { .Name: 1321, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12251177, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1977 { .Name: 1576, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12169258, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1978 { .Name: 1880, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12087339, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1979 { .Name: 2095, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 12005420, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1980 { .Name: 2398, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11923501, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1981 { .Name: 2630, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11841582, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1982 { .Name: 108, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11759663, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1983 { .Name: 469, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11677744, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1984 { .Name: 844, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11595825, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1985 { .Name: 1123, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11513906, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1986 { .Name: 1410, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11431987, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1987 { .Name: 1695, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11350068, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1988 { .Name: 1948, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11268149, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1989 { .Name: 2195, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11186230, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1990 { .Name: 2466, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11104311, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1991 { .Name: 2730, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 11022392, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1992 { .Name: 176, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 10940473, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1993 { .Name: 569, .SubRegs: 396, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 10858554, .RegUnitLaneMasks: 322, .IsConstant: 0, .IsArtificial: 0 },
1994 { .Name: 286, .SubRegs: 444, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 16207902, .RegUnitLaneMasks: 357, .IsConstant: 0, .IsArtificial: 0 },
1995 { .Name: 671, .SubRegs: 108, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 20856862, .RegUnitLaneMasks: 287, .IsConstant: 0, .IsArtificial: 0 },
1996 { .Name: 927, .SubRegs: 252, .SuperRegs: 9232, .SubRegIndices: 235, .RegUnits: 35233822, .RegUnitLaneMasks: 17, .IsConstant: 0, .IsArtificial: 0 },
1997 { .Name: 931, .SubRegs: 5203, .SuperRegs: 8704, .SubRegIndices: 203, .RegUnits: 20643870, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
1998 { .Name: 1240, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 20582431, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
1999 { .Name: 1503, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 20520992, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2000 { .Name: 1820, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 20459553, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2001 { .Name: 2041, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 20398114, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2002 { .Name: 2320, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 20336675, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2003 { .Name: 2570, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 20275236, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2004 { .Name: 2834, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 20181029, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2005 { .Name: 42, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17858598, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2006 { .Name: 375, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17797159, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2007 { .Name: 761, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17670184, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2008 { .Name: 1011, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17608745, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2009 { .Name: 1325, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17547306, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2010 { .Name: 1580, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17485867, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2011 { .Name: 1884, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17424428, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2012 { .Name: 2099, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17362989, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2013 { .Name: 2402, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17301550, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2014 { .Name: 2634, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17240111, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2015 { .Name: 112, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17178672, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2016 { .Name: 473, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17117233, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2017 { .Name: 848, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 17055794, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2018 { .Name: 1127, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16994355, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2019 { .Name: 1414, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16932916, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2020 { .Name: 1699, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16871477, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2021 { .Name: 1952, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16810038, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2022 { .Name: 2199, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16748599, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2023 { .Name: 2470, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16687160, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2024 { .Name: 2734, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16625721, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2025 { .Name: 180, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16564282, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2026 { .Name: 573, .SubRegs: 5203, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 16502843, .RegUnitLaneMasks: 342, .IsConstant: 0, .IsArtificial: 0 },
2027 { .Name: 290, .SubRegs: 5236, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 21037086, .RegUnitLaneMasks: 307, .IsConstant: 0, .IsArtificial: 0 },
2028 { .Name: 675, .SubRegs: 684, .SuperRegs: 1303, .SubRegIndices: 203, .RegUnits: 35504158, .RegUnitLaneMasks: 37, .IsConstant: 0, .IsArtificial: 0 },
2029 { .Name: 4191, .SubRegs: 1186, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9695233, .RegUnitLaneMasks: 393, .IsConstant: 0, .IsArtificial: 0 },
2030 { .Name: 2338, .SubRegs: 1153, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629902, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2031 { .Name: 2852, .SubRegs: 1120, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629904, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2032 { .Name: 398, .SubRegs: 1087, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629906, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2033 { .Name: 1035, .SubRegs: 1054, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629908, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2034 { .Name: 1604, .SubRegs: 1021, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629910, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2035 { .Name: 2123, .SubRegs: 988, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629912, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2036 { .Name: 2658, .SubRegs: 955, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629914, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2037 { .Name: 497, .SubRegs: 922, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629916, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2038 { .Name: 1151, .SubRegs: 889, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629918, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2039 { .Name: 1723, .SubRegs: 856, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629920, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2040 { .Name: 2223, .SubRegs: 823, .SuperRegs: 5, .SubRegIndices: 282, .RegUnits: 9629922, .RegUnitLaneMasks: 377, .IsConstant: 0, .IsArtificial: 0 },
2041 { .Name: 4248, .SubRegs: 96, .SuperRegs: 8241, .SubRegIndices: 23, .RegUnits: 26333190, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2042 { .Name: 690, .SubRegs: 1219, .SuperRegs: 795, .SubRegIndices: 23, .RegUnits: 4997326, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2043 { .Name: 1254, .SubRegs: 1222, .SuperRegs: 1311, .SubRegIndices: 23, .RegUnits: 4997328, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2044 { .Name: 1832, .SubRegs: 1225, .SuperRegs: 1336, .SubRegIndices: 23, .RegUnits: 4997330, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2045 { .Name: 2332, .SubRegs: 1228, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997332, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2046 { .Name: 2846, .SubRegs: 1231, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997334, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2047 { .Name: 390, .SubRegs: 1234, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997336, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2048 { .Name: 1027, .SubRegs: 1237, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997338, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2049 { .Name: 1596, .SubRegs: 1240, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997340, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2050 { .Name: 2115, .SubRegs: 1243, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997342, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2051 { .Name: 2650, .SubRegs: 1246, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997344, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2052 { .Name: 489, .SubRegs: 1249, .SuperRegs: 1362, .SubRegIndices: 23, .RegUnits: 4997346, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2053 { .Name: 1143, .SubRegs: 1252, .SuperRegs: 3929, .SubRegIndices: 23, .RegUnits: 4997348, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2054 { .Name: 1715, .SubRegs: 1255, .SuperRegs: 5064, .SubRegIndices: 23, .RegUnits: 4997350, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2055 { .Name: 2215, .SubRegs: 1258, .SuperRegs: 7003, .SubRegIndices: 23, .RegUnits: 4997352, .RegUnitLaneMasks: 103, .IsConstant: 0, .IsArtificial: 0 },
2056 { .Name: 2750, .SubRegs: 1261, .SuperRegs: 785, .SubRegIndices: 23, .RegUnits: 37986305, .RegUnitLaneMasks: 101, .IsConstant: 0, .IsArtificial: 0 },
2057 { .Name: 4256, .SubRegs: 9408, .SuperRegs: 5, .SubRegIndices: 314, .RegUnits: 20717574, .RegUnitLaneMasks: 413, .IsConstant: 0, .IsArtificial: 0 },
2058 { .Name: 4215, .SubRegs: 9276, .SuperRegs: 786, .SubRegIndices: 314, .RegUnits: 35414017, .RegUnitLaneMasks: 97, .IsConstant: 0, .IsArtificial: 0 },
2059 { .Name: 696, .SubRegs: 9388, .SuperRegs: 786, .SubRegIndices: 314, .RegUnits: 20840654, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2060 { .Name: 1260, .SubRegs: 9380, .SuperRegs: 1312, .SubRegIndices: 314, .RegUnits: 20840656, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2061 { .Name: 1838, .SubRegs: 9372, .SuperRegs: 1337, .SubRegIndices: 314, .RegUnits: 20840658, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2062 { .Name: 2356, .SubRegs: 9364, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840660, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2063 { .Name: 2870, .SubRegs: 9356, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840662, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2064 { .Name: 416, .SubRegs: 9348, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840664, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2065 { .Name: 1055, .SubRegs: 9340, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840666, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2066 { .Name: 1626, .SubRegs: 9332, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840668, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2067 { .Name: 2147, .SubRegs: 9324, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840670, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2068 { .Name: 2682, .SubRegs: 9316, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840672, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2069 { .Name: 521, .SubRegs: 9308, .SuperRegs: 1363, .SubRegIndices: 314, .RegUnits: 20840674, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2070 { .Name: 1175, .SubRegs: 9300, .SuperRegs: 3930, .SubRegIndices: 314, .RegUnits: 20840676, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2071 { .Name: 1747, .SubRegs: 9292, .SuperRegs: 5065, .SubRegIndices: 314, .RegUnits: 20840678, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2072 { .Name: 2247, .SubRegs: 9284, .SuperRegs: 7004, .SubRegIndices: 314, .RegUnits: 20840680, .RegUnitLaneMasks: 409, .IsConstant: 0, .IsArtificial: 0 },
2073 { .Name: 710, .SubRegs: 9181, .SuperRegs: 1294, .SubRegIndices: 321, .RegUnits: 24592414, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2074 { .Name: 958, .SubRegs: 9181, .SuperRegs: 8662, .SubRegIndices: 321, .RegUnits: 24543263, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2075 { .Name: 1272, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24494112, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2076 { .Name: 1527, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24444961, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2077 { .Name: 1850, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24395810, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2078 { .Name: 2065, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24346659, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2079 { .Name: 2368, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24297508, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2080 { .Name: 2600, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24248357, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2081 { .Name: 2888, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24199206, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2082 { .Name: 77, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24150055, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2083 { .Name: 430, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24100904, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2084 { .Name: 792, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24051753, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2085 { .Name: 1071, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 24002602, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2086 { .Name: 1371, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23953451, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2087 { .Name: 1656, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23904300, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2088 { .Name: 1916, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23855149, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2089 { .Name: 2163, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23805998, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2090 { .Name: 2434, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23756847, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2091 { .Name: 2698, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23707696, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2092 { .Name: 144, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23658545, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2093 { .Name: 537, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23609394, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2094 { .Name: 880, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23560243, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2095 { .Name: 1191, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23511092, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2096 { .Name: 1446, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23461941, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2097 { .Name: 1763, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23412790, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2098 { .Name: 1984, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23363639, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2099 { .Name: 2263, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23314488, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2100 { .Name: 2526, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23265337, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2101 { .Name: 2790, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23216186, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2102 { .Name: 232, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23167035, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2103 { .Name: 597, .SubRegs: 9181, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 23117884, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2104 { .Name: 324, .SubRegs: 9206, .SuperRegs: 1276, .SubRegIndices: 321, .RegUnits: 35717150, .RegUnitLaneMasks: 113, .IsConstant: 0, .IsArtificial: 0 },
2105 { .Name: 1266, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 15413278, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2106 { .Name: 1521, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 15314975, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2107 { .Name: 1844, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 15216672, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2108 { .Name: 2059, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 15118369, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2109 { .Name: 2362, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 15020066, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2110 { .Name: 2594, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14921763, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2111 { .Name: 2882, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14823460, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2112 { .Name: 71, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14725157, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2113 { .Name: 424, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14626854, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2114 { .Name: 785, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14528551, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2115 { .Name: 1063, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14430248, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2116 { .Name: 1363, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14331945, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2117 { .Name: 1648, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14233642, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2118 { .Name: 1908, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14135339, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2119 { .Name: 2155, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 14037036, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2120 { .Name: 2426, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13938733, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2121 { .Name: 2690, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13840430, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2122 { .Name: 136, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13742127, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2123 { .Name: 529, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13643824, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2124 { .Name: 872, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13545521, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2125 { .Name: 1183, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13447218, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2126 { .Name: 1438, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13348915, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2127 { .Name: 1755, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13250612, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2128 { .Name: 1976, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13152309, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2129 { .Name: 2255, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 13054006, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2130 { .Name: 2518, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 12955703, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2131 { .Name: 2782, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 12857400, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2132 { .Name: 224, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 12759097, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2133 { .Name: 589, .SubRegs: 526, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 12660794, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2134 { .Name: 316, .SubRegs: 588, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 16289822, .RegUnitLaneMasks: 513, .IsConstant: 0, .IsArtificial: 0 },
2135 { .Name: 702, .SubRegs: 156, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 20938782, .RegUnitLaneMasks: 429, .IsConstant: 0, .IsArtificial: 0 },
2136 { .Name: 951, .SubRegs: 300, .SuperRegs: 5, .SubRegIndices: 386, .RegUnits: 35315742, .RegUnitLaneMasks: 125, .IsConstant: 0, .IsArtificial: 0 },
2137 { .Name: 955, .SubRegs: 5472, .SuperRegs: 8707, .SubRegIndices: 345, .RegUnits: 20107294, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2138 { .Name: 1269, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 20033567, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2139 { .Name: 1524, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19959840, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2140 { .Name: 1847, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19886113, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2141 { .Name: 2062, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19812386, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2142 { .Name: 2365, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19738659, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2143 { .Name: 2597, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19664932, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2144 { .Name: 2885, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19591205, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2145 { .Name: 74, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19517478, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2146 { .Name: 427, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19443751, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2147 { .Name: 788, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19370024, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2148 { .Name: 1067, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19296297, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2149 { .Name: 1367, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19222570, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2150 { .Name: 1652, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19148843, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2151 { .Name: 1912, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19075116, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2152 { .Name: 2159, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 19001389, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2153 { .Name: 2430, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18927662, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2154 { .Name: 2694, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18853935, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2155 { .Name: 140, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18780208, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2156 { .Name: 533, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18706481, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2157 { .Name: 876, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18632754, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2158 { .Name: 1187, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18559027, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2159 { .Name: 1442, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18485300, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2160 { .Name: 1759, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18411573, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2161 { .Name: 1980, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18337846, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2162 { .Name: 2259, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18264119, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2163 { .Name: 2522, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18190392, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2164 { .Name: 2786, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18116665, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2165 { .Name: 228, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 18042938, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2166 { .Name: 593, .SubRegs: 5472, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 17969211, .RegUnitLaneMasks: 495, .IsConstant: 0, .IsArtificial: 0 },
2167 { .Name: 320, .SubRegs: 5514, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 21098526, .RegUnitLaneMasks: 453, .IsConstant: 0, .IsArtificial: 0 },
2168 { .Name: 706, .SubRegs: 717, .SuperRegs: 1279, .SubRegIndices: 345, .RegUnits: 35565598, .RegUnitLaneMasks: 149, .IsConstant: 0, .IsArtificial: 0 },
2169 { .Name: 1454, .SubRegs: 8811, .SuperRegs: 8241, .SubRegIndices: 106, .RegUnits: 28233774, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2170 { .Name: 1771, .SubRegs: 8811, .SuperRegs: 8241, .SubRegIndices: 106, .RegUnits: 28184623, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2171 { .Name: 1992, .SubRegs: 8811, .SuperRegs: 8241, .SubRegIndices: 106, .RegUnits: 28135472, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2172 { .Name: 2271, .SubRegs: 8811, .SuperRegs: 8241, .SubRegIndices: 106, .RegUnits: 28086321, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2173 { .Name: 2494, .SubRegs: 8811, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 28037170, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2174 { .Name: 2758, .SubRegs: 8811, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 27988019, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2175 { .Name: 200, .SubRegs: 8811, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 27938868, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2176 { .Name: 605, .SubRegs: 8811, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 27889717, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2177 { .Name: 2588, .SubRegs: 8788, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 28626974, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2178 { .Name: 2876, .SubRegs: 8788, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 28577823, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2179 { .Name: 64, .SubRegs: 8788, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 28528672, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2180 { .Name: 438, .SubRegs: 8788, .SuperRegs: 7054, .SubRegIndices: 106, .RegUnits: 28479521, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2181 { .Name: 800, .SubRegs: 8788, .SuperRegs: 6461, .SubRegIndices: 106, .RegUnits: 28430370, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2182 { .Name: 1079, .SubRegs: 8788, .SuperRegs: 6461, .SubRegIndices: 106, .RegUnits: 28381219, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2183 { .Name: 1379, .SubRegs: 8788, .SuperRegs: 6461, .SubRegIndices: 106, .RegUnits: 28332068, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2184 { .Name: 1664, .SubRegs: 8788, .SuperRegs: 6461, .SubRegIndices: 106, .RegUnits: 28282917, .RegUnitLaneMasks: 417, .IsConstant: 0, .IsArtificial: 0 },
2185 { .Name: 2502, .SubRegs: 6335, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25456686, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2186 { .Name: 2766, .SubRegs: 6335, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25358383, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2187 { .Name: 208, .SubRegs: 6335, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25260080, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2188 { .Name: 613, .SubRegs: 6335, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25161777, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2189 { .Name: 807, .SubRegs: 6382, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25849886, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2190 { .Name: 1086, .SubRegs: 6382, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25751583, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2191 { .Name: 1349, .SubRegs: 6382, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25653280, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2192 { .Name: 1634, .SubRegs: 6382, .SuperRegs: 5, .SubRegIndices: 447, .RegUnits: 25554977, .RegUnitLaneMasks: 471, .IsConstant: 0, .IsArtificial: 0 },
2193};
2194
2195extern const MCPhysReg AArch64RegUnitRoots[][2] = {
2196 { AArch64::FFR },
2197 { AArch64::W29 },
2198 { AArch64::W29_HI },
2199 { AArch64::FPCR },
2200 { AArch64::FPMR },
2201 { AArch64::FPSR },
2202 { AArch64::W30 },
2203 { AArch64::W30_HI },
2204 { AArch64::NZCV },
2205 { AArch64::WSP },
2206 { AArch64::WSP_HI },
2207 { AArch64::VG },
2208 { AArch64::WZR },
2209 { AArch64::WZR_HI },
2210 { AArch64::ZAQ0 },
2211 { AArch64::ZAQ8 },
2212 { AArch64::ZAQ4 },
2213 { AArch64::ZAQ12 },
2214 { AArch64::ZAQ2 },
2215 { AArch64::ZAQ10 },
2216 { AArch64::ZAQ6 },
2217 { AArch64::ZAQ14 },
2218 { AArch64::ZAQ1 },
2219 { AArch64::ZAQ9 },
2220 { AArch64::ZAQ5 },
2221 { AArch64::ZAQ13 },
2222 { AArch64::ZAQ3 },
2223 { AArch64::ZAQ11 },
2224 { AArch64::ZAQ7 },
2225 { AArch64::ZAQ15 },
2226 { AArch64::B0 },
2227 { AArch64::B1 },
2228 { AArch64::B2 },
2229 { AArch64::B3 },
2230 { AArch64::B4 },
2231 { AArch64::B5 },
2232 { AArch64::B6 },
2233 { AArch64::B7 },
2234 { AArch64::B8 },
2235 { AArch64::B9 },
2236 { AArch64::B10 },
2237 { AArch64::B11 },
2238 { AArch64::B12 },
2239 { AArch64::B13 },
2240 { AArch64::B14 },
2241 { AArch64::B15 },
2242 { AArch64::B16 },
2243 { AArch64::B17 },
2244 { AArch64::B18 },
2245 { AArch64::B19 },
2246 { AArch64::B20 },
2247 { AArch64::B21 },
2248 { AArch64::B22 },
2249 { AArch64::B23 },
2250 { AArch64::B24 },
2251 { AArch64::B25 },
2252 { AArch64::B26 },
2253 { AArch64::B27 },
2254 { AArch64::B28 },
2255 { AArch64::B29 },
2256 { AArch64::B30 },
2257 { AArch64::B31 },
2258 { AArch64::B0_HI },
2259 { AArch64::H0_HI },
2260 { AArch64::S0_HI },
2261 { AArch64::B1_HI },
2262 { AArch64::H1_HI },
2263 { AArch64::S1_HI },
2264 { AArch64::B2_HI },
2265 { AArch64::H2_HI },
2266 { AArch64::S2_HI },
2267 { AArch64::B3_HI },
2268 { AArch64::H3_HI },
2269 { AArch64::S3_HI },
2270 { AArch64::B4_HI },
2271 { AArch64::H4_HI },
2272 { AArch64::S4_HI },
2273 { AArch64::B5_HI },
2274 { AArch64::H5_HI },
2275 { AArch64::S5_HI },
2276 { AArch64::B6_HI },
2277 { AArch64::H6_HI },
2278 { AArch64::S6_HI },
2279 { AArch64::B7_HI },
2280 { AArch64::H7_HI },
2281 { AArch64::S7_HI },
2282 { AArch64::B8_HI },
2283 { AArch64::H8_HI },
2284 { AArch64::S8_HI },
2285 { AArch64::B9_HI },
2286 { AArch64::H9_HI },
2287 { AArch64::S9_HI },
2288 { AArch64::B10_HI },
2289 { AArch64::H10_HI },
2290 { AArch64::S10_HI },
2291 { AArch64::B11_HI },
2292 { AArch64::H11_HI },
2293 { AArch64::S11_HI },
2294 { AArch64::B12_HI },
2295 { AArch64::H12_HI },
2296 { AArch64::S12_HI },
2297 { AArch64::B13_HI },
2298 { AArch64::H13_HI },
2299 { AArch64::S13_HI },
2300 { AArch64::B14_HI },
2301 { AArch64::H14_HI },
2302 { AArch64::S14_HI },
2303 { AArch64::B15_HI },
2304 { AArch64::H15_HI },
2305 { AArch64::S15_HI },
2306 { AArch64::B16_HI },
2307 { AArch64::H16_HI },
2308 { AArch64::S16_HI },
2309 { AArch64::B17_HI },
2310 { AArch64::H17_HI },
2311 { AArch64::S17_HI },
2312 { AArch64::B18_HI },
2313 { AArch64::H18_HI },
2314 { AArch64::S18_HI },
2315 { AArch64::B19_HI },
2316 { AArch64::H19_HI },
2317 { AArch64::S19_HI },
2318 { AArch64::B20_HI },
2319 { AArch64::H20_HI },
2320 { AArch64::S20_HI },
2321 { AArch64::B21_HI },
2322 { AArch64::H21_HI },
2323 { AArch64::S21_HI },
2324 { AArch64::B22_HI },
2325 { AArch64::H22_HI },
2326 { AArch64::S22_HI },
2327 { AArch64::B23_HI },
2328 { AArch64::H23_HI },
2329 { AArch64::S23_HI },
2330 { AArch64::B24_HI },
2331 { AArch64::H24_HI },
2332 { AArch64::S24_HI },
2333 { AArch64::B25_HI },
2334 { AArch64::H25_HI },
2335 { AArch64::S25_HI },
2336 { AArch64::B26_HI },
2337 { AArch64::H26_HI },
2338 { AArch64::S26_HI },
2339 { AArch64::B27_HI },
2340 { AArch64::H27_HI },
2341 { AArch64::S27_HI },
2342 { AArch64::B28_HI },
2343 { AArch64::H28_HI },
2344 { AArch64::S28_HI },
2345 { AArch64::B29_HI },
2346 { AArch64::H29_HI },
2347 { AArch64::S29_HI },
2348 { AArch64::B30_HI },
2349 { AArch64::H30_HI },
2350 { AArch64::S30_HI },
2351 { AArch64::B31_HI },
2352 { AArch64::H31_HI },
2353 { AArch64::S31_HI },
2354 { AArch64::PN0 },
2355 { AArch64::PN1 },
2356 { AArch64::PN2 },
2357 { AArch64::PN3 },
2358 { AArch64::PN4 },
2359 { AArch64::PN5 },
2360 { AArch64::PN6 },
2361 { AArch64::PN7 },
2362 { AArch64::PN8 },
2363 { AArch64::PN9 },
2364 { AArch64::PN10 },
2365 { AArch64::PN11 },
2366 { AArch64::PN12 },
2367 { AArch64::PN13 },
2368 { AArch64::PN14 },
2369 { AArch64::PN15 },
2370 { AArch64::D0_HI },
2371 { AArch64::D1_HI },
2372 { AArch64::D2_HI },
2373 { AArch64::D3_HI },
2374 { AArch64::D4_HI },
2375 { AArch64::D5_HI },
2376 { AArch64::D6_HI },
2377 { AArch64::D7_HI },
2378 { AArch64::D8_HI },
2379 { AArch64::D9_HI },
2380 { AArch64::D10_HI },
2381 { AArch64::D11_HI },
2382 { AArch64::D12_HI },
2383 { AArch64::D13_HI },
2384 { AArch64::D14_HI },
2385 { AArch64::D15_HI },
2386 { AArch64::D16_HI },
2387 { AArch64::D17_HI },
2388 { AArch64::D18_HI },
2389 { AArch64::D19_HI },
2390 { AArch64::D20_HI },
2391 { AArch64::D21_HI },
2392 { AArch64::D22_HI },
2393 { AArch64::D23_HI },
2394 { AArch64::D24_HI },
2395 { AArch64::D25_HI },
2396 { AArch64::D26_HI },
2397 { AArch64::D27_HI },
2398 { AArch64::D28_HI },
2399 { AArch64::D29_HI },
2400 { AArch64::D30_HI },
2401 { AArch64::D31_HI },
2402 { AArch64::W0 },
2403 { AArch64::W1 },
2404 { AArch64::W2 },
2405 { AArch64::W3 },
2406 { AArch64::W4 },
2407 { AArch64::W5 },
2408 { AArch64::W6 },
2409 { AArch64::W7 },
2410 { AArch64::W8 },
2411 { AArch64::W9 },
2412 { AArch64::W10 },
2413 { AArch64::W11 },
2414 { AArch64::W12 },
2415 { AArch64::W13 },
2416 { AArch64::W14 },
2417 { AArch64::W15 },
2418 { AArch64::W16 },
2419 { AArch64::W17 },
2420 { AArch64::W18 },
2421 { AArch64::W19 },
2422 { AArch64::W20 },
2423 { AArch64::W21 },
2424 { AArch64::W22 },
2425 { AArch64::W23 },
2426 { AArch64::W24 },
2427 { AArch64::W25 },
2428 { AArch64::W26 },
2429 { AArch64::W27 },
2430 { AArch64::W28 },
2431 { AArch64::W0_HI },
2432 { AArch64::W1_HI },
2433 { AArch64::W2_HI },
2434 { AArch64::W3_HI },
2435 { AArch64::W4_HI },
2436 { AArch64::W5_HI },
2437 { AArch64::W6_HI },
2438 { AArch64::W7_HI },
2439 { AArch64::W8_HI },
2440 { AArch64::W9_HI },
2441 { AArch64::W10_HI },
2442 { AArch64::W11_HI },
2443 { AArch64::W12_HI },
2444 { AArch64::W13_HI },
2445 { AArch64::W14_HI },
2446 { AArch64::W15_HI },
2447 { AArch64::W16_HI },
2448 { AArch64::W17_HI },
2449 { AArch64::W18_HI },
2450 { AArch64::W19_HI },
2451 { AArch64::W20_HI },
2452 { AArch64::W21_HI },
2453 { AArch64::W22_HI },
2454 { AArch64::W23_HI },
2455 { AArch64::W24_HI },
2456 { AArch64::W25_HI },
2457 { AArch64::W26_HI },
2458 { AArch64::W27_HI },
2459 { AArch64::W28_HI },
2460 { AArch64::Q0_HI },
2461 { AArch64::Q1_HI },
2462 { AArch64::Q2_HI },
2463 { AArch64::Q3_HI },
2464 { AArch64::Q4_HI },
2465 { AArch64::Q5_HI },
2466 { AArch64::Q6_HI },
2467 { AArch64::Q7_HI },
2468 { AArch64::Q8_HI },
2469 { AArch64::Q9_HI },
2470 { AArch64::Q10_HI },
2471 { AArch64::Q11_HI },
2472 { AArch64::Q12_HI },
2473 { AArch64::Q13_HI },
2474 { AArch64::Q14_HI },
2475 { AArch64::Q15_HI },
2476 { AArch64::Q16_HI },
2477 { AArch64::Q17_HI },
2478 { AArch64::Q18_HI },
2479 { AArch64::Q19_HI },
2480 { AArch64::Q20_HI },
2481 { AArch64::Q21_HI },
2482 { AArch64::Q22_HI },
2483 { AArch64::Q23_HI },
2484 { AArch64::Q24_HI },
2485 { AArch64::Q25_HI },
2486 { AArch64::Q26_HI },
2487 { AArch64::Q27_HI },
2488 { AArch64::Q28_HI },
2489 { AArch64::Q29_HI },
2490 { AArch64::Q30_HI },
2491 { AArch64::Q31_HI },
2492 { AArch64::ZT0 },
2493};
2494
2495namespace {
2496
2497// Register classes...
2498 // W_HI_DummyRC Register Class...
2499 const MCPhysReg W_HI_DummyRC[] = {
2500 AArch64::W0_HI, AArch64::W1_HI, AArch64::W2_HI, AArch64::W3_HI, AArch64::W4_HI, AArch64::W5_HI, AArch64::W6_HI, AArch64::W7_HI, AArch64::W8_HI, AArch64::W9_HI, AArch64::W10_HI, AArch64::W11_HI, AArch64::W12_HI, AArch64::W13_HI, AArch64::W14_HI, AArch64::W15_HI, AArch64::W16_HI, AArch64::W17_HI, AArch64::W18_HI, AArch64::W19_HI, AArch64::W20_HI, AArch64::W21_HI, AArch64::W22_HI, AArch64::W23_HI, AArch64::W24_HI, AArch64::W25_HI, AArch64::W26_HI, AArch64::W27_HI, AArch64::W28_HI, AArch64::W29_HI, AArch64::W30_HI, AArch64::WZR_HI, AArch64::WSP_HI,
2501 };
2502
2503 // W_HI_DummyRC Bit set.
2504 const uint8_t W_HI_DummyRCBits[] = {
2505 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2506 };
2507
2508 // B_HI_DummyRC Register Class...
2509 const MCPhysReg B_HI_DummyRC[] = {
2510 AArch64::B0_HI, AArch64::B1_HI, AArch64::B2_HI, AArch64::B3_HI, AArch64::B4_HI, AArch64::B5_HI, AArch64::B6_HI, AArch64::B7_HI, AArch64::B8_HI, AArch64::B9_HI, AArch64::B10_HI, AArch64::B11_HI, AArch64::B12_HI, AArch64::B13_HI, AArch64::B14_HI, AArch64::B15_HI, AArch64::B16_HI, AArch64::B17_HI, AArch64::B18_HI, AArch64::B19_HI, AArch64::B20_HI, AArch64::B21_HI, AArch64::B22_HI, AArch64::B23_HI, AArch64::B24_HI, AArch64::B25_HI, AArch64::B26_HI, AArch64::B27_HI, AArch64::B28_HI, AArch64::B29_HI, AArch64::B30_HI, AArch64::B31_HI,
2511 };
2512
2513 // B_HI_DummyRC Bit set.
2514 const uint8_t B_HI_DummyRCBits[] = {
2515 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2516 };
2517
2518 // D_HI_DummyRC Register Class...
2519 const MCPhysReg D_HI_DummyRC[] = {
2520 AArch64::D0_HI, AArch64::D1_HI, AArch64::D2_HI, AArch64::D3_HI, AArch64::D4_HI, AArch64::D5_HI, AArch64::D6_HI, AArch64::D7_HI, AArch64::D8_HI, AArch64::D9_HI, AArch64::D10_HI, AArch64::D11_HI, AArch64::D12_HI, AArch64::D13_HI, AArch64::D14_HI, AArch64::D15_HI, AArch64::D16_HI, AArch64::D17_HI, AArch64::D18_HI, AArch64::D19_HI, AArch64::D20_HI, AArch64::D21_HI, AArch64::D22_HI, AArch64::D23_HI, AArch64::D24_HI, AArch64::D25_HI, AArch64::D26_HI, AArch64::D27_HI, AArch64::D28_HI, AArch64::D29_HI, AArch64::D30_HI, AArch64::D31_HI,
2521 };
2522
2523 // D_HI_DummyRC Bit set.
2524 const uint8_t D_HI_DummyRCBits[] = {
2525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2526 };
2527
2528 // H_HI_DummyRC Register Class...
2529 const MCPhysReg H_HI_DummyRC[] = {
2530 AArch64::H0_HI, AArch64::H1_HI, AArch64::H2_HI, AArch64::H3_HI, AArch64::H4_HI, AArch64::H5_HI, AArch64::H6_HI, AArch64::H7_HI, AArch64::H8_HI, AArch64::H9_HI, AArch64::H10_HI, AArch64::H11_HI, AArch64::H12_HI, AArch64::H13_HI, AArch64::H14_HI, AArch64::H15_HI, AArch64::H16_HI, AArch64::H17_HI, AArch64::H18_HI, AArch64::H19_HI, AArch64::H20_HI, AArch64::H21_HI, AArch64::H22_HI, AArch64::H23_HI, AArch64::H24_HI, AArch64::H25_HI, AArch64::H26_HI, AArch64::H27_HI, AArch64::H28_HI, AArch64::H29_HI, AArch64::H30_HI, AArch64::H31_HI,
2531 };
2532
2533 // H_HI_DummyRC Bit set.
2534 const uint8_t H_HI_DummyRCBits[] = {
2535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2536 };
2537
2538 // Q_HI_DummyRC Register Class...
2539 const MCPhysReg Q_HI_DummyRC[] = {
2540 AArch64::Q0_HI, AArch64::Q1_HI, AArch64::Q2_HI, AArch64::Q3_HI, AArch64::Q4_HI, AArch64::Q5_HI, AArch64::Q6_HI, AArch64::Q7_HI, AArch64::Q8_HI, AArch64::Q9_HI, AArch64::Q10_HI, AArch64::Q11_HI, AArch64::Q12_HI, AArch64::Q13_HI, AArch64::Q14_HI, AArch64::Q15_HI, AArch64::Q16_HI, AArch64::Q17_HI, AArch64::Q18_HI, AArch64::Q19_HI, AArch64::Q20_HI, AArch64::Q21_HI, AArch64::Q22_HI, AArch64::Q23_HI, AArch64::Q24_HI, AArch64::Q25_HI, AArch64::Q26_HI, AArch64::Q27_HI, AArch64::Q28_HI, AArch64::Q29_HI, AArch64::Q30_HI, AArch64::Q31_HI,
2541 };
2542
2543 // Q_HI_DummyRC Bit set.
2544 const uint8_t Q_HI_DummyRCBits[] = {
2545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2546 };
2547
2548 // S_HI_DummyRC Register Class...
2549 const MCPhysReg S_HI_DummyRC[] = {
2550 AArch64::S0_HI, AArch64::S1_HI, AArch64::S2_HI, AArch64::S3_HI, AArch64::S4_HI, AArch64::S5_HI, AArch64::S6_HI, AArch64::S7_HI, AArch64::S8_HI, AArch64::S9_HI, AArch64::S10_HI, AArch64::S11_HI, AArch64::S12_HI, AArch64::S13_HI, AArch64::S14_HI, AArch64::S15_HI, AArch64::S16_HI, AArch64::S17_HI, AArch64::S18_HI, AArch64::S19_HI, AArch64::S20_HI, AArch64::S21_HI, AArch64::S22_HI, AArch64::S23_HI, AArch64::S24_HI, AArch64::S25_HI, AArch64::S26_HI, AArch64::S27_HI, AArch64::S28_HI, AArch64::S29_HI, AArch64::S30_HI, AArch64::S31_HI,
2551 };
2552
2553 // S_HI_DummyRC Bit set.
2554 const uint8_t S_HI_DummyRCBits[] = {
2555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2556 };
2557
2558 // FPR8 Register Class...
2559 const MCPhysReg FPR8[] = {
2560 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31,
2561 };
2562
2563 // FPR8 Bit set.
2564 const uint8_t FPR8Bits[] = {
2565 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2566 };
2567
2568 // FPR16 Register Class...
2569 const MCPhysReg FPR16[] = {
2570 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31,
2571 };
2572
2573 // FPR16 Bit set.
2574 const uint8_t FPR16Bits[] = {
2575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2576 };
2577
2578 // PPRorPNR Register Class...
2579 const MCPhysReg PPRorPNR[] = {
2580 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, AArch64::PN0, AArch64::PN1, AArch64::PN2, AArch64::PN3, AArch64::PN4, AArch64::PN5, AArch64::PN6, AArch64::PN7, AArch64::PN8, AArch64::PN9, AArch64::PN10, AArch64::PN11, AArch64::PN12, AArch64::PN13, AArch64::PN14, AArch64::PN15,
2581 };
2582
2583 // PPRorPNR Bit set.
2584 const uint8_t PPRorPNRBits[] = {
2585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2586 };
2587
2588 // FPR16_lo Register Class...
2589 const MCPhysReg FPR16_lo[] = {
2590 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15,
2591 };
2592
2593 // FPR16_lo Bit set.
2594 const uint8_t FPR16_loBits[] = {
2595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2596 };
2597
2598 // PNR Register Class...
2599 const MCPhysReg PNR[] = {
2600 AArch64::PN0, AArch64::PN1, AArch64::PN2, AArch64::PN3, AArch64::PN4, AArch64::PN5, AArch64::PN6, AArch64::PN7, AArch64::PN8, AArch64::PN9, AArch64::PN10, AArch64::PN11, AArch64::PN12, AArch64::PN13, AArch64::PN14, AArch64::PN15,
2601 };
2602
2603 // PNR Bit set.
2604 const uint8_t PNRBits[] = {
2605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2606 };
2607
2608 // PPR Register Class...
2609 const MCPhysReg PPR[] = {
2610 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15,
2611 };
2612
2613 // PPR Bit set.
2614 const uint8_t PPRBits[] = {
2615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2616 };
2617
2618 // PNR_3b Register Class...
2619 const MCPhysReg PNR_3b[] = {
2620 AArch64::PN0, AArch64::PN1, AArch64::PN2, AArch64::PN3, AArch64::PN4, AArch64::PN5, AArch64::PN6, AArch64::PN7,
2621 };
2622
2623 // PNR_3b Bit set.
2624 const uint8_t PNR_3bBits[] = {
2625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2626 };
2627
2628 // PNR_p8to15 Register Class...
2629 const MCPhysReg PNR_p8to15[] = {
2630 AArch64::PN8, AArch64::PN9, AArch64::PN10, AArch64::PN11, AArch64::PN12, AArch64::PN13, AArch64::PN14, AArch64::PN15,
2631 };
2632
2633 // PNR_p8to15 Bit set.
2634 const uint8_t PNR_p8to15Bits[] = {
2635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2636 };
2637
2638 // PPRMul2 Register Class...
2639 const MCPhysReg PPRMul2[] = {
2640 AArch64::P0, AArch64::P2, AArch64::P4, AArch64::P6, AArch64::P8, AArch64::P10, AArch64::P12, AArch64::P14,
2641 };
2642
2643 // PPRMul2 Bit set.
2644 const uint8_t PPRMul2Bits[] = {
2645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
2646 };
2647
2648 // PPR_3b Register Class...
2649 const MCPhysReg PPR_3b[] = {
2650 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
2651 };
2652
2653 // PPR_3b Bit set.
2654 const uint8_t PPR_3bBits[] = {
2655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2656 };
2657
2658 // PPR_p8to15 Register Class...
2659 const MCPhysReg PPR_p8to15[] = {
2660 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15,
2661 };
2662
2663 // PPR_p8to15 Bit set.
2664 const uint8_t PPR_p8to15Bits[] = {
2665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2666 };
2667
2668 // PPRMul2_and_PPR_3b Register Class...
2669 const MCPhysReg PPRMul2_and_PPR_3b[] = {
2670 AArch64::P0, AArch64::P2, AArch64::P4, AArch64::P6,
2671 };
2672
2673 // PPRMul2_and_PPR_3b Bit set.
2674 const uint8_t PPRMul2_and_PPR_3bBits[] = {
2675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
2676 };
2677
2678 // PPRMul2_and_PPR_p8to15 Register Class...
2679 const MCPhysReg PPRMul2_and_PPR_p8to15[] = {
2680 AArch64::P8, AArch64::P10, AArch64::P12, AArch64::P14,
2681 };
2682
2683 // PPRMul2_and_PPR_p8to15 Bit set.
2684 const uint8_t PPRMul2_and_PPR_p8to15Bits[] = {
2685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
2686 };
2687
2688 // PPR2 Register Class...
2689 const MCPhysReg PPR2[] = {
2690 AArch64::P0_P1, AArch64::P1_P2, AArch64::P2_P3, AArch64::P3_P4, AArch64::P4_P5, AArch64::P5_P6, AArch64::P6_P7, AArch64::P7_P8, AArch64::P8_P9, AArch64::P9_P10, AArch64::P10_P11, AArch64::P11_P12, AArch64::P12_P13, AArch64::P13_P14, AArch64::P14_P15, AArch64::P15_P0,
2691 };
2692
2693 // PPR2 Bit set.
2694 const uint8_t PPR2Bits[] = {
2695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
2696 };
2697
2698 // PPR2Mul2 Register Class...
2699 const MCPhysReg PPR2Mul2[] = {
2700 AArch64::P0_P1, AArch64::P2_P3, AArch64::P4_P5, AArch64::P6_P7, AArch64::P8_P9, AArch64::P10_P11, AArch64::P12_P13, AArch64::P14_P15,
2701 };
2702
2703 // PPR2Mul2 Bit set.
2704 const uint8_t PPR2Mul2Bits[] = {
2705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0x02,
2706 };
2707
2708 // PPR2_with_psub1_in_PPRMul2 Register Class...
2709 const MCPhysReg PPR2_with_psub1_in_PPRMul2[] = {
2710 AArch64::P1_P2, AArch64::P3_P4, AArch64::P5_P6, AArch64::P7_P8, AArch64::P9_P10, AArch64::P11_P12, AArch64::P13_P14, AArch64::P15_P0,
2711 };
2712
2713 // PPR2_with_psub1_in_PPRMul2 Bit set.
2714 const uint8_t PPR2_with_psub1_in_PPRMul2Bits[] = {
2715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x05,
2716 };
2717
2718 // PPR2_with_psub1_in_PPR_3b Register Class...
2719 const MCPhysReg PPR2_with_psub1_in_PPR_3b[] = {
2720 AArch64::P0_P1, AArch64::P1_P2, AArch64::P2_P3, AArch64::P3_P4, AArch64::P4_P5, AArch64::P5_P6, AArch64::P6_P7, AArch64::P15_P0,
2721 };
2722
2723 // PPR2_with_psub1_in_PPR_3b Bit set.
2724 const uint8_t PPR2_with_psub1_in_PPR_3bBits[] = {
2725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x04,
2726 };
2727
2728 // PPR2_with_psub1_in_PPR_p8to15 Register Class...
2729 const MCPhysReg PPR2_with_psub1_in_PPR_p8to15[] = {
2730 AArch64::P7_P8, AArch64::P8_P9, AArch64::P9_P10, AArch64::P10_P11, AArch64::P11_P12, AArch64::P12_P13, AArch64::P13_P14, AArch64::P14_P15,
2731 };
2732
2733 // PPR2_with_psub1_in_PPR_p8to15 Bit set.
2734 const uint8_t PPR2_with_psub1_in_PPR_p8to15Bits[] = {
2735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
2736 };
2737
2738 // PPR2_with_psub_in_PNR_3b Register Class...
2739 const MCPhysReg PPR2_with_psub_in_PNR_3b[] = {
2740 AArch64::P0_P1, AArch64::P1_P2, AArch64::P2_P3, AArch64::P3_P4, AArch64::P4_P5, AArch64::P5_P6, AArch64::P6_P7, AArch64::P7_P8,
2741 };
2742
2743 // PPR2_with_psub_in_PNR_3b Bit set.
2744 const uint8_t PPR2_with_psub_in_PNR_3bBits[] = {
2745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2746 };
2747
2748 // PPR2_with_psub_in_PNR_p8to15 Register Class...
2749 const MCPhysReg PPR2_with_psub_in_PNR_p8to15[] = {
2750 AArch64::P8_P9, AArch64::P9_P10, AArch64::P10_P11, AArch64::P11_P12, AArch64::P12_P13, AArch64::P13_P14, AArch64::P14_P15, AArch64::P15_P0,
2751 };
2752
2753 // PPR2_with_psub_in_PNR_p8to15 Bit set.
2754 const uint8_t PPR2_with_psub_in_PNR_p8to15Bits[] = {
2755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2756 };
2757
2758 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3b Register Class...
2759 const MCPhysReg PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3b[] = {
2760 AArch64::P0_P1, AArch64::P1_P2, AArch64::P2_P3, AArch64::P3_P4, AArch64::P4_P5, AArch64::P5_P6, AArch64::P6_P7,
2761 };
2762
2763 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3b Bit set.
2764 const uint8_t PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3bBits[] = {
2765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2766 };
2767
2768 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15 Register Class...
2769 const MCPhysReg PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15[] = {
2770 AArch64::P8_P9, AArch64::P9_P10, AArch64::P10_P11, AArch64::P11_P12, AArch64::P12_P13, AArch64::P13_P14, AArch64::P14_P15,
2771 };
2772
2773 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15 Bit set.
2774 const uint8_t PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15Bits[] = {
2775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2776 };
2777
2778 // PPR2Mul2_and_PPR2_with_psub_in_PNR_3b Register Class...
2779 const MCPhysReg PPR2Mul2_and_PPR2_with_psub_in_PNR_3b[] = {
2780 AArch64::P0_P1, AArch64::P2_P3, AArch64::P4_P5, AArch64::P6_P7,
2781 };
2782
2783 // PPR2Mul2_and_PPR2_with_psub_in_PNR_3b Bit set.
2784 const uint8_t PPR2Mul2_and_PPR2_with_psub_in_PNR_3bBits[] = {
2785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02,
2786 };
2787
2788 // PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15 Register Class...
2789 const MCPhysReg PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15[] = {
2790 AArch64::P8_P9, AArch64::P10_P11, AArch64::P12_P13, AArch64::P14_P15,
2791 };
2792
2793 // PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15 Bit set.
2794 const uint8_t PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15Bits[] = {
2795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02,
2796 };
2797
2798 // PPR2_with_psub1_in_PPRMul2_and_PPR_3b Register Class...
2799 const MCPhysReg PPR2_with_psub1_in_PPRMul2_and_PPR_3b[] = {
2800 AArch64::P1_P2, AArch64::P3_P4, AArch64::P5_P6, AArch64::P15_P0,
2801 };
2802
2803 // PPR2_with_psub1_in_PPRMul2_and_PPR_3b Bit set.
2804 const uint8_t PPR2_with_psub1_in_PPRMul2_and_PPR_3bBits[] = {
2805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01, 0x04,
2806 };
2807
2808 // PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15 Register Class...
2809 const MCPhysReg PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15[] = {
2810 AArch64::P7_P8, AArch64::P9_P10, AArch64::P11_P12, AArch64::P13_P14,
2811 };
2812
2813 // PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15 Bit set.
2814 const uint8_t PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15Bits[] = {
2815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01,
2816 };
2817
2818 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2 Register Class...
2819 const MCPhysReg PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2[] = {
2820 AArch64::P1_P2, AArch64::P3_P4, AArch64::P5_P6, AArch64::P7_P8,
2821 };
2822
2823 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2 Bit set.
2824 const uint8_t PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2Bits[] = {
2825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x05,
2826 };
2827
2828 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2 Register Class...
2829 const MCPhysReg PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2[] = {
2830 AArch64::P9_P10, AArch64::P11_P12, AArch64::P13_P14, AArch64::P15_P0,
2831 };
2832
2833 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2 Bit set.
2834 const uint8_t PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2Bits[] = {
2835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x05,
2836 };
2837
2838 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3b Register Class...
2839 const MCPhysReg PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3b[] = {
2840 AArch64::P1_P2, AArch64::P3_P4, AArch64::P5_P6,
2841 };
2842
2843 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3b Bit set.
2844 const uint8_t PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3bBits[] = {
2845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01,
2846 };
2847
2848 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15 Register Class...
2849 const MCPhysReg PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15[] = {
2850 AArch64::P9_P10, AArch64::P11_P12, AArch64::P13_P14,
2851 };
2852
2853 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15 Bit set.
2854 const uint8_t PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15Bits[] = {
2855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01,
2856 };
2857
2858 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 Register Class...
2859 const MCPhysReg PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15[] = {
2860 AArch64::P7_P8,
2861 };
2862
2863 // PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 Bit set.
2864 const uint8_t PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15Bits[] = {
2865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2866 };
2867
2868 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3b Register Class...
2869 const MCPhysReg PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3b[] = {
2870 AArch64::P15_P0,
2871 };
2872
2873 // PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3b Bit set.
2874 const uint8_t PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3bBits[] = {
2875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2876 };
2877
2878 // GPR32all Register Class...
2879 const MCPhysReg GPR32all[] = {
2880 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP,
2881 };
2882
2883 // GPR32all Bit set.
2884 const uint8_t GPR32allBits[] = {
2885 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
2886 };
2887
2888 // FPR32 Register Class...
2889 const MCPhysReg FPR32[] = {
2890 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31,
2891 };
2892
2893 // FPR32 Bit set.
2894 const uint8_t FPR32Bits[] = {
2895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
2896 };
2897
2898 // GPR32 Register Class...
2899 const MCPhysReg GPR32[] = {
2900 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR,
2901 };
2902
2903 // GPR32 Bit set.
2904 const uint8_t GPR32Bits[] = {
2905 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
2906 };
2907
2908 // GPR32sp Register Class...
2909 const MCPhysReg GPR32sp[] = {
2910 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP,
2911 };
2912
2913 // GPR32sp Bit set.
2914 const uint8_t GPR32spBits[] = {
2915 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
2916 };
2917
2918 // GPR32common Register Class...
2919 const MCPhysReg GPR32common[] = {
2920 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30,
2921 };
2922
2923 // GPR32common Bit set.
2924 const uint8_t GPR32commonBits[] = {
2925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
2926 };
2927
2928 // FPR32_with_hsub_in_FPR16_lo Register Class...
2929 const MCPhysReg FPR32_with_hsub_in_FPR16_lo[] = {
2930 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15,
2931 };
2932
2933 // FPR32_with_hsub_in_FPR16_lo Bit set.
2934 const uint8_t FPR32_with_hsub_in_FPR16_loBits[] = {
2935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
2936 };
2937
2938 // GPR32arg Register Class...
2939 const MCPhysReg GPR32arg[] = {
2940 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7,
2941 };
2942
2943 // GPR32arg Bit set.
2944 const uint8_t GPR32argBits[] = {
2945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2946 };
2947
2948 // MatrixIndexGPR32_12_15 Register Class...
2949 const MCPhysReg MatrixIndexGPR32_12_15[] = {
2950 AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15,
2951 };
2952
2953 // MatrixIndexGPR32_12_15 Bit set.
2954 const uint8_t MatrixIndexGPR32_12_15Bits[] = {
2955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2956 };
2957
2958 // MatrixIndexGPR32_8_11 Register Class...
2959 const MCPhysReg MatrixIndexGPR32_8_11[] = {
2960 AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11,
2961 };
2962
2963 // MatrixIndexGPR32_8_11 Bit set.
2964 const uint8_t MatrixIndexGPR32_8_11Bits[] = {
2965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
2966 };
2967
2968 // CCR Register Class...
2969 const MCPhysReg CCR[] = {
2970 AArch64::NZCV,
2971 };
2972
2973 // CCR Bit set.
2974 const uint8_t CCRBits[] = {
2975 0x80,
2976 };
2977
2978 // GPR32sponly Register Class...
2979 const MCPhysReg GPR32sponly[] = {
2980 AArch64::WSP,
2981 };
2982
2983 // GPR32sponly Bit set.
2984 const uint8_t GPR32sponlyBits[] = {
2985 0x00, 0x04,
2986 };
2987
2988 // WSeqPairsClass Register Class...
2989 const MCPhysReg WSeqPairsClass[] = {
2990 AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29, AArch64::W30_WZR,
2991 };
2992
2993 // WSeqPairsClass Bit set.
2994 const uint8_t WSeqPairsClassBits[] = {
2995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2996 };
2997
2998 // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2999 const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
3000 AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29,
3001 };
3002
3003 // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
3004 const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
3005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
3006 };
3007
3008 // WSeqPairsClass_with_sube32_in_GPR32arg Register Class...
3009 const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32arg[] = {
3010 AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7,
3011 };
3012
3013 // WSeqPairsClass_with_sube32_in_GPR32arg Bit set.
3014 const uint8_t WSeqPairsClass_with_sube32_in_GPR32argBits[] = {
3015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
3016 };
3017
3018 // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 Register Class...
3019 const MCPhysReg WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15[] = {
3020 AArch64::W12_W13, AArch64::W14_W15,
3021 };
3022
3023 // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 Bit set.
3024 const uint8_t WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15Bits[] = {
3025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
3026 };
3027
3028 // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11 Register Class...
3029 const MCPhysReg WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11[] = {
3030 AArch64::W8_W9, AArch64::W10_W11,
3031 };
3032
3033 // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11 Bit set.
3034 const uint8_t WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11Bits[] = {
3035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
3036 };
3037
3038 // GPR64all Register Class...
3039 const MCPhysReg GPR64all[] = {
3040 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP,
3041 };
3042
3043 // GPR64all Bit set.
3044 const uint8_t GPR64allBits[] = {
3045 0x44, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
3046 };
3047
3048 // FPR64 Register Class...
3049 const MCPhysReg FPR64[] = {
3050 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31,
3051 };
3052
3053 // FPR64 Bit set.
3054 const uint8_t FPR64Bits[] = {
3055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
3056 };
3057
3058 // GPR64 Register Class...
3059 const MCPhysReg GPR64[] = {
3060 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR,
3061 };
3062
3063 // GPR64 Bit set.
3064 const uint8_t GPR64Bits[] = {
3065 0x44, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
3066 };
3067
3068 // GPR64sp Register Class...
3069 const MCPhysReg GPR64sp[] = {
3070 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP,
3071 };
3072
3073 // GPR64sp Bit set.
3074 const uint8_t GPR64spBits[] = {
3075 0x44, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
3076 };
3077
3078 // GPR64common Register Class...
3079 const MCPhysReg GPR64common[] = {
3080 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR,
3081 };
3082
3083 // GPR64common Bit set.
3084 const uint8_t GPR64commonBits[] = {
3085 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
3086 };
3087
3088 // GPR64noip Register Class...
3089 const MCPhysReg GPR64noip[] = {
3090 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::XZR,
3091 };
3092
3093 // GPR64noip Bit set.
3094 const uint8_t GPR64noipBits[] = {
3095 0x04, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0xfe, 0x0f,
3096 };
3097
3098 // GPR64common_and_GPR64noip Register Class...
3099 const MCPhysReg GPR64common_and_GPR64noip[] = {
3100 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
3101 };
3102
3103 // GPR64common_and_GPR64noip Bit set.
3104 const uint8_t GPR64common_and_GPR64noipBits[] = {
3105 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0xfe, 0x0f,
3106 };
3107
3108 // tcGPR64 Register Class...
3109 const MCPhysReg tcGPR64[] = {
3110 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18,
3111 };
3112
3113 // tcGPR64 Bit set.
3114 const uint8_t tcGPR64Bits[] = {
3115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03,
3116 };
3117
3118 // tcGPRnotx16 Register Class...
3119 const MCPhysReg tcGPRnotx16[] = {
3120 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X17, AArch64::X18,
3121 };
3122
3123 // tcGPRnotx16 Bit set.
3124 const uint8_t tcGPRnotx16Bits[] = {
3125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x03,
3126 };
3127
3128 // tcGPRnotx16x17 Register Class...
3129 const MCPhysReg tcGPRnotx16x17[] = {
3130 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18,
3131 };
3132
3133 // tcGPRnotx16x17 Bit set.
3134 const uint8_t tcGPRnotx16x17Bits[] = {
3135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x02,
3136 };
3137
3138 // FPR64_lo Register Class...
3139 const MCPhysReg FPR64_lo[] = {
3140 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15,
3141 };
3142
3143 // FPR64_lo Bit set.
3144 const uint8_t FPR64_loBits[] = {
3145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
3146 };
3147
3148 // GPR64arg Register Class...
3149 const MCPhysReg GPR64arg[] = {
3150 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7,
3151 };
3152
3153 // GPR64arg Bit set.
3154 const uint8_t GPR64argBits[] = {
3155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
3156 };
3157
3158 // FIXED_REGS Register Class...
3159 const MCPhysReg FIXED_REGS[] = {
3160 AArch64::FP, AArch64::SP, AArch64::VG, AArch64::FFR,
3161 };
3162
3163 // FIXED_REGS Bit set.
3164 const uint8_t FIXED_REGSBits[] = {
3165 0x06, 0x03,
3166 };
3167
3168 // GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Register Class...
3169 const MCPhysReg GPR64_with_sub_32_in_MatrixIndexGPR32_12_15[] = {
3170 AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15,
3171 };
3172
3173 // GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Bit set.
3174 const uint8_t GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits[] = {
3175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
3176 };
3177
3178 // GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
3179 const MCPhysReg GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
3180 AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11,
3181 };
3182
3183 // GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
3184 const uint8_t GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
3185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
3186 };
3187
3188 // FIXED_REGS_with_sub_32 Register Class...
3189 const MCPhysReg FIXED_REGS_with_sub_32[] = {
3190 AArch64::FP, AArch64::SP,
3191 };
3192
3193 // FIXED_REGS_with_sub_32 Bit set.
3194 const uint8_t FIXED_REGS_with_sub_32Bits[] = {
3195 0x04, 0x01,
3196 };
3197
3198 // tcGPRx16x17 Register Class...
3199 const MCPhysReg tcGPRx16x17[] = {
3200 AArch64::X16, AArch64::X17,
3201 };
3202
3203 // tcGPRx16x17 Bit set.
3204 const uint8_t tcGPRx16x17Bits[] = {
3205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
3206 };
3207
3208 // FIXED_REGS_and_GPR64 Register Class...
3209 const MCPhysReg FIXED_REGS_and_GPR64[] = {
3210 AArch64::FP,
3211 };
3212
3213 // FIXED_REGS_and_GPR64 Bit set.
3214 const uint8_t FIXED_REGS_and_GPR64Bits[] = {
3215 0x04,
3216 };
3217
3218 // GPR64sponly Register Class...
3219 const MCPhysReg GPR64sponly[] = {
3220 AArch64::SP,
3221 };
3222
3223 // GPR64sponly Bit set.
3224 const uint8_t GPR64sponlyBits[] = {
3225 0x00, 0x01,
3226 };
3227
3228 // tcGPRx17 Register Class...
3229 const MCPhysReg tcGPRx17[] = {
3230 AArch64::X17,
3231 };
3232
3233 // tcGPRx17 Bit set.
3234 const uint8_t tcGPRx17Bits[] = {
3235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
3236 };
3237
3238 // DD Register Class...
3239 const MCPhysReg DD[] = {
3240 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0,
3241 };
3242
3243 // DD Bit set.
3244 const uint8_t DDBits[] = {
3245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
3246 };
3247
3248 // DD_with_dsub0_in_FPR64_lo Register Class...
3249 const MCPhysReg DD_with_dsub0_in_FPR64_lo[] = {
3250 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
3251 };
3252
3253 // DD_with_dsub0_in_FPR64_lo Bit set.
3254 const uint8_t DD_with_dsub0_in_FPR64_loBits[] = {
3255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
3256 };
3257
3258 // DD_with_dsub1_in_FPR64_lo Register Class...
3259 const MCPhysReg DD_with_dsub1_in_FPR64_lo[] = {
3260 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D31_D0,
3261 };
3262
3263 // DD_with_dsub1_in_FPR64_lo Bit set.
3264 const uint8_t DD_with_dsub1_in_FPR64_loBits[] = {
3265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x04,
3266 };
3267
3268 // XSeqPairsClass Register Class...
3269 const MCPhysReg XSeqPairsClass[] = {
3270 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR,
3271 };
3272
3273 // XSeqPairsClass Bit set.
3274 const uint8_t XSeqPairsClassBits[] = {
3275 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3276 };
3277
3278 // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo Register Class...
3279 const MCPhysReg DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo[] = {
3280 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15,
3281 };
3282
3283 // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo Bit set.
3284 const uint8_t DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits[] = {
3285 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
3286 };
3287
3288 // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
3289 const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
3290 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP,
3291 };
3292
3293 // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
3294 const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
3295 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
3296 };
3297
3298 // XSeqPairsClass_with_subo64_in_GPR64noip Register Class...
3299 const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip[] = {
3300 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR,
3301 };
3302
3303 // XSeqPairsClass_with_subo64_in_GPR64noip Bit set.
3304 const uint8_t XSeqPairsClass_with_subo64_in_GPR64noipBits[] = {
3305 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7d,
3306 };
3307
3308 // XSeqPairsClass_with_sube64_in_GPR64noip Register Class...
3309 const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip[] = {
3310 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP,
3311 };
3312
3313 // XSeqPairsClass_with_sube64_in_GPR64noip Bit set.
3314 const uint8_t XSeqPairsClass_with_sube64_in_GPR64noipBits[] = {
3315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7d,
3316 };
3317
3318 // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
3319 const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
3320 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19,
3321 };
3322
3323 // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
3324 const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
3325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07,
3326 };
3327
3328 // XSeqPairsClass_with_sube64_in_tcGPRnotx16 Register Class...
3329 const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPRnotx16[] = {
3330 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19,
3331 };
3332
3333 // XSeqPairsClass_with_sube64_in_tcGPRnotx16 Bit set.
3334 const uint8_t XSeqPairsClass_with_sube64_in_tcGPRnotx16Bits[] = {
3335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x05,
3336 };
3337
3338 // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
3339 const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
3340 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17,
3341 };
3342
3343 // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
3344 const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
3345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x03,
3346 };
3347
3348 // XSeqPairsClass_with_subo64_in_tcGPRnotx16x17 Register Class...
3349 const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPRnotx16x17[] = {
3350 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15,
3351 };
3352
3353 // XSeqPairsClass_with_subo64_in_tcGPRnotx16x17 Bit set.
3354 const uint8_t XSeqPairsClass_with_subo64_in_tcGPRnotx16x17Bits[] = {
3355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
3356 };
3357
3358 // XSeqPairsClass_with_sube64_in_GPR64arg Register Class...
3359 const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64arg[] = {
3360 AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7,
3361 };
3362
3363 // XSeqPairsClass_with_sube64_in_GPR64arg Bit set.
3364 const uint8_t XSeqPairsClass_with_sube64_in_GPR64argBits[] = {
3365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
3366 };
3367
3368 // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Register Class...
3369 const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15[] = {
3370 AArch64::X12_X13, AArch64::X14_X15,
3371 };
3372
3373 // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Bit set.
3374 const uint8_t XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits[] = {
3375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
3376 };
3377
3378 // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
3379 const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
3380 AArch64::X8_X9, AArch64::X10_X11,
3381 };
3382
3383 // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
3384 const uint8_t XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
3385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
3386 };
3387
3388 // XSeqPairsClass_with_sube64_in_tcGPRx16x17 Register Class...
3389 const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPRx16x17[] = {
3390 AArch64::X16_X17,
3391 };
3392
3393 // XSeqPairsClass_with_sube64_in_tcGPRx16x17 Bit set.
3394 const uint8_t XSeqPairsClass_with_sube64_in_tcGPRx16x17Bits[] = {
3395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
3396 };
3397
3398 // XSeqPairsClass_with_subo64_in_FIXED_REGS Register Class...
3399 const MCPhysReg XSeqPairsClass_with_subo64_in_FIXED_REGS[] = {
3400 AArch64::X28_FP,
3401 };
3402
3403 // XSeqPairsClass_with_subo64_in_FIXED_REGS Bit set.
3404 const uint8_t XSeqPairsClass_with_subo64_in_FIXED_REGSBits[] = {
3405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
3406 };
3407
3408 // FPR128 Register Class...
3409 const MCPhysReg FPR128[] = {
3410 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31,
3411 };
3412
3413 // FPR128 Bit set.
3414 const uint8_t FPR128Bits[] = {
3415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
3416 };
3417
3418 // ZPR Register Class...
3419 const MCPhysReg ZPR[] = {
3420 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31,
3421 };
3422
3423 // ZPR Bit set.
3424 const uint8_t ZPRBits[] = {
3425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
3426 };
3427
3428 // FPR128_lo Register Class...
3429 const MCPhysReg FPR128_lo[] = {
3430 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15,
3431 };
3432
3433 // FPR128_lo Bit set.
3434 const uint8_t FPR128_loBits[] = {
3435 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
3436 };
3437
3438 // MPR128 Register Class...
3439 const MCPhysReg MPR128[] = {
3440 AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15,
3441 };
3442
3443 // MPR128 Bit set.
3444 const uint8_t MPR128Bits[] = {
3445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3446 };
3447
3448 // ZPRMul2 Register Class...
3449 const MCPhysReg ZPRMul2[] = {
3450 AArch64::Z0, AArch64::Z2, AArch64::Z4, AArch64::Z6, AArch64::Z8, AArch64::Z10, AArch64::Z12, AArch64::Z14, AArch64::Z16, AArch64::Z18, AArch64::Z20, AArch64::Z22, AArch64::Z24, AArch64::Z26, AArch64::Z28, AArch64::Z30,
3451 };
3452
3453 // ZPRMul2 Bit set.
3454 const uint8_t ZPRMul2Bits[] = {
3455 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
3456 };
3457
3458 // ZPR_4b Register Class...
3459 const MCPhysReg ZPR_4b[] = {
3460 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
3461 };
3462
3463 // ZPR_4b Bit set.
3464 const uint8_t ZPR_4bBits[] = {
3465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
3466 };
3467
3468 // FPR128_0to7 Register Class...
3469 const MCPhysReg FPR128_0to7[] = {
3470 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7,
3471 };
3472
3473 // FPR128_0to7 Bit set.
3474 const uint8_t FPR128_0to7Bits[] = {
3475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
3476 };
3477
3478 // ZPRMul2_Hi Register Class...
3479 const MCPhysReg ZPRMul2_Hi[] = {
3480 AArch64::Z16, AArch64::Z18, AArch64::Z20, AArch64::Z22, AArch64::Z24, AArch64::Z26, AArch64::Z28, AArch64::Z30,
3481 };
3482
3483 // ZPRMul2_Hi Bit set.
3484 const uint8_t ZPRMul2_HiBits[] = {
3485 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x05,
3486 };
3487
3488 // ZPRMul2_Lo Register Class...
3489 const MCPhysReg ZPRMul2_Lo[] = {
3490 AArch64::Z0, AArch64::Z2, AArch64::Z4, AArch64::Z6, AArch64::Z8, AArch64::Z10, AArch64::Z12, AArch64::Z14,
3491 };
3492
3493 // ZPRMul2_Lo Bit set.
3494 const uint8_t ZPRMul2_LoBits[] = {
3495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x05,
3496 };
3497
3498 // ZPRMul4 Register Class...
3499 const MCPhysReg ZPRMul4[] = {
3500 AArch64::Z0, AArch64::Z4, AArch64::Z8, AArch64::Z12, AArch64::Z16, AArch64::Z20, AArch64::Z24, AArch64::Z28,
3501 };
3502
3503 // ZPRMul4 Bit set.
3504 const uint8_t ZPRMul4Bits[] = {
3505 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11, 0x01,
3506 };
3507
3508 // ZPR_3b Register Class...
3509 const MCPhysReg ZPR_3b[] = {
3510 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
3511 };
3512
3513 // ZPR_3b Bit set.
3514 const uint8_t ZPR_3bBits[] = {
3515 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
3516 };
3517
3518 // ZPR_K Register Class...
3519 const MCPhysReg ZPR_K[] = {
3520 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31,
3521 };
3522
3523 // ZPR_K Bit set.
3524 const uint8_t ZPR_KBits[] = {
3525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f,
3526 };
3527
3528 // ZPRMul2_Hi_and_ZPRMul4 Register Class...
3529 const MCPhysReg ZPRMul2_Hi_and_ZPRMul4[] = {
3530 AArch64::Z16, AArch64::Z20, AArch64::Z24, AArch64::Z28,
3531 };
3532
3533 // ZPRMul2_Hi_and_ZPRMul4 Bit set.
3534 const uint8_t ZPRMul2_Hi_and_ZPRMul4Bits[] = {
3535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01,
3536 };
3537
3538 // ZPRMul2_Lo_and_ZPRMul4 Register Class...
3539 const MCPhysReg ZPRMul2_Lo_and_ZPRMul4[] = {
3540 AArch64::Z0, AArch64::Z4, AArch64::Z8, AArch64::Z12,
3541 };
3542
3543 // ZPRMul2_Lo_and_ZPRMul4 Bit set.
3544 const uint8_t ZPRMul2_Lo_and_ZPRMul4Bits[] = {
3545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01,
3546 };
3547
3548 // ZPRMul2_and_ZPR_3b Register Class...
3549 const MCPhysReg ZPRMul2_and_ZPR_3b[] = {
3550 AArch64::Z0, AArch64::Z2, AArch64::Z4, AArch64::Z6,
3551 };
3552
3553 // ZPRMul2_and_ZPR_3b Bit set.
3554 const uint8_t ZPRMul2_and_ZPR_3bBits[] = {
3555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x05,
3556 };
3557
3558 // ZPRMul2_and_ZPR_K Register Class...
3559 const MCPhysReg ZPRMul2_and_ZPR_K[] = {
3560 AArch64::Z20, AArch64::Z22, AArch64::Z28, AArch64::Z30,
3561 };
3562
3563 // ZPRMul2_and_ZPR_K Bit set.
3564 const uint8_t ZPRMul2_and_ZPR_KBits[] = {
3565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05,
3566 };
3567
3568 // ZPRMul4_and_ZPR_3b Register Class...
3569 const MCPhysReg ZPRMul4_and_ZPR_3b[] = {
3570 AArch64::Z0, AArch64::Z4,
3571 };
3572
3573 // ZPRMul4_and_ZPR_3b Bit set.
3574 const uint8_t ZPRMul4_and_ZPR_3bBits[] = {
3575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01,
3576 };
3577
3578 // ZPRMul4_and_ZPR_K Register Class...
3579 const MCPhysReg ZPRMul4_and_ZPR_K[] = {
3580 AArch64::Z20, AArch64::Z28,
3581 };
3582
3583 // ZPRMul4_and_ZPR_K Bit set.
3584 const uint8_t ZPRMul4_and_ZPR_KBits[] = {
3585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
3586 };
3587
3588 // DDD Register Class...
3589 const MCPhysReg DDD[] = {
3590 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1,
3591 };
3592
3593 // DDD Bit set.
3594 const uint8_t DDDBits[] = {
3595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
3596 };
3597
3598 // DDD_with_dsub0_in_FPR64_lo Register Class...
3599 const MCPhysReg DDD_with_dsub0_in_FPR64_lo[] = {
3600 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17,
3601 };
3602
3603 // DDD_with_dsub0_in_FPR64_lo Bit set.
3604 const uint8_t DDD_with_dsub0_in_FPR64_loBits[] = {
3605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
3606 };
3607
3608 // DDD_with_dsub1_in_FPR64_lo Register Class...
3609 const MCPhysReg DDD_with_dsub1_in_FPR64_lo[] = {
3610 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D31_D0_D1,
3611 };
3612
3613 // DDD_with_dsub1_in_FPR64_lo Bit set.
3614 const uint8_t DDD_with_dsub1_in_FPR64_loBits[] = {
3615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x04,
3616 };
3617
3618 // DDD_with_dsub2_in_FPR64_lo Register Class...
3619 const MCPhysReg DDD_with_dsub2_in_FPR64_lo[] = {
3620 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D30_D31_D0, AArch64::D31_D0_D1,
3621 };
3622
3623 // DDD_with_dsub2_in_FPR64_lo Bit set.
3624 const uint8_t DDD_with_dsub2_in_FPR64_loBits[] = {
3625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x06,
3626 };
3627
3628 // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo Register Class...
3629 const MCPhysReg DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo[] = {
3630 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
3631 };
3632
3633 // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo Bit set.
3634 const uint8_t DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits[] = {
3635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
3636 };
3637
3638 // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Register Class...
3639 const MCPhysReg DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo[] = {
3640 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D31_D0_D1,
3641 };
3642
3643 // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Bit set.
3644 const uint8_t DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits[] = {
3645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x04,
3646 };
3647
3648 // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Register Class...
3649 const MCPhysReg DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo[] = {
3650 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15,
3651 };
3652
3653 // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Bit set.
3654 const uint8_t DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits[] = {
3655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
3656 };
3657
3658 // DDDD Register Class...
3659 const MCPhysReg DDDD[] = {
3660 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2,
3661 };
3662
3663 // DDDD Bit set.
3664 const uint8_t DDDDBits[] = {
3665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
3666 };
3667
3668 // DDDD_with_dsub0_in_FPR64_lo Register Class...
3669 const MCPhysReg DDDD_with_dsub0_in_FPR64_lo[] = {
3670 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18,
3671 };
3672
3673 // DDDD_with_dsub0_in_FPR64_lo Bit set.
3674 const uint8_t DDDD_with_dsub0_in_FPR64_loBits[] = {
3675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
3676 };
3677
3678 // DDDD_with_dsub1_in_FPR64_lo Register Class...
3679 const MCPhysReg DDDD_with_dsub1_in_FPR64_lo[] = {
3680 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D31_D0_D1_D2,
3681 };
3682
3683 // DDDD_with_dsub1_in_FPR64_lo Bit set.
3684 const uint8_t DDDD_with_dsub1_in_FPR64_loBits[] = {
3685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x04,
3686 };
3687
3688 // DDDD_with_dsub2_in_FPR64_lo Register Class...
3689 const MCPhysReg DDDD_with_dsub2_in_FPR64_lo[] = {
3690 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2,
3691 };
3692
3693 // DDDD_with_dsub2_in_FPR64_lo Bit set.
3694 const uint8_t DDDD_with_dsub2_in_FPR64_loBits[] = {
3695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x06,
3696 };
3697
3698 // DDDD_with_dsub3_in_FPR64_lo Register Class...
3699 const MCPhysReg DDDD_with_dsub3_in_FPR64_lo[] = {
3700 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2,
3701 };
3702
3703 // DDDD_with_dsub3_in_FPR64_lo Bit set.
3704 const uint8_t DDDD_with_dsub3_in_FPR64_loBits[] = {
3705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x00, 0x00, 0x07,
3706 };
3707
3708 // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo Register Class...
3709 const MCPhysReg DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo[] = {
3710 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
3711 };
3712
3713 // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo Bit set.
3714 const uint8_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits[] = {
3715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
3716 };
3717
3718 // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Register Class...
3719 const MCPhysReg DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo[] = {
3720 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D31_D0_D1_D2,
3721 };
3722
3723 // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Bit set.
3724 const uint8_t DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits[] = {
3725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x04,
3726 };
3727
3728 // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class...
3729 const MCPhysReg DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = {
3730 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2,
3731 };
3732
3733 // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set.
3734 const uint8_t DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = {
3735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x00, 0x00, 0x06,
3736 };
3737
3738 // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Register Class...
3739 const MCPhysReg DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo[] = {
3740 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16,
3741 };
3742
3743 // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Bit set.
3744 const uint8_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits[] = {
3745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
3746 };
3747
3748 // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class...
3749 const MCPhysReg DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = {
3750 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D31_D0_D1_D2,
3751 };
3752
3753 // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set.
3754 const uint8_t DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = {
3755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x00, 0x00, 0x04,
3756 };
3757
3758 // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class...
3759 const MCPhysReg DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = {
3760 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15,
3761 };
3762
3763 // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set.
3764 const uint8_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = {
3765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff,
3766 };
3767
3768 // QQ Register Class...
3769 const MCPhysReg QQ[] = {
3770 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0,
3771 };
3772
3773 // QQ Bit set.
3774 const uint8_t QQBits[] = {
3775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
3776 };
3777
3778 // ZPR2 Register Class...
3779 const MCPhysReg ZPR2[] = {
3780 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0,
3781 };
3782
3783 // ZPR2 Bit set.
3784 const uint8_t ZPR2Bits[] = {
3785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
3786 };
3787
3788 // ZPR2StridedOrContiguous Register Class...
3789 const MCPhysReg ZPR2StridedOrContiguous[] = {
3790 AArch64::Z0_Z8, AArch64::Z1_Z9, AArch64::Z2_Z10, AArch64::Z3_Z11, AArch64::Z4_Z12, AArch64::Z5_Z13, AArch64::Z6_Z14, AArch64::Z7_Z15, AArch64::Z16_Z24, AArch64::Z17_Z25, AArch64::Z18_Z26, AArch64::Z19_Z27, AArch64::Z20_Z28, AArch64::Z21_Z29, AArch64::Z22_Z30, AArch64::Z23_Z31, AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7, AArch64::Z8_Z9, AArch64::Z10_Z11, AArch64::Z12_Z13, AArch64::Z14_Z15, AArch64::Z16_Z17, AArch64::Z18_Z19, AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z24_Z25, AArch64::Z26_Z27, AArch64::Z28_Z29, AArch64::Z30_Z31,
3791 };
3792
3793 // ZPR2StridedOrContiguous Bit set.
3794 const uint8_t ZPR2StridedOrContiguousBits[] = {
3795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3796 };
3797
3798 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2 Register Class...
3799 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2[] = {
3800 AArch64::Z0_Z8, AArch64::Z2_Z10, AArch64::Z4_Z12, AArch64::Z6_Z14, AArch64::Z16_Z24, AArch64::Z18_Z26, AArch64::Z20_Z28, AArch64::Z22_Z30, AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7, AArch64::Z8_Z9, AArch64::Z10_Z11, AArch64::Z12_Z13, AArch64::Z14_Z15, AArch64::Z16_Z17, AArch64::Z18_Z19, AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z24_Z25, AArch64::Z26_Z27, AArch64::Z28_Z29, AArch64::Z30_Z31,
3801 };
3802
3803 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2 Bit set.
3804 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2Bits[] = {
3805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
3806 };
3807
3808 // QQ_with_dsub1_in_FPR64_lo Register Class...
3809 const MCPhysReg QQ_with_dsub1_in_FPR64_lo[] = {
3810 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0,
3811 };
3812
3813 // QQ_with_dsub1_in_FPR64_lo Bit set.
3814 const uint8_t QQ_with_dsub1_in_FPR64_loBits[] = {
3815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x04,
3816 };
3817
3818 // QQ_with_qsub0_in_FPR128_lo Register Class...
3819 const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
3820 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
3821 };
3822
3823 // QQ_with_qsub0_in_FPR128_lo Bit set.
3824 const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
3825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
3826 };
3827
3828 // ZPR2Mul2 Register Class...
3829 const MCPhysReg ZPR2Mul2[] = {
3830 AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7, AArch64::Z8_Z9, AArch64::Z10_Z11, AArch64::Z12_Z13, AArch64::Z14_Z15, AArch64::Z16_Z17, AArch64::Z18_Z19, AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z24_Z25, AArch64::Z26_Z27, AArch64::Z28_Z29, AArch64::Z30_Z31,
3831 };
3832
3833 // ZPR2Mul2 Bit set.
3834 const uint8_t ZPR2Mul2Bits[] = {
3835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x2a,
3836 };
3837
3838 // ZPR2Strided Register Class...
3839 const MCPhysReg ZPR2Strided[] = {
3840 AArch64::Z0_Z8, AArch64::Z1_Z9, AArch64::Z2_Z10, AArch64::Z3_Z11, AArch64::Z4_Z12, AArch64::Z5_Z13, AArch64::Z6_Z14, AArch64::Z7_Z15, AArch64::Z16_Z24, AArch64::Z17_Z25, AArch64::Z18_Z26, AArch64::Z19_Z27, AArch64::Z20_Z28, AArch64::Z21_Z29, AArch64::Z22_Z30, AArch64::Z23_Z31,
3841 };
3842
3843 // ZPR2Strided Bit set.
3844 const uint8_t ZPR2StridedBits[] = {
3845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3846 };
3847
3848 // ZPR2StridedOrContiguous_with_dsub_in_FPR64_lo Register Class...
3849 const MCPhysReg ZPR2StridedOrContiguous_with_dsub_in_FPR64_lo[] = {
3850 AArch64::Z0_Z8, AArch64::Z1_Z9, AArch64::Z2_Z10, AArch64::Z3_Z11, AArch64::Z4_Z12, AArch64::Z5_Z13, AArch64::Z6_Z14, AArch64::Z7_Z15, AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7, AArch64::Z8_Z9, AArch64::Z10_Z11, AArch64::Z12_Z13, AArch64::Z14_Z15,
3851 };
3852
3853 // ZPR2StridedOrContiguous_with_dsub_in_FPR64_lo Bit set.
3854 const uint8_t ZPR2StridedOrContiguous_with_dsub_in_FPR64_loBits[] = {
3855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
3856 };
3857
3858 // ZPR2_with_dsub1_in_FPR64_lo Register Class...
3859 const MCPhysReg ZPR2_with_dsub1_in_FPR64_lo[] = {
3860 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0,
3861 };
3862
3863 // ZPR2_with_dsub1_in_FPR64_lo Bit set.
3864 const uint8_t ZPR2_with_dsub1_in_FPR64_loBits[] = {
3865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, 0x00, 0x40,
3866 };
3867
3868 // ZPR2_with_zsub1_in_ZPRMul2 Register Class...
3869 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul2[] = {
3870 AArch64::Z1_Z2, AArch64::Z3_Z4, AArch64::Z5_Z6, AArch64::Z7_Z8, AArch64::Z9_Z10, AArch64::Z11_Z12, AArch64::Z13_Z14, AArch64::Z15_Z16, AArch64::Z17_Z18, AArch64::Z19_Z20, AArch64::Z21_Z22, AArch64::Z23_Z24, AArch64::Z25_Z26, AArch64::Z27_Z28, AArch64::Z29_Z30, AArch64::Z31_Z0,
3871 };
3872
3873 // ZPR2_with_zsub1_in_ZPRMul2 Bit set.
3874 const uint8_t ZPR2_with_zsub1_in_ZPRMul2Bits[] = {
3875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x55,
3876 };
3877
3878 // ZPR2_with_zsub_in_FPR128_lo Register Class...
3879 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
3880 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
3881 };
3882
3883 // ZPR2_with_zsub_in_FPR128_lo Bit set.
3884 const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
3885 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3886 };
3887
3888 // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_lo Register Class...
3889 const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_lo[] = {
3890 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15,
3891 };
3892
3893 // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_lo Bit set.
3894 const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loBits[] = {
3895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
3896 };
3897
3898 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_lo Register Class...
3899 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_lo[] = {
3900 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15,
3901 };
3902
3903 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_lo Bit set.
3904 const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_loBits[] = {
3905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f,
3906 };
3907
3908 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi Register Class...
3909 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi[] = {
3910 AArch64::Z16_Z24, AArch64::Z18_Z26, AArch64::Z20_Z28, AArch64::Z22_Z30, AArch64::Z16_Z17, AArch64::Z18_Z19, AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z24_Z25, AArch64::Z26_Z27, AArch64::Z28_Z29, AArch64::Z30_Z31,
3911 };
3912
3913 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi Bit set.
3914 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_HiBits[] = {
3915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
3916 };
3917
3918 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo Register Class...
3919 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo[] = {
3920 AArch64::Z0_Z8, AArch64::Z2_Z10, AArch64::Z4_Z12, AArch64::Z6_Z14, AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7, AArch64::Z8_Z9, AArch64::Z10_Z11, AArch64::Z12_Z13, AArch64::Z14_Z15,
3921 };
3922
3923 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo Bit set.
3924 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_LoBits[] = {
3925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
3926 };
3927
3928 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4 Register Class...
3929 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4[] = {
3930 AArch64::Z0_Z8, AArch64::Z4_Z12, AArch64::Z16_Z24, AArch64::Z20_Z28, AArch64::Z0_Z1, AArch64::Z4_Z5, AArch64::Z8_Z9, AArch64::Z12_Z13, AArch64::Z16_Z17, AArch64::Z20_Z21, AArch64::Z24_Z25, AArch64::Z28_Z29,
3931 };
3932
3933 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4 Bit set.
3934 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4Bits[] = {
3935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x88, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
3936 };
3937
3938 // ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7 Register Class...
3939 const MCPhysReg ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7[] = {
3940 AArch64::Z0_Z8, AArch64::Z1_Z9, AArch64::Z2_Z10, AArch64::Z3_Z11, AArch64::Z4_Z12, AArch64::Z5_Z13, AArch64::Z6_Z14, AArch64::Z7_Z15, AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7,
3941 };
3942
3943 // ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7 Bit set.
3944 const uint8_t ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7Bits[] = {
3945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
3946 };
3947
3948 // QQ_with_qsub0_in_FPR128_0to7 Register Class...
3949 const MCPhysReg QQ_with_qsub0_in_FPR128_0to7[] = {
3950 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
3951 };
3952
3953 // QQ_with_qsub0_in_FPR128_0to7 Bit set.
3954 const uint8_t QQ_with_qsub0_in_FPR128_0to7Bits[] = {
3955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
3956 };
3957
3958 // QQ_with_qsub1_in_FPR128_0to7 Register Class...
3959 const MCPhysReg QQ_with_qsub1_in_FPR128_0to7[] = {
3960 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q31_Q0,
3961 };
3962
3963 // QQ_with_qsub1_in_FPR128_0to7 Bit set.
3964 const uint8_t QQ_with_qsub1_in_FPR128_0to7Bits[] = {
3965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x04,
3966 };
3967
3968 // ZPR2Mul2_Hi Register Class...
3969 const MCPhysReg ZPR2Mul2_Hi[] = {
3970 AArch64::Z16_Z17, AArch64::Z18_Z19, AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z24_Z25, AArch64::Z26_Z27, AArch64::Z28_Z29, AArch64::Z30_Z31,
3971 };
3972
3973 // ZPR2Mul2_Hi Bit set.
3974 const uint8_t ZPR2Mul2_HiBits[] = {
3975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
3976 };
3977
3978 // ZPR2Mul2_Lo Register Class...
3979 const MCPhysReg ZPR2Mul2_Lo[] = {
3980 AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7, AArch64::Z8_Z9, AArch64::Z10_Z11, AArch64::Z12_Z13, AArch64::Z14_Z15,
3981 };
3982
3983 // ZPR2Mul2_Lo Bit set.
3984 const uint8_t ZPR2Mul2_LoBits[] = {
3985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
3986 };
3987
3988 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b Register Class...
3989 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b[] = {
3990 AArch64::Z0_Z8, AArch64::Z2_Z10, AArch64::Z4_Z12, AArch64::Z6_Z14, AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7,
3991 };
3992
3993 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b Bit set.
3994 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bBits[] = {
3995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
3996 };
3997
3998 // ZPR2StridedOrContiguous_with_zsub0_in_ZPR_K Register Class...
3999 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPR_K[] = {
4000 AArch64::Z20_Z28, AArch64::Z21_Z29, AArch64::Z22_Z30, AArch64::Z23_Z31, AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z28_Z29, AArch64::Z30_Z31,
4001 };
4002
4003 // ZPR2StridedOrContiguous_with_zsub0_in_ZPR_K Bit set.
4004 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPR_KBits[] = {
4005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
4006 };
4007
4008 // ZPR2Strided_with_dsub_in_FPR64_lo Register Class...
4009 const MCPhysReg ZPR2Strided_with_dsub_in_FPR64_lo[] = {
4010 AArch64::Z0_Z8, AArch64::Z1_Z9, AArch64::Z2_Z10, AArch64::Z3_Z11, AArch64::Z4_Z12, AArch64::Z5_Z13, AArch64::Z6_Z14, AArch64::Z7_Z15,
4011 };
4012
4013 // ZPR2Strided_with_dsub_in_FPR64_lo Bit set.
4014 const uint8_t ZPR2Strided_with_dsub_in_FPR64_loBits[] = {
4015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4016 };
4017
4018 // ZPR2Strided_with_zsub0_in_ZPRMul2 Register Class...
4019 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul2[] = {
4020 AArch64::Z0_Z8, AArch64::Z2_Z10, AArch64::Z4_Z12, AArch64::Z6_Z14, AArch64::Z16_Z24, AArch64::Z18_Z26, AArch64::Z20_Z28, AArch64::Z22_Z30,
4021 };
4022
4023 // ZPR2Strided_with_zsub0_in_ZPRMul2 Bit set.
4024 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul2Bits[] = {
4025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
4026 };
4027
4028 // ZPR2_with_qsub1_in_FPR128_0to7 Register Class...
4029 const MCPhysReg ZPR2_with_qsub1_in_FPR128_0to7[] = {
4030 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0,
4031 };
4032
4033 // ZPR2_with_qsub1_in_FPR128_0to7 Bit set.
4034 const uint8_t ZPR2_with_qsub1_in_FPR128_0to7Bits[] = {
4035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x40,
4036 };
4037
4038 // ZPR2_with_zsub0_in_ZPRMul4 Register Class...
4039 const MCPhysReg ZPR2_with_zsub0_in_ZPRMul4[] = {
4040 AArch64::Z0_Z1, AArch64::Z4_Z5, AArch64::Z8_Z9, AArch64::Z12_Z13, AArch64::Z16_Z17, AArch64::Z20_Z21, AArch64::Z24_Z25, AArch64::Z28_Z29,
4041 };
4042
4043 // ZPR2_with_zsub0_in_ZPRMul4 Bit set.
4044 const uint8_t ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
4045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x88, 0x88, 0x08,
4046 };
4047
4048 // ZPR2_with_zsub0_in_ZPR_K Register Class...
4049 const MCPhysReg ZPR2_with_zsub0_in_ZPR_K[] = {
4050 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0,
4051 };
4052
4053 // ZPR2_with_zsub0_in_ZPR_K Bit set.
4054 const uint8_t ZPR2_with_zsub0_in_ZPR_KBits[] = {
4055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x78,
4056 };
4057
4058 // ZPR2_with_zsub1_in_ZPRMul2_Hi Register Class...
4059 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul2_Hi[] = {
4060 AArch64::Z15_Z16, AArch64::Z17_Z18, AArch64::Z19_Z20, AArch64::Z21_Z22, AArch64::Z23_Z24, AArch64::Z25_Z26, AArch64::Z27_Z28, AArch64::Z29_Z30,
4061 };
4062
4063 // ZPR2_with_zsub1_in_ZPRMul2_Hi Bit set.
4064 const uint8_t ZPR2_with_zsub1_in_ZPRMul2_HiBits[] = {
4065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x15,
4066 };
4067
4068 // ZPR2_with_zsub1_in_ZPRMul2_Lo Register Class...
4069 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul2_Lo[] = {
4070 AArch64::Z1_Z2, AArch64::Z3_Z4, AArch64::Z5_Z6, AArch64::Z7_Z8, AArch64::Z9_Z10, AArch64::Z11_Z12, AArch64::Z13_Z14, AArch64::Z31_Z0,
4071 };
4072
4073 // ZPR2_with_zsub1_in_ZPRMul2_Lo Bit set.
4074 const uint8_t ZPR2_with_zsub1_in_ZPRMul2_LoBits[] = {
4075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 0x00, 0x40,
4076 };
4077
4078 // ZPR2_with_zsub1_in_ZPRMul4 Register Class...
4079 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul4[] = {
4080 AArch64::Z3_Z4, AArch64::Z7_Z8, AArch64::Z11_Z12, AArch64::Z15_Z16, AArch64::Z19_Z20, AArch64::Z23_Z24, AArch64::Z27_Z28, AArch64::Z31_Z0,
4081 };
4082
4083 // ZPR2_with_zsub1_in_ZPRMul4 Bit set.
4084 const uint8_t ZPR2_with_zsub1_in_ZPRMul4Bits[] = {
4085 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x44,
4086 };
4087
4088 // ZPR2_with_zsub1_in_ZPR_K Register Class...
4089 const MCPhysReg ZPR2_with_zsub1_in_ZPR_K[] = {
4090 AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31,
4091 };
4092
4093 // ZPR2_with_zsub1_in_ZPR_K Bit set.
4094 const uint8_t ZPR2_with_zsub1_in_ZPR_KBits[] = {
4095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x3c,
4096 };
4097
4098 // ZPR2_with_zsub_in_FPR128_0to7 Register Class...
4099 const MCPhysReg ZPR2_with_zsub_in_FPR128_0to7[] = {
4100 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
4101 };
4102
4103 // ZPR2_with_zsub_in_FPR128_0to7 Bit set.
4104 const uint8_t ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
4105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4106 };
4107
4108 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2 Register Class...
4109 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2[] = {
4110 AArch64::Z1_Z2, AArch64::Z3_Z4, AArch64::Z5_Z6, AArch64::Z7_Z8, AArch64::Z9_Z10, AArch64::Z11_Z12, AArch64::Z13_Z14, AArch64::Z15_Z16,
4111 };
4112
4113 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2 Bit set.
4114 const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2Bits[] = {
4115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
4116 };
4117
4118 // QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7 Register Class...
4119 const MCPhysReg QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7[] = {
4120 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7,
4121 };
4122
4123 // QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7 Bit set.
4124 const uint8_t QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7Bits[] = {
4125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
4126 };
4127
4128 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7 Register Class...
4129 const MCPhysReg ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7[] = {
4130 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7,
4131 };
4132
4133 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7 Bit set.
4134 const uint8_t ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7Bits[] = {
4135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
4136 };
4137
4138 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo Register Class...
4139 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo[] = {
4140 AArch64::Z1_Z2, AArch64::Z3_Z4, AArch64::Z5_Z6, AArch64::Z7_Z8, AArch64::Z9_Z10, AArch64::Z11_Z12, AArch64::Z13_Z14,
4141 };
4142
4143 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo Bit set.
4144 const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_LoBits[] = {
4145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
4146 };
4147
4148 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
4149 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4[] = {
4150 AArch64::Z16_Z24, AArch64::Z20_Z28, AArch64::Z16_Z17, AArch64::Z20_Z21, AArch64::Z24_Z25, AArch64::Z28_Z29,
4151 };
4152
4153 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
4154 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
4155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
4156 };
4157
4158 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
4159 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4[] = {
4160 AArch64::Z0_Z8, AArch64::Z4_Z12, AArch64::Z0_Z1, AArch64::Z4_Z5, AArch64::Z8_Z9, AArch64::Z12_Z13,
4161 };
4162
4163 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
4164 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
4165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
4166 };
4167
4168 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_K Register Class...
4169 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_K[] = {
4170 AArch64::Z20_Z28, AArch64::Z22_Z30, AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z28_Z29, AArch64::Z30_Z31,
4171 };
4172
4173 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_K Bit set.
4174 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_KBits[] = {
4175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
4176 };
4177
4178 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_K Register Class...
4179 const MCPhysReg ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_K[] = {
4180 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31,
4181 };
4182
4183 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_K Bit set.
4184 const uint8_t ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_KBits[] = {
4185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x38,
4186 };
4187
4188 // ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
4189 const MCPhysReg ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
4190 AArch64::Z16_Z17, AArch64::Z20_Z21, AArch64::Z24_Z25, AArch64::Z28_Z29,
4191 };
4192
4193 // ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
4194 const uint8_t ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
4195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
4196 };
4197
4198 // ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
4199 const MCPhysReg ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
4200 AArch64::Z0_Z1, AArch64::Z4_Z5, AArch64::Z8_Z9, AArch64::Z12_Z13,
4201 };
4202
4203 // ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
4204 const uint8_t ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
4205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
4206 };
4207
4208 // ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
4209 const MCPhysReg ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
4210 AArch64::Z20_Z21, AArch64::Z22_Z23, AArch64::Z28_Z29, AArch64::Z30_Z31,
4211 };
4212
4213 // ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
4214 const uint8_t ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
4215 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x28,
4216 };
4217
4218 // ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
4219 const MCPhysReg ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
4220 AArch64::Z0_Z1, AArch64::Z2_Z3, AArch64::Z4_Z5, AArch64::Z6_Z7,
4221 };
4222
4223 // ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
4224 const uint8_t ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
4225 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
4226 };
4227
4228 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b Register Class...
4229 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b[] = {
4230 AArch64::Z0_Z8, AArch64::Z4_Z12, AArch64::Z0_Z1, AArch64::Z4_Z5,
4231 };
4232
4233 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b Bit set.
4234 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bBits[] = {
4235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
4236 };
4237
4238 // ZPR2Strided_with_zsub0_in_ZPRMul2_Hi Register Class...
4239 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul2_Hi[] = {
4240 AArch64::Z16_Z24, AArch64::Z18_Z26, AArch64::Z20_Z28, AArch64::Z22_Z30,
4241 };
4242
4243 // ZPR2Strided_with_zsub0_in_ZPRMul2_Hi Bit set.
4244 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul2_HiBits[] = {
4245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
4246 };
4247
4248 // ZPR2Strided_with_zsub0_in_ZPRMul2_Lo Register Class...
4249 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul2_Lo[] = {
4250 AArch64::Z0_Z8, AArch64::Z2_Z10, AArch64::Z4_Z12, AArch64::Z6_Z14,
4251 };
4252
4253 // ZPR2Strided_with_zsub0_in_ZPRMul2_Lo Bit set.
4254 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul2_LoBits[] = {
4255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
4256 };
4257
4258 // ZPR2Strided_with_zsub0_in_ZPRMul4 Register Class...
4259 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul4[] = {
4260 AArch64::Z0_Z8, AArch64::Z4_Z12, AArch64::Z16_Z24, AArch64::Z20_Z28,
4261 };
4262
4263 // ZPR2Strided_with_zsub0_in_ZPRMul4 Bit set.
4264 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul4Bits[] = {
4265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
4266 };
4267
4268 // ZPR2Strided_with_zsub0_in_ZPR_K Register Class...
4269 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPR_K[] = {
4270 AArch64::Z20_Z28, AArch64::Z21_Z29, AArch64::Z22_Z30, AArch64::Z23_Z31,
4271 };
4272
4273 // ZPR2Strided_with_zsub0_in_ZPR_K Bit set.
4274 const uint8_t ZPR2Strided_with_zsub0_in_ZPR_KBits[] = {
4275 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
4276 };
4277
4278 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2 Register Class...
4279 const MCPhysReg ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2[] = {
4280 AArch64::Z21_Z22, AArch64::Z23_Z24, AArch64::Z29_Z30, AArch64::Z31_Z0,
4281 };
4282
4283 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2 Bit set.
4284 const uint8_t ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2Bits[] = {
4285 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x50,
4286 };
4287
4288 // ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
4289 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4[] = {
4290 AArch64::Z15_Z16, AArch64::Z19_Z20, AArch64::Z23_Z24, AArch64::Z27_Z28,
4291 };
4292
4293 // ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
4294 const uint8_t ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
4295 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x44, 0x04,
4296 };
4297
4298 // ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
4299 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4[] = {
4300 AArch64::Z3_Z4, AArch64::Z7_Z8, AArch64::Z11_Z12, AArch64::Z31_Z0,
4301 };
4302
4303 // ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
4304 const uint8_t ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
4305 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x04, 0x00, 0x40,
4306 };
4307
4308 // ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b Register Class...
4309 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b[] = {
4310 AArch64::Z1_Z2, AArch64::Z3_Z4, AArch64::Z5_Z6, AArch64::Z31_Z0,
4311 };
4312
4313 // ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b Bit set.
4314 const uint8_t ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bBits[] = {
4315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x40,
4316 };
4317
4318 // ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K Register Class...
4319 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K[] = {
4320 AArch64::Z19_Z20, AArch64::Z21_Z22, AArch64::Z27_Z28, AArch64::Z29_Z30,
4321 };
4322
4323 // ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K Bit set.
4324 const uint8_t ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KBits[] = {
4325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14,
4326 };
4327
4328 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2 Register Class...
4329 const MCPhysReg ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2[] = {
4330 AArch64::Z1_Z2, AArch64::Z3_Z4, AArch64::Z5_Z6, AArch64::Z7_Z8,
4331 };
4332
4333 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2 Bit set.
4334 const uint8_t ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2Bits[] = {
4335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
4336 };
4337
4338 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4 Register Class...
4339 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4[] = {
4340 AArch64::Z3_Z4, AArch64::Z7_Z8, AArch64::Z11_Z12, AArch64::Z15_Z16,
4341 };
4342
4343 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4 Bit set.
4344 const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4Bits[] = {
4345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x44,
4346 };
4347
4348 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_K Register Class...
4349 const MCPhysReg ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_K[] = {
4350 AArch64::Z20_Z28, AArch64::Z20_Z21, AArch64::Z28_Z29,
4351 };
4352
4353 // ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_K Bit set.
4354 const uint8_t ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_KBits[] = {
4355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
4356 };
4357
4358 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Register Class...
4359 const MCPhysReg ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi[] = {
4360 AArch64::Z21_Z22, AArch64::Z23_Z24, AArch64::Z29_Z30,
4361 };
4362
4363 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Bit set.
4364 const uint8_t ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits[] = {
4365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x10,
4366 };
4367
4368 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b Register Class...
4369 const MCPhysReg ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b[] = {
4370 AArch64::Z1_Z2, AArch64::Z3_Z4, AArch64::Z5_Z6,
4371 };
4372
4373 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b Bit set.
4374 const uint8_t ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bBits[] = {
4375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
4376 };
4377
4378 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
4379 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4[] = {
4380 AArch64::Z3_Z4, AArch64::Z7_Z8, AArch64::Z11_Z12,
4381 };
4382
4383 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
4384 const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
4385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x04,
4386 };
4387
4388 // ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
4389 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4[] = {
4390 AArch64::Z16_Z24, AArch64::Z20_Z28,
4391 };
4392
4393 // ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
4394 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
4395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
4396 };
4397
4398 // ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
4399 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4[] = {
4400 AArch64::Z0_Z8, AArch64::Z4_Z12,
4401 };
4402
4403 // ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
4404 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
4405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
4406 };
4407
4408 // ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_K Register Class...
4409 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_K[] = {
4410 AArch64::Z20_Z28, AArch64::Z22_Z30,
4411 };
4412
4413 // ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_K Bit set.
4414 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_KBits[] = {
4415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
4416 };
4417
4418 // ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3b Register Class...
4419 const MCPhysReg ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3b[] = {
4420 AArch64::Z0_Z1, AArch64::Z4_Z5,
4421 };
4422
4423 // ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3b Bit set.
4424 const uint8_t ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3bBits[] = {
4425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
4426 };
4427
4428 // ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_K Register Class...
4429 const MCPhysReg ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_K[] = {
4430 AArch64::Z20_Z21, AArch64::Z28_Z29,
4431 };
4432
4433 // ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_K Bit set.
4434 const uint8_t ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_KBits[] = {
4435 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08,
4436 };
4437
4438 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K Register Class...
4439 const MCPhysReg ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K[] = {
4440 AArch64::Z21_Z22, AArch64::Z29_Z30,
4441 };
4442
4443 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K Bit set.
4444 const uint8_t ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KBits[] = {
4445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10,
4446 };
4447
4448 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4 Register Class...
4449 const MCPhysReg ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4[] = {
4450 AArch64::Z23_Z24, AArch64::Z31_Z0,
4451 };
4452
4453 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4 Bit set.
4454 const uint8_t ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits[] = {
4455 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40,
4456 };
4457
4458 // ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b Register Class...
4459 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b[] = {
4460 AArch64::Z3_Z4, AArch64::Z31_Z0,
4461 };
4462
4463 // ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b Bit set.
4464 const uint8_t ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bBits[] = {
4465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x40,
4466 };
4467
4468 // ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_K Register Class...
4469 const MCPhysReg ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_K[] = {
4470 AArch64::Z19_Z20, AArch64::Z27_Z28,
4471 };
4472
4473 // ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_K Bit set.
4474 const uint8_t ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_KBits[] = {
4475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04,
4476 };
4477
4478 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4 Register Class...
4479 const MCPhysReg ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4[] = {
4480 AArch64::Z3_Z4, AArch64::Z7_Z8,
4481 };
4482
4483 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4 Bit set.
4484 const uint8_t ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4Bits[] = {
4485 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44,
4486 };
4487
4488 // ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_K Register Class...
4489 const MCPhysReg ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_K[] = {
4490 AArch64::Z20_Z28,
4491 };
4492
4493 // ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_K Bit set.
4494 const uint8_t ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_KBits[] = {
4495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
4496 };
4497
4498 // ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
4499 const MCPhysReg ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_K[] = {
4500 AArch64::Z31_Z0,
4501 };
4502
4503 // ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
4504 const uint8_t ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
4505 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
4506 };
4507
4508 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
4509 const MCPhysReg ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4[] = {
4510 AArch64::Z23_Z24,
4511 };
4512
4513 // ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
4514 const uint8_t ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
4515 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
4516 };
4517
4518 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b Register Class...
4519 const MCPhysReg ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b[] = {
4520 AArch64::Z3_Z4,
4521 };
4522
4523 // ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b Bit set.
4524 const uint8_t ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bBits[] = {
4525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
4526 };
4527
4528 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Register Class...
4529 const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Hi[] = {
4530 AArch64::Z15_Z16,
4531 };
4532
4533 // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Bit set.
4534 const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits[] = {
4535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
4536 };
4537
4538 // MPR64 Register Class...
4539 const MCPhysReg MPR64[] = {
4540 AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7,
4541 };
4542
4543 // MPR64 Bit set.
4544 const uint8_t MPR64Bits[] = {
4545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
4546 };
4547
4548 // QQQ Register Class...
4549 const MCPhysReg QQQ[] = {
4550 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1,
4551 };
4552
4553 // QQQ Bit set.
4554 const uint8_t QQQBits[] = {
4555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
4556 };
4557
4558 // ZPR3 Register Class...
4559 const MCPhysReg ZPR3[] = {
4560 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
4561 };
4562
4563 // ZPR3 Bit set.
4564 const uint8_t ZPR3Bits[] = {
4565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
4566 };
4567
4568 // QQQ_with_dsub1_in_FPR64_lo Register Class...
4569 const MCPhysReg QQQ_with_dsub1_in_FPR64_lo[] = {
4570 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1,
4571 };
4572
4573 // QQQ_with_dsub1_in_FPR64_lo Bit set.
4574 const uint8_t QQQ_with_dsub1_in_FPR64_loBits[] = {
4575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x04,
4576 };
4577
4578 // QQQ_with_dsub2_in_FPR64_lo Register Class...
4579 const MCPhysReg QQQ_with_dsub2_in_FPR64_lo[] = {
4580 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1,
4581 };
4582
4583 // QQQ_with_dsub2_in_FPR64_lo Bit set.
4584 const uint8_t QQQ_with_dsub2_in_FPR64_loBits[] = {
4585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x06,
4586 };
4587
4588 // QQQ_with_qsub0_in_FPR128_lo Register Class...
4589 const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
4590 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17,
4591 };
4592
4593 // QQQ_with_qsub0_in_FPR128_lo Bit set.
4594 const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
4595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
4596 };
4597
4598 // ZPR3_with_dsub1_in_FPR64_lo Register Class...
4599 const MCPhysReg ZPR3_with_dsub1_in_FPR64_lo[] = {
4600 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1,
4601 };
4602
4603 // ZPR3_with_dsub1_in_FPR64_lo Bit set.
4604 const uint8_t ZPR3_with_dsub1_in_FPR64_loBits[] = {
4605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, 0x00, 0x40,
4606 };
4607
4608 // ZPR3_with_dsub2_in_FPR64_lo Register Class...
4609 const MCPhysReg ZPR3_with_dsub2_in_FPR64_lo[] = {
4610 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
4611 };
4612
4613 // ZPR3_with_dsub2_in_FPR64_lo Bit set.
4614 const uint8_t ZPR3_with_dsub2_in_FPR64_loBits[] = {
4615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 0x00, 0x60,
4616 };
4617
4618 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2 Register Class...
4619 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2[] = {
4620 AArch64::Z0_Z1_Z2, AArch64::Z2_Z3_Z4, AArch64::Z4_Z5_Z6, AArch64::Z6_Z7_Z8, AArch64::Z8_Z9_Z10, AArch64::Z10_Z11_Z12, AArch64::Z12_Z13_Z14, AArch64::Z14_Z15_Z16, AArch64::Z16_Z17_Z18, AArch64::Z18_Z19_Z20, AArch64::Z20_Z21_Z22, AArch64::Z22_Z23_Z24, AArch64::Z24_Z25_Z26, AArch64::Z26_Z27_Z28, AArch64::Z28_Z29_Z30, AArch64::Z30_Z31_Z0,
4621 };
4622
4623 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2 Bit set.
4624 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2Bits[] = {
4625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x2a,
4626 };
4627
4628 // ZPR3_with_zsub1_in_ZPRMul2 Register Class...
4629 const MCPhysReg ZPR3_with_zsub1_in_ZPRMul2[] = {
4630 AArch64::Z1_Z2_Z3, AArch64::Z3_Z4_Z5, AArch64::Z5_Z6_Z7, AArch64::Z7_Z8_Z9, AArch64::Z9_Z10_Z11, AArch64::Z11_Z12_Z13, AArch64::Z13_Z14_Z15, AArch64::Z15_Z16_Z17, AArch64::Z17_Z18_Z19, AArch64::Z19_Z20_Z21, AArch64::Z21_Z22_Z23, AArch64::Z23_Z24_Z25, AArch64::Z25_Z26_Z27, AArch64::Z27_Z28_Z29, AArch64::Z29_Z30_Z31, AArch64::Z31_Z0_Z1,
4631 };
4632
4633 // ZPR3_with_zsub1_in_ZPRMul2 Bit set.
4634 const uint8_t ZPR3_with_zsub1_in_ZPRMul2Bits[] = {
4635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x55,
4636 };
4637
4638 // ZPR3_with_zsub_in_FPR128_lo Register Class...
4639 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
4640 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17,
4641 };
4642
4643 // ZPR3_with_zsub_in_FPR128_lo Bit set.
4644 const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
4645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
4646 };
4647
4648 // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_lo Register Class...
4649 const MCPhysReg QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_lo[] = {
4650 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1,
4651 };
4652
4653 // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_lo Bit set.
4654 const uint8_t QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loBits[] = {
4655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x04,
4656 };
4657
4658 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_lo Register Class...
4659 const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_lo[] = {
4660 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
4661 };
4662
4663 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_lo Bit set.
4664 const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loBits[] = {
4665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
4666 };
4667
4668 // ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_lo Register Class...
4669 const MCPhysReg ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_lo[] = {
4670 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1,
4671 };
4672
4673 // ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_lo Bit set.
4674 const uint8_t ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_loBits[] = {
4675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 0x00, 0x40,
4676 };
4677
4678 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_lo Register Class...
4679 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_lo[] = {
4680 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
4681 };
4682
4683 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_lo Bit set.
4684 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_loBits[] = {
4685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f,
4686 };
4687
4688 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_lo Register Class...
4689 const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_lo[] = {
4690 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15,
4691 };
4692
4693 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_lo Bit set.
4694 const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loBits[] = {
4695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
4696 };
4697
4698 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_lo Register Class...
4699 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_lo[] = {
4700 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15,
4701 };
4702
4703 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_lo Bit set.
4704 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_loBits[] = {
4705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
4706 };
4707
4708 // QQQ_with_qsub0_in_FPR128_0to7 Register Class...
4709 const MCPhysReg QQQ_with_qsub0_in_FPR128_0to7[] = {
4710 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9,
4711 };
4712
4713 // QQQ_with_qsub0_in_FPR128_0to7 Bit set.
4714 const uint8_t QQQ_with_qsub0_in_FPR128_0to7Bits[] = {
4715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
4716 };
4717
4718 // QQQ_with_qsub1_in_FPR128_0to7 Register Class...
4719 const MCPhysReg QQQ_with_qsub1_in_FPR128_0to7[] = {
4720 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q31_Q0_Q1,
4721 };
4722
4723 // QQQ_with_qsub1_in_FPR128_0to7 Bit set.
4724 const uint8_t QQQ_with_qsub1_in_FPR128_0to7Bits[] = {
4725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x04,
4726 };
4727
4728 // QQQ_with_qsub2_in_FPR128_0to7 Register Class...
4729 const MCPhysReg QQQ_with_qsub2_in_FPR128_0to7[] = {
4730 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1,
4731 };
4732
4733 // QQQ_with_qsub2_in_FPR128_0to7 Bit set.
4734 const uint8_t QQQ_with_qsub2_in_FPR128_0to7Bits[] = {
4735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x00, 0x06,
4736 };
4737
4738 // ZPR3_with_qsub1_in_FPR128_0to7 Register Class...
4739 const MCPhysReg ZPR3_with_qsub1_in_FPR128_0to7[] = {
4740 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1,
4741 };
4742
4743 // ZPR3_with_qsub1_in_FPR128_0to7 Bit set.
4744 const uint8_t ZPR3_with_qsub1_in_FPR128_0to7Bits[] = {
4745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x40,
4746 };
4747
4748 // ZPR3_with_qsub2_in_FPR128_0to7 Register Class...
4749 const MCPhysReg ZPR3_with_qsub2_in_FPR128_0to7[] = {
4750 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
4751 };
4752
4753 // ZPR3_with_qsub2_in_FPR128_0to7 Bit set.
4754 const uint8_t ZPR3_with_qsub2_in_FPR128_0to7Bits[] = {
4755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x00, 0x60,
4756 };
4757
4758 // ZPR3_with_zsub0_in_ZPRMul4 Register Class...
4759 const MCPhysReg ZPR3_with_zsub0_in_ZPRMul4[] = {
4760 AArch64::Z0_Z1_Z2, AArch64::Z4_Z5_Z6, AArch64::Z8_Z9_Z10, AArch64::Z12_Z13_Z14, AArch64::Z16_Z17_Z18, AArch64::Z20_Z21_Z22, AArch64::Z24_Z25_Z26, AArch64::Z28_Z29_Z30,
4761 };
4762
4763 // ZPR3_with_zsub0_in_ZPRMul4 Bit set.
4764 const uint8_t ZPR3_with_zsub0_in_ZPRMul4Bits[] = {
4765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x88, 0x88, 0x08,
4766 };
4767
4768 // ZPR3_with_zsub0_in_ZPR_K Register Class...
4769 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K[] = {
4770 AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
4771 };
4772
4773 // ZPR3_with_zsub0_in_ZPR_K Bit set.
4774 const uint8_t ZPR3_with_zsub0_in_ZPR_KBits[] = {
4775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x78,
4776 };
4777
4778 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi Register Class...
4779 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi[] = {
4780 AArch64::Z16_Z17_Z18, AArch64::Z18_Z19_Z20, AArch64::Z20_Z21_Z22, AArch64::Z22_Z23_Z24, AArch64::Z24_Z25_Z26, AArch64::Z26_Z27_Z28, AArch64::Z28_Z29_Z30, AArch64::Z30_Z31_Z0,
4781 };
4782
4783 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi Bit set.
4784 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiBits[] = {
4785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
4786 };
4787
4788 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo Register Class...
4789 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo[] = {
4790 AArch64::Z0_Z1_Z2, AArch64::Z2_Z3_Z4, AArch64::Z4_Z5_Z6, AArch64::Z6_Z7_Z8, AArch64::Z8_Z9_Z10, AArch64::Z10_Z11_Z12, AArch64::Z12_Z13_Z14, AArch64::Z14_Z15_Z16,
4791 };
4792
4793 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo Bit set.
4794 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_LoBits[] = {
4795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
4796 };
4797
4798 // ZPR3_with_zsub1_in_ZPRMul2_Hi Register Class...
4799 const MCPhysReg ZPR3_with_zsub1_in_ZPRMul2_Hi[] = {
4800 AArch64::Z15_Z16_Z17, AArch64::Z17_Z18_Z19, AArch64::Z19_Z20_Z21, AArch64::Z21_Z22_Z23, AArch64::Z23_Z24_Z25, AArch64::Z25_Z26_Z27, AArch64::Z27_Z28_Z29, AArch64::Z29_Z30_Z31,
4801 };
4802
4803 // ZPR3_with_zsub1_in_ZPRMul2_Hi Bit set.
4804 const uint8_t ZPR3_with_zsub1_in_ZPRMul2_HiBits[] = {
4805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x15,
4806 };
4807
4808 // ZPR3_with_zsub1_in_ZPRMul2_Lo Register Class...
4809 const MCPhysReg ZPR3_with_zsub1_in_ZPRMul2_Lo[] = {
4810 AArch64::Z1_Z2_Z3, AArch64::Z3_Z4_Z5, AArch64::Z5_Z6_Z7, AArch64::Z7_Z8_Z9, AArch64::Z9_Z10_Z11, AArch64::Z11_Z12_Z13, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1,
4811 };
4812
4813 // ZPR3_with_zsub1_in_ZPRMul2_Lo Bit set.
4814 const uint8_t ZPR3_with_zsub1_in_ZPRMul2_LoBits[] = {
4815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 0x00, 0x40,
4816 };
4817
4818 // ZPR3_with_zsub1_in_ZPRMul4 Register Class...
4819 const MCPhysReg ZPR3_with_zsub1_in_ZPRMul4[] = {
4820 AArch64::Z3_Z4_Z5, AArch64::Z7_Z8_Z9, AArch64::Z11_Z12_Z13, AArch64::Z15_Z16_Z17, AArch64::Z19_Z20_Z21, AArch64::Z23_Z24_Z25, AArch64::Z27_Z28_Z29, AArch64::Z31_Z0_Z1,
4821 };
4822
4823 // ZPR3_with_zsub1_in_ZPRMul4 Bit set.
4824 const uint8_t ZPR3_with_zsub1_in_ZPRMul4Bits[] = {
4825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x44,
4826 };
4827
4828 // ZPR3_with_zsub1_in_ZPR_K Register Class...
4829 const MCPhysReg ZPR3_with_zsub1_in_ZPR_K[] = {
4830 AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0,
4831 };
4832
4833 // ZPR3_with_zsub1_in_ZPR_K Bit set.
4834 const uint8_t ZPR3_with_zsub1_in_ZPR_KBits[] = {
4835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x3c,
4836 };
4837
4838 // ZPR3_with_zsub2_in_ZPRMul2_Hi Register Class...
4839 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul2_Hi[] = {
4840 AArch64::Z14_Z15_Z16, AArch64::Z16_Z17_Z18, AArch64::Z18_Z19_Z20, AArch64::Z20_Z21_Z22, AArch64::Z22_Z23_Z24, AArch64::Z24_Z25_Z26, AArch64::Z26_Z27_Z28, AArch64::Z28_Z29_Z30,
4841 };
4842
4843 // ZPR3_with_zsub2_in_ZPRMul2_Hi Bit set.
4844 const uint8_t ZPR3_with_zsub2_in_ZPRMul2_HiBits[] = {
4845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0x0a,
4846 };
4847
4848 // ZPR3_with_zsub2_in_ZPRMul2_Lo Register Class...
4849 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul2_Lo[] = {
4850 AArch64::Z0_Z1_Z2, AArch64::Z2_Z3_Z4, AArch64::Z4_Z5_Z6, AArch64::Z6_Z7_Z8, AArch64::Z8_Z9_Z10, AArch64::Z10_Z11_Z12, AArch64::Z12_Z13_Z14, AArch64::Z30_Z31_Z0,
4851 };
4852
4853 // ZPR3_with_zsub2_in_ZPRMul2_Lo Bit set.
4854 const uint8_t ZPR3_with_zsub2_in_ZPRMul2_LoBits[] = {
4855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a, 0x00, 0x20,
4856 };
4857
4858 // ZPR3_with_zsub2_in_ZPRMul4 Register Class...
4859 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul4[] = {
4860 AArch64::Z2_Z3_Z4, AArch64::Z6_Z7_Z8, AArch64::Z10_Z11_Z12, AArch64::Z14_Z15_Z16, AArch64::Z18_Z19_Z20, AArch64::Z22_Z23_Z24, AArch64::Z26_Z27_Z28, AArch64::Z30_Z31_Z0,
4861 };
4862
4863 // ZPR3_with_zsub2_in_ZPRMul4 Bit set.
4864 const uint8_t ZPR3_with_zsub2_in_ZPRMul4Bits[] = {
4865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22,
4866 };
4867
4868 // ZPR3_with_zsub2_in_ZPR_K Register Class...
4869 const MCPhysReg ZPR3_with_zsub2_in_ZPR_K[] = {
4870 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
4871 };
4872
4873 // ZPR3_with_zsub2_in_ZPR_K Bit set.
4874 const uint8_t ZPR3_with_zsub2_in_ZPR_KBits[] = {
4875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e,
4876 };
4877
4878 // ZPR3_with_zsub_in_FPR128_0to7 Register Class...
4879 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7[] = {
4880 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9,
4881 };
4882
4883 // ZPR3_with_zsub_in_FPR128_0to7 Bit set.
4884 const uint8_t ZPR3_with_zsub_in_FPR128_0to7Bits[] = {
4885 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
4886 };
4887
4888 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2 Register Class...
4889 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2[] = {
4890 AArch64::Z1_Z2_Z3, AArch64::Z3_Z4_Z5, AArch64::Z5_Z6_Z7, AArch64::Z7_Z8_Z9, AArch64::Z9_Z10_Z11, AArch64::Z11_Z12_Z13, AArch64::Z13_Z14_Z15, AArch64::Z15_Z16_Z17,
4891 };
4892
4893 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2 Bit set.
4894 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2Bits[] = {
4895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
4896 };
4897
4898 // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7 Register Class...
4899 const MCPhysReg QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7[] = {
4900 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q31_Q0_Q1,
4901 };
4902
4903 // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7 Bit set.
4904 const uint8_t QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7Bits[] = {
4905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x00, 0x04,
4906 };
4907
4908 // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7 Register Class...
4909 const MCPhysReg QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7[] = {
4910 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8,
4911 };
4912
4913 // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7 Bit set.
4914 const uint8_t QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7Bits[] = {
4915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
4916 };
4917
4918 // ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7 Register Class...
4919 const MCPhysReg ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7[] = {
4920 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1,
4921 };
4922
4923 // ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7 Bit set.
4924 const uint8_t ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7Bits[] = {
4925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x00, 0x40,
4926 };
4927
4928 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Register Class...
4929 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi[] = {
4930 AArch64::Z16_Z17_Z18, AArch64::Z18_Z19_Z20, AArch64::Z20_Z21_Z22, AArch64::Z22_Z23_Z24, AArch64::Z24_Z25_Z26, AArch64::Z26_Z27_Z28, AArch64::Z28_Z29_Z30,
4931 };
4932
4933 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Bit set.
4934 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits[] = {
4935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a,
4936 };
4937
4938 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7 Register Class...
4939 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7[] = {
4940 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8,
4941 };
4942
4943 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7 Bit set.
4944 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7Bits[] = {
4945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
4946 };
4947
4948 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Lo Register Class...
4949 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Lo[] = {
4950 AArch64::Z1_Z2_Z3, AArch64::Z3_Z4_Z5, AArch64::Z5_Z6_Z7, AArch64::Z7_Z8_Z9, AArch64::Z9_Z10_Z11, AArch64::Z11_Z12_Z13, AArch64::Z13_Z14_Z15,
4951 };
4952
4953 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Lo Bit set.
4954 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_LoBits[] = {
4955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
4956 };
4957
4958 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo Register Class...
4959 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo[] = {
4960 AArch64::Z0_Z1_Z2, AArch64::Z2_Z3_Z4, AArch64::Z4_Z5_Z6, AArch64::Z6_Z7_Z8, AArch64::Z8_Z9_Z10, AArch64::Z10_Z11_Z12, AArch64::Z12_Z13_Z14,
4961 };
4962
4963 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo Bit set.
4964 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_LoBits[] = {
4965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a,
4966 };
4967
4968 // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7 Register Class...
4969 const MCPhysReg QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7[] = {
4970 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
4971 };
4972
4973 // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7 Bit set.
4974 const uint8_t QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7Bits[] = {
4975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
4976 };
4977
4978 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_K Register Class...
4979 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_K[] = {
4980 AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0,
4981 };
4982
4983 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_K Bit set.
4984 const uint8_t ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_KBits[] = {
4985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x38,
4986 };
4987
4988 // ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K Register Class...
4989 const MCPhysReg ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K[] = {
4990 AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
4991 };
4992
4993 // ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K Bit set.
4994 const uint8_t ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KBits[] = {
4995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1c,
4996 };
4997
4998 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7 Register Class...
4999 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7[] = {
5000 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
5001 };
5002
5003 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7 Bit set.
5004 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7Bits[] = {
5005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
5006 };
5007
5008 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2 Register Class...
5009 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2[] = {
5010 AArch64::Z21_Z22_Z23, AArch64::Z23_Z24_Z25, AArch64::Z29_Z30_Z31, AArch64::Z31_Z0_Z1,
5011 };
5012
5013 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2 Bit set.
5014 const uint8_t ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2Bits[] = {
5015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x50,
5016 };
5017
5018 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K Register Class...
5019 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K[] = {
5020 AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
5021 };
5022
5023 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K Bit set.
5024 const uint8_t ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KBits[] = {
5025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18,
5026 };
5027
5028 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
5029 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
5030 AArch64::Z16_Z17_Z18, AArch64::Z20_Z21_Z22, AArch64::Z24_Z25_Z26, AArch64::Z28_Z29_Z30,
5031 };
5032
5033 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
5034 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
5035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
5036 };
5037
5038 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4 Register Class...
5039 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4[] = {
5040 AArch64::Z18_Z19_Z20, AArch64::Z22_Z23_Z24, AArch64::Z26_Z27_Z28, AArch64::Z30_Z31_Z0,
5041 };
5042
5043 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4 Bit set.
5044 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits[] = {
5045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22,
5046 };
5047
5048 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
5049 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
5050 AArch64::Z0_Z1_Z2, AArch64::Z4_Z5_Z6, AArch64::Z8_Z9_Z10, AArch64::Z12_Z13_Z14,
5051 };
5052
5053 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
5054 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
5055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
5056 };
5057
5058 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
5059 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
5060 AArch64::Z20_Z21_Z22, AArch64::Z22_Z23_Z24, AArch64::Z28_Z29_Z30, AArch64::Z30_Z31_Z0,
5061 };
5062
5063 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
5064 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
5065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x28,
5066 };
5067
5068 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
5069 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
5070 AArch64::Z0_Z1_Z2, AArch64::Z2_Z3_Z4, AArch64::Z4_Z5_Z6, AArch64::Z6_Z7_Z8,
5071 };
5072
5073 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
5074 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
5075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
5076 };
5077
5078 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
5079 const MCPhysReg ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
5080 AArch64::Z15_Z16_Z17, AArch64::Z19_Z20_Z21, AArch64::Z23_Z24_Z25, AArch64::Z27_Z28_Z29,
5081 };
5082
5083 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
5084 const uint8_t ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
5085 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x44, 0x04,
5086 };
5087
5088 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
5089 const MCPhysReg ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
5090 AArch64::Z3_Z4_Z5, AArch64::Z7_Z8_Z9, AArch64::Z11_Z12_Z13, AArch64::Z31_Z0_Z1,
5091 };
5092
5093 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
5094 const uint8_t ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
5095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x04, 0x00, 0x40,
5096 };
5097
5098 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
5099 const MCPhysReg ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
5100 AArch64::Z19_Z20_Z21, AArch64::Z21_Z22_Z23, AArch64::Z27_Z28_Z29, AArch64::Z29_Z30_Z31,
5101 };
5102
5103 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
5104 const uint8_t ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
5105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14,
5106 };
5107
5108 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
5109 const MCPhysReg ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
5110 AArch64::Z1_Z2_Z3, AArch64::Z3_Z4_Z5, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1,
5111 };
5112
5113 // ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
5114 const uint8_t ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
5115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x40,
5116 };
5117
5118 // ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
5119 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4[] = {
5120 AArch64::Z14_Z15_Z16, AArch64::Z18_Z19_Z20, AArch64::Z22_Z23_Z24, AArch64::Z26_Z27_Z28,
5121 };
5122
5123 // ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
5124 const uint8_t ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
5125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x22, 0x02,
5126 };
5127
5128 // ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
5129 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4[] = {
5130 AArch64::Z2_Z3_Z4, AArch64::Z6_Z7_Z8, AArch64::Z10_Z11_Z12, AArch64::Z30_Z31_Z0,
5131 };
5132
5133 // ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
5134 const uint8_t ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
5135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x02, 0x00, 0x20,
5136 };
5137
5138 // ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b Register Class...
5139 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b[] = {
5140 AArch64::Z0_Z1_Z2, AArch64::Z2_Z3_Z4, AArch64::Z4_Z5_Z6, AArch64::Z30_Z31_Z0,
5141 };
5142
5143 // ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b Bit set.
5144 const uint8_t ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bBits[] = {
5145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, 0x00, 0x00, 0x20,
5146 };
5147
5148 // ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_K Register Class...
5149 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_K[] = {
5150 AArch64::Z18_Z19_Z20, AArch64::Z20_Z21_Z22, AArch64::Z26_Z27_Z28, AArch64::Z28_Z29_Z30,
5151 };
5152
5153 // ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_K Bit set.
5154 const uint8_t ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_KBits[] = {
5155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a,
5156 };
5157
5158 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2 Register Class...
5159 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2[] = {
5160 AArch64::Z1_Z2_Z3, AArch64::Z3_Z4_Z5, AArch64::Z5_Z6_Z7, AArch64::Z7_Z8_Z9,
5161 };
5162
5163 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2 Bit set.
5164 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2Bits[] = {
5165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
5166 };
5167
5168 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4 Register Class...
5169 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4[] = {
5170 AArch64::Z3_Z4_Z5, AArch64::Z7_Z8_Z9, AArch64::Z11_Z12_Z13, AArch64::Z15_Z16_Z17,
5171 };
5172
5173 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4 Bit set.
5174 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4Bits[] = {
5175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x44,
5176 };
5177
5178 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4 Register Class...
5179 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4[] = {
5180 AArch64::Z2_Z3_Z4, AArch64::Z6_Z7_Z8, AArch64::Z10_Z11_Z12, AArch64::Z14_Z15_Z16,
5181 };
5182
5183 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4 Bit set.
5184 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4Bits[] = {
5185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22,
5186 };
5187
5188 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_Hi Register Class...
5189 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_Hi[] = {
5190 AArch64::Z21_Z22_Z23, AArch64::Z23_Z24_Z25, AArch64::Z29_Z30_Z31,
5191 };
5192
5193 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_Hi Bit set.
5194 const uint8_t ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_HiBits[] = {
5195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x10,
5196 };
5197
5198 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
5199 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4[] = {
5200 AArch64::Z18_Z19_Z20, AArch64::Z22_Z23_Z24, AArch64::Z26_Z27_Z28,
5201 };
5202
5203 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
5204 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
5205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x02,
5206 };
5207
5208 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Register Class...
5209 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi[] = {
5210 AArch64::Z20_Z21_Z22, AArch64::Z22_Z23_Z24, AArch64::Z28_Z29_Z30,
5211 };
5212
5213 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Bit set.
5214 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits[] = {
5215 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x08,
5216 };
5217
5218 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
5219 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
5220 AArch64::Z1_Z2_Z3, AArch64::Z3_Z4_Z5, AArch64::Z5_Z6_Z7,
5221 };
5222
5223 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
5224 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
5225 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
5226 };
5227
5228 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b Register Class...
5229 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b[] = {
5230 AArch64::Z0_Z1_Z2, AArch64::Z2_Z3_Z4, AArch64::Z4_Z5_Z6,
5231 };
5232
5233 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b Bit set.
5234 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bBits[] = {
5235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a,
5236 };
5237
5238 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
5239 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
5240 AArch64::Z3_Z4_Z5, AArch64::Z7_Z8_Z9, AArch64::Z11_Z12_Z13,
5241 };
5242
5243 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
5244 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
5245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x04,
5246 };
5247
5248 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
5249 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4[] = {
5250 AArch64::Z2_Z3_Z4, AArch64::Z6_Z7_Z8, AArch64::Z10_Z11_Z12,
5251 };
5252
5253 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
5254 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
5255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x02,
5256 };
5257
5258 // ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K Register Class...
5259 const MCPhysReg ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K[] = {
5260 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
5261 };
5262
5263 // ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K Bit set.
5264 const uint8_t ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KBits[] = {
5265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
5266 };
5267
5268 // ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3b Register Class...
5269 const MCPhysReg ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3b[] = {
5270 AArch64::Z0_Z1_Z2, AArch64::Z4_Z5_Z6,
5271 };
5272
5273 // ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3b Bit set.
5274 const uint8_t ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3bBits[] = {
5275 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
5276 };
5277
5278 // ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_K Register Class...
5279 const MCPhysReg ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_K[] = {
5280 AArch64::Z20_Z21_Z22, AArch64::Z28_Z29_Z30,
5281 };
5282
5283 // ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_K Bit set.
5284 const uint8_t ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_KBits[] = {
5285 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08,
5286 };
5287
5288 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4 Register Class...
5289 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4[] = {
5290 AArch64::Z23_Z24_Z25, AArch64::Z31_Z0_Z1,
5291 };
5292
5293 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4 Bit set.
5294 const uint8_t ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4Bits[] = {
5295 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40,
5296 };
5297
5298 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
5299 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
5300 AArch64::Z21_Z22_Z23, AArch64::Z29_Z30_Z31,
5301 };
5302
5303 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
5304 const uint8_t ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
5305 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10,
5306 };
5307
5308 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4 Register Class...
5309 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4[] = {
5310 AArch64::Z22_Z23_Z24, AArch64::Z30_Z31_Z0,
5311 };
5312
5313 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4 Bit set.
5314 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits[] = {
5315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20,
5316 };
5317
5318 // ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b Register Class...
5319 const MCPhysReg ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b[] = {
5320 AArch64::Z3_Z4_Z5, AArch64::Z31_Z0_Z1,
5321 };
5322
5323 // ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b Bit set.
5324 const uint8_t ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bBits[] = {
5325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x40,
5326 };
5327
5328 // ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_K Register Class...
5329 const MCPhysReg ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_K[] = {
5330 AArch64::Z19_Z20_Z21, AArch64::Z27_Z28_Z29,
5331 };
5332
5333 // ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_K Bit set.
5334 const uint8_t ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_KBits[] = {
5335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04,
5336 };
5337
5338 // ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b Register Class...
5339 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b[] = {
5340 AArch64::Z2_Z3_Z4, AArch64::Z30_Z31_Z0,
5341 };
5342
5343 // ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b Bit set.
5344 const uint8_t ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bBits[] = {
5345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x20,
5346 };
5347
5348 // ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_K Register Class...
5349 const MCPhysReg ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_K[] = {
5350 AArch64::Z18_Z19_Z20, AArch64::Z26_Z27_Z28,
5351 };
5352
5353 // ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_K Bit set.
5354 const uint8_t ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_KBits[] = {
5355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02,
5356 };
5357
5358 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4 Register Class...
5359 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4[] = {
5360 AArch64::Z3_Z4_Z5, AArch64::Z7_Z8_Z9,
5361 };
5362
5363 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4 Bit set.
5364 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4Bits[] = {
5365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44,
5366 };
5367
5368 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4 Register Class...
5369 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4[] = {
5370 AArch64::Z2_Z3_Z4, AArch64::Z6_Z7_Z8,
5371 };
5372
5373 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4 Bit set.
5374 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4Bits[] = {
5375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22,
5376 };
5377
5378 // ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K Register Class...
5379 const MCPhysReg ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K[] = {
5380 AArch64::Z31_Z0_Z1,
5381 };
5382
5383 // ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K Bit set.
5384 const uint8_t ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KBits[] = {
5385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
5386 };
5387
5388 // ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi Register Class...
5389 const MCPhysReg ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi[] = {
5390 AArch64::Z30_Z31_Z0,
5391 };
5392
5393 // ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi Bit set.
5394 const uint8_t ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiBits[] = {
5395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
5396 };
5397
5398 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
5399 const MCPhysReg ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
5400 AArch64::Z23_Z24_Z25,
5401 };
5402
5403 // ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
5404 const uint8_t ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
5405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
5406 };
5407
5408 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
5409 const MCPhysReg ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4[] = {
5410 AArch64::Z22_Z23_Z24,
5411 };
5412
5413 // ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
5414 const uint8_t ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
5415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
5416 };
5417
5418 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b Register Class...
5419 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b[] = {
5420 AArch64::Z3_Z4_Z5,
5421 };
5422
5423 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b Bit set.
5424 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bBits[] = {
5425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
5426 };
5427
5428 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b Register Class...
5429 const MCPhysReg ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b[] = {
5430 AArch64::Z2_Z3_Z4,
5431 };
5432
5433 // ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b Bit set.
5434 const uint8_t ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bBits[] = {
5435 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
5436 };
5437
5438 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Hi Register Class...
5439 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Hi[] = {
5440 AArch64::Z15_Z16_Z17,
5441 };
5442
5443 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Hi Bit set.
5444 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_HiBits[] = {
5445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
5446 };
5447
5448 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Register Class...
5449 const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Hi[] = {
5450 AArch64::Z14_Z15_Z16,
5451 };
5452
5453 // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Bit set.
5454 const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits[] = {
5455 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
5456 };
5457
5458 // QQQQ Register Class...
5459 const MCPhysReg QQQQ[] = {
5460 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
5461 };
5462
5463 // QQQQ Bit set.
5464 const uint8_t QQQQBits[] = {
5465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
5466 };
5467
5468 // ZPR4 Register Class...
5469 const MCPhysReg ZPR4[] = {
5470 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
5471 };
5472
5473 // ZPR4 Bit set.
5474 const uint8_t ZPR4Bits[] = {
5475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
5476 };
5477
5478 // QQQQ_with_dsub1_in_FPR64_lo Register Class...
5479 const MCPhysReg QQQQ_with_dsub1_in_FPR64_lo[] = {
5480 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2,
5481 };
5482
5483 // QQQQ_with_dsub1_in_FPR64_lo Bit set.
5484 const uint8_t QQQQ_with_dsub1_in_FPR64_loBits[] = {
5485 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x04,
5486 };
5487
5488 // QQQQ_with_dsub2_in_FPR64_lo Register Class...
5489 const MCPhysReg QQQQ_with_dsub2_in_FPR64_lo[] = {
5490 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
5491 };
5492
5493 // QQQQ_with_dsub2_in_FPR64_lo Bit set.
5494 const uint8_t QQQQ_with_dsub2_in_FPR64_loBits[] = {
5495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x06,
5496 };
5497
5498 // QQQQ_with_dsub3_in_FPR64_lo Register Class...
5499 const MCPhysReg QQQQ_with_dsub3_in_FPR64_lo[] = {
5500 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
5501 };
5502
5503 // QQQQ_with_dsub3_in_FPR64_lo Bit set.
5504 const uint8_t QQQQ_with_dsub3_in_FPR64_loBits[] = {
5505 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x00, 0x00, 0x07,
5506 };
5507
5508 // QQQQ_with_qsub0_in_FPR128_lo Register Class...
5509 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
5510 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18,
5511 };
5512
5513 // QQQQ_with_qsub0_in_FPR128_lo Bit set.
5514 const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
5515 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
5516 };
5517
5518 // ZPR4StridedOrContiguous Register Class...
5519 const MCPhysReg ZPR4StridedOrContiguous[] = {
5520 AArch64::Z0_Z4_Z8_Z12, AArch64::Z1_Z5_Z9_Z13, AArch64::Z2_Z6_Z10_Z14, AArch64::Z3_Z7_Z11_Z15, AArch64::Z16_Z20_Z24_Z28, AArch64::Z17_Z21_Z25_Z29, AArch64::Z18_Z22_Z26_Z30, AArch64::Z19_Z23_Z27_Z31, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15, AArch64::Z16_Z17_Z18_Z19, AArch64::Z20_Z21_Z22_Z23, AArch64::Z24_Z25_Z26_Z27, AArch64::Z28_Z29_Z30_Z31,
5521 };
5522
5523 // ZPR4StridedOrContiguous Bit set.
5524 const uint8_t ZPR4StridedOrContiguousBits[] = {
5525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x88, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
5526 };
5527
5528 // ZPR4_with_dsub1_in_FPR64_lo Register Class...
5529 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo[] = {
5530 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2,
5531 };
5532
5533 // ZPR4_with_dsub1_in_FPR64_lo Bit set.
5534 const uint8_t ZPR4_with_dsub1_in_FPR64_loBits[] = {
5535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, 0x00, 0x40,
5536 };
5537
5538 // ZPR4_with_dsub2_in_FPR64_lo Register Class...
5539 const MCPhysReg ZPR4_with_dsub2_in_FPR64_lo[] = {
5540 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
5541 };
5542
5543 // ZPR4_with_dsub2_in_FPR64_lo Bit set.
5544 const uint8_t ZPR4_with_dsub2_in_FPR64_loBits[] = {
5545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 0x00, 0x60,
5546 };
5547
5548 // ZPR4_with_dsub3_in_FPR64_lo Register Class...
5549 const MCPhysReg ZPR4_with_dsub3_in_FPR64_lo[] = {
5550 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
5551 };
5552
5553 // ZPR4_with_dsub3_in_FPR64_lo Bit set.
5554 const uint8_t ZPR4_with_dsub3_in_FPR64_loBits[] = {
5555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x0f, 0x00, 0x70,
5556 };
5557
5558 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2 Register Class...
5559 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2[] = {
5560 AArch64::Z0_Z1_Z2_Z3, AArch64::Z2_Z3_Z4_Z5, AArch64::Z4_Z5_Z6_Z7, AArch64::Z6_Z7_Z8_Z9, AArch64::Z8_Z9_Z10_Z11, AArch64::Z10_Z11_Z12_Z13, AArch64::Z12_Z13_Z14_Z15, AArch64::Z14_Z15_Z16_Z17, AArch64::Z16_Z17_Z18_Z19, AArch64::Z18_Z19_Z20_Z21, AArch64::Z20_Z21_Z22_Z23, AArch64::Z22_Z23_Z24_Z25, AArch64::Z24_Z25_Z26_Z27, AArch64::Z26_Z27_Z28_Z29, AArch64::Z28_Z29_Z30_Z31, AArch64::Z30_Z31_Z0_Z1,
5561 };
5562
5563 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2 Bit set.
5564 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2Bits[] = {
5565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x2a,
5566 };
5567
5568 // ZPR4_with_zsub1_in_ZPRMul2 Register Class...
5569 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul2[] = {
5570 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10, AArch64::Z9_Z10_Z11_Z12, AArch64::Z11_Z12_Z13_Z14, AArch64::Z13_Z14_Z15_Z16, AArch64::Z15_Z16_Z17_Z18, AArch64::Z17_Z18_Z19_Z20, AArch64::Z19_Z20_Z21_Z22, AArch64::Z21_Z22_Z23_Z24, AArch64::Z23_Z24_Z25_Z26, AArch64::Z25_Z26_Z27_Z28, AArch64::Z27_Z28_Z29_Z30, AArch64::Z29_Z30_Z31_Z0, AArch64::Z31_Z0_Z1_Z2,
5571 };
5572
5573 // ZPR4_with_zsub1_in_ZPRMul2 Bit set.
5574 const uint8_t ZPR4_with_zsub1_in_ZPRMul2Bits[] = {
5575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x55,
5576 };
5577
5578 // ZPR4_with_zsub_in_FPR128_lo Register Class...
5579 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
5580 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18,
5581 };
5582
5583 // ZPR4_with_zsub_in_FPR128_lo Bit set.
5584 const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
5585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
5586 };
5587
5588 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_lo Register Class...
5589 const MCPhysReg QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_lo[] = {
5590 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2,
5591 };
5592
5593 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_lo Bit set.
5594 const uint8_t QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loBits[] = {
5595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 0x00, 0x04,
5596 };
5597
5598 // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo Register Class...
5599 const MCPhysReg QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo[] = {
5600 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
5601 };
5602
5603 // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo Bit set.
5604 const uint8_t QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loBits[] = {
5605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x00, 0x00, 0x06,
5606 };
5607
5608 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_lo Register Class...
5609 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_lo[] = {
5610 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
5611 };
5612
5613 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_lo Bit set.
5614 const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loBits[] = {
5615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
5616 };
5617
5618 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_lo Register Class...
5619 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_lo[] = {
5620 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2,
5621 };
5622
5623 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_lo Bit set.
5624 const uint8_t ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_loBits[] = {
5625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 0x00, 0x40,
5626 };
5627
5628 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo Register Class...
5629 const MCPhysReg ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo[] = {
5630 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
5631 };
5632
5633 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo Bit set.
5634 const uint8_t ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loBits[] = {
5635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x0f, 0x00, 0x60,
5636 };
5637
5638 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_lo Register Class...
5639 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_lo[] = {
5640 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
5641 };
5642
5643 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_lo Bit set.
5644 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_loBits[] = {
5645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f,
5646 };
5647
5648 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo Register Class...
5649 const MCPhysReg QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo[] = {
5650 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2,
5651 };
5652
5653 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo Bit set.
5654 const uint8_t QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loBits[] = {
5655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x00, 0x00, 0x04,
5656 };
5657
5658 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_lo Register Class...
5659 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_lo[] = {
5660 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16,
5661 };
5662
5663 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_lo Bit set.
5664 const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loBits[] = {
5665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
5666 };
5667
5668 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo Register Class...
5669 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo[] = {
5670 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2,
5671 };
5672
5673 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo Bit set.
5674 const uint8_t ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loBits[] = {
5675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x0f, 0x00, 0x40,
5676 };
5677
5678 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_lo Register Class...
5679 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_lo[] = {
5680 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16,
5681 };
5682
5683 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_lo Bit set.
5684 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_loBits[] = {
5685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
5686 };
5687
5688 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_lo Register Class...
5689 const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_lo[] = {
5690 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15,
5691 };
5692
5693 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_lo Bit set.
5694 const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loBits[] = {
5695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff,
5696 };
5697
5698 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_lo Register Class...
5699 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_lo[] = {
5700 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15,
5701 };
5702
5703 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_lo Bit set.
5704 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_loBits[] = {
5705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x0f,
5706 };
5707
5708 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2 Register Class...
5709 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2[] = {
5710 AArch64::Z0_Z4_Z8_Z12, AArch64::Z2_Z6_Z10_Z14, AArch64::Z16_Z20_Z24_Z28, AArch64::Z18_Z22_Z26_Z30, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15, AArch64::Z16_Z17_Z18_Z19, AArch64::Z20_Z21_Z22_Z23, AArch64::Z24_Z25_Z26_Z27, AArch64::Z28_Z29_Z30_Z31,
5711 };
5712
5713 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2 Bit set.
5714 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2Bits[] = {
5715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x88, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
5716 };
5717
5718 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4 Register Class...
5719 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4[] = {
5720 AArch64::Z0_Z4_Z8_Z12, AArch64::Z16_Z20_Z24_Z28, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15, AArch64::Z16_Z17_Z18_Z19, AArch64::Z20_Z21_Z22_Z23, AArch64::Z24_Z25_Z26_Z27, AArch64::Z28_Z29_Z30_Z31,
5721 };
5722
5723 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4 Bit set.
5724 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4Bits[] = {
5725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x88, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
5726 };
5727
5728 // QQQQ_with_qsub0_in_FPR128_0to7 Register Class...
5729 const MCPhysReg QQQQ_with_qsub0_in_FPR128_0to7[] = {
5730 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10,
5731 };
5732
5733 // QQQQ_with_qsub0_in_FPR128_0to7 Bit set.
5734 const uint8_t QQQQ_with_qsub0_in_FPR128_0to7Bits[] = {
5735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
5736 };
5737
5738 // QQQQ_with_qsub1_in_FPR128_0to7 Register Class...
5739 const MCPhysReg QQQQ_with_qsub1_in_FPR128_0to7[] = {
5740 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q31_Q0_Q1_Q2,
5741 };
5742
5743 // QQQQ_with_qsub1_in_FPR128_0to7 Bit set.
5744 const uint8_t QQQQ_with_qsub1_in_FPR128_0to7Bits[] = {
5745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x04,
5746 };
5747
5748 // QQQQ_with_qsub2_in_FPR128_0to7 Register Class...
5749 const MCPhysReg QQQQ_with_qsub2_in_FPR128_0to7[] = {
5750 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
5751 };
5752
5753 // QQQQ_with_qsub2_in_FPR128_0to7 Bit set.
5754 const uint8_t QQQQ_with_qsub2_in_FPR128_0to7Bits[] = {
5755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x00, 0x06,
5756 };
5757
5758 // QQQQ_with_qsub3_in_FPR128_0to7 Register Class...
5759 const MCPhysReg QQQQ_with_qsub3_in_FPR128_0to7[] = {
5760 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
5761 };
5762
5763 // QQQQ_with_qsub3_in_FPR128_0to7 Bit set.
5764 const uint8_t QQQQ_with_qsub3_in_FPR128_0to7Bits[] = {
5765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x07,
5766 };
5767
5768 // ZPR4Mul4 Register Class...
5769 const MCPhysReg ZPR4Mul4[] = {
5770 AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15, AArch64::Z16_Z17_Z18_Z19, AArch64::Z20_Z21_Z22_Z23, AArch64::Z24_Z25_Z26_Z27, AArch64::Z28_Z29_Z30_Z31,
5771 };
5772
5773 // ZPR4Mul4 Bit set.
5774 const uint8_t ZPR4Mul4Bits[] = {
5775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x88, 0x88, 0x08,
5776 };
5777
5778 // ZPR4Strided Register Class...
5779 const MCPhysReg ZPR4Strided[] = {
5780 AArch64::Z0_Z4_Z8_Z12, AArch64::Z1_Z5_Z9_Z13, AArch64::Z2_Z6_Z10_Z14, AArch64::Z3_Z7_Z11_Z15, AArch64::Z16_Z20_Z24_Z28, AArch64::Z17_Z21_Z25_Z29, AArch64::Z18_Z22_Z26_Z30, AArch64::Z19_Z23_Z27_Z31,
5781 };
5782
5783 // ZPR4Strided Bit set.
5784 const uint8_t ZPR4StridedBits[] = {
5785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
5786 };
5787
5788 // ZPR4StridedOrContiguous_with_dsub_in_FPR64_lo Register Class...
5789 const MCPhysReg ZPR4StridedOrContiguous_with_dsub_in_FPR64_lo[] = {
5790 AArch64::Z0_Z4_Z8_Z12, AArch64::Z1_Z5_Z9_Z13, AArch64::Z2_Z6_Z10_Z14, AArch64::Z3_Z7_Z11_Z15, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15,
5791 };
5792
5793 // ZPR4StridedOrContiguous_with_dsub_in_FPR64_lo Bit set.
5794 const uint8_t ZPR4StridedOrContiguous_with_dsub_in_FPR64_loBits[] = {
5795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
5796 };
5797
5798 // ZPR4_with_qsub1_in_FPR128_0to7 Register Class...
5799 const MCPhysReg ZPR4_with_qsub1_in_FPR128_0to7[] = {
5800 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2,
5801 };
5802
5803 // ZPR4_with_qsub1_in_FPR128_0to7 Bit set.
5804 const uint8_t ZPR4_with_qsub1_in_FPR128_0to7Bits[] = {
5805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x40,
5806 };
5807
5808 // ZPR4_with_qsub2_in_FPR128_0to7 Register Class...
5809 const MCPhysReg ZPR4_with_qsub2_in_FPR128_0to7[] = {
5810 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
5811 };
5812
5813 // ZPR4_with_qsub2_in_FPR128_0to7 Bit set.
5814 const uint8_t ZPR4_with_qsub2_in_FPR128_0to7Bits[] = {
5815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x00, 0x60,
5816 };
5817
5818 // ZPR4_with_qsub3_in_FPR128_0to7 Register Class...
5819 const MCPhysReg ZPR4_with_qsub3_in_FPR128_0to7[] = {
5820 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
5821 };
5822
5823 // ZPR4_with_qsub3_in_FPR128_0to7 Bit set.
5824 const uint8_t ZPR4_with_qsub3_in_FPR128_0to7Bits[] = {
5825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0x00, 0x70,
5826 };
5827
5828 // ZPR4_with_zsub0_in_ZPR_K Register Class...
5829 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K[] = {
5830 AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
5831 };
5832
5833 // ZPR4_with_zsub0_in_ZPR_K Bit set.
5834 const uint8_t ZPR4_with_zsub0_in_ZPR_KBits[] = {
5835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x78,
5836 };
5837
5838 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi Register Class...
5839 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi[] = {
5840 AArch64::Z16_Z17_Z18_Z19, AArch64::Z18_Z19_Z20_Z21, AArch64::Z20_Z21_Z22_Z23, AArch64::Z22_Z23_Z24_Z25, AArch64::Z24_Z25_Z26_Z27, AArch64::Z26_Z27_Z28_Z29, AArch64::Z28_Z29_Z30_Z31, AArch64::Z30_Z31_Z0_Z1,
5841 };
5842
5843 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi Bit set.
5844 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiBits[] = {
5845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
5846 };
5847
5848 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo Register Class...
5849 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo[] = {
5850 AArch64::Z0_Z1_Z2_Z3, AArch64::Z2_Z3_Z4_Z5, AArch64::Z4_Z5_Z6_Z7, AArch64::Z6_Z7_Z8_Z9, AArch64::Z8_Z9_Z10_Z11, AArch64::Z10_Z11_Z12_Z13, AArch64::Z12_Z13_Z14_Z15, AArch64::Z14_Z15_Z16_Z17,
5851 };
5852
5853 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo Bit set.
5854 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_LoBits[] = {
5855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
5856 };
5857
5858 // ZPR4_with_zsub1_in_ZPRMul2_Hi Register Class...
5859 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul2_Hi[] = {
5860 AArch64::Z15_Z16_Z17_Z18, AArch64::Z17_Z18_Z19_Z20, AArch64::Z19_Z20_Z21_Z22, AArch64::Z21_Z22_Z23_Z24, AArch64::Z23_Z24_Z25_Z26, AArch64::Z25_Z26_Z27_Z28, AArch64::Z27_Z28_Z29_Z30, AArch64::Z29_Z30_Z31_Z0,
5861 };
5862
5863 // ZPR4_with_zsub1_in_ZPRMul2_Hi Bit set.
5864 const uint8_t ZPR4_with_zsub1_in_ZPRMul2_HiBits[] = {
5865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x15,
5866 };
5867
5868 // ZPR4_with_zsub1_in_ZPRMul2_Lo Register Class...
5869 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul2_Lo[] = {
5870 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10, AArch64::Z9_Z10_Z11_Z12, AArch64::Z11_Z12_Z13_Z14, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2,
5871 };
5872
5873 // ZPR4_with_zsub1_in_ZPRMul2_Lo Bit set.
5874 const uint8_t ZPR4_with_zsub1_in_ZPRMul2_LoBits[] = {
5875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 0x00, 0x40,
5876 };
5877
5878 // ZPR4_with_zsub1_in_ZPRMul4 Register Class...
5879 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul4[] = {
5880 AArch64::Z3_Z4_Z5_Z6, AArch64::Z7_Z8_Z9_Z10, AArch64::Z11_Z12_Z13_Z14, AArch64::Z15_Z16_Z17_Z18, AArch64::Z19_Z20_Z21_Z22, AArch64::Z23_Z24_Z25_Z26, AArch64::Z27_Z28_Z29_Z30, AArch64::Z31_Z0_Z1_Z2,
5881 };
5882
5883 // ZPR4_with_zsub1_in_ZPRMul4 Bit set.
5884 const uint8_t ZPR4_with_zsub1_in_ZPRMul4Bits[] = {
5885 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x44,
5886 };
5887
5888 // ZPR4_with_zsub1_in_ZPR_K Register Class...
5889 const MCPhysReg ZPR4_with_zsub1_in_ZPR_K[] = {
5890 AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1,
5891 };
5892
5893 // ZPR4_with_zsub1_in_ZPR_K Bit set.
5894 const uint8_t ZPR4_with_zsub1_in_ZPR_KBits[] = {
5895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x3c,
5896 };
5897
5898 // ZPR4_with_zsub2_in_ZPRMul2_Hi Register Class...
5899 const MCPhysReg ZPR4_with_zsub2_in_ZPRMul2_Hi[] = {
5900 AArch64::Z14_Z15_Z16_Z17, AArch64::Z16_Z17_Z18_Z19, AArch64::Z18_Z19_Z20_Z21, AArch64::Z20_Z21_Z22_Z23, AArch64::Z22_Z23_Z24_Z25, AArch64::Z24_Z25_Z26_Z27, AArch64::Z26_Z27_Z28_Z29, AArch64::Z28_Z29_Z30_Z31,
5901 };
5902
5903 // ZPR4_with_zsub2_in_ZPRMul2_Hi Bit set.
5904 const uint8_t ZPR4_with_zsub2_in_ZPRMul2_HiBits[] = {
5905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0x0a,
5906 };
5907
5908 // ZPR4_with_zsub2_in_ZPRMul2_Lo Register Class...
5909 const MCPhysReg ZPR4_with_zsub2_in_ZPRMul2_Lo[] = {
5910 AArch64::Z0_Z1_Z2_Z3, AArch64::Z2_Z3_Z4_Z5, AArch64::Z4_Z5_Z6_Z7, AArch64::Z6_Z7_Z8_Z9, AArch64::Z8_Z9_Z10_Z11, AArch64::Z10_Z11_Z12_Z13, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1,
5911 };
5912
5913 // ZPR4_with_zsub2_in_ZPRMul2_Lo Bit set.
5914 const uint8_t ZPR4_with_zsub2_in_ZPRMul2_LoBits[] = {
5915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a, 0x00, 0x20,
5916 };
5917
5918 // ZPR4_with_zsub2_in_ZPRMul4 Register Class...
5919 const MCPhysReg ZPR4_with_zsub2_in_ZPRMul4[] = {
5920 AArch64::Z2_Z3_Z4_Z5, AArch64::Z6_Z7_Z8_Z9, AArch64::Z10_Z11_Z12_Z13, AArch64::Z14_Z15_Z16_Z17, AArch64::Z18_Z19_Z20_Z21, AArch64::Z22_Z23_Z24_Z25, AArch64::Z26_Z27_Z28_Z29, AArch64::Z30_Z31_Z0_Z1,
5921 };
5922
5923 // ZPR4_with_zsub2_in_ZPRMul4 Bit set.
5924 const uint8_t ZPR4_with_zsub2_in_ZPRMul4Bits[] = {
5925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22,
5926 };
5927
5928 // ZPR4_with_zsub2_in_ZPR_K Register Class...
5929 const MCPhysReg ZPR4_with_zsub2_in_ZPR_K[] = {
5930 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
5931 };
5932
5933 // ZPR4_with_zsub2_in_ZPR_K Bit set.
5934 const uint8_t ZPR4_with_zsub2_in_ZPR_KBits[] = {
5935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e,
5936 };
5937
5938 // ZPR4_with_zsub3_in_ZPRMul2_Hi Register Class...
5939 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul2_Hi[] = {
5940 AArch64::Z13_Z14_Z15_Z16, AArch64::Z15_Z16_Z17_Z18, AArch64::Z17_Z18_Z19_Z20, AArch64::Z19_Z20_Z21_Z22, AArch64::Z21_Z22_Z23_Z24, AArch64::Z23_Z24_Z25_Z26, AArch64::Z25_Z26_Z27_Z28, AArch64::Z27_Z28_Z29_Z30,
5941 };
5942
5943 // ZPR4_with_zsub3_in_ZPRMul2_Hi Bit set.
5944 const uint8_t ZPR4_with_zsub3_in_ZPRMul2_HiBits[] = {
5945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x05,
5946 };
5947
5948 // ZPR4_with_zsub3_in_ZPRMul2_Lo Register Class...
5949 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul2_Lo[] = {
5950 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10, AArch64::Z9_Z10_Z11_Z12, AArch64::Z11_Z12_Z13_Z14, AArch64::Z29_Z30_Z31_Z0, AArch64::Z31_Z0_Z1_Z2,
5951 };
5952
5953 // ZPR4_with_zsub3_in_ZPRMul2_Lo Bit set.
5954 const uint8_t ZPR4_with_zsub3_in_ZPRMul2_LoBits[] = {
5955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x05, 0x00, 0x50,
5956 };
5957
5958 // ZPR4_with_zsub3_in_ZPRMul4 Register Class...
5959 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul4[] = {
5960 AArch64::Z1_Z2_Z3_Z4, AArch64::Z5_Z6_Z7_Z8, AArch64::Z9_Z10_Z11_Z12, AArch64::Z13_Z14_Z15_Z16, AArch64::Z17_Z18_Z19_Z20, AArch64::Z21_Z22_Z23_Z24, AArch64::Z25_Z26_Z27_Z28, AArch64::Z29_Z30_Z31_Z0,
5961 };
5962
5963 // ZPR4_with_zsub3_in_ZPRMul4 Bit set.
5964 const uint8_t ZPR4_with_zsub3_in_ZPRMul4Bits[] = {
5965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11, 0x11, 0x11,
5966 };
5967
5968 // ZPR4_with_zsub3_in_ZPR_K Register Class...
5969 const MCPhysReg ZPR4_with_zsub3_in_ZPR_K[] = {
5970 AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31,
5971 };
5972
5973 // ZPR4_with_zsub3_in_ZPR_K Bit set.
5974 const uint8_t ZPR4_with_zsub3_in_ZPR_KBits[] = {
5975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f,
5976 };
5977
5978 // ZPR4_with_zsub_in_FPR128_0to7 Register Class...
5979 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7[] = {
5980 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10,
5981 };
5982
5983 // ZPR4_with_zsub_in_FPR128_0to7 Bit set.
5984 const uint8_t ZPR4_with_zsub_in_FPR128_0to7Bits[] = {
5985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
5986 };
5987
5988 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2 Register Class...
5989 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2[] = {
5990 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10, AArch64::Z9_Z10_Z11_Z12, AArch64::Z11_Z12_Z13_Z14, AArch64::Z13_Z14_Z15_Z16, AArch64::Z15_Z16_Z17_Z18,
5991 };
5992
5993 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2 Bit set.
5994 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2Bits[] = {
5995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
5996 };
5997
5998 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7 Register Class...
5999 const MCPhysReg QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7[] = {
6000 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q31_Q0_Q1_Q2,
6001 };
6002
6003 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7 Bit set.
6004 const uint8_t QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7Bits[] = {
6005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x00, 0x04,
6006 };
6007
6008 // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7 Register Class...
6009 const MCPhysReg QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7[] = {
6010 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
6011 };
6012
6013 // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7 Bit set.
6014 const uint8_t QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7Bits[] = {
6015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x06,
6016 };
6017
6018 // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7 Register Class...
6019 const MCPhysReg QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7[] = {
6020 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9,
6021 };
6022
6023 // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7 Bit set.
6024 const uint8_t QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7Bits[] = {
6025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
6026 };
6027
6028 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7 Register Class...
6029 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7[] = {
6030 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2,
6031 };
6032
6033 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7 Bit set.
6034 const uint8_t ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7Bits[] = {
6035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x00, 0x00, 0x40,
6036 };
6037
6038 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo Register Class...
6039 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo[] = {
6040 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10, AArch64::Z9_Z10_Z11_Z12, AArch64::Z11_Z12_Z13_Z14, AArch64::Z31_Z0_Z1_Z2,
6041 };
6042
6043 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo Bit set.
6044 const uint8_t ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoBits[] = {
6045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x05, 0x00, 0x40,
6046 };
6047
6048 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7 Register Class...
6049 const MCPhysReg ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7[] = {
6050 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
6051 };
6052
6053 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7 Bit set.
6054 const uint8_t ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7Bits[] = {
6055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0x00, 0x60,
6056 };
6057
6058 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Register Class...
6059 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi[] = {
6060 AArch64::Z16_Z17_Z18_Z19, AArch64::Z18_Z19_Z20_Z21, AArch64::Z20_Z21_Z22_Z23, AArch64::Z22_Z23_Z24_Z25, AArch64::Z24_Z25_Z26_Z27, AArch64::Z26_Z27_Z28_Z29, AArch64::Z28_Z29_Z30_Z31,
6061 };
6062
6063 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Bit set.
6064 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits[] = {
6065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a,
6066 };
6067
6068 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Register Class...
6069 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi[] = {
6070 AArch64::Z15_Z16_Z17_Z18, AArch64::Z17_Z18_Z19_Z20, AArch64::Z19_Z20_Z21_Z22, AArch64::Z21_Z22_Z23_Z24, AArch64::Z23_Z24_Z25_Z26, AArch64::Z25_Z26_Z27_Z28, AArch64::Z27_Z28_Z29_Z30,
6071 };
6072
6073 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi Bit set.
6074 const uint8_t ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits[] = {
6075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x05,
6076 };
6077
6078 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7 Register Class...
6079 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7[] = {
6080 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9,
6081 };
6082
6083 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7 Bit set.
6084 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7Bits[] = {
6085 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
6086 };
6087
6088 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Lo Register Class...
6089 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Lo[] = {
6090 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10, AArch64::Z9_Z10_Z11_Z12, AArch64::Z11_Z12_Z13_Z14, AArch64::Z13_Z14_Z15_Z16,
6091 };
6092
6093 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Lo Bit set.
6094 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_LoBits[] = {
6095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
6096 };
6097
6098 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Lo Register Class...
6099 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Lo[] = {
6100 AArch64::Z0_Z1_Z2_Z3, AArch64::Z2_Z3_Z4_Z5, AArch64::Z4_Z5_Z6_Z7, AArch64::Z6_Z7_Z8_Z9, AArch64::Z8_Z9_Z10_Z11, AArch64::Z10_Z11_Z12_Z13, AArch64::Z12_Z13_Z14_Z15,
6101 };
6102
6103 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Lo Bit set.
6104 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_LoBits[] = {
6105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a,
6106 };
6107
6108 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7 Register Class...
6109 const MCPhysReg QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7[] = {
6110 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q31_Q0_Q1_Q2,
6111 };
6112
6113 // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7 Bit set.
6114 const uint8_t QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7Bits[] = {
6115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x04,
6116 };
6117
6118 // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7 Register Class...
6119 const MCPhysReg QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7[] = {
6120 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
6121 };
6122
6123 // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7 Bit set.
6124 const uint8_t QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7Bits[] = {
6125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
6126 };
6127
6128 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi Register Class...
6129 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi[] = {
6130 AArch64::Z16_Z20_Z24_Z28, AArch64::Z18_Z22_Z26_Z30, AArch64::Z16_Z17_Z18_Z19, AArch64::Z20_Z21_Z22_Z23, AArch64::Z24_Z25_Z26_Z27, AArch64::Z28_Z29_Z30_Z31,
6131 };
6132
6133 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi Bit set.
6134 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_HiBits[] = {
6135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02,
6136 };
6137
6138 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo Register Class...
6139 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo[] = {
6140 AArch64::Z0_Z4_Z8_Z12, AArch64::Z2_Z6_Z10_Z14, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15,
6141 };
6142
6143 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo Bit set.
6144 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_LoBits[] = {
6145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
6146 };
6147
6148 // ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K Register Class...
6149 const MCPhysReg ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K[] = {
6150 AArch64::Z16_Z20_Z24_Z28, AArch64::Z17_Z21_Z25_Z29, AArch64::Z18_Z22_Z26_Z30, AArch64::Z19_Z23_Z27_Z31, AArch64::Z20_Z21_Z22_Z23, AArch64::Z28_Z29_Z30_Z31,
6151 };
6152
6153 // ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K Bit set.
6154 const uint8_t ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits[] = {
6155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
6156 };
6157
6158 // ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7 Register Class...
6159 const MCPhysReg ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7[] = {
6160 AArch64::Z0_Z4_Z8_Z12, AArch64::Z1_Z5_Z9_Z13, AArch64::Z2_Z6_Z10_Z14, AArch64::Z3_Z7_Z11_Z15, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7,
6161 };
6162
6163 // ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7 Bit set.
6164 const uint8_t ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7Bits[] = {
6165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
6166 };
6167
6168 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7 Register Class...
6169 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7[] = {
6170 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2,
6171 };
6172
6173 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7 Bit set.
6174 const uint8_t ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7Bits[] = {
6175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0x00, 0x40,
6176 };
6177
6178 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_K Register Class...
6179 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_K[] = {
6180 AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1,
6181 };
6182
6183 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_K Bit set.
6184 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_KBits[] = {
6185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x38,
6186 };
6187
6188 // ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K Register Class...
6189 const MCPhysReg ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K[] = {
6190 AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
6191 };
6192
6193 // ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K Bit set.
6194 const uint8_t ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KBits[] = {
6195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1c,
6196 };
6197
6198 // ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K Register Class...
6199 const MCPhysReg ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K[] = {
6200 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31,
6201 };
6202
6203 // ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K Bit set.
6204 const uint8_t ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KBits[] = {
6205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e,
6206 };
6207
6208 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7 Register Class...
6209 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7[] = {
6210 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
6211 };
6212
6213 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7 Bit set.
6214 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7Bits[] = {
6215 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
6216 };
6217
6218 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo Register Class...
6219 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo[] = {
6220 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10, AArch64::Z9_Z10_Z11_Z12, AArch64::Z11_Z12_Z13_Z14,
6221 };
6222
6223 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo Bit set.
6224 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoBits[] = {
6225 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x05,
6226 };
6227
6228 // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7 Register Class...
6229 const MCPhysReg QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7[] = {
6230 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7,
6231 };
6232
6233 // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7 Bit set.
6234 const uint8_t QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7Bits[] = {
6235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
6236 };
6237
6238 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
6239 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4[] = {
6240 AArch64::Z16_Z20_Z24_Z28, AArch64::Z16_Z17_Z18_Z19, AArch64::Z20_Z21_Z22_Z23, AArch64::Z24_Z25_Z26_Z27, AArch64::Z28_Z29_Z30_Z31,
6241 };
6242
6243 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
6244 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
6245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
6246 };
6247
6248 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
6249 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4[] = {
6250 AArch64::Z0_Z4_Z8_Z12, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15,
6251 };
6252
6253 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
6254 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
6255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
6256 };
6257
6258 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7 Register Class...
6259 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7[] = {
6260 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7,
6261 };
6262
6263 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7 Bit set.
6264 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7Bits[] = {
6265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f,
6266 };
6267
6268 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K Register Class...
6269 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K[] = {
6270 AArch64::Z16_Z20_Z24_Z28, AArch64::Z18_Z22_Z26_Z30, AArch64::Z20_Z21_Z22_Z23, AArch64::Z28_Z29_Z30_Z31,
6271 };
6272
6273 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K Bit set.
6274 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits[] = {
6275 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02,
6276 };
6277
6278 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b Register Class...
6279 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b[] = {
6280 AArch64::Z0_Z4_Z8_Z12, AArch64::Z2_Z6_Z10_Z14, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7,
6281 };
6282
6283 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b Bit set.
6284 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bBits[] = {
6285 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
6286 };
6287
6288 // ZPR4Strided_with_dsub_in_FPR64_lo Register Class...
6289 const MCPhysReg ZPR4Strided_with_dsub_in_FPR64_lo[] = {
6290 AArch64::Z0_Z4_Z8_Z12, AArch64::Z1_Z5_Z9_Z13, AArch64::Z2_Z6_Z10_Z14, AArch64::Z3_Z7_Z11_Z15,
6291 };
6292
6293 // ZPR4Strided_with_dsub_in_FPR64_lo Bit set.
6294 const uint8_t ZPR4Strided_with_dsub_in_FPR64_loBits[] = {
6295 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
6296 };
6297
6298 // ZPR4Strided_with_zsub0_in_ZPRMul2 Register Class...
6299 const MCPhysReg ZPR4Strided_with_zsub0_in_ZPRMul2[] = {
6300 AArch64::Z0_Z4_Z8_Z12, AArch64::Z2_Z6_Z10_Z14, AArch64::Z16_Z20_Z24_Z28, AArch64::Z18_Z22_Z26_Z30,
6301 };
6302
6303 // ZPR4Strided_with_zsub0_in_ZPRMul2 Bit set.
6304 const uint8_t ZPR4Strided_with_zsub0_in_ZPRMul2Bits[] = {
6305 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
6306 };
6307
6308 // ZPR4Strided_with_zsub1_in_ZPR_K Register Class...
6309 const MCPhysReg ZPR4Strided_with_zsub1_in_ZPR_K[] = {
6310 AArch64::Z16_Z20_Z24_Z28, AArch64::Z17_Z21_Z25_Z29, AArch64::Z18_Z22_Z26_Z30, AArch64::Z19_Z23_Z27_Z31,
6311 };
6312
6313 // ZPR4Strided_with_zsub1_in_ZPR_K Bit set.
6314 const uint8_t ZPR4Strided_with_zsub1_in_ZPR_KBits[] = {
6315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
6316 };
6317
6318 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2 Register Class...
6319 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2[] = {
6320 AArch64::Z21_Z22_Z23_Z24, AArch64::Z23_Z24_Z25_Z26, AArch64::Z29_Z30_Z31_Z0, AArch64::Z31_Z0_Z1_Z2,
6321 };
6322
6323 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2 Bit set.
6324 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2Bits[] = {
6325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x50,
6326 };
6327
6328 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K Register Class...
6329 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K[] = {
6330 AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
6331 };
6332
6333 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K Bit set.
6334 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KBits[] = {
6335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18,
6336 };
6337
6338 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6339 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6340 AArch64::Z16_Z17_Z18_Z19, AArch64::Z20_Z21_Z22_Z23, AArch64::Z24_Z25_Z26_Z27, AArch64::Z28_Z29_Z30_Z31,
6341 };
6342
6343 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6344 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
6346 };
6347
6348 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6349 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6350 AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7, AArch64::Z8_Z9_Z10_Z11, AArch64::Z12_Z13_Z14_Z15,
6351 };
6352
6353 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6354 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x88, 0x08,
6356 };
6357
6358 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
6359 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
6360 AArch64::Z20_Z21_Z22_Z23, AArch64::Z22_Z23_Z24_Z25, AArch64::Z28_Z29_Z30_Z31, AArch64::Z30_Z31_Z0_Z1,
6361 };
6362
6363 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
6364 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
6365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x28,
6366 };
6367
6368 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
6369 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
6370 AArch64::Z0_Z1_Z2_Z3, AArch64::Z2_Z3_Z4_Z5, AArch64::Z4_Z5_Z6_Z7, AArch64::Z6_Z7_Z8_Z9,
6371 };
6372
6373 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
6374 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
6375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
6376 };
6377
6378 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4 Register Class...
6379 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4[] = {
6380 AArch64::Z18_Z19_Z20_Z21, AArch64::Z22_Z23_Z24_Z25, AArch64::Z26_Z27_Z28_Z29, AArch64::Z30_Z31_Z0_Z1,
6381 };
6382
6383 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4 Bit set.
6384 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits[] = {
6385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22,
6386 };
6387
6388 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6389 const MCPhysReg ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6390 AArch64::Z15_Z16_Z17_Z18, AArch64::Z19_Z20_Z21_Z22, AArch64::Z23_Z24_Z25_Z26, AArch64::Z27_Z28_Z29_Z30,
6391 };
6392
6393 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6394 const uint8_t ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x44, 0x04,
6396 };
6397
6398 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6399 const MCPhysReg ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6400 AArch64::Z3_Z4_Z5_Z6, AArch64::Z7_Z8_Z9_Z10, AArch64::Z11_Z12_Z13_Z14, AArch64::Z31_Z0_Z1_Z2,
6401 };
6402
6403 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6404 const uint8_t ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x04, 0x00, 0x40,
6406 };
6407
6408 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
6409 const MCPhysReg ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
6410 AArch64::Z19_Z20_Z21_Z22, AArch64::Z21_Z22_Z23_Z24, AArch64::Z27_Z28_Z29_Z30, AArch64::Z29_Z30_Z31_Z0,
6411 };
6412
6413 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
6414 const uint8_t ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
6415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14,
6416 };
6417
6418 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
6419 const MCPhysReg ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
6420 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2,
6421 };
6422
6423 // ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
6424 const uint8_t ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
6425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x40,
6426 };
6427
6428 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4 Register Class...
6429 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4[] = {
6430 AArch64::Z17_Z18_Z19_Z20, AArch64::Z21_Z22_Z23_Z24, AArch64::Z25_Z26_Z27_Z28, AArch64::Z29_Z30_Z31_Z0,
6431 };
6432
6433 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4 Bit set.
6434 const uint8_t ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits[] = {
6435 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
6436 };
6437
6438 // ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K Register Class...
6439 const MCPhysReg ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K[] = {
6440 AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31,
6441 };
6442
6443 // ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K Bit set.
6444 const uint8_t ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KBits[] = {
6445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c,
6446 };
6447
6448 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6449 const MCPhysReg ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6450 AArch64::Z14_Z15_Z16_Z17, AArch64::Z18_Z19_Z20_Z21, AArch64::Z22_Z23_Z24_Z25, AArch64::Z26_Z27_Z28_Z29,
6451 };
6452
6453 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6454 const uint8_t ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6455 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x22, 0x02,
6456 };
6457
6458 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6459 const MCPhysReg ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6460 AArch64::Z2_Z3_Z4_Z5, AArch64::Z6_Z7_Z8_Z9, AArch64::Z10_Z11_Z12_Z13, AArch64::Z30_Z31_Z0_Z1,
6461 };
6462
6463 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6464 const uint8_t ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x02, 0x00, 0x20,
6466 };
6467
6468 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
6469 const MCPhysReg ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
6470 AArch64::Z18_Z19_Z20_Z21, AArch64::Z20_Z21_Z22_Z23, AArch64::Z26_Z27_Z28_Z29, AArch64::Z28_Z29_Z30_Z31,
6471 };
6472
6473 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
6474 const uint8_t ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
6475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a,
6476 };
6477
6478 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
6479 const MCPhysReg ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
6480 AArch64::Z0_Z1_Z2_Z3, AArch64::Z2_Z3_Z4_Z5, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1,
6481 };
6482
6483 // ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
6484 const uint8_t ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
6485 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, 0x00, 0x00, 0x20,
6486 };
6487
6488 // ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
6489 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4[] = {
6490 AArch64::Z13_Z14_Z15_Z16, AArch64::Z17_Z18_Z19_Z20, AArch64::Z21_Z22_Z23_Z24, AArch64::Z25_Z26_Z27_Z28,
6491 };
6492
6493 // ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
6494 const uint8_t ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
6495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01,
6496 };
6497
6498 // ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
6499 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4[] = {
6500 AArch64::Z1_Z2_Z3_Z4, AArch64::Z5_Z6_Z7_Z8, AArch64::Z9_Z10_Z11_Z12, AArch64::Z29_Z30_Z31_Z0,
6501 };
6502
6503 // ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
6504 const uint8_t ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
6505 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x10,
6506 };
6507
6508 // ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b Register Class...
6509 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b[] = {
6510 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z29_Z30_Z31_Z0, AArch64::Z31_Z0_Z1_Z2,
6511 };
6512
6513 // ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b Bit set.
6514 const uint8_t ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits[] = {
6515 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x50,
6516 };
6517
6518 // ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_K Register Class...
6519 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_K[] = {
6520 AArch64::Z17_Z18_Z19_Z20, AArch64::Z19_Z20_Z21_Z22, AArch64::Z25_Z26_Z27_Z28, AArch64::Z27_Z28_Z29_Z30,
6521 };
6522
6523 // ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_K Bit set.
6524 const uint8_t ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_KBits[] = {
6525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05,
6526 };
6527
6528 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2 Register Class...
6529 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2[] = {
6530 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8, AArch64::Z7_Z8_Z9_Z10,
6531 };
6532
6533 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2 Bit set.
6534 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2Bits[] = {
6535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
6536 };
6537
6538 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4 Register Class...
6539 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4[] = {
6540 AArch64::Z3_Z4_Z5_Z6, AArch64::Z7_Z8_Z9_Z10, AArch64::Z11_Z12_Z13_Z14, AArch64::Z15_Z16_Z17_Z18,
6541 };
6542
6543 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4 Bit set.
6544 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4Bits[] = {
6545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x44,
6546 };
6547
6548 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4 Register Class...
6549 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4[] = {
6550 AArch64::Z2_Z3_Z4_Z5, AArch64::Z6_Z7_Z8_Z9, AArch64::Z10_Z11_Z12_Z13, AArch64::Z14_Z15_Z16_Z17,
6551 };
6552
6553 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4 Bit set.
6554 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4Bits[] = {
6555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22,
6556 };
6557
6558 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4 Register Class...
6559 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4[] = {
6560 AArch64::Z1_Z2_Z3_Z4, AArch64::Z5_Z6_Z7_Z8, AArch64::Z9_Z10_Z11_Z12, AArch64::Z13_Z14_Z15_Z16,
6561 };
6562
6563 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4 Bit set.
6564 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4Bits[] = {
6565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
6566 };
6567
6568 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K Register Class...
6569 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K[] = {
6570 AArch64::Z16_Z20_Z24_Z28, AArch64::Z20_Z21_Z22_Z23, AArch64::Z28_Z29_Z30_Z31,
6571 };
6572
6573 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K Bit set.
6574 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits[] = {
6575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
6576 };
6577
6578 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b Register Class...
6579 const MCPhysReg ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b[] = {
6580 AArch64::Z0_Z4_Z8_Z12, AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7,
6581 };
6582
6583 // ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b Bit set.
6584 const uint8_t ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bBits[] = {
6585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
6586 };
6587
6588 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b Register Class...
6589 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b[] = {
6590 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z31_Z0_Z1_Z2,
6591 };
6592
6593 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b Bit set.
6594 const uint8_t ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits[] = {
6595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x40,
6596 };
6597
6598 // ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K Register Class...
6599 const MCPhysReg ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K[] = {
6600 AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
6601 };
6602
6603 // ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K Bit set.
6604 const uint8_t ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits[] = {
6605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
6606 };
6607
6608 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_Hi Register Class...
6609 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_Hi[] = {
6610 AArch64::Z21_Z22_Z23_Z24, AArch64::Z23_Z24_Z25_Z26, AArch64::Z29_Z30_Z31_Z0,
6611 };
6612
6613 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_Hi Bit set.
6614 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits[] = {
6615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x10,
6616 };
6617
6618 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
6619 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4[] = {
6620 AArch64::Z18_Z19_Z20_Z21, AArch64::Z22_Z23_Z24_Z25, AArch64::Z26_Z27_Z28_Z29,
6621 };
6622
6623 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
6624 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
6625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x02,
6626 };
6627
6628 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Register Class...
6629 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi[] = {
6630 AArch64::Z20_Z21_Z22_Z23, AArch64::Z22_Z23_Z24_Z25, AArch64::Z28_Z29_Z30_Z31,
6631 };
6632
6633 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Bit set.
6634 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits[] = {
6635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x08,
6636 };
6637
6638 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
6639 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4[] = {
6640 AArch64::Z17_Z18_Z19_Z20, AArch64::Z21_Z22_Z23_Z24, AArch64::Z25_Z26_Z27_Z28,
6641 };
6642
6643 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
6644 const uint8_t ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
6645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01,
6646 };
6647
6648 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Register Class...
6649 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi[] = {
6650 AArch64::Z19_Z20_Z21_Z22, AArch64::Z21_Z22_Z23_Z24, AArch64::Z27_Z28_Z29_Z30,
6651 };
6652
6653 // ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi Bit set.
6654 const uint8_t ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits[] = {
6655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x04,
6656 };
6657
6658 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
6659 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
6660 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6, AArch64::Z5_Z6_Z7_Z8,
6661 };
6662
6663 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
6664 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
6665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
6666 };
6667
6668 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Register Class...
6669 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7[] = {
6670 AArch64::Z0_Z1_Z2_Z3, AArch64::Z2_Z3_Z4_Z5, AArch64::Z4_Z5_Z6_Z7,
6671 };
6672
6673 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7 Bit set.
6674 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits[] = {
6675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a,
6676 };
6677
6678 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6679 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6680 AArch64::Z3_Z4_Z5_Z6, AArch64::Z7_Z8_Z9_Z10, AArch64::Z11_Z12_Z13_Z14,
6681 };
6682
6683 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6684 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x04,
6686 };
6687
6688 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6689 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6690 AArch64::Z2_Z3_Z4_Z5, AArch64::Z6_Z7_Z8_Z9, AArch64::Z10_Z11_Z12_Z13,
6691 };
6692
6693 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6694 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x02,
6696 };
6697
6698 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
6699 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4[] = {
6700 AArch64::Z1_Z2_Z3_Z4, AArch64::Z5_Z6_Z7_Z8, AArch64::Z9_Z10_Z11_Z12,
6701 };
6702
6703 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
6704 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
6705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01,
6706 };
6707
6708 // ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_K Register Class...
6709 const MCPhysReg ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_K[] = {
6710 AArch64::Z20_Z21_Z22_Z23, AArch64::Z28_Z29_Z30_Z31,
6711 };
6712
6713 // ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_K Bit set.
6714 const uint8_t ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_KBits[] = {
6715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08,
6716 };
6717
6718 // ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7 Register Class...
6719 const MCPhysReg ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7[] = {
6720 AArch64::Z0_Z1_Z2_Z3, AArch64::Z4_Z5_Z6_Z7,
6721 };
6722
6723 // ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7 Bit set.
6724 const uint8_t ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7Bits[] = {
6725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
6726 };
6727
6728 // ZPR4Strided_with_zsub0_in_ZPRMul2_Hi Register Class...
6729 const MCPhysReg ZPR4Strided_with_zsub0_in_ZPRMul2_Hi[] = {
6730 AArch64::Z16_Z20_Z24_Z28, AArch64::Z18_Z22_Z26_Z30,
6731 };
6732
6733 // ZPR4Strided_with_zsub0_in_ZPRMul2_Hi Bit set.
6734 const uint8_t ZPR4Strided_with_zsub0_in_ZPRMul2_HiBits[] = {
6735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02,
6736 };
6737
6738 // ZPR4Strided_with_zsub0_in_ZPRMul2_Lo Register Class...
6739 const MCPhysReg ZPR4Strided_with_zsub0_in_ZPRMul2_Lo[] = {
6740 AArch64::Z0_Z4_Z8_Z12, AArch64::Z2_Z6_Z10_Z14,
6741 };
6742
6743 // ZPR4Strided_with_zsub0_in_ZPRMul2_Lo Bit set.
6744 const uint8_t ZPR4Strided_with_zsub0_in_ZPRMul2_LoBits[] = {
6745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
6746 };
6747
6748 // ZPR4Strided_with_zsub0_in_ZPRMul4 Register Class...
6749 const MCPhysReg ZPR4Strided_with_zsub0_in_ZPRMul4[] = {
6750 AArch64::Z0_Z4_Z8_Z12, AArch64::Z16_Z20_Z24_Z28,
6751 };
6752
6753 // ZPR4Strided_with_zsub0_in_ZPRMul4 Bit set.
6754 const uint8_t ZPR4Strided_with_zsub0_in_ZPRMul4Bits[] = {
6755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x08,
6756 };
6757
6758 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K Register Class...
6759 const MCPhysReg ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K[] = {
6760 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
6761 };
6762
6763 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K Bit set.
6764 const uint8_t ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits[] = {
6765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
6766 };
6767
6768 // ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_K Register Class...
6769 const MCPhysReg ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_K[] = {
6770 AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1,
6771 };
6772
6773 // ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_K Bit set.
6774 const uint8_t ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_KBits[] = {
6775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
6776 };
6777
6778 // ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2 Register Class...
6779 const MCPhysReg ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2[] = {
6780 AArch64::Z29_Z30_Z31_Z0, AArch64::Z31_Z0_Z1_Z2,
6781 };
6782
6783 // ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2 Bit set.
6784 const uint8_t ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2Bits[] = {
6785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
6786 };
6787
6788 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Register Class...
6789 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K[] = {
6790 AArch64::Z21_Z22_Z23_Z24, AArch64::Z29_Z30_Z31_Z0,
6791 };
6792
6793 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K Bit set.
6794 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits[] = {
6795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10,
6796 };
6797
6798 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4 Register Class...
6799 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4[] = {
6800 AArch64::Z23_Z24_Z25_Z26, AArch64::Z31_Z0_Z1_Z2,
6801 };
6802
6803 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4 Bit set.
6804 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4Bits[] = {
6805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40,
6806 };
6807
6808 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi Register Class...
6809 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi[] = {
6810 AArch64::Z21_Z22_Z23_Z24, AArch64::Z23_Z24_Z25_Z26,
6811 };
6812
6813 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi Bit set.
6814 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_HiBits[] = {
6815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
6816 };
6817
6818 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4 Register Class...
6819 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4[] = {
6820 AArch64::Z22_Z23_Z24_Z25, AArch64::Z30_Z31_Z0_Z1,
6821 };
6822
6823 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4 Bit set.
6824 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits[] = {
6825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20,
6826 };
6827
6828 // ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b Register Class...
6829 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b[] = {
6830 AArch64::Z3_Z4_Z5_Z6, AArch64::Z31_Z0_Z1_Z2,
6831 };
6832
6833 // ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b Bit set.
6834 const uint8_t ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bBits[] = {
6835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x40,
6836 };
6837
6838 // ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_K Register Class...
6839 const MCPhysReg ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_K[] = {
6840 AArch64::Z19_Z20_Z21_Z22, AArch64::Z27_Z28_Z29_Z30,
6841 };
6842
6843 // ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_K Bit set.
6844 const uint8_t ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_KBits[] = {
6845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04,
6846 };
6847
6848 // ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b Register Class...
6849 const MCPhysReg ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b[] = {
6850 AArch64::Z2_Z3_Z4_Z5, AArch64::Z30_Z31_Z0_Z1,
6851 };
6852
6853 // ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b Bit set.
6854 const uint8_t ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bBits[] = {
6855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x20,
6856 };
6857
6858 // ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_K Register Class...
6859 const MCPhysReg ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_K[] = {
6860 AArch64::Z18_Z19_Z20_Z21, AArch64::Z26_Z27_Z28_Z29,
6861 };
6862
6863 // ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_K Bit set.
6864 const uint8_t ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_KBits[] = {
6865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02,
6866 };
6867
6868 // ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b Register Class...
6869 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b[] = {
6870 AArch64::Z1_Z2_Z3_Z4, AArch64::Z29_Z30_Z31_Z0,
6871 };
6872
6873 // ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b Bit set.
6874 const uint8_t ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bBits[] = {
6875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x10,
6876 };
6877
6878 // ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_K Register Class...
6879 const MCPhysReg ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_K[] = {
6880 AArch64::Z17_Z18_Z19_Z20, AArch64::Z25_Z26_Z27_Z28,
6881 };
6882
6883 // ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_K Bit set.
6884 const uint8_t ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_KBits[] = {
6885 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
6886 };
6887
6888 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4 Register Class...
6889 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4[] = {
6890 AArch64::Z3_Z4_Z5_Z6, AArch64::Z7_Z8_Z9_Z10,
6891 };
6892
6893 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4 Bit set.
6894 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4Bits[] = {
6895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44,
6896 };
6897
6898 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4 Register Class...
6899 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4[] = {
6900 AArch64::Z2_Z3_Z4_Z5, AArch64::Z6_Z7_Z8_Z9,
6901 };
6902
6903 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4 Bit set.
6904 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4Bits[] = {
6905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22,
6906 };
6907
6908 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b Register Class...
6909 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b[] = {
6910 AArch64::Z1_Z2_Z3_Z4, AArch64::Z3_Z4_Z5_Z6,
6911 };
6912
6913 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b Bit set.
6914 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits[] = {
6915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
6916 };
6917
6918 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4 Register Class...
6919 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4[] = {
6920 AArch64::Z1_Z2_Z3_Z4, AArch64::Z5_Z6_Z7_Z8,
6921 };
6922
6923 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4 Bit set.
6924 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4Bits[] = {
6925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
6926 };
6927
6928 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi Register Class...
6929 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi[] = {
6930 AArch64::Z13_Z14_Z15_Z16, AArch64::Z15_Z16_Z17_Z18,
6931 };
6932
6933 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi Bit set.
6934 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_HiBits[] = {
6935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
6936 };
6937
6938 // ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
6939 const MCPhysReg ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4[] = {
6940 AArch64::Z16_Z20_Z24_Z28,
6941 };
6942
6943 // ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
6944 const uint8_t ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
6945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
6946 };
6947
6948 // ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Register Class...
6949 const MCPhysReg ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4[] = {
6950 AArch64::Z0_Z4_Z8_Z12,
6951 };
6952
6953 // ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4 Bit set.
6954 const uint8_t ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits[] = {
6955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
6956 };
6957
6958 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K Register Class...
6959 const MCPhysReg ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K[] = {
6960 AArch64::Z31_Z0_Z1_Z2,
6961 };
6962
6963 // ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K Bit set.
6964 const uint8_t ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits[] = {
6965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
6966 };
6967
6968 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi Register Class...
6969 const MCPhysReg ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi[] = {
6970 AArch64::Z30_Z31_Z0_Z1,
6971 };
6972
6973 // ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi Bit set.
6974 const uint8_t ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiBits[] = {
6975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
6976 };
6977
6978 // ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi Register Class...
6979 const MCPhysReg ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi[] = {
6980 AArch64::Z29_Z30_Z31_Z0,
6981 };
6982
6983 // ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi Bit set.
6984 const uint8_t ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits[] = {
6985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
6986 };
6987
6988 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Register Class...
6989 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4[] = {
6990 AArch64::Z23_Z24_Z25_Z26,
6991 };
6992
6993 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4 Bit set.
6994 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits[] = {
6995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
6996 };
6997
6998 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
6999 const MCPhysReg ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4[] = {
7000 AArch64::Z21_Z22_Z23_Z24,
7001 };
7002
7003 // ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
7004 const uint8_t ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
7005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
7006 };
7007
7008 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
7009 const MCPhysReg ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4[] = {
7010 AArch64::Z22_Z23_Z24_Z25,
7011 };
7012
7013 // ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
7014 const uint8_t ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
7015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
7016 };
7017
7018 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b Register Class...
7019 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b[] = {
7020 AArch64::Z3_Z4_Z5_Z6,
7021 };
7022
7023 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b Bit set.
7024 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bBits[] = {
7025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
7026 };
7027
7028 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b Register Class...
7029 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b[] = {
7030 AArch64::Z2_Z3_Z4_Z5,
7031 };
7032
7033 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b Bit set.
7034 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bBits[] = {
7035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
7036 };
7037
7038 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b Register Class...
7039 const MCPhysReg ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b[] = {
7040 AArch64::Z1_Z2_Z3_Z4,
7041 };
7042
7043 // ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b Bit set.
7044 const uint8_t ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bBits[] = {
7045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
7046 };
7047
7048 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi Register Class...
7049 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi[] = {
7050 AArch64::Z15_Z16_Z17_Z18,
7051 };
7052
7053 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi Bit set.
7054 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits[] = {
7055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
7056 };
7057
7058 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Hi Register Class...
7059 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Hi[] = {
7060 AArch64::Z14_Z15_Z16_Z17,
7061 };
7062
7063 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Hi Bit set.
7064 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_HiBits[] = {
7065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
7066 };
7067
7068 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4 Register Class...
7069 const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4[] = {
7070 AArch64::Z13_Z14_Z15_Z16,
7071 };
7072
7073 // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4 Bit set.
7074 const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits[] = {
7075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
7076 };
7077
7078 // GPR64x8Class Register Class...
7079 const MCPhysReg GPR64x8Class[] = {
7080 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7081 };
7082
7083 // GPR64x8Class Bit set.
7084 const uint8_t GPR64x8ClassBits[] = {
7085 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7f,
7086 };
7087
7088 // GPR64x8Class_with_x8sub_0_in_GPR64noip Register Class...
7089 const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip[] = {
7090 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7091 };
7092
7093 // GPR64x8Class_with_x8sub_0_in_GPR64noip Bit set.
7094 const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noipBits[] = {
7095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x6f,
7096 };
7097
7098 // GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class...
7099 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip[] = {
7100 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7101 };
7102
7103 // GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set.
7104 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = {
7105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x77,
7106 };
7107
7108 // GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7109 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7110 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7111 };
7112
7113 // GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7114 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7b,
7116 };
7117
7118 // GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7119 const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7120 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7121 };
7122
7123 // GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7124 const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7d,
7126 };
7127
7128 // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class...
7129 const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip[] = {
7130 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7131 };
7132
7133 // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set.
7134 const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = {
7135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x67,
7136 };
7137
7138 // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7139 const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7140 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7141 };
7142
7143 // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7144 const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x6b,
7146 };
7147
7148 // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7149 const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7150 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7151 };
7152
7153 // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7154 const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x6d,
7156 };
7157
7158 // GPR64x8Class_with_x8sub_0_in_tcGPR64 Register Class...
7159 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64[] = {
7160 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7161 };
7162
7163 // GPR64x8Class_with_x8sub_0_in_tcGPR64 Bit set.
7164 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64Bits[] = {
7165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f,
7166 };
7167
7168 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7169 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7170 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7171 };
7172
7173 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7174 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73,
7176 };
7177
7178 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7179 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7180 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7181 };
7182
7183 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7184 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x75,
7186 };
7187
7188 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7189 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7190 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7191 };
7192
7193 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7194 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x79,
7196 };
7197
7198 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class...
7199 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip[] = {
7200 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7201 };
7202
7203 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set.
7204 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = {
7205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x37,
7206 };
7207
7208 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7209 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7210 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7211 };
7212
7213 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7214 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7215 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3b,
7216 };
7217
7218 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7219 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7220 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7221 };
7222
7223 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7224 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7225 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3d,
7226 };
7227
7228 // GPR64x8Class_with_x8sub_0_in_tcGPRnotx16 Register Class...
7229 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPRnotx16[] = {
7230 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7231 };
7232
7233 // GPR64x8Class_with_x8sub_0_in_tcGPRnotx16 Bit set.
7234 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPRnotx16Bits[] = {
7235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x2f,
7236 };
7237
7238 // GPR64x8Class_with_x8sub_1_in_tcGPR64 Register Class...
7239 const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64[] = {
7240 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7241 };
7242
7243 // GPR64x8Class_with_x8sub_1_in_tcGPR64 Bit set.
7244 const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64Bits[] = {
7245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x1f,
7246 };
7247
7248 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7249 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7250 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7251 };
7252
7253 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7254 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x63,
7256 };
7257
7258 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7259 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7260 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7261 };
7262
7263 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7264 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x65,
7266 };
7267
7268 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7269 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7270 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7271 };
7272
7273 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7274 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7275 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x69,
7276 };
7277
7278 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7279 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7280 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7281 };
7282
7283 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7284 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7285 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x71,
7286 };
7287
7288 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class...
7289 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip[] = {
7290 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7291 };
7292
7293 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set.
7294 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = {
7295 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x27,
7296 };
7297
7298 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7299 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7300 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7301 };
7302
7303 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7304 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7305 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x2b,
7306 };
7307
7308 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7309 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7310 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7311 };
7312
7313 // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7314 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x2d,
7316 };
7317
7318 // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7319 const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7320 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7321 };
7322
7323 // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7324 const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x1b,
7326 };
7327
7328 // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7329 const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7330 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7331 };
7332
7333 // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7334 const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x1d,
7336 };
7337
7338 // GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17 Register Class...
7339 const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17[] = {
7340 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21,
7341 };
7342
7343 // GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17 Bit set.
7344 const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17Bits[] = {
7345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
7346 };
7347
7348 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7349 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7350 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7351 };
7352
7353 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7354 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x33,
7356 };
7357
7358 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7359 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7360 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7361 };
7362
7363 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7364 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x35,
7366 };
7367
7368 // GPR64x8Class_with_x8sub_2_in_tcGPRnotx16 Register Class...
7369 const MCPhysReg GPR64x8Class_with_x8sub_2_in_tcGPRnotx16[] = {
7370 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7371 };
7372
7373 // GPR64x8Class_with_x8sub_2_in_tcGPRnotx16 Bit set.
7374 const uint8_t GPR64x8Class_with_x8sub_2_in_tcGPRnotx16Bits[] = {
7375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x17,
7376 };
7377
7378 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7379 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7380 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7381 };
7382
7383 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7384 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x39,
7386 };
7387
7388 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7389 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7390 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7391 };
7392
7393 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7394 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x61,
7396 };
7397
7398 // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7399 const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7400 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21,
7401 };
7402
7403 // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7404 const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0d,
7406 };
7407
7408 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7409 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7410 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7411 };
7412
7413 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7414 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x23,
7416 };
7417
7418 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7419 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7420 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7421 };
7422
7423 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7424 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x25,
7426 };
7427
7428 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class...
7429 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = {
7430 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7431 };
7432
7433 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set.
7434 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = {
7435 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x13,
7436 };
7437
7438 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7439 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7440 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7441 };
7442
7443 // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7444 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x15,
7446 };
7447
7448 // GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17 Register Class...
7449 const MCPhysReg GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17[] = {
7450 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19,
7451 };
7452
7453 // GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17 Bit set.
7454 const uint8_t GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17Bits[] = {
7455 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
7456 };
7457
7458 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7459 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7460 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7461 };
7462
7463 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7464 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x29,
7466 };
7467
7468 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7469 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7470 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7471 };
7472
7473 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7474 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x19,
7476 };
7477
7478 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7479 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7480 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7481 };
7482
7483 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7484 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7485 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x31,
7486 };
7487
7488 // GPR64x8Class_with_x8sub_4_in_tcGPRnotx16 Register Class...
7489 const MCPhysReg GPR64x8Class_with_x8sub_4_in_tcGPRnotx16[] = {
7490 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21,
7491 };
7492
7493 // GPR64x8Class_with_x8sub_4_in_tcGPRnotx16 Bit set.
7494 const uint8_t GPR64x8Class_with_x8sub_4_in_tcGPRnotx16Bits[] = {
7495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0b,
7496 };
7497
7498 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7499 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7500 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21,
7501 };
7502
7503 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7504 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7505 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x09,
7506 };
7507
7508 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7509 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7510 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
7511 };
7512
7513 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7514 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7515 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x21,
7516 };
7517
7518 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class...
7519 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = {
7520 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7521 };
7522
7523 // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set.
7524 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = {
7525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x11,
7526 };
7527
7528 // GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17 Register Class...
7529 const MCPhysReg GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17[] = {
7530 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17,
7531 };
7532
7533 // GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17 Bit set.
7534 const uint8_t GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17Bits[] = {
7535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
7536 };
7537
7538 // GPR64x8Class_with_x8sub_6_in_tcGPRnotx16 Register Class...
7539 const MCPhysReg GPR64x8Class_with_x8sub_6_in_tcGPRnotx16[] = {
7540 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19,
7541 };
7542
7543 // GPR64x8Class_with_x8sub_6_in_tcGPRnotx16 Bit set.
7544 const uint8_t GPR64x8Class_with_x8sub_6_in_tcGPRnotx16Bits[] = {
7545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x05,
7546 };
7547
7548 // GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17 Register Class...
7549 const MCPhysReg GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17[] = {
7550 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15,
7551 };
7552
7553 // GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17 Bit set.
7554 const uint8_t GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17Bits[] = {
7555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
7556 };
7557
7558 // GPR64x8Class_with_sub_32_in_GPR32arg Register Class...
7559 const MCPhysReg GPR64x8Class_with_sub_32_in_GPR32arg[] = {
7560 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13,
7561 };
7562
7563 // GPR64x8Class_with_sub_32_in_GPR32arg Bit set.
7564 const uint8_t GPR64x8Class_with_sub_32_in_GPR32argBits[] = {
7565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
7566 };
7567
7568 // MPR32 Register Class...
7569 const MCPhysReg MPR32[] = {
7570 AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3,
7571 };
7572
7573 // MPR32 Bit set.
7574 const uint8_t MPR32Bits[] = {
7575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
7576 };
7577
7578 // GPR64x8Class_with_x8sub_2_in_GPR64arg Register Class...
7579 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64arg[] = {
7580 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11,
7581 };
7582
7583 // GPR64x8Class_with_x8sub_2_in_GPR64arg Bit set.
7584 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64argBits[] = {
7585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
7586 };
7587
7588 // GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15 Register Class...
7589 const MCPhysReg GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15[] = {
7590 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21,
7591 };
7592
7593 // GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15 Bit set.
7594 const uint8_t GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15Bits[] = {
7595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
7596 };
7597
7598 // GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7599 const MCPhysReg GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7600 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17,
7601 };
7602
7603 // GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7604 const uint8_t GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
7606 };
7607
7608 // GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Register Class...
7609 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15[] = {
7610 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19,
7611 };
7612
7613 // GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Bit set.
7614 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits[] = {
7615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
7616 };
7617
7618 // GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7619 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7620 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15,
7621 };
7622
7623 // GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7624 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
7626 };
7627
7628 // GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7629 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7630 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13,
7631 };
7632
7633 // GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7634 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
7636 };
7637
7638 // GPR64x8Class_with_x8sub_4_in_GPR64arg Register Class...
7639 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64arg[] = {
7640 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9,
7641 };
7642
7643 // GPR64x8Class_with_x8sub_4_in_GPR64arg Bit set.
7644 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64argBits[] = {
7645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
7646 };
7647
7648 // GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7649 const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7650 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11,
7651 };
7652
7653 // GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7654 const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
7656 };
7657
7658 // GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7659 const MCPhysReg GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7660 AArch64::X6_X7_X8_X9_X10_X11_X12_X13,
7661 };
7662
7663 // GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7664 const uint8_t GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7666 };
7667
7668 // GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7669 const MCPhysReg GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7670 AArch64::X8_X9_X10_X11_X12_X13_X14_X15,
7671 };
7672
7673 // GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7674 const uint8_t GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
7676 };
7677
7678 // GPR64x8Class_with_x8sub_0_in_tcGPRx16x17 Register Class...
7679 const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPRx16x17[] = {
7680 AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
7681 };
7682
7683 // GPR64x8Class_with_x8sub_0_in_tcGPRx16x17 Bit set.
7684 const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPRx16x17Bits[] = {
7685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
7686 };
7687
7688 // GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7689 const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7690 AArch64::X4_X5_X6_X7_X8_X9_X10_X11,
7691 };
7692
7693 // GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7694 const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
7696 };
7697
7698 // GPR64x8Class_with_x8sub_2_in_tcGPRx16x17 Register Class...
7699 const MCPhysReg GPR64x8Class_with_x8sub_2_in_tcGPRx16x17[] = {
7700 AArch64::X14_X15_X16_X17_X18_X19_X20_X21,
7701 };
7702
7703 // GPR64x8Class_with_x8sub_2_in_tcGPRx16x17 Bit set.
7704 const uint8_t GPR64x8Class_with_x8sub_2_in_tcGPRx16x17Bits[] = {
7705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
7706 };
7707
7708 // GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Register Class...
7709 const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11[] = {
7710 AArch64::X2_X3_X4_X5_X6_X7_X8_X9,
7711 };
7712
7713 // GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11 Bit set.
7714 const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits[] = {
7715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
7716 };
7717
7718 // GPR64x8Class_with_x8sub_4_in_tcGPRx16x17 Register Class...
7719 const MCPhysReg GPR64x8Class_with_x8sub_4_in_tcGPRx16x17[] = {
7720 AArch64::X12_X13_X14_X15_X16_X17_X18_X19,
7721 };
7722
7723 // GPR64x8Class_with_x8sub_4_in_tcGPRx16x17 Bit set.
7724 const uint8_t GPR64x8Class_with_x8sub_4_in_tcGPRx16x17Bits[] = {
7725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
7726 };
7727
7728 // GPR64x8Class_with_x8sub_6_in_GPR64arg Register Class...
7729 const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64arg[] = {
7730 AArch64::X0_X1_X2_X3_X4_X5_X6_X7,
7731 };
7732
7733 // GPR64x8Class_with_x8sub_6_in_GPR64arg Bit set.
7734 const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64argBits[] = {
7735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
7736 };
7737
7738 // GPR64x8Class_with_x8sub_6_in_tcGPRx16x17 Register Class...
7739 const MCPhysReg GPR64x8Class_with_x8sub_6_in_tcGPRx16x17[] = {
7740 AArch64::X10_X11_X12_X13_X14_X15_X16_X17,
7741 };
7742
7743 // GPR64x8Class_with_x8sub_6_in_tcGPRx16x17 Bit set.
7744 const uint8_t GPR64x8Class_with_x8sub_6_in_tcGPRx16x17Bits[] = {
7745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
7746 };
7747
7748 // GPR64x8Class_with_x8sub_7_in_FIXED_REGS Register Class...
7749 const MCPhysReg GPR64x8Class_with_x8sub_7_in_FIXED_REGS[] = {
7750 AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
7751 };
7752
7753 // GPR64x8Class_with_x8sub_7_in_FIXED_REGS Bit set.
7754 const uint8_t GPR64x8Class_with_x8sub_7_in_FIXED_REGSBits[] = {
7755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
7756 };
7757
7758 // ZTR Register Class...
7759 const MCPhysReg ZTR[] = {
7760 AArch64::ZT0,
7761 };
7762
7763 // ZTR Bit set.
7764 const uint8_t ZTRBits[] = {
7765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
7766 };
7767
7768 // MPR16 Register Class...
7769 const MCPhysReg MPR16[] = {
7770 AArch64::ZAH0, AArch64::ZAH1,
7771 };
7772
7773 // MPR16 Bit set.
7774 const uint8_t MPR16Bits[] = {
7775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
7776 };
7777
7778 // MPR Register Class...
7779 const MCPhysReg MPR[] = {
7780 AArch64::ZA,
7781 };
7782
7783 // MPR Bit set.
7784 const uint8_t MPRBits[] = {
7785 0x00, 0x80,
7786 };
7787
7788 // MPR8 Register Class...
7789 const MCPhysReg MPR8[] = {
7790 AArch64::ZAB0,
7791 };
7792
7793 // MPR8 Bit set.
7794 const uint8_t MPR8Bits[] = {
7795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
7796 };
7797
7798} // namespace
7799
7800#ifdef __GNUC__
7801#pragma GCC diagnostic push
7802#pragma GCC diagnostic ignored "-Woverlength-strings"
7803#endif
7804extern const char AArch64RegClassStrings[] = {
7805 /* 0 */ "GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11\000"
7806 /* 126 */ "GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11\000"
7807 /* 239 */ "XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11\000"
7808 /* 312 */ "GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11\000"
7809 /* 426 */ "GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11\000"
7810 /* 540 */ "GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11\000"
7811 /* 590 */ "WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11\000"
7812 /* 642 */ "FPR32\000"
7813 /* 648 */ "GPR32\000"
7814 /* 654 */ "MPR32\000"
7815 /* 660 */ "FIXED_REGS_with_sub_32\000"
7816 /* 683 */ "PPR2\000"
7817 /* 688 */ "ZPR2\000"
7818 /* 693 */ "PPR2Mul2\000"
7819 /* 702 */ "ZPR3_with_zsub0_zsub1_in_ZPR2Mul2\000"
7820 /* 736 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2\000"
7821 /* 770 */ "PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2\000"
7822 /* 830 */ "PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2\000"
7823 /* 886 */ "ZPR2Strided_with_zsub0_in_ZPRMul2\000"
7824 /* 920 */ "ZPR4Strided_with_zsub0_in_ZPRMul2\000"
7825 /* 954 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2\000"
7826 /* 1000 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2\000"
7827 /* 1046 */ "ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2\000"
7828 /* 1107 */ "ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2\000"
7829 /* 1211 */ "ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2\000"
7830 /* 1270 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2\000"
7831 /* 1331 */ "ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2\000"
7832 /* 1387 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2\000"
7833 /* 1446 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2\000"
7834 /* 1507 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2\000"
7835 /* 1563 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2\000"
7836 /* 1622 */ "ZPR3\000"
7837 /* 1627 */ "FPR64\000"
7838 /* 1633 */ "FIXED_REGS_and_GPR64\000"
7839 /* 1654 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64\000"
7840 /* 1691 */ "GPR64x8Class_with_x8sub_1_in_tcGPR64\000"
7841 /* 1728 */ "XSeqPairsClass_with_sube64_in_tcGPR64\000"
7842 /* 1766 */ "XSeqPairsClass_with_subo64_in_tcGPR64\000"
7843 /* 1804 */ "MPR64\000"
7844 /* 1810 */ "ZPR4\000"
7845 /* 1815 */ "ZPR4Mul4\000"
7846 /* 1824 */ "ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4\000"
7847 /* 1873 */ "ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4\000"
7848 /* 1922 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4\000"
7849 /* 1983 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4\000"
7850 /* 2044 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4\000"
7851 /* 2229 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4\000"
7852 /* 2372 */ "ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4\000"
7853 /* 2508 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4\000"
7854 /* 2579 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4\000"
7855 /* 2653 */ "ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4\000"
7856 /* 2702 */ "ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4\000"
7857 /* 2751 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4\000"
7858 /* 2812 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4\000"
7859 /* 2873 */ "ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4\000"
7860 /* 2947 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4\000"
7861 /* 3021 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4\000"
7862 /* 3095 */ "ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7863 /* 3163 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7864 /* 3231 */ "ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7865 /* 3328 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7866 /* 3456 */ "ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7867 /* 3555 */ "ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7868 /* 3623 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7869 /* 3691 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7870 /* 3791 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7871 /* 3922 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4\000"
7872 /* 4053 */ "ZPR3_with_zsub0_in_ZPRMul4\000"
7873 /* 4080 */ "ZPR2Strided_with_zsub0_in_ZPRMul4\000"
7874 /* 4114 */ "ZPR4Strided_with_zsub0_in_ZPRMul4\000"
7875 /* 4148 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4\000"
7876 /* 4194 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4\000"
7877 /* 4240 */ "ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4\000"
7878 /* 4301 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4\000"
7879 /* 4471 */ "ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4\000"
7880 /* 4530 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4\000"
7881 /* 4591 */ "ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4\000"
7882 /* 4647 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4\000"
7883 /* 4706 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4\000"
7884 /* 4767 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4\000"
7885 /* 4823 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4\000"
7886 /* 4882 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4\000"
7887 /* 4943 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4\000"
7888 /* 5071 */ "ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4\000"
7889 /* 5192 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4\000"
7890 /* 5251 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4\000"
7891 /* 5312 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4\000"
7892 /* 5371 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4\000"
7893 /* 5432 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4\000"
7894 /* 5491 */ "GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15\000"
7895 /* 5564 */ "XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15\000"
7896 /* 5638 */ "GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15\000"
7897 /* 5689 */ "WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15\000"
7898 /* 5742 */ "PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15\000"
7899 /* 5784 */ "PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15\000"
7900 /* 5859 */ "PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15\000"
7901 /* 5922 */ "PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15\000"
7902 /* 5981 */ "FPR16\000"
7903 /* 5987 */ "MPR16\000"
7904 /* 5993 */ "GPR64x8Class_with_x8sub_0_in_tcGPRnotx16\000"
7905 /* 6034 */ "GPR64x8Class_with_x8sub_2_in_tcGPRnotx16\000"
7906 /* 6075 */ "XSeqPairsClass_with_sube64_in_tcGPRnotx16\000"
7907 /* 6117 */ "GPR64x8Class_with_x8sub_4_in_tcGPRnotx16\000"
7908 /* 6158 */ "GPR64x8Class_with_x8sub_6_in_tcGPRnotx16\000"
7909 /* 6199 */ "GPR64x8Class_with_x8sub_0_in_tcGPRx16x17\000"
7910 /* 6240 */ "GPR64x8Class_with_x8sub_2_in_tcGPRx16x17\000"
7911 /* 6281 */ "XSeqPairsClass_with_sube64_in_tcGPRx16x17\000"
7912 /* 6323 */ "GPR64x8Class_with_x8sub_4_in_tcGPRx16x17\000"
7913 /* 6364 */ "GPR64x8Class_with_x8sub_6_in_tcGPRx16x17\000"
7914 /* 6405 */ "GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17\000"
7915 /* 6449 */ "GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17\000"
7916 /* 6493 */ "XSeqPairsClass_with_subo64_in_tcGPRnotx16x17\000"
7917 /* 6538 */ "GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17\000"
7918 /* 6582 */ "GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17\000"
7919 /* 6626 */ "tcGPRx17\000"
7920 /* 6635 */ "QQQQ_with_qsub0_in_FPR128_0to7\000"
7921 /* 6666 */ "ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7\000"
7922 /* 6731 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7\000"
7923 /* 6796 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7\000"
7924 /* 6861 */ "QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7\000"
7925 /* 6927 */ "QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7\000"
7926 /* 6991 */ "QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7\000"
7927 /* 7053 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7\000"
7928 /* 7118 */ "ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7\000"
7929 /* 7181 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7\000"
7930 /* 7246 */ "ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7\000"
7931 /* 7309 */ "QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7\000"
7932 /* 7375 */ "QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7\000"
7933 /* 7438 */ "QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7\000"
7934 /* 7502 */ "QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7\000"
7935 /* 7563 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7\000"
7936 /* 7628 */ "ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7\000"
7937 /* 7691 */ "ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7\000"
7938 /* 7754 */ "QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7\000"
7939 /* 7820 */ "QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7\000"
7940 /* 7883 */ "QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7\000"
7941 /* 7946 */ "ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7\000"
7942 /* 8014 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7\000"
7943 /* 8082 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7\000"
7944 /* 8184 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7\000"
7945 /* 8317 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7\000"
7946 /* 8450 */ "ZPR3_with_zsub_in_FPR128_0to7\000"
7947 /* 8480 */ "ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7\000"
7948 /* 8523 */ "ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7\000"
7949 /* 8572 */ "ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7\000"
7950 /* 8621 */ "FPR128\000"
7951 /* 8628 */ "MPR128\000"
7952 /* 8635 */ "FPR8\000"
7953 /* 8640 */ "MPR8\000"
7954 /* 8645 */ "B_HI_DummyRC\000"
7955 /* 8658 */ "D_HI_DummyRC\000"
7956 /* 8671 */ "H_HI_DummyRC\000"
7957 /* 8684 */ "Q_HI_DummyRC\000"
7958 /* 8697 */ "S_HI_DummyRC\000"
7959 /* 8710 */ "W_HI_DummyRC\000"
7960 /* 8723 */ "DDDD\000"
7961 /* 8728 */ "ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_K\000"
7962 /* 8772 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_K\000"
7963 /* 8828 */ "ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K\000"
7964 /* 8894 */ "ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_K\000"
7965 /* 8931 */ "ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_K\000"
7966 /* 8968 */ "ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_K\000"
7967 /* 9005 */ "ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_K\000"
7968 /* 9042 */ "ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_K\000"
7969 /* 9086 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_K\000"
7970 /* 9142 */ "ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_K\000"
7971 /* 9179 */ "ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_K\000"
7972 /* 9216 */ "ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_K\000"
7973 /* 9253 */ "ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_K\000"
7974 /* 9290 */ "ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_K\000"
7975 /* 9327 */ "ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_K\000"
7976 /* 9364 */ "ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K\000"
7977 /* 9427 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K\000"
7978 /* 9490 */ "ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K\000"
7979 /* 9582 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K\000"
7980 /* 9705 */ "ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K\000"
7981 /* 9799 */ "ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_K\000"
7982 /* 9856 */ "ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K\000"
7983 /* 9913 */ "ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K\000"
7984 /* 9970 */ "ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_K\000"
7985 /* 10008 */ "ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K\000"
7986 /* 10065 */ "ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K\000"
7987 /* 10122 */ "ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K\000"
7988 /* 10179 */ "ZPR2Strided_with_zsub0_in_ZPR_K\000"
7989 /* 10211 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPR_K\000"
7990 /* 10255 */ "ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_K\000"
7991 /* 10309 */ "ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_K\000"
7992 /* 10363 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_K\000"
7993 /* 10417 */ "ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_K\000"
7994 /* 10474 */ "ZPR4Strided_with_zsub1_in_ZPR_K\000"
7995 /* 10506 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K\000"
7996 /* 10600 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K\000"
7997 /* 10694 */ "ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K\000"
7998 /* 10748 */ "ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K\000"
7999 /* 10802 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K\000"
8000 /* 10856 */ "ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K\000"
8001 /* 10910 */ "ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K\000"
8002 /* 10964 */ "ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K\000"
8003 /* 11018 */ "QQQQ\000"
8004 /* 11023 */ "CCR\000"
8005 /* 11027 */ "PPRorPNR\000"
8006 /* 11036 */ "MPR\000"
8007 /* 11040 */ "PPR\000"
8008 /* 11044 */ "ZPR\000"
8009 /* 11048 */ "ZTR\000"
8010 /* 11052 */ "XSeqPairsClass_with_subo64_in_FIXED_REGS\000"
8011 /* 11093 */ "GPR64x8Class_with_x8sub_7_in_FIXED_REGS\000"
8012 /* 11133 */ "PPR2Mul2_and_PPR2_with_psub_in_PNR_3b\000"
8013 /* 11171 */ "PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3b\000"
8014 /* 11238 */ "PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3b\000"
8015 /* 11297 */ "PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3b\000"
8016 /* 11352 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b\000"
8017 /* 11409 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b\000"
8018 /* 11466 */ "ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b\000"
8019 /* 11538 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b\000"
8020 /* 11610 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b\000"
8021 /* 11682 */ "ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b\000"
8022 /* 11752 */ "ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3b\000"
8023 /* 11790 */ "ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3b\000"
8024 /* 11828 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b\000"
8025 /* 11885 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b\000"
8026 /* 11942 */ "ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b\000"
8027 /* 12014 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b\000"
8028 /* 12086 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b\000"
8029 /* 12158 */ "ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b\000"
8030 /* 12230 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b\000"
8031 /* 12302 */ "ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b\000"
8032 /* 12374 */ "ZPR_4b\000"
8033 /* 12381 */ "ZPR2Strided\000"
8034 /* 12393 */ "ZPR4Strided\000"
8035 /* 12405 */ "GPR64x8Class_with_sub_32_in_GPR32arg\000"
8036 /* 12442 */ "WSeqPairsClass_with_sube32_in_GPR32arg\000"
8037 /* 12481 */ "GPR64x8Class_with_x8sub_2_in_GPR64arg\000"
8038 /* 12519 */ "XSeqPairsClass_with_sube64_in_GPR64arg\000"
8039 /* 12558 */ "GPR64x8Class_with_x8sub_4_in_GPR64arg\000"
8040 /* 12596 */ "GPR64x8Class_with_x8sub_6_in_GPR64arg\000"
8041 /* 12634 */ "ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi\000"
8042 /* 12703 */ "ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi\000"
8043 /* 12772 */ "ZPR2Strided_with_zsub0_in_ZPRMul2_Hi\000"
8044 /* 12809 */ "ZPR4Strided_with_zsub0_in_ZPRMul2_Hi\000"
8045 /* 12846 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi\000"
8046 /* 12895 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi\000"
8047 /* 12944 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi\000"
8048 /* 13117 */ "ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi\000"
8049 /* 13283 */ "ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Hi\000"
8050 /* 13345 */ "ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_Hi\000"
8051 /* 13404 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Hi\000"
8052 /* 13466 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_Hi\000"
8053 /* 13525 */ "ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi\000"
8054 /* 13587 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi\000"
8055 /* 13649 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi\000"
8056 /* 13780 */ "ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi\000"
8057 /* 13904 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Hi\000"
8058 /* 13966 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Hi\000"
8059 /* 14028 */ "ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi\000"
8060 /* 14087 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi\000"
8061 /* 14149 */ "GPR32all\000"
8062 /* 14158 */ "GPR64all\000"
8063 /* 14167 */ "WSeqPairsClass_with_subo32_in_GPR32common\000"
8064 /* 14209 */ "XSeqPairsClass_with_subo64_in_GPR64common\000"
8065 /* 14251 */ "ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo\000"
8066 /* 14288 */ "ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo\000"
8067 /* 14325 */ "ZPR2Strided_with_zsub0_in_ZPRMul2_Lo\000"
8068 /* 14362 */ "ZPR4Strided_with_zsub0_in_ZPRMul2_Lo\000"
8069 /* 14399 */ "ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo\000"
8070 /* 14448 */ "ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo\000"
8071 /* 14497 */ "ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo\000"
8072 /* 14559 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Lo\000"
8073 /* 14621 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Lo\000"
8074 /* 14683 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo\000"
8075 /* 14745 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Lo\000"
8076 /* 14807 */ "ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo\000"
8077 /* 14869 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo\000"
8078 /* 14931 */ "DDDD_with_dsub0_in_FPR64_lo\000"
8079 /* 14959 */ "ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_lo\000"
8080 /* 15019 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_lo\000"
8081 /* 15079 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_lo\000"
8082 /* 15139 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo\000"
8083 /* 15199 */ "DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo\000"
8084 /* 15257 */ "DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo\000"
8085 /* 15313 */ "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_lo\000"
8086 /* 15374 */ "QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_lo\000"
8087 /* 15433 */ "QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_lo\000"
8088 /* 15490 */ "ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_lo\000"
8089 /* 15550 */ "ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_lo\000"
8090 /* 15610 */ "ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_lo\000"
8091 /* 15670 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_lo\000"
8092 /* 15730 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo\000"
8093 /* 15790 */ "DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo\000"
8094 /* 15850 */ "DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo\000"
8095 /* 15908 */ "DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo\000"
8096 /* 15966 */ "QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_lo\000"
8097 /* 16026 */ "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_lo\000"
8098 /* 16087 */ "QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_lo\000"
8099 /* 16145 */ "QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_lo\000"
8100 /* 16204 */ "ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo\000"
8101 /* 16264 */ "ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo\000"
8102 /* 16324 */ "ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_lo\000"
8103 /* 16384 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\000"
8104 /* 16444 */ "DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\000"
8105 /* 16504 */ "DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\000"
8106 /* 16564 */ "QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo\000"
8107 /* 16624 */ "QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo\000"
8108 /* 16684 */ "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_lo\000"
8109 /* 16745 */ "ZPR2Strided_with_dsub_in_FPR64_lo\000"
8110 /* 16779 */ "ZPR4Strided_with_dsub_in_FPR64_lo\000"
8111 /* 16813 */ "ZPR2StridedOrContiguous_with_dsub_in_FPR64_lo\000"
8112 /* 16859 */ "ZPR4StridedOrContiguous_with_dsub_in_FPR64_lo\000"
8113 /* 16905 */ "FPR32_with_hsub_in_FPR16_lo\000"
8114 /* 16933 */ "QQQQ_with_qsub0_in_FPR128_lo\000"
8115 /* 16962 */ "ZPR2_with_zsub_in_FPR128_lo\000"
8116 /* 16990 */ "ZPR3_with_zsub_in_FPR128_lo\000"
8117 /* 17018 */ "ZPR4_with_zsub_in_FPR128_lo\000"
8118 /* 17046 */ "GPR64common_and_GPR64noip\000"
8119 /* 17072 */ "GPR64x8Class_with_x8sub_0_in_GPR64noip\000"
8120 /* 17111 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip\000"
8121 /* 17191 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip\000"
8122 /* 17314 */ "XSeqPairsClass_with_sube64_in_GPR64noip\000"
8123 /* 17354 */ "XSeqPairsClass_with_subo64_in_GPR64noip\000"
8124 /* 17394 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\000"
8125 /* 17517 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\000"
8126 /* 17640 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\000"
8127 /* 17806 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\000"
8128 /* 17931 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\000"
8129 /* 18013 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8130 /* 18179 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8131 /* 18302 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8132 /* 18468 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8133 /* 18591 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8134 /* 18800 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8135 /* 18966 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8136 /* 19132 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8137 /* 19300 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8138 /* 19425 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8139 /* 19550 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\000"
8140 /* 19632 */ "GPR32sp\000"
8141 /* 19640 */ "GPR64sp\000"
8142 /* 19648 */ "GPR64x8Class\000"
8143 /* 19661 */ "WSeqPairsClass\000"
8144 /* 19676 */ "XSeqPairsClass\000"
8145 /* 19691 */ "ZPR2StridedOrContiguous\000"
8146 /* 19715 */ "ZPR4StridedOrContiguous\000"
8147 /* 19739 */ "GPR32sponly\000"
8148 /* 19751 */ "GPR64sponly\000"
8149};
8150#ifdef __GNUC__
8151#pragma GCC diagnostic pop
8152#endif
8153
8154extern const MCRegisterClass AArch64MCRegisterClasses[] = {
8155 { .RegsBegin: W_HI_DummyRC, .RegSet: W_HI_DummyRCBits, .NameIdx: 8710, .RegsSize: 33, .RegSetSize: sizeof(W_HI_DummyRCBits), .ID: AArch64::W_HI_DummyRCRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8156 { .RegsBegin: B_HI_DummyRC, .RegSet: B_HI_DummyRCBits, .NameIdx: 8645, .RegsSize: 32, .RegSetSize: sizeof(B_HI_DummyRCBits), .ID: AArch64::B_HI_DummyRCRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8157 { .RegsBegin: D_HI_DummyRC, .RegSet: D_HI_DummyRCBits, .NameIdx: 8658, .RegsSize: 32, .RegSetSize: sizeof(D_HI_DummyRCBits), .ID: AArch64::D_HI_DummyRCRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8158 { .RegsBegin: H_HI_DummyRC, .RegSet: H_HI_DummyRCBits, .NameIdx: 8671, .RegsSize: 32, .RegSetSize: sizeof(H_HI_DummyRCBits), .ID: AArch64::H_HI_DummyRCRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8159 { .RegsBegin: Q_HI_DummyRC, .RegSet: Q_HI_DummyRCBits, .NameIdx: 8684, .RegsSize: 32, .RegSetSize: sizeof(Q_HI_DummyRCBits), .ID: AArch64::Q_HI_DummyRCRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8160 { .RegsBegin: S_HI_DummyRC, .RegSet: S_HI_DummyRCBits, .NameIdx: 8697, .RegsSize: 32, .RegSetSize: sizeof(S_HI_DummyRCBits), .ID: AArch64::S_HI_DummyRCRegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8161 { .RegsBegin: FPR8, .RegSet: FPR8Bits, .NameIdx: 8635, .RegsSize: 32, .RegSetSize: sizeof(FPR8Bits), .ID: AArch64::FPR8RegClassID, .RegSizeInBits: 8, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8162 { .RegsBegin: FPR16, .RegSet: FPR16Bits, .NameIdx: 5981, .RegsSize: 32, .RegSetSize: sizeof(FPR16Bits), .ID: AArch64::FPR16RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8163 { .RegsBegin: PPRorPNR, .RegSet: PPRorPNRBits, .NameIdx: 11027, .RegsSize: 32, .RegSetSize: sizeof(PPRorPNRBits), .ID: AArch64::PPRorPNRRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8164 { .RegsBegin: FPR16_lo, .RegSet: FPR16_loBits, .NameIdx: 16924, .RegsSize: 16, .RegSetSize: sizeof(FPR16_loBits), .ID: AArch64::FPR16_loRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8165 { .RegsBegin: PNR, .RegSet: PNRBits, .NameIdx: 11032, .RegsSize: 16, .RegSetSize: sizeof(PNRBits), .ID: AArch64::PNRRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8166 { .RegsBegin: PPR, .RegSet: PPRBits, .NameIdx: 11040, .RegsSize: 16, .RegSetSize: sizeof(PPRBits), .ID: AArch64::PPRRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8167 { .RegsBegin: PNR_3b, .RegSet: PNR_3bBits, .NameIdx: 11164, .RegsSize: 8, .RegSetSize: sizeof(PNR_3bBits), .ID: AArch64::PNR_3bRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8168 { .RegsBegin: PNR_p8to15, .RegSet: PNR_p8to15Bits, .NameIdx: 5773, .RegsSize: 8, .RegSetSize: sizeof(PNR_p8to15Bits), .ID: AArch64::PNR_p8to15RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8169 { .RegsBegin: PPRMul2, .RegSet: PPRMul2Bits, .NameIdx: 822, .RegsSize: 8, .RegSetSize: sizeof(PPRMul2Bits), .ID: AArch64::PPRMul2RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8170 { .RegsBegin: PPR_3b, .RegSet: PPR_3bBits, .NameIdx: 11231, .RegsSize: 8, .RegSetSize: sizeof(PPR_3bBits), .ID: AArch64::PPR_3bRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8171 { .RegsBegin: PPR_p8to15, .RegSet: PPR_p8to15Bits, .NameIdx: 5848, .RegsSize: 8, .RegSetSize: sizeof(PPR_p8to15Bits), .ID: AArch64::PPR_p8to15RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8172 { .RegsBegin: PPRMul2_and_PPR_3b, .RegSet: PPRMul2_and_PPR_3bBits, .NameIdx: 11219, .RegsSize: 4, .RegSetSize: sizeof(PPRMul2_and_PPR_3bBits), .ID: AArch64::PPRMul2_and_PPR_3bRegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8173 { .RegsBegin: PPRMul2_and_PPR_p8to15, .RegSet: PPRMul2_and_PPR_p8to15Bits, .NameIdx: 5836, .RegsSize: 4, .RegSetSize: sizeof(PPRMul2_and_PPR_p8to15Bits), .ID: AArch64::PPRMul2_and_PPR_p8to15RegClassID, .RegSizeInBits: 16, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8174 { .RegsBegin: PPR2, .RegSet: PPR2Bits, .NameIdx: 683, .RegsSize: 16, .RegSetSize: sizeof(PPR2Bits), .ID: AArch64::PPR2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8175 { .RegsBegin: PPR2Mul2, .RegSet: PPR2Mul2Bits, .NameIdx: 693, .RegsSize: 8, .RegSetSize: sizeof(PPR2Mul2Bits), .ID: AArch64::PPR2Mul2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8176 { .RegsBegin: PPR2_with_psub1_in_PPRMul2, .RegSet: PPR2_with_psub1_in_PPRMul2Bits, .NameIdx: 803, .RegsSize: 8, .RegSetSize: sizeof(PPR2_with_psub1_in_PPRMul2Bits), .ID: AArch64::PPR2_with_psub1_in_PPRMul2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8177 { .RegsBegin: PPR2_with_psub1_in_PPR_3b, .RegSet: PPR2_with_psub1_in_PPR_3bBits, .NameIdx: 11271, .RegsSize: 8, .RegSetSize: sizeof(PPR2_with_psub1_in_PPR_3bBits), .ID: AArch64::PPR2_with_psub1_in_PPR_3bRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8178 { .RegsBegin: PPR2_with_psub1_in_PPR_p8to15, .RegSet: PPR2_with_psub1_in_PPR_p8to15Bits, .NameIdx: 5892, .RegsSize: 8, .RegSetSize: sizeof(PPR2_with_psub1_in_PPR_p8to15Bits), .ID: AArch64::PPR2_with_psub1_in_PPR_p8to15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8179 { .RegsBegin: PPR2_with_psub_in_PNR_3b, .RegSet: PPR2_with_psub_in_PNR_3bBits, .NameIdx: 11146, .RegsSize: 8, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_3bBits), .ID: AArch64::PPR2_with_psub_in_PNR_3bRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8180 { .RegsBegin: PPR2_with_psub_in_PNR_p8to15, .RegSet: PPR2_with_psub_in_PNR_p8to15Bits, .NameIdx: 5755, .RegsSize: 8, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_p8to15Bits), .ID: AArch64::PPR2_with_psub_in_PNR_p8to15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8181 { .RegsBegin: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3b, .RegSet: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3bBits, .NameIdx: 11297, .RegsSize: 7, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3bBits), .ID: AArch64::PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_3bRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8182 { .RegsBegin: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15, .RegSet: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15Bits, .NameIdx: 5859, .RegsSize: 7, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15Bits), .ID: AArch64::PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_p8to15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8183 { .RegsBegin: PPR2Mul2_and_PPR2_with_psub_in_PNR_3b, .RegSet: PPR2Mul2_and_PPR2_with_psub_in_PNR_3bBits, .NameIdx: 11133, .RegsSize: 4, .RegSetSize: sizeof(PPR2Mul2_and_PPR2_with_psub_in_PNR_3bBits), .ID: AArch64::PPR2Mul2_and_PPR2_with_psub_in_PNR_3bRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8184 { .RegsBegin: PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15, .RegSet: PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15Bits, .NameIdx: 5742, .RegsSize: 4, .RegSetSize: sizeof(PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15Bits), .ID: AArch64::PPR2Mul2_and_PPR2_with_psub_in_PNR_p8to15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8185 { .RegsBegin: PPR2_with_psub1_in_PPRMul2_and_PPR_3b, .RegSet: PPR2_with_psub1_in_PPRMul2_and_PPR_3bBits, .NameIdx: 11200, .RegsSize: 4, .RegSetSize: sizeof(PPR2_with_psub1_in_PPRMul2_and_PPR_3bBits), .ID: AArch64::PPR2_with_psub1_in_PPRMul2_and_PPR_3bRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8186 { .RegsBegin: PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15, .RegSet: PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15Bits, .NameIdx: 5817, .RegsSize: 4, .RegSetSize: sizeof(PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15Bits), .ID: AArch64::PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8187 { .RegsBegin: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2, .RegSet: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2Bits, .NameIdx: 830, .RegsSize: 4, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2Bits), .ID: AArch64::PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8188 { .RegsBegin: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2, .RegSet: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2Bits, .NameIdx: 770, .RegsSize: 4, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2Bits), .ID: AArch64::PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8189 { .RegsBegin: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3b, .RegSet: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3bBits, .NameIdx: 11171, .RegsSize: 3, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3bBits), .ID: AArch64::PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPRMul2_and_PPR_3bRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8190 { .RegsBegin: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15, .RegSet: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15Bits, .NameIdx: 5784, .RegsSize: 3, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15Bits), .ID: AArch64::PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPRMul2_and_PPR_p8to15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8191 { .RegsBegin: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15, .RegSet: PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15Bits, .NameIdx: 5922, .RegsSize: 1, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15Bits), .ID: AArch64::PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8192 { .RegsBegin: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3b, .RegSet: PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3bBits, .NameIdx: 11238, .RegsSize: 1, .RegSetSize: sizeof(PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3bBits), .ID: AArch64::PPR2_with_psub_in_PNR_p8to15_and_PPR2_with_psub1_in_PPR_3bRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8193 { .RegsBegin: GPR32all, .RegSet: GPR32allBits, .NameIdx: 14149, .RegsSize: 33, .RegSetSize: sizeof(GPR32allBits), .ID: AArch64::GPR32allRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8194 { .RegsBegin: FPR32, .RegSet: FPR32Bits, .NameIdx: 642, .RegsSize: 32, .RegSetSize: sizeof(FPR32Bits), .ID: AArch64::FPR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8195 { .RegsBegin: GPR32, .RegSet: GPR32Bits, .NameIdx: 648, .RegsSize: 32, .RegSetSize: sizeof(GPR32Bits), .ID: AArch64::GPR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8196 { .RegsBegin: GPR32sp, .RegSet: GPR32spBits, .NameIdx: 19632, .RegsSize: 32, .RegSetSize: sizeof(GPR32spBits), .ID: AArch64::GPR32spRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8197 { .RegsBegin: GPR32common, .RegSet: GPR32commonBits, .NameIdx: 14197, .RegsSize: 31, .RegSetSize: sizeof(GPR32commonBits), .ID: AArch64::GPR32commonRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8198 { .RegsBegin: FPR32_with_hsub_in_FPR16_lo, .RegSet: FPR32_with_hsub_in_FPR16_loBits, .NameIdx: 16905, .RegsSize: 16, .RegSetSize: sizeof(FPR32_with_hsub_in_FPR16_loBits), .ID: AArch64::FPR32_with_hsub_in_FPR16_loRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8199 { .RegsBegin: GPR32arg, .RegSet: GPR32argBits, .NameIdx: 12433, .RegsSize: 8, .RegSetSize: sizeof(GPR32argBits), .ID: AArch64::GPR32argRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8200 { .RegsBegin: MatrixIndexGPR32_12_15, .RegSet: MatrixIndexGPR32_12_15Bits, .NameIdx: 5541, .RegsSize: 4, .RegSetSize: sizeof(MatrixIndexGPR32_12_15Bits), .ID: AArch64::MatrixIndexGPR32_12_15RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8201 { .RegsBegin: MatrixIndexGPR32_8_11, .RegSet: MatrixIndexGPR32_8_11Bits, .NameIdx: 104, .RegsSize: 4, .RegSetSize: sizeof(MatrixIndexGPR32_8_11Bits), .ID: AArch64::MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8202 { .RegsBegin: CCR, .RegSet: CCRBits, .NameIdx: 11023, .RegsSize: 1, .RegSetSize: sizeof(CCRBits), .ID: AArch64::CCRRegClassID, .RegSizeInBits: 32, .CopyCost: 255, .Allocatable: false, .BaseClass: false },
8203 { .RegsBegin: GPR32sponly, .RegSet: GPR32sponlyBits, .NameIdx: 19739, .RegsSize: 1, .RegSetSize: sizeof(GPR32sponlyBits), .ID: AArch64::GPR32sponlyRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8204 { .RegsBegin: WSeqPairsClass, .RegSet: WSeqPairsClassBits, .NameIdx: 19661, .RegsSize: 16, .RegSetSize: sizeof(WSeqPairsClassBits), .ID: AArch64::WSeqPairsClassRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8205 { .RegsBegin: WSeqPairsClass_with_subo32_in_GPR32common, .RegSet: WSeqPairsClass_with_subo32_in_GPR32commonBits, .NameIdx: 14167, .RegsSize: 15, .RegSetSize: sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), .ID: AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8206 { .RegsBegin: WSeqPairsClass_with_sube32_in_GPR32arg, .RegSet: WSeqPairsClass_with_sube32_in_GPR32argBits, .NameIdx: 12442, .RegsSize: 4, .RegSetSize: sizeof(WSeqPairsClass_with_sube32_in_GPR32argBits), .ID: AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8207 { .RegsBegin: WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15, .RegSet: WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15Bits, .NameIdx: 5689, .RegsSize: 2, .RegSetSize: sizeof(WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15Bits), .ID: AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8208 { .RegsBegin: WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11, .RegSet: WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 590, .RegsSize: 2, .RegSetSize: sizeof(WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8209 { .RegsBegin: GPR64all, .RegSet: GPR64allBits, .NameIdx: 14158, .RegsSize: 33, .RegSetSize: sizeof(GPR64allBits), .ID: AArch64::GPR64allRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8210 { .RegsBegin: FPR64, .RegSet: FPR64Bits, .NameIdx: 1627, .RegsSize: 32, .RegSetSize: sizeof(FPR64Bits), .ID: AArch64::FPR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8211 { .RegsBegin: GPR64, .RegSet: GPR64Bits, .NameIdx: 1648, .RegsSize: 32, .RegSetSize: sizeof(GPR64Bits), .ID: AArch64::GPR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8212 { .RegsBegin: GPR64sp, .RegSet: GPR64spBits, .NameIdx: 19640, .RegsSize: 32, .RegSetSize: sizeof(GPR64spBits), .ID: AArch64::GPR64spRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8213 { .RegsBegin: GPR64common, .RegSet: GPR64commonBits, .NameIdx: 14239, .RegsSize: 31, .RegSetSize: sizeof(GPR64commonBits), .ID: AArch64::GPR64commonRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8214 { .RegsBegin: GPR64noip, .RegSet: GPR64noipBits, .NameIdx: 17062, .RegsSize: 29, .RegSetSize: sizeof(GPR64noipBits), .ID: AArch64::GPR64noipRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8215 { .RegsBegin: GPR64common_and_GPR64noip, .RegSet: GPR64common_and_GPR64noipBits, .NameIdx: 17046, .RegsSize: 28, .RegSetSize: sizeof(GPR64common_and_GPR64noipBits), .ID: AArch64::GPR64common_and_GPR64noipRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8216 { .RegsBegin: tcGPR64, .RegSet: tcGPR64Bits, .NameIdx: 1683, .RegsSize: 19, .RegSetSize: sizeof(tcGPR64Bits), .ID: AArch64::tcGPR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8217 { .RegsBegin: tcGPRnotx16, .RegSet: tcGPRnotx16Bits, .NameIdx: 6022, .RegsSize: 18, .RegSetSize: sizeof(tcGPRnotx16Bits), .ID: AArch64::tcGPRnotx16RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8218 { .RegsBegin: tcGPRnotx16x17, .RegSet: tcGPRnotx16x17Bits, .NameIdx: 6434, .RegsSize: 17, .RegSetSize: sizeof(tcGPRnotx16x17Bits), .ID: AArch64::tcGPRnotx16x17RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8219 { .RegsBegin: FPR64_lo, .RegSet: FPR64_loBits, .NameIdx: 14950, .RegsSize: 16, .RegSetSize: sizeof(FPR64_loBits), .ID: AArch64::FPR64_loRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8220 { .RegsBegin: GPR64arg, .RegSet: GPR64argBits, .NameIdx: 12510, .RegsSize: 8, .RegSetSize: sizeof(GPR64argBits), .ID: AArch64::GPR64argRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8221 { .RegsBegin: FIXED_REGS, .RegSet: FIXED_REGSBits, .NameIdx: 11082, .RegsSize: 4, .RegSetSize: sizeof(FIXED_REGSBits), .ID: AArch64::FIXED_REGSRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8222 { .RegsBegin: GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, .RegSet: GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, .NameIdx: 5520, .RegsSize: 4, .RegSetSize: sizeof(GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits), .ID: AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8223 { .RegsBegin: GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 83, .RegsSize: 4, .RegSetSize: sizeof(GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8224 { .RegsBegin: FIXED_REGS_with_sub_32, .RegSet: FIXED_REGS_with_sub_32Bits, .NameIdx: 660, .RegsSize: 2, .RegSetSize: sizeof(FIXED_REGS_with_sub_32Bits), .ID: AArch64::FIXED_REGS_with_sub_32RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8225 { .RegsBegin: tcGPRx16x17, .RegSet: tcGPRx16x17Bits, .NameIdx: 6228, .RegsSize: 2, .RegSetSize: sizeof(tcGPRx16x17Bits), .ID: AArch64::tcGPRx16x17RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8226 { .RegsBegin: FIXED_REGS_and_GPR64, .RegSet: FIXED_REGS_and_GPR64Bits, .NameIdx: 1633, .RegsSize: 1, .RegSetSize: sizeof(FIXED_REGS_and_GPR64Bits), .ID: AArch64::FIXED_REGS_and_GPR64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8227 { .RegsBegin: GPR64sponly, .RegSet: GPR64sponlyBits, .NameIdx: 19751, .RegsSize: 1, .RegSetSize: sizeof(GPR64sponlyBits), .ID: AArch64::GPR64sponlyRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8228 { .RegsBegin: tcGPRx17, .RegSet: tcGPRx17Bits, .NameIdx: 6626, .RegsSize: 1, .RegSetSize: sizeof(tcGPRx17Bits), .ID: AArch64::tcGPRx17RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8229 { .RegsBegin: DD, .RegSet: DDBits, .NameIdx: 8725, .RegsSize: 32, .RegSetSize: sizeof(DDBits), .ID: AArch64::DDRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8230 { .RegsBegin: DD_with_dsub0_in_FPR64_lo, .RegSet: DD_with_dsub0_in_FPR64_loBits, .NameIdx: 14933, .RegsSize: 16, .RegSetSize: sizeof(DD_with_dsub0_in_FPR64_loBits), .ID: AArch64::DD_with_dsub0_in_FPR64_loRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8231 { .RegsBegin: DD_with_dsub1_in_FPR64_lo, .RegSet: DD_with_dsub1_in_FPR64_loBits, .NameIdx: 15173, .RegsSize: 16, .RegSetSize: sizeof(DD_with_dsub1_in_FPR64_loBits), .ID: AArch64::DD_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8232 { .RegsBegin: XSeqPairsClass, .RegSet: XSeqPairsClassBits, .NameIdx: 19676, .RegsSize: 16, .RegSetSize: sizeof(XSeqPairsClassBits), .ID: AArch64::XSeqPairsClassRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8233 { .RegsBegin: DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo, .RegSet: DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits, .NameIdx: 15257, .RegsSize: 15, .RegSetSize: sizeof(DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits), .ID: AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8234 { .RegsBegin: XSeqPairsClass_with_subo64_in_GPR64common, .RegSet: XSeqPairsClass_with_subo64_in_GPR64commonBits, .NameIdx: 14209, .RegsSize: 15, .RegSetSize: sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), .ID: AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8235 { .RegsBegin: XSeqPairsClass_with_subo64_in_GPR64noip, .RegSet: XSeqPairsClass_with_subo64_in_GPR64noipBits, .NameIdx: 17354, .RegsSize: 15, .RegSetSize: sizeof(XSeqPairsClass_with_subo64_in_GPR64noipBits), .ID: AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8236 { .RegsBegin: XSeqPairsClass_with_sube64_in_GPR64noip, .RegSet: XSeqPairsClass_with_sube64_in_GPR64noipBits, .NameIdx: 17314, .RegsSize: 14, .RegSetSize: sizeof(XSeqPairsClass_with_sube64_in_GPR64noipBits), .ID: AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8237 { .RegsBegin: XSeqPairsClass_with_sube64_in_tcGPR64, .RegSet: XSeqPairsClass_with_sube64_in_tcGPR64Bits, .NameIdx: 1728, .RegsSize: 10, .RegSetSize: sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), .ID: AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8238 { .RegsBegin: XSeqPairsClass_with_sube64_in_tcGPRnotx16, .RegSet: XSeqPairsClass_with_sube64_in_tcGPRnotx16Bits, .NameIdx: 6075, .RegsSize: 9, .RegSetSize: sizeof(XSeqPairsClass_with_sube64_in_tcGPRnotx16Bits), .ID: AArch64::XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8239 { .RegsBegin: XSeqPairsClass_with_subo64_in_tcGPR64, .RegSet: XSeqPairsClass_with_subo64_in_tcGPR64Bits, .NameIdx: 1766, .RegsSize: 9, .RegSetSize: sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), .ID: AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8240 { .RegsBegin: XSeqPairsClass_with_subo64_in_tcGPRnotx16x17, .RegSet: XSeqPairsClass_with_subo64_in_tcGPRnotx16x17Bits, .NameIdx: 6493, .RegsSize: 8, .RegSetSize: sizeof(XSeqPairsClass_with_subo64_in_tcGPRnotx16x17Bits), .ID: AArch64::XSeqPairsClass_with_subo64_in_tcGPRnotx16x17RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8241 { .RegsBegin: XSeqPairsClass_with_sube64_in_GPR64arg, .RegSet: XSeqPairsClass_with_sube64_in_GPR64argBits, .NameIdx: 12519, .RegsSize: 4, .RegSetSize: sizeof(XSeqPairsClass_with_sube64_in_GPR64argBits), .ID: AArch64::XSeqPairsClass_with_sube64_in_GPR64argRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8242 { .RegsBegin: XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, .RegSet: XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, .NameIdx: 5564, .RegsSize: 2, .RegSetSize: sizeof(XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits), .ID: AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8243 { .RegsBegin: XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 239, .RegsSize: 2, .RegSetSize: sizeof(XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8244 { .RegsBegin: XSeqPairsClass_with_sube64_in_tcGPRx16x17, .RegSet: XSeqPairsClass_with_sube64_in_tcGPRx16x17Bits, .NameIdx: 6281, .RegsSize: 1, .RegSetSize: sizeof(XSeqPairsClass_with_sube64_in_tcGPRx16x17Bits), .ID: AArch64::XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8245 { .RegsBegin: XSeqPairsClass_with_subo64_in_FIXED_REGS, .RegSet: XSeqPairsClass_with_subo64_in_FIXED_REGSBits, .NameIdx: 11052, .RegsSize: 1, .RegSetSize: sizeof(XSeqPairsClass_with_subo64_in_FIXED_REGSBits), .ID: AArch64::XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8246 { .RegsBegin: FPR128, .RegSet: FPR128Bits, .NameIdx: 8621, .RegsSize: 32, .RegSetSize: sizeof(FPR128Bits), .ID: AArch64::FPR128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8247 { .RegsBegin: ZPR, .RegSet: ZPRBits, .NameIdx: 11044, .RegsSize: 32, .RegSetSize: sizeof(ZPRBits), .ID: AArch64::ZPRRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8248 { .RegsBegin: FPR128_lo, .RegSet: FPR128_loBits, .NameIdx: 16952, .RegsSize: 16, .RegSetSize: sizeof(FPR128_loBits), .ID: AArch64::FPR128_loRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8249 { .RegsBegin: MPR128, .RegSet: MPR128Bits, .NameIdx: 8628, .RegsSize: 16, .RegSetSize: sizeof(MPR128Bits), .ID: AArch64::MPR128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8250 { .RegsBegin: ZPRMul2, .RegSet: ZPRMul2Bits, .NameIdx: 912, .RegsSize: 16, .RegSetSize: sizeof(ZPRMul2Bits), .ID: AArch64::ZPRMul2RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8251 { .RegsBegin: ZPR_4b, .RegSet: ZPR_4bBits, .NameIdx: 12374, .RegsSize: 16, .RegSetSize: sizeof(ZPR_4bBits), .ID: AArch64::ZPR_4bRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8252 { .RegsBegin: FPR128_0to7, .RegSet: FPR128_0to7Bits, .NameIdx: 6654, .RegsSize: 8, .RegSetSize: sizeof(FPR128_0to7Bits), .ID: AArch64::FPR128_0to7RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8253 { .RegsBegin: ZPRMul2_Hi, .RegSet: ZPRMul2_HiBits, .NameIdx: 12798, .RegsSize: 8, .RegSetSize: sizeof(ZPRMul2_HiBits), .ID: AArch64::ZPRMul2_HiRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8254 { .RegsBegin: ZPRMul2_Lo, .RegSet: ZPRMul2_LoBits, .NameIdx: 14351, .RegsSize: 8, .RegSetSize: sizeof(ZPRMul2_LoBits), .ID: AArch64::ZPRMul2_LoRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8255 { .RegsBegin: ZPRMul4, .RegSet: ZPRMul4Bits, .NameIdx: 1865, .RegsSize: 8, .RegSetSize: sizeof(ZPRMul4Bits), .ID: AArch64::ZPRMul4RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8256 { .RegsBegin: ZPR_3b, .RegSet: ZPR_3bBits, .NameIdx: 11402, .RegsSize: 8, .RegSetSize: sizeof(ZPR_3bBits), .ID: AArch64::ZPR_3bRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8257 { .RegsBegin: ZPR_K, .RegSet: ZPR_KBits, .NameIdx: 8766, .RegsSize: 8, .RegSetSize: sizeof(ZPR_KBits), .ID: AArch64::ZPR_KRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8258 { .RegsBegin: ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 1850, .RegsSize: 4, .RegSetSize: sizeof(ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8259 { .RegsBegin: ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2679, .RegsSize: 4, .RegSetSize: sizeof(ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8260 { .RegsBegin: ZPRMul2_and_ZPR_3b, .RegSet: ZPRMul2_and_ZPR_3bBits, .NameIdx: 11390, .RegsSize: 4, .RegSetSize: sizeof(ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8261 { .RegsBegin: ZPRMul2_and_ZPR_K, .RegSet: ZPRMul2_and_ZPR_KBits, .NameIdx: 8754, .RegsSize: 4, .RegSetSize: sizeof(ZPRMul2_and_ZPR_KBits), .ID: AArch64::ZPRMul2_and_ZPR_KRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8262 { .RegsBegin: ZPRMul4_and_ZPR_3b, .RegSet: ZPRMul4_and_ZPR_3bBits, .NameIdx: 11771, .RegsSize: 2, .RegSetSize: sizeof(ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8263 { .RegsBegin: ZPRMul4_and_ZPR_K, .RegSet: ZPRMul4_and_ZPR_KBits, .NameIdx: 8987, .RegsSize: 2, .RegSetSize: sizeof(ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8264 { .RegsBegin: DDD, .RegSet: DDDBits, .NameIdx: 8724, .RegsSize: 32, .RegSetSize: sizeof(DDDBits), .ID: AArch64::DDDRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8265 { .RegsBegin: DDD_with_dsub0_in_FPR64_lo, .RegSet: DDD_with_dsub0_in_FPR64_loBits, .NameIdx: 14932, .RegsSize: 16, .RegSetSize: sizeof(DDD_with_dsub0_in_FPR64_loBits), .ID: AArch64::DDD_with_dsub0_in_FPR64_loRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8266 { .RegsBegin: DDD_with_dsub1_in_FPR64_lo, .RegSet: DDD_with_dsub1_in_FPR64_loBits, .NameIdx: 15172, .RegsSize: 16, .RegSetSize: sizeof(DDD_with_dsub1_in_FPR64_loBits), .ID: AArch64::DDD_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8267 { .RegsBegin: DDD_with_dsub2_in_FPR64_lo, .RegSet: DDD_with_dsub2_in_FPR64_loBits, .NameIdx: 15763, .RegsSize: 16, .RegSetSize: sizeof(DDD_with_dsub2_in_FPR64_loBits), .ID: AArch64::DDD_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8268 { .RegsBegin: DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo, .RegSet: DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits, .NameIdx: 15199, .RegsSize: 15, .RegSetSize: sizeof(DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits), .ID: AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8269 { .RegsBegin: DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo, .RegSet: DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits, .NameIdx: 15908, .RegsSize: 15, .RegSetSize: sizeof(DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits), .ID: AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8270 { .RegsBegin: DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo, .RegSet: DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits, .NameIdx: 15850, .RegsSize: 14, .RegSetSize: sizeof(DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits), .ID: AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 192, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8271 { .RegsBegin: DDDD, .RegSet: DDDDBits, .NameIdx: 8723, .RegsSize: 32, .RegSetSize: sizeof(DDDDBits), .ID: AArch64::DDDDRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8272 { .RegsBegin: DDDD_with_dsub0_in_FPR64_lo, .RegSet: DDDD_with_dsub0_in_FPR64_loBits, .NameIdx: 14931, .RegsSize: 16, .RegSetSize: sizeof(DDDD_with_dsub0_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8273 { .RegsBegin: DDDD_with_dsub1_in_FPR64_lo, .RegSet: DDDD_with_dsub1_in_FPR64_loBits, .NameIdx: 15171, .RegsSize: 16, .RegSetSize: sizeof(DDDD_with_dsub1_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8274 { .RegsBegin: DDDD_with_dsub2_in_FPR64_lo, .RegSet: DDDD_with_dsub2_in_FPR64_loBits, .NameIdx: 15762, .RegsSize: 16, .RegSetSize: sizeof(DDDD_with_dsub2_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8275 { .RegsBegin: DDDD_with_dsub3_in_FPR64_lo, .RegSet: DDDD_with_dsub3_in_FPR64_loBits, .NameIdx: 16416, .RegsSize: 16, .RegSetSize: sizeof(DDDD_with_dsub3_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8276 { .RegsBegin: DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo, .RegSet: DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits, .NameIdx: 15139, .RegsSize: 15, .RegSetSize: sizeof(DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8277 { .RegsBegin: DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo, .RegSet: DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits, .NameIdx: 15790, .RegsSize: 15, .RegSetSize: sizeof(DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8278 { .RegsBegin: DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, .RegSet: DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, .NameIdx: 16504, .RegsSize: 15, .RegSetSize: sizeof(DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8279 { .RegsBegin: DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo, .RegSet: DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits, .NameIdx: 15730, .RegsSize: 14, .RegSetSize: sizeof(DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8280 { .RegsBegin: DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, .RegSet: DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, .NameIdx: 16444, .RegsSize: 14, .RegSetSize: sizeof(DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8281 { .RegsBegin: DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, .RegSet: DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, .NameIdx: 16384, .RegsSize: 13, .RegSetSize: sizeof(DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits), .ID: AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8282 { .RegsBegin: QQ, .RegSet: QQBits, .NameIdx: 11020, .RegsSize: 32, .RegSetSize: sizeof(QQBits), .ID: AArch64::QQRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8283 { .RegsBegin: ZPR2, .RegSet: ZPR2Bits, .NameIdx: 688, .RegsSize: 32, .RegSetSize: sizeof(ZPR2Bits), .ID: AArch64::ZPR2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8284 { .RegsBegin: ZPR2StridedOrContiguous, .RegSet: ZPR2StridedOrContiguousBits, .NameIdx: 19691, .RegsSize: 32, .RegSetSize: sizeof(ZPR2StridedOrContiguousBits), .ID: AArch64::ZPR2StridedOrContiguousRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8285 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2Bits, .NameIdx: 954, .RegsSize: 24, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2Bits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8286 { .RegsBegin: QQ_with_dsub1_in_FPR64_lo, .RegSet: QQ_with_dsub1_in_FPR64_loBits, .NameIdx: 15348, .RegsSize: 16, .RegSetSize: sizeof(QQ_with_dsub1_in_FPR64_loBits), .ID: AArch64::QQ_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8287 { .RegsBegin: QQ_with_qsub0_in_FPR128_lo, .RegSet: QQ_with_qsub0_in_FPR128_loBits, .NameIdx: 16935, .RegsSize: 16, .RegSetSize: sizeof(QQ_with_qsub0_in_FPR128_loBits), .ID: AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8288 { .RegsBegin: ZPR2Mul2, .RegSet: ZPR2Mul2Bits, .NameIdx: 727, .RegsSize: 16, .RegSetSize: sizeof(ZPR2Mul2Bits), .ID: AArch64::ZPR2Mul2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8289 { .RegsBegin: ZPR2Strided, .RegSet: ZPR2StridedBits, .NameIdx: 12381, .RegsSize: 16, .RegSetSize: sizeof(ZPR2StridedBits), .ID: AArch64::ZPR2StridedRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8290 { .RegsBegin: ZPR2StridedOrContiguous_with_dsub_in_FPR64_lo, .RegSet: ZPR2StridedOrContiguous_with_dsub_in_FPR64_loBits, .NameIdx: 16813, .RegsSize: 16, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_dsub_in_FPR64_loBits), .ID: AArch64::ZPR2StridedOrContiguous_with_dsub_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8291 { .RegsBegin: ZPR2_with_dsub1_in_FPR64_lo, .RegSet: ZPR2_with_dsub1_in_FPR64_loBits, .NameIdx: 14991, .RegsSize: 16, .RegSetSize: sizeof(ZPR2_with_dsub1_in_FPR64_loBits), .ID: AArch64::ZPR2_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8292 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul2, .RegSet: ZPR2_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1080, .RegsSize: 16, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8293 { .RegsBegin: ZPR2_with_zsub_in_FPR128_lo, .RegSet: ZPR2_with_zsub_in_FPR128_loBits, .NameIdx: 16962, .RegsSize: 16, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_loBits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8294 { .RegsBegin: QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_lo, .RegSet: QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loBits, .NameIdx: 15433, .RegsSize: 15, .RegSetSize: sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loBits), .ID: AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8295 { .RegsBegin: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_lo, .RegSet: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_loBits, .NameIdx: 14959, .RegsSize: 15, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_loBits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8296 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_HiBits, .NameIdx: 12846, .RegsSize: 12, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_HiBits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8297 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_LoBits, .NameIdx: 14399, .RegsSize: 12, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_LoBits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8298 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4Bits, .NameIdx: 4148, .RegsSize: 12, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8299 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7, .RegSet: ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8523, .RegsSize: 12, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8300 { .RegsBegin: QQ_with_qsub0_in_FPR128_0to7, .RegSet: QQ_with_qsub0_in_FPR128_0to7Bits, .NameIdx: 6637, .RegsSize: 8, .RegSetSize: sizeof(QQ_with_qsub0_in_FPR128_0to7Bits), .ID: AArch64::QQ_with_qsub0_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8301 { .RegsBegin: QQ_with_qsub1_in_FPR128_0to7, .RegSet: QQ_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6898, .RegsSize: 8, .RegSetSize: sizeof(QQ_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::QQ_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8302 { .RegsBegin: ZPR2Mul2_Hi, .RegSet: ZPR2Mul2_HiBits, .NameIdx: 12691, .RegsSize: 8, .RegSetSize: sizeof(ZPR2Mul2_HiBits), .ID: AArch64::ZPR2Mul2_HiRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8303 { .RegsBegin: ZPR2Mul2_Lo, .RegSet: ZPR2Mul2_LoBits, .NameIdx: 14276, .RegsSize: 8, .RegSetSize: sizeof(ZPR2Mul2_LoBits), .ID: AArch64::ZPR2Mul2_LoRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8304 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11352, .RegsSize: 8, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8305 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPR_K, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPR_KBits, .NameIdx: 10211, .RegsSize: 8, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8306 { .RegsBegin: ZPR2Strided_with_dsub_in_FPR64_lo, .RegSet: ZPR2Strided_with_dsub_in_FPR64_loBits, .NameIdx: 16745, .RegsSize: 8, .RegSetSize: sizeof(ZPR2Strided_with_dsub_in_FPR64_loBits), .ID: AArch64::ZPR2Strided_with_dsub_in_FPR64_loRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8307 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul2, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul2Bits, .NameIdx: 886, .RegsSize: 8, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul2Bits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8308 { .RegsBegin: ZPR2_with_qsub1_in_FPR128_0to7, .RegSet: ZPR2_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6700, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::ZPR2_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8309 { .RegsBegin: ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3136, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8310 { .RegsBegin: ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9402, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8311 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR2_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13087, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8312 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul2_Lo, .RegSet: ZPR2_with_zsub1_in_ZPRMul2_LoBits, .NameIdx: 14529, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul2_LoBits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8313 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul4, .RegSet: ZPR2_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4274, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8314 { .RegsBegin: ZPR2_with_zsub1_in_ZPR_K, .RegSet: ZPR2_with_zsub1_in_ZPR_KBits, .NameIdx: 10284, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR2_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8315 { .RegsBegin: ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 7984, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8316 { .RegsBegin: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2, .RegSet: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1211, .RegsSize: 8, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8317 { .RegsBegin: QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7, .RegSet: QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6991, .RegsSize: 7, .RegSetSize: sizeof(QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8318 { .RegsBegin: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7, .RegSet: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6666, .RegsSize: 7, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8319 { .RegsBegin: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo, .RegSet: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_LoBits, .NameIdx: 14497, .RegsSize: 7, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_LoBits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8320 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 1922, .RegsSize: 6, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8321 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2751, .RegsSize: 6, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8322 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_K, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_KBits, .NameIdx: 8772, .RegsSize: 6, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_KBits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8323 { .RegsBegin: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_K, .RegSet: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_KBits, .NameIdx: 10255, .RegsSize: 6, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8324 { .RegsBegin: ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3120, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8325 { .RegsBegin: ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3580, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8326 { .RegsBegin: ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9389, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8327 { .RegsBegin: ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 7971, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8328 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 11828, .RegsSize: 4, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8329 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul2_Hi, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul2_HiBits, .NameIdx: 12772, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul2_HiBits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8330 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul2_Lo, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul2_LoBits, .NameIdx: 14325, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul2_LoBits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8331 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul4, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul4Bits, .NameIdx: 4080, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8332 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPR_K, .RegSet: ZPR2Strided_with_zsub0_in_ZPR_KBits, .NameIdx: 10179, .RegsSize: 4, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8333 { .RegsBegin: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2, .RegSet: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1155, .RegsSize: 4, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8334 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2187, .RegsSize: 4, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8335 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2905, .RegsSize: 4, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8336 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11500, .RegsSize: 4, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8337 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K, .RegSet: ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KBits, .NameIdx: 8857, .RegsSize: 4, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KBits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8338 { .RegsBegin: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2, .RegSet: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1046, .RegsSize: 4, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8339 { .RegsBegin: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4, .RegSet: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4471, .RegsSize: 4, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8340 { .RegsBegin: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9086, .RegsSize: 3, .RegSetSize: sizeof(ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR2StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8341 { .RegsBegin: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13058, .RegsSize: 3, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8342 { .RegsBegin: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11466, .RegsSize: 3, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8343 { .RegsBegin: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2873, .RegsSize: 3, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8344 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 1824, .RegsSize: 2, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8345 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2653, .RegsSize: 2, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8346 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_K, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_KBits, .NameIdx: 8728, .RegsSize: 2, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_KBits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul2_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8347 { .RegsBegin: ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 11752, .RegsSize: 2, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8348 { .RegsBegin: ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 8968, .RegsSize: 2, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR2_with_zsub0_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8349 { .RegsBegin: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_K, .RegSet: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KBits, .NameIdx: 8828, .RegsSize: 2, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KBits), .ID: AArch64::ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8350 { .RegsBegin: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4, .RegSet: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4415, .RegsSize: 2, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8351 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 11976, .RegsSize: 2, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8352 { .RegsBegin: ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9142, .RegsSize: 2, .RegSetSize: sizeof(ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8353 { .RegsBegin: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4, .RegSet: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4240, .RegsSize: 2, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8354 { .RegsBegin: ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9042, .RegsSize: 1, .RegSetSize: sizeof(ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR2Strided_with_zsub0_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8355 { .RegsBegin: ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9799, .RegsSize: 1, .RegSetSize: sizeof(ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR2_with_dsub1_in_FPR64_lo_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8356 { .RegsBegin: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2158, .RegsSize: 1, .RegSetSize: sizeof(ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8357 { .RegsBegin: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 11942, .RegsSize: 1, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_0to7_and_ZPR2_with_zsub1_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8358 { .RegsBegin: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13283, .RegsSize: 1, .RegSetSize: sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8359 { .RegsBegin: MPR64, .RegSet: MPR64Bits, .NameIdx: 1804, .RegsSize: 8, .RegSetSize: sizeof(MPR64Bits), .ID: AArch64::MPR64RegClassID, .RegSizeInBits: 256, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8360 { .RegsBegin: QQQ, .RegSet: QQQBits, .NameIdx: 11019, .RegsSize: 32, .RegSetSize: sizeof(QQQBits), .ID: AArch64::QQQRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8361 { .RegsBegin: ZPR3, .RegSet: ZPR3Bits, .NameIdx: 1622, .RegsSize: 32, .RegSetSize: sizeof(ZPR3Bits), .ID: AArch64::ZPR3RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8362 { .RegsBegin: QQQ_with_dsub1_in_FPR64_lo, .RegSet: QQQ_with_dsub1_in_FPR64_loBits, .NameIdx: 15347, .RegsSize: 16, .RegSetSize: sizeof(QQQ_with_dsub1_in_FPR64_loBits), .ID: AArch64::QQQ_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8363 { .RegsBegin: QQQ_with_dsub2_in_FPR64_lo, .RegSet: QQQ_with_dsub2_in_FPR64_loBits, .NameIdx: 15999, .RegsSize: 16, .RegSetSize: sizeof(QQQ_with_dsub2_in_FPR64_loBits), .ID: AArch64::QQQ_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8364 { .RegsBegin: QQQ_with_qsub0_in_FPR128_lo, .RegSet: QQQ_with_qsub0_in_FPR128_loBits, .NameIdx: 16934, .RegsSize: 16, .RegSetSize: sizeof(QQQ_with_qsub0_in_FPR128_loBits), .ID: AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8365 { .RegsBegin: ZPR3_with_dsub1_in_FPR64_lo, .RegSet: ZPR3_with_dsub1_in_FPR64_loBits, .NameIdx: 15051, .RegsSize: 16, .RegSetSize: sizeof(ZPR3_with_dsub1_in_FPR64_loBits), .ID: AArch64::ZPR3_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8366 { .RegsBegin: ZPR3_with_dsub2_in_FPR64_lo, .RegSet: ZPR3_with_dsub2_in_FPR64_loBits, .NameIdx: 15522, .RegsSize: 16, .RegSetSize: sizeof(ZPR3_with_dsub2_in_FPR64_loBits), .ID: AArch64::ZPR3_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8367 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2Bits, .NameIdx: 702, .RegsSize: 16, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8368 { .RegsBegin: ZPR3_with_zsub1_in_ZPRMul2, .RegSet: ZPR3_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1304, .RegsSize: 16, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR3_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8369 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo, .RegSet: ZPR3_with_zsub_in_FPR128_loBits, .NameIdx: 16990, .RegsSize: 16, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_loBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8370 { .RegsBegin: QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_lo, .RegSet: QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loBits, .NameIdx: 16087, .RegsSize: 15, .RegSetSize: sizeof(QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loBits), .ID: AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8371 { .RegsBegin: QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_lo, .RegSet: QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loBits, .NameIdx: 15374, .RegsSize: 15, .RegSetSize: sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loBits), .ID: AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8372 { .RegsBegin: ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_lo, .RegSet: ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_loBits, .NameIdx: 15490, .RegsSize: 15, .RegSetSize: sizeof(ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_loBits), .ID: AArch64::ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8373 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_lo, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_loBits, .NameIdx: 15019, .RegsSize: 15, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_loBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8374 { .RegsBegin: QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_lo, .RegSet: QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loBits, .NameIdx: 16145, .RegsSize: 14, .RegSetSize: sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loBits), .ID: AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8375 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_lo, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_loBits, .NameIdx: 15550, .RegsSize: 14, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_loBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8376 { .RegsBegin: QQQ_with_qsub0_in_FPR128_0to7, .RegSet: QQQ_with_qsub0_in_FPR128_0to7Bits, .NameIdx: 6636, .RegsSize: 8, .RegSetSize: sizeof(QQQ_with_qsub0_in_FPR128_0to7Bits), .ID: AArch64::QQQ_with_qsub0_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8377 { .RegsBegin: QQQ_with_qsub1_in_FPR128_0to7, .RegSet: QQQ_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6897, .RegsSize: 8, .RegSetSize: sizeof(QQQ_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::QQQ_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8378 { .RegsBegin: QQQ_with_qsub2_in_FPR128_0to7, .RegSet: QQQ_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7345, .RegsSize: 8, .RegSetSize: sizeof(QQQ_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::QQQ_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8379 { .RegsBegin: ZPR3_with_qsub1_in_FPR128_0to7, .RegSet: ZPR3_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6765, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8380 { .RegsBegin: ZPR3_with_qsub2_in_FPR128_0to7, .RegSet: ZPR3_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7087, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8381 { .RegsBegin: ZPR3_with_zsub0_in_ZPRMul4, .RegSet: ZPR3_with_zsub0_in_ZPRMul4Bits, .NameIdx: 4053, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8382 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K, .RegSet: ZPR3_with_zsub0_in_ZPR_KBits, .NameIdx: 9888, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8383 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiBits, .NameIdx: 12666, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiBits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8384 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_LoBits, .NameIdx: 14251, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_LoBits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_LoRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8385 { .RegsBegin: ZPR3_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR3_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13374, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR3_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8386 { .RegsBegin: ZPR3_with_zsub1_in_ZPRMul2_Lo, .RegSet: ZPR3_with_zsub1_in_ZPRMul2_LoBits, .NameIdx: 14591, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPRMul2_LoBits), .ID: AArch64::ZPR3_with_zsub1_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8387 { .RegsBegin: ZPR3_with_zsub1_in_ZPRMul4, .RegSet: ZPR3_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4564, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8388 { .RegsBegin: ZPR3_with_zsub1_in_ZPR_K, .RegSet: ZPR3_with_zsub1_in_ZPR_KBits, .NameIdx: 10338, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8389 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul2_Hi, .RegSet: ZPR3_with_zsub2_in_ZPRMul2_HiBits, .NameIdx: 13750, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul2_HiBits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8390 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul2_Lo, .RegSet: ZPR3_with_zsub2_in_ZPRMul2_LoBits, .NameIdx: 14715, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul2_LoBits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8391 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul4, .RegSet: ZPR3_with_zsub2_in_ZPRMul4Bits, .NameIdx: 4916, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8392 { .RegsBegin: ZPR3_with_zsub2_in_ZPR_K, .RegSet: ZPR3_with_zsub2_in_ZPR_KBits, .NameIdx: 10723, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub2_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8393 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7, .RegSet: ZPR3_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8450, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8394 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1387, .RegsSize: 8, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8395 { .RegsBegin: QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7, .RegSet: QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7502, .RegsSize: 7, .RegSetSize: sizeof(QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8396 { .RegsBegin: QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7, .RegSet: QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6927, .RegsSize: 7, .RegSetSize: sizeof(QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8397 { .RegsBegin: ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7, .RegSet: ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7118, .RegsSize: 7, .RegSetSize: sizeof(ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8398 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits, .NameIdx: 13709, .RegsSize: 7, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8399 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6731, .RegsSize: 7, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8400 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Lo, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_LoBits, .NameIdx: 14559, .RegsSize: 7, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_LoBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8401 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_LoBits, .NameIdx: 14683, .RegsSize: 7, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_LoBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8402 { .RegsBegin: QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7, .RegSet: QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7438, .RegsSize: 6, .RegSetSize: sizeof(QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8403 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_K, .RegSet: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_KBits, .NameIdx: 10309, .RegsSize: 6, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8404 { .RegsBegin: ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K, .RegSet: ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KBits, .NameIdx: 10748, .RegsSize: 6, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub1_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8405 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7053, .RegsSize: 6, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8406 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2, .RegSet: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1331, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8407 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_K, .RegSet: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KBits, .NameIdx: 10694, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub2_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8408 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3095, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8409 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits, .NameIdx: 5003, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8410 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3555, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8411 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9364, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8412 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 7946, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8413 { .RegsBegin: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3260, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8414 { .RegsBegin: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3723, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8415 { .RegsBegin: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9519, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8416 { .RegsBegin: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8116, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8417 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2330, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8418 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2979, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8419 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11572, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8420 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_K, .RegSet: ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_KBits, .NameIdx: 8894, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8421 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1270, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8422 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4647, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8423 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4Bits, .NameIdx: 5192, .RegsSize: 4, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8424 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13345, .RegsSize: 3, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8425 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2289, .RegsSize: 3, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8426 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13004, .RegsSize: 3, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8427 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8082, .RegsSize: 3, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8428 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11538, .RegsSize: 3, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8429 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3691, .RegsSize: 3, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8430 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2947, .RegsSize: 3, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8431 { .RegsBegin: ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K, .RegSet: ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KBits, .NameIdx: 9913, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8432 { .RegsBegin: ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 11790, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8433 { .RegsBegin: ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9005, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub0_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8434 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4, .RegSet: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4591, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8435 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9490, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8436 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4361, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8437 { .RegsBegin: ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12048, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8438 { .RegsBegin: ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9179, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8439 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12192, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8440 { .RegsBegin: ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9253, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8441 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4530, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8442 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4Bits, .NameIdx: 4882, .RegsSize: 2, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8443 { .RegsBegin: ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_K, .RegSet: ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KBits, .NameIdx: 9856, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR3_with_dsub1_in_FPR64_lo_and_ZPR3_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8444 { .RegsBegin: ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi, .RegSet: ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiBits, .NameIdx: 12634, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiBits), .ID: AArch64::ZPR3_with_dsub2_in_FPR64_lo_and_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8445 { .RegsBegin: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3231, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_in_ZPR_K_and_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8446 { .RegsBegin: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2104, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8447 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12014, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub1_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8448 { .RegsBegin: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12158, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_0to7_and_ZPR3_with_zsub2_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8449 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13404, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8450 { .RegsBegin: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_Hi, .RegSet: ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits, .NameIdx: 13904, .RegsSize: 1, .RegSetSize: sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits), .ID: AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 384, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8451 { .RegsBegin: QQQQ, .RegSet: QQQQBits, .NameIdx: 11018, .RegsSize: 32, .RegSetSize: sizeof(QQQQBits), .ID: AArch64::QQQQRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8452 { .RegsBegin: ZPR4, .RegSet: ZPR4Bits, .NameIdx: 1810, .RegsSize: 32, .RegSetSize: sizeof(ZPR4Bits), .ID: AArch64::ZPR4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8453 { .RegsBegin: QQQQ_with_dsub1_in_FPR64_lo, .RegSet: QQQQ_with_dsub1_in_FPR64_loBits, .NameIdx: 15346, .RegsSize: 16, .RegSetSize: sizeof(QQQQ_with_dsub1_in_FPR64_loBits), .ID: AArch64::QQQQ_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8454 { .RegsBegin: QQQQ_with_dsub2_in_FPR64_lo, .RegSet: QQQQ_with_dsub2_in_FPR64_loBits, .NameIdx: 15998, .RegsSize: 16, .RegSetSize: sizeof(QQQQ_with_dsub2_in_FPR64_loBits), .ID: AArch64::QQQQ_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8455 { .RegsBegin: QQQQ_with_dsub3_in_FPR64_lo, .RegSet: QQQQ_with_dsub3_in_FPR64_loBits, .NameIdx: 16596, .RegsSize: 16, .RegSetSize: sizeof(QQQQ_with_dsub3_in_FPR64_loBits), .ID: AArch64::QQQQ_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8456 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_lo, .RegSet: QQQQ_with_qsub0_in_FPR128_loBits, .NameIdx: 16933, .RegsSize: 16, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_loBits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8457 { .RegsBegin: ZPR4StridedOrContiguous, .RegSet: ZPR4StridedOrContiguousBits, .NameIdx: 19715, .RegsSize: 16, .RegSetSize: sizeof(ZPR4StridedOrContiguousBits), .ID: AArch64::ZPR4StridedOrContiguousRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8458 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo, .RegSet: ZPR4_with_dsub1_in_FPR64_loBits, .NameIdx: 15111, .RegsSize: 16, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_loBits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8459 { .RegsBegin: ZPR4_with_dsub2_in_FPR64_lo, .RegSet: ZPR4_with_dsub2_in_FPR64_loBits, .NameIdx: 15642, .RegsSize: 16, .RegSetSize: sizeof(ZPR4_with_dsub2_in_FPR64_loBits), .ID: AArch64::ZPR4_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8460 { .RegsBegin: ZPR4_with_dsub3_in_FPR64_lo, .RegSet: ZPR4_with_dsub3_in_FPR64_loBits, .NameIdx: 16236, .RegsSize: 16, .RegSetSize: sizeof(ZPR4_with_dsub3_in_FPR64_loBits), .ID: AArch64::ZPR4_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8461 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2Bits, .NameIdx: 736, .RegsSize: 16, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8462 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul2, .RegSet: ZPR4_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1480, .RegsSize: 16, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8463 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo, .RegSet: ZPR4_with_zsub_in_FPR128_loBits, .NameIdx: 17018, .RegsSize: 16, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_loBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8464 { .RegsBegin: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_lo, .RegSet: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loBits, .NameIdx: 15966, .RegsSize: 15, .RegSetSize: sizeof(QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loBits), .ID: AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8465 { .RegsBegin: QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo, .RegSet: QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loBits, .NameIdx: 16624, .RegsSize: 15, .RegSetSize: sizeof(QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loBits), .ID: AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8466 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_lo, .RegSet: QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loBits, .NameIdx: 15313, .RegsSize: 15, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loBits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8467 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_lo, .RegSet: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_loBits, .NameIdx: 15610, .RegsSize: 15, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_loBits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8468 { .RegsBegin: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo, .RegSet: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loBits, .NameIdx: 16264, .RegsSize: 15, .RegSetSize: sizeof(ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loBits), .ID: AArch64::ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8469 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_lo, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_loBits, .NameIdx: 15079, .RegsSize: 15, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_loBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub1_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8470 { .RegsBegin: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_lo, .RegSet: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loBits, .NameIdx: 16564, .RegsSize: 14, .RegSetSize: sizeof(QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loBits), .ID: AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8471 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_lo, .RegSet: QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loBits, .NameIdx: 16026, .RegsSize: 14, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loBits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8472 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_lo, .RegSet: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loBits, .NameIdx: 16204, .RegsSize: 14, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loBits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8473 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_lo, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_loBits, .NameIdx: 15670, .RegsSize: 14, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_loBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub2_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8474 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_lo, .RegSet: QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loBits, .NameIdx: 16684, .RegsSize: 13, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loBits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8475 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_lo, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_loBits, .NameIdx: 16324, .RegsSize: 13, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_loBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_dsub3_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8476 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2Bits, .NameIdx: 1000, .RegsSize: 12, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2Bits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8477 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4Bits, .NameIdx: 4194, .RegsSize: 10, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8478 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_0to7, .RegSet: QQQQ_with_qsub0_in_FPR128_0to7Bits, .NameIdx: 6635, .RegsSize: 8, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8479 { .RegsBegin: QQQQ_with_qsub1_in_FPR128_0to7, .RegSet: QQQQ_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6896, .RegsSize: 8, .RegSetSize: sizeof(QQQQ_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8480 { .RegsBegin: QQQQ_with_qsub2_in_FPR128_0to7, .RegSet: QQQQ_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7344, .RegsSize: 8, .RegSetSize: sizeof(QQQQ_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8481 { .RegsBegin: QQQQ_with_qsub3_in_FPR128_0to7, .RegSet: QQQQ_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7789, .RegsSize: 8, .RegSetSize: sizeof(QQQQ_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8482 { .RegsBegin: ZPR4Mul4, .RegSet: ZPR4Mul4Bits, .NameIdx: 1815, .RegsSize: 8, .RegSetSize: sizeof(ZPR4Mul4Bits), .ID: AArch64::ZPR4Mul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8483 { .RegsBegin: ZPR4Strided, .RegSet: ZPR4StridedBits, .NameIdx: 12393, .RegsSize: 8, .RegSetSize: sizeof(ZPR4StridedBits), .ID: AArch64::ZPR4StridedRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8484 { .RegsBegin: ZPR4StridedOrContiguous_with_dsub_in_FPR64_lo, .RegSet: ZPR4StridedOrContiguous_with_dsub_in_FPR64_loBits, .NameIdx: 16859, .RegsSize: 8, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_dsub_in_FPR64_loBits), .ID: AArch64::ZPR4StridedOrContiguous_with_dsub_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8485 { .RegsBegin: ZPR4_with_qsub1_in_FPR128_0to7, .RegSet: ZPR4_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6830, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8486 { .RegsBegin: ZPR4_with_qsub2_in_FPR128_0to7, .RegSet: ZPR4_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7215, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8487 { .RegsBegin: ZPR4_with_qsub3_in_FPR128_0to7, .RegSet: ZPR4_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7597, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8488 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_zsub0_in_ZPR_KBits, .NameIdx: 9983, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8489 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiBits, .NameIdx: 12735, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiBits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8490 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_LoBits, .NameIdx: 14288, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_LoBits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8491 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13495, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8492 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul2_Lo, .RegSet: ZPR4_with_zsub1_in_ZPRMul2_LoBits, .NameIdx: 14653, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8493 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul4, .RegSet: ZPR4_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4740, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8494 { .RegsBegin: ZPR4_with_zsub1_in_ZPR_K, .RegSet: ZPR4_with_zsub1_in_ZPR_KBits, .NameIdx: 10392, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8495 { .RegsBegin: ZPR4_with_zsub2_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub2_in_ZPRMul2_HiBits, .NameIdx: 13998, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub2_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub2_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8496 { .RegsBegin: ZPR4_with_zsub2_in_ZPRMul2_Lo, .RegSet: ZPR4_with_zsub2_in_ZPRMul2_LoBits, .NameIdx: 14777, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub2_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4_with_zsub2_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8497 { .RegsBegin: ZPR4_with_zsub2_in_ZPRMul4, .RegSet: ZPR4_with_zsub2_in_ZPRMul4Bits, .NameIdx: 5285, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8498 { .RegsBegin: ZPR4_with_zsub2_in_ZPR_K, .RegSet: ZPR4_with_zsub2_in_ZPR_KBits, .NameIdx: 10831, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub2_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub2_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8499 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub3_in_ZPRMul2_HiBits, .NameIdx: 14057, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8500 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul2_Lo, .RegSet: ZPR4_with_zsub3_in_ZPRMul2_LoBits, .NameIdx: 14839, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8501 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul4, .RegSet: ZPR4_with_zsub3_in_ZPRMul4Bits, .NameIdx: 5405, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8502 { .RegsBegin: ZPR4_with_zsub3_in_ZPR_K, .RegSet: ZPR4_with_zsub3_in_ZPR_KBits, .NameIdx: 10939, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub3_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8503 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7, .RegSet: ZPR4_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8493, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8504 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1563, .RegsSize: 8, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8505 { .RegsBegin: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7, .RegSet: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7375, .RegsSize: 7, .RegSetSize: sizeof(QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8506 { .RegsBegin: QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7, .RegSet: QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7883, .RegsSize: 7, .RegSetSize: sizeof(QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8507 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7, .RegSet: QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6861, .RegsSize: 7, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8508 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7, .RegSet: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7246, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8509 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo, .RegSet: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoBits, .NameIdx: 14807, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8510 { .RegsBegin: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7, .RegSet: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7691, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8511 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits, .NameIdx: 13649, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8512 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits, .NameIdx: 13780, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8513 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7Bits, .NameIdx: 6796, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub1_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8514 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Lo, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_LoBits, .NameIdx: 14621, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8515 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Lo, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_LoBits, .NameIdx: 14745, .RegsSize: 7, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8516 { .RegsBegin: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7, .RegSet: QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7820, .RegsSize: 6, .RegSetSize: sizeof(QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8517 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7, .RegSet: QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7309, .RegsSize: 6, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8518 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_HiBits, .NameIdx: 12895, .RegsSize: 6, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8519 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_LoBits, .NameIdx: 14448, .RegsSize: 6, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8520 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K, .RegSet: ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits, .NameIdx: 10556, .RegsSize: 6, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8521 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7, .RegSet: ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8572, .RegsSize: 6, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8522 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7, .RegSet: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7628, .RegsSize: 6, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8523 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_K, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_KBits, .NameIdx: 10363, .RegsSize: 6, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8524 { .RegsBegin: ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K, .RegSet: ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KBits, .NameIdx: 10856, .RegsSize: 6, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8525 { .RegsBegin: ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K, .RegSet: ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KBits, .NameIdx: 10964, .RegsSize: 6, .RegSetSize: sizeof(ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub2_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8526 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7Bits, .NameIdx: 7181, .RegsSize: 6, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub2_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8527 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoBits, .NameIdx: 14869, .RegsSize: 6, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8528 { .RegsBegin: QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7, .RegSet: QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7754, .RegsSize: 5, .RegSetSize: sizeof(QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8529 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 1983, .RegsSize: 5, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8530 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2812, .RegsSize: 5, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8531 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7Bits, .NameIdx: 7563, .RegsSize: 5, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_qsub3_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8532 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits, .NameIdx: 10506, .RegsSize: 4, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8533 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11409, .RegsSize: 4, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8534 { .RegsBegin: ZPR4Strided_with_dsub_in_FPR64_lo, .RegSet: ZPR4Strided_with_dsub_in_FPR64_loBits, .NameIdx: 16779, .RegsSize: 4, .RegSetSize: sizeof(ZPR4Strided_with_dsub_in_FPR64_loBits), .ID: AArch64::ZPR4Strided_with_dsub_in_FPR64_loRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8535 { .RegsBegin: ZPR4Strided_with_zsub0_in_ZPRMul2, .RegSet: ZPR4Strided_with_zsub0_in_ZPRMul2Bits, .NameIdx: 920, .RegsSize: 4, .RegSetSize: sizeof(ZPR4Strided_with_zsub0_in_ZPRMul2Bits), .ID: AArch64::ZPR4Strided_with_zsub0_in_ZPRMul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8536 { .RegsBegin: ZPR4Strided_with_zsub1_in_ZPR_K, .RegSet: ZPR4Strided_with_zsub1_in_ZPR_KBits, .NameIdx: 10474, .RegsSize: 4, .RegSetSize: sizeof(ZPR4Strided_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR4Strided_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8537 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1507, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8538 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_K, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KBits, .NameIdx: 10802, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub2_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8539 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3163, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8540 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3623, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8541 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9427, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8542 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8014, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8543 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits, .NameIdx: 4943, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8544 { .RegsBegin: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3357, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8545 { .RegsBegin: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3823, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8546 { .RegsBegin: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9611, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8547 { .RegsBegin: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8218, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8548 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4, .RegSet: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits, .NameIdx: 5071, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8549 { .RegsBegin: ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_K, .RegSet: ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KBits, .NameIdx: 10910, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8550 { .RegsBegin: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3456, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8551 { .RegsBegin: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3954, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8552 { .RegsBegin: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9705, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8553 { .RegsBegin: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8351, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8554 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2537, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8555 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 3053, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8556 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11644, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8557 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_K, .RegSet: ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_KBits, .NameIdx: 8931, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8558 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1446, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8559 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4823, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8560 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4Bits, .NameIdx: 5312, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8561 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4Bits, .NameIdx: 5432, .RegsSize: 4, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8562 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_K, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits, .NameIdx: 10600, .RegsSize: 3, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR4StridedOrContiguous_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8563 { .RegsBegin: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 11885, .RegsSize: 3, .RegSetSize: sizeof(ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR4StridedOrContiguous_with_zsub0_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8564 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11682, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8565 { .RegsBegin: ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits, .NameIdx: 10122, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8566 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13466, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8567 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2229, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8568 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 12944, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8569 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2372, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_Hi_and_ZPR3_with_zsub2_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8570 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13117, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul2_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8571 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8184, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8572 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8317, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8573 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3791, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8574 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3922, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_zsub2_zsub3_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Lo_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8575 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 3021, .RegsSize: 3, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8576 { .RegsBegin: ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_K, .RegSet: ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_KBits, .NameIdx: 9970, .RegsSize: 2, .RegSetSize: sizeof(ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4Mul4_and_ZPR4_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8577 { .RegsBegin: ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7, .RegSet: ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7Bits, .NameIdx: 8480, .RegsSize: 2, .RegSetSize: sizeof(ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7Bits), .ID: AArch64::ZPR4Mul4_and_ZPR4_with_zsub_in_FPR128_0to7RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8578 { .RegsBegin: ZPR4Strided_with_zsub0_in_ZPRMul2_Hi, .RegSet: ZPR4Strided_with_zsub0_in_ZPRMul2_HiBits, .NameIdx: 12809, .RegsSize: 2, .RegSetSize: sizeof(ZPR4Strided_with_zsub0_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4Strided_with_zsub0_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8579 { .RegsBegin: ZPR4Strided_with_zsub0_in_ZPRMul2_Lo, .RegSet: ZPR4Strided_with_zsub0_in_ZPRMul2_LoBits, .NameIdx: 14362, .RegsSize: 2, .RegSetSize: sizeof(ZPR4Strided_with_zsub0_in_ZPRMul2_LoBits), .ID: AArch64::ZPR4Strided_with_zsub0_in_ZPRMul2_LoRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8580 { .RegsBegin: ZPR4Strided_with_zsub0_in_ZPRMul4, .RegSet: ZPR4Strided_with_zsub0_in_ZPRMul4Bits, .NameIdx: 4114, .RegsSize: 2, .RegSetSize: sizeof(ZPR4Strided_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4Strided_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8581 { .RegsBegin: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits, .NameIdx: 10065, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8582 { .RegsBegin: ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_K, .RegSet: ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_KBits, .NameIdx: 10417, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_KBits), .ID: AArch64::ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8583 { .RegsBegin: ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2, .RegSet: ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2Bits, .NameIdx: 1107, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2Bits), .ID: AArch64::ZPR4_with_dsub3_in_FPR64_lo_with_zsub0_zsub1_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8584 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits, .NameIdx: 9582, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_and_ZPR2_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8585 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4767, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8586 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_HiBits, .NameIdx: 14028, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8587 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4301, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8588 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12120, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8589 { .RegsBegin: ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9216, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8590 { .RegsBegin: ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12264, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8591 { .RegsBegin: ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9290, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8592 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12336, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8593 { .RegsBegin: ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_K, .RegSet: ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_KBits, .NameIdx: 9327, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_KBits), .ID: AArch64::ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8594 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4Bits, .NameIdx: 4706, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8595 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4Bits, .NameIdx: 5251, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8596 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3b, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits, .NameIdx: 11610, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul2_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8597 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4Bits, .NameIdx: 5371, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8598 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_HiBits, .NameIdx: 14087, .RegsSize: 2, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8599 { .RegsBegin: ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 1873, .RegsSize: 1, .RegSetSize: sizeof(ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4Strided_with_zsub0_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8600 { .RegsBegin: ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4, .RegSet: ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits, .NameIdx: 2702, .RegsSize: 1, .RegSetSize: sizeof(ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4Bits), .ID: AArch64::ZPR4Strided_with_zsub0_in_ZPRMul2_Lo_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8601 { .RegsBegin: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_K, .RegSet: ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits, .NameIdx: 10008, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KBits), .ID: AArch64::ZPR4_with_dsub1_in_FPR64_lo_and_ZPR4_with_zsub0_in_ZPR_KRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8602 { .RegsBegin: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_Hi, .RegSet: ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiBits, .NameIdx: 12703, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiBits), .ID: AArch64::ZPR4_with_dsub2_in_FPR64_lo_and_ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8603 { .RegsBegin: ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13525, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_dsub3_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8604 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits, .NameIdx: 3328, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub1_zsub2_in_ZPR2Mul2_Hi_and_ZPR2_with_zsub0_in_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8605 { .RegsBegin: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2508, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_in_ZPR_K_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8606 { .RegsBegin: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2044, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub0_zsub1_zsub2_in_ZPR3_with_zsub0_zsub1_in_ZPR2Mul2_with_zsub1_zsub2_in_ZPR2_with_zsub0_in_ZPR_K_and_ZPR2_with_zsub1_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8607 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12086, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub1_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8608 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12230, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub2_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8609 { .RegsBegin: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3b, .RegSet: ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bBits, .NameIdx: 12302, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_0to7_and_ZPR4_with_zsub3_in_ZPRMul4_and_ZPR_3bRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8610 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits, .NameIdx: 13587, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8611 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_Hi, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_HiBits, .NameIdx: 13966, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_HiBits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPRMul2_HiRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8612 { .RegsBegin: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4, .RegSet: ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits, .NameIdx: 2579, .RegsSize: 1, .RegSetSize: sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4Bits), .ID: AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPRMul2_Hi_and_ZPRMul4RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8613 { .RegsBegin: GPR64x8Class, .RegSet: GPR64x8ClassBits, .NameIdx: 19648, .RegsSize: 12, .RegSetSize: sizeof(GPR64x8ClassBits), .ID: AArch64::GPR64x8ClassRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8614 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_GPR64noipBits, .NameIdx: 17072, .RegsSize: 11, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8615 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noipBits, .NameIdx: 17152, .RegsSize: 11, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8616 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17478, .RegsSize: 11, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8617 { .RegsBegin: GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18140, .RegsSize: 11, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8618 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, .NameIdx: 17232, .RegsSize: 10, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8619 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17724, .RegsSize: 10, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8620 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18718, .RegsSize: 10, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8621 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPR64, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPR64Bits, .NameIdx: 1654, .RegsSize: 10, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64Bits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8622 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17931, .RegsSize: 10, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8623 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 19468, .RegsSize: 10, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8624 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 19550, .RegsSize: 10, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8625 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, .NameIdx: 17111, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8626 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17437, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8627 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18099, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8628 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPRnotx16, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPRnotx16Bits, .NameIdx: 5993, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPRnotx16Bits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPRnotx16RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8629 { .RegsBegin: GPR64x8Class_with_x8sub_1_in_tcGPR64, .RegSet: GPR64x8Class_with_x8sub_1_in_tcGPR64Bits, .NameIdx: 1691, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64Bits), .ID: AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8630 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17806, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8631 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 19175, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8632 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 19300, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8633 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 19425, .RegsSize: 9, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8634 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, .NameIdx: 17191, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8635 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17683, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8636 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18677, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8637 { .RegsBegin: GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17560, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8638 { .RegsBegin: GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18388, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8639 { .RegsBegin: GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17, .RegSet: GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17Bits, .NameIdx: 6405, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_1_in_tcGPRnotx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8640 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17394, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8641 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18056, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8642 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_tcGPRnotx16, .RegSet: GPR64x8Class_with_x8sub_2_in_tcGPRnotx16Bits, .NameIdx: 6034, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_tcGPRnotx16Bits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_tcGPRnotx16RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8643 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18179, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8644 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 19132, .RegsSize: 8, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8645 { .RegsBegin: GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 19009, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8646 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17640, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8647 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18634, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8648 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, .NameIdx: 17517, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8649 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18345, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8650 { .RegsBegin: GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17, .RegSet: GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17Bits, .NameIdx: 6449, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_3_in_tcGPRnotx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8651 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18800, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8652 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18468, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8653 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18013, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8654 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_tcGPRnotx16, .RegSet: GPR64x8Class_with_x8sub_4_in_tcGPRnotx16Bits, .NameIdx: 6117, .RegsSize: 7, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_tcGPRnotx16Bits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_tcGPRnotx16RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8655 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18966, .RegsSize: 6, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8656 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18591, .RegsSize: 6, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8657 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, .NameIdx: 18302, .RegsSize: 6, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8658 { .RegsBegin: GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17, .RegSet: GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17Bits, .NameIdx: 6538, .RegsSize: 6, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_5_in_tcGPRnotx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8659 { .RegsBegin: GPR64x8Class_with_x8sub_6_in_tcGPRnotx16, .RegSet: GPR64x8Class_with_x8sub_6_in_tcGPRnotx16Bits, .NameIdx: 6158, .RegsSize: 6, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_6_in_tcGPRnotx16Bits), .ID: AArch64::GPR64x8Class_with_x8sub_6_in_tcGPRnotx16RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8660 { .RegsBegin: GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17, .RegSet: GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17Bits, .NameIdx: 6582, .RegsSize: 5, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_7_in_tcGPRnotx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8661 { .RegsBegin: GPR64x8Class_with_sub_32_in_GPR32arg, .RegSet: GPR64x8Class_with_sub_32_in_GPR32argBits, .NameIdx: 12405, .RegsSize: 4, .RegSetSize: sizeof(GPR64x8Class_with_sub_32_in_GPR32argBits), .ID: AArch64::GPR64x8Class_with_sub_32_in_GPR32argRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8662 { .RegsBegin: MPR32, .RegSet: MPR32Bits, .NameIdx: 654, .RegsSize: 4, .RegSetSize: sizeof(MPR32Bits), .ID: AArch64::MPR32RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8663 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64arg, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64argBits, .NameIdx: 12481, .RegsSize: 3, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64argBits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64argRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8664 { .RegsBegin: GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15, .RegSet: GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15Bits, .NameIdx: 5638, .RegsSize: 2, .RegSetSize: sizeof(GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15Bits), .ID: AArch64::GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8665 { .RegsBegin: GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 540, .RegsSize: 2, .RegSetSize: sizeof(GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8666 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, .NameIdx: 5491, .RegsSize: 2, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8667 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 54, .RegsSize: 2, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8668 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 354, .RegsSize: 2, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8669 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64arg, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64argBits, .NameIdx: 12558, .RegsSize: 2, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64argBits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64argRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8670 { .RegsBegin: GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 468, .RegsSize: 2, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8671 { .RegsBegin: GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 126, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8672 { .RegsBegin: GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 0, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_8_11_and_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8673 { .RegsBegin: GPR64x8Class_with_x8sub_0_in_tcGPRx16x17, .RegSet: GPR64x8Class_with_x8sub_0_in_tcGPRx16x17Bits, .NameIdx: 6199, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_0_in_tcGPRx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_0_in_tcGPRx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8674 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 312, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_GPR64arg_and_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8675 { .RegsBegin: GPR64x8Class_with_x8sub_2_in_tcGPRx16x17, .RegSet: GPR64x8Class_with_x8sub_2_in_tcGPRx16x17Bits, .NameIdx: 6240, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_2_in_tcGPRx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_2_in_tcGPRx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8676 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11, .RegSet: GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits, .NameIdx: 426, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11Bits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_GPR64arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8677 { .RegsBegin: GPR64x8Class_with_x8sub_4_in_tcGPRx16x17, .RegSet: GPR64x8Class_with_x8sub_4_in_tcGPRx16x17Bits, .NameIdx: 6323, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_4_in_tcGPRx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_4_in_tcGPRx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8678 { .RegsBegin: GPR64x8Class_with_x8sub_6_in_GPR64arg, .RegSet: GPR64x8Class_with_x8sub_6_in_GPR64argBits, .NameIdx: 12596, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_6_in_GPR64argBits), .ID: AArch64::GPR64x8Class_with_x8sub_6_in_GPR64argRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8679 { .RegsBegin: GPR64x8Class_with_x8sub_6_in_tcGPRx16x17, .RegSet: GPR64x8Class_with_x8sub_6_in_tcGPRx16x17Bits, .NameIdx: 6364, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_6_in_tcGPRx16x17Bits), .ID: AArch64::GPR64x8Class_with_x8sub_6_in_tcGPRx16x17RegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8680 { .RegsBegin: GPR64x8Class_with_x8sub_7_in_FIXED_REGS, .RegSet: GPR64x8Class_with_x8sub_7_in_FIXED_REGSBits, .NameIdx: 11093, .RegsSize: 1, .RegSetSize: sizeof(GPR64x8Class_with_x8sub_7_in_FIXED_REGSBits), .ID: AArch64::GPR64x8Class_with_x8sub_7_in_FIXED_REGSRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8681 { .RegsBegin: ZTR, .RegSet: ZTRBits, .NameIdx: 11048, .RegsSize: 1, .RegSetSize: sizeof(ZTRBits), .ID: AArch64::ZTRRegClassID, .RegSizeInBits: 512, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
8682 { .RegsBegin: MPR16, .RegSet: MPR16Bits, .NameIdx: 5987, .RegsSize: 2, .RegSetSize: sizeof(MPR16Bits), .ID: AArch64::MPR16RegClassID, .RegSizeInBits: 1024, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8683 { .RegsBegin: MPR, .RegSet: MPRBits, .NameIdx: 11036, .RegsSize: 1, .RegSetSize: sizeof(MPRBits), .ID: AArch64::MPRRegClassID, .RegSizeInBits: 2048, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8684 { .RegsBegin: MPR8, .RegSet: MPR8Bits, .NameIdx: 8640, .RegsSize: 1, .RegSetSize: sizeof(MPR8Bits), .ID: AArch64::MPR8RegClassID, .RegSizeInBits: 2048, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
8685};
8686
8687// AArch64 Dwarf<->LLVM register mappings.
8688extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
8689 { .FromReg: 0U, .ToReg: AArch64::W0 },
8690 { .FromReg: 1U, .ToReg: AArch64::W1 },
8691 { .FromReg: 2U, .ToReg: AArch64::W2 },
8692 { .FromReg: 3U, .ToReg: AArch64::W3 },
8693 { .FromReg: 4U, .ToReg: AArch64::W4 },
8694 { .FromReg: 5U, .ToReg: AArch64::W5 },
8695 { .FromReg: 6U, .ToReg: AArch64::W6 },
8696 { .FromReg: 7U, .ToReg: AArch64::W7 },
8697 { .FromReg: 8U, .ToReg: AArch64::W8 },
8698 { .FromReg: 9U, .ToReg: AArch64::W9 },
8699 { .FromReg: 10U, .ToReg: AArch64::W10 },
8700 { .FromReg: 11U, .ToReg: AArch64::W11 },
8701 { .FromReg: 12U, .ToReg: AArch64::W12 },
8702 { .FromReg: 13U, .ToReg: AArch64::W13 },
8703 { .FromReg: 14U, .ToReg: AArch64::W14 },
8704 { .FromReg: 15U, .ToReg: AArch64::W15 },
8705 { .FromReg: 16U, .ToReg: AArch64::W16 },
8706 { .FromReg: 17U, .ToReg: AArch64::W17 },
8707 { .FromReg: 18U, .ToReg: AArch64::W18 },
8708 { .FromReg: 19U, .ToReg: AArch64::W19 },
8709 { .FromReg: 20U, .ToReg: AArch64::W20 },
8710 { .FromReg: 21U, .ToReg: AArch64::W21 },
8711 { .FromReg: 22U, .ToReg: AArch64::W22 },
8712 { .FromReg: 23U, .ToReg: AArch64::W23 },
8713 { .FromReg: 24U, .ToReg: AArch64::W24 },
8714 { .FromReg: 25U, .ToReg: AArch64::W25 },
8715 { .FromReg: 26U, .ToReg: AArch64::W26 },
8716 { .FromReg: 27U, .ToReg: AArch64::W27 },
8717 { .FromReg: 28U, .ToReg: AArch64::W28 },
8718 { .FromReg: 29U, .ToReg: AArch64::W29 },
8719 { .FromReg: 30U, .ToReg: AArch64::W30 },
8720 { .FromReg: 31U, .ToReg: AArch64::WSP },
8721 { .FromReg: 46U, .ToReg: AArch64::VG },
8722 { .FromReg: 47U, .ToReg: AArch64::FFR },
8723 { .FromReg: 48U, .ToReg: AArch64::PN0 },
8724 { .FromReg: 49U, .ToReg: AArch64::PN1 },
8725 { .FromReg: 50U, .ToReg: AArch64::PN2 },
8726 { .FromReg: 51U, .ToReg: AArch64::PN3 },
8727 { .FromReg: 52U, .ToReg: AArch64::PN4 },
8728 { .FromReg: 53U, .ToReg: AArch64::PN5 },
8729 { .FromReg: 54U, .ToReg: AArch64::PN6 },
8730 { .FromReg: 55U, .ToReg: AArch64::PN7 },
8731 { .FromReg: 56U, .ToReg: AArch64::PN8 },
8732 { .FromReg: 57U, .ToReg: AArch64::PN9 },
8733 { .FromReg: 58U, .ToReg: AArch64::PN10 },
8734 { .FromReg: 59U, .ToReg: AArch64::PN11 },
8735 { .FromReg: 60U, .ToReg: AArch64::PN12 },
8736 { .FromReg: 61U, .ToReg: AArch64::PN13 },
8737 { .FromReg: 62U, .ToReg: AArch64::PN14 },
8738 { .FromReg: 63U, .ToReg: AArch64::PN15 },
8739 { .FromReg: 64U, .ToReg: AArch64::B0 },
8740 { .FromReg: 65U, .ToReg: AArch64::B1 },
8741 { .FromReg: 66U, .ToReg: AArch64::B2 },
8742 { .FromReg: 67U, .ToReg: AArch64::B3 },
8743 { .FromReg: 68U, .ToReg: AArch64::B4 },
8744 { .FromReg: 69U, .ToReg: AArch64::B5 },
8745 { .FromReg: 70U, .ToReg: AArch64::B6 },
8746 { .FromReg: 71U, .ToReg: AArch64::B7 },
8747 { .FromReg: 72U, .ToReg: AArch64::B8 },
8748 { .FromReg: 73U, .ToReg: AArch64::B9 },
8749 { .FromReg: 74U, .ToReg: AArch64::B10 },
8750 { .FromReg: 75U, .ToReg: AArch64::B11 },
8751 { .FromReg: 76U, .ToReg: AArch64::B12 },
8752 { .FromReg: 77U, .ToReg: AArch64::B13 },
8753 { .FromReg: 78U, .ToReg: AArch64::B14 },
8754 { .FromReg: 79U, .ToReg: AArch64::B15 },
8755 { .FromReg: 80U, .ToReg: AArch64::B16 },
8756 { .FromReg: 81U, .ToReg: AArch64::B17 },
8757 { .FromReg: 82U, .ToReg: AArch64::B18 },
8758 { .FromReg: 83U, .ToReg: AArch64::B19 },
8759 { .FromReg: 84U, .ToReg: AArch64::B20 },
8760 { .FromReg: 85U, .ToReg: AArch64::B21 },
8761 { .FromReg: 86U, .ToReg: AArch64::B22 },
8762 { .FromReg: 87U, .ToReg: AArch64::B23 },
8763 { .FromReg: 88U, .ToReg: AArch64::B24 },
8764 { .FromReg: 89U, .ToReg: AArch64::B25 },
8765 { .FromReg: 90U, .ToReg: AArch64::B26 },
8766 { .FromReg: 91U, .ToReg: AArch64::B27 },
8767 { .FromReg: 92U, .ToReg: AArch64::B28 },
8768 { .FromReg: 93U, .ToReg: AArch64::B29 },
8769 { .FromReg: 94U, .ToReg: AArch64::B30 },
8770 { .FromReg: 95U, .ToReg: AArch64::B31 },
8771 { .FromReg: 96U, .ToReg: AArch64::Z0 },
8772 { .FromReg: 97U, .ToReg: AArch64::Z1 },
8773 { .FromReg: 98U, .ToReg: AArch64::Z2 },
8774 { .FromReg: 99U, .ToReg: AArch64::Z3 },
8775 { .FromReg: 100U, .ToReg: AArch64::Z4 },
8776 { .FromReg: 101U, .ToReg: AArch64::Z5 },
8777 { .FromReg: 102U, .ToReg: AArch64::Z6 },
8778 { .FromReg: 103U, .ToReg: AArch64::Z7 },
8779 { .FromReg: 104U, .ToReg: AArch64::Z8 },
8780 { .FromReg: 105U, .ToReg: AArch64::Z9 },
8781 { .FromReg: 106U, .ToReg: AArch64::Z10 },
8782 { .FromReg: 107U, .ToReg: AArch64::Z11 },
8783 { .FromReg: 108U, .ToReg: AArch64::Z12 },
8784 { .FromReg: 109U, .ToReg: AArch64::Z13 },
8785 { .FromReg: 110U, .ToReg: AArch64::Z14 },
8786 { .FromReg: 111U, .ToReg: AArch64::Z15 },
8787 { .FromReg: 112U, .ToReg: AArch64::Z16 },
8788 { .FromReg: 113U, .ToReg: AArch64::Z17 },
8789 { .FromReg: 114U, .ToReg: AArch64::Z18 },
8790 { .FromReg: 115U, .ToReg: AArch64::Z19 },
8791 { .FromReg: 116U, .ToReg: AArch64::Z20 },
8792 { .FromReg: 117U, .ToReg: AArch64::Z21 },
8793 { .FromReg: 118U, .ToReg: AArch64::Z22 },
8794 { .FromReg: 119U, .ToReg: AArch64::Z23 },
8795 { .FromReg: 120U, .ToReg: AArch64::Z24 },
8796 { .FromReg: 121U, .ToReg: AArch64::Z25 },
8797 { .FromReg: 122U, .ToReg: AArch64::Z26 },
8798 { .FromReg: 123U, .ToReg: AArch64::Z27 },
8799 { .FromReg: 124U, .ToReg: AArch64::Z28 },
8800 { .FromReg: 125U, .ToReg: AArch64::Z29 },
8801 { .FromReg: 126U, .ToReg: AArch64::Z30 },
8802 { .FromReg: 127U, .ToReg: AArch64::Z31 },
8803};
8804extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = std::size(AArch64DwarfFlavour0Dwarf2L);
8805
8806extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
8807 { .FromReg: 0U, .ToReg: AArch64::W0 },
8808 { .FromReg: 1U, .ToReg: AArch64::W1 },
8809 { .FromReg: 2U, .ToReg: AArch64::W2 },
8810 { .FromReg: 3U, .ToReg: AArch64::W3 },
8811 { .FromReg: 4U, .ToReg: AArch64::W4 },
8812 { .FromReg: 5U, .ToReg: AArch64::W5 },
8813 { .FromReg: 6U, .ToReg: AArch64::W6 },
8814 { .FromReg: 7U, .ToReg: AArch64::W7 },
8815 { .FromReg: 8U, .ToReg: AArch64::W8 },
8816 { .FromReg: 9U, .ToReg: AArch64::W9 },
8817 { .FromReg: 10U, .ToReg: AArch64::W10 },
8818 { .FromReg: 11U, .ToReg: AArch64::W11 },
8819 { .FromReg: 12U, .ToReg: AArch64::W12 },
8820 { .FromReg: 13U, .ToReg: AArch64::W13 },
8821 { .FromReg: 14U, .ToReg: AArch64::W14 },
8822 { .FromReg: 15U, .ToReg: AArch64::W15 },
8823 { .FromReg: 16U, .ToReg: AArch64::W16 },
8824 { .FromReg: 17U, .ToReg: AArch64::W17 },
8825 { .FromReg: 18U, .ToReg: AArch64::W18 },
8826 { .FromReg: 19U, .ToReg: AArch64::W19 },
8827 { .FromReg: 20U, .ToReg: AArch64::W20 },
8828 { .FromReg: 21U, .ToReg: AArch64::W21 },
8829 { .FromReg: 22U, .ToReg: AArch64::W22 },
8830 { .FromReg: 23U, .ToReg: AArch64::W23 },
8831 { .FromReg: 24U, .ToReg: AArch64::W24 },
8832 { .FromReg: 25U, .ToReg: AArch64::W25 },
8833 { .FromReg: 26U, .ToReg: AArch64::W26 },
8834 { .FromReg: 27U, .ToReg: AArch64::W27 },
8835 { .FromReg: 28U, .ToReg: AArch64::W28 },
8836 { .FromReg: 29U, .ToReg: AArch64::W29 },
8837 { .FromReg: 30U, .ToReg: AArch64::W30 },
8838 { .FromReg: 31U, .ToReg: AArch64::WSP },
8839 { .FromReg: 46U, .ToReg: AArch64::VG },
8840 { .FromReg: 47U, .ToReg: AArch64::FFR },
8841 { .FromReg: 48U, .ToReg: AArch64::PN0 },
8842 { .FromReg: 49U, .ToReg: AArch64::PN1 },
8843 { .FromReg: 50U, .ToReg: AArch64::PN2 },
8844 { .FromReg: 51U, .ToReg: AArch64::PN3 },
8845 { .FromReg: 52U, .ToReg: AArch64::PN4 },
8846 { .FromReg: 53U, .ToReg: AArch64::PN5 },
8847 { .FromReg: 54U, .ToReg: AArch64::PN6 },
8848 { .FromReg: 55U, .ToReg: AArch64::PN7 },
8849 { .FromReg: 56U, .ToReg: AArch64::PN8 },
8850 { .FromReg: 57U, .ToReg: AArch64::PN9 },
8851 { .FromReg: 58U, .ToReg: AArch64::PN10 },
8852 { .FromReg: 59U, .ToReg: AArch64::PN11 },
8853 { .FromReg: 60U, .ToReg: AArch64::PN12 },
8854 { .FromReg: 61U, .ToReg: AArch64::PN13 },
8855 { .FromReg: 62U, .ToReg: AArch64::PN14 },
8856 { .FromReg: 63U, .ToReg: AArch64::PN15 },
8857 { .FromReg: 64U, .ToReg: AArch64::B0 },
8858 { .FromReg: 65U, .ToReg: AArch64::B1 },
8859 { .FromReg: 66U, .ToReg: AArch64::B2 },
8860 { .FromReg: 67U, .ToReg: AArch64::B3 },
8861 { .FromReg: 68U, .ToReg: AArch64::B4 },
8862 { .FromReg: 69U, .ToReg: AArch64::B5 },
8863 { .FromReg: 70U, .ToReg: AArch64::B6 },
8864 { .FromReg: 71U, .ToReg: AArch64::B7 },
8865 { .FromReg: 72U, .ToReg: AArch64::B8 },
8866 { .FromReg: 73U, .ToReg: AArch64::B9 },
8867 { .FromReg: 74U, .ToReg: AArch64::B10 },
8868 { .FromReg: 75U, .ToReg: AArch64::B11 },
8869 { .FromReg: 76U, .ToReg: AArch64::B12 },
8870 { .FromReg: 77U, .ToReg: AArch64::B13 },
8871 { .FromReg: 78U, .ToReg: AArch64::B14 },
8872 { .FromReg: 79U, .ToReg: AArch64::B15 },
8873 { .FromReg: 80U, .ToReg: AArch64::B16 },
8874 { .FromReg: 81U, .ToReg: AArch64::B17 },
8875 { .FromReg: 82U, .ToReg: AArch64::B18 },
8876 { .FromReg: 83U, .ToReg: AArch64::B19 },
8877 { .FromReg: 84U, .ToReg: AArch64::B20 },
8878 { .FromReg: 85U, .ToReg: AArch64::B21 },
8879 { .FromReg: 86U, .ToReg: AArch64::B22 },
8880 { .FromReg: 87U, .ToReg: AArch64::B23 },
8881 { .FromReg: 88U, .ToReg: AArch64::B24 },
8882 { .FromReg: 89U, .ToReg: AArch64::B25 },
8883 { .FromReg: 90U, .ToReg: AArch64::B26 },
8884 { .FromReg: 91U, .ToReg: AArch64::B27 },
8885 { .FromReg: 92U, .ToReg: AArch64::B28 },
8886 { .FromReg: 93U, .ToReg: AArch64::B29 },
8887 { .FromReg: 94U, .ToReg: AArch64::B30 },
8888 { .FromReg: 95U, .ToReg: AArch64::B31 },
8889 { .FromReg: 96U, .ToReg: AArch64::Z0 },
8890 { .FromReg: 97U, .ToReg: AArch64::Z1 },
8891 { .FromReg: 98U, .ToReg: AArch64::Z2 },
8892 { .FromReg: 99U, .ToReg: AArch64::Z3 },
8893 { .FromReg: 100U, .ToReg: AArch64::Z4 },
8894 { .FromReg: 101U, .ToReg: AArch64::Z5 },
8895 { .FromReg: 102U, .ToReg: AArch64::Z6 },
8896 { .FromReg: 103U, .ToReg: AArch64::Z7 },
8897 { .FromReg: 104U, .ToReg: AArch64::Z8 },
8898 { .FromReg: 105U, .ToReg: AArch64::Z9 },
8899 { .FromReg: 106U, .ToReg: AArch64::Z10 },
8900 { .FromReg: 107U, .ToReg: AArch64::Z11 },
8901 { .FromReg: 108U, .ToReg: AArch64::Z12 },
8902 { .FromReg: 109U, .ToReg: AArch64::Z13 },
8903 { .FromReg: 110U, .ToReg: AArch64::Z14 },
8904 { .FromReg: 111U, .ToReg: AArch64::Z15 },
8905 { .FromReg: 112U, .ToReg: AArch64::Z16 },
8906 { .FromReg: 113U, .ToReg: AArch64::Z17 },
8907 { .FromReg: 114U, .ToReg: AArch64::Z18 },
8908 { .FromReg: 115U, .ToReg: AArch64::Z19 },
8909 { .FromReg: 116U, .ToReg: AArch64::Z20 },
8910 { .FromReg: 117U, .ToReg: AArch64::Z21 },
8911 { .FromReg: 118U, .ToReg: AArch64::Z22 },
8912 { .FromReg: 119U, .ToReg: AArch64::Z23 },
8913 { .FromReg: 120U, .ToReg: AArch64::Z24 },
8914 { .FromReg: 121U, .ToReg: AArch64::Z25 },
8915 { .FromReg: 122U, .ToReg: AArch64::Z26 },
8916 { .FromReg: 123U, .ToReg: AArch64::Z27 },
8917 { .FromReg: 124U, .ToReg: AArch64::Z28 },
8918 { .FromReg: 125U, .ToReg: AArch64::Z29 },
8919 { .FromReg: 126U, .ToReg: AArch64::Z30 },
8920 { .FromReg: 127U, .ToReg: AArch64::Z31 },
8921};
8922extern const unsigned AArch64EHFlavour0Dwarf2LSize = std::size(AArch64EHFlavour0Dwarf2L);
8923
8924extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
8925 { .FromReg: AArch64::FFR, .ToReg: 47U },
8926 { .FromReg: AArch64::FP, .ToReg: 29U },
8927 { .FromReg: AArch64::LR, .ToReg: 30U },
8928 { .FromReg: AArch64::SP, .ToReg: 31U },
8929 { .FromReg: AArch64::VG, .ToReg: 46U },
8930 { .FromReg: AArch64::WSP, .ToReg: 31U },
8931 { .FromReg: AArch64::WZR, .ToReg: 31U },
8932 { .FromReg: AArch64::XZR, .ToReg: 31U },
8933 { .FromReg: AArch64::B0, .ToReg: 64U },
8934 { .FromReg: AArch64::B1, .ToReg: 65U },
8935 { .FromReg: AArch64::B2, .ToReg: 66U },
8936 { .FromReg: AArch64::B3, .ToReg: 67U },
8937 { .FromReg: AArch64::B4, .ToReg: 68U },
8938 { .FromReg: AArch64::B5, .ToReg: 69U },
8939 { .FromReg: AArch64::B6, .ToReg: 70U },
8940 { .FromReg: AArch64::B7, .ToReg: 71U },
8941 { .FromReg: AArch64::B8, .ToReg: 72U },
8942 { .FromReg: AArch64::B9, .ToReg: 73U },
8943 { .FromReg: AArch64::B10, .ToReg: 74U },
8944 { .FromReg: AArch64::B11, .ToReg: 75U },
8945 { .FromReg: AArch64::B12, .ToReg: 76U },
8946 { .FromReg: AArch64::B13, .ToReg: 77U },
8947 { .FromReg: AArch64::B14, .ToReg: 78U },
8948 { .FromReg: AArch64::B15, .ToReg: 79U },
8949 { .FromReg: AArch64::B16, .ToReg: 80U },
8950 { .FromReg: AArch64::B17, .ToReg: 81U },
8951 { .FromReg: AArch64::B18, .ToReg: 82U },
8952 { .FromReg: AArch64::B19, .ToReg: 83U },
8953 { .FromReg: AArch64::B20, .ToReg: 84U },
8954 { .FromReg: AArch64::B21, .ToReg: 85U },
8955 { .FromReg: AArch64::B22, .ToReg: 86U },
8956 { .FromReg: AArch64::B23, .ToReg: 87U },
8957 { .FromReg: AArch64::B24, .ToReg: 88U },
8958 { .FromReg: AArch64::B25, .ToReg: 89U },
8959 { .FromReg: AArch64::B26, .ToReg: 90U },
8960 { .FromReg: AArch64::B27, .ToReg: 91U },
8961 { .FromReg: AArch64::B28, .ToReg: 92U },
8962 { .FromReg: AArch64::B29, .ToReg: 93U },
8963 { .FromReg: AArch64::B30, .ToReg: 94U },
8964 { .FromReg: AArch64::B31, .ToReg: 95U },
8965 { .FromReg: AArch64::D0, .ToReg: 64U },
8966 { .FromReg: AArch64::D1, .ToReg: 65U },
8967 { .FromReg: AArch64::D2, .ToReg: 66U },
8968 { .FromReg: AArch64::D3, .ToReg: 67U },
8969 { .FromReg: AArch64::D4, .ToReg: 68U },
8970 { .FromReg: AArch64::D5, .ToReg: 69U },
8971 { .FromReg: AArch64::D6, .ToReg: 70U },
8972 { .FromReg: AArch64::D7, .ToReg: 71U },
8973 { .FromReg: AArch64::D8, .ToReg: 72U },
8974 { .FromReg: AArch64::D9, .ToReg: 73U },
8975 { .FromReg: AArch64::D10, .ToReg: 74U },
8976 { .FromReg: AArch64::D11, .ToReg: 75U },
8977 { .FromReg: AArch64::D12, .ToReg: 76U },
8978 { .FromReg: AArch64::D13, .ToReg: 77U },
8979 { .FromReg: AArch64::D14, .ToReg: 78U },
8980 { .FromReg: AArch64::D15, .ToReg: 79U },
8981 { .FromReg: AArch64::D16, .ToReg: 80U },
8982 { .FromReg: AArch64::D17, .ToReg: 81U },
8983 { .FromReg: AArch64::D18, .ToReg: 82U },
8984 { .FromReg: AArch64::D19, .ToReg: 83U },
8985 { .FromReg: AArch64::D20, .ToReg: 84U },
8986 { .FromReg: AArch64::D21, .ToReg: 85U },
8987 { .FromReg: AArch64::D22, .ToReg: 86U },
8988 { .FromReg: AArch64::D23, .ToReg: 87U },
8989 { .FromReg: AArch64::D24, .ToReg: 88U },
8990 { .FromReg: AArch64::D25, .ToReg: 89U },
8991 { .FromReg: AArch64::D26, .ToReg: 90U },
8992 { .FromReg: AArch64::D27, .ToReg: 91U },
8993 { .FromReg: AArch64::D28, .ToReg: 92U },
8994 { .FromReg: AArch64::D29, .ToReg: 93U },
8995 { .FromReg: AArch64::D30, .ToReg: 94U },
8996 { .FromReg: AArch64::D31, .ToReg: 95U },
8997 { .FromReg: AArch64::H0, .ToReg: 64U },
8998 { .FromReg: AArch64::H1, .ToReg: 65U },
8999 { .FromReg: AArch64::H2, .ToReg: 66U },
9000 { .FromReg: AArch64::H3, .ToReg: 67U },
9001 { .FromReg: AArch64::H4, .ToReg: 68U },
9002 { .FromReg: AArch64::H5, .ToReg: 69U },
9003 { .FromReg: AArch64::H6, .ToReg: 70U },
9004 { .FromReg: AArch64::H7, .ToReg: 71U },
9005 { .FromReg: AArch64::H8, .ToReg: 72U },
9006 { .FromReg: AArch64::H9, .ToReg: 73U },
9007 { .FromReg: AArch64::H10, .ToReg: 74U },
9008 { .FromReg: AArch64::H11, .ToReg: 75U },
9009 { .FromReg: AArch64::H12, .ToReg: 76U },
9010 { .FromReg: AArch64::H13, .ToReg: 77U },
9011 { .FromReg: AArch64::H14, .ToReg: 78U },
9012 { .FromReg: AArch64::H15, .ToReg: 79U },
9013 { .FromReg: AArch64::H16, .ToReg: 80U },
9014 { .FromReg: AArch64::H17, .ToReg: 81U },
9015 { .FromReg: AArch64::H18, .ToReg: 82U },
9016 { .FromReg: AArch64::H19, .ToReg: 83U },
9017 { .FromReg: AArch64::H20, .ToReg: 84U },
9018 { .FromReg: AArch64::H21, .ToReg: 85U },
9019 { .FromReg: AArch64::H22, .ToReg: 86U },
9020 { .FromReg: AArch64::H23, .ToReg: 87U },
9021 { .FromReg: AArch64::H24, .ToReg: 88U },
9022 { .FromReg: AArch64::H25, .ToReg: 89U },
9023 { .FromReg: AArch64::H26, .ToReg: 90U },
9024 { .FromReg: AArch64::H27, .ToReg: 91U },
9025 { .FromReg: AArch64::H28, .ToReg: 92U },
9026 { .FromReg: AArch64::H29, .ToReg: 93U },
9027 { .FromReg: AArch64::H30, .ToReg: 94U },
9028 { .FromReg: AArch64::H31, .ToReg: 95U },
9029 { .FromReg: AArch64::P0, .ToReg: 48U },
9030 { .FromReg: AArch64::P1, .ToReg: 49U },
9031 { .FromReg: AArch64::P2, .ToReg: 50U },
9032 { .FromReg: AArch64::P3, .ToReg: 51U },
9033 { .FromReg: AArch64::P4, .ToReg: 52U },
9034 { .FromReg: AArch64::P5, .ToReg: 53U },
9035 { .FromReg: AArch64::P6, .ToReg: 54U },
9036 { .FromReg: AArch64::P7, .ToReg: 55U },
9037 { .FromReg: AArch64::P8, .ToReg: 56U },
9038 { .FromReg: AArch64::P9, .ToReg: 57U },
9039 { .FromReg: AArch64::P10, .ToReg: 58U },
9040 { .FromReg: AArch64::P11, .ToReg: 59U },
9041 { .FromReg: AArch64::P12, .ToReg: 60U },
9042 { .FromReg: AArch64::P13, .ToReg: 61U },
9043 { .FromReg: AArch64::P14, .ToReg: 62U },
9044 { .FromReg: AArch64::P15, .ToReg: 63U },
9045 { .FromReg: AArch64::PN0, .ToReg: 48U },
9046 { .FromReg: AArch64::PN1, .ToReg: 49U },
9047 { .FromReg: AArch64::PN2, .ToReg: 50U },
9048 { .FromReg: AArch64::PN3, .ToReg: 51U },
9049 { .FromReg: AArch64::PN4, .ToReg: 52U },
9050 { .FromReg: AArch64::PN5, .ToReg: 53U },
9051 { .FromReg: AArch64::PN6, .ToReg: 54U },
9052 { .FromReg: AArch64::PN7, .ToReg: 55U },
9053 { .FromReg: AArch64::PN8, .ToReg: 56U },
9054 { .FromReg: AArch64::PN9, .ToReg: 57U },
9055 { .FromReg: AArch64::PN10, .ToReg: 58U },
9056 { .FromReg: AArch64::PN11, .ToReg: 59U },
9057 { .FromReg: AArch64::PN12, .ToReg: 60U },
9058 { .FromReg: AArch64::PN13, .ToReg: 61U },
9059 { .FromReg: AArch64::PN14, .ToReg: 62U },
9060 { .FromReg: AArch64::PN15, .ToReg: 63U },
9061 { .FromReg: AArch64::Q0, .ToReg: 64U },
9062 { .FromReg: AArch64::Q1, .ToReg: 65U },
9063 { .FromReg: AArch64::Q2, .ToReg: 66U },
9064 { .FromReg: AArch64::Q3, .ToReg: 67U },
9065 { .FromReg: AArch64::Q4, .ToReg: 68U },
9066 { .FromReg: AArch64::Q5, .ToReg: 69U },
9067 { .FromReg: AArch64::Q6, .ToReg: 70U },
9068 { .FromReg: AArch64::Q7, .ToReg: 71U },
9069 { .FromReg: AArch64::Q8, .ToReg: 72U },
9070 { .FromReg: AArch64::Q9, .ToReg: 73U },
9071 { .FromReg: AArch64::Q10, .ToReg: 74U },
9072 { .FromReg: AArch64::Q11, .ToReg: 75U },
9073 { .FromReg: AArch64::Q12, .ToReg: 76U },
9074 { .FromReg: AArch64::Q13, .ToReg: 77U },
9075 { .FromReg: AArch64::Q14, .ToReg: 78U },
9076 { .FromReg: AArch64::Q15, .ToReg: 79U },
9077 { .FromReg: AArch64::Q16, .ToReg: 80U },
9078 { .FromReg: AArch64::Q17, .ToReg: 81U },
9079 { .FromReg: AArch64::Q18, .ToReg: 82U },
9080 { .FromReg: AArch64::Q19, .ToReg: 83U },
9081 { .FromReg: AArch64::Q20, .ToReg: 84U },
9082 { .FromReg: AArch64::Q21, .ToReg: 85U },
9083 { .FromReg: AArch64::Q22, .ToReg: 86U },
9084 { .FromReg: AArch64::Q23, .ToReg: 87U },
9085 { .FromReg: AArch64::Q24, .ToReg: 88U },
9086 { .FromReg: AArch64::Q25, .ToReg: 89U },
9087 { .FromReg: AArch64::Q26, .ToReg: 90U },
9088 { .FromReg: AArch64::Q27, .ToReg: 91U },
9089 { .FromReg: AArch64::Q28, .ToReg: 92U },
9090 { .FromReg: AArch64::Q29, .ToReg: 93U },
9091 { .FromReg: AArch64::Q30, .ToReg: 94U },
9092 { .FromReg: AArch64::Q31, .ToReg: 95U },
9093 { .FromReg: AArch64::S0, .ToReg: 64U },
9094 { .FromReg: AArch64::S1, .ToReg: 65U },
9095 { .FromReg: AArch64::S2, .ToReg: 66U },
9096 { .FromReg: AArch64::S3, .ToReg: 67U },
9097 { .FromReg: AArch64::S4, .ToReg: 68U },
9098 { .FromReg: AArch64::S5, .ToReg: 69U },
9099 { .FromReg: AArch64::S6, .ToReg: 70U },
9100 { .FromReg: AArch64::S7, .ToReg: 71U },
9101 { .FromReg: AArch64::S8, .ToReg: 72U },
9102 { .FromReg: AArch64::S9, .ToReg: 73U },
9103 { .FromReg: AArch64::S10, .ToReg: 74U },
9104 { .FromReg: AArch64::S11, .ToReg: 75U },
9105 { .FromReg: AArch64::S12, .ToReg: 76U },
9106 { .FromReg: AArch64::S13, .ToReg: 77U },
9107 { .FromReg: AArch64::S14, .ToReg: 78U },
9108 { .FromReg: AArch64::S15, .ToReg: 79U },
9109 { .FromReg: AArch64::S16, .ToReg: 80U },
9110 { .FromReg: AArch64::S17, .ToReg: 81U },
9111 { .FromReg: AArch64::S18, .ToReg: 82U },
9112 { .FromReg: AArch64::S19, .ToReg: 83U },
9113 { .FromReg: AArch64::S20, .ToReg: 84U },
9114 { .FromReg: AArch64::S21, .ToReg: 85U },
9115 { .FromReg: AArch64::S22, .ToReg: 86U },
9116 { .FromReg: AArch64::S23, .ToReg: 87U },
9117 { .FromReg: AArch64::S24, .ToReg: 88U },
9118 { .FromReg: AArch64::S25, .ToReg: 89U },
9119 { .FromReg: AArch64::S26, .ToReg: 90U },
9120 { .FromReg: AArch64::S27, .ToReg: 91U },
9121 { .FromReg: AArch64::S28, .ToReg: 92U },
9122 { .FromReg: AArch64::S29, .ToReg: 93U },
9123 { .FromReg: AArch64::S30, .ToReg: 94U },
9124 { .FromReg: AArch64::S31, .ToReg: 95U },
9125 { .FromReg: AArch64::W0, .ToReg: 0U },
9126 { .FromReg: AArch64::W1, .ToReg: 1U },
9127 { .FromReg: AArch64::W2, .ToReg: 2U },
9128 { .FromReg: AArch64::W3, .ToReg: 3U },
9129 { .FromReg: AArch64::W4, .ToReg: 4U },
9130 { .FromReg: AArch64::W5, .ToReg: 5U },
9131 { .FromReg: AArch64::W6, .ToReg: 6U },
9132 { .FromReg: AArch64::W7, .ToReg: 7U },
9133 { .FromReg: AArch64::W8, .ToReg: 8U },
9134 { .FromReg: AArch64::W9, .ToReg: 9U },
9135 { .FromReg: AArch64::W10, .ToReg: 10U },
9136 { .FromReg: AArch64::W11, .ToReg: 11U },
9137 { .FromReg: AArch64::W12, .ToReg: 12U },
9138 { .FromReg: AArch64::W13, .ToReg: 13U },
9139 { .FromReg: AArch64::W14, .ToReg: 14U },
9140 { .FromReg: AArch64::W15, .ToReg: 15U },
9141 { .FromReg: AArch64::W16, .ToReg: 16U },
9142 { .FromReg: AArch64::W17, .ToReg: 17U },
9143 { .FromReg: AArch64::W18, .ToReg: 18U },
9144 { .FromReg: AArch64::W19, .ToReg: 19U },
9145 { .FromReg: AArch64::W20, .ToReg: 20U },
9146 { .FromReg: AArch64::W21, .ToReg: 21U },
9147 { .FromReg: AArch64::W22, .ToReg: 22U },
9148 { .FromReg: AArch64::W23, .ToReg: 23U },
9149 { .FromReg: AArch64::W24, .ToReg: 24U },
9150 { .FromReg: AArch64::W25, .ToReg: 25U },
9151 { .FromReg: AArch64::W26, .ToReg: 26U },
9152 { .FromReg: AArch64::W27, .ToReg: 27U },
9153 { .FromReg: AArch64::W28, .ToReg: 28U },
9154 { .FromReg: AArch64::W29, .ToReg: 29U },
9155 { .FromReg: AArch64::W30, .ToReg: 30U },
9156 { .FromReg: AArch64::X0, .ToReg: 0U },
9157 { .FromReg: AArch64::X1, .ToReg: 1U },
9158 { .FromReg: AArch64::X2, .ToReg: 2U },
9159 { .FromReg: AArch64::X3, .ToReg: 3U },
9160 { .FromReg: AArch64::X4, .ToReg: 4U },
9161 { .FromReg: AArch64::X5, .ToReg: 5U },
9162 { .FromReg: AArch64::X6, .ToReg: 6U },
9163 { .FromReg: AArch64::X7, .ToReg: 7U },
9164 { .FromReg: AArch64::X8, .ToReg: 8U },
9165 { .FromReg: AArch64::X9, .ToReg: 9U },
9166 { .FromReg: AArch64::X10, .ToReg: 10U },
9167 { .FromReg: AArch64::X11, .ToReg: 11U },
9168 { .FromReg: AArch64::X12, .ToReg: 12U },
9169 { .FromReg: AArch64::X13, .ToReg: 13U },
9170 { .FromReg: AArch64::X14, .ToReg: 14U },
9171 { .FromReg: AArch64::X15, .ToReg: 15U },
9172 { .FromReg: AArch64::X16, .ToReg: 16U },
9173 { .FromReg: AArch64::X17, .ToReg: 17U },
9174 { .FromReg: AArch64::X18, .ToReg: 18U },
9175 { .FromReg: AArch64::X19, .ToReg: 19U },
9176 { .FromReg: AArch64::X20, .ToReg: 20U },
9177 { .FromReg: AArch64::X21, .ToReg: 21U },
9178 { .FromReg: AArch64::X22, .ToReg: 22U },
9179 { .FromReg: AArch64::X23, .ToReg: 23U },
9180 { .FromReg: AArch64::X24, .ToReg: 24U },
9181 { .FromReg: AArch64::X25, .ToReg: 25U },
9182 { .FromReg: AArch64::X26, .ToReg: 26U },
9183 { .FromReg: AArch64::X27, .ToReg: 27U },
9184 { .FromReg: AArch64::X28, .ToReg: 28U },
9185 { .FromReg: AArch64::Z0, .ToReg: 96U },
9186 { .FromReg: AArch64::Z1, .ToReg: 97U },
9187 { .FromReg: AArch64::Z2, .ToReg: 98U },
9188 { .FromReg: AArch64::Z3, .ToReg: 99U },
9189 { .FromReg: AArch64::Z4, .ToReg: 100U },
9190 { .FromReg: AArch64::Z5, .ToReg: 101U },
9191 { .FromReg: AArch64::Z6, .ToReg: 102U },
9192 { .FromReg: AArch64::Z7, .ToReg: 103U },
9193 { .FromReg: AArch64::Z8, .ToReg: 104U },
9194 { .FromReg: AArch64::Z9, .ToReg: 105U },
9195 { .FromReg: AArch64::Z10, .ToReg: 106U },
9196 { .FromReg: AArch64::Z11, .ToReg: 107U },
9197 { .FromReg: AArch64::Z12, .ToReg: 108U },
9198 { .FromReg: AArch64::Z13, .ToReg: 109U },
9199 { .FromReg: AArch64::Z14, .ToReg: 110U },
9200 { .FromReg: AArch64::Z15, .ToReg: 111U },
9201 { .FromReg: AArch64::Z16, .ToReg: 112U },
9202 { .FromReg: AArch64::Z17, .ToReg: 113U },
9203 { .FromReg: AArch64::Z18, .ToReg: 114U },
9204 { .FromReg: AArch64::Z19, .ToReg: 115U },
9205 { .FromReg: AArch64::Z20, .ToReg: 116U },
9206 { .FromReg: AArch64::Z21, .ToReg: 117U },
9207 { .FromReg: AArch64::Z22, .ToReg: 118U },
9208 { .FromReg: AArch64::Z23, .ToReg: 119U },
9209 { .FromReg: AArch64::Z24, .ToReg: 120U },
9210 { .FromReg: AArch64::Z25, .ToReg: 121U },
9211 { .FromReg: AArch64::Z26, .ToReg: 122U },
9212 { .FromReg: AArch64::Z27, .ToReg: 123U },
9213 { .FromReg: AArch64::Z28, .ToReg: 124U },
9214 { .FromReg: AArch64::Z29, .ToReg: 125U },
9215 { .FromReg: AArch64::Z30, .ToReg: 126U },
9216 { .FromReg: AArch64::Z31, .ToReg: 127U },
9217};
9218extern const unsigned AArch64DwarfFlavour0L2DwarfSize = std::size(AArch64DwarfFlavour0L2Dwarf);
9219
9220extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
9221 { .FromReg: AArch64::FFR, .ToReg: 47U },
9222 { .FromReg: AArch64::FP, .ToReg: 29U },
9223 { .FromReg: AArch64::LR, .ToReg: 30U },
9224 { .FromReg: AArch64::SP, .ToReg: 31U },
9225 { .FromReg: AArch64::VG, .ToReg: 46U },
9226 { .FromReg: AArch64::WSP, .ToReg: 31U },
9227 { .FromReg: AArch64::WZR, .ToReg: 31U },
9228 { .FromReg: AArch64::XZR, .ToReg: 31U },
9229 { .FromReg: AArch64::B0, .ToReg: 64U },
9230 { .FromReg: AArch64::B1, .ToReg: 65U },
9231 { .FromReg: AArch64::B2, .ToReg: 66U },
9232 { .FromReg: AArch64::B3, .ToReg: 67U },
9233 { .FromReg: AArch64::B4, .ToReg: 68U },
9234 { .FromReg: AArch64::B5, .ToReg: 69U },
9235 { .FromReg: AArch64::B6, .ToReg: 70U },
9236 { .FromReg: AArch64::B7, .ToReg: 71U },
9237 { .FromReg: AArch64::B8, .ToReg: 72U },
9238 { .FromReg: AArch64::B9, .ToReg: 73U },
9239 { .FromReg: AArch64::B10, .ToReg: 74U },
9240 { .FromReg: AArch64::B11, .ToReg: 75U },
9241 { .FromReg: AArch64::B12, .ToReg: 76U },
9242 { .FromReg: AArch64::B13, .ToReg: 77U },
9243 { .FromReg: AArch64::B14, .ToReg: 78U },
9244 { .FromReg: AArch64::B15, .ToReg: 79U },
9245 { .FromReg: AArch64::B16, .ToReg: 80U },
9246 { .FromReg: AArch64::B17, .ToReg: 81U },
9247 { .FromReg: AArch64::B18, .ToReg: 82U },
9248 { .FromReg: AArch64::B19, .ToReg: 83U },
9249 { .FromReg: AArch64::B20, .ToReg: 84U },
9250 { .FromReg: AArch64::B21, .ToReg: 85U },
9251 { .FromReg: AArch64::B22, .ToReg: 86U },
9252 { .FromReg: AArch64::B23, .ToReg: 87U },
9253 { .FromReg: AArch64::B24, .ToReg: 88U },
9254 { .FromReg: AArch64::B25, .ToReg: 89U },
9255 { .FromReg: AArch64::B26, .ToReg: 90U },
9256 { .FromReg: AArch64::B27, .ToReg: 91U },
9257 { .FromReg: AArch64::B28, .ToReg: 92U },
9258 { .FromReg: AArch64::B29, .ToReg: 93U },
9259 { .FromReg: AArch64::B30, .ToReg: 94U },
9260 { .FromReg: AArch64::B31, .ToReg: 95U },
9261 { .FromReg: AArch64::D0, .ToReg: 64U },
9262 { .FromReg: AArch64::D1, .ToReg: 65U },
9263 { .FromReg: AArch64::D2, .ToReg: 66U },
9264 { .FromReg: AArch64::D3, .ToReg: 67U },
9265 { .FromReg: AArch64::D4, .ToReg: 68U },
9266 { .FromReg: AArch64::D5, .ToReg: 69U },
9267 { .FromReg: AArch64::D6, .ToReg: 70U },
9268 { .FromReg: AArch64::D7, .ToReg: 71U },
9269 { .FromReg: AArch64::D8, .ToReg: 72U },
9270 { .FromReg: AArch64::D9, .ToReg: 73U },
9271 { .FromReg: AArch64::D10, .ToReg: 74U },
9272 { .FromReg: AArch64::D11, .ToReg: 75U },
9273 { .FromReg: AArch64::D12, .ToReg: 76U },
9274 { .FromReg: AArch64::D13, .ToReg: 77U },
9275 { .FromReg: AArch64::D14, .ToReg: 78U },
9276 { .FromReg: AArch64::D15, .ToReg: 79U },
9277 { .FromReg: AArch64::D16, .ToReg: 80U },
9278 { .FromReg: AArch64::D17, .ToReg: 81U },
9279 { .FromReg: AArch64::D18, .ToReg: 82U },
9280 { .FromReg: AArch64::D19, .ToReg: 83U },
9281 { .FromReg: AArch64::D20, .ToReg: 84U },
9282 { .FromReg: AArch64::D21, .ToReg: 85U },
9283 { .FromReg: AArch64::D22, .ToReg: 86U },
9284 { .FromReg: AArch64::D23, .ToReg: 87U },
9285 { .FromReg: AArch64::D24, .ToReg: 88U },
9286 { .FromReg: AArch64::D25, .ToReg: 89U },
9287 { .FromReg: AArch64::D26, .ToReg: 90U },
9288 { .FromReg: AArch64::D27, .ToReg: 91U },
9289 { .FromReg: AArch64::D28, .ToReg: 92U },
9290 { .FromReg: AArch64::D29, .ToReg: 93U },
9291 { .FromReg: AArch64::D30, .ToReg: 94U },
9292 { .FromReg: AArch64::D31, .ToReg: 95U },
9293 { .FromReg: AArch64::H0, .ToReg: 64U },
9294 { .FromReg: AArch64::H1, .ToReg: 65U },
9295 { .FromReg: AArch64::H2, .ToReg: 66U },
9296 { .FromReg: AArch64::H3, .ToReg: 67U },
9297 { .FromReg: AArch64::H4, .ToReg: 68U },
9298 { .FromReg: AArch64::H5, .ToReg: 69U },
9299 { .FromReg: AArch64::H6, .ToReg: 70U },
9300 { .FromReg: AArch64::H7, .ToReg: 71U },
9301 { .FromReg: AArch64::H8, .ToReg: 72U },
9302 { .FromReg: AArch64::H9, .ToReg: 73U },
9303 { .FromReg: AArch64::H10, .ToReg: 74U },
9304 { .FromReg: AArch64::H11, .ToReg: 75U },
9305 { .FromReg: AArch64::H12, .ToReg: 76U },
9306 { .FromReg: AArch64::H13, .ToReg: 77U },
9307 { .FromReg: AArch64::H14, .ToReg: 78U },
9308 { .FromReg: AArch64::H15, .ToReg: 79U },
9309 { .FromReg: AArch64::H16, .ToReg: 80U },
9310 { .FromReg: AArch64::H17, .ToReg: 81U },
9311 { .FromReg: AArch64::H18, .ToReg: 82U },
9312 { .FromReg: AArch64::H19, .ToReg: 83U },
9313 { .FromReg: AArch64::H20, .ToReg: 84U },
9314 { .FromReg: AArch64::H21, .ToReg: 85U },
9315 { .FromReg: AArch64::H22, .ToReg: 86U },
9316 { .FromReg: AArch64::H23, .ToReg: 87U },
9317 { .FromReg: AArch64::H24, .ToReg: 88U },
9318 { .FromReg: AArch64::H25, .ToReg: 89U },
9319 { .FromReg: AArch64::H26, .ToReg: 90U },
9320 { .FromReg: AArch64::H27, .ToReg: 91U },
9321 { .FromReg: AArch64::H28, .ToReg: 92U },
9322 { .FromReg: AArch64::H29, .ToReg: 93U },
9323 { .FromReg: AArch64::H30, .ToReg: 94U },
9324 { .FromReg: AArch64::H31, .ToReg: 95U },
9325 { .FromReg: AArch64::P0, .ToReg: 48U },
9326 { .FromReg: AArch64::P1, .ToReg: 49U },
9327 { .FromReg: AArch64::P2, .ToReg: 50U },
9328 { .FromReg: AArch64::P3, .ToReg: 51U },
9329 { .FromReg: AArch64::P4, .ToReg: 52U },
9330 { .FromReg: AArch64::P5, .ToReg: 53U },
9331 { .FromReg: AArch64::P6, .ToReg: 54U },
9332 { .FromReg: AArch64::P7, .ToReg: 55U },
9333 { .FromReg: AArch64::P8, .ToReg: 56U },
9334 { .FromReg: AArch64::P9, .ToReg: 57U },
9335 { .FromReg: AArch64::P10, .ToReg: 58U },
9336 { .FromReg: AArch64::P11, .ToReg: 59U },
9337 { .FromReg: AArch64::P12, .ToReg: 60U },
9338 { .FromReg: AArch64::P13, .ToReg: 61U },
9339 { .FromReg: AArch64::P14, .ToReg: 62U },
9340 { .FromReg: AArch64::P15, .ToReg: 63U },
9341 { .FromReg: AArch64::PN0, .ToReg: 48U },
9342 { .FromReg: AArch64::PN1, .ToReg: 49U },
9343 { .FromReg: AArch64::PN2, .ToReg: 50U },
9344 { .FromReg: AArch64::PN3, .ToReg: 51U },
9345 { .FromReg: AArch64::PN4, .ToReg: 52U },
9346 { .FromReg: AArch64::PN5, .ToReg: 53U },
9347 { .FromReg: AArch64::PN6, .ToReg: 54U },
9348 { .FromReg: AArch64::PN7, .ToReg: 55U },
9349 { .FromReg: AArch64::PN8, .ToReg: 56U },
9350 { .FromReg: AArch64::PN9, .ToReg: 57U },
9351 { .FromReg: AArch64::PN10, .ToReg: 58U },
9352 { .FromReg: AArch64::PN11, .ToReg: 59U },
9353 { .FromReg: AArch64::PN12, .ToReg: 60U },
9354 { .FromReg: AArch64::PN13, .ToReg: 61U },
9355 { .FromReg: AArch64::PN14, .ToReg: 62U },
9356 { .FromReg: AArch64::PN15, .ToReg: 63U },
9357 { .FromReg: AArch64::Q0, .ToReg: 64U },
9358 { .FromReg: AArch64::Q1, .ToReg: 65U },
9359 { .FromReg: AArch64::Q2, .ToReg: 66U },
9360 { .FromReg: AArch64::Q3, .ToReg: 67U },
9361 { .FromReg: AArch64::Q4, .ToReg: 68U },
9362 { .FromReg: AArch64::Q5, .ToReg: 69U },
9363 { .FromReg: AArch64::Q6, .ToReg: 70U },
9364 { .FromReg: AArch64::Q7, .ToReg: 71U },
9365 { .FromReg: AArch64::Q8, .ToReg: 72U },
9366 { .FromReg: AArch64::Q9, .ToReg: 73U },
9367 { .FromReg: AArch64::Q10, .ToReg: 74U },
9368 { .FromReg: AArch64::Q11, .ToReg: 75U },
9369 { .FromReg: AArch64::Q12, .ToReg: 76U },
9370 { .FromReg: AArch64::Q13, .ToReg: 77U },
9371 { .FromReg: AArch64::Q14, .ToReg: 78U },
9372 { .FromReg: AArch64::Q15, .ToReg: 79U },
9373 { .FromReg: AArch64::Q16, .ToReg: 80U },
9374 { .FromReg: AArch64::Q17, .ToReg: 81U },
9375 { .FromReg: AArch64::Q18, .ToReg: 82U },
9376 { .FromReg: AArch64::Q19, .ToReg: 83U },
9377 { .FromReg: AArch64::Q20, .ToReg: 84U },
9378 { .FromReg: AArch64::Q21, .ToReg: 85U },
9379 { .FromReg: AArch64::Q22, .ToReg: 86U },
9380 { .FromReg: AArch64::Q23, .ToReg: 87U },
9381 { .FromReg: AArch64::Q24, .ToReg: 88U },
9382 { .FromReg: AArch64::Q25, .ToReg: 89U },
9383 { .FromReg: AArch64::Q26, .ToReg: 90U },
9384 { .FromReg: AArch64::Q27, .ToReg: 91U },
9385 { .FromReg: AArch64::Q28, .ToReg: 92U },
9386 { .FromReg: AArch64::Q29, .ToReg: 93U },
9387 { .FromReg: AArch64::Q30, .ToReg: 94U },
9388 { .FromReg: AArch64::Q31, .ToReg: 95U },
9389 { .FromReg: AArch64::S0, .ToReg: 64U },
9390 { .FromReg: AArch64::S1, .ToReg: 65U },
9391 { .FromReg: AArch64::S2, .ToReg: 66U },
9392 { .FromReg: AArch64::S3, .ToReg: 67U },
9393 { .FromReg: AArch64::S4, .ToReg: 68U },
9394 { .FromReg: AArch64::S5, .ToReg: 69U },
9395 { .FromReg: AArch64::S6, .ToReg: 70U },
9396 { .FromReg: AArch64::S7, .ToReg: 71U },
9397 { .FromReg: AArch64::S8, .ToReg: 72U },
9398 { .FromReg: AArch64::S9, .ToReg: 73U },
9399 { .FromReg: AArch64::S10, .ToReg: 74U },
9400 { .FromReg: AArch64::S11, .ToReg: 75U },
9401 { .FromReg: AArch64::S12, .ToReg: 76U },
9402 { .FromReg: AArch64::S13, .ToReg: 77U },
9403 { .FromReg: AArch64::S14, .ToReg: 78U },
9404 { .FromReg: AArch64::S15, .ToReg: 79U },
9405 { .FromReg: AArch64::S16, .ToReg: 80U },
9406 { .FromReg: AArch64::S17, .ToReg: 81U },
9407 { .FromReg: AArch64::S18, .ToReg: 82U },
9408 { .FromReg: AArch64::S19, .ToReg: 83U },
9409 { .FromReg: AArch64::S20, .ToReg: 84U },
9410 { .FromReg: AArch64::S21, .ToReg: 85U },
9411 { .FromReg: AArch64::S22, .ToReg: 86U },
9412 { .FromReg: AArch64::S23, .ToReg: 87U },
9413 { .FromReg: AArch64::S24, .ToReg: 88U },
9414 { .FromReg: AArch64::S25, .ToReg: 89U },
9415 { .FromReg: AArch64::S26, .ToReg: 90U },
9416 { .FromReg: AArch64::S27, .ToReg: 91U },
9417 { .FromReg: AArch64::S28, .ToReg: 92U },
9418 { .FromReg: AArch64::S29, .ToReg: 93U },
9419 { .FromReg: AArch64::S30, .ToReg: 94U },
9420 { .FromReg: AArch64::S31, .ToReg: 95U },
9421 { .FromReg: AArch64::W0, .ToReg: 0U },
9422 { .FromReg: AArch64::W1, .ToReg: 1U },
9423 { .FromReg: AArch64::W2, .ToReg: 2U },
9424 { .FromReg: AArch64::W3, .ToReg: 3U },
9425 { .FromReg: AArch64::W4, .ToReg: 4U },
9426 { .FromReg: AArch64::W5, .ToReg: 5U },
9427 { .FromReg: AArch64::W6, .ToReg: 6U },
9428 { .FromReg: AArch64::W7, .ToReg: 7U },
9429 { .FromReg: AArch64::W8, .ToReg: 8U },
9430 { .FromReg: AArch64::W9, .ToReg: 9U },
9431 { .FromReg: AArch64::W10, .ToReg: 10U },
9432 { .FromReg: AArch64::W11, .ToReg: 11U },
9433 { .FromReg: AArch64::W12, .ToReg: 12U },
9434 { .FromReg: AArch64::W13, .ToReg: 13U },
9435 { .FromReg: AArch64::W14, .ToReg: 14U },
9436 { .FromReg: AArch64::W15, .ToReg: 15U },
9437 { .FromReg: AArch64::W16, .ToReg: 16U },
9438 { .FromReg: AArch64::W17, .ToReg: 17U },
9439 { .FromReg: AArch64::W18, .ToReg: 18U },
9440 { .FromReg: AArch64::W19, .ToReg: 19U },
9441 { .FromReg: AArch64::W20, .ToReg: 20U },
9442 { .FromReg: AArch64::W21, .ToReg: 21U },
9443 { .FromReg: AArch64::W22, .ToReg: 22U },
9444 { .FromReg: AArch64::W23, .ToReg: 23U },
9445 { .FromReg: AArch64::W24, .ToReg: 24U },
9446 { .FromReg: AArch64::W25, .ToReg: 25U },
9447 { .FromReg: AArch64::W26, .ToReg: 26U },
9448 { .FromReg: AArch64::W27, .ToReg: 27U },
9449 { .FromReg: AArch64::W28, .ToReg: 28U },
9450 { .FromReg: AArch64::W29, .ToReg: 29U },
9451 { .FromReg: AArch64::W30, .ToReg: 30U },
9452 { .FromReg: AArch64::X0, .ToReg: 0U },
9453 { .FromReg: AArch64::X1, .ToReg: 1U },
9454 { .FromReg: AArch64::X2, .ToReg: 2U },
9455 { .FromReg: AArch64::X3, .ToReg: 3U },
9456 { .FromReg: AArch64::X4, .ToReg: 4U },
9457 { .FromReg: AArch64::X5, .ToReg: 5U },
9458 { .FromReg: AArch64::X6, .ToReg: 6U },
9459 { .FromReg: AArch64::X7, .ToReg: 7U },
9460 { .FromReg: AArch64::X8, .ToReg: 8U },
9461 { .FromReg: AArch64::X9, .ToReg: 9U },
9462 { .FromReg: AArch64::X10, .ToReg: 10U },
9463 { .FromReg: AArch64::X11, .ToReg: 11U },
9464 { .FromReg: AArch64::X12, .ToReg: 12U },
9465 { .FromReg: AArch64::X13, .ToReg: 13U },
9466 { .FromReg: AArch64::X14, .ToReg: 14U },
9467 { .FromReg: AArch64::X15, .ToReg: 15U },
9468 { .FromReg: AArch64::X16, .ToReg: 16U },
9469 { .FromReg: AArch64::X17, .ToReg: 17U },
9470 { .FromReg: AArch64::X18, .ToReg: 18U },
9471 { .FromReg: AArch64::X19, .ToReg: 19U },
9472 { .FromReg: AArch64::X20, .ToReg: 20U },
9473 { .FromReg: AArch64::X21, .ToReg: 21U },
9474 { .FromReg: AArch64::X22, .ToReg: 22U },
9475 { .FromReg: AArch64::X23, .ToReg: 23U },
9476 { .FromReg: AArch64::X24, .ToReg: 24U },
9477 { .FromReg: AArch64::X25, .ToReg: 25U },
9478 { .FromReg: AArch64::X26, .ToReg: 26U },
9479 { .FromReg: AArch64::X27, .ToReg: 27U },
9480 { .FromReg: AArch64::X28, .ToReg: 28U },
9481 { .FromReg: AArch64::Z0, .ToReg: 96U },
9482 { .FromReg: AArch64::Z1, .ToReg: 97U },
9483 { .FromReg: AArch64::Z2, .ToReg: 98U },
9484 { .FromReg: AArch64::Z3, .ToReg: 99U },
9485 { .FromReg: AArch64::Z4, .ToReg: 100U },
9486 { .FromReg: AArch64::Z5, .ToReg: 101U },
9487 { .FromReg: AArch64::Z6, .ToReg: 102U },
9488 { .FromReg: AArch64::Z7, .ToReg: 103U },
9489 { .FromReg: AArch64::Z8, .ToReg: 104U },
9490 { .FromReg: AArch64::Z9, .ToReg: 105U },
9491 { .FromReg: AArch64::Z10, .ToReg: 106U },
9492 { .FromReg: AArch64::Z11, .ToReg: 107U },
9493 { .FromReg: AArch64::Z12, .ToReg: 108U },
9494 { .FromReg: AArch64::Z13, .ToReg: 109U },
9495 { .FromReg: AArch64::Z14, .ToReg: 110U },
9496 { .FromReg: AArch64::Z15, .ToReg: 111U },
9497 { .FromReg: AArch64::Z16, .ToReg: 112U },
9498 { .FromReg: AArch64::Z17, .ToReg: 113U },
9499 { .FromReg: AArch64::Z18, .ToReg: 114U },
9500 { .FromReg: AArch64::Z19, .ToReg: 115U },
9501 { .FromReg: AArch64::Z20, .ToReg: 116U },
9502 { .FromReg: AArch64::Z21, .ToReg: 117U },
9503 { .FromReg: AArch64::Z22, .ToReg: 118U },
9504 { .FromReg: AArch64::Z23, .ToReg: 119U },
9505 { .FromReg: AArch64::Z24, .ToReg: 120U },
9506 { .FromReg: AArch64::Z25, .ToReg: 121U },
9507 { .FromReg: AArch64::Z26, .ToReg: 122U },
9508 { .FromReg: AArch64::Z27, .ToReg: 123U },
9509 { .FromReg: AArch64::Z28, .ToReg: 124U },
9510 { .FromReg: AArch64::Z29, .ToReg: 125U },
9511 { .FromReg: AArch64::Z30, .ToReg: 126U },
9512 { .FromReg: AArch64::Z31, .ToReg: 127U },
9513};
9514extern const unsigned AArch64EHFlavour0L2DwarfSize = std::size(AArch64EHFlavour0L2Dwarf);
9515
9516extern const uint16_t AArch64RegEncodingTable[] = {
9517 0,
9518 0,
9519 29,
9520 0,
9521 0,
9522 0,
9523 30,
9524 0,
9525 31,
9526 0,
9527 31,
9528 65535,
9529 31,
9530 65535,
9531 31,
9532 0,
9533 0,
9534 1,
9535 2,
9536 3,
9537 4,
9538 5,
9539 6,
9540 7,
9541 8,
9542 9,
9543 10,
9544 11,
9545 12,
9546 13,
9547 14,
9548 15,
9549 16,
9550 17,
9551 18,
9552 19,
9553 20,
9554 21,
9555 22,
9556 23,
9557 24,
9558 25,
9559 26,
9560 27,
9561 28,
9562 29,
9563 30,
9564 31,
9565 0,
9566 1,
9567 2,
9568 3,
9569 4,
9570 5,
9571 6,
9572 7,
9573 8,
9574 9,
9575 10,
9576 11,
9577 12,
9578 13,
9579 14,
9580 15,
9581 16,
9582 17,
9583 18,
9584 19,
9585 20,
9586 21,
9587 22,
9588 23,
9589 24,
9590 25,
9591 26,
9592 27,
9593 28,
9594 29,
9595 30,
9596 31,
9597 0,
9598 1,
9599 2,
9600 3,
9601 4,
9602 5,
9603 6,
9604 7,
9605 8,
9606 9,
9607 10,
9608 11,
9609 12,
9610 13,
9611 14,
9612 15,
9613 16,
9614 17,
9615 18,
9616 19,
9617 20,
9618 21,
9619 22,
9620 23,
9621 24,
9622 25,
9623 26,
9624 27,
9625 28,
9626 29,
9627 30,
9628 31,
9629 0,
9630 1,
9631 2,
9632 3,
9633 4,
9634 5,
9635 6,
9636 7,
9637 8,
9638 9,
9639 10,
9640 11,
9641 12,
9642 13,
9643 14,
9644 15,
9645 0,
9646 1,
9647 2,
9648 3,
9649 4,
9650 5,
9651 6,
9652 7,
9653 8,
9654 9,
9655 10,
9656 11,
9657 12,
9658 13,
9659 14,
9660 15,
9661 0,
9662 1,
9663 2,
9664 3,
9665 4,
9666 5,
9667 6,
9668 7,
9669 8,
9670 9,
9671 10,
9672 11,
9673 12,
9674 13,
9675 14,
9676 15,
9677 16,
9678 17,
9679 18,
9680 19,
9681 20,
9682 21,
9683 22,
9684 23,
9685 24,
9686 25,
9687 26,
9688 27,
9689 28,
9690 29,
9691 30,
9692 31,
9693 0,
9694 1,
9695 2,
9696 3,
9697 4,
9698 5,
9699 6,
9700 7,
9701 8,
9702 9,
9703 10,
9704 11,
9705 12,
9706 13,
9707 14,
9708 15,
9709 16,
9710 17,
9711 18,
9712 19,
9713 20,
9714 21,
9715 22,
9716 23,
9717 24,
9718 25,
9719 26,
9720 27,
9721 28,
9722 29,
9723 30,
9724 31,
9725 0,
9726 1,
9727 2,
9728 3,
9729 4,
9730 5,
9731 6,
9732 7,
9733 8,
9734 9,
9735 10,
9736 11,
9737 12,
9738 13,
9739 14,
9740 15,
9741 16,
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9743 18,
9744 19,
9745 20,
9746 21,
9747 22,
9748 23,
9749 24,
9750 25,
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9752 27,
9753 28,
9754 29,
9755 30,
9756 0,
9757 1,
9758 2,
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9760 4,
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9764 8,
9765 9,
9766 10,
9767 11,
9768 12,
9769 13,
9770 14,
9771 15,
9772 16,
9773 17,
9774 18,
9775 19,
9776 20,
9777 21,
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9780 24,
9781 25,
9782 26,
9783 27,
9784 28,
9785 0,
9786 1,
9787 2,
9788 3,
9789 4,
9790 5,
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9795 10,
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9799 14,
9800 15,
9801 16,
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9803 18,
9804 19,
9805 20,
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9810 25,
9811 26,
9812 27,
9813 28,
9814 29,
9815 30,
9816 31,
9817 0,
9818 0,
9819 1,
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9831 3,
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9833 5,
9834 6,
9835 7,
9836 8,
9837 9,
9838 10,
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9840 12,
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9843 15,
9844 0,
9845 1,
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9847 3,
9848 0,
9849 65535,
9850 65535,
9851 65535,
9852 65535,
9853 65535,
9854 65535,
9855 65535,
9856 65535,
9857 65535,
9858 65535,
9859 65535,
9860 65535,
9861 65535,
9862 65535,
9863 65535,
9864 65535,
9865 65535,
9866 65535,
9867 65535,
9868 65535,
9869 65535,
9870 65535,
9871 65535,
9872 65535,
9873 65535,
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9875 65535,
9876 65535,
9877 65535,
9878 65535,
9879 65535,
9880 65535,
9881 65535,
9882 65535,
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9886 65535,
9887 65535,
9888 65535,
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9890 65535,
9891 65535,
9892 65535,
9893 65535,
9894 65535,
9895 65535,
9896 65535,
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9899 65535,
9900 65535,
9901 65535,
9902 65535,
9903 65535,
9904 65535,
9905 65535,
9906 65535,
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9911 65535,
9912 65535,
9913 65535,
9914 65535,
9915 65535,
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9917 65535,
9918 65535,
9919 65535,
9920 65535,
9921 65535,
9922 65535,
9923 65535,
9924 65535,
9925 65535,
9926 65535,
9927 65535,
9928 65535,
9929 65535,
9930 65535,
9931 65535,
9932 65535,
9933 65535,
9934 65535,
9935 65535,
9936 65535,
9937 65535,
9938 65535,
9939 65535,
9940 65535,
9941 65535,
9942 65535,
9943 65535,
9944 65535,
9945 65535,
9946 65535,
9947 65535,
9948 65535,
9949 65535,
9950 65535,
9951 65535,
9952 65535,
9953 65535,
9954 65535,
9955 65535,
9956 65535,
9957 65535,
9958 65535,
9959 65535,
9960 65535,
9961 65535,
9962 65535,
9963 65535,
9964 65535,
9965 65535,
9966 65535,
9967 65535,
9968 65535,
9969 65535,
9970 65535,
9971 65535,
9972 65535,
9973 65535,
9974 65535,
9975 65535,
9976 65535,
9977 65535,
9978 65535,
9979 65535,
9980 65535,
9981 65535,
9982 65535,
9983 65535,
9984 65535,
9985 65535,
9986 65535,
9987 65535,
9988 65535,
9989 65535,
9990 65535,
9991 65535,
9992 65535,
9993 65535,
9994 65535,
9995 65535,
9996 65535,
9997 65535,
9998 65535,
9999 65535,
10000 65535,
10001 65535,
10002 65535,
10003 65535,
10004 65535,
10005 65535,
10006 65535,
10007 65535,
10008 65535,
10009 65535,
10010 65535,
10011 65535,
10012 65535,
10013 65535,
10014 65535,
10015 65535,
10016 65535,
10017 65535,
10018 65535,
10019 65535,
10020 65535,
10021 65535,
10022 65535,
10023 65535,
10024 65535,
10025 65535,
10026 65535,
10027 65535,
10028 65535,
10029 65535,
10030 65535,
10031 65535,
10032 65535,
10033 65535,
10034 65535,
10035 65535,
10036 65535,
10037 65535,
10038 65535,
10039 65535,
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10412};
10413static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
10414 RI->InitMCRegisterInfo(D: AArch64RegDesc, NR: 895, RA, PC, C: AArch64MCRegisterClasses, NC: 530, RURoots: AArch64RegUnitRoots, NRU: 297, DL: AArch64RegDiffLists, RUMS: AArch64LaneMaskLists, Strings: AArch64RegStrings, ClassStrings: AArch64RegClassStrings, SubIndices: AArch64SubRegIdxLists, NumIndices: 144,
10415RET: AArch64RegEncodingTable, RUI: nullptr);
10416
10417 switch (DwarfFlavour) {
10418 default:
10419 llvm_unreachable("Unknown DWARF flavour");
10420 case 0:
10421 RI->mapDwarfRegsToLLVMRegs(Map: AArch64DwarfFlavour0Dwarf2L, Size: AArch64DwarfFlavour0Dwarf2LSize, isEH: false);
10422 break;
10423 }
10424 switch (EHFlavour) {
10425 default:
10426 llvm_unreachable("Unknown DWARF flavour");
10427 case 0:
10428 RI->mapDwarfRegsToLLVMRegs(Map: AArch64EHFlavour0Dwarf2L, Size: AArch64EHFlavour0Dwarf2LSize, isEH: true);
10429 break;
10430 }
10431 switch (DwarfFlavour) {
10432 default:
10433 llvm_unreachable("Unknown DWARF flavour");
10434 case 0:
10435 RI->mapLLVMRegsToDwarfRegs(Map: AArch64DwarfFlavour0L2Dwarf, Size: AArch64DwarfFlavour0L2DwarfSize, isEH: false);
10436 break;
10437 }
10438 switch (EHFlavour) {
10439 default:
10440 llvm_unreachable("Unknown DWARF flavour");
10441 case 0:
10442 RI->mapLLVMRegsToDwarfRegs(Map: AArch64EHFlavour0L2Dwarf, Size: AArch64EHFlavour0L2DwarfSize, isEH: true);
10443 break;
10444 }
10445}
10446
10447
10448} // namespace llvm
10449