1//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AArch64 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64MCTargetDesc.h"
14#include "AArch64ELFStreamer.h"
15#include "AArch64MCAsmInfo.h"
16#include "AArch64MCLFIRewriter.h"
17#include "AArch64WinCOFFStreamer.h"
18#include "MCTargetDesc/AArch64AddressingModes.h"
19#include "MCTargetDesc/AArch64InstPrinter.h"
20#include "TargetInfo/AArch64TargetInfo.h"
21#include "llvm/DebugInfo/CodeView/CodeView.h"
22#include "llvm/MC/MCAsmBackend.h"
23#include "llvm/MC/MCCodeEmitter.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/TargetRegistry.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Endian.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/TargetParser/AArch64TargetParser.h"
35
36using namespace llvm;
37
38#define GET_INSTRINFO_MC_DESC
39#define GET_INSTRINFO_MC_HELPERS
40#define ENABLE_INSTR_PREDICATE_VERIFIER
41#include "AArch64GenInstrInfo.inc"
42
43#define GET_SUBTARGETINFO_MC_DESC
44#include "AArch64GenSubtargetInfo.inc"
45
46#define GET_REGINFO_MC_DESC
47#include "AArch64GenRegisterInfo.inc"
48
49static MCInstrInfo *createAArch64MCInstrInfo() {
50 MCInstrInfo *X = new MCInstrInfo();
51 InitAArch64MCInstrInfo(II: X);
52 return X;
53}
54
55static MCSubtargetInfo *
56createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
57 CPU = AArch64::resolveCPUAlias(CPU);
58
59 if (CPU.empty()) {
60 CPU = "generic";
61 if (FS.empty())
62 FS = "+v8a";
63
64 if (TT.isArm64e())
65 CPU = "apple-a12";
66 }
67
68 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
69}
70
71void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
72 // Mapping from CodeView to MC register id.
73 static const struct {
74 codeview::RegisterId CVReg;
75 MCPhysReg Reg;
76 } RegMap[] = {
77 {.CVReg: codeview::RegisterId::ARM64_W0, .Reg: AArch64::W0},
78 {.CVReg: codeview::RegisterId::ARM64_W1, .Reg: AArch64::W1},
79 {.CVReg: codeview::RegisterId::ARM64_W2, .Reg: AArch64::W2},
80 {.CVReg: codeview::RegisterId::ARM64_W3, .Reg: AArch64::W3},
81 {.CVReg: codeview::RegisterId::ARM64_W4, .Reg: AArch64::W4},
82 {.CVReg: codeview::RegisterId::ARM64_W5, .Reg: AArch64::W5},
83 {.CVReg: codeview::RegisterId::ARM64_W6, .Reg: AArch64::W6},
84 {.CVReg: codeview::RegisterId::ARM64_W7, .Reg: AArch64::W7},
85 {.CVReg: codeview::RegisterId::ARM64_W8, .Reg: AArch64::W8},
86 {.CVReg: codeview::RegisterId::ARM64_W9, .Reg: AArch64::W9},
87 {.CVReg: codeview::RegisterId::ARM64_W10, .Reg: AArch64::W10},
88 {.CVReg: codeview::RegisterId::ARM64_W11, .Reg: AArch64::W11},
89 {.CVReg: codeview::RegisterId::ARM64_W12, .Reg: AArch64::W12},
90 {.CVReg: codeview::RegisterId::ARM64_W13, .Reg: AArch64::W13},
91 {.CVReg: codeview::RegisterId::ARM64_W14, .Reg: AArch64::W14},
92 {.CVReg: codeview::RegisterId::ARM64_W15, .Reg: AArch64::W15},
93 {.CVReg: codeview::RegisterId::ARM64_W16, .Reg: AArch64::W16},
94 {.CVReg: codeview::RegisterId::ARM64_W17, .Reg: AArch64::W17},
95 {.CVReg: codeview::RegisterId::ARM64_W18, .Reg: AArch64::W18},
96 {.CVReg: codeview::RegisterId::ARM64_W19, .Reg: AArch64::W19},
97 {.CVReg: codeview::RegisterId::ARM64_W20, .Reg: AArch64::W20},
98 {.CVReg: codeview::RegisterId::ARM64_W21, .Reg: AArch64::W21},
99 {.CVReg: codeview::RegisterId::ARM64_W22, .Reg: AArch64::W22},
100 {.CVReg: codeview::RegisterId::ARM64_W23, .Reg: AArch64::W23},
101 {.CVReg: codeview::RegisterId::ARM64_W24, .Reg: AArch64::W24},
102 {.CVReg: codeview::RegisterId::ARM64_W25, .Reg: AArch64::W25},
103 {.CVReg: codeview::RegisterId::ARM64_W26, .Reg: AArch64::W26},
104 {.CVReg: codeview::RegisterId::ARM64_W27, .Reg: AArch64::W27},
105 {.CVReg: codeview::RegisterId::ARM64_W28, .Reg: AArch64::W28},
106 {.CVReg: codeview::RegisterId::ARM64_W29, .Reg: AArch64::W29},
107 {.CVReg: codeview::RegisterId::ARM64_W30, .Reg: AArch64::W30},
108 {.CVReg: codeview::RegisterId::ARM64_WZR, .Reg: AArch64::WZR},
109 {.CVReg: codeview::RegisterId::ARM64_X0, .Reg: AArch64::X0},
110 {.CVReg: codeview::RegisterId::ARM64_X1, .Reg: AArch64::X1},
111 {.CVReg: codeview::RegisterId::ARM64_X2, .Reg: AArch64::X2},
112 {.CVReg: codeview::RegisterId::ARM64_X3, .Reg: AArch64::X3},
113 {.CVReg: codeview::RegisterId::ARM64_X4, .Reg: AArch64::X4},
114 {.CVReg: codeview::RegisterId::ARM64_X5, .Reg: AArch64::X5},
115 {.CVReg: codeview::RegisterId::ARM64_X6, .Reg: AArch64::X6},
116 {.CVReg: codeview::RegisterId::ARM64_X7, .Reg: AArch64::X7},
117 {.CVReg: codeview::RegisterId::ARM64_X8, .Reg: AArch64::X8},
118 {.CVReg: codeview::RegisterId::ARM64_X9, .Reg: AArch64::X9},
119 {.CVReg: codeview::RegisterId::ARM64_X10, .Reg: AArch64::X10},
120 {.CVReg: codeview::RegisterId::ARM64_X11, .Reg: AArch64::X11},
121 {.CVReg: codeview::RegisterId::ARM64_X12, .Reg: AArch64::X12},
122 {.CVReg: codeview::RegisterId::ARM64_X13, .Reg: AArch64::X13},
123 {.CVReg: codeview::RegisterId::ARM64_X14, .Reg: AArch64::X14},
124 {.CVReg: codeview::RegisterId::ARM64_X15, .Reg: AArch64::X15},
125 {.CVReg: codeview::RegisterId::ARM64_X16, .Reg: AArch64::X16},
126 {.CVReg: codeview::RegisterId::ARM64_X17, .Reg: AArch64::X17},
127 {.CVReg: codeview::RegisterId::ARM64_X18, .Reg: AArch64::X18},
128 {.CVReg: codeview::RegisterId::ARM64_X19, .Reg: AArch64::X19},
129 {.CVReg: codeview::RegisterId::ARM64_X20, .Reg: AArch64::X20},
130 {.CVReg: codeview::RegisterId::ARM64_X21, .Reg: AArch64::X21},
131 {.CVReg: codeview::RegisterId::ARM64_X22, .Reg: AArch64::X22},
132 {.CVReg: codeview::RegisterId::ARM64_X23, .Reg: AArch64::X23},
133 {.CVReg: codeview::RegisterId::ARM64_X24, .Reg: AArch64::X24},
134 {.CVReg: codeview::RegisterId::ARM64_X25, .Reg: AArch64::X25},
135 {.CVReg: codeview::RegisterId::ARM64_X26, .Reg: AArch64::X26},
136 {.CVReg: codeview::RegisterId::ARM64_X27, .Reg: AArch64::X27},
137 {.CVReg: codeview::RegisterId::ARM64_X28, .Reg: AArch64::X28},
138 {.CVReg: codeview::RegisterId::ARM64_FP, .Reg: AArch64::FP},
139 {.CVReg: codeview::RegisterId::ARM64_LR, .Reg: AArch64::LR},
140 {.CVReg: codeview::RegisterId::ARM64_SP, .Reg: AArch64::SP},
141 {.CVReg: codeview::RegisterId::ARM64_ZR, .Reg: AArch64::XZR},
142 {.CVReg: codeview::RegisterId::ARM64_NZCV, .Reg: AArch64::NZCV},
143 {.CVReg: codeview::RegisterId::ARM64_S0, .Reg: AArch64::S0},
144 {.CVReg: codeview::RegisterId::ARM64_S1, .Reg: AArch64::S1},
145 {.CVReg: codeview::RegisterId::ARM64_S2, .Reg: AArch64::S2},
146 {.CVReg: codeview::RegisterId::ARM64_S3, .Reg: AArch64::S3},
147 {.CVReg: codeview::RegisterId::ARM64_S4, .Reg: AArch64::S4},
148 {.CVReg: codeview::RegisterId::ARM64_S5, .Reg: AArch64::S5},
149 {.CVReg: codeview::RegisterId::ARM64_S6, .Reg: AArch64::S6},
150 {.CVReg: codeview::RegisterId::ARM64_S7, .Reg: AArch64::S7},
151 {.CVReg: codeview::RegisterId::ARM64_S8, .Reg: AArch64::S8},
152 {.CVReg: codeview::RegisterId::ARM64_S9, .Reg: AArch64::S9},
153 {.CVReg: codeview::RegisterId::ARM64_S10, .Reg: AArch64::S10},
154 {.CVReg: codeview::RegisterId::ARM64_S11, .Reg: AArch64::S11},
155 {.CVReg: codeview::RegisterId::ARM64_S12, .Reg: AArch64::S12},
156 {.CVReg: codeview::RegisterId::ARM64_S13, .Reg: AArch64::S13},
157 {.CVReg: codeview::RegisterId::ARM64_S14, .Reg: AArch64::S14},
158 {.CVReg: codeview::RegisterId::ARM64_S15, .Reg: AArch64::S15},
159 {.CVReg: codeview::RegisterId::ARM64_S16, .Reg: AArch64::S16},
160 {.CVReg: codeview::RegisterId::ARM64_S17, .Reg: AArch64::S17},
161 {.CVReg: codeview::RegisterId::ARM64_S18, .Reg: AArch64::S18},
162 {.CVReg: codeview::RegisterId::ARM64_S19, .Reg: AArch64::S19},
163 {.CVReg: codeview::RegisterId::ARM64_S20, .Reg: AArch64::S20},
164 {.CVReg: codeview::RegisterId::ARM64_S21, .Reg: AArch64::S21},
165 {.CVReg: codeview::RegisterId::ARM64_S22, .Reg: AArch64::S22},
166 {.CVReg: codeview::RegisterId::ARM64_S23, .Reg: AArch64::S23},
167 {.CVReg: codeview::RegisterId::ARM64_S24, .Reg: AArch64::S24},
168 {.CVReg: codeview::RegisterId::ARM64_S25, .Reg: AArch64::S25},
169 {.CVReg: codeview::RegisterId::ARM64_S26, .Reg: AArch64::S26},
170 {.CVReg: codeview::RegisterId::ARM64_S27, .Reg: AArch64::S27},
171 {.CVReg: codeview::RegisterId::ARM64_S28, .Reg: AArch64::S28},
172 {.CVReg: codeview::RegisterId::ARM64_S29, .Reg: AArch64::S29},
173 {.CVReg: codeview::RegisterId::ARM64_S30, .Reg: AArch64::S30},
174 {.CVReg: codeview::RegisterId::ARM64_S31, .Reg: AArch64::S31},
175 {.CVReg: codeview::RegisterId::ARM64_D0, .Reg: AArch64::D0},
176 {.CVReg: codeview::RegisterId::ARM64_D1, .Reg: AArch64::D1},
177 {.CVReg: codeview::RegisterId::ARM64_D2, .Reg: AArch64::D2},
178 {.CVReg: codeview::RegisterId::ARM64_D3, .Reg: AArch64::D3},
179 {.CVReg: codeview::RegisterId::ARM64_D4, .Reg: AArch64::D4},
180 {.CVReg: codeview::RegisterId::ARM64_D5, .Reg: AArch64::D5},
181 {.CVReg: codeview::RegisterId::ARM64_D6, .Reg: AArch64::D6},
182 {.CVReg: codeview::RegisterId::ARM64_D7, .Reg: AArch64::D7},
183 {.CVReg: codeview::RegisterId::ARM64_D8, .Reg: AArch64::D8},
184 {.CVReg: codeview::RegisterId::ARM64_D9, .Reg: AArch64::D9},
185 {.CVReg: codeview::RegisterId::ARM64_D10, .Reg: AArch64::D10},
186 {.CVReg: codeview::RegisterId::ARM64_D11, .Reg: AArch64::D11},
187 {.CVReg: codeview::RegisterId::ARM64_D12, .Reg: AArch64::D12},
188 {.CVReg: codeview::RegisterId::ARM64_D13, .Reg: AArch64::D13},
189 {.CVReg: codeview::RegisterId::ARM64_D14, .Reg: AArch64::D14},
190 {.CVReg: codeview::RegisterId::ARM64_D15, .Reg: AArch64::D15},
191 {.CVReg: codeview::RegisterId::ARM64_D16, .Reg: AArch64::D16},
192 {.CVReg: codeview::RegisterId::ARM64_D17, .Reg: AArch64::D17},
193 {.CVReg: codeview::RegisterId::ARM64_D18, .Reg: AArch64::D18},
194 {.CVReg: codeview::RegisterId::ARM64_D19, .Reg: AArch64::D19},
195 {.CVReg: codeview::RegisterId::ARM64_D20, .Reg: AArch64::D20},
196 {.CVReg: codeview::RegisterId::ARM64_D21, .Reg: AArch64::D21},
197 {.CVReg: codeview::RegisterId::ARM64_D22, .Reg: AArch64::D22},
198 {.CVReg: codeview::RegisterId::ARM64_D23, .Reg: AArch64::D23},
199 {.CVReg: codeview::RegisterId::ARM64_D24, .Reg: AArch64::D24},
200 {.CVReg: codeview::RegisterId::ARM64_D25, .Reg: AArch64::D25},
201 {.CVReg: codeview::RegisterId::ARM64_D26, .Reg: AArch64::D26},
202 {.CVReg: codeview::RegisterId::ARM64_D27, .Reg: AArch64::D27},
203 {.CVReg: codeview::RegisterId::ARM64_D28, .Reg: AArch64::D28},
204 {.CVReg: codeview::RegisterId::ARM64_D29, .Reg: AArch64::D29},
205 {.CVReg: codeview::RegisterId::ARM64_D30, .Reg: AArch64::D30},
206 {.CVReg: codeview::RegisterId::ARM64_D31, .Reg: AArch64::D31},
207 {.CVReg: codeview::RegisterId::ARM64_Q0, .Reg: AArch64::Q0},
208 {.CVReg: codeview::RegisterId::ARM64_Q1, .Reg: AArch64::Q1},
209 {.CVReg: codeview::RegisterId::ARM64_Q2, .Reg: AArch64::Q2},
210 {.CVReg: codeview::RegisterId::ARM64_Q3, .Reg: AArch64::Q3},
211 {.CVReg: codeview::RegisterId::ARM64_Q4, .Reg: AArch64::Q4},
212 {.CVReg: codeview::RegisterId::ARM64_Q5, .Reg: AArch64::Q5},
213 {.CVReg: codeview::RegisterId::ARM64_Q6, .Reg: AArch64::Q6},
214 {.CVReg: codeview::RegisterId::ARM64_Q7, .Reg: AArch64::Q7},
215 {.CVReg: codeview::RegisterId::ARM64_Q8, .Reg: AArch64::Q8},
216 {.CVReg: codeview::RegisterId::ARM64_Q9, .Reg: AArch64::Q9},
217 {.CVReg: codeview::RegisterId::ARM64_Q10, .Reg: AArch64::Q10},
218 {.CVReg: codeview::RegisterId::ARM64_Q11, .Reg: AArch64::Q11},
219 {.CVReg: codeview::RegisterId::ARM64_Q12, .Reg: AArch64::Q12},
220 {.CVReg: codeview::RegisterId::ARM64_Q13, .Reg: AArch64::Q13},
221 {.CVReg: codeview::RegisterId::ARM64_Q14, .Reg: AArch64::Q14},
222 {.CVReg: codeview::RegisterId::ARM64_Q15, .Reg: AArch64::Q15},
223 {.CVReg: codeview::RegisterId::ARM64_Q16, .Reg: AArch64::Q16},
224 {.CVReg: codeview::RegisterId::ARM64_Q17, .Reg: AArch64::Q17},
225 {.CVReg: codeview::RegisterId::ARM64_Q18, .Reg: AArch64::Q18},
226 {.CVReg: codeview::RegisterId::ARM64_Q19, .Reg: AArch64::Q19},
227 {.CVReg: codeview::RegisterId::ARM64_Q20, .Reg: AArch64::Q20},
228 {.CVReg: codeview::RegisterId::ARM64_Q21, .Reg: AArch64::Q21},
229 {.CVReg: codeview::RegisterId::ARM64_Q22, .Reg: AArch64::Q22},
230 {.CVReg: codeview::RegisterId::ARM64_Q23, .Reg: AArch64::Q23},
231 {.CVReg: codeview::RegisterId::ARM64_Q24, .Reg: AArch64::Q24},
232 {.CVReg: codeview::RegisterId::ARM64_Q25, .Reg: AArch64::Q25},
233 {.CVReg: codeview::RegisterId::ARM64_Q26, .Reg: AArch64::Q26},
234 {.CVReg: codeview::RegisterId::ARM64_Q27, .Reg: AArch64::Q27},
235 {.CVReg: codeview::RegisterId::ARM64_Q28, .Reg: AArch64::Q28},
236 {.CVReg: codeview::RegisterId::ARM64_Q29, .Reg: AArch64::Q29},
237 {.CVReg: codeview::RegisterId::ARM64_Q30, .Reg: AArch64::Q30},
238 {.CVReg: codeview::RegisterId::ARM64_Q31, .Reg: AArch64::Q31},
239 {.CVReg: codeview::RegisterId::ARM64_B0, .Reg: AArch64::B0},
240 {.CVReg: codeview::RegisterId::ARM64_B1, .Reg: AArch64::B1},
241 {.CVReg: codeview::RegisterId::ARM64_B2, .Reg: AArch64::B2},
242 {.CVReg: codeview::RegisterId::ARM64_B3, .Reg: AArch64::B3},
243 {.CVReg: codeview::RegisterId::ARM64_B4, .Reg: AArch64::B4},
244 {.CVReg: codeview::RegisterId::ARM64_B5, .Reg: AArch64::B5},
245 {.CVReg: codeview::RegisterId::ARM64_B6, .Reg: AArch64::B6},
246 {.CVReg: codeview::RegisterId::ARM64_B7, .Reg: AArch64::B7},
247 {.CVReg: codeview::RegisterId::ARM64_B8, .Reg: AArch64::B8},
248 {.CVReg: codeview::RegisterId::ARM64_B9, .Reg: AArch64::B9},
249 {.CVReg: codeview::RegisterId::ARM64_B10, .Reg: AArch64::B10},
250 {.CVReg: codeview::RegisterId::ARM64_B11, .Reg: AArch64::B11},
251 {.CVReg: codeview::RegisterId::ARM64_B12, .Reg: AArch64::B12},
252 {.CVReg: codeview::RegisterId::ARM64_B13, .Reg: AArch64::B13},
253 {.CVReg: codeview::RegisterId::ARM64_B14, .Reg: AArch64::B14},
254 {.CVReg: codeview::RegisterId::ARM64_B15, .Reg: AArch64::B15},
255 {.CVReg: codeview::RegisterId::ARM64_B16, .Reg: AArch64::B16},
256 {.CVReg: codeview::RegisterId::ARM64_B17, .Reg: AArch64::B17},
257 {.CVReg: codeview::RegisterId::ARM64_B18, .Reg: AArch64::B18},
258 {.CVReg: codeview::RegisterId::ARM64_B19, .Reg: AArch64::B19},
259 {.CVReg: codeview::RegisterId::ARM64_B20, .Reg: AArch64::B20},
260 {.CVReg: codeview::RegisterId::ARM64_B21, .Reg: AArch64::B21},
261 {.CVReg: codeview::RegisterId::ARM64_B22, .Reg: AArch64::B22},
262 {.CVReg: codeview::RegisterId::ARM64_B23, .Reg: AArch64::B23},
263 {.CVReg: codeview::RegisterId::ARM64_B24, .Reg: AArch64::B24},
264 {.CVReg: codeview::RegisterId::ARM64_B25, .Reg: AArch64::B25},
265 {.CVReg: codeview::RegisterId::ARM64_B26, .Reg: AArch64::B26},
266 {.CVReg: codeview::RegisterId::ARM64_B27, .Reg: AArch64::B27},
267 {.CVReg: codeview::RegisterId::ARM64_B28, .Reg: AArch64::B28},
268 {.CVReg: codeview::RegisterId::ARM64_B29, .Reg: AArch64::B29},
269 {.CVReg: codeview::RegisterId::ARM64_B30, .Reg: AArch64::B30},
270 {.CVReg: codeview::RegisterId::ARM64_B31, .Reg: AArch64::B31},
271 {.CVReg: codeview::RegisterId::ARM64_H0, .Reg: AArch64::H0},
272 {.CVReg: codeview::RegisterId::ARM64_H1, .Reg: AArch64::H1},
273 {.CVReg: codeview::RegisterId::ARM64_H2, .Reg: AArch64::H2},
274 {.CVReg: codeview::RegisterId::ARM64_H3, .Reg: AArch64::H3},
275 {.CVReg: codeview::RegisterId::ARM64_H4, .Reg: AArch64::H4},
276 {.CVReg: codeview::RegisterId::ARM64_H5, .Reg: AArch64::H5},
277 {.CVReg: codeview::RegisterId::ARM64_H6, .Reg: AArch64::H6},
278 {.CVReg: codeview::RegisterId::ARM64_H7, .Reg: AArch64::H7},
279 {.CVReg: codeview::RegisterId::ARM64_H8, .Reg: AArch64::H8},
280 {.CVReg: codeview::RegisterId::ARM64_H9, .Reg: AArch64::H9},
281 {.CVReg: codeview::RegisterId::ARM64_H10, .Reg: AArch64::H10},
282 {.CVReg: codeview::RegisterId::ARM64_H11, .Reg: AArch64::H11},
283 {.CVReg: codeview::RegisterId::ARM64_H12, .Reg: AArch64::H12},
284 {.CVReg: codeview::RegisterId::ARM64_H13, .Reg: AArch64::H13},
285 {.CVReg: codeview::RegisterId::ARM64_H14, .Reg: AArch64::H14},
286 {.CVReg: codeview::RegisterId::ARM64_H15, .Reg: AArch64::H15},
287 {.CVReg: codeview::RegisterId::ARM64_H16, .Reg: AArch64::H16},
288 {.CVReg: codeview::RegisterId::ARM64_H17, .Reg: AArch64::H17},
289 {.CVReg: codeview::RegisterId::ARM64_H18, .Reg: AArch64::H18},
290 {.CVReg: codeview::RegisterId::ARM64_H19, .Reg: AArch64::H19},
291 {.CVReg: codeview::RegisterId::ARM64_H20, .Reg: AArch64::H20},
292 {.CVReg: codeview::RegisterId::ARM64_H21, .Reg: AArch64::H21},
293 {.CVReg: codeview::RegisterId::ARM64_H22, .Reg: AArch64::H22},
294 {.CVReg: codeview::RegisterId::ARM64_H23, .Reg: AArch64::H23},
295 {.CVReg: codeview::RegisterId::ARM64_H24, .Reg: AArch64::H24},
296 {.CVReg: codeview::RegisterId::ARM64_H25, .Reg: AArch64::H25},
297 {.CVReg: codeview::RegisterId::ARM64_H26, .Reg: AArch64::H26},
298 {.CVReg: codeview::RegisterId::ARM64_H27, .Reg: AArch64::H27},
299 {.CVReg: codeview::RegisterId::ARM64_H28, .Reg: AArch64::H28},
300 {.CVReg: codeview::RegisterId::ARM64_H29, .Reg: AArch64::H29},
301 {.CVReg: codeview::RegisterId::ARM64_H30, .Reg: AArch64::H30},
302 {.CVReg: codeview::RegisterId::ARM64_H31, .Reg: AArch64::H31},
303 };
304 for (const auto &I : RegMap)
305 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
306}
307
308bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) {
309 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];
310 return llvm::any_of(Range: MI, P: [&](const MCOperand &Op) {
311 return Op.isReg() && FPR16.contains(Reg: Op.getReg());
312 });
313}
314
315bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {
316 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
317 return llvm::any_of(Range: MI, P: [&](const MCOperand &Op) {
318 return Op.isReg() && FPR128.contains(Reg: Op.getReg());
319 });
320}
321
322bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) {
323 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
324 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID];
325 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID];
326 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];
327 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID];
328
329 auto IsFPR = [&](const MCOperand &Op) {
330 if (!Op.isReg())
331 return false;
332 auto Reg = Op.getReg();
333 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||
334 FPR16.contains(Reg) || FPR8.contains(Reg);
335 };
336
337 return llvm::any_of(Range: MI, P: IsFPR);
338}
339
340static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
341 MCRegisterInfo *X = new MCRegisterInfo();
342 InitAArch64MCRegisterInfo(RI: X, RA: AArch64::LR);
343 AArch64_MC::initLLVMToCVRegMapping(MRI: X);
344 return X;
345}
346
347static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
348 const Triple &TheTriple,
349 const MCTargetOptions &Options) {
350 MCAsmInfo *MAI;
351 if (TheTriple.isOSBinFormatMachO())
352 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32,
353 Options);
354 else if (TheTriple.isOSBinFormatELF())
355 MAI = new AArch64MCAsmInfoELF(TheTriple, Options);
356 else if (TheTriple.isWindowsMSVCEnvironment())
357 MAI = new AArch64MCAsmInfoMicrosoftCOFF(Options);
358 else if (TheTriple.isOSBinFormatCOFF())
359 MAI = new AArch64MCAsmInfoGNUCOFF(Options);
360 else
361 reportFatalUsageError(reason: "unsupported object format");
362
363 // Initial state of the frame pointer is SP.
364 unsigned Reg = MRI.getDwarfRegNum(Reg: AArch64::SP, isEH: true);
365 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0);
366 MAI->addInitialFrameState(Inst);
367
368 return MAI;
369}
370
371static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
372 unsigned SyntaxVariant,
373 const MCAsmInfo &MAI,
374 const MCInstrInfo &MII,
375 const MCRegisterInfo &MRI) {
376 if (SyntaxVariant == 0)
377 return new AArch64InstPrinter(MAI, MII, MRI);
378 if (SyntaxVariant == 1)
379 return new AArch64AppleInstPrinter(MAI, MII, MRI);
380
381 return nullptr;
382}
383
384static MCStreamer *
385createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
386 std::unique_ptr<MCObjectWriter> &&OW,
387 std::unique_ptr<MCCodeEmitter> &&Emitter) {
388 return createMachOStreamer(Ctx, TAB: std::move(TAB), OW: std::move(OW),
389 CE: std::move(Emitter), /*ignore=*/DWARFMustBeAtTheEnd: false,
390 /*LabelSections*/ true);
391}
392
393namespace {
394
395class AArch64MCInstrAnalysis : public MCInstrAnalysis {
396public:
397 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
398
399 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
400 uint64_t &Target) const override {
401 // Search for a PC-relative argument.
402 // This will handle instructions like bcc (where the first argument is the
403 // condition code) and cbz (where it is a register).
404 const auto &Desc = Info->get(Opcode: Inst.getOpcode());
405 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
406 if (Desc.operands()[i].OperandType == MCOI::OPERAND_PCREL) {
407 int64_t Imm = Inst.getOperand(i).getImm();
408 if (Inst.getOpcode() == AArch64::ADR)
409 Target = Addr + Imm;
410 else if (Inst.getOpcode() == AArch64::ADRP)
411 Target = (Addr & -4096) + Imm * 4096;
412 else
413 Target = Addr + Imm * 4;
414 return true;
415 }
416 }
417 return false;
418 }
419
420 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
421 APInt &Mask) const override {
422 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
423 unsigned NumDefs = Desc.getNumDefs();
424 unsigned NumImplicitDefs = Desc.implicit_defs().size();
425 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
426 "Unexpected number of bits in the mask!");
427 // 32-bit General Purpose Register class.
428 const MCRegisterClass &GPR32RC = MRI.getRegClass(i: AArch64::GPR32RegClassID);
429 // Floating Point Register classes.
430 const MCRegisterClass &FPR8RC = MRI.getRegClass(i: AArch64::FPR8RegClassID);
431 const MCRegisterClass &FPR16RC = MRI.getRegClass(i: AArch64::FPR16RegClassID);
432 const MCRegisterClass &FPR32RC = MRI.getRegClass(i: AArch64::FPR32RegClassID);
433 const MCRegisterClass &FPR64RC = MRI.getRegClass(i: AArch64::FPR64RegClassID);
434 const MCRegisterClass &FPR128RC =
435 MRI.getRegClass(i: AArch64::FPR128RegClassID);
436
437 auto ClearsSuperReg = [=](MCRegister Reg) {
438 // An update to the lower 32 bits of a 64 bit integer register is
439 // architecturally defined to zero extend the upper 32 bits on a write.
440 if (GPR32RC.contains(Reg))
441 return true;
442 // SIMD&FP instructions operating on scalar data only access the lower
443 // bits of a register, the upper bits are zero extended on a write. For
444 // SIMD vector registers smaller than 128-bits, the upper 64-bits of the
445 // register are zero extended on a write.
446 // When VL is higher than 128 bits, any write to a SIMD&FP register sets
447 // bits higher than 128 to zero.
448 return FPR8RC.contains(Reg) || FPR16RC.contains(Reg) ||
449 FPR32RC.contains(Reg) || FPR64RC.contains(Reg) ||
450 FPR128RC.contains(Reg);
451 };
452
453 Mask.clearAllBits();
454 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
455 const MCOperand &Op = Inst.getOperand(i: I);
456 if (ClearsSuperReg(Op.getReg()))
457 Mask.setBit(I);
458 }
459
460 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
461 const MCPhysReg Reg = Desc.implicit_defs()[I];
462 if (ClearsSuperReg(Reg))
463 Mask.setBit(NumDefs + I);
464 }
465
466 return Mask.getBoolValue();
467 }
468
469 std::vector<std::pair<uint64_t, uint64_t>>
470 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
471 const MCSubtargetInfo &STI) const override {
472 // Do a lightweight parsing of PLT entries.
473 std::vector<std::pair<uint64_t, uint64_t>> Result;
474 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
475 Byte += 4) {
476 uint32_t Insn = support::endian::read32le(P: PltContents.data() + Byte);
477 uint64_t Off = 0;
478 // Check for optional bti c that prefixes adrp in BTI enabled entries
479 if (Insn == 0xd503245f) {
480 Off = 4;
481 Insn = support::endian::read32le(P: PltContents.data() + Byte + Off);
482 }
483 // Check for adrp.
484 if ((Insn & 0x9f000000) != 0x90000000)
485 continue;
486 Off += 4;
487 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
488 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
489 uint32_t Insn2 =
490 support::endian::read32le(P: PltContents.data() + Byte + Off);
491 // Check for: ldr Xt, [Xn, #pimm].
492 if (Insn2 >> 22 == 0x3e5) {
493 Imm += ((Insn2 >> 10) & 0xfff) << 3;
494 Result.push_back(x: std::make_pair(x: PltSectionVA + Byte, y&: Imm));
495 Byte += 4;
496 }
497 }
498 return Result;
499 }
500};
501
502} // end anonymous namespace
503
504static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
505 return new AArch64MCInstrAnalysis(Info);
506}
507
508static MCLFIRewriter *
509createAArch64MCLFIRewriter(MCContext &Ctx,
510 std::unique_ptr<MCRegisterInfo> &&RegInfo,
511 std::unique_ptr<MCInstrInfo> &&InstInfo) {
512 return new AArch64MCLFIRewriter(Ctx, std::move(RegInfo), std::move(InstInfo));
513}
514
515// Force static initialization.
516extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
517LLVMInitializeAArch64TargetMC() {
518 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
519 &getTheAArch64_32Target(), &getTheARM64Target(),
520 &getTheARM64_32Target()}) {
521 // Register the MC asm info.
522 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
523
524 // Register the MC instruction info.
525 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createAArch64MCInstrInfo);
526
527 // Register the MC register info.
528 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createAArch64MCRegisterInfo);
529
530 // Register the MC subtarget info.
531 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createAArch64MCSubtargetInfo);
532
533 // Register the MC instruction analyzer.
534 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createAArch64InstrAnalysis);
535
536 // Register the MC Code Emitter
537 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createAArch64MCCodeEmitter);
538
539 // Register the obj streamers.
540 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createAArch64ELFStreamer);
541 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createMachOStreamer);
542 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createAArch64WinCOFFStreamer);
543
544 // Register the LFI rewriter.
545 TargetRegistry::RegisterMCLFIRewriter(T&: *T, Fn: createAArch64MCLFIRewriter);
546
547 // Register the obj target streamer.
548 TargetRegistry::RegisterObjectTargetStreamer(
549 T&: *T, Fn: createAArch64ObjectTargetStreamer);
550
551 // Register the asm streamer.
552 TargetRegistry::RegisterAsmTargetStreamer(T&: *T,
553 Fn: createAArch64AsmTargetStreamer);
554 // Register the null streamer.
555 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
556 Fn: createAArch64NullTargetStreamer);
557
558 // Register the MCInstPrinter.
559 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createAArch64MCInstPrinter);
560 }
561
562 // Register the asm backend.
563 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
564 &getTheARM64Target(), &getTheARM64_32Target()})
565 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createAArch64leAsmBackend);
566 TargetRegistry::RegisterMCAsmBackend(T&: getTheAArch64beTarget(),
567 Fn: createAArch64beAsmBackend);
568}
569