1//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AArch64 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64MCTargetDesc.h"
14#include "AArch64ELFStreamer.h"
15#include "AArch64MCAsmInfo.h"
16#include "AArch64MCLFIRewriter.h"
17#include "AArch64MCOptions.h"
18#include "AArch64WinCOFFStreamer.h"
19#include "MCTargetDesc/AArch64InstPrinter.h"
20#include "TargetInfo/AArch64TargetInfo.h"
21#include "llvm/DebugInfo/CodeView/CodeView.h"
22#include "llvm/MC/MCAsmBackend.h"
23#include "llvm/MC/MCCodeEmitter.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/TargetRegistry.h"
31#include "llvm/Option/LibraryOptions.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/Endian.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/TargetParser/AArch64TargetParser.h"
36
37using namespace llvm;
38
39#define GET_INSTRINFO_MC_DESC
40#define GET_INSTRINFO_MC_HELPERS
41#define ENABLE_INSTR_PREDICATE_VERIFIER
42#include "AArch64GenInstrInfo.inc"
43
44#define GET_SUBTARGETINFO_MC_DESC
45#include "AArch64GenSubtargetInfo.inc"
46
47#define OPTIONS_STRUCT_DEFS
48#include "AArch64MCOptions.inc"
49
50#define GET_REGINFO_MC_DESC
51#include "AArch64GenRegisterInfo.inc"
52
53static MCInstrInfo *createAArch64MCInstrInfo() {
54 MCInstrInfo *X = new MCInstrInfo();
55 InitAArch64MCInstrInfo(II: X);
56 return X;
57}
58
59static MCSubtargetInfo *
60createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
61 CPU = AArch64::resolveCPUAlias(CPU);
62
63 if (CPU.empty()) {
64 CPU = "generic";
65 if (FS.empty())
66 FS = "+v8a";
67
68 if (TT.isArm64e())
69 CPU = "apple-a12";
70 }
71
72 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
73}
74
75void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
76 // Mapping from CodeView to MC register id.
77 static const struct {
78 codeview::RegisterId CVReg;
79 MCPhysReg Reg;
80 } RegMap[] = {
81 {.CVReg: codeview::RegisterId::ARM64_W0, .Reg: AArch64::W0},
82 {.CVReg: codeview::RegisterId::ARM64_W1, .Reg: AArch64::W1},
83 {.CVReg: codeview::RegisterId::ARM64_W2, .Reg: AArch64::W2},
84 {.CVReg: codeview::RegisterId::ARM64_W3, .Reg: AArch64::W3},
85 {.CVReg: codeview::RegisterId::ARM64_W4, .Reg: AArch64::W4},
86 {.CVReg: codeview::RegisterId::ARM64_W5, .Reg: AArch64::W5},
87 {.CVReg: codeview::RegisterId::ARM64_W6, .Reg: AArch64::W6},
88 {.CVReg: codeview::RegisterId::ARM64_W7, .Reg: AArch64::W7},
89 {.CVReg: codeview::RegisterId::ARM64_W8, .Reg: AArch64::W8},
90 {.CVReg: codeview::RegisterId::ARM64_W9, .Reg: AArch64::W9},
91 {.CVReg: codeview::RegisterId::ARM64_W10, .Reg: AArch64::W10},
92 {.CVReg: codeview::RegisterId::ARM64_W11, .Reg: AArch64::W11},
93 {.CVReg: codeview::RegisterId::ARM64_W12, .Reg: AArch64::W12},
94 {.CVReg: codeview::RegisterId::ARM64_W13, .Reg: AArch64::W13},
95 {.CVReg: codeview::RegisterId::ARM64_W14, .Reg: AArch64::W14},
96 {.CVReg: codeview::RegisterId::ARM64_W15, .Reg: AArch64::W15},
97 {.CVReg: codeview::RegisterId::ARM64_W16, .Reg: AArch64::W16},
98 {.CVReg: codeview::RegisterId::ARM64_W17, .Reg: AArch64::W17},
99 {.CVReg: codeview::RegisterId::ARM64_W18, .Reg: AArch64::W18},
100 {.CVReg: codeview::RegisterId::ARM64_W19, .Reg: AArch64::W19},
101 {.CVReg: codeview::RegisterId::ARM64_W20, .Reg: AArch64::W20},
102 {.CVReg: codeview::RegisterId::ARM64_W21, .Reg: AArch64::W21},
103 {.CVReg: codeview::RegisterId::ARM64_W22, .Reg: AArch64::W22},
104 {.CVReg: codeview::RegisterId::ARM64_W23, .Reg: AArch64::W23},
105 {.CVReg: codeview::RegisterId::ARM64_W24, .Reg: AArch64::W24},
106 {.CVReg: codeview::RegisterId::ARM64_W25, .Reg: AArch64::W25},
107 {.CVReg: codeview::RegisterId::ARM64_W26, .Reg: AArch64::W26},
108 {.CVReg: codeview::RegisterId::ARM64_W27, .Reg: AArch64::W27},
109 {.CVReg: codeview::RegisterId::ARM64_W28, .Reg: AArch64::W28},
110 {.CVReg: codeview::RegisterId::ARM64_W29, .Reg: AArch64::W29},
111 {.CVReg: codeview::RegisterId::ARM64_W30, .Reg: AArch64::W30},
112 {.CVReg: codeview::RegisterId::ARM64_WZR, .Reg: AArch64::WZR},
113 {.CVReg: codeview::RegisterId::ARM64_X0, .Reg: AArch64::X0},
114 {.CVReg: codeview::RegisterId::ARM64_X1, .Reg: AArch64::X1},
115 {.CVReg: codeview::RegisterId::ARM64_X2, .Reg: AArch64::X2},
116 {.CVReg: codeview::RegisterId::ARM64_X3, .Reg: AArch64::X3},
117 {.CVReg: codeview::RegisterId::ARM64_X4, .Reg: AArch64::X4},
118 {.CVReg: codeview::RegisterId::ARM64_X5, .Reg: AArch64::X5},
119 {.CVReg: codeview::RegisterId::ARM64_X6, .Reg: AArch64::X6},
120 {.CVReg: codeview::RegisterId::ARM64_X7, .Reg: AArch64::X7},
121 {.CVReg: codeview::RegisterId::ARM64_X8, .Reg: AArch64::X8},
122 {.CVReg: codeview::RegisterId::ARM64_X9, .Reg: AArch64::X9},
123 {.CVReg: codeview::RegisterId::ARM64_X10, .Reg: AArch64::X10},
124 {.CVReg: codeview::RegisterId::ARM64_X11, .Reg: AArch64::X11},
125 {.CVReg: codeview::RegisterId::ARM64_X12, .Reg: AArch64::X12},
126 {.CVReg: codeview::RegisterId::ARM64_X13, .Reg: AArch64::X13},
127 {.CVReg: codeview::RegisterId::ARM64_X14, .Reg: AArch64::X14},
128 {.CVReg: codeview::RegisterId::ARM64_X15, .Reg: AArch64::X15},
129 {.CVReg: codeview::RegisterId::ARM64_X16, .Reg: AArch64::X16},
130 {.CVReg: codeview::RegisterId::ARM64_X17, .Reg: AArch64::X17},
131 {.CVReg: codeview::RegisterId::ARM64_X18, .Reg: AArch64::X18},
132 {.CVReg: codeview::RegisterId::ARM64_X19, .Reg: AArch64::X19},
133 {.CVReg: codeview::RegisterId::ARM64_X20, .Reg: AArch64::X20},
134 {.CVReg: codeview::RegisterId::ARM64_X21, .Reg: AArch64::X21},
135 {.CVReg: codeview::RegisterId::ARM64_X22, .Reg: AArch64::X22},
136 {.CVReg: codeview::RegisterId::ARM64_X23, .Reg: AArch64::X23},
137 {.CVReg: codeview::RegisterId::ARM64_X24, .Reg: AArch64::X24},
138 {.CVReg: codeview::RegisterId::ARM64_X25, .Reg: AArch64::X25},
139 {.CVReg: codeview::RegisterId::ARM64_X26, .Reg: AArch64::X26},
140 {.CVReg: codeview::RegisterId::ARM64_X27, .Reg: AArch64::X27},
141 {.CVReg: codeview::RegisterId::ARM64_X28, .Reg: AArch64::X28},
142 {.CVReg: codeview::RegisterId::ARM64_FP, .Reg: AArch64::FP},
143 {.CVReg: codeview::RegisterId::ARM64_LR, .Reg: AArch64::LR},
144 {.CVReg: codeview::RegisterId::ARM64_SP, .Reg: AArch64::SP},
145 {.CVReg: codeview::RegisterId::ARM64_ZR, .Reg: AArch64::XZR},
146 {.CVReg: codeview::RegisterId::ARM64_NZCV, .Reg: AArch64::NZCV},
147 {.CVReg: codeview::RegisterId::ARM64_S0, .Reg: AArch64::S0},
148 {.CVReg: codeview::RegisterId::ARM64_S1, .Reg: AArch64::S1},
149 {.CVReg: codeview::RegisterId::ARM64_S2, .Reg: AArch64::S2},
150 {.CVReg: codeview::RegisterId::ARM64_S3, .Reg: AArch64::S3},
151 {.CVReg: codeview::RegisterId::ARM64_S4, .Reg: AArch64::S4},
152 {.CVReg: codeview::RegisterId::ARM64_S5, .Reg: AArch64::S5},
153 {.CVReg: codeview::RegisterId::ARM64_S6, .Reg: AArch64::S6},
154 {.CVReg: codeview::RegisterId::ARM64_S7, .Reg: AArch64::S7},
155 {.CVReg: codeview::RegisterId::ARM64_S8, .Reg: AArch64::S8},
156 {.CVReg: codeview::RegisterId::ARM64_S9, .Reg: AArch64::S9},
157 {.CVReg: codeview::RegisterId::ARM64_S10, .Reg: AArch64::S10},
158 {.CVReg: codeview::RegisterId::ARM64_S11, .Reg: AArch64::S11},
159 {.CVReg: codeview::RegisterId::ARM64_S12, .Reg: AArch64::S12},
160 {.CVReg: codeview::RegisterId::ARM64_S13, .Reg: AArch64::S13},
161 {.CVReg: codeview::RegisterId::ARM64_S14, .Reg: AArch64::S14},
162 {.CVReg: codeview::RegisterId::ARM64_S15, .Reg: AArch64::S15},
163 {.CVReg: codeview::RegisterId::ARM64_S16, .Reg: AArch64::S16},
164 {.CVReg: codeview::RegisterId::ARM64_S17, .Reg: AArch64::S17},
165 {.CVReg: codeview::RegisterId::ARM64_S18, .Reg: AArch64::S18},
166 {.CVReg: codeview::RegisterId::ARM64_S19, .Reg: AArch64::S19},
167 {.CVReg: codeview::RegisterId::ARM64_S20, .Reg: AArch64::S20},
168 {.CVReg: codeview::RegisterId::ARM64_S21, .Reg: AArch64::S21},
169 {.CVReg: codeview::RegisterId::ARM64_S22, .Reg: AArch64::S22},
170 {.CVReg: codeview::RegisterId::ARM64_S23, .Reg: AArch64::S23},
171 {.CVReg: codeview::RegisterId::ARM64_S24, .Reg: AArch64::S24},
172 {.CVReg: codeview::RegisterId::ARM64_S25, .Reg: AArch64::S25},
173 {.CVReg: codeview::RegisterId::ARM64_S26, .Reg: AArch64::S26},
174 {.CVReg: codeview::RegisterId::ARM64_S27, .Reg: AArch64::S27},
175 {.CVReg: codeview::RegisterId::ARM64_S28, .Reg: AArch64::S28},
176 {.CVReg: codeview::RegisterId::ARM64_S29, .Reg: AArch64::S29},
177 {.CVReg: codeview::RegisterId::ARM64_S30, .Reg: AArch64::S30},
178 {.CVReg: codeview::RegisterId::ARM64_S31, .Reg: AArch64::S31},
179 {.CVReg: codeview::RegisterId::ARM64_D0, .Reg: AArch64::D0},
180 {.CVReg: codeview::RegisterId::ARM64_D1, .Reg: AArch64::D1},
181 {.CVReg: codeview::RegisterId::ARM64_D2, .Reg: AArch64::D2},
182 {.CVReg: codeview::RegisterId::ARM64_D3, .Reg: AArch64::D3},
183 {.CVReg: codeview::RegisterId::ARM64_D4, .Reg: AArch64::D4},
184 {.CVReg: codeview::RegisterId::ARM64_D5, .Reg: AArch64::D5},
185 {.CVReg: codeview::RegisterId::ARM64_D6, .Reg: AArch64::D6},
186 {.CVReg: codeview::RegisterId::ARM64_D7, .Reg: AArch64::D7},
187 {.CVReg: codeview::RegisterId::ARM64_D8, .Reg: AArch64::D8},
188 {.CVReg: codeview::RegisterId::ARM64_D9, .Reg: AArch64::D9},
189 {.CVReg: codeview::RegisterId::ARM64_D10, .Reg: AArch64::D10},
190 {.CVReg: codeview::RegisterId::ARM64_D11, .Reg: AArch64::D11},
191 {.CVReg: codeview::RegisterId::ARM64_D12, .Reg: AArch64::D12},
192 {.CVReg: codeview::RegisterId::ARM64_D13, .Reg: AArch64::D13},
193 {.CVReg: codeview::RegisterId::ARM64_D14, .Reg: AArch64::D14},
194 {.CVReg: codeview::RegisterId::ARM64_D15, .Reg: AArch64::D15},
195 {.CVReg: codeview::RegisterId::ARM64_D16, .Reg: AArch64::D16},
196 {.CVReg: codeview::RegisterId::ARM64_D17, .Reg: AArch64::D17},
197 {.CVReg: codeview::RegisterId::ARM64_D18, .Reg: AArch64::D18},
198 {.CVReg: codeview::RegisterId::ARM64_D19, .Reg: AArch64::D19},
199 {.CVReg: codeview::RegisterId::ARM64_D20, .Reg: AArch64::D20},
200 {.CVReg: codeview::RegisterId::ARM64_D21, .Reg: AArch64::D21},
201 {.CVReg: codeview::RegisterId::ARM64_D22, .Reg: AArch64::D22},
202 {.CVReg: codeview::RegisterId::ARM64_D23, .Reg: AArch64::D23},
203 {.CVReg: codeview::RegisterId::ARM64_D24, .Reg: AArch64::D24},
204 {.CVReg: codeview::RegisterId::ARM64_D25, .Reg: AArch64::D25},
205 {.CVReg: codeview::RegisterId::ARM64_D26, .Reg: AArch64::D26},
206 {.CVReg: codeview::RegisterId::ARM64_D27, .Reg: AArch64::D27},
207 {.CVReg: codeview::RegisterId::ARM64_D28, .Reg: AArch64::D28},
208 {.CVReg: codeview::RegisterId::ARM64_D29, .Reg: AArch64::D29},
209 {.CVReg: codeview::RegisterId::ARM64_D30, .Reg: AArch64::D30},
210 {.CVReg: codeview::RegisterId::ARM64_D31, .Reg: AArch64::D31},
211 {.CVReg: codeview::RegisterId::ARM64_Q0, .Reg: AArch64::Q0},
212 {.CVReg: codeview::RegisterId::ARM64_Q1, .Reg: AArch64::Q1},
213 {.CVReg: codeview::RegisterId::ARM64_Q2, .Reg: AArch64::Q2},
214 {.CVReg: codeview::RegisterId::ARM64_Q3, .Reg: AArch64::Q3},
215 {.CVReg: codeview::RegisterId::ARM64_Q4, .Reg: AArch64::Q4},
216 {.CVReg: codeview::RegisterId::ARM64_Q5, .Reg: AArch64::Q5},
217 {.CVReg: codeview::RegisterId::ARM64_Q6, .Reg: AArch64::Q6},
218 {.CVReg: codeview::RegisterId::ARM64_Q7, .Reg: AArch64::Q7},
219 {.CVReg: codeview::RegisterId::ARM64_Q8, .Reg: AArch64::Q8},
220 {.CVReg: codeview::RegisterId::ARM64_Q9, .Reg: AArch64::Q9},
221 {.CVReg: codeview::RegisterId::ARM64_Q10, .Reg: AArch64::Q10},
222 {.CVReg: codeview::RegisterId::ARM64_Q11, .Reg: AArch64::Q11},
223 {.CVReg: codeview::RegisterId::ARM64_Q12, .Reg: AArch64::Q12},
224 {.CVReg: codeview::RegisterId::ARM64_Q13, .Reg: AArch64::Q13},
225 {.CVReg: codeview::RegisterId::ARM64_Q14, .Reg: AArch64::Q14},
226 {.CVReg: codeview::RegisterId::ARM64_Q15, .Reg: AArch64::Q15},
227 {.CVReg: codeview::RegisterId::ARM64_Q16, .Reg: AArch64::Q16},
228 {.CVReg: codeview::RegisterId::ARM64_Q17, .Reg: AArch64::Q17},
229 {.CVReg: codeview::RegisterId::ARM64_Q18, .Reg: AArch64::Q18},
230 {.CVReg: codeview::RegisterId::ARM64_Q19, .Reg: AArch64::Q19},
231 {.CVReg: codeview::RegisterId::ARM64_Q20, .Reg: AArch64::Q20},
232 {.CVReg: codeview::RegisterId::ARM64_Q21, .Reg: AArch64::Q21},
233 {.CVReg: codeview::RegisterId::ARM64_Q22, .Reg: AArch64::Q22},
234 {.CVReg: codeview::RegisterId::ARM64_Q23, .Reg: AArch64::Q23},
235 {.CVReg: codeview::RegisterId::ARM64_Q24, .Reg: AArch64::Q24},
236 {.CVReg: codeview::RegisterId::ARM64_Q25, .Reg: AArch64::Q25},
237 {.CVReg: codeview::RegisterId::ARM64_Q26, .Reg: AArch64::Q26},
238 {.CVReg: codeview::RegisterId::ARM64_Q27, .Reg: AArch64::Q27},
239 {.CVReg: codeview::RegisterId::ARM64_Q28, .Reg: AArch64::Q28},
240 {.CVReg: codeview::RegisterId::ARM64_Q29, .Reg: AArch64::Q29},
241 {.CVReg: codeview::RegisterId::ARM64_Q30, .Reg: AArch64::Q30},
242 {.CVReg: codeview::RegisterId::ARM64_Q31, .Reg: AArch64::Q31},
243 {.CVReg: codeview::RegisterId::ARM64_B0, .Reg: AArch64::B0},
244 {.CVReg: codeview::RegisterId::ARM64_B1, .Reg: AArch64::B1},
245 {.CVReg: codeview::RegisterId::ARM64_B2, .Reg: AArch64::B2},
246 {.CVReg: codeview::RegisterId::ARM64_B3, .Reg: AArch64::B3},
247 {.CVReg: codeview::RegisterId::ARM64_B4, .Reg: AArch64::B4},
248 {.CVReg: codeview::RegisterId::ARM64_B5, .Reg: AArch64::B5},
249 {.CVReg: codeview::RegisterId::ARM64_B6, .Reg: AArch64::B6},
250 {.CVReg: codeview::RegisterId::ARM64_B7, .Reg: AArch64::B7},
251 {.CVReg: codeview::RegisterId::ARM64_B8, .Reg: AArch64::B8},
252 {.CVReg: codeview::RegisterId::ARM64_B9, .Reg: AArch64::B9},
253 {.CVReg: codeview::RegisterId::ARM64_B10, .Reg: AArch64::B10},
254 {.CVReg: codeview::RegisterId::ARM64_B11, .Reg: AArch64::B11},
255 {.CVReg: codeview::RegisterId::ARM64_B12, .Reg: AArch64::B12},
256 {.CVReg: codeview::RegisterId::ARM64_B13, .Reg: AArch64::B13},
257 {.CVReg: codeview::RegisterId::ARM64_B14, .Reg: AArch64::B14},
258 {.CVReg: codeview::RegisterId::ARM64_B15, .Reg: AArch64::B15},
259 {.CVReg: codeview::RegisterId::ARM64_B16, .Reg: AArch64::B16},
260 {.CVReg: codeview::RegisterId::ARM64_B17, .Reg: AArch64::B17},
261 {.CVReg: codeview::RegisterId::ARM64_B18, .Reg: AArch64::B18},
262 {.CVReg: codeview::RegisterId::ARM64_B19, .Reg: AArch64::B19},
263 {.CVReg: codeview::RegisterId::ARM64_B20, .Reg: AArch64::B20},
264 {.CVReg: codeview::RegisterId::ARM64_B21, .Reg: AArch64::B21},
265 {.CVReg: codeview::RegisterId::ARM64_B22, .Reg: AArch64::B22},
266 {.CVReg: codeview::RegisterId::ARM64_B23, .Reg: AArch64::B23},
267 {.CVReg: codeview::RegisterId::ARM64_B24, .Reg: AArch64::B24},
268 {.CVReg: codeview::RegisterId::ARM64_B25, .Reg: AArch64::B25},
269 {.CVReg: codeview::RegisterId::ARM64_B26, .Reg: AArch64::B26},
270 {.CVReg: codeview::RegisterId::ARM64_B27, .Reg: AArch64::B27},
271 {.CVReg: codeview::RegisterId::ARM64_B28, .Reg: AArch64::B28},
272 {.CVReg: codeview::RegisterId::ARM64_B29, .Reg: AArch64::B29},
273 {.CVReg: codeview::RegisterId::ARM64_B30, .Reg: AArch64::B30},
274 {.CVReg: codeview::RegisterId::ARM64_B31, .Reg: AArch64::B31},
275 {.CVReg: codeview::RegisterId::ARM64_H0, .Reg: AArch64::H0},
276 {.CVReg: codeview::RegisterId::ARM64_H1, .Reg: AArch64::H1},
277 {.CVReg: codeview::RegisterId::ARM64_H2, .Reg: AArch64::H2},
278 {.CVReg: codeview::RegisterId::ARM64_H3, .Reg: AArch64::H3},
279 {.CVReg: codeview::RegisterId::ARM64_H4, .Reg: AArch64::H4},
280 {.CVReg: codeview::RegisterId::ARM64_H5, .Reg: AArch64::H5},
281 {.CVReg: codeview::RegisterId::ARM64_H6, .Reg: AArch64::H6},
282 {.CVReg: codeview::RegisterId::ARM64_H7, .Reg: AArch64::H7},
283 {.CVReg: codeview::RegisterId::ARM64_H8, .Reg: AArch64::H8},
284 {.CVReg: codeview::RegisterId::ARM64_H9, .Reg: AArch64::H9},
285 {.CVReg: codeview::RegisterId::ARM64_H10, .Reg: AArch64::H10},
286 {.CVReg: codeview::RegisterId::ARM64_H11, .Reg: AArch64::H11},
287 {.CVReg: codeview::RegisterId::ARM64_H12, .Reg: AArch64::H12},
288 {.CVReg: codeview::RegisterId::ARM64_H13, .Reg: AArch64::H13},
289 {.CVReg: codeview::RegisterId::ARM64_H14, .Reg: AArch64::H14},
290 {.CVReg: codeview::RegisterId::ARM64_H15, .Reg: AArch64::H15},
291 {.CVReg: codeview::RegisterId::ARM64_H16, .Reg: AArch64::H16},
292 {.CVReg: codeview::RegisterId::ARM64_H17, .Reg: AArch64::H17},
293 {.CVReg: codeview::RegisterId::ARM64_H18, .Reg: AArch64::H18},
294 {.CVReg: codeview::RegisterId::ARM64_H19, .Reg: AArch64::H19},
295 {.CVReg: codeview::RegisterId::ARM64_H20, .Reg: AArch64::H20},
296 {.CVReg: codeview::RegisterId::ARM64_H21, .Reg: AArch64::H21},
297 {.CVReg: codeview::RegisterId::ARM64_H22, .Reg: AArch64::H22},
298 {.CVReg: codeview::RegisterId::ARM64_H23, .Reg: AArch64::H23},
299 {.CVReg: codeview::RegisterId::ARM64_H24, .Reg: AArch64::H24},
300 {.CVReg: codeview::RegisterId::ARM64_H25, .Reg: AArch64::H25},
301 {.CVReg: codeview::RegisterId::ARM64_H26, .Reg: AArch64::H26},
302 {.CVReg: codeview::RegisterId::ARM64_H27, .Reg: AArch64::H27},
303 {.CVReg: codeview::RegisterId::ARM64_H28, .Reg: AArch64::H28},
304 {.CVReg: codeview::RegisterId::ARM64_H29, .Reg: AArch64::H29},
305 {.CVReg: codeview::RegisterId::ARM64_H30, .Reg: AArch64::H30},
306 {.CVReg: codeview::RegisterId::ARM64_H31, .Reg: AArch64::H31},
307 };
308 for (const auto &I : RegMap)
309 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
310}
311
312bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) {
313 const auto &FPR16 = getAArch64MCRegisterClass(RC: AArch64::FPR16RegClassID);
314 return llvm::any_of(Range: MI, P: [&](const MCOperand &Op) {
315 return Op.isReg() && FPR16.contains(Reg: Op.getReg());
316 });
317}
318
319bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {
320 const auto &FPR128 = getAArch64MCRegisterClass(RC: AArch64::FPR128RegClassID);
321 return llvm::any_of(Range: MI, P: [&](const MCOperand &Op) {
322 return Op.isReg() && FPR128.contains(Reg: Op.getReg());
323 });
324}
325
326bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) {
327 const auto &FPR128 = getAArch64MCRegisterClass(RC: AArch64::FPR128RegClassID);
328 const auto &FPR64 = getAArch64MCRegisterClass(RC: AArch64::FPR64RegClassID);
329 const auto &FPR32 = getAArch64MCRegisterClass(RC: AArch64::FPR32RegClassID);
330 const auto &FPR16 = getAArch64MCRegisterClass(RC: AArch64::FPR16RegClassID);
331 const auto &FPR8 = getAArch64MCRegisterClass(RC: AArch64::FPR8RegClassID);
332
333 auto IsFPR = [&](const MCOperand &Op) {
334 if (!Op.isReg())
335 return false;
336 auto Reg = Op.getReg();
337 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||
338 FPR16.contains(Reg) || FPR8.contains(Reg);
339 };
340
341 return llvm::any_of(Range: MI, P: IsFPR);
342}
343
344static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
345 MCRegisterInfo *X = new MCRegisterInfo();
346 InitAArch64MCRegisterInfo(RI: X, RA: AArch64::LR);
347 AArch64_MC::initLLVMToCVRegMapping(MRI: X);
348 return X;
349}
350
351static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
352 const Triple &TheTriple,
353 const MCTargetOptions &Options) {
354 MCAsmInfo *MAI;
355 if (TheTriple.isOSBinFormatMachO())
356 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32,
357 Options);
358 else if (TheTriple.isOSBinFormatELF())
359 MAI = new AArch64MCAsmInfoELF(TheTriple, Options);
360 else if (TheTriple.isWindowsMSVCEnvironment())
361 MAI = new AArch64MCAsmInfoMicrosoftCOFF(Options);
362 else if (TheTriple.isOSBinFormatCOFF())
363 MAI = new AArch64MCAsmInfoGNUCOFF(Options);
364 else
365 reportFatalUsageError(reason: "unsupported object format");
366
367 // Initial state of the frame pointer is SP.
368 unsigned Reg = MRI.getDwarfRegNum(Reg: AArch64::SP, isEH: true);
369 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0);
370 MAI->addInitialFrameState(Inst);
371
372 return MAI;
373}
374
375static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
376 unsigned SyntaxVariant,
377 const MCAsmInfo &MAI,
378 const MCInstrInfo &MII,
379 const MCRegisterInfo &MRI) {
380 if (SyntaxVariant == 0)
381 return new AArch64InstPrinter(MAI, MII, MRI);
382 if (SyntaxVariant == 1)
383 return new AArch64AppleInstPrinter(MAI, MII, MRI);
384
385 return nullptr;
386}
387
388static MCStreamer *
389createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
390 std::unique_ptr<MCObjectWriter> &&OW,
391 std::unique_ptr<MCCodeEmitter> &&Emitter) {
392 return createMachOStreamer(Ctx, TAB: std::move(TAB), OW: std::move(OW),
393 CE: std::move(Emitter), /*ignore=*/DWARFMustBeAtTheEnd: false,
394 /*LabelSections*/ true);
395}
396
397namespace {
398
399class AArch64MCInstrAnalysis : public MCInstrAnalysis {
400public:
401 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
402
403 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
404 uint64_t &Target) const override {
405 // Search for a PC-relative argument.
406 // This will handle instructions like bcc (where the first argument is the
407 // condition code) and cbz (where it is a register).
408 const auto &Desc = Info->get(Opcode: Inst.getOpcode());
409 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
410 if (Desc.operands()[i].OperandType == MCOI::OPERAND_PCREL) {
411 int64_t Imm = Inst.getOperand(i).getImm();
412 if (Inst.getOpcode() == AArch64::ADR)
413 Target = Addr + Imm;
414 else if (Inst.getOpcode() == AArch64::ADRP)
415 Target = (Addr & -4096) + Imm * 4096;
416 else
417 Target = Addr + Imm * 4;
418 return true;
419 }
420 }
421 return false;
422 }
423
424 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
425 APInt &Mask) const override {
426 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
427 unsigned NumDefs = Desc.getNumDefs();
428 unsigned NumImplicitDefs = Desc.implicit_defs().size();
429 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
430 "Unexpected number of bits in the mask!");
431 // 32-bit General Purpose Register class.
432 const MCRegisterClass &GPR32RC = MRI.getRegClass(i: AArch64::GPR32RegClassID);
433 // Floating Point Register classes.
434 const MCRegisterClass &FPR8RC = MRI.getRegClass(i: AArch64::FPR8RegClassID);
435 const MCRegisterClass &FPR16RC = MRI.getRegClass(i: AArch64::FPR16RegClassID);
436 const MCRegisterClass &FPR32RC = MRI.getRegClass(i: AArch64::FPR32RegClassID);
437 const MCRegisterClass &FPR64RC = MRI.getRegClass(i: AArch64::FPR64RegClassID);
438 const MCRegisterClass &FPR128RC =
439 MRI.getRegClass(i: AArch64::FPR128RegClassID);
440
441 auto ClearsSuperReg = [&](MCRegister Reg) {
442 // An update to the lower 32 bits of a 64 bit integer register is
443 // architecturally defined to zero extend the upper 32 bits on a write.
444 if (GPR32RC.contains(Reg))
445 return true;
446 // SIMD&FP instructions operating on scalar data only access the lower
447 // bits of a register, the upper bits are zero extended on a write. For
448 // SIMD vector registers smaller than 128-bits, the upper 64-bits of the
449 // register are zero extended on a write.
450 // When VL is higher than 128 bits, any write to a SIMD&FP register sets
451 // bits higher than 128 to zero.
452 return FPR8RC.contains(Reg) || FPR16RC.contains(Reg) ||
453 FPR32RC.contains(Reg) || FPR64RC.contains(Reg) ||
454 FPR128RC.contains(Reg);
455 };
456
457 Mask.clearAllBits();
458 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
459 const MCOperand &Op = Inst.getOperand(i: I);
460 if (ClearsSuperReg(Op.getReg()))
461 Mask.setBit(I);
462 }
463
464 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
465 const MCPhysReg Reg = Desc.implicit_defs()[I];
466 if (ClearsSuperReg(Reg))
467 Mask.setBit(NumDefs + I);
468 }
469
470 return Mask.getBoolValue();
471 }
472
473 std::vector<std::pair<uint64_t, uint64_t>>
474 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
475 const MCSubtargetInfo &STI) const override {
476 // Do a lightweight parsing of PLT entries.
477 std::vector<std::pair<uint64_t, uint64_t>> Result;
478 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
479 Byte += 4) {
480 uint32_t Insn = support::endian::read32le(P: PltContents.data() + Byte);
481 uint64_t Off = 0;
482 // Check for optional bti c that prefixes adrp in BTI enabled entries
483 if (Insn == 0xd503245f) {
484 Off = 4;
485 Insn = support::endian::read32le(P: PltContents.data() + Byte + Off);
486 }
487 // Check for adrp.
488 if ((Insn & 0x9f000000) != 0x90000000)
489 continue;
490 Off += 4;
491 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
492 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
493 uint32_t Insn2 =
494 support::endian::read32le(P: PltContents.data() + Byte + Off);
495 // Check for: ldr Xt, [Xn, #pimm].
496 if (Insn2 >> 22 == 0x3e5) {
497 Imm += ((Insn2 >> 10) & 0xfff) << 3;
498 Result.push_back(x: std::make_pair(x: PltSectionVA + Byte, y&: Imm));
499 Byte += 4;
500 }
501 }
502 return Result;
503 }
504};
505
506} // end anonymous namespace
507
508static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
509 return new AArch64MCInstrAnalysis(Info);
510}
511
512static MCLFIRewriter *
513createAArch64MCLFIRewriter(MCContext &Ctx,
514 std::unique_ptr<MCRegisterInfo> &&RegInfo,
515 std::unique_ptr<MCInstrInfo> &&InstInfo) {
516 return new AArch64MCLFIRewriter(Ctx, std::move(RegInfo), std::move(InstInfo));
517}
518
519// Force static initialization.
520extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
521LLVMInitializeAArch64TargetMC() {
522 static opt::RegisterLibraryOptions<AArch64MCOptions> O;
523 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
524 &getTheAArch64_32Target(), &getTheARM64Target(),
525 &getTheARM64_32Target()}) {
526 // Register the MC asm info.
527 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
528
529 // Register the MC instruction info.
530 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createAArch64MCInstrInfo);
531
532 // Register the MC register info.
533 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createAArch64MCRegisterInfo);
534
535 // Register the MC subtarget info.
536 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createAArch64MCSubtargetInfo);
537
538 // Register the MC instruction analyzer.
539 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createAArch64InstrAnalysis);
540
541 // Register the MC Code Emitter
542 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createAArch64MCCodeEmitter);
543
544 // Register the obj streamers.
545 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createAArch64ELFStreamer);
546 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createMachOStreamer);
547 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createAArch64WinCOFFStreamer);
548
549 // Register the LFI rewriter.
550 TargetRegistry::RegisterMCLFIRewriter(T&: *T, Fn: createAArch64MCLFIRewriter);
551
552 // Register the obj target streamer.
553 TargetRegistry::RegisterObjectTargetStreamer(
554 T&: *T, Fn: createAArch64ObjectTargetStreamer);
555
556 // Register the asm streamer.
557 TargetRegistry::RegisterAsmTargetStreamer(T&: *T,
558 Fn: createAArch64AsmTargetStreamer);
559 // Register the null streamer.
560 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
561 Fn: createAArch64NullTargetStreamer);
562
563 // Register the MCInstPrinter.
564 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createAArch64MCInstPrinter);
565 }
566
567 // Register the asm backend.
568 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
569 &getTheARM64Target(), &getTheARM64_32Target()})
570 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createAArch64leAsmBackend);
571 TargetRegistry::RegisterMCAsmBackend(T&: getTheAArch64beTarget(),
572 Fn: createAArch64beAsmBackend);
573}
574