1//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an AArch64 MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
14#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
15
16#include "MCTargetDesc/AArch64MCTargetDesc.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/MC/MCInstPrinter.h"
19#include "../Utils/AArch64BaseInfo.h"
20
21namespace llvm {
22
23class AArch64InstPrinter : public MCInstPrinter {
24public:
25 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
26 const MCRegisterInfo &MRI);
27
28 bool applyTargetSpecificCLOption(StringRef Opt) override;
29
30 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
31 const MCSubtargetInfo &STI, raw_ostream &O) override;
32 void printRegName(raw_ostream &OS, MCRegister Reg) override;
33 void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx);
34
35 // Autogenerated by tblgen.
36 std::pair<const char *, uint64_t>
37 getMnemonic(const MCInst &MI) const override;
38 virtual void printInstruction(const MCInst *MI, uint64_t Address,
39 const MCSubtargetInfo &STI, raw_ostream &O);
40 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
41 const MCSubtargetInfo &STI, raw_ostream &O);
42 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
43 unsigned OpIdx, unsigned PrintMethodIdx,
44 const MCSubtargetInfo &STI,
45 raw_ostream &O);
46
47 virtual StringRef getRegName(MCRegister Reg) const;
48
49 static const char *getRegisterName(MCRegister Reg,
50 unsigned AltIdx = AArch64::NoRegAltName);
51
52protected:
53 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
54 raw_ostream &O);
55 bool printSyslAlias(const MCInst *MI, const MCSubtargetInfo &STI,
56 raw_ostream &O);
57 bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI,
58 raw_ostream &O);
59 bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI,
60 raw_ostream &O, StringRef Annot);
61 // Operand printers
62 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
63 raw_ostream &O);
64 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
65 raw_ostream &O);
66 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
67 raw_ostream &O);
68 template <int Size>
69 void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
70 raw_ostream &O);
71 template <typename T> void printImmSVE(T Value, raw_ostream &O);
72 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
73 raw_ostream &O);
74 template <int Amount>
75 void printPostIncOperand(const MCInst *MI, unsigned OpNo,
76 const MCSubtargetInfo &STI, raw_ostream &O) {
77 printPostIncOperand(MI, OpNo, Imm: Amount, O);
78 }
79
80 void printVRegOperand(const MCInst *MI, unsigned OpNo,
81 const MCSubtargetInfo &STI, raw_ostream &O);
82 void printSysCROperand(const MCInst *MI, unsigned OpNo,
83 const MCSubtargetInfo &STI, raw_ostream &O);
84 void printAddSubImm(const MCInst *MI, unsigned OpNum,
85 const MCSubtargetInfo &STI, raw_ostream &O);
86 template <typename T>
87 void printLogicalImm(const MCInst *MI, unsigned OpNum,
88 const MCSubtargetInfo &STI, raw_ostream &O);
89 void printShifter(const MCInst *MI, unsigned OpNum,
90 const MCSubtargetInfo &STI, raw_ostream &O);
91 void printShiftedRegister(const MCInst *MI, unsigned OpNum,
92 const MCSubtargetInfo &STI, raw_ostream &O);
93 void printExtendedRegister(const MCInst *MI, unsigned OpNum,
94 const MCSubtargetInfo &STI, raw_ostream &O);
95 void printArithExtend(const MCInst *MI, unsigned OpNum,
96 const MCSubtargetInfo &STI, raw_ostream &O);
97 void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width,
98 char SrcRegKind, raw_ostream &O);
99 void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
100 char SrcRegKind, unsigned Width);
101 template <char SrcRegKind, unsigned Width>
102 void printMemExtend(const MCInst *MI, unsigned OpNum,
103 const MCSubtargetInfo &STI, raw_ostream &O) {
104 printMemExtend(MI, OpNum, O, SrcRegKind, Width);
105 }
106 template <bool SignedExtend, int ExtWidth, char SrcRegKind, char Suffix>
107 void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
108 const MCSubtargetInfo &STI, raw_ostream &O);
109 void printCondCode(const MCInst *MI, unsigned OpNum,
110 const MCSubtargetInfo &STI, raw_ostream &O);
111 void printInverseCondCode(const MCInst *MI, unsigned OpNum,
112 const MCSubtargetInfo &STI, raw_ostream &O);
113 void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum,
114 const MCSubtargetInfo &STI, raw_ostream &O);
115 void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
116 raw_ostream &O);
117 void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
118 raw_ostream &O);
119
120 template <int Scale>
121 void printUImm12Offset(const MCInst *MI, unsigned OpNum,
122 const MCSubtargetInfo &STI, raw_ostream &O) {
123 printUImm12Offset(MI, OpNum, Scale, O);
124 }
125
126 template <int BitWidth>
127 void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
128 const MCSubtargetInfo &STI, raw_ostream &O) {
129 printAMIndexedWB(MI, OpNum, Scale: BitWidth / 8, O);
130 }
131
132 void printAMNoIndex(const MCInst *MI, unsigned OpNum,
133 const MCSubtargetInfo &STI, raw_ostream &O);
134
135 template <int Scale>
136 void printImmScale(const MCInst *MI, unsigned OpNum,
137 const MCSubtargetInfo &STI, raw_ostream &O);
138
139 template <int Scale, int Offset>
140 void printImmRangeScale(const MCInst *MI, unsigned OpNum,
141 const MCSubtargetInfo &STI, raw_ostream &O);
142
143 template <bool IsSVEPrefetch = false>
144 void printPrefetchOp(const MCInst *MI, unsigned OpNum,
145 const MCSubtargetInfo &STI, raw_ostream &O);
146
147 void printRPRFMOperand(const MCInst *MI, unsigned OpNum,
148 const MCSubtargetInfo &STI, raw_ostream &O);
149
150 void printPSBHintOp(const MCInst *MI, unsigned OpNum,
151 const MCSubtargetInfo &STI, raw_ostream &O);
152
153 void printBTIHintOp(const MCInst *MI, unsigned OpNum,
154 const MCSubtargetInfo &STI, raw_ostream &O);
155
156 void printCMHPriorityHintOp(const MCInst *MI, unsigned OpNum,
157 const MCSubtargetInfo &STI, raw_ostream &O);
158
159 void printTIndexHintOp(const MCInst *MI, unsigned OpNum,
160 const MCSubtargetInfo &STI, raw_ostream &O);
161
162 void printFPImmOperand(const MCInst *MI, unsigned OpNum,
163 const MCSubtargetInfo &STI, raw_ostream &O);
164
165 void printVectorList(const MCInst *MI, unsigned OpNum,
166 const MCSubtargetInfo &STI, raw_ostream &O,
167 StringRef LayoutSuffix);
168
169 void printMatrixTileList(const MCInst *MI, unsigned OpNum,
170 const MCSubtargetInfo &STI, raw_ostream &O);
171
172 /// Print a list of vector registers where the type suffix is implicit
173 /// (i.e. attached to the instruction rather than the registers).
174 void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
175 const MCSubtargetInfo &STI,
176 raw_ostream &O);
177
178 template <unsigned NumLanes, char LaneKind>
179 void printTypedVectorList(const MCInst *MI, unsigned OpNum,
180 const MCSubtargetInfo &STI, raw_ostream &O);
181
182 template <unsigned Scale = 1>
183 void printVectorIndex(const MCInst *MI, unsigned OpNum,
184 const MCSubtargetInfo &STI, raw_ostream &O);
185 template <unsigned Scale = 1>
186 void printMatrixIndex(const MCInst *MI, unsigned OpNum,
187 const MCSubtargetInfo &STI, raw_ostream &O);
188 void printAdrAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum,
189 const MCSubtargetInfo &STI, raw_ostream &O);
190 void printBarrierOption(const MCInst *MI, unsigned OpNum,
191 const MCSubtargetInfo &STI, raw_ostream &O);
192 void printBarriernXSOption(const MCInst *MI, unsigned OpNum,
193 const MCSubtargetInfo &STI, raw_ostream &O);
194 void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
195 const MCSubtargetInfo &STI, raw_ostream &O);
196 void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
197 const MCSubtargetInfo &STI, raw_ostream &O);
198 void printSystemPStateField(const MCInst *MI, unsigned OpNum,
199 const MCSubtargetInfo &STI, raw_ostream &O);
200 void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
201 const MCSubtargetInfo &STI, raw_ostream &O);
202 template <int EltSize>
203 void printPredicateAsCounter(const MCInst *MI, unsigned OpNum,
204 const MCSubtargetInfo &STI, raw_ostream &O);
205 template<int64_t Angle, int64_t Remainder>
206 void printComplexRotationOp(const MCInst *MI, unsigned OpNo,
207 const MCSubtargetInfo &STI, raw_ostream &O);
208 template<unsigned size>
209 void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
210 const MCSubtargetInfo &STI,
211 raw_ostream &O);
212 template <typename T>
213 void printImm8OptLsl(const MCInst *MI, unsigned OpNum,
214 const MCSubtargetInfo &STI, raw_ostream &O);
215 template <typename T>
216 void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
217 const MCSubtargetInfo &STI, raw_ostream &O);
218 void printSVEPattern(const MCInst *MI, unsigned OpNum,
219 const MCSubtargetInfo &STI, raw_ostream &O);
220 void printSVEVecLenSpecifier(const MCInst *MI, unsigned OpNum,
221 const MCSubtargetInfo &STI, raw_ostream &O);
222
223 template <bool IsVertical>
224 void printMatrixTileVector(const MCInst *MI, unsigned OpNum,
225 const MCSubtargetInfo &STI, raw_ostream &O);
226 void printMatrixTile(const MCInst *MI, unsigned OpNum,
227 const MCSubtargetInfo &STI, raw_ostream &O);
228 template <int EltSize>
229 void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
230 raw_ostream &O);
231 void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
232 raw_ostream &O);
233 template <char = 0>
234 void printSVERegOp(const MCInst *MI, unsigned OpNum,
235 const MCSubtargetInfo &STI, raw_ostream &O);
236 void printGPR64as32(const MCInst *MI, unsigned OpNum,
237 const MCSubtargetInfo &STI, raw_ostream &O);
238 void printGPR64x8(const MCInst *MI, unsigned OpNum,
239 const MCSubtargetInfo &STI, raw_ostream &O);
240 void printSyspXzrPair(const MCInst *MI, unsigned OpNum,
241 const MCSubtargetInfo &STI, raw_ostream &O);
242 template <int Width>
243 void printZPRasFPR(const MCInst *MI, unsigned OpNum,
244 const MCSubtargetInfo &STI, raw_ostream &O);
245 template <unsigned ImmIs0, unsigned ImmIs1>
246 void printExactFPImm(const MCInst *MI, unsigned OpNum,
247 const MCSubtargetInfo &STI, raw_ostream &O);
248 void printPHintOp(const MCInst *MI, unsigned OpNum,
249 const MCSubtargetInfo &STI, raw_ostream &O);
250};
251
252class AArch64AppleInstPrinter : public AArch64InstPrinter {
253public:
254 AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
255 const MCRegisterInfo &MRI);
256
257 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
258 const MCSubtargetInfo &STI, raw_ostream &O) override;
259
260 std::pair<const char *, uint64_t>
261 getMnemonic(const MCInst &MI) const override;
262 void printInstruction(const MCInst *MI, uint64_t Address,
263 const MCSubtargetInfo &STI, raw_ostream &O) override;
264 bool printAliasInstr(const MCInst *MI, uint64_t Address,
265 const MCSubtargetInfo &STI, raw_ostream &O) override;
266 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
267 unsigned OpIdx, unsigned PrintMethodIdx,
268 const MCSubtargetInfo &STI,
269 raw_ostream &O) override;
270
271 StringRef getRegName(MCRegister Reg) const override;
272
273 static const char *getRegisterName(MCRegister Reg,
274 unsigned AltIdx = AArch64::NoRegAltName);
275};
276
277} // end namespace llvm
278
279#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
280