1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
20 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
21bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
23 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
24bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT,
25 MVT LocVT, CCValAssign::LocInfo LocInfo,
26 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
27bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
28 MVT LocVT, CCValAssign::LocInfo LocInfo,
29 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
30bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
31 MVT LocVT, CCValAssign::LocInfo LocInfo,
32 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
33bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
34 MVT LocVT, CCValAssign::LocInfo LocInfo,
35 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
36static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
37 MVT LocVT, CCValAssign::LocInfo LocInfo,
38 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
39bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
40 MVT LocVT, CCValAssign::LocInfo LocInfo,
41 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
42bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT,
43 MVT LocVT, CCValAssign::LocInfo LocInfo,
44 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
45bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
46 MVT LocVT, CCValAssign::LocInfo LocInfo,
47 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
48
49
50bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
53
54 if (ArgFlags.isByVal()) {
55 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
56 return false;
57 }
58
59 if (ArgFlags.isNest()) {
60 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R12)) {
61 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
62 return false;
63 }
64 }
65
66 if (LocVT == MVT::v1i64 ||
67 LocVT == MVT::v2i32 ||
68 LocVT == MVT::v4i16 ||
69 LocVT == MVT::v4f16 ||
70 LocVT == MVT::v4bf16 ||
71 LocVT == MVT::v8i8 ||
72 LocVT == MVT::v2f32) {
73 LocVT = MVT::f64;
74 LocInfo = CCValAssign::BCvt;
75 }
76
77 if (LocVT == MVT::v2i64 ||
78 LocVT == MVT::v4i32 ||
79 LocVT == MVT::v8i16 ||
80 LocVT == MVT::v8f16 ||
81 LocVT == MVT::v8bf16 ||
82 LocVT == MVT::v16i8 ||
83 LocVT == MVT::v4f32) {
84 LocVT = MVT::v2f64;
85 LocInfo = CCValAssign::BCvt;
86 }
87
88 if (ArgFlags.isSwiftSelf()) {
89 if (LocVT == MVT::i32) {
90 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
91 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
92 return false;
93 }
94 }
95 }
96
97 if (ArgFlags.isSwiftError()) {
98 if (LocVT == MVT::i32) {
99 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
100 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
101 return false;
102 }
103 }
104 }
105
106 if (LocVT == MVT::f64 ||
107 LocVT == MVT::v2f64) {
108 if (CC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
109 return false;
110 }
111
112 if (LocVT == MVT::f32) {
113 LocVT = MVT::i32;
114 LocInfo = CCValAssign::BCvt;
115 }
116
117 if (LocVT == MVT::f16 ||
118 LocVT == MVT::bf16) {
119 if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
120 return false;
121 }
122
123 if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
124 return false;
125
126 return true; // CC didn't match.
127}
128
129
130static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
131 MVT LocVT, CCValAssign::LocInfo LocInfo,
132 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
133
134 if (LocVT == MVT::i1 ||
135 LocVT == MVT::i8 ||
136 LocVT == MVT::i16) {
137 LocVT = MVT::i32;
138 if (ArgFlags.isSExt())
139 LocInfo = CCValAssign::SExt;
140 else if (ArgFlags.isZExt())
141 LocInfo = CCValAssign::ZExt;
142 else
143 LocInfo = CCValAssign::AExt;
144 }
145
146 if (LocVT == MVT::i32) {
147 if (ArgFlags.getNonZeroOrigAlign() == 8) {
148 static const MCPhysReg RegList1[] = {
149 ARM::R0, ARM::R2
150 };
151 static const MCPhysReg RegList2[] = {
152 ARM::R0, ARM::R1
153 };
154 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
155 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
156 return false;
157 }
158 }
159 }
160
161 if (LocVT == MVT::i32) {
162 if (ArgFlags.getNonZeroOrigAlign() != Align(8)) {
163 static const MCPhysReg RegList3[] = {
164 ARM::R0, ARM::R1, ARM::R2, ARM::R3
165 };
166 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
167 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
168 return false;
169 }
170 }
171 }
172
173 if (LocVT == MVT::i32) {
174 if (ArgFlags.getNonZeroOrigAlign() == 8) {
175 static const MCPhysReg ShadowRegList4[] = {
176 ARM::R0, ARM::R1, ARM::R2, ARM::R3
177 };
178 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(8), ShadowRegs: ShadowRegList4);
179 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
180 return false;
181 }
182 }
183
184 if (LocVT == MVT::i32) {
185 static const MCPhysReg ShadowRegList6[] = {
186 ARM::R0, ARM::R1, ARM::R2, ARM::R3
187 };
188 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList6);
189 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
190 return false;
191 }
192
193 if (LocVT == MVT::f32) {
194 static const MCPhysReg ShadowRegList8[] = {
195 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
196 };
197 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList8);
198 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
199 return false;
200 }
201
202 if (LocVT == MVT::f16 ||
203 LocVT == MVT::bf16) {
204 if (CC_ARM_AAPCS_Common_Custom_f16_Stack(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
205 return false;
206 }
207
208 if (LocVT == MVT::f64) {
209 static const MCPhysReg ShadowRegList10[] = {
210 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
211 };
212 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8), ShadowRegs: ShadowRegList10);
213 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
214 return false;
215 }
216
217 if (LocVT == MVT::v2f64) {
218 if (ArgFlags.getNonZeroOrigAlign() == 16) {
219 static const MCPhysReg ShadowRegList12[] = {
220 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
221 };
222 int64_t Offset13 = State.AllocateStack(Size: 16, Alignment: Align(16), ShadowRegs: ShadowRegList12);
223 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
224 return false;
225 }
226 }
227
228 if (LocVT == MVT::v2f64) {
229 static const MCPhysReg ShadowRegList14[] = {
230 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
231 };
232 int64_t Offset15 = State.AllocateStack(Size: 16, Alignment: Align(8), ShadowRegs: ShadowRegList14);
233 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
234 return false;
235 }
236
237 return true; // CC didn't match.
238}
239
240
241bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
242 MVT LocVT, CCValAssign::LocInfo LocInfo,
243 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
244
245 if (ArgFlags.isByVal()) {
246 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
247 return false;
248 }
249
250 if (LocVT == MVT::v1i64 ||
251 LocVT == MVT::v2i32 ||
252 LocVT == MVT::v4i16 ||
253 LocVT == MVT::v4f16 ||
254 LocVT == MVT::v4bf16 ||
255 LocVT == MVT::v8i8 ||
256 LocVT == MVT::v2f32) {
257 LocVT = MVT::f64;
258 LocInfo = CCValAssign::BCvt;
259 }
260
261 if (LocVT == MVT::v2i64 ||
262 LocVT == MVT::v4i32 ||
263 LocVT == MVT::v8i16 ||
264 LocVT == MVT::v8f16 ||
265 LocVT == MVT::v8bf16 ||
266 LocVT == MVT::v16i8 ||
267 LocVT == MVT::v4f32) {
268 LocVT = MVT::v2f64;
269 LocInfo = CCValAssign::BCvt;
270 }
271
272 if (ArgFlags.isSwiftSelf()) {
273 if (LocVT == MVT::i32) {
274 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
275 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
276 return false;
277 }
278 }
279 }
280
281 if (ArgFlags.isSwiftError()) {
282 if (LocVT == MVT::i32) {
283 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
284 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
285 return false;
286 }
287 }
288 }
289
290 if (ArgFlags.isInConsecutiveRegs()) {
291 if (CC_ARM_AAPCS_Custom_Aggregate(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
292 return false;
293 }
294
295 if (LocVT == MVT::v2f64) {
296 static const MCPhysReg RegList1[] = {
297 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
298 };
299 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
300 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
301 return false;
302 }
303 }
304
305 if (LocVT == MVT::f64) {
306 static const MCPhysReg RegList2[] = {
307 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
308 };
309 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
310 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
311 return false;
312 }
313 }
314
315 if (LocVT == MVT::f32) {
316 static const MCPhysReg RegList3[] = {
317 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
318 };
319 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
320 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
321 return false;
322 }
323 }
324
325 if (LocVT == MVT::f16 ||
326 LocVT == MVT::bf16) {
327 if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
328 return false;
329 }
330
331 if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
332 return false;
333
334 return true; // CC didn't match.
335}
336
337
338bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT,
339 MVT LocVT, CCValAssign::LocInfo LocInfo,
340 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
341
342 if (ArgFlags.isByVal()) {
343 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
344 return false;
345 }
346
347 if (LocVT == MVT::i1 ||
348 LocVT == MVT::i8 ||
349 LocVT == MVT::i16) {
350 LocVT = MVT::i32;
351 if (ArgFlags.isSExt())
352 LocInfo = CCValAssign::SExt;
353 else if (ArgFlags.isZExt())
354 LocInfo = CCValAssign::ZExt;
355 else
356 LocInfo = CCValAssign::AExt;
357 }
358
359 if (ArgFlags.isSwiftSelf()) {
360 if (LocVT == MVT::i32) {
361 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
362 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
363 return false;
364 }
365 }
366 }
367
368 if (ArgFlags.isSwiftError()) {
369 if (LocVT == MVT::i32) {
370 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
371 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
372 return false;
373 }
374 }
375 }
376
377 if (LocVT == MVT::v1i64 ||
378 LocVT == MVT::v2i32 ||
379 LocVT == MVT::v4i16 ||
380 LocVT == MVT::v4f16 ||
381 LocVT == MVT::v4bf16 ||
382 LocVT == MVT::v8i8 ||
383 LocVT == MVT::v2f32) {
384 LocVT = MVT::f64;
385 LocInfo = CCValAssign::BCvt;
386 }
387
388 if (LocVT == MVT::v2i64 ||
389 LocVT == MVT::v4i32 ||
390 LocVT == MVT::v8i16 ||
391 LocVT == MVT::v8f16 ||
392 LocVT == MVT::v8bf16 ||
393 LocVT == MVT::v16i8 ||
394 LocVT == MVT::v4f32) {
395 LocVT = MVT::v2f64;
396 LocInfo = CCValAssign::BCvt;
397 }
398
399 if (LocVT == MVT::f64 ||
400 LocVT == MVT::v2f64) {
401 if (CC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
402 return false;
403 }
404
405 if (LocVT == MVT::f32) {
406 LocVT = MVT::i32;
407 LocInfo = CCValAssign::BCvt;
408 }
409
410 if (LocVT == MVT::i32) {
411 static const MCPhysReg RegList1[] = {
412 ARM::R0, ARM::R1, ARM::R2, ARM::R3
413 };
414 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
415 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
416 return false;
417 }
418 }
419
420 if (LocVT == MVT::i32) {
421 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
422 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
423 return false;
424 }
425
426 if (LocVT == MVT::f64) {
427 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(4));
428 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
429 return false;
430 }
431
432 if (LocVT == MVT::v2f64) {
433 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(4));
434 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
435 return false;
436 }
437
438 return true; // CC didn't match.
439}
440
441
442bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT,
443 MVT LocVT, CCValAssign::LocInfo LocInfo,
444 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
445
446 if (LocVT == MVT::v1i64 ||
447 LocVT == MVT::v2i32 ||
448 LocVT == MVT::v4i16 ||
449 LocVT == MVT::v4f16 ||
450 LocVT == MVT::v4bf16 ||
451 LocVT == MVT::v8i8 ||
452 LocVT == MVT::v2f32) {
453 LocVT = MVT::f64;
454 LocInfo = CCValAssign::BCvt;
455 }
456
457 if (LocVT == MVT::v2i64 ||
458 LocVT == MVT::v4i32 ||
459 LocVT == MVT::v8i16 ||
460 LocVT == MVT::v8f16 ||
461 LocVT == MVT::v8bf16 ||
462 LocVT == MVT::v16i8 ||
463 LocVT == MVT::v4f32) {
464 LocVT = MVT::v2f64;
465 LocInfo = CCValAssign::BCvt;
466 }
467
468 if (LocVT == MVT::v2f64) {
469 static const MCPhysReg RegList1[] = {
470 ARM::Q4, ARM::Q5
471 };
472 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
473 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
474 return false;
475 }
476 }
477
478 if (LocVT == MVT::f64) {
479 static const MCPhysReg RegList2[] = {
480 ARM::D8, ARM::D9, ARM::D10, ARM::D11
481 };
482 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
483 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
484 return false;
485 }
486 }
487
488 if (LocVT == MVT::f32) {
489 static const MCPhysReg RegList3[] = {
490 ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23
491 };
492 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
493 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
494 return false;
495 }
496 }
497
498 if (LocVT == MVT::i8 ||
499 LocVT == MVT::i16) {
500 LocVT = MVT::i32;
501 if (ArgFlags.isSExt())
502 LocInfo = CCValAssign::SExt;
503 else if (ArgFlags.isZExt())
504 LocInfo = CCValAssign::ZExt;
505 else
506 LocInfo = CCValAssign::AExt;
507 }
508
509 if (LocVT == MVT::i32) {
510 static const MCPhysReg RegList4[] = {
511 ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11
512 };
513 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
514 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
515 return false;
516 }
517 }
518
519 return true; // CC didn't match.
520}
521
522
523bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
524 MVT LocVT, CCValAssign::LocInfo LocInfo,
525 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
526
527 if (LocVT == MVT::i32) {
528 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R0)) {
529 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
530 return false;
531 }
532 }
533
534 return true; // CC didn't match.
535}
536
537
538bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
539 MVT LocVT, CCValAssign::LocInfo LocInfo,
540 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
541
542 if (LocVT == MVT::v1i64 ||
543 LocVT == MVT::v2i32 ||
544 LocVT == MVT::v4i16 ||
545 LocVT == MVT::v4f16 ||
546 LocVT == MVT::v4bf16 ||
547 LocVT == MVT::v8i8 ||
548 LocVT == MVT::v2f32) {
549 LocVT = MVT::f64;
550 LocInfo = CCValAssign::BCvt;
551 }
552
553 if (LocVT == MVT::v2i64 ||
554 LocVT == MVT::v4i32 ||
555 LocVT == MVT::v8i16 ||
556 LocVT == MVT::v8f16 ||
557 LocVT == MVT::v8bf16 ||
558 LocVT == MVT::v16i8 ||
559 LocVT == MVT::v4f32) {
560 LocVT = MVT::v2f64;
561 LocInfo = CCValAssign::BCvt;
562 }
563
564 if (LocVT == MVT::v2f64) {
565 static const MCPhysReg RegList1[] = {
566 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
567 };
568 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
569 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
570 return false;
571 }
572 }
573
574 if (LocVT == MVT::f64) {
575 static const MCPhysReg RegList2[] = {
576 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
577 };
578 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
579 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
580 return false;
581 }
582 }
583
584 if (LocVT == MVT::f32) {
585 static const MCPhysReg RegList3[] = {
586 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
587 };
588 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
589 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
590 return false;
591 }
592 }
593
594 if (LocVT == MVT::f32) {
595 static const MCPhysReg ShadowRegList4[] = {
596 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
597 };
598 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList4);
599 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
600 return false;
601 }
602
603 if (LocVT == MVT::f64) {
604 static const MCPhysReg ShadowRegList6[] = {
605 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
606 };
607 int64_t Offset7 = State.AllocateStack(Size: 8, Alignment: Align(4), ShadowRegs: ShadowRegList6);
608 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
609 return false;
610 }
611
612 if (LocVT == MVT::v2f64) {
613 static const MCPhysReg ShadowRegList8[] = {
614 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
615 };
616 int64_t Offset9 = State.AllocateStack(Size: 16, Alignment: Align(4), ShadowRegs: ShadowRegList8);
617 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
618 return false;
619 }
620
621 if (!CC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
622 return false;
623
624 return true; // CC didn't match.
625}
626
627
628bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
629 MVT LocVT, CCValAssign::LocInfo LocInfo,
630 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
631
632 if (LocVT == MVT::v1i64 ||
633 LocVT == MVT::v2i32 ||
634 LocVT == MVT::v4i16 ||
635 LocVT == MVT::v4f16 ||
636 LocVT == MVT::v4bf16 ||
637 LocVT == MVT::v8i8 ||
638 LocVT == MVT::v2f32) {
639 LocVT = MVT::f64;
640 LocInfo = CCValAssign::BCvt;
641 }
642
643 if (LocVT == MVT::v2i64 ||
644 LocVT == MVT::v4i32 ||
645 LocVT == MVT::v8i16 ||
646 LocVT == MVT::v8f16 ||
647 LocVT == MVT::v8bf16 ||
648 LocVT == MVT::v16i8 ||
649 LocVT == MVT::v4f32) {
650 LocVT = MVT::v2f64;
651 LocInfo = CCValAssign::BCvt;
652 }
653
654 if (ArgFlags.isSwiftSelf()) {
655 if (LocVT == MVT::i32) {
656 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
657 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
658 return false;
659 }
660 }
661 }
662
663 if (ArgFlags.isSwiftError()) {
664 if (LocVT == MVT::i32) {
665 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
666 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
667 return false;
668 }
669 }
670 }
671
672 if (LocVT == MVT::f64 ||
673 LocVT == MVT::v2f64) {
674 if (RetCC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
675 return false;
676 }
677
678 if (LocVT == MVT::f32) {
679 LocVT = MVT::i32;
680 LocInfo = CCValAssign::BCvt;
681 }
682
683 if (LocVT == MVT::f16 ||
684 LocVT == MVT::bf16) {
685 if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
686 return false;
687 }
688
689 if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
690 return false;
691
692 return true; // CC didn't match.
693}
694
695
696static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
697 MVT LocVT, CCValAssign::LocInfo LocInfo,
698 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
699
700 if (LocVT == MVT::i1 ||
701 LocVT == MVT::i8 ||
702 LocVT == MVT::i16) {
703 LocVT = MVT::i32;
704 if (ArgFlags.isSExt())
705 LocInfo = CCValAssign::SExt;
706 else if (ArgFlags.isZExt())
707 LocInfo = CCValAssign::ZExt;
708 else
709 LocInfo = CCValAssign::AExt;
710 }
711
712 if (LocVT == MVT::i32) {
713 static const MCPhysReg RegList1[] = {
714 ARM::R0, ARM::R1, ARM::R2, ARM::R3
715 };
716 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
717 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
718 return false;
719 }
720 }
721
722 if (LocVT == MVT::i64) {
723 static const MCPhysReg RegList2[] = {
724 ARM::R0, ARM::R2
725 };
726 static const MCPhysReg RegList3[] = {
727 ARM::R1, ARM::R3
728 };
729 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
730 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
731 return false;
732 }
733 }
734
735 return true; // CC didn't match.
736}
737
738
739bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
740 MVT LocVT, CCValAssign::LocInfo LocInfo,
741 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
742
743 if (LocVT == MVT::v1i64 ||
744 LocVT == MVT::v2i32 ||
745 LocVT == MVT::v4i16 ||
746 LocVT == MVT::v4f16 ||
747 LocVT == MVT::v4bf16 ||
748 LocVT == MVT::v8i8 ||
749 LocVT == MVT::v2f32) {
750 LocVT = MVT::f64;
751 LocInfo = CCValAssign::BCvt;
752 }
753
754 if (LocVT == MVT::v2i64 ||
755 LocVT == MVT::v4i32 ||
756 LocVT == MVT::v8i16 ||
757 LocVT == MVT::v8f16 ||
758 LocVT == MVT::v8bf16 ||
759 LocVT == MVT::v16i8 ||
760 LocVT == MVT::v4f32) {
761 LocVT = MVT::v2f64;
762 LocInfo = CCValAssign::BCvt;
763 }
764
765 if (ArgFlags.isSwiftSelf()) {
766 if (LocVT == MVT::i32) {
767 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
768 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
769 return false;
770 }
771 }
772 }
773
774 if (ArgFlags.isSwiftError()) {
775 if (LocVT == MVT::i32) {
776 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
777 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
778 return false;
779 }
780 }
781 }
782
783 if (LocVT == MVT::v2f64) {
784 static const MCPhysReg RegList1[] = {
785 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
786 };
787 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
788 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
789 return false;
790 }
791 }
792
793 if (LocVT == MVT::f64) {
794 static const MCPhysReg RegList2[] = {
795 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
796 };
797 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
798 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
799 return false;
800 }
801 }
802
803 if (LocVT == MVT::f32) {
804 static const MCPhysReg RegList3[] = {
805 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
806 };
807 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
808 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
809 return false;
810 }
811 }
812
813 if (LocVT == MVT::f16 ||
814 LocVT == MVT::bf16) {
815 if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
816 return false;
817 }
818
819 if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
820 return false;
821
822 return true; // CC didn't match.
823}
824
825
826bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT,
827 MVT LocVT, CCValAssign::LocInfo LocInfo,
828 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
829
830 if (LocVT == MVT::i1 ||
831 LocVT == MVT::i8 ||
832 LocVT == MVT::i16) {
833 LocVT = MVT::i32;
834 if (ArgFlags.isSExt())
835 LocInfo = CCValAssign::SExt;
836 else if (ArgFlags.isZExt())
837 LocInfo = CCValAssign::ZExt;
838 else
839 LocInfo = CCValAssign::AExt;
840 }
841
842 if (LocVT == MVT::f32) {
843 LocVT = MVT::i32;
844 LocInfo = CCValAssign::BCvt;
845 }
846
847 if (ArgFlags.isSwiftSelf()) {
848 if (LocVT == MVT::i32) {
849 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
850 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
851 return false;
852 }
853 }
854 }
855
856 if (ArgFlags.isSwiftError()) {
857 if (LocVT == MVT::i32) {
858 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
859 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
860 return false;
861 }
862 }
863 }
864
865 if (LocVT == MVT::v1i64 ||
866 LocVT == MVT::v2i32 ||
867 LocVT == MVT::v4i16 ||
868 LocVT == MVT::v4f16 ||
869 LocVT == MVT::v4bf16 ||
870 LocVT == MVT::v8i8 ||
871 LocVT == MVT::v2f32) {
872 LocVT = MVT::f64;
873 LocInfo = CCValAssign::BCvt;
874 }
875
876 if (LocVT == MVT::v2i64 ||
877 LocVT == MVT::v4i32 ||
878 LocVT == MVT::v8i16 ||
879 LocVT == MVT::v8f16 ||
880 LocVT == MVT::v8bf16 ||
881 LocVT == MVT::v16i8 ||
882 LocVT == MVT::v4f32) {
883 LocVT = MVT::v2f64;
884 LocInfo = CCValAssign::BCvt;
885 }
886
887 if (LocVT == MVT::f64 ||
888 LocVT == MVT::v2f64) {
889 if (RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
890 return false;
891 }
892
893 if (LocVT == MVT::i32) {
894 static const MCPhysReg RegList1[] = {
895 ARM::R0, ARM::R1, ARM::R2, ARM::R3
896 };
897 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
898 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
899 return false;
900 }
901 }
902
903 if (LocVT == MVT::i64) {
904 static const MCPhysReg RegList2[] = {
905 ARM::R0, ARM::R2
906 };
907 static const MCPhysReg RegList3[] = {
908 ARM::R1, ARM::R3
909 };
910 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
911 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
912 return false;
913 }
914 }
915
916 return true; // CC didn't match.
917}
918
919
920bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
921 MVT LocVT, CCValAssign::LocInfo LocInfo,
922 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
923
924 if (LocVT == MVT::v1i64 ||
925 LocVT == MVT::v2i32 ||
926 LocVT == MVT::v4i16 ||
927 LocVT == MVT::v4f16 ||
928 LocVT == MVT::v4bf16 ||
929 LocVT == MVT::v8i8 ||
930 LocVT == MVT::v2f32) {
931 LocVT = MVT::f64;
932 LocInfo = CCValAssign::BCvt;
933 }
934
935 if (LocVT == MVT::v2i64 ||
936 LocVT == MVT::v4i32 ||
937 LocVT == MVT::v8i16 ||
938 LocVT == MVT::v8f16 ||
939 LocVT == MVT::v8bf16 ||
940 LocVT == MVT::v16i8 ||
941 LocVT == MVT::v4f32) {
942 LocVT = MVT::v2f64;
943 LocInfo = CCValAssign::BCvt;
944 }
945
946 if (LocVT == MVT::v2f64) {
947 static const MCPhysReg RegList1[] = {
948 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
949 };
950 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
951 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
952 return false;
953 }
954 }
955
956 if (LocVT == MVT::f64) {
957 static const MCPhysReg RegList2[] = {
958 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
959 };
960 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
961 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
962 return false;
963 }
964 }
965
966 if (LocVT == MVT::f32) {
967 static const MCPhysReg RegList3[] = {
968 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
969 };
970 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
971 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
972 return false;
973 }
974 }
975
976 if (!RetCC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State))
977 return false;
978
979 return true; // CC didn't match.
980}
981
982#endif // GET_CALLING_CONV_IMPL
983
984#ifdef GET_CC_REGISTER_LISTS
985#undef GET_CC_REGISTER_LISTS
986
987const MCRegister CC_ARM_AAPCS_ArgRegs[] = { ARM::R12 };
988const MCRegister CC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
989const MCRegister CC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
990const MCRegister CC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
991const MCRegister CC_ARM_APCS_GHC_ArgRegs[] = { ARM::D10, ARM::D11, ARM::D8, ARM::D9, ARM::Q4, ARM::Q5, ARM::R10, ARM::R11, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23 };
992const MCRegister CC_ARM_Win32_CFGuard_Check_ArgRegs[] = { ARM::R0 };
993const MCRegister FastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
994const MCRegister RetCC_ARM_AAPCS_ArgRegs[] = { 0 };
995const MCRegister RetCC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
996const MCRegister RetCC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
997const MCRegister RetCC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
998const MCRegister RetFastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
999
1000// Registers used by Swift.
1001const MCRegister CC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1002const MCRegister CC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1003const MCRegister CC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1004const MCRegister RetCC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1005const MCRegister RetCC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1006const MCRegister RetCC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1007
1008#endif // GET_CC_REGISTER_LISTS
1009
1010