1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the ARM target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11const unsigned MAX_SUBTARGET_PREDICATES = 82;
12using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18 mutable MatcherState State;
19 typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
20 typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
21 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22 static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23 static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
24 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27 const uint8_t *getMatchTable() const override;
28 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30 bool testSimplePredicate(unsigned PredicateID) const override;
31 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37, State(0),
38ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42#ifdef GET_GLOBALISEL_IMPL
43
44// LLT Objects.
45enum {
46 GILLT_s16,
47 GILLT_s32,
48 GILLT_s64,
49 GILLT_v2s1,
50 GILLT_v4s1,
51 GILLT_v8s1,
52 GILLT_v16s1,
53 GILLT_v8s8,
54 GILLT_v16s8,
55 GILLT_v4s16,
56 GILLT_v8s16,
57 GILLT_v2s32,
58 GILLT_v4s32,
59 GILLT_v2s64,
60 GILLT_v4s64,
61 GILLT_v8s64,
62};
63const static size_t NumTypeObjects = 16;
64const static LLT TypeObjects[] = {
65 LLT::scalar(16),
66 LLT::scalar(32),
67 LLT::scalar(64),
68 LLT::vector(ElementCount::getFixed(2), LLT::scalar(1)),
69 LLT::vector(ElementCount::getFixed(4), LLT::scalar(1)),
70 LLT::vector(ElementCount::getFixed(8), LLT::scalar(1)),
71 LLT::vector(ElementCount::getFixed(16), LLT::scalar(1)),
72 LLT::vector(ElementCount::getFixed(8), LLT::scalar(8)),
73 LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)),
74 LLT::vector(ElementCount::getFixed(4), LLT::scalar(16)),
75 LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)),
76 LLT::vector(ElementCount::getFixed(2), LLT::scalar(32)),
77 LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)),
78 LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)),
79 LLT::vector(ElementCount::getFixed(4), LLT::scalar(64)),
80 LLT::vector(ElementCount::getFixed(8), LLT::scalar(64)),
81};
82
83// Bits for subtarget features that participate in instruction matching.
84enum SubtargetFeatureBits : uint8_t {
85 Feature_HasV4TBit = 4,
86 Feature_NoV4TBit = 5,
87 Feature_HasV5TBit = 11,
88 Feature_NoV5TBit = 63,
89 Feature_HasV5TEBit = 9,
90 Feature_HasV6Bit = 0,
91 Feature_NoV6Bit = 7,
92 Feature_HasV6MBit = 26,
93 Feature_HasV8MBaselineBit = 33,
94 Feature_HasV8_1MMainlineBit = 39,
95 Feature_HasMVEIntBit = 61,
96 Feature_HasMVEFloatBit = 62,
97 Feature_HasCDEBit = 81,
98 Feature_HasFPRegsBit = 40,
99 Feature_HasFPRegs16Bit = 41,
100 Feature_HasFPRegs64Bit = 73,
101 Feature_HasV6T2Bit = 6,
102 Feature_HasV6KBit = 16,
103 Feature_HasV7Bit = 3,
104 Feature_HasV8Bit = 53,
105 Feature_PreV8Bit = 17,
106 Feature_HasV8_1aBit = 75,
107 Feature_HasV8_3aBit = 76,
108 Feature_NoVFPBit = 20,
109 Feature_HasVFP2Bit = 19,
110 Feature_HasVFP3Bit = 50,
111 Feature_HasVFP4Bit = 48,
112 Feature_HasDPVFPBit = 42,
113 Feature_HasFPARMv8Bit = 45,
114 Feature_HasNEONBit = 51,
115 Feature_HasSHA2Bit = 60,
116 Feature_HasAESBit = 52,
117 Feature_HasDotProdBit = 54,
118 Feature_HasCRCBit = 12,
119 Feature_HasLOBBit = 38,
120 Feature_HasFP16Bit = 59,
121 Feature_HasFullFP16Bit = 44,
122 Feature_HasMatMulInt8Bit = 55,
123 Feature_HasDivideInThumbBit = 35,
124 Feature_HasDivideInARMBit = 10,
125 Feature_HasDSPBit = 34,
126 Feature_HasDBBit = 13,
127 Feature_HasV7ClrexBit = 15,
128 Feature_HasAcquireReleaseBit = 14,
129 Feature_HasMPBit = 2,
130 Feature_Has8MSecExtBit = 27,
131 Feature_HasZCZBit = 56,
132 Feature_UseNEONForFPBit = 79,
133 Feature_DontUseNEONForFPBit = 43,
134 Feature_IsThumbBit = 24,
135 Feature_IsThumb1OnlyBit = 25,
136 Feature_IsThumb2Bit = 32,
137 Feature_IsNotMClassBit = 36,
138 Feature_IsARMBit = 1,
139 Feature_IsWindowsBit = 28,
140 Feature_IsNotWindowsBit = 29,
141 Feature_IsReadTPTPIDRURWBit = 66,
142 Feature_IsReadTPTPIDRUROBit = 67,
143 Feature_IsReadTPTPIDRPRWBit = 68,
144 Feature_IsReadTPSoftBit = 18,
145 Feature_UseMovtBit = 37,
146 Feature_DontUseMovtBit = 21,
147 Feature_UseMovtInPicBit = 22,
148 Feature_DontUseMovtInPicBit = 23,
149 Feature_UseFPVMLxBit = 47,
150 Feature_SLSBLRMitigationBit = 65,
151 Feature_NoSLSBLRMitigationBit = 64,
152 Feature_UseMulOpsBit = 8,
153 Feature_UseFusedMACBit = 49,
154 Feature_HasFastVGETLNi32Bit = 57,
155 Feature_HasSlowVGETLNi32Bit = 77,
156 Feature_HasFastVDUP32Bit = 58,
157 Feature_HasSlowVDUP32Bit = 78,
158 Feature_UseVMOVSRBit = 46,
159 Feature_DontUseVMOVSRBit = 80,
160 Feature_IsLEBit = 72,
161 Feature_IsBEBit = 74,
162 Feature_GenExecuteOnlyBit = 31,
163 Feature_DontGenExecuteOnlyBit = 30,
164 Feature_GenT1ExecuteOnlyBit = 71,
165 Feature_SignRetAddrBit = 70,
166 Feature_NoSignRetAddrBit = 69,
167};
168
169PredicateBitset ARMInstructionSelector::
170computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
171 PredicateBitset Features{};
172 if (Subtarget->hasV4TOps())
173 Features.set(Feature_HasV4TBit);
174 if (!Subtarget->hasV4TOps())
175 Features.set(Feature_NoV4TBit);
176 if (Subtarget->hasV5TOps())
177 Features.set(Feature_HasV5TBit);
178 if (!Subtarget->hasV5TOps())
179 Features.set(Feature_NoV5TBit);
180 if (Subtarget->hasV5TEOps())
181 Features.set(Feature_HasV5TEBit);
182 if (Subtarget->hasV6Ops())
183 Features.set(Feature_HasV6Bit);
184 if (!Subtarget->hasV6Ops())
185 Features.set(Feature_NoV6Bit);
186 if (Subtarget->hasV6MOps())
187 Features.set(Feature_HasV6MBit);
188 if (Subtarget->hasV8MBaselineOps())
189 Features.set(Feature_HasV8MBaselineBit);
190 if (Subtarget->hasV8_1MMainlineOps())
191 Features.set(Feature_HasV8_1MMainlineBit);
192 if (Subtarget->hasMVEIntegerOps())
193 Features.set(Feature_HasMVEIntBit);
194 if (Subtarget->hasMVEFloatOps())
195 Features.set(Feature_HasMVEFloatBit);
196 if (Subtarget->hasCDEOps())
197 Features.set(Feature_HasCDEBit);
198 if (Subtarget->hasFPRegs())
199 Features.set(Feature_HasFPRegsBit);
200 if (Subtarget->hasFPRegs16())
201 Features.set(Feature_HasFPRegs16Bit);
202 if (Subtarget->hasFPRegs64())
203 Features.set(Feature_HasFPRegs64Bit);
204 if (Subtarget->hasV6T2Ops())
205 Features.set(Feature_HasV6T2Bit);
206 if (Subtarget->hasV6KOps())
207 Features.set(Feature_HasV6KBit);
208 if (Subtarget->hasV7Ops())
209 Features.set(Feature_HasV7Bit);
210 if (Subtarget->hasV8Ops())
211 Features.set(Feature_HasV8Bit);
212 if (!Subtarget->hasV8Ops())
213 Features.set(Feature_PreV8Bit);
214 if (Subtarget->hasV8_1aOps())
215 Features.set(Feature_HasV8_1aBit);
216 if (Subtarget->hasV8_3aOps())
217 Features.set(Feature_HasV8_3aBit);
218 if (!Subtarget->hasVFP2Base())
219 Features.set(Feature_NoVFPBit);
220 if (Subtarget->hasVFP2Base())
221 Features.set(Feature_HasVFP2Bit);
222 if (Subtarget->hasVFP3Base())
223 Features.set(Feature_HasVFP3Bit);
224 if (Subtarget->hasVFP4Base())
225 Features.set(Feature_HasVFP4Bit);
226 if (Subtarget->hasFP64())
227 Features.set(Feature_HasDPVFPBit);
228 if (Subtarget->hasFPARMv8Base())
229 Features.set(Feature_HasFPARMv8Bit);
230 if (Subtarget->hasNEON())
231 Features.set(Feature_HasNEONBit);
232 if (Subtarget->hasSHA2())
233 Features.set(Feature_HasSHA2Bit);
234 if (Subtarget->hasAES())
235 Features.set(Feature_HasAESBit);
236 if (Subtarget->hasDotProd())
237 Features.set(Feature_HasDotProdBit);
238 if (Subtarget->hasCRC())
239 Features.set(Feature_HasCRCBit);
240 if (Subtarget->hasLOB())
241 Features.set(Feature_HasLOBBit);
242 if (Subtarget->hasFP16())
243 Features.set(Feature_HasFP16Bit);
244 if (Subtarget->hasFullFP16())
245 Features.set(Feature_HasFullFP16Bit);
246 if (Subtarget->hasMatMulInt8())
247 Features.set(Feature_HasMatMulInt8Bit);
248 if (Subtarget->hasDivideInThumbMode())
249 Features.set(Feature_HasDivideInThumbBit);
250 if (Subtarget->hasDivideInARMMode())
251 Features.set(Feature_HasDivideInARMBit);
252 if (Subtarget->hasDSP())
253 Features.set(Feature_HasDSPBit);
254 if (Subtarget->hasDataBarrier())
255 Features.set(Feature_HasDBBit);
256 if (Subtarget->hasV7Clrex())
257 Features.set(Feature_HasV7ClrexBit);
258 if (Subtarget->hasAcquireRelease())
259 Features.set(Feature_HasAcquireReleaseBit);
260 if (Subtarget->hasMPExtension())
261 Features.set(Feature_HasMPBit);
262 if (Subtarget->has8MSecExt())
263 Features.set(Feature_Has8MSecExtBit);
264 if (Subtarget->hasZeroCycleZeroing())
265 Features.set(Feature_HasZCZBit);
266 if (Subtarget->useNEONForSinglePrecisionFP())
267 Features.set(Feature_UseNEONForFPBit);
268 if (!Subtarget->useNEONForSinglePrecisionFP())
269 Features.set(Feature_DontUseNEONForFPBit);
270 if (Subtarget->isThumb())
271 Features.set(Feature_IsThumbBit);
272 if (Subtarget->isThumb1Only())
273 Features.set(Feature_IsThumb1OnlyBit);
274 if (Subtarget->isThumb2())
275 Features.set(Feature_IsThumb2Bit);
276 if (!Subtarget->isMClass())
277 Features.set(Feature_IsNotMClassBit);
278 if (!Subtarget->isThumb())
279 Features.set(Feature_IsARMBit);
280 if (Subtarget->isTargetWindows())
281 Features.set(Feature_IsWindowsBit);
282 if (!Subtarget->isTargetWindows())
283 Features.set(Feature_IsNotWindowsBit);
284 if (Subtarget->isReadTPTPIDRURW())
285 Features.set(Feature_IsReadTPTPIDRURWBit);
286 if (Subtarget->isReadTPTPIDRURO())
287 Features.set(Feature_IsReadTPTPIDRUROBit);
288 if (Subtarget->isReadTPTPIDRPRW())
289 Features.set(Feature_IsReadTPTPIDRPRWBit);
290 if (Subtarget->isReadTPSoft())
291 Features.set(Feature_IsReadTPSoftBit);
292 if (Subtarget->useMulOps())
293 Features.set(Feature_UseMulOpsBit);
294 if (Subtarget->useFPVFMx())
295 Features.set(Feature_UseFusedMACBit);
296 if (!Subtarget->hasSlowVGETLNi32())
297 Features.set(Feature_HasFastVGETLNi32Bit);
298 if (Subtarget->hasSlowVGETLNi32())
299 Features.set(Feature_HasSlowVGETLNi32Bit);
300 if (!Subtarget->hasSlowVDUP32())
301 Features.set(Feature_HasFastVDUP32Bit);
302 if (Subtarget->hasSlowVDUP32())
303 Features.set(Feature_HasSlowVDUP32Bit);
304 if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
305 Features.set(Feature_UseVMOVSRBit);
306 if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
307 Features.set(Feature_DontUseVMOVSRBit);
308 if (Subtarget->genExecuteOnly())
309 Features.set(Feature_GenExecuteOnlyBit);
310 if (!Subtarget->genExecuteOnly())
311 Features.set(Feature_DontGenExecuteOnlyBit);
312 if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps())
313 Features.set(Feature_GenT1ExecuteOnlyBit);
314 return Features;
315}
316
317void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
318 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
319}
320PredicateBitset ARMInstructionSelector::
321computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
322 PredicateBitset Features{};
323 if (Subtarget->useMovt())
324 Features.set(Feature_UseMovtBit);
325 if (!Subtarget->useMovt())
326 Features.set(Feature_DontUseMovtBit);
327 if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
328 Features.set(Feature_UseMovtInPicBit);
329 if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
330 Features.set(Feature_DontUseMovtInPicBit);
331 if (Subtarget->useFPVMLx() || Subtarget->hasMinSize())
332 Features.set(Feature_UseFPVMLxBit);
333 if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
334 Features.set(Feature_SLSBLRMitigationBit);
335 if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
336 Features.set(Feature_NoSLSBLRMitigationBit);
337 if (MF->getDataLayout().isLittleEndian())
338 Features.set(Feature_IsLEBit);
339 if (MF->getDataLayout().isBigEndian())
340 Features.set(Feature_IsBEBit);
341 if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
342 Features.set(Feature_SignRetAddrBit);
343 if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
344 Features.set(Feature_NoSignRetAddrBit);
345 return Features;
346}
347
348// Feature bitsets.
349enum {
350 GIFBS_Invalid,
351 GIFBS_HasDPVFP,
352 GIFBS_HasDotProd,
353 GIFBS_HasFP16,
354 GIFBS_HasFPARMv8,
355 GIFBS_HasFPRegs,
356 GIFBS_HasFullFP16,
357 GIFBS_HasMVEFloat,
358 GIFBS_HasMVEInt,
359 GIFBS_HasMatMulInt8,
360 GIFBS_HasNEON,
361 GIFBS_HasVFP2,
362 GIFBS_HasVFP3,
363 GIFBS_HasVFP4,
364 GIFBS_IsARM,
365 GIFBS_IsThumb,
366 GIFBS_IsThumb2,
367 GIFBS_DontUseNEONForFP_HasVFP2,
368 GIFBS_DontUseVMOVSR_HasNEON,
369 GIFBS_Has8MSecExt_IsThumb,
370 GIFBS_HasAES_HasV8,
371 GIFBS_HasCRC_IsARM,
372 GIFBS_HasCRC_IsThumb2,
373 GIFBS_HasDB_IsARM,
374 GIFBS_HasDB_IsThumb,
375 GIFBS_HasDPVFP_HasFPARMv8,
376 GIFBS_HasDPVFP_HasVFP2,
377 GIFBS_HasDPVFP_HasVFP3,
378 GIFBS_HasDPVFP_HasVFP4,
379 GIFBS_HasDSP_IsThumb2,
380 GIFBS_HasDivideInARM_IsARM,
381 GIFBS_HasFP16_HasNEON,
382 GIFBS_HasFPARMv8_HasNEON,
383 GIFBS_HasFPRegs_HasFastVGETLNi32,
384 GIFBS_HasFPRegs_UseVMOVSR,
385 GIFBS_HasFullFP16_HasNEON,
386 GIFBS_HasMVEInt_HasV8_1MMainline,
387 GIFBS_HasMVEInt_IsBE,
388 GIFBS_HasMVEInt_IsLE,
389 GIFBS_HasNEON_HasV8,
390 GIFBS_HasNEON_HasV8_1a,
391 GIFBS_HasNEON_HasV8_3a,
392 GIFBS_HasNEON_HasVFP4,
393 GIFBS_HasNEON_IsBE,
394 GIFBS_HasNEON_IsLE,
395 GIFBS_HasNEON_UseNEONForFP,
396 GIFBS_HasSHA2_HasV8,
397 GIFBS_HasV4T_IsARM,
398 GIFBS_HasV5T_IsARM,
399 GIFBS_HasV5T_IsThumb,
400 GIFBS_HasV5TE_IsARM,
401 GIFBS_HasV6_IsARM,
402 GIFBS_HasV6K_IsARM,
403 GIFBS_HasV6M_IsThumb,
404 GIFBS_HasV6T2_IsARM,
405 GIFBS_HasV7_IsARM,
406 GIFBS_HasV7Clrex_IsThumb,
407 GIFBS_HasV8MBaseline_IsThumb,
408 GIFBS_IsARM_NoV4T,
409 GIFBS_IsARM_NoV5T,
410 GIFBS_IsARM_NoV6,
411 GIFBS_IsARM_PreV8,
412 GIFBS_IsThumb_IsThumb1Only,
413 GIFBS_IsThumb_IsWindows,
414 GIFBS_IsThumb_NoV5T,
415 GIFBS_IsThumb_UseMovt,
416 GIFBS_IsThumb2_PreV8,
417 GIFBS_IsThumb2_UseMulOps,
418 GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only,
419 GIFBS_HasDSP_IsThumb2_UseMulOps,
420 GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
421 GIFBS_HasFPARMv8_HasFullFP16_HasNEON,
422 GIFBS_HasFullFP16_HasNEON_HasV8,
423 GIFBS_HasFullFP16_HasNEON_HasV8_3a,
424 GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
425 GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
426 GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
427 GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
428 GIFBS_HasV5TE_IsARM_UseMulOps,
429 GIFBS_HasV6_IsARM_UseMulOps,
430 GIFBS_HasV6_IsThumb_IsThumb1Only,
431 GIFBS_HasV6T2_IsARM_UseMulOps,
432 GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
433 GIFBS_IsARM_NoV6_UseMulOps,
434};
435constexpr static PredicateBitset FeatureBitsets[] {
436 {}, // GIFBS_Invalid
437 {Feature_HasDPVFPBit, },
438 {Feature_HasDotProdBit, },
439 {Feature_HasFP16Bit, },
440 {Feature_HasFPARMv8Bit, },
441 {Feature_HasFPRegsBit, },
442 {Feature_HasFullFP16Bit, },
443 {Feature_HasMVEFloatBit, },
444 {Feature_HasMVEIntBit, },
445 {Feature_HasMatMulInt8Bit, },
446 {Feature_HasNEONBit, },
447 {Feature_HasVFP2Bit, },
448 {Feature_HasVFP3Bit, },
449 {Feature_HasVFP4Bit, },
450 {Feature_IsARMBit, },
451 {Feature_IsThumbBit, },
452 {Feature_IsThumb2Bit, },
453 {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
454 {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
455 {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
456 {Feature_HasAESBit, Feature_HasV8Bit, },
457 {Feature_HasCRCBit, Feature_IsARMBit, },
458 {Feature_HasCRCBit, Feature_IsThumb2Bit, },
459 {Feature_HasDBBit, Feature_IsARMBit, },
460 {Feature_HasDBBit, Feature_IsThumbBit, },
461 {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
462 {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
463 {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
464 {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
465 {Feature_HasDSPBit, Feature_IsThumb2Bit, },
466 {Feature_HasDivideInARMBit, Feature_IsARMBit, },
467 {Feature_HasFP16Bit, Feature_HasNEONBit, },
468 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, },
469 {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, },
470 {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
471 {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
472 {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
473 {Feature_HasMVEIntBit, Feature_IsBEBit, },
474 {Feature_HasMVEIntBit, Feature_IsLEBit, },
475 {Feature_HasNEONBit, Feature_HasV8Bit, },
476 {Feature_HasNEONBit, Feature_HasV8_1aBit, },
477 {Feature_HasNEONBit, Feature_HasV8_3aBit, },
478 {Feature_HasNEONBit, Feature_HasVFP4Bit, },
479 {Feature_HasNEONBit, Feature_IsBEBit, },
480 {Feature_HasNEONBit, Feature_IsLEBit, },
481 {Feature_HasNEONBit, Feature_UseNEONForFPBit, },
482 {Feature_HasSHA2Bit, Feature_HasV8Bit, },
483 {Feature_HasV4TBit, Feature_IsARMBit, },
484 {Feature_HasV5TBit, Feature_IsARMBit, },
485 {Feature_HasV5TBit, Feature_IsThumbBit, },
486 {Feature_HasV5TEBit, Feature_IsARMBit, },
487 {Feature_HasV6Bit, Feature_IsARMBit, },
488 {Feature_HasV6KBit, Feature_IsARMBit, },
489 {Feature_HasV6MBit, Feature_IsThumbBit, },
490 {Feature_HasV6T2Bit, Feature_IsARMBit, },
491 {Feature_HasV7Bit, Feature_IsARMBit, },
492 {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
493 {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
494 {Feature_IsARMBit, Feature_NoV4TBit, },
495 {Feature_IsARMBit, Feature_NoV5TBit, },
496 {Feature_IsARMBit, Feature_NoV6Bit, },
497 {Feature_IsARMBit, Feature_PreV8Bit, },
498 {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
499 {Feature_IsThumbBit, Feature_IsWindowsBit, },
500 {Feature_IsThumbBit, Feature_NoV5TBit, },
501 {Feature_IsThumbBit, Feature_UseMovtBit, },
502 {Feature_IsThumb2Bit, Feature_PreV8Bit, },
503 {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
504 {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, },
505 {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
506 {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
507 {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
508 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
509 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
510 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
511 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
512 {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
513 {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
514 {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
515 {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
516 {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
517 {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
518 {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
519 {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
520};
521
522// ComplexPattern predicates.
523enum {
524 GICP_Invalid,
525};
526// See constructor for table contents
527
528ARMInstructionSelector::ComplexMatcherMemFn
529ARMInstructionSelector::ComplexPredicateFns[] = {
530 nullptr, // GICP_Invalid
531};
532
533// PatFrag predicates.
534enum {
535 GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1,
536 GICXXPred_MI_Predicate_fadd_contract,
537 GICXXPred_MI_Predicate_ffloor_nnan,
538 GICXXPred_MI_Predicate_fmul_contract,
539 GICXXPred_MI_Predicate_fsub_contract,
540 GICXXPred_MI_Predicate_or_disjoint,
541 GICXXPred_MI_Predicate_vfp_f32imm,
542 GICXXPred_MI_Predicate_vfp_f64imm,
543};
544bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
545 const MachineFunction &MF = *MI.getParent()->getParent();
546 const MachineRegisterInfo &MRI = MF.getRegInfo();
547 const auto &Operands = State.RecordedOperands;
548 (void)Operands;
549 (void)MRI;
550 switch (PredicateID) {
551 case GICXXPred_MI_Predicate_bf_inv_mask_imm: {
552
553 // There's better methods of implementing this check. IntImmLeaf<> would be
554 // equivalent and have less boilerplate but we need a test for C++
555 // predicates and this one causes new rules to be imported into GlobalISel
556 // without requiring additional features first.
557 const auto &MO = MI.getOperand(1);
558 if (!MO.isCImm())
559 return false;
560 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
561
562 llvm_unreachable("bf_inv_mask_imm should have returned");
563 }
564 case GICXXPred_MI_Predicate_fadd_contract: {
565
566 return MI.getFlag(MachineInstr::FmContract);
567
568 }
569 case GICXXPred_MI_Predicate_ffloor_nnan: {
570
571 return MI.getFlag(MachineInstr::FmNoNans);
572
573 }
574 case GICXXPred_MI_Predicate_fmul_contract: {
575
576 return MI.getFlag(MachineInstr::FmContract);
577
578 }
579 case GICXXPred_MI_Predicate_fsub_contract: {
580
581 return MI.getFlag(MachineInstr::FmContract);
582
583 }
584 case GICXXPred_MI_Predicate_or_disjoint: {
585
586 return MI.getFlag(MachineInstr::Disjoint);
587
588 }
589 case GICXXPred_MI_Predicate_vfp_f32imm: {
590
591 const auto &MO = MI.getOperand(1);
592 if (!MO.isFPImm())
593 return false;
594 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
595
596 llvm_unreachable("vfp_f32imm should have returned");
597 }
598 case GICXXPred_MI_Predicate_vfp_f64imm: {
599
600 const auto &MO = MI.getOperand(1);
601 if (!MO.isFPImm())
602 return false;
603 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
604
605 llvm_unreachable("vfp_f64imm should have returned");
606 }
607 }
608 llvm_unreachable("Unknown predicate");
609 return false;
610}
611// PatFrag predicates.
612bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
613 const auto &Operands = State.RecordedOperands;
614 Register Reg = MO.getReg();
615 (void)Operands;
616 (void)Reg;
617 llvm_unreachable("Unknown predicate");
618 return false;
619}
620// PatFrag predicates.
621enum {
622 GICXXPred_I64_Predicate_FPNoSaturation = GICXXPred_Invalid + 1,
623 GICXXPred_I64_Predicate_Float8E4M3FN,
624 GICXXPred_I64_Predicate_Float8E5M2,
625 GICXXPred_I64_Predicate_NearestTiesToEven,
626 GICXXPred_I64_Predicate_VectorIndex8,
627 GICXXPred_I64_Predicate_VectorIndex16,
628 GICXXPred_I64_Predicate_VectorIndex32,
629 GICXXPred_I64_Predicate_VectorIndex32_Hi,
630 GICXXPred_I64_Predicate_VectorIndex64,
631 GICXXPred_I64_Predicate_asr_imm,
632 GICXXPred_I64_Predicate_imm0_7,
633 GICXXPred_I64_Predicate_imm0_15,
634 GICXXPred_I64_Predicate_imm0_31,
635 GICXXPred_I64_Predicate_imm0_32,
636 GICXXPred_I64_Predicate_imm0_63,
637 GICXXPred_I64_Predicate_imm0_239,
638 GICXXPred_I64_Predicate_imm0_255,
639 GICXXPred_I64_Predicate_imm0_255_expr,
640 GICXXPred_I64_Predicate_imm0_4095,
641 GICXXPred_I64_Predicate_imm0_65535,
642 GICXXPred_I64_Predicate_imm0_65535_expr,
643 GICXXPred_I64_Predicate_imm0_65535_neg,
644 GICXXPred_I64_Predicate_imm1_7,
645 GICXXPred_I64_Predicate_imm1_15,
646 GICXXPred_I64_Predicate_imm1_16,
647 GICXXPred_I64_Predicate_imm1_31,
648 GICXXPred_I64_Predicate_imm8,
649 GICXXPred_I64_Predicate_imm8_255,
650 GICXXPred_I64_Predicate_imm8_or_16,
651 GICXXPred_I64_Predicate_imm16,
652 GICXXPred_I64_Predicate_imm16_31,
653 GICXXPred_I64_Predicate_imm24b,
654 GICXXPred_I64_Predicate_imm32,
655 GICXXPred_I64_Predicate_imm256_510,
656 GICXXPred_I64_Predicate_imm_3b,
657 GICXXPred_I64_Predicate_imm_4b,
658 GICXXPred_I64_Predicate_imm_6b,
659 GICXXPred_I64_Predicate_imm_7b,
660 GICXXPred_I64_Predicate_imm_9b,
661 GICXXPred_I64_Predicate_imm_11b,
662 GICXXPred_I64_Predicate_imm_12b,
663 GICXXPred_I64_Predicate_imm_13b,
664 GICXXPred_I64_Predicate_imm_even,
665 GICXXPred_I64_Predicate_imm_odd,
666 GICXXPred_I64_Predicate_imm_sr,
667 GICXXPred_I64_Predicate_long_shift,
668 GICXXPred_I64_Predicate_mod_imm,
669 GICXXPred_I64_Predicate_mod_imm_not,
670 GICXXPred_I64_Predicate_pkh_asr_amt,
671 GICXXPred_I64_Predicate_pkh_lsl_amt,
672 GICXXPred_I64_Predicate_shr_imm8,
673 GICXXPred_I64_Predicate_shr_imm16,
674 GICXXPred_I64_Predicate_shr_imm32,
675 GICXXPred_I64_Predicate_shr_imm64,
676 GICXXPred_I64_Predicate_t2_so_imm,
677 GICXXPred_I64_Predicate_t2_so_imm_neg,
678};
679bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
680 switch (PredicateID) {
681 case GICXXPred_I64_Predicate_FPNoSaturation: {
682 return Imm == 0;
683 }
684 case GICXXPred_I64_Predicate_Float8E4M3FN: {
685 return Imm == APFloatBase::S_Float8E4M3FN;
686 }
687 case GICXXPred_I64_Predicate_Float8E5M2: {
688 return Imm == APFloatBase::S_Float8E5M2;
689 }
690 case GICXXPred_I64_Predicate_NearestTiesToEven: {
691 return Imm == static_cast<int>(RoundingMode::NearestTiesToEven);
692 }
693 case GICXXPred_I64_Predicate_VectorIndex8: {
694
695 return ((uint64_t)Imm) < 8;
696
697 }
698 case GICXXPred_I64_Predicate_VectorIndex16: {
699
700 return ((uint64_t)Imm) < 4;
701
702 }
703 case GICXXPred_I64_Predicate_VectorIndex32: {
704
705 return ((uint64_t)Imm) < 2;
706
707 }
708 case GICXXPred_I64_Predicate_VectorIndex32_Hi: {
709
710 return ((uint64_t)Imm) >= 2 && ((uint64_t)Imm) < 4;
711
712 }
713 case GICXXPred_I64_Predicate_VectorIndex64: {
714
715 return ((uint64_t)Imm) < 1;
716
717 }
718 case GICXXPred_I64_Predicate_asr_imm: {
719 return Imm > 0 && Imm <= 32;
720 }
721 case GICXXPred_I64_Predicate_imm0_7: {
722
723 return Imm >= 0 && Imm < 8;
724
725 }
726 case GICXXPred_I64_Predicate_imm0_15: {
727
728 return Imm >= 0 && Imm < 16;
729
730 }
731 case GICXXPred_I64_Predicate_imm0_31: {
732
733 return Imm >= 0 && Imm < 32;
734
735 }
736 case GICXXPred_I64_Predicate_imm0_32: {
737
738 return Imm >= 0 && Imm < 33;
739
740 }
741 case GICXXPred_I64_Predicate_imm0_63: {
742
743 return Imm >= 0 && Imm < 64;
744
745 }
746 case GICXXPred_I64_Predicate_imm0_239: {
747 return Imm >= 0 && Imm < 240;
748 }
749 case GICXXPred_I64_Predicate_imm0_255: {
750 return Imm >= 0 && Imm < 256;
751 }
752 case GICXXPred_I64_Predicate_imm0_255_expr: {
753 return Imm >= 0 && Imm < 256;
754 }
755 case GICXXPred_I64_Predicate_imm0_4095: {
756
757 return Imm >= 0 && Imm < 4096;
758
759 }
760 case GICXXPred_I64_Predicate_imm0_65535: {
761
762 return Imm >= 0 && Imm < 65536;
763
764 }
765 case GICXXPred_I64_Predicate_imm0_65535_expr: {
766
767 return Imm >= 0 && Imm < 65536;
768
769 }
770 case GICXXPred_I64_Predicate_imm0_65535_neg: {
771
772 return -Imm >= 0 && -Imm < 65536;
773
774 }
775 case GICXXPred_I64_Predicate_imm1_7: {
776 return Imm > 0 && Imm < 8;
777 }
778 case GICXXPred_I64_Predicate_imm1_15: {
779 return Imm > 0 && Imm < 16;
780 }
781 case GICXXPred_I64_Predicate_imm1_16: {
782
783 return Imm > 0 && Imm <= 16;
784
785 }
786 case GICXXPred_I64_Predicate_imm1_31: {
787 return Imm > 0 && Imm < 32;
788 }
789 case GICXXPred_I64_Predicate_imm8: {
790 return Imm == 8;
791 }
792 case GICXXPred_I64_Predicate_imm8_255: {
793
794 return Imm >= 8 && Imm < 256;
795
796 }
797 case GICXXPred_I64_Predicate_imm8_or_16: {
798 return Imm == 8 || Imm == 16;
799 }
800 case GICXXPred_I64_Predicate_imm16: {
801 return Imm == 16;
802 }
803 case GICXXPred_I64_Predicate_imm16_31: {
804
805 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
806
807 }
808 case GICXXPred_I64_Predicate_imm24b: {
809
810 return Imm >= 0 && Imm <= 0xffffff;
811
812 }
813 case GICXXPred_I64_Predicate_imm32: {
814 return Imm == 32;
815 }
816 case GICXXPred_I64_Predicate_imm256_510: {
817
818 return Imm >= 256 && Imm < 511;
819
820 }
821 case GICXXPred_I64_Predicate_imm_3b: {
822 { return Imm >= 0 && Imm < (1 << 3); }
823 llvm_unreachable("imm_3b should have returned");
824 }
825 case GICXXPred_I64_Predicate_imm_4b: {
826 { return Imm >= 0 && Imm < (1 << 4); }
827 llvm_unreachable("imm_4b should have returned");
828 }
829 case GICXXPred_I64_Predicate_imm_6b: {
830 { return Imm >= 0 && Imm < (1 << 6); }
831 llvm_unreachable("imm_6b should have returned");
832 }
833 case GICXXPred_I64_Predicate_imm_7b: {
834 { return Imm >= 0 && Imm < (1 << 7); }
835 llvm_unreachable("imm_7b should have returned");
836 }
837 case GICXXPred_I64_Predicate_imm_9b: {
838 { return Imm >= 0 && Imm < (1 << 9); }
839 llvm_unreachable("imm_9b should have returned");
840 }
841 case GICXXPred_I64_Predicate_imm_11b: {
842 { return Imm >= 0 && Imm < (1 << 11); }
843 llvm_unreachable("imm_11b should have returned");
844 }
845 case GICXXPred_I64_Predicate_imm_12b: {
846 { return Imm >= 0 && Imm < (1 << 12); }
847 llvm_unreachable("imm_12b should have returned");
848 }
849 case GICXXPred_I64_Predicate_imm_13b: {
850 { return Imm >= 0 && Imm < (1 << 13); }
851 llvm_unreachable("imm_13b should have returned");
852 }
853 case GICXXPred_I64_Predicate_imm_even: {
854 return (Imm & 1) == 0;
855 }
856 case GICXXPred_I64_Predicate_imm_odd: {
857 return (Imm & 1) == 1;
858 }
859 case GICXXPred_I64_Predicate_imm_sr: {
860
861 return Imm > 0 && Imm <= 32;
862
863 }
864 case GICXXPred_I64_Predicate_long_shift: {
865 return Imm > 0 && Imm <= 32;
866 }
867 case GICXXPred_I64_Predicate_mod_imm: {
868
869 return ARM_AM::getSOImmVal(Imm) != -1;
870
871 }
872 case GICXXPred_I64_Predicate_mod_imm_not: {
873
874 return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1;
875
876 }
877 case GICXXPred_I64_Predicate_pkh_asr_amt: {
878 return Imm > 0 && Imm <= 32;
879 }
880 case GICXXPred_I64_Predicate_pkh_lsl_amt: {
881 return Imm >= 0 && Imm < 32;
882 }
883 case GICXXPred_I64_Predicate_shr_imm8: {
884 return Imm > 0 && Imm <= 8;
885 }
886 case GICXXPred_I64_Predicate_shr_imm16: {
887 return Imm > 0 && Imm <= 16;
888 }
889 case GICXXPred_I64_Predicate_shr_imm32: {
890 return Imm > 0 && Imm <= 32;
891 }
892 case GICXXPred_I64_Predicate_shr_imm64: {
893 return Imm > 0 && Imm <= 64;
894 }
895 case GICXXPred_I64_Predicate_t2_so_imm: {
896
897 return ARM_AM::getT2SOImmVal(Imm) != -1;
898
899 }
900 case GICXXPred_I64_Predicate_t2_so_imm_neg: {
901
902 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
903
904 }
905 }
906 llvm_unreachable("Unknown predicate");
907 return false;
908}
909// PatFrag predicates.
910bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
911 llvm_unreachable("Unknown predicate");
912 return false;
913}
914// PatFrag predicates.
915enum {
916 GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1,
917};
918bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
919 switch (PredicateID) {
920 case GICXXPred_APInt_Predicate_arm_i32imm: {
921
922 if (Subtarget->useMovt())
923 return true;
924 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
925 return true;
926 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
927
928 llvm_unreachable("arm_i32imm should have returned");
929 }
930 }
931 llvm_unreachable("Unknown predicate");
932 return false;
933}
934bool ARMInstructionSelector::testSimplePredicate(unsigned) const {
935 llvm_unreachable("ARMInstructionSelector does not support simple predicates!");
936 return false;
937}
938// Custom renderers.
939enum {
940 GICR_Invalid,
941 GICR_renderFrameIndex,
942 GICR_renderInvertedImm,
943 GICR_renderVFPF32Imm,
944 GICR_renderVFPF64Imm,
945};
946ARMInstructionSelector::CustomRendererFn
947ARMInstructionSelector::CustomRenderers[] = {
948 nullptr, // GICR_Invalid
949 &ARMInstructionSelector::renderFrameIndex,
950 &ARMInstructionSelector::renderInvertedImm,
951 &ARMInstructionSelector::renderVFPF32Imm,
952 &ARMInstructionSelector::renderVFPF64Imm,
953};
954
955bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
956 const PredicateBitset AvailableFeatures = getAvailableFeatures();
957 MachineIRBuilder B(I);
958 State.MIs.clear();
959 State.MIs.push_back(&I);
960
961 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
962 return true;
963 }
964
965 return false;
966}
967
968bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
969 llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!");
970}
971#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
972#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
973#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
974#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
975#else
976#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
977#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
978#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
979#endif
980const uint8_t *ARMInstructionSelector::getMatchTable() const {
981 constexpr static uint8_t MatchTable0[] = {
982 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(333), /*)*//*default:*//*Label 95*/ GIMT_Encode4(132527),
983 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1122),
984 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(12550),
985 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(15648),
986 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(17311),
987 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(17405), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
988 /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(17499),
989 /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(20599),
990 /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(26325),
991 /* 58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(27984),
992 /* 62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(28494),
993 /* 66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(29004),
994 /* 70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(29231),
995 /* 74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(29458),
996 /* 78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(29685), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
997 /* 130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(29912), GIMT_Encode4(0), GIMT_Encode4(0),
998 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(30579), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
999 /* 158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(37766),
1000 /* 162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(38165), GIMT_Encode4(0), GIMT_Encode4(0),
1001 /* 174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 18*/ GIMT_Encode4(38531), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1002 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(38897), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1003 /* 326 */ /*TargetOpcode::G_FENCE*//*Label 20*/ GIMT_Encode4(39058), GIMT_Encode4(0), GIMT_Encode4(0),
1004 /* 338 */ /*TargetOpcode::G_BRINDIRECT*//*Label 21*/ GIMT_Encode4(39079), GIMT_Encode4(0),
1005 /* 346 */ /*TargetOpcode::G_INTRINSIC*//*Label 22*/ GIMT_Encode4(39145),
1006 /* 350 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 23*/ GIMT_Encode4(90441), GIMT_Encode4(0), GIMT_Encode4(0),
1007 /* 362 */ /*TargetOpcode::G_ANYEXT*//*Label 24*/ GIMT_Encode4(96221),
1008 /* 366 */ /*TargetOpcode::G_TRUNC*//*Label 25*/ GIMT_Encode4(96360), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1009 /* 382 */ /*TargetOpcode::G_CONSTANT*//*Label 26*/ GIMT_Encode4(96503),
1010 /* 386 */ /*TargetOpcode::G_FCONSTANT*//*Label 27*/ GIMT_Encode4(96815), GIMT_Encode4(0), GIMT_Encode4(0),
1011 /* 398 */ /*TargetOpcode::G_SEXT*//*Label 28*/ GIMT_Encode4(96909),
1012 /* 402 */ /*TargetOpcode::G_SEXT_INREG*//*Label 29*/ GIMT_Encode4(97048),
1013 /* 406 */ /*TargetOpcode::G_ZEXT*//*Label 30*/ GIMT_Encode4(97638),
1014 /* 410 */ /*TargetOpcode::G_SHL*//*Label 31*/ GIMT_Encode4(98326),
1015 /* 414 */ /*TargetOpcode::G_LSHR*//*Label 32*/ GIMT_Encode4(98538),
1016 /* 418 */ /*TargetOpcode::G_ASHR*//*Label 33*/ GIMT_Encode4(98644), GIMT_Encode4(0), GIMT_Encode4(0),
1017 /* 430 */ /*TargetOpcode::G_ROTR*//*Label 34*/ GIMT_Encode4(98912), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1018 /* 498 */ /*TargetOpcode::G_UMULH*//*Label 35*/ GIMT_Encode4(99238),
1019 /* 502 */ /*TargetOpcode::G_SMULH*//*Label 36*/ GIMT_Encode4(99471),
1020 /* 506 */ /*TargetOpcode::G_UADDSAT*//*Label 37*/ GIMT_Encode4(99823),
1021 /* 510 */ /*TargetOpcode::G_SADDSAT*//*Label 38*/ GIMT_Encode4(100449),
1022 /* 514 */ /*TargetOpcode::G_USUBSAT*//*Label 39*/ GIMT_Encode4(101722),
1023 /* 518 */ /*TargetOpcode::G_SSUBSAT*//*Label 40*/ GIMT_Encode4(102348), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1024 /* 562 */ /*TargetOpcode::G_FADD*//*Label 41*/ GIMT_Encode4(103341),
1025 /* 566 */ /*TargetOpcode::G_FSUB*//*Label 42*/ GIMT_Encode4(106146),
1026 /* 570 */ /*TargetOpcode::G_FMUL*//*Label 43*/ GIMT_Encode4(107859),
1027 /* 574 */ /*TargetOpcode::G_FMA*//*Label 44*/ GIMT_Encode4(108824), GIMT_Encode4(0),
1028 /* 582 */ /*TargetOpcode::G_FDIV*//*Label 45*/ GIMT_Encode4(110887), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1029 /* 634 */ /*TargetOpcode::G_FNEG*//*Label 46*/ GIMT_Encode4(111049),
1030 /* 638 */ /*TargetOpcode::G_FPEXT*//*Label 47*/ GIMT_Encode4(113457),
1031 /* 642 */ /*TargetOpcode::G_FPTRUNC*//*Label 48*/ GIMT_Encode4(113721),
1032 /* 646 */ /*TargetOpcode::G_FPTOSI*//*Label 49*/ GIMT_Encode4(114013),
1033 /* 650 */ /*TargetOpcode::G_FPTOUI*//*Label 50*/ GIMT_Encode4(115295),
1034 /* 654 */ /*TargetOpcode::G_SITOFP*//*Label 51*/ GIMT_Encode4(116577),
1035 /* 658 */ /*TargetOpcode::G_UITOFP*//*Label 52*/ GIMT_Encode4(117219),
1036 /* 662 */ /*TargetOpcode::G_FPTOSI_SAT*//*Label 53*/ GIMT_Encode4(117861),
1037 /* 666 */ /*TargetOpcode::G_FPTOUI_SAT*//*Label 54*/ GIMT_Encode4(118224),
1038 /* 670 */ /*TargetOpcode::G_FABS*//*Label 55*/ GIMT_Encode4(118587), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1039 /* 686 */ /*TargetOpcode::G_FMINNUM*//*Label 56*/ GIMT_Encode4(119351),
1040 /* 690 */ /*TargetOpcode::G_FMAXNUM*//*Label 57*/ GIMT_Encode4(119932), GIMT_Encode4(0), GIMT_Encode4(0),
1041 /* 702 */ /*TargetOpcode::G_FMINIMUM*//*Label 58*/ GIMT_Encode4(120513),
1042 /* 706 */ /*TargetOpcode::G_FMAXIMUM*//*Label 59*/ GIMT_Encode4(121241), GIMT_Encode4(0), GIMT_Encode4(0),
1043 /* 718 */ /*TargetOpcode::G_GET_FPENV*//*Label 60*/ GIMT_Encode4(121969),
1044 /* 722 */ /*TargetOpcode::G_SET_FPENV*//*Label 61*/ GIMT_Encode4(122002),
1045 /* 726 */ /*TargetOpcode::G_RESET_FPENV*//*Label 62*/ GIMT_Encode4(122038),
1046 /* 730 */ /*TargetOpcode::G_GET_FPMODE*//*Label 63*/ GIMT_Encode4(122165), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1047 /* 758 */ /*TargetOpcode::G_SMIN*//*Label 64*/ GIMT_Encode4(122198),
1048 /* 762 */ /*TargetOpcode::G_SMAX*//*Label 65*/ GIMT_Encode4(122708),
1049 /* 766 */ /*TargetOpcode::G_UMIN*//*Label 66*/ GIMT_Encode4(123218),
1050 /* 770 */ /*TargetOpcode::G_UMAX*//*Label 67*/ GIMT_Encode4(124106),
1051 /* 774 */ /*TargetOpcode::G_ABS*//*Label 68*/ GIMT_Encode4(124994), GIMT_Encode4(0), GIMT_Encode4(0),
1052 /* 786 */ /*TargetOpcode::G_BR*//*Label 69*/ GIMT_Encode4(125432), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1053 /* 806 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 70*/ GIMT_Encode4(125502),
1054 /* 810 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 71*/ GIMT_Encode4(125778), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1055 /* 838 */ /*TargetOpcode::G_CTLZ*//*Label 72*/ GIMT_Encode4(125834), GIMT_Encode4(0),
1056 /* 846 */ /*TargetOpcode::G_CTLS*//*Label 73*/ GIMT_Encode4(126372),
1057 /* 850 */ /*TargetOpcode::G_CTPOP*//*Label 74*/ GIMT_Encode4(126810),
1058 /* 854 */ /*TargetOpcode::G_BSWAP*//*Label 75*/ GIMT_Encode4(126904),
1059 /* 858 */ /*TargetOpcode::G_BITREVERSE*//*Label 76*/ GIMT_Encode4(127189), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1060 /* 874 */ /*TargetOpcode::G_FCEIL*//*Label 77*/ GIMT_Encode4(127604), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1061 /* 922 */ /*TargetOpcode::G_FSQRT*//*Label 78*/ GIMT_Encode4(127970),
1062 /* 926 */ /*TargetOpcode::G_FFLOOR*//*Label 79*/ GIMT_Encode4(128105),
1063 /* 930 */ /*TargetOpcode::G_FRINT*//*Label 80*/ GIMT_Encode4(128471),
1064 /* 934 */ /*TargetOpcode::G_FNEARBYINT*//*Label 81*/ GIMT_Encode4(128870), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1065 /* 962 */ /*TargetOpcode::G_STRICT_FADD*//*Label 82*/ GIMT_Encode4(129005),
1066 /* 966 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 83*/ GIMT_Encode4(129167),
1067 /* 970 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 84*/ GIMT_Encode4(129329),
1068 /* 974 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 85*/ GIMT_Encode4(129491), GIMT_Encode4(0),
1069 /* 982 */ /*TargetOpcode::G_STRICT_FMA*//*Label 86*/ GIMT_Encode4(129653),
1070 /* 986 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 87*/ GIMT_Encode4(130820), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1071 /* 1034 */ /*TargetOpcode::G_TRAP*//*Label 88*/ GIMT_Encode4(130955),
1072 /* 1038 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 89*/ GIMT_Encode4(130984), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1073 /* 1086 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 90*/ GIMT_Encode4(131067), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1074 /* 1106 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 91*/ GIMT_Encode4(131441),
1075 /* 1110 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 92*/ GIMT_Encode4(131706),
1076 /* 1114 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 93*/ GIMT_Encode4(131980),
1077 /* 1118 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 94*/ GIMT_Encode4(132246),
1078 /* 1122 */ // Label 0: @1122
1079 /* 1122 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 105*/ GIMT_Encode4(12549),
1080 /* 1133 */ /*GILLT_s32*//*Label 96*/ GIMT_Encode4(1185),
1081 /* 1137 */ /*GILLT_s64*//*Label 97*/ GIMT_Encode4(6828), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1082 /* 1157 */ /*GILLT_v8s8*//*Label 98*/ GIMT_Encode4(6874),
1083 /* 1161 */ /*GILLT_v16s8*//*Label 99*/ GIMT_Encode4(7308),
1084 /* 1165 */ /*GILLT_v4s16*//*Label 100*/ GIMT_Encode4(7808),
1085 /* 1169 */ /*GILLT_v8s16*//*Label 101*/ GIMT_Encode4(8242),
1086 /* 1173 */ /*GILLT_v2s32*//*Label 102*/ GIMT_Encode4(9677),
1087 /* 1177 */ /*GILLT_v4s32*//*Label 103*/ GIMT_Encode4(10111),
1088 /* 1181 */ /*GILLT_v2s64*//*Label 104*/ GIMT_Encode4(11546),
1089 /* 1185 */ // Label 96: @1185
1090 /* 1185 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(6827),
1091 /* 1190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1092 /* 1193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1093 /* 1196 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1342),
1094 /* 1201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1095 /* 1205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1096 /* 1209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 108*/ GIMT_Encode4(1275), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6275 //
1097 /* 1216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1098 /* 1220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1099 /* 1224 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1100 /* 1228 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1101 /* 1232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1102 /* 1237 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1103 /* 1248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1104 /* 1250 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1105 /* 1250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1106 /* 1253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1107 /* 1255 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1108 /* 1257 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1109 /* 1261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1110 /* 1264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1111 /* 1267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1112 /* 1273 */ GIR_RootConstrainSelectedInstOperands,
1113 /* 1274 */ // GIR_Coverage, 6275,
1114 /* 1274 */ GIR_EraseRootFromParent_Done,
1115 /* 1275 */ // Label 108: @1275
1116 /* 1275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 109*/ GIMT_Encode4(1341), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6276 //
1117 /* 1282 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1118 /* 1286 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1119 /* 1290 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1120 /* 1294 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1121 /* 1298 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1122 /* 1303 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1123 /* 1314 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1124 /* 1316 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1125 /* 1316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1126 /* 1319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1127 /* 1321 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1128 /* 1323 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1129 /* 1327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1130 /* 1330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1131 /* 1333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1132 /* 1339 */ GIR_RootConstrainSelectedInstOperands,
1133 /* 1340 */ // GIR_Coverage, 6276,
1134 /* 1340 */ GIR_EraseRootFromParent_Done,
1135 /* 1341 */ // Label 109: @1341
1136 /* 1341 */ GIM_Reject,
1137 /* 1342 */ // Label 107: @1342
1138 /* 1342 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1488),
1139 /* 1347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1140 /* 1351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1141 /* 1355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 111*/ GIMT_Encode4(1421), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6314 //
1142 /* 1362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1143 /* 1366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1144 /* 1370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1145 /* 1374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1146 /* 1378 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1147 /* 1383 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1148 /* 1394 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1149 /* 1396 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1150 /* 1396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1151 /* 1399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1152 /* 1401 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1153 /* 1403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1154 /* 1407 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1155 /* 1410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1156 /* 1413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1157 /* 1419 */ GIR_RootConstrainSelectedInstOperands,
1158 /* 1420 */ // GIR_Coverage, 6314,
1159 /* 1420 */ GIR_EraseRootFromParent_Done,
1160 /* 1421 */ // Label 111: @1421
1161 /* 1421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 112*/ GIMT_Encode4(1487), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6315 //
1162 /* 1428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1163 /* 1432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1164 /* 1436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1165 /* 1440 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1166 /* 1444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1167 /* 1449 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1168 /* 1460 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1169 /* 1462 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1170 /* 1462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1171 /* 1465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1172 /* 1467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1173 /* 1469 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1174 /* 1473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1175 /* 1476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1176 /* 1479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1177 /* 1485 */ GIR_RootConstrainSelectedInstOperands,
1178 /* 1486 */ // GIR_Coverage, 6315,
1179 /* 1486 */ GIR_EraseRootFromParent_Done,
1180 /* 1487 */ // Label 112: @1487
1181 /* 1487 */ GIM_Reject,
1182 /* 1488 */ // Label 110: @1488
1183 /* 1488 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1634),
1184 /* 1493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1185 /* 1497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1186 /* 1501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 114*/ GIMT_Encode4(1567), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2195 //
1187 /* 1508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1188 /* 1512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1189 /* 1516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1190 /* 1520 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1191 /* 1524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1192 /* 1529 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1193 /* 1540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1194 /* 1542 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1195 /* 1542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1196 /* 1545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1197 /* 1547 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1198 /* 1549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1199 /* 1553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1200 /* 1556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1201 /* 1559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1202 /* 1565 */ GIR_RootConstrainSelectedInstOperands,
1203 /* 1566 */ // GIR_Coverage, 2195,
1204 /* 1566 */ GIR_EraseRootFromParent_Done,
1205 /* 1567 */ // Label 114: @1567
1206 /* 1567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 115*/ GIMT_Encode4(1633), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2196 //
1207 /* 1574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1208 /* 1578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1209 /* 1582 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1210 /* 1586 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1211 /* 1590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1212 /* 1595 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1213 /* 1606 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1214 /* 1608 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1215 /* 1608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1216 /* 1611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1217 /* 1613 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1218 /* 1615 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1219 /* 1619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1220 /* 1622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1221 /* 1625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1222 /* 1631 */ GIR_RootConstrainSelectedInstOperands,
1223 /* 1632 */ // GIR_Coverage, 2196,
1224 /* 1632 */ GIR_EraseRootFromParent_Done,
1225 /* 1633 */ // Label 115: @1633
1226 /* 1633 */ GIM_Reject,
1227 /* 1634 */ // Label 113: @1634
1228 /* 1634 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(2282),
1229 /* 1639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1230 /* 1643 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(1785),
1231 /* 1648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1232 /* 1652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 118*/ GIMT_Encode4(1718), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2439 //
1233 /* 1659 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1234 /* 1663 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1235 /* 1667 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1236 /* 1671 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1237 /* 1675 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1238 /* 1680 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1239 /* 1691 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1240 /* 1693 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1241 /* 1693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1242 /* 1696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1243 /* 1698 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1244 /* 1700 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1245 /* 1704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1246 /* 1707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1247 /* 1710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1248 /* 1716 */ GIR_RootConstrainSelectedInstOperands,
1249 /* 1717 */ // GIR_Coverage, 2439,
1250 /* 1717 */ GIR_EraseRootFromParent_Done,
1251 /* 1718 */ // Label 118: @1718
1252 /* 1718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 119*/ GIMT_Encode4(1784), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2440 //
1253 /* 1725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1254 /* 1729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1255 /* 1733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1256 /* 1737 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1257 /* 1741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1258 /* 1746 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1259 /* 1757 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1260 /* 1759 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1261 /* 1759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1262 /* 1762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1263 /* 1764 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1264 /* 1766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1265 /* 1770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1266 /* 1773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1267 /* 1776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1268 /* 1782 */ GIR_RootConstrainSelectedInstOperands,
1269 /* 1783 */ // GIR_Coverage, 2440,
1270 /* 1783 */ GIR_EraseRootFromParent_Done,
1271 /* 1784 */ // Label 119: @1784
1272 /* 1784 */ GIM_Reject,
1273 /* 1785 */ // Label 117: @1785
1274 /* 1785 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2033),
1275 /* 1790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1276 /* 1794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 121*/ GIMT_Encode4(1913), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6287 //
1277 /* 1801 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1278 /* 1805 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1279 /* 1809 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1280 /* 1813 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1281 /* 1817 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1282 /* 1821 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1283 /* 1825 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1284 /* 1829 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1285 /* 1833 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1286 /* 1837 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1287 /* 1841 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1288 /* 1845 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1289 /* 1850 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1290 /* 1854 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1291 /* 1858 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1292 /* 1862 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1293 /* 1866 */ // MIs[4] Rm
1294 /* 1866 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1295 /* 1871 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1296 /* 1875 */ // MIs[1] Operand 2
1297 /* 1875 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1298 /* 1886 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1299 /* 1888 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1300 /* 1888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1301 /* 1891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1302 /* 1893 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1303 /* 1895 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1304 /* 1899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1305 /* 1902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1306 /* 1905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1307 /* 1911 */ GIR_RootConstrainSelectedInstOperands,
1308 /* 1912 */ // GIR_Coverage, 6287,
1309 /* 1912 */ GIR_EraseRootFromParent_Done,
1310 /* 1913 */ // Label 121: @1913
1311 /* 1913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 122*/ GIMT_Encode4(2032), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6288 //
1312 /* 1920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1313 /* 1924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1314 /* 1928 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1315 /* 1932 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1316 /* 1936 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1317 /* 1940 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1318 /* 1944 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1319 /* 1948 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1320 /* 1952 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1321 /* 1956 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1322 /* 1960 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1323 /* 1964 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1324 /* 1969 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1325 /* 1973 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1326 /* 1977 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1327 /* 1981 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1328 /* 1985 */ // MIs[4] Rm
1329 /* 1985 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1330 /* 1990 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1331 /* 1994 */ // MIs[1] Operand 2
1332 /* 1994 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1333 /* 2005 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1334 /* 2007 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1335 /* 2007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1336 /* 2010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1337 /* 2012 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1338 /* 2014 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1339 /* 2018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1340 /* 2021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1341 /* 2024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1342 /* 2030 */ GIR_RootConstrainSelectedInstOperands,
1343 /* 2031 */ // GIR_Coverage, 6288,
1344 /* 2031 */ GIR_EraseRootFromParent_Done,
1345 /* 2032 */ // Label 122: @2032
1346 /* 2032 */ GIM_Reject,
1347 /* 2033 */ // Label 120: @2033
1348 /* 2033 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(2281),
1349 /* 2038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1350 /* 2042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 124*/ GIMT_Encode4(2161), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2302 //
1351 /* 2049 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1352 /* 2053 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1353 /* 2057 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1354 /* 2061 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1355 /* 2065 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1356 /* 2069 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1357 /* 2073 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1358 /* 2077 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1359 /* 2081 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1360 /* 2085 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1361 /* 2089 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1362 /* 2093 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1363 /* 2098 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1364 /* 2102 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1365 /* 2106 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1366 /* 2110 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1367 /* 2114 */ // MIs[4] Rm
1368 /* 2114 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1369 /* 2119 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1370 /* 2123 */ // MIs[1] Operand 2
1371 /* 2123 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1372 /* 2134 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1373 /* 2136 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1374 /* 2136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1375 /* 2139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1376 /* 2141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1377 /* 2143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1378 /* 2147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1379 /* 2150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1380 /* 2153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1381 /* 2159 */ GIR_RootConstrainSelectedInstOperands,
1382 /* 2160 */ // GIR_Coverage, 2302,
1383 /* 2160 */ GIR_EraseRootFromParent_Done,
1384 /* 2161 */ // Label 124: @2161
1385 /* 2161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 125*/ GIMT_Encode4(2280), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6286 //
1386 /* 2168 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1387 /* 2172 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1388 /* 2176 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1389 /* 2180 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1390 /* 2184 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1391 /* 2188 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1392 /* 2192 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1393 /* 2196 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1394 /* 2200 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1395 /* 2204 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1396 /* 2208 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1397 /* 2212 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1398 /* 2217 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1399 /* 2221 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1400 /* 2225 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1401 /* 2229 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1402 /* 2233 */ // MIs[4] Rm
1403 /* 2233 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1404 /* 2238 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1405 /* 2242 */ // MIs[1] Operand 2
1406 /* 2242 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1407 /* 2253 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1408 /* 2255 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1409 /* 2255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1410 /* 2258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1411 /* 2260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1412 /* 2262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1413 /* 2266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1414 /* 2269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1415 /* 2272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1416 /* 2278 */ GIR_RootConstrainSelectedInstOperands,
1417 /* 2279 */ // GIR_Coverage, 6286,
1418 /* 2279 */ GIR_EraseRootFromParent_Done,
1419 /* 2280 */ // Label 125: @2280
1420 /* 2280 */ GIM_Reject,
1421 /* 2281 */ // Label 123: @2281
1422 /* 2281 */ GIM_Reject,
1423 /* 2282 */ // Label 116: @2282
1424 /* 2282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 126*/ GIMT_Encode4(2391), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5984 //
1425 /* 2289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1426 /* 2293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1427 /* 2297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1428 /* 2301 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1429 /* 2305 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1430 /* 2309 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1431 /* 2313 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1432 /* 2317 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1433 /* 2321 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1434 /* 2325 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1435 /* 2330 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1436 /* 2334 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1437 /* 2338 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1438 /* 2342 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1439 /* 2346 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1440 /* 2350 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1441 /* 2355 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1442 /* 2359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1443 /* 2363 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1444 /* 2365 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1445 /* 2365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1446 /* 2368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1447 /* 2370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1448 /* 2374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1449 /* 2378 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1450 /* 2380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1451 /* 2383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1452 /* 2389 */ GIR_RootConstrainSelectedInstOperands,
1453 /* 2390 */ // GIR_Coverage, 5984,
1454 /* 2390 */ GIR_EraseRootFromParent_Done,
1455 /* 2391 */ // Label 126: @2391
1456 /* 2391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 127*/ GIMT_Encode4(2500), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6019 //
1457 /* 2398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1458 /* 2402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1459 /* 2406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1460 /* 2410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1461 /* 2414 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1462 /* 2418 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1463 /* 2422 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1464 /* 2426 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1465 /* 2430 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1466 /* 2434 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1467 /* 2439 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1468 /* 2443 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1469 /* 2447 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1470 /* 2451 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1471 /* 2455 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1472 /* 2459 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1473 /* 2464 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1474 /* 2468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1475 /* 2472 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1476 /* 2474 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1477 /* 2474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1478 /* 2477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1479 /* 2479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1480 /* 2483 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1481 /* 2487 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1482 /* 2489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1483 /* 2492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1484 /* 2498 */ GIR_RootConstrainSelectedInstOperands,
1485 /* 2499 */ // GIR_Coverage, 6019,
1486 /* 2499 */ GIR_EraseRootFromParent_Done,
1487 /* 2500 */ // Label 127: @2500
1488 /* 2500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 128*/ GIMT_Encode4(2609), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 191 //
1489 /* 2507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1490 /* 2511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1491 /* 2515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1492 /* 2519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1493 /* 2523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1494 /* 2527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1495 /* 2531 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1496 /* 2535 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1497 /* 2539 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1498 /* 2543 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1499 /* 2547 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1500 /* 2552 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1501 /* 2556 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1502 /* 2560 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1503 /* 2564 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1504 /* 2568 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1505 /* 2572 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1506 /* 2577 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1507 /* 2581 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1508 /* 2583 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1509 /* 2583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1510 /* 2586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1511 /* 2588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1512 /* 2592 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1513 /* 2596 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1514 /* 2598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1515 /* 2601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1516 /* 2607 */ GIR_RootConstrainSelectedInstOperands,
1517 /* 2608 */ // GIR_Coverage, 191,
1518 /* 2608 */ GIR_EraseRootFromParent_Done,
1519 /* 2609 */ // Label 128: @2609
1520 /* 2609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 129*/ GIMT_Encode4(2718), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 520 //
1521 /* 2616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1522 /* 2620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1523 /* 2624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1524 /* 2628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1525 /* 2632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1526 /* 2636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1527 /* 2640 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1528 /* 2644 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1529 /* 2648 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1530 /* 2652 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1531 /* 2656 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1532 /* 2661 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1533 /* 2665 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1534 /* 2669 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1535 /* 2673 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1536 /* 2677 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1537 /* 2681 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1538 /* 2686 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1539 /* 2690 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1540 /* 2692 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1541 /* 2692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1542 /* 2695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1543 /* 2697 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1544 /* 2701 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1545 /* 2705 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1546 /* 2707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1547 /* 2710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1548 /* 2716 */ GIR_RootConstrainSelectedInstOperands,
1549 /* 2717 */ // GIR_Coverage, 520,
1550 /* 2717 */ GIR_EraseRootFromParent_Done,
1551 /* 2718 */ // Label 129: @2718
1552 /* 2718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 130*/ GIMT_Encode4(2830), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5983 //
1553 /* 2725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1554 /* 2729 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1555 /* 2733 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1556 /* 2737 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1557 /* 2741 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1558 /* 2745 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1559 /* 2749 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1560 /* 2753 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1561 /* 2757 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1562 /* 2761 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1563 /* 2766 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1564 /* 2770 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1565 /* 2774 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1566 /* 2778 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1567 /* 2782 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1568 /* 2787 */ // MIs[3] Operand 2
1569 /* 2787 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1570 /* 2798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1571 /* 2802 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1572 /* 2804 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1573 /* 2804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1574 /* 2807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1575 /* 2809 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1576 /* 2813 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1577 /* 2817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1578 /* 2819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1579 /* 2822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1580 /* 2828 */ GIR_RootConstrainSelectedInstOperands,
1581 /* 2829 */ // GIR_Coverage, 5983,
1582 /* 2829 */ GIR_EraseRootFromParent_Done,
1583 /* 2830 */ // Label 130: @2830
1584 /* 2830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 131*/ GIMT_Encode4(2942), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6018 //
1585 /* 2837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1586 /* 2841 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1587 /* 2845 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1588 /* 2849 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1589 /* 2853 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1590 /* 2857 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1591 /* 2861 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1592 /* 2865 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1593 /* 2869 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1594 /* 2873 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1595 /* 2878 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1596 /* 2882 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1597 /* 2886 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1598 /* 2890 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1599 /* 2894 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1600 /* 2899 */ // MIs[3] Operand 2
1601 /* 2899 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1602 /* 2910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1603 /* 2914 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1604 /* 2916 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1605 /* 2916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1606 /* 2919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1607 /* 2921 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1608 /* 2925 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1609 /* 2929 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1610 /* 2931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1611 /* 2934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1612 /* 2940 */ GIR_RootConstrainSelectedInstOperands,
1613 /* 2941 */ // GIR_Coverage, 6018,
1614 /* 2941 */ GIR_EraseRootFromParent_Done,
1615 /* 2942 */ // Label 131: @2942
1616 /* 2942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 132*/ GIMT_Encode4(3054), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5982 //
1617 /* 2949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1618 /* 2953 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1619 /* 2957 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1620 /* 2961 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1621 /* 2965 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1622 /* 2969 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1623 /* 2973 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1624 /* 2977 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1625 /* 2981 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1626 /* 2986 */ // MIs[2] Operand 2
1627 /* 2986 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1628 /* 2997 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1629 /* 3001 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1630 /* 3005 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1631 /* 3009 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1632 /* 3013 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1633 /* 3018 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1634 /* 3022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1635 /* 3026 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1636 /* 3028 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1637 /* 3028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1638 /* 3031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1639 /* 3033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1640 /* 3037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1641 /* 3041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1642 /* 3043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1643 /* 3046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1644 /* 3052 */ GIR_RootConstrainSelectedInstOperands,
1645 /* 3053 */ // GIR_Coverage, 5982,
1646 /* 3053 */ GIR_EraseRootFromParent_Done,
1647 /* 3054 */ // Label 132: @3054
1648 /* 3054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 133*/ GIMT_Encode4(3166), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6017 //
1649 /* 3061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1650 /* 3065 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1651 /* 3069 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1652 /* 3073 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1653 /* 3077 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1654 /* 3081 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1655 /* 3085 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1656 /* 3089 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1657 /* 3093 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1658 /* 3098 */ // MIs[2] Operand 2
1659 /* 3098 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1660 /* 3109 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1661 /* 3113 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1662 /* 3117 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1663 /* 3121 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1664 /* 3125 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1665 /* 3130 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1666 /* 3134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1667 /* 3138 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1668 /* 3140 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1669 /* 3140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1670 /* 3143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1671 /* 3145 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1672 /* 3149 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1673 /* 3153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1674 /* 3155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1675 /* 3158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1676 /* 3164 */ GIR_RootConstrainSelectedInstOperands,
1677 /* 3165 */ // GIR_Coverage, 6017,
1678 /* 3165 */ GIR_EraseRootFromParent_Done,
1679 /* 3166 */ // Label 133: @3166
1680 /* 3166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 134*/ GIMT_Encode4(3278), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 190 //
1681 /* 3173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1682 /* 3177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1683 /* 3181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1684 /* 3185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1685 /* 3189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1686 /* 3193 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1687 /* 3197 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1688 /* 3201 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1689 /* 3205 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1690 /* 3209 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1691 /* 3213 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1692 /* 3218 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1693 /* 3222 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1694 /* 3226 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1695 /* 3230 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1696 /* 3234 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1697 /* 3239 */ // MIs[3] Operand 2
1698 /* 3239 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1699 /* 3250 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1700 /* 3252 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1701 /* 3252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
1702 /* 3255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1703 /* 3257 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1704 /* 3261 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1705 /* 3265 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1706 /* 3267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1707 /* 3270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1708 /* 3276 */ GIR_RootConstrainSelectedInstOperands,
1709 /* 3277 */ // GIR_Coverage, 190,
1710 /* 3277 */ GIR_EraseRootFromParent_Done,
1711 /* 3278 */ // Label 134: @3278
1712 /* 3278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 135*/ GIMT_Encode4(3390), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 519 //
1713 /* 3285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1714 /* 3289 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1715 /* 3293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1716 /* 3297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1717 /* 3301 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1718 /* 3305 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1719 /* 3309 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1720 /* 3313 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1721 /* 3317 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1722 /* 3321 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1723 /* 3325 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1724 /* 3330 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1725 /* 3334 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1726 /* 3338 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1727 /* 3342 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1728 /* 3346 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1729 /* 3351 */ // MIs[3] Operand 2
1730 /* 3351 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1731 /* 3362 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1732 /* 3364 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1733 /* 3364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
1734 /* 3367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1735 /* 3369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1736 /* 3373 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1737 /* 3377 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1738 /* 3379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1739 /* 3382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1740 /* 3388 */ GIR_RootConstrainSelectedInstOperands,
1741 /* 3389 */ // GIR_Coverage, 519,
1742 /* 3389 */ GIR_EraseRootFromParent_Done,
1743 /* 3390 */ // Label 135: @3390
1744 /* 3390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 136*/ GIMT_Encode4(3502), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 189 //
1745 /* 3397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1746 /* 3401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1747 /* 3405 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1748 /* 3409 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1749 /* 3413 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1750 /* 3417 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1751 /* 3421 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1752 /* 3425 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1753 /* 3429 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1754 /* 3433 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1755 /* 3438 */ // MIs[2] Operand 2
1756 /* 3438 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1757 /* 3449 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1758 /* 3453 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1759 /* 3457 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1760 /* 3461 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1761 /* 3465 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1762 /* 3470 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1763 /* 3474 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1764 /* 3476 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1765 /* 3476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1766 /* 3479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1767 /* 3481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1768 /* 3485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1769 /* 3489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1770 /* 3491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1771 /* 3494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1772 /* 3500 */ GIR_RootConstrainSelectedInstOperands,
1773 /* 3501 */ // GIR_Coverage, 189,
1774 /* 3501 */ GIR_EraseRootFromParent_Done,
1775 /* 3502 */ // Label 136: @3502
1776 /* 3502 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(3792),
1777 /* 3507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1778 /* 3511 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 138*/ GIMT_Encode4(3619), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 518 //
1779 /* 3518 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1780 /* 3522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1781 /* 3526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1782 /* 3530 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1783 /* 3534 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1784 /* 3538 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1785 /* 3542 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1786 /* 3546 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1787 /* 3550 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1788 /* 3555 */ // MIs[2] Operand 2
1789 /* 3555 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1790 /* 3566 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1791 /* 3570 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1792 /* 3574 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1793 /* 3578 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1794 /* 3582 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1795 /* 3587 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1796 /* 3591 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1797 /* 3593 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1798 /* 3593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1799 /* 3596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1800 /* 3598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1801 /* 3602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1802 /* 3606 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1803 /* 3608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1804 /* 3611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1805 /* 3617 */ GIR_RootConstrainSelectedInstOperands,
1806 /* 3618 */ // GIR_Coverage, 518,
1807 /* 3618 */ GIR_EraseRootFromParent_Done,
1808 /* 3619 */ // Label 138: @3619
1809 /* 3619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 139*/ GIMT_Encode4(3705), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6285 //
1810 /* 3626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1811 /* 3630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1812 /* 3634 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1813 /* 3638 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1814 /* 3642 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1815 /* 3646 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1816 /* 3650 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1817 /* 3654 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1818 /* 3659 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1819 /* 3663 */ // MIs[1] Operand 2
1820 /* 3663 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1821 /* 3674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1822 /* 3678 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1823 /* 3680 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1824 /* 3680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1825 /* 3683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1826 /* 3685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1827 /* 3687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1828 /* 3691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1829 /* 3694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1830 /* 3697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1831 /* 3703 */ GIR_RootConstrainSelectedInstOperands,
1832 /* 3704 */ // GIR_Coverage, 6285,
1833 /* 3704 */ GIR_EraseRootFromParent_Done,
1834 /* 3705 */ // Label 139: @3705
1835 /* 3705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 140*/ GIMT_Encode4(3791), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2301 //
1836 /* 3712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1837 /* 3716 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1838 /* 3720 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1839 /* 3724 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1840 /* 3728 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1841 /* 3732 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1842 /* 3736 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1843 /* 3740 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1844 /* 3744 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1845 /* 3749 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1846 /* 3753 */ // MIs[1] Operand 2
1847 /* 3753 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1848 /* 3764 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1849 /* 3766 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1850 /* 3766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1851 /* 3769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1852 /* 3771 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1853 /* 3773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1854 /* 3777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1855 /* 3780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1856 /* 3783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1857 /* 3789 */ GIR_RootConstrainSelectedInstOperands,
1858 /* 3790 */ // GIR_Coverage, 2301,
1859 /* 3790 */ GIR_EraseRootFromParent_Done,
1860 /* 3791 */ // Label 140: @3791
1861 /* 3791 */ GIM_Reject,
1862 /* 3792 */ // Label 137: @3792
1863 /* 3792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 141*/ GIMT_Encode4(3907), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5981 //
1864 /* 3799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1865 /* 3803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1866 /* 3807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1867 /* 3811 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1868 /* 3815 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1869 /* 3819 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1870 /* 3823 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1871 /* 3827 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1872 /* 3831 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1873 /* 3836 */ // MIs[2] Operand 2
1874 /* 3836 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1875 /* 3847 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1876 /* 3851 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1877 /* 3855 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1878 /* 3859 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1879 /* 3864 */ // MIs[3] Operand 2
1880 /* 3864 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1881 /* 3875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1882 /* 3879 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1883 /* 3881 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1884 /* 3881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1885 /* 3884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1886 /* 3886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1887 /* 3890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1888 /* 3894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1889 /* 3896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1890 /* 3899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1891 /* 3905 */ GIR_RootConstrainSelectedInstOperands,
1892 /* 3906 */ // GIR_Coverage, 5981,
1893 /* 3906 */ GIR_EraseRootFromParent_Done,
1894 /* 3907 */ // Label 141: @3907
1895 /* 3907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 142*/ GIMT_Encode4(4022), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6016 //
1896 /* 3914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1897 /* 3918 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1898 /* 3922 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1899 /* 3926 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1900 /* 3930 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1901 /* 3934 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1902 /* 3938 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1903 /* 3942 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1904 /* 3946 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1905 /* 3951 */ // MIs[2] Operand 2
1906 /* 3951 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1907 /* 3962 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1908 /* 3966 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1909 /* 3970 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1910 /* 3974 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1911 /* 3979 */ // MIs[3] Operand 2
1912 /* 3979 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1913 /* 3990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1914 /* 3994 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1915 /* 3996 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1916 /* 3996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1917 /* 3999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1918 /* 4001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1919 /* 4005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1920 /* 4009 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1921 /* 4011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1922 /* 4014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1923 /* 4020 */ GIR_RootConstrainSelectedInstOperands,
1924 /* 4021 */ // GIR_Coverage, 6016,
1925 /* 4021 */ GIR_EraseRootFromParent_Done,
1926 /* 4022 */ // Label 142: @4022
1927 /* 4022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 143*/ GIMT_Encode4(4137), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 188 //
1928 /* 4029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1929 /* 4033 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1930 /* 4037 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1931 /* 4041 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1932 /* 4045 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1933 /* 4049 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1934 /* 4053 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1935 /* 4057 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1936 /* 4061 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1937 /* 4065 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1938 /* 4070 */ // MIs[2] Operand 2
1939 /* 4070 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1940 /* 4081 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1941 /* 4085 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1942 /* 4089 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1943 /* 4093 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1944 /* 4098 */ // MIs[3] Operand 2
1945 /* 4098 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1946 /* 4109 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1947 /* 4111 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1948 /* 4111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1949 /* 4114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1950 /* 4116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1951 /* 4120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1952 /* 4124 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1953 /* 4126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1954 /* 4129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1955 /* 4135 */ GIR_RootConstrainSelectedInstOperands,
1956 /* 4136 */ // GIR_Coverage, 188,
1957 /* 4136 */ GIR_EraseRootFromParent_Done,
1958 /* 4137 */ // Label 143: @4137
1959 /* 4137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 144*/ GIMT_Encode4(4252), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 517 //
1960 /* 4144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1961 /* 4148 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1962 /* 4152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1963 /* 4156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1964 /* 4160 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1965 /* 4164 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1966 /* 4168 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1967 /* 4172 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1968 /* 4176 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1969 /* 4180 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1970 /* 4185 */ // MIs[2] Operand 2
1971 /* 4185 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1972 /* 4196 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1973 /* 4200 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1974 /* 4204 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1975 /* 4208 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1976 /* 4213 */ // MIs[3] Operand 2
1977 /* 4213 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1978 /* 4224 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1979 /* 4226 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1980 /* 4226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1981 /* 4229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1982 /* 4231 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1983 /* 4235 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1984 /* 4239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1985 /* 4241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1986 /* 4244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1987 /* 4250 */ GIR_RootConstrainSelectedInstOperands,
1988 /* 4251 */ // GIR_Coverage, 517,
1989 /* 4251 */ GIR_EraseRootFromParent_Done,
1990 /* 4252 */ // Label 144: @4252
1991 /* 4252 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(4756),
1992 /* 4257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1993 /* 4261 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(4508),
1994 /* 4266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1995 /* 4270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 147*/ GIMT_Encode4(4349), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3639 //
1996 /* 4277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1997 /* 4281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
1998 /* 4285 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1999 /* 4289 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2000 /* 4293 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2001 /* 4297 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2002 /* 4301 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2003 /* 4305 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2004 /* 4310 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2005 /* 4315 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2006 /* 4317 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
2007 /* 4317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
2008 /* 4320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2009 /* 4322 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2010 /* 4324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2011 /* 4328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2012 /* 4332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2013 /* 4335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2014 /* 4341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2015 /* 4347 */ GIR_RootConstrainSelectedInstOperands,
2016 /* 4348 */ // GIR_Coverage, 3639,
2017 /* 4348 */ GIR_EraseRootFromParent_Done,
2018 /* 4349 */ // Label 147: @4349
2019 /* 4349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 148*/ GIMT_Encode4(4428), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3640 //
2020 /* 4356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2021 /* 4360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2022 /* 4364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2023 /* 4368 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2024 /* 4372 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2025 /* 4376 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2026 /* 4380 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2027 /* 4384 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2028 /* 4389 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2029 /* 4394 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2030 /* 4396 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2031 /* 4396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2032 /* 4399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2033 /* 4401 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2034 /* 4403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2035 /* 4407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2036 /* 4411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2037 /* 4414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2038 /* 4420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2039 /* 4426 */ GIR_RootConstrainSelectedInstOperands,
2040 /* 4427 */ // GIR_Coverage, 3640,
2041 /* 4427 */ GIR_EraseRootFromParent_Done,
2042 /* 4428 */ // Label 148: @4428
2043 /* 4428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 149*/ GIMT_Encode4(4507), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3643 //
2044 /* 4435 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2045 /* 4439 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2046 /* 4443 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2047 /* 4447 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2048 /* 4451 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2049 /* 4455 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2050 /* 4459 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2051 /* 4463 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2052 /* 4468 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2053 /* 4473 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2054 /* 4475 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2055 /* 4475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2056 /* 4478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2057 /* 4480 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2058 /* 4482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2059 /* 4486 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2060 /* 4490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2061 /* 4493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2062 /* 4499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2063 /* 4505 */ GIR_RootConstrainSelectedInstOperands,
2064 /* 4506 */ // GIR_Coverage, 3643,
2065 /* 4506 */ GIR_EraseRootFromParent_Done,
2066 /* 4507 */ // Label 149: @4507
2067 /* 4507 */ GIM_Reject,
2068 /* 4508 */ // Label 146: @4508
2069 /* 4508 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(4755),
2070 /* 4513 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2071 /* 4517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 151*/ GIMT_Encode4(4596), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6586 //
2072 /* 4524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2073 /* 4528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2074 /* 4532 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2075 /* 4536 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2076 /* 4540 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2077 /* 4544 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2078 /* 4548 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2079 /* 4552 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2080 /* 4557 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2081 /* 4562 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2082 /* 4564 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
2083 /* 4564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
2084 /* 4567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2085 /* 4569 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2086 /* 4571 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2087 /* 4575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2088 /* 4579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2089 /* 4582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2090 /* 4588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2091 /* 4594 */ GIR_RootConstrainSelectedInstOperands,
2092 /* 4595 */ // GIR_Coverage, 6586,
2093 /* 4595 */ GIR_EraseRootFromParent_Done,
2094 /* 4596 */ // Label 151: @4596
2095 /* 4596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 152*/ GIMT_Encode4(4675), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6587 //
2096 /* 4603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2097 /* 4607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2098 /* 4611 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2099 /* 4615 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2100 /* 4619 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2101 /* 4623 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2102 /* 4627 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2103 /* 4631 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2104 /* 4636 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2105 /* 4641 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2106 /* 4643 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2107 /* 4643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2108 /* 4646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2109 /* 4648 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2110 /* 4650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2111 /* 4654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2112 /* 4658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2113 /* 4661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2114 /* 4667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2115 /* 4673 */ GIR_RootConstrainSelectedInstOperands,
2116 /* 4674 */ // GIR_Coverage, 6587,
2117 /* 4674 */ GIR_EraseRootFromParent_Done,
2118 /* 4675 */ // Label 152: @4675
2119 /* 4675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 153*/ GIMT_Encode4(4754), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6590 //
2120 /* 4682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2121 /* 4686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2122 /* 4690 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2123 /* 4694 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2124 /* 4698 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2125 /* 4702 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2126 /* 4706 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2127 /* 4710 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2128 /* 4715 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2129 /* 4720 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2130 /* 4722 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2131 /* 4722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2132 /* 4725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2133 /* 4727 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2134 /* 4729 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2135 /* 4733 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2136 /* 4737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2137 /* 4740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2138 /* 4746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2139 /* 4752 */ GIR_RootConstrainSelectedInstOperands,
2140 /* 4753 */ // GIR_Coverage, 6590,
2141 /* 4753 */ GIR_EraseRootFromParent_Done,
2142 /* 4754 */ // Label 153: @4754
2143 /* 4754 */ GIM_Reject,
2144 /* 4755 */ // Label 150: @4755
2145 /* 4755 */ GIM_Reject,
2146 /* 4756 */ // Label 145: @4756
2147 /* 4756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 154*/ GIMT_Encode4(4812), GIMT_Encode2(GIFBS_IsARM), // Rule ID 71 //
2148 /* 4763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2149 /* 4767 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2150 /* 4771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2151 /* 4775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2152 /* 4779 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
2153 /* 4783 */ // MIs[1] Operand 1
2154 /* 4783 */ // No operand predicates
2155 /* 4783 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2156 /* 4785 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2157 /* 4785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri),
2158 /* 4788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2159 /* 4790 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2160 /* 4792 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2161 /* 4795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2162 /* 4798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2163 /* 4804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2164 /* 4810 */ GIR_RootConstrainSelectedInstOperands,
2165 /* 4811 */ // GIR_Coverage, 71,
2166 /* 4811 */ GIR_EraseRootFromParent_Done,
2167 /* 4812 */ // Label 154: @4812
2168 /* 4812 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(4922),
2169 /* 4817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2170 /* 4821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2171 /* 4825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 156*/ GIMT_Encode4(4873), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 302 //
2172 /* 4832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2173 /* 4836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2174 /* 4840 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
2175 /* 4844 */ // MIs[1] Operand 1
2176 /* 4844 */ // No operand predicates
2177 /* 4844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2178 /* 4846 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3)
2179 /* 4846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3),
2180 /* 4849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2181 /* 4851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2182 /* 4857 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2183 /* 4859 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3
2184 /* 4862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2185 /* 4865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2186 /* 4871 */ GIR_RootConstrainSelectedInstOperands,
2187 /* 4872 */ // GIR_Coverage, 302,
2188 /* 4872 */ GIR_EraseRootFromParent_Done,
2189 /* 4873 */ // Label 156: @4873
2190 /* 4873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 157*/ GIMT_Encode4(4921), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 303 //
2191 /* 4880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2192 /* 4884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2193 /* 4888 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
2194 /* 4892 */ // MIs[1] Operand 1
2195 /* 4892 */ // No operand predicates
2196 /* 4892 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2197 /* 4894 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8)
2198 /* 4894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8),
2199 /* 4897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2200 /* 4899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2201 /* 4905 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2202 /* 4907 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
2203 /* 4910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2204 /* 4913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2205 /* 4919 */ GIR_RootConstrainSelectedInstOperands,
2206 /* 4920 */ // GIR_Coverage, 303,
2207 /* 4920 */ GIR_EraseRootFromParent_Done,
2208 /* 4921 */ // Label 157: @4921
2209 /* 4921 */ GIM_Reject,
2210 /* 4922 */ // Label 155: @4922
2211 /* 4922 */ GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(5030),
2212 /* 4927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2213 /* 4931 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 159*/ GIMT_Encode4(4983), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 406 //
2214 /* 4938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2215 /* 4942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2216 /* 4946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2217 /* 4950 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
2218 /* 4954 */ // MIs[1] Operand 1
2219 /* 4954 */ // No operand predicates
2220 /* 4954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2221 /* 4956 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2222 /* 4956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri),
2223 /* 4959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2224 /* 4961 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2225 /* 4963 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2226 /* 4966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2227 /* 4969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2228 /* 4975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2229 /* 4981 */ GIR_RootConstrainSelectedInstOperands,
2230 /* 4982 */ // GIR_Coverage, 406,
2231 /* 4982 */ GIR_EraseRootFromParent_Done,
2232 /* 4983 */ // Label 159: @4983
2233 /* 4983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 160*/ GIMT_Encode4(5029), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 407 //
2234 /* 4990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2235 /* 4994 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2236 /* 4998 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2237 /* 5002 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
2238 /* 5006 */ // MIs[1] Operand 1
2239 /* 5006 */ // No operand predicates
2240 /* 5006 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2241 /* 5008 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2242 /* 5008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12),
2243 /* 5011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2244 /* 5013 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2245 /* 5015 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2246 /* 5018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2247 /* 5021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2248 /* 5027 */ GIR_RootConstrainSelectedInstOperands,
2249 /* 5028 */ // GIR_Coverage, 407,
2250 /* 5028 */ GIR_EraseRootFromParent_Done,
2251 /* 5029 */ // Label 160: @5029
2252 /* 5029 */ GIM_Reject,
2253 /* 5030 */ // Label 158: @5030
2254 /* 5030 */ GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(5178),
2255 /* 5035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2256 /* 5039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2257 /* 5043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 162*/ GIMT_Encode4(5110), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 170 //
2258 /* 5050 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2259 /* 5054 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2260 /* 5058 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2261 /* 5062 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2262 /* 5066 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2263 /* 5071 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2264 /* 5076 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2265 /* 5078 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2266 /* 5078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2267 /* 5081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2268 /* 5083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2269 /* 5087 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2270 /* 5091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2271 /* 5093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2272 /* 5096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2273 /* 5102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2274 /* 5108 */ GIR_RootConstrainSelectedInstOperands,
2275 /* 5109 */ // GIR_Coverage, 170,
2276 /* 5109 */ GIR_EraseRootFromParent_Done,
2277 /* 5110 */ // Label 162: @5110
2278 /* 5110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 163*/ GIMT_Encode4(5177), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 171 //
2279 /* 5117 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2280 /* 5121 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2281 /* 5125 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2282 /* 5129 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2283 /* 5133 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2284 /* 5138 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2285 /* 5143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2286 /* 5145 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2287 /* 5145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2288 /* 5148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2289 /* 5150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2290 /* 5154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2291 /* 5158 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2292 /* 5160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2293 /* 5163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2294 /* 5169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2295 /* 5175 */ GIR_RootConstrainSelectedInstOperands,
2296 /* 5176 */ // GIR_Coverage, 171,
2297 /* 5176 */ GIR_EraseRootFromParent_Done,
2298 /* 5177 */ // Label 163: @5177
2299 /* 5177 */ GIM_Reject,
2300 /* 5178 */ // Label 161: @5178
2301 /* 5178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 164*/ GIMT_Encode4(5247), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 502 //
2302 /* 5185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2303 /* 5189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2304 /* 5193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2305 /* 5197 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2306 /* 5201 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2307 /* 5205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2308 /* 5210 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2309 /* 5215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2310 /* 5219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2311 /* 5221 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2312 /* 5221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2313 /* 5224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2314 /* 5226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2315 /* 5230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2316 /* 5234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2317 /* 5236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2318 /* 5239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2319 /* 5245 */ GIR_RootConstrainSelectedInstOperands,
2320 /* 5246 */ // GIR_Coverage, 502,
2321 /* 5246 */ GIR_EraseRootFromParent_Done,
2322 /* 5247 */ // Label 164: @5247
2323 /* 5247 */ GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(5385),
2324 /* 5252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2325 /* 5256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2326 /* 5260 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 166*/ GIMT_Encode4(5322), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6277 //
2327 /* 5267 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2328 /* 5271 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2329 /* 5275 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2330 /* 5279 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2331 /* 5284 */ // MIs[1] Operand 2
2332 /* 5284 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2333 /* 5295 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2334 /* 5297 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2335 /* 5297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2336 /* 5300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2337 /* 5302 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2338 /* 5304 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2339 /* 5308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2340 /* 5311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2341 /* 5314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2342 /* 5320 */ GIR_RootConstrainSelectedInstOperands,
2343 /* 5321 */ // GIR_Coverage, 6277,
2344 /* 5321 */ GIR_EraseRootFromParent_Done,
2345 /* 5322 */ // Label 166: @5322
2346 /* 5322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 167*/ GIMT_Encode4(5384), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6278 //
2347 /* 5329 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2348 /* 5333 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2349 /* 5337 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2350 /* 5341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2351 /* 5346 */ // MIs[1] Operand 2
2352 /* 5346 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2353 /* 5357 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2354 /* 5359 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2355 /* 5359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2356 /* 5362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2357 /* 5364 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2358 /* 5366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2359 /* 5370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2360 /* 5373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2361 /* 5376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2362 /* 5382 */ GIR_RootConstrainSelectedInstOperands,
2363 /* 5383 */ // GIR_Coverage, 6278,
2364 /* 5383 */ GIR_EraseRootFromParent_Done,
2365 /* 5384 */ // Label 167: @5384
2366 /* 5384 */ GIM_Reject,
2367 /* 5385 */ // Label 165: @5385
2368 /* 5385 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(5523),
2369 /* 5390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2370 /* 5394 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2371 /* 5398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 169*/ GIMT_Encode4(5460), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6316 //
2372 /* 5405 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2373 /* 5409 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2374 /* 5413 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2375 /* 5417 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2376 /* 5422 */ // MIs[1] Operand 2
2377 /* 5422 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2378 /* 5433 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2379 /* 5435 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2380 /* 5435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2381 /* 5438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2382 /* 5440 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2383 /* 5442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2384 /* 5446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2385 /* 5449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2386 /* 5452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2387 /* 5458 */ GIR_RootConstrainSelectedInstOperands,
2388 /* 5459 */ // GIR_Coverage, 6316,
2389 /* 5459 */ GIR_EraseRootFromParent_Done,
2390 /* 5460 */ // Label 169: @5460
2391 /* 5460 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 170*/ GIMT_Encode4(5522), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6317 //
2392 /* 5467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2393 /* 5471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2394 /* 5475 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2395 /* 5479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2396 /* 5484 */ // MIs[1] Operand 2
2397 /* 5484 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2398 /* 5495 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2399 /* 5497 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2400 /* 5497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2401 /* 5500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2402 /* 5502 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2403 /* 5504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2404 /* 5508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2405 /* 5511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2406 /* 5514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2407 /* 5520 */ GIR_RootConstrainSelectedInstOperands,
2408 /* 5521 */ // GIR_Coverage, 6317,
2409 /* 5521 */ GIR_EraseRootFromParent_Done,
2410 /* 5522 */ // Label 170: @5522
2411 /* 5522 */ GIM_Reject,
2412 /* 5523 */ // Label 168: @5523
2413 /* 5523 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 171*/ GIMT_Encode4(5592), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 179 //
2414 /* 5530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2415 /* 5534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2416 /* 5538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2417 /* 5542 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2418 /* 5546 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2419 /* 5550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2420 /* 5555 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2421 /* 5560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2422 /* 5564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2423 /* 5566 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2424 /* 5566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2425 /* 5569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2426 /* 5571 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2427 /* 5575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2428 /* 5579 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2429 /* 5581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2430 /* 5584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2431 /* 5590 */ GIR_RootConstrainSelectedInstOperands,
2432 /* 5591 */ // GIR_Coverage, 179,
2433 /* 5591 */ GIR_EraseRootFromParent_Done,
2434 /* 5592 */ // Label 171: @5592
2435 /* 5592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 172*/ GIMT_Encode4(5661), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 508 //
2436 /* 5599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2437 /* 5603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2438 /* 5607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2439 /* 5611 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2440 /* 5615 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2441 /* 5619 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2442 /* 5624 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2443 /* 5629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2444 /* 5633 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2445 /* 5635 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2446 /* 5635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2447 /* 5638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2448 /* 5640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2449 /* 5644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2450 /* 5648 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2451 /* 5650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2452 /* 5653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2453 /* 5659 */ GIR_RootConstrainSelectedInstOperands,
2454 /* 5660 */ // GIR_Coverage, 508,
2455 /* 5660 */ GIR_EraseRootFromParent_Done,
2456 /* 5661 */ // Label 172: @5661
2457 /* 5661 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(5837),
2458 /* 5666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2459 /* 5670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2460 /* 5674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 174*/ GIMT_Encode4(5728), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3444 //
2461 /* 5681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2462 /* 5685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2463 /* 5689 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2464 /* 5693 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2465 /* 5698 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2466 /* 5700 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2467 /* 5700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2468 /* 5703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2469 /* 5705 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2470 /* 5707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2471 /* 5711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2472 /* 5714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2473 /* 5720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2474 /* 5726 */ GIR_RootConstrainSelectedInstOperands,
2475 /* 5727 */ // GIR_Coverage, 3444,
2476 /* 5727 */ GIR_EraseRootFromParent_Done,
2477 /* 5728 */ // Label 174: @5728
2478 /* 5728 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 175*/ GIMT_Encode4(5782), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3472 //
2479 /* 5735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2480 /* 5739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2481 /* 5743 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2482 /* 5747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2483 /* 5752 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2484 /* 5754 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2485 /* 5754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2486 /* 5757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2487 /* 5759 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2488 /* 5761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2489 /* 5765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2490 /* 5768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2491 /* 5774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2492 /* 5780 */ GIR_RootConstrainSelectedInstOperands,
2493 /* 5781 */ // GIR_Coverage, 3472,
2494 /* 5781 */ GIR_EraseRootFromParent_Done,
2495 /* 5782 */ // Label 175: @5782
2496 /* 5782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 176*/ GIMT_Encode4(5836), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3482 //
2497 /* 5789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2498 /* 5793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2499 /* 5797 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2500 /* 5801 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2501 /* 5806 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2502 /* 5808 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2503 /* 5808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2504 /* 5811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2505 /* 5813 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2506 /* 5815 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2507 /* 5819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2508 /* 5822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2509 /* 5828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2510 /* 5834 */ GIR_RootConstrainSelectedInstOperands,
2511 /* 5835 */ // GIR_Coverage, 3482,
2512 /* 5835 */ GIR_EraseRootFromParent_Done,
2513 /* 5836 */ // Label 176: @5836
2514 /* 5836 */ GIM_Reject,
2515 /* 5837 */ // Label 173: @5837
2516 /* 5837 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(5985),
2517 /* 5842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2518 /* 5846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2519 /* 5850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 178*/ GIMT_Encode4(5917), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5978 //
2520 /* 5857 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2521 /* 5861 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2522 /* 5865 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2523 /* 5869 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2524 /* 5873 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2525 /* 5878 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2526 /* 5883 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2527 /* 5885 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2528 /* 5885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2529 /* 5888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2530 /* 5890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2531 /* 5894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2532 /* 5898 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2533 /* 5900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2534 /* 5903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2535 /* 5909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2536 /* 5915 */ GIR_RootConstrainSelectedInstOperands,
2537 /* 5916 */ // GIR_Coverage, 5978,
2538 /* 5916 */ GIR_EraseRootFromParent_Done,
2539 /* 5917 */ // Label 178: @5917
2540 /* 5917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 179*/ GIMT_Encode4(5984), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 5979 //
2541 /* 5924 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2542 /* 5928 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2543 /* 5932 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2544 /* 5936 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2545 /* 5940 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2546 /* 5945 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2547 /* 5950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2548 /* 5952 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2549 /* 5952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2550 /* 5955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2551 /* 5957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2552 /* 5961 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2553 /* 5965 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2554 /* 5967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2555 /* 5970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2556 /* 5976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2557 /* 5982 */ GIR_RootConstrainSelectedInstOperands,
2558 /* 5983 */ // GIR_Coverage, 5979,
2559 /* 5983 */ GIR_EraseRootFromParent_Done,
2560 /* 5984 */ // Label 179: @5984
2561 /* 5984 */ GIM_Reject,
2562 /* 5985 */ // Label 177: @5985
2563 /* 5985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 180*/ GIMT_Encode4(6054), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 6014 //
2564 /* 5992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2565 /* 5996 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2566 /* 6000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2567 /* 6004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2568 /* 6008 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2569 /* 6012 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2570 /* 6016 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2571 /* 6021 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2572 /* 6026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2573 /* 6028 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2574 /* 6028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2575 /* 6031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2576 /* 6033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2577 /* 6037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2578 /* 6041 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2579 /* 6043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2580 /* 6046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2581 /* 6052 */ GIR_RootConstrainSelectedInstOperands,
2582 /* 6053 */ // GIR_Coverage, 6014,
2583 /* 6053 */ GIR_EraseRootFromParent_Done,
2584 /* 6054 */ // Label 180: @6054
2585 /* 6054 */ GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(6192),
2586 /* 6059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2587 /* 6063 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2588 /* 6067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 182*/ GIMT_Encode4(6129), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2199 //
2589 /* 6074 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2590 /* 6078 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2591 /* 6082 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2592 /* 6086 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2593 /* 6091 */ // MIs[1] Operand 2
2594 /* 6091 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2595 /* 6102 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2596 /* 6104 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2597 /* 6104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2598 /* 6107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2599 /* 6109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2600 /* 6111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2601 /* 6115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2602 /* 6118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2603 /* 6121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2604 /* 6127 */ GIR_RootConstrainSelectedInstOperands,
2605 /* 6128 */ // GIR_Coverage, 2199,
2606 /* 6128 */ GIR_EraseRootFromParent_Done,
2607 /* 6129 */ // Label 182: @6129
2608 /* 6129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 183*/ GIMT_Encode4(6191), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2200 //
2609 /* 6136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2610 /* 6140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2611 /* 6144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2612 /* 6148 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2613 /* 6153 */ // MIs[1] Operand 2
2614 /* 6153 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2615 /* 6164 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2616 /* 6166 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2617 /* 6166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2618 /* 6169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2619 /* 6171 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2620 /* 6173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2621 /* 6177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2622 /* 6180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2623 /* 6183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2624 /* 6189 */ GIR_RootConstrainSelectedInstOperands,
2625 /* 6190 */ // GIR_Coverage, 2200,
2626 /* 6190 */ GIR_EraseRootFromParent_Done,
2627 /* 6191 */ // Label 183: @6191
2628 /* 6191 */ GIM_Reject,
2629 /* 6192 */ // Label 181: @6192
2630 /* 6192 */ GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(6330),
2631 /* 6197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2632 /* 6201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2633 /* 6205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 185*/ GIMT_Encode4(6267), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2443 //
2634 /* 6212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2635 /* 6216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2636 /* 6220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2637 /* 6224 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2638 /* 6229 */ // MIs[1] Operand 2
2639 /* 6229 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2640 /* 6240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2641 /* 6242 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2642 /* 6242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2643 /* 6245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2644 /* 6247 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2645 /* 6249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2646 /* 6253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2647 /* 6256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2648 /* 6259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2649 /* 6265 */ GIR_RootConstrainSelectedInstOperands,
2650 /* 6266 */ // GIR_Coverage, 2443,
2651 /* 6266 */ GIR_EraseRootFromParent_Done,
2652 /* 6267 */ // Label 185: @6267
2653 /* 6267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 186*/ GIMT_Encode4(6329), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2444 //
2654 /* 6274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2655 /* 6278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2656 /* 6282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2657 /* 6286 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2658 /* 6291 */ // MIs[1] Operand 2
2659 /* 6291 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2660 /* 6302 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2661 /* 6304 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2662 /* 6304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2663 /* 6307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2664 /* 6309 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2665 /* 6311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2666 /* 6315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2667 /* 6318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2668 /* 6321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2669 /* 6327 */ GIR_RootConstrainSelectedInstOperands,
2670 /* 6328 */ // GIR_Coverage, 2444,
2671 /* 6328 */ GIR_EraseRootFromParent_Done,
2672 /* 6329 */ // Label 186: @6329
2673 /* 6329 */ GIM_Reject,
2674 /* 6330 */ // Label 184: @6330
2675 /* 6330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 187*/ GIMT_Encode4(6399), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5980 //
2676 /* 6337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2677 /* 6341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2678 /* 6345 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2679 /* 6349 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2680 /* 6353 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2681 /* 6357 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2682 /* 6361 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2683 /* 6366 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2684 /* 6371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2685 /* 6373 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2686 /* 6373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2687 /* 6376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2688 /* 6378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2689 /* 6382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2690 /* 6386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2691 /* 6388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2692 /* 6391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2693 /* 6397 */ GIR_RootConstrainSelectedInstOperands,
2694 /* 6398 */ // GIR_Coverage, 5980,
2695 /* 6398 */ GIR_EraseRootFromParent_Done,
2696 /* 6399 */ // Label 187: @6399
2697 /* 6399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 188*/ GIMT_Encode4(6468), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6015 //
2698 /* 6406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2699 /* 6410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2700 /* 6414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2701 /* 6418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2702 /* 6422 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2703 /* 6426 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2704 /* 6430 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2705 /* 6435 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2706 /* 6440 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2707 /* 6442 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2708 /* 6442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2709 /* 6445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2710 /* 6447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2711 /* 6451 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2712 /* 6455 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2713 /* 6457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2714 /* 6460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2715 /* 6466 */ GIR_RootConstrainSelectedInstOperands,
2716 /* 6467 */ // GIR_Coverage, 6015,
2717 /* 6467 */ GIR_EraseRootFromParent_Done,
2718 /* 6468 */ // Label 188: @6468
2719 /* 6468 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(6644),
2720 /* 6473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2721 /* 6477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2722 /* 6481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 190*/ GIMT_Encode4(6535), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6562 //
2723 /* 6488 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2724 /* 6492 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2725 /* 6496 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2726 /* 6500 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2727 /* 6505 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2728 /* 6507 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2729 /* 6507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2730 /* 6510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2731 /* 6512 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2732 /* 6514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2733 /* 6518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2734 /* 6521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2735 /* 6527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2736 /* 6533 */ GIR_RootConstrainSelectedInstOperands,
2737 /* 6534 */ // GIR_Coverage, 6562,
2738 /* 6534 */ GIR_EraseRootFromParent_Done,
2739 /* 6535 */ // Label 190: @6535
2740 /* 6535 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 191*/ GIMT_Encode4(6589), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6576 //
2741 /* 6542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2742 /* 6546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2743 /* 6550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2744 /* 6554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2745 /* 6559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2746 /* 6561 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2747 /* 6561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2748 /* 6564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2749 /* 6566 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2750 /* 6568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2751 /* 6572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2752 /* 6575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2753 /* 6581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2754 /* 6587 */ GIR_RootConstrainSelectedInstOperands,
2755 /* 6588 */ // GIR_Coverage, 6576,
2756 /* 6588 */ GIR_EraseRootFromParent_Done,
2757 /* 6589 */ // Label 191: @6589
2758 /* 6589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 192*/ GIMT_Encode4(6643), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6581 //
2759 /* 6596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2760 /* 6600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2761 /* 6604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2762 /* 6608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2763 /* 6613 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2764 /* 6615 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2765 /* 6615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2766 /* 6618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2767 /* 6620 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2768 /* 6622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2769 /* 6626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2770 /* 6629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2771 /* 6635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2772 /* 6641 */ GIR_RootConstrainSelectedInstOperands,
2773 /* 6642 */ // GIR_Coverage, 6581,
2774 /* 6642 */ GIR_EraseRootFromParent_Done,
2775 /* 6643 */ // Label 192: @6643
2776 /* 6643 */ GIM_Reject,
2777 /* 6644 */ // Label 189: @6644
2778 /* 6644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 193*/ GIMT_Encode4(6689), GIMT_Encode2(GIFBS_IsARM), // Rule ID 72 //
2779 /* 6651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2780 /* 6655 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2781 /* 6659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2782 /* 6663 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
2783 /* 6663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr),
2784 /* 6666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2785 /* 6668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2786 /* 6670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2787 /* 6672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2788 /* 6675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2789 /* 6681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2790 /* 6687 */ GIR_RootConstrainSelectedInstOperands,
2791 /* 6688 */ // GIR_Coverage, 72,
2792 /* 6688 */ GIR_EraseRootFromParent_Done,
2793 /* 6689 */ // Label 193: @6689
2794 /* 6689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 194*/ GIMT_Encode4(6734), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 304 //
2795 /* 6696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2796 /* 6700 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2797 /* 6704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2798 /* 6708 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
2799 /* 6708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr),
2800 /* 6711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2801 /* 6713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2802 /* 6719 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2803 /* 6721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2804 /* 6723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2805 /* 6726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2806 /* 6732 */ GIR_RootConstrainSelectedInstOperands,
2807 /* 6733 */ // GIR_Coverage, 304,
2808 /* 6733 */ GIR_EraseRootFromParent_Done,
2809 /* 6734 */ // Label 194: @6734
2810 /* 6734 */ GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(6826),
2811 /* 6739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2812 /* 6743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 196*/ GIMT_Encode4(6784), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 408 //
2813 /* 6750 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2814 /* 6754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2815 /* 6758 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2816 /* 6758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2817 /* 6761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2818 /* 6763 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2819 /* 6765 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2820 /* 6767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2821 /* 6770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2822 /* 6776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2823 /* 6782 */ GIR_RootConstrainSelectedInstOperands,
2824 /* 6783 */ // GIR_Coverage, 408,
2825 /* 6783 */ GIR_EraseRootFromParent_Done,
2826 /* 6784 */ // Label 196: @6784
2827 /* 6784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 197*/ GIMT_Encode4(6825), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5996 //
2828 /* 6791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2829 /* 6795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2830 /* 6799 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2831 /* 6799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2832 /* 6802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2833 /* 6804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2834 /* 6806 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2835 /* 6808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2836 /* 6811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2837 /* 6817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2838 /* 6823 */ GIR_RootConstrainSelectedInstOperands,
2839 /* 6824 */ // GIR_Coverage, 5996,
2840 /* 6824 */ GIR_EraseRootFromParent_Done,
2841 /* 6825 */ // Label 197: @6825
2842 /* 6825 */ GIM_Reject,
2843 /* 6826 */ // Label 195: @6826
2844 /* 6826 */ GIM_Reject,
2845 /* 6827 */ // Label 106: @6827
2846 /* 6827 */ GIM_Reject,
2847 /* 6828 */ // Label 97: @6828
2848 /* 6828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 198*/ GIMT_Encode4(6873), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 882 //
2849 /* 6835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2850 /* 6838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2851 /* 6841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2852 /* 6845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2853 /* 6849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2854 /* 6853 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
2855 /* 6853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64),
2856 /* 6856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2857 /* 6858 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
2858 /* 6860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
2859 /* 6862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2860 /* 6865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2861 /* 6871 */ GIR_RootConstrainSelectedInstOperands,
2862 /* 6872 */ // GIR_Coverage, 882,
2863 /* 6872 */ GIR_EraseRootFromParent_Done,
2864 /* 6873 */ // Label 198: @6873
2865 /* 6873 */ GIM_Reject,
2866 /* 6874 */ // Label 98: @6874
2867 /* 6874 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(7307),
2868 /* 6879 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
2869 /* 6882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
2870 /* 6885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2871 /* 6889 */ GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(7082),
2872 /* 6894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2873 /* 6898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 201*/ GIMT_Encode4(6959), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6200 //
2874 /* 6905 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2875 /* 6909 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2876 /* 6913 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2877 /* 6917 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2878 /* 6921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2879 /* 6926 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2880 /* 6931 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2881 /* 6933 */ // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2882 /* 6933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
2883 /* 6936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2884 /* 6938 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2885 /* 6940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2886 /* 6944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2887 /* 6948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2888 /* 6951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2889 /* 6957 */ GIR_RootConstrainSelectedInstOperands,
2890 /* 6958 */ // GIR_Coverage, 6200,
2891 /* 6958 */ GIR_EraseRootFromParent_Done,
2892 /* 6959 */ // Label 201: @6959
2893 /* 6959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 202*/ GIMT_Encode4(7020), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6206 //
2894 /* 6966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2895 /* 6970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2896 /* 6974 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2897 /* 6978 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2898 /* 6982 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2899 /* 6987 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2900 /* 6992 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2901 /* 6994 */ // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2902 /* 6994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
2903 /* 6997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2904 /* 6999 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2905 /* 7001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2906 /* 7005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2907 /* 7009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2908 /* 7012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2909 /* 7018 */ GIR_RootConstrainSelectedInstOperands,
2910 /* 7019 */ // GIR_Coverage, 6206,
2911 /* 7019 */ GIR_EraseRootFromParent_Done,
2912 /* 7020 */ // Label 202: @7020
2913 /* 7020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 203*/ GIMT_Encode4(7081), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6088 //
2914 /* 7027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2915 /* 7031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2916 /* 7035 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2917 /* 7039 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2918 /* 7043 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2919 /* 7048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2920 /* 7053 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2921 /* 7055 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2922 /* 7055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
2923 /* 7058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2924 /* 7060 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2925 /* 7062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2926 /* 7066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2927 /* 7070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2928 /* 7073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2929 /* 7079 */ GIR_RootConstrainSelectedInstOperands,
2930 /* 7080 */ // GIR_Coverage, 6088,
2931 /* 7080 */ GIR_EraseRootFromParent_Done,
2932 /* 7081 */ // Label 203: @7081
2933 /* 7081 */ GIM_Reject,
2934 /* 7082 */ // Label 200: @7082
2935 /* 7082 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(7306),
2936 /* 7087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2937 /* 7091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 205*/ GIMT_Encode4(7152), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1341 //
2938 /* 7098 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2939 /* 7102 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2940 /* 7106 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2941 /* 7110 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2942 /* 7114 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2943 /* 7119 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2944 /* 7124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2945 /* 7126 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2946 /* 7126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
2947 /* 7129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2948 /* 7131 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2949 /* 7133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2950 /* 7137 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2951 /* 7141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2952 /* 7144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2953 /* 7150 */ GIR_RootConstrainSelectedInstOperands,
2954 /* 7151 */ // GIR_Coverage, 1341,
2955 /* 7151 */ GIR_EraseRootFromParent_Done,
2956 /* 7152 */ // Label 205: @7152
2957 /* 7152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 206*/ GIMT_Encode4(7213), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1347 //
2958 /* 7159 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2959 /* 7163 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2960 /* 7167 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2961 /* 7171 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2962 /* 7175 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2963 /* 7180 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2964 /* 7185 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2965 /* 7187 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2966 /* 7187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
2967 /* 7190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2968 /* 7192 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2969 /* 7194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2970 /* 7198 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2971 /* 7202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2972 /* 7205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2973 /* 7211 */ GIR_RootConstrainSelectedInstOperands,
2974 /* 7212 */ // GIR_Coverage, 1347,
2975 /* 7212 */ GIR_EraseRootFromParent_Done,
2976 /* 7213 */ // Label 206: @7213
2977 /* 7213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 207*/ GIMT_Encode4(7274), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1007 //
2978 /* 7220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2979 /* 7224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2980 /* 7228 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2981 /* 7232 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2982 /* 7236 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2983 /* 7241 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2984 /* 7246 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2985 /* 7248 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2986 /* 7248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
2987 /* 7251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2988 /* 7253 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2989 /* 7255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2990 /* 7259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2991 /* 7263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2992 /* 7266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2993 /* 7272 */ GIR_RootConstrainSelectedInstOperands,
2994 /* 7273 */ // GIR_Coverage, 1007,
2995 /* 7273 */ GIR_EraseRootFromParent_Done,
2996 /* 7274 */ // Label 207: @7274
2997 /* 7274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 208*/ GIMT_Encode4(7305), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 876 //
2998 /* 7281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2999 /* 7285 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3000 /* 7285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8),
3001 /* 7288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3002 /* 7290 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3003 /* 7292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3004 /* 7294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3005 /* 7297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3006 /* 7303 */ GIR_RootConstrainSelectedInstOperands,
3007 /* 7304 */ // GIR_Coverage, 876,
3008 /* 7304 */ GIR_EraseRootFromParent_Done,
3009 /* 7305 */ // Label 208: @7305
3010 /* 7305 */ GIM_Reject,
3011 /* 7306 */ // Label 204: @7306
3012 /* 7306 */ GIM_Reject,
3013 /* 7307 */ // Label 199: @7307
3014 /* 7307 */ GIM_Reject,
3015 /* 7308 */ // Label 99: @7308
3016 /* 7308 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(7807),
3017 /* 7313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3018 /* 7316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
3019 /* 7319 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(7746),
3020 /* 7324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3021 /* 7328 */ GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(7521),
3022 /* 7333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3023 /* 7337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 212*/ GIMT_Encode4(7398), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6203 //
3024 /* 7344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3025 /* 7348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3026 /* 7352 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3027 /* 7356 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3028 /* 7360 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3029 /* 7365 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3030 /* 7370 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3031 /* 7372 */ // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3032 /* 7372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3033 /* 7375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3034 /* 7377 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3035 /* 7379 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3036 /* 7383 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3037 /* 7387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3038 /* 7390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3039 /* 7396 */ GIR_RootConstrainSelectedInstOperands,
3040 /* 7397 */ // GIR_Coverage, 6203,
3041 /* 7397 */ GIR_EraseRootFromParent_Done,
3042 /* 7398 */ // Label 212: @7398
3043 /* 7398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 213*/ GIMT_Encode4(7459), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6209 //
3044 /* 7405 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3045 /* 7409 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3046 /* 7413 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3047 /* 7417 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3048 /* 7421 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3049 /* 7426 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3050 /* 7431 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3051 /* 7433 */ // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3052 /* 7433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3053 /* 7436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3054 /* 7438 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3055 /* 7440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3056 /* 7444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3057 /* 7448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3058 /* 7451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3059 /* 7457 */ GIR_RootConstrainSelectedInstOperands,
3060 /* 7458 */ // GIR_Coverage, 6209,
3061 /* 7458 */ GIR_EraseRootFromParent_Done,
3062 /* 7459 */ // Label 213: @7459
3063 /* 7459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 214*/ GIMT_Encode4(7520), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6091 //
3064 /* 7466 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3065 /* 7470 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3066 /* 7474 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3067 /* 7478 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3068 /* 7482 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3069 /* 7487 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3070 /* 7492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3071 /* 7494 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3072 /* 7494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3073 /* 7497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3074 /* 7499 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3075 /* 7501 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3076 /* 7505 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3077 /* 7509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3078 /* 7512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3079 /* 7518 */ GIR_RootConstrainSelectedInstOperands,
3080 /* 7519 */ // GIR_Coverage, 6091,
3081 /* 7519 */ GIR_EraseRootFromParent_Done,
3082 /* 7520 */ // Label 214: @7520
3083 /* 7520 */ GIM_Reject,
3084 /* 7521 */ // Label 211: @7521
3085 /* 7521 */ GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(7745),
3086 /* 7526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3087 /* 7530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 216*/ GIMT_Encode4(7591), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1344 //
3088 /* 7537 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3089 /* 7541 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3090 /* 7545 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3091 /* 7549 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3092 /* 7553 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3093 /* 7558 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3094 /* 7563 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3095 /* 7565 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3096 /* 7565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3097 /* 7568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3098 /* 7570 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3099 /* 7572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3100 /* 7576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3101 /* 7580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3102 /* 7583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3103 /* 7589 */ GIR_RootConstrainSelectedInstOperands,
3104 /* 7590 */ // GIR_Coverage, 1344,
3105 /* 7590 */ GIR_EraseRootFromParent_Done,
3106 /* 7591 */ // Label 216: @7591
3107 /* 7591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 217*/ GIMT_Encode4(7652), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1350 //
3108 /* 7598 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3109 /* 7602 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3110 /* 7606 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3111 /* 7610 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3112 /* 7614 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3113 /* 7619 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3114 /* 7624 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3115 /* 7626 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3116 /* 7626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3117 /* 7629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3118 /* 7631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3119 /* 7633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3120 /* 7637 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3121 /* 7641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3122 /* 7644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3123 /* 7650 */ GIR_RootConstrainSelectedInstOperands,
3124 /* 7651 */ // GIR_Coverage, 1350,
3125 /* 7651 */ GIR_EraseRootFromParent_Done,
3126 /* 7652 */ // Label 217: @7652
3127 /* 7652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 218*/ GIMT_Encode4(7713), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1010 //
3128 /* 7659 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3129 /* 7663 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3130 /* 7667 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3131 /* 7671 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3132 /* 7675 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3133 /* 7680 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3134 /* 7685 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3135 /* 7687 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3136 /* 7687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3137 /* 7690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3138 /* 7692 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3139 /* 7694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3140 /* 7698 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3141 /* 7702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3142 /* 7705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3143 /* 7711 */ GIR_RootConstrainSelectedInstOperands,
3144 /* 7712 */ // GIR_Coverage, 1010,
3145 /* 7712 */ GIR_EraseRootFromParent_Done,
3146 /* 7713 */ // Label 218: @7713
3147 /* 7713 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 219*/ GIMT_Encode4(7744), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 879 //
3148 /* 7720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3149 /* 7724 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3150 /* 7724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8),
3151 /* 7727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3152 /* 7729 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3153 /* 7731 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3154 /* 7733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3155 /* 7736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3156 /* 7742 */ GIR_RootConstrainSelectedInstOperands,
3157 /* 7743 */ // GIR_Coverage, 879,
3158 /* 7743 */ GIR_EraseRootFromParent_Done,
3159 /* 7744 */ // Label 219: @7744
3160 /* 7744 */ GIM_Reject,
3161 /* 7745 */ // Label 215: @7745
3162 /* 7745 */ GIM_Reject,
3163 /* 7746 */ // Label 210: @7746
3164 /* 7746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 220*/ GIMT_Encode4(7806), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3885 //
3165 /* 7753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3166 /* 7757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3167 /* 7761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3168 /* 7765 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
3169 /* 7765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3170 /* 7768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3171 /* 7772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3172 /* 7777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8),
3173 /* 7780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
3174 /* 7782 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
3175 /* 7784 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
3176 /* 7786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3177 /* 7789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3178 /* 7795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3179 /* 7801 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3180 /* 7804 */ GIR_RootConstrainSelectedInstOperands,
3181 /* 7805 */ // GIR_Coverage, 3885,
3182 /* 7805 */ GIR_EraseRootFromParent_Done,
3183 /* 7806 */ // Label 220: @7806
3184 /* 7806 */ GIM_Reject,
3185 /* 7807 */ // Label 209: @7807
3186 /* 7807 */ GIM_Reject,
3187 /* 7808 */ // Label 100: @7808
3188 /* 7808 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(8241),
3189 /* 7813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
3190 /* 7816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
3191 /* 7819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3192 /* 7823 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(8016),
3193 /* 7828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3194 /* 7832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 223*/ GIMT_Encode4(7893), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6201 //
3195 /* 7839 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3196 /* 7843 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3197 /* 7847 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3198 /* 7851 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3199 /* 7855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3200 /* 7860 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3201 /* 7865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3202 /* 7867 */ // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3203 /* 7867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3204 /* 7870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3205 /* 7872 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3206 /* 7874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3207 /* 7878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3208 /* 7882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3209 /* 7885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3210 /* 7891 */ GIR_RootConstrainSelectedInstOperands,
3211 /* 7892 */ // GIR_Coverage, 6201,
3212 /* 7892 */ GIR_EraseRootFromParent_Done,
3213 /* 7893 */ // Label 223: @7893
3214 /* 7893 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 224*/ GIMT_Encode4(7954), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6207 //
3215 /* 7900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3216 /* 7904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3217 /* 7908 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3218 /* 7912 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3219 /* 7916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3220 /* 7921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3221 /* 7926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3222 /* 7928 */ // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3223 /* 7928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3224 /* 7931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3225 /* 7933 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3226 /* 7935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3227 /* 7939 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3228 /* 7943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3229 /* 7946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3230 /* 7952 */ GIR_RootConstrainSelectedInstOperands,
3231 /* 7953 */ // GIR_Coverage, 6207,
3232 /* 7953 */ GIR_EraseRootFromParent_Done,
3233 /* 7954 */ // Label 224: @7954
3234 /* 7954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 225*/ GIMT_Encode4(8015), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6089 //
3235 /* 7961 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3236 /* 7965 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3237 /* 7969 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3238 /* 7973 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3239 /* 7977 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3240 /* 7982 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3241 /* 7987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3242 /* 7989 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3243 /* 7989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3244 /* 7992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3245 /* 7994 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3246 /* 7996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3247 /* 8000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3248 /* 8004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3249 /* 8007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3250 /* 8013 */ GIR_RootConstrainSelectedInstOperands,
3251 /* 8014 */ // GIR_Coverage, 6089,
3252 /* 8014 */ GIR_EraseRootFromParent_Done,
3253 /* 8015 */ // Label 225: @8015
3254 /* 8015 */ GIM_Reject,
3255 /* 8016 */ // Label 222: @8016
3256 /* 8016 */ GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(8240),
3257 /* 8021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3258 /* 8025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 227*/ GIMT_Encode4(8086), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1342 //
3259 /* 8032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3260 /* 8036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3261 /* 8040 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3262 /* 8044 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3263 /* 8048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3264 /* 8053 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3265 /* 8058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3266 /* 8060 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3267 /* 8060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3268 /* 8063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3269 /* 8065 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3270 /* 8067 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3271 /* 8071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3272 /* 8075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3273 /* 8078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3274 /* 8084 */ GIR_RootConstrainSelectedInstOperands,
3275 /* 8085 */ // GIR_Coverage, 1342,
3276 /* 8085 */ GIR_EraseRootFromParent_Done,
3277 /* 8086 */ // Label 227: @8086
3278 /* 8086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 228*/ GIMT_Encode4(8147), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1348 //
3279 /* 8093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3280 /* 8097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3281 /* 8101 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3282 /* 8105 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3283 /* 8109 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3284 /* 8114 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3285 /* 8119 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3286 /* 8121 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3287 /* 8121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3288 /* 8124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3289 /* 8126 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3290 /* 8128 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3291 /* 8132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3292 /* 8136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3293 /* 8139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3294 /* 8145 */ GIR_RootConstrainSelectedInstOperands,
3295 /* 8146 */ // GIR_Coverage, 1348,
3296 /* 8146 */ GIR_EraseRootFromParent_Done,
3297 /* 8147 */ // Label 228: @8147
3298 /* 8147 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 229*/ GIMT_Encode4(8208), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1008 //
3299 /* 8154 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3300 /* 8158 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3301 /* 8162 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3302 /* 8166 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3303 /* 8170 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3304 /* 8175 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3305 /* 8180 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3306 /* 8182 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3307 /* 8182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3308 /* 8185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3309 /* 8187 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3310 /* 8189 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3311 /* 8193 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3312 /* 8197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3313 /* 8200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3314 /* 8206 */ GIR_RootConstrainSelectedInstOperands,
3315 /* 8207 */ // GIR_Coverage, 1008,
3316 /* 8207 */ GIR_EraseRootFromParent_Done,
3317 /* 8208 */ // Label 229: @8208
3318 /* 8208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 230*/ GIMT_Encode4(8239), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 877 //
3319 /* 8215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3320 /* 8219 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3321 /* 8219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16),
3322 /* 8222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3323 /* 8224 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3324 /* 8226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3325 /* 8228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3326 /* 8231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3327 /* 8237 */ GIR_RootConstrainSelectedInstOperands,
3328 /* 8238 */ // GIR_Coverage, 877,
3329 /* 8238 */ GIR_EraseRootFromParent_Done,
3330 /* 8239 */ // Label 230: @8239
3331 /* 8239 */ GIM_Reject,
3332 /* 8240 */ // Label 226: @8240
3333 /* 8240 */ GIM_Reject,
3334 /* 8241 */ // Label 221: @8241
3335 /* 8241 */ GIM_Reject,
3336 /* 8242 */ // Label 101: @8242
3337 /* 8242 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(9676),
3338 /* 8247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3339 /* 8250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
3340 /* 8253 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(9615),
3341 /* 8258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3342 /* 8262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 233*/ GIMT_Encode4(8329), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 894 //
3343 /* 8269 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3344 /* 8273 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3345 /* 8277 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3346 /* 8281 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3347 /* 8286 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3348 /* 8290 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3349 /* 8294 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3350 /* 8298 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3351 /* 8303 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3352 /* 8305 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3353 /* 8305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3354 /* 8308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3355 /* 8310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3356 /* 8314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3357 /* 8318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3358 /* 8321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3359 /* 8327 */ GIR_RootConstrainSelectedInstOperands,
3360 /* 8328 */ // GIR_Coverage, 894,
3361 /* 8328 */ GIR_EraseRootFromParent_Done,
3362 /* 8329 */ // Label 233: @8329
3363 /* 8329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 234*/ GIMT_Encode4(8396), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 893 //
3364 /* 8336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3365 /* 8340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3366 /* 8344 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3367 /* 8348 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3368 /* 8353 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3369 /* 8357 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3370 /* 8361 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3371 /* 8365 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3372 /* 8370 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3373 /* 8372 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3374 /* 8372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3375 /* 8375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3376 /* 8377 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3377 /* 8381 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3378 /* 8385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3379 /* 8388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3380 /* 8394 */ GIR_RootConstrainSelectedInstOperands,
3381 /* 8395 */ // GIR_Coverage, 893,
3382 /* 8395 */ GIR_EraseRootFromParent_Done,
3383 /* 8396 */ // Label 234: @8396
3384 /* 8396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 235*/ GIMT_Encode4(8463), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 888 //
3385 /* 8403 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3386 /* 8407 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3387 /* 8411 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3388 /* 8415 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3389 /* 8420 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3390 /* 8424 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
3391 /* 8428 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3392 /* 8432 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3393 /* 8437 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3394 /* 8439 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3395 /* 8439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16),
3396 /* 8442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3397 /* 8444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3398 /* 8448 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3399 /* 8452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3400 /* 8455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3401 /* 8461 */ GIR_RootConstrainSelectedInstOperands,
3402 /* 8462 */ // GIR_Coverage, 888,
3403 /* 8462 */ GIR_EraseRootFromParent_Done,
3404 /* 8463 */ // Label 235: @8463
3405 /* 8463 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(8619),
3406 /* 8468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3407 /* 8472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 237*/ GIMT_Encode4(8545), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6212 //
3408 /* 8479 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3409 /* 8483 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3410 /* 8487 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3411 /* 8491 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3412 /* 8495 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3413 /* 8499 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3414 /* 8503 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3415 /* 8507 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3416 /* 8512 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3417 /* 8517 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3418 /* 8519 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3419 /* 8519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3420 /* 8522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3421 /* 8524 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3422 /* 8526 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3423 /* 8530 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3424 /* 8534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3425 /* 8537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3426 /* 8543 */ GIR_RootConstrainSelectedInstOperands,
3427 /* 8544 */ // GIR_Coverage, 6212,
3428 /* 8544 */ GIR_EraseRootFromParent_Done,
3429 /* 8545 */ // Label 237: @8545
3430 /* 8545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 238*/ GIMT_Encode4(8618), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6215 //
3431 /* 8552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3432 /* 8556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3433 /* 8560 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3434 /* 8564 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3435 /* 8568 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3436 /* 8572 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3437 /* 8576 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3438 /* 8580 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3439 /* 8585 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3440 /* 8590 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3441 /* 8592 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3442 /* 8592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3443 /* 8595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3444 /* 8597 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3445 /* 8599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3446 /* 8603 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3447 /* 8607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3448 /* 8610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3449 /* 8616 */ GIR_RootConstrainSelectedInstOperands,
3450 /* 8617 */ // GIR_Coverage, 6215,
3451 /* 8617 */ GIR_EraseRootFromParent_Done,
3452 /* 8618 */ // Label 238: @8618
3453 /* 8618 */ GIM_Reject,
3454 /* 8619 */ // Label 236: @8619
3455 /* 8619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 239*/ GIMT_Encode4(8686), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 892 //
3456 /* 8626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3457 /* 8630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3458 /* 8634 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3459 /* 8638 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3460 /* 8643 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3461 /* 8647 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3462 /* 8651 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3463 /* 8655 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3464 /* 8660 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3465 /* 8662 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3466 /* 8662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3467 /* 8665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3468 /* 8667 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3469 /* 8671 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3470 /* 8675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3471 /* 8678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3472 /* 8684 */ GIR_RootConstrainSelectedInstOperands,
3473 /* 8685 */ // GIR_Coverage, 892,
3474 /* 8685 */ GIR_EraseRootFromParent_Done,
3475 /* 8686 */ // Label 239: @8686
3476 /* 8686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 240*/ GIMT_Encode4(8753), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 891 //
3477 /* 8693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3478 /* 8697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3479 /* 8701 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3480 /* 8705 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3481 /* 8710 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3482 /* 8714 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3483 /* 8718 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3484 /* 8722 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3485 /* 8727 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3486 /* 8729 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3487 /* 8729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3488 /* 8732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3489 /* 8734 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3490 /* 8738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3491 /* 8742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3492 /* 8745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3493 /* 8751 */ GIR_RootConstrainSelectedInstOperands,
3494 /* 8752 */ // GIR_Coverage, 891,
3495 /* 8752 */ GIR_EraseRootFromParent_Done,
3496 /* 8753 */ // Label 240: @8753
3497 /* 8753 */ GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(8909),
3498 /* 8758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3499 /* 8762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 242*/ GIMT_Encode4(8835), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1353 //
3500 /* 8769 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3501 /* 8773 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3502 /* 8777 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3503 /* 8781 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3504 /* 8785 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3505 /* 8789 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3506 /* 8793 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3507 /* 8797 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3508 /* 8802 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3509 /* 8807 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3510 /* 8809 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3511 /* 8809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3512 /* 8812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3513 /* 8814 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3514 /* 8816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3515 /* 8820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3516 /* 8824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3517 /* 8827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3518 /* 8833 */ GIR_RootConstrainSelectedInstOperands,
3519 /* 8834 */ // GIR_Coverage, 1353,
3520 /* 8834 */ GIR_EraseRootFromParent_Done,
3521 /* 8835 */ // Label 242: @8835
3522 /* 8835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 243*/ GIMT_Encode4(8908), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1356 //
3523 /* 8842 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3524 /* 8846 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3525 /* 8850 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3526 /* 8854 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3527 /* 8858 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3528 /* 8862 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3529 /* 8866 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3530 /* 8870 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3531 /* 8875 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3532 /* 8880 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3533 /* 8882 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3534 /* 8882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3535 /* 8885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3536 /* 8887 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3537 /* 8889 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3538 /* 8893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3539 /* 8897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3540 /* 8900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3541 /* 8906 */ GIR_RootConstrainSelectedInstOperands,
3542 /* 8907 */ // GIR_Coverage, 1356,
3543 /* 8907 */ GIR_EraseRootFromParent_Done,
3544 /* 8908 */ // Label 243: @8908
3545 /* 8908 */ GIM_Reject,
3546 /* 8909 */ // Label 241: @8909
3547 /* 8909 */ GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(9246),
3548 /* 8914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3549 /* 8918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 245*/ GIMT_Encode4(8979), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6204 //
3550 /* 8925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3551 /* 8929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3552 /* 8933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3553 /* 8937 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3554 /* 8941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3555 /* 8946 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3556 /* 8951 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3557 /* 8953 */ // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3558 /* 8953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3559 /* 8956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3560 /* 8958 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3561 /* 8960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3562 /* 8964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3563 /* 8968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3564 /* 8971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3565 /* 8977 */ GIR_RootConstrainSelectedInstOperands,
3566 /* 8978 */ // GIR_Coverage, 6204,
3567 /* 8978 */ GIR_EraseRootFromParent_Done,
3568 /* 8979 */ // Label 245: @8979
3569 /* 8979 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 246*/ GIMT_Encode4(9040), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6210 //
3570 /* 8986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3571 /* 8990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3572 /* 8994 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3573 /* 8998 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3574 /* 9002 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3575 /* 9007 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3576 /* 9012 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3577 /* 9014 */ // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3578 /* 9014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3579 /* 9017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3580 /* 9019 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3581 /* 9021 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3582 /* 9025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3583 /* 9029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3584 /* 9032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3585 /* 9038 */ GIR_RootConstrainSelectedInstOperands,
3586 /* 9039 */ // GIR_Coverage, 6210,
3587 /* 9039 */ GIR_EraseRootFromParent_Done,
3588 /* 9040 */ // Label 246: @9040
3589 /* 9040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 247*/ GIMT_Encode4(9101), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6092 //
3590 /* 9047 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3591 /* 9051 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3592 /* 9055 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3593 /* 9059 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3594 /* 9063 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3595 /* 9068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3596 /* 9073 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3597 /* 9075 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3598 /* 9075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3599 /* 9078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3600 /* 9080 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3601 /* 9082 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3602 /* 9086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3603 /* 9090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3604 /* 9093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3605 /* 9099 */ GIR_RootConstrainSelectedInstOperands,
3606 /* 9100 */ // GIR_Coverage, 6092,
3607 /* 9100 */ GIR_EraseRootFromParent_Done,
3608 /* 9101 */ // Label 247: @9101
3609 /* 9101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 248*/ GIMT_Encode4(9149), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6065 //
3610 /* 9108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3611 /* 9112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3612 /* 9116 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3613 /* 9120 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3614 /* 9125 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3615 /* 9127 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3616 /* 9127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3617 /* 9130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3618 /* 9132 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3619 /* 9134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3620 /* 9138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3621 /* 9141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3622 /* 9147 */ GIR_RootConstrainSelectedInstOperands,
3623 /* 9148 */ // GIR_Coverage, 6065,
3624 /* 9148 */ GIR_EraseRootFromParent_Done,
3625 /* 9149 */ // Label 248: @9149
3626 /* 9149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 249*/ GIMT_Encode4(9197), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6061 //
3627 /* 9156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3628 /* 9160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3629 /* 9164 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3630 /* 9168 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3631 /* 9173 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3632 /* 9175 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3633 /* 9175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3634 /* 9178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3635 /* 9180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3636 /* 9182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3637 /* 9186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3638 /* 9189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3639 /* 9195 */ GIR_RootConstrainSelectedInstOperands,
3640 /* 9196 */ // GIR_Coverage, 6061,
3641 /* 9196 */ GIR_EraseRootFromParent_Done,
3642 /* 9197 */ // Label 249: @9197
3643 /* 9197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 250*/ GIMT_Encode4(9245), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6064 //
3644 /* 9204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3645 /* 9208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3646 /* 9212 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3647 /* 9216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3648 /* 9221 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3649 /* 9223 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3650 /* 9223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3651 /* 9226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3652 /* 9228 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3653 /* 9230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3654 /* 9234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3655 /* 9237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3656 /* 9243 */ GIR_RootConstrainSelectedInstOperands,
3657 /* 9244 */ // GIR_Coverage, 6064,
3658 /* 9244 */ GIR_EraseRootFromParent_Done,
3659 /* 9245 */ // Label 250: @9245
3660 /* 9245 */ GIM_Reject,
3661 /* 9246 */ // Label 244: @9246
3662 /* 9246 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(9614),
3663 /* 9251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3664 /* 9255 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 252*/ GIMT_Encode4(9316), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1345 //
3665 /* 9262 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3666 /* 9266 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3667 /* 9270 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3668 /* 9274 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3669 /* 9278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3670 /* 9283 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3671 /* 9288 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3672 /* 9290 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3673 /* 9290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3674 /* 9293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3675 /* 9295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3676 /* 9297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3677 /* 9301 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3678 /* 9305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3679 /* 9308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3680 /* 9314 */ GIR_RootConstrainSelectedInstOperands,
3681 /* 9315 */ // GIR_Coverage, 1345,
3682 /* 9315 */ GIR_EraseRootFromParent_Done,
3683 /* 9316 */ // Label 252: @9316
3684 /* 9316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 253*/ GIMT_Encode4(9377), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1351 //
3685 /* 9323 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3686 /* 9327 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3687 /* 9331 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3688 /* 9335 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3689 /* 9339 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3690 /* 9344 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3691 /* 9349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3692 /* 9351 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3693 /* 9351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3694 /* 9354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3695 /* 9356 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3696 /* 9358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3697 /* 9362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3698 /* 9366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3699 /* 9369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3700 /* 9375 */ GIR_RootConstrainSelectedInstOperands,
3701 /* 9376 */ // GIR_Coverage, 1351,
3702 /* 9376 */ GIR_EraseRootFromParent_Done,
3703 /* 9377 */ // Label 253: @9377
3704 /* 9377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 254*/ GIMT_Encode4(9438), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1011 //
3705 /* 9384 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3706 /* 9388 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3707 /* 9392 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3708 /* 9396 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3709 /* 9400 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3710 /* 9405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3711 /* 9410 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3712 /* 9412 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3713 /* 9412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3714 /* 9415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3715 /* 9417 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3716 /* 9419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3717 /* 9423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3718 /* 9427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3719 /* 9430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3720 /* 9436 */ GIR_RootConstrainSelectedInstOperands,
3721 /* 9437 */ // GIR_Coverage, 1011,
3722 /* 9437 */ GIR_EraseRootFromParent_Done,
3723 /* 9438 */ // Label 254: @9438
3724 /* 9438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 255*/ GIMT_Encode4(9486), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 907 //
3725 /* 9445 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3726 /* 9449 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3727 /* 9453 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3728 /* 9457 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3729 /* 9462 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3730 /* 9464 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3731 /* 9464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3732 /* 9467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3733 /* 9469 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3734 /* 9471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3735 /* 9475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3736 /* 9478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3737 /* 9484 */ GIR_RootConstrainSelectedInstOperands,
3738 /* 9485 */ // GIR_Coverage, 907,
3739 /* 9485 */ GIR_EraseRootFromParent_Done,
3740 /* 9486 */ // Label 255: @9486
3741 /* 9486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 256*/ GIMT_Encode4(9534), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 903 //
3742 /* 9493 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3743 /* 9497 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3744 /* 9501 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3745 /* 9505 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3746 /* 9510 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3747 /* 9512 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3748 /* 9512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3749 /* 9515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3750 /* 9517 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3751 /* 9519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3752 /* 9523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3753 /* 9526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3754 /* 9532 */ GIR_RootConstrainSelectedInstOperands,
3755 /* 9533 */ // GIR_Coverage, 903,
3756 /* 9533 */ GIR_EraseRootFromParent_Done,
3757 /* 9534 */ // Label 256: @9534
3758 /* 9534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 257*/ GIMT_Encode4(9582), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 906 //
3759 /* 9541 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3760 /* 9545 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3761 /* 9549 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3762 /* 9553 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3763 /* 9558 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3764 /* 9560 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3765 /* 9560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3766 /* 9563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3767 /* 9565 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3768 /* 9567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3769 /* 9571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3770 /* 9574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3771 /* 9580 */ GIR_RootConstrainSelectedInstOperands,
3772 /* 9581 */ // GIR_Coverage, 906,
3773 /* 9581 */ GIR_EraseRootFromParent_Done,
3774 /* 9582 */ // Label 257: @9582
3775 /* 9582 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 258*/ GIMT_Encode4(9613), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 880 //
3776 /* 9589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3777 /* 9593 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3778 /* 9593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16),
3779 /* 9596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3780 /* 9598 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3781 /* 9600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3782 /* 9602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3783 /* 9605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3784 /* 9611 */ GIR_RootConstrainSelectedInstOperands,
3785 /* 9612 */ // GIR_Coverage, 880,
3786 /* 9612 */ GIR_EraseRootFromParent_Done,
3787 /* 9613 */ // Label 258: @9613
3788 /* 9613 */ GIM_Reject,
3789 /* 9614 */ // Label 251: @9614
3790 /* 9614 */ GIM_Reject,
3791 /* 9615 */ // Label 232: @9615
3792 /* 9615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 259*/ GIMT_Encode4(9675), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3889 //
3793 /* 9622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3794 /* 9626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3795 /* 9630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3796 /* 9634 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
3797 /* 9634 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3798 /* 9637 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3799 /* 9641 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3800 /* 9646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16),
3801 /* 9649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
3802 /* 9651 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
3803 /* 9653 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
3804 /* 9655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3805 /* 9658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3806 /* 9664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3807 /* 9670 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3808 /* 9673 */ GIR_RootConstrainSelectedInstOperands,
3809 /* 9674 */ // GIR_Coverage, 3889,
3810 /* 9674 */ GIR_EraseRootFromParent_Done,
3811 /* 9675 */ // Label 259: @9675
3812 /* 9675 */ GIM_Reject,
3813 /* 9676 */ // Label 231: @9676
3814 /* 9676 */ GIM_Reject,
3815 /* 9677 */ // Label 102: @9677
3816 /* 9677 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(10110),
3817 /* 9682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
3818 /* 9685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
3819 /* 9688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3820 /* 9692 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(9885),
3821 /* 9697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3822 /* 9701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 262*/ GIMT_Encode4(9762), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6202 //
3823 /* 9708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3824 /* 9712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3825 /* 9716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3826 /* 9720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3827 /* 9724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3828 /* 9729 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3829 /* 9734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3830 /* 9736 */ // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3831 /* 9736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
3832 /* 9739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3833 /* 9741 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3834 /* 9743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3835 /* 9747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3836 /* 9751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3837 /* 9754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3838 /* 9760 */ GIR_RootConstrainSelectedInstOperands,
3839 /* 9761 */ // GIR_Coverage, 6202,
3840 /* 9761 */ GIR_EraseRootFromParent_Done,
3841 /* 9762 */ // Label 262: @9762
3842 /* 9762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 263*/ GIMT_Encode4(9823), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6208 //
3843 /* 9769 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3844 /* 9773 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3845 /* 9777 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3846 /* 9781 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3847 /* 9785 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3848 /* 9790 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3849 /* 9795 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3850 /* 9797 */ // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3851 /* 9797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
3852 /* 9800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3853 /* 9802 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3854 /* 9804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3855 /* 9808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3856 /* 9812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3857 /* 9815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3858 /* 9821 */ GIR_RootConstrainSelectedInstOperands,
3859 /* 9822 */ // GIR_Coverage, 6208,
3860 /* 9822 */ GIR_EraseRootFromParent_Done,
3861 /* 9823 */ // Label 263: @9823
3862 /* 9823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 264*/ GIMT_Encode4(9884), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6090 //
3863 /* 9830 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3864 /* 9834 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3865 /* 9838 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3866 /* 9842 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3867 /* 9846 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3868 /* 9851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3869 /* 9856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3870 /* 9858 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3871 /* 9858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
3872 /* 9861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3873 /* 9863 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3874 /* 9865 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3875 /* 9869 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3876 /* 9873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3877 /* 9876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3878 /* 9882 */ GIR_RootConstrainSelectedInstOperands,
3879 /* 9883 */ // GIR_Coverage, 6090,
3880 /* 9883 */ GIR_EraseRootFromParent_Done,
3881 /* 9884 */ // Label 264: @9884
3882 /* 9884 */ GIM_Reject,
3883 /* 9885 */ // Label 261: @9885
3884 /* 9885 */ GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(10109),
3885 /* 9890 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3886 /* 9894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 266*/ GIMT_Encode4(9955), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1343 //
3887 /* 9901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3888 /* 9905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3889 /* 9909 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3890 /* 9913 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3891 /* 9917 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3892 /* 9922 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3893 /* 9927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3894 /* 9929 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3895 /* 9929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
3896 /* 9932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3897 /* 9934 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3898 /* 9936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3899 /* 9940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3900 /* 9944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3901 /* 9947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3902 /* 9953 */ GIR_RootConstrainSelectedInstOperands,
3903 /* 9954 */ // GIR_Coverage, 1343,
3904 /* 9954 */ GIR_EraseRootFromParent_Done,
3905 /* 9955 */ // Label 266: @9955
3906 /* 9955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 267*/ GIMT_Encode4(10016), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1349 //
3907 /* 9962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3908 /* 9966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3909 /* 9970 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3910 /* 9974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3911 /* 9978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3912 /* 9983 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3913 /* 9988 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3914 /* 9990 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3915 /* 9990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
3916 /* 9993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3917 /* 9995 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3918 /* 9997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3919 /* 10001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3920 /* 10005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3921 /* 10008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3922 /* 10014 */ GIR_RootConstrainSelectedInstOperands,
3923 /* 10015 */ // GIR_Coverage, 1349,
3924 /* 10015 */ GIR_EraseRootFromParent_Done,
3925 /* 10016 */ // Label 267: @10016
3926 /* 10016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 268*/ GIMT_Encode4(10077), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1009 //
3927 /* 10023 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3928 /* 10027 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3929 /* 10031 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3930 /* 10035 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3931 /* 10039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3932 /* 10044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3933 /* 10049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3934 /* 10051 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3935 /* 10051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
3936 /* 10054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3937 /* 10056 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3938 /* 10058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3939 /* 10062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3940 /* 10066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3941 /* 10069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3942 /* 10075 */ GIR_RootConstrainSelectedInstOperands,
3943 /* 10076 */ // GIR_Coverage, 1009,
3944 /* 10076 */ GIR_EraseRootFromParent_Done,
3945 /* 10077 */ // Label 268: @10077
3946 /* 10077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 269*/ GIMT_Encode4(10108), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 878 //
3947 /* 10084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3948 /* 10088 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3949 /* 10088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32),
3950 /* 10091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3951 /* 10093 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3952 /* 10095 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3953 /* 10097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3954 /* 10100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3955 /* 10106 */ GIR_RootConstrainSelectedInstOperands,
3956 /* 10107 */ // GIR_Coverage, 878,
3957 /* 10107 */ GIR_EraseRootFromParent_Done,
3958 /* 10108 */ // Label 269: @10108
3959 /* 10108 */ GIM_Reject,
3960 /* 10109 */ // Label 265: @10109
3961 /* 10109 */ GIM_Reject,
3962 /* 10110 */ // Label 260: @10110
3963 /* 10110 */ GIM_Reject,
3964 /* 10111 */ // Label 103: @10111
3965 /* 10111 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(11545),
3966 /* 10116 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3967 /* 10119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
3968 /* 10122 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(11484),
3969 /* 10127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3970 /* 10131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 272*/ GIMT_Encode4(10198), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 898 //
3971 /* 10138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3972 /* 10142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3973 /* 10146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3974 /* 10150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3975 /* 10155 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3976 /* 10159 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3977 /* 10163 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3978 /* 10167 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3979 /* 10172 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3980 /* 10174 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3981 /* 10174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
3982 /* 10177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3983 /* 10179 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3984 /* 10183 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3985 /* 10187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3986 /* 10190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3987 /* 10196 */ GIR_RootConstrainSelectedInstOperands,
3988 /* 10197 */ // GIR_Coverage, 898,
3989 /* 10197 */ GIR_EraseRootFromParent_Done,
3990 /* 10198 */ // Label 272: @10198
3991 /* 10198 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 273*/ GIMT_Encode4(10265), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 897 //
3992 /* 10205 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3993 /* 10209 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3994 /* 10213 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3995 /* 10217 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3996 /* 10222 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3997 /* 10226 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3998 /* 10230 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3999 /* 10234 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4000 /* 10239 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4001 /* 10241 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4002 /* 10241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4003 /* 10244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4004 /* 10246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4005 /* 10250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4006 /* 10254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4007 /* 10257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4008 /* 10263 */ GIR_RootConstrainSelectedInstOperands,
4009 /* 10264 */ // GIR_Coverage, 897,
4010 /* 10264 */ GIR_EraseRootFromParent_Done,
4011 /* 10265 */ // Label 273: @10265
4012 /* 10265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 274*/ GIMT_Encode4(10332), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 889 //
4013 /* 10272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4014 /* 10276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4015 /* 10280 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4016 /* 10284 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4017 /* 10289 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4018 /* 10293 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4019 /* 10297 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4020 /* 10301 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4021 /* 10306 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4022 /* 10308 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4023 /* 10308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32),
4024 /* 10311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4025 /* 10313 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4026 /* 10317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4027 /* 10321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4028 /* 10324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4029 /* 10330 */ GIR_RootConstrainSelectedInstOperands,
4030 /* 10331 */ // GIR_Coverage, 889,
4031 /* 10331 */ GIR_EraseRootFromParent_Done,
4032 /* 10332 */ // Label 274: @10332
4033 /* 10332 */ GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(10488),
4034 /* 10337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4035 /* 10341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 276*/ GIMT_Encode4(10414), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6213 //
4036 /* 10348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4037 /* 10352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4038 /* 10356 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4039 /* 10360 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4040 /* 10364 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4041 /* 10368 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4042 /* 10372 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4043 /* 10376 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4044 /* 10381 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4045 /* 10386 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4046 /* 10388 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4047 /* 10388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
4048 /* 10391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4049 /* 10393 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4050 /* 10395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4051 /* 10399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4052 /* 10403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4053 /* 10406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4054 /* 10412 */ GIR_RootConstrainSelectedInstOperands,
4055 /* 10413 */ // GIR_Coverage, 6213,
4056 /* 10413 */ GIR_EraseRootFromParent_Done,
4057 /* 10414 */ // Label 276: @10414
4058 /* 10414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 277*/ GIMT_Encode4(10487), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6216 //
4059 /* 10421 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4060 /* 10425 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4061 /* 10429 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4062 /* 10433 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4063 /* 10437 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4064 /* 10441 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4065 /* 10445 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4066 /* 10449 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4067 /* 10454 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4068 /* 10459 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4069 /* 10461 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4070 /* 10461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
4071 /* 10464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4072 /* 10466 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4073 /* 10468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4074 /* 10472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4075 /* 10476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4076 /* 10479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4077 /* 10485 */ GIR_RootConstrainSelectedInstOperands,
4078 /* 10486 */ // GIR_Coverage, 6216,
4079 /* 10486 */ GIR_EraseRootFromParent_Done,
4080 /* 10487 */ // Label 277: @10487
4081 /* 10487 */ GIM_Reject,
4082 /* 10488 */ // Label 275: @10488
4083 /* 10488 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 278*/ GIMT_Encode4(10555), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 896 //
4084 /* 10495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4085 /* 10499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4086 /* 10503 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4087 /* 10507 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4088 /* 10512 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4089 /* 10516 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4090 /* 10520 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4091 /* 10524 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4092 /* 10529 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4093 /* 10531 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4094 /* 10531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4095 /* 10534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4096 /* 10536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4097 /* 10540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4098 /* 10544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4099 /* 10547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4100 /* 10553 */ GIR_RootConstrainSelectedInstOperands,
4101 /* 10554 */ // GIR_Coverage, 896,
4102 /* 10554 */ GIR_EraseRootFromParent_Done,
4103 /* 10555 */ // Label 278: @10555
4104 /* 10555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 279*/ GIMT_Encode4(10622), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 895 //
4105 /* 10562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4106 /* 10566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4107 /* 10570 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4108 /* 10574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4109 /* 10579 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4110 /* 10583 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4111 /* 10587 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4112 /* 10591 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4113 /* 10596 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4114 /* 10598 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4115 /* 10598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4116 /* 10601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4117 /* 10603 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4118 /* 10607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4119 /* 10611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4120 /* 10614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4121 /* 10620 */ GIR_RootConstrainSelectedInstOperands,
4122 /* 10621 */ // GIR_Coverage, 895,
4123 /* 10621 */ GIR_EraseRootFromParent_Done,
4124 /* 10622 */ // Label 279: @10622
4125 /* 10622 */ GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(10778),
4126 /* 10627 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4127 /* 10631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 281*/ GIMT_Encode4(10704), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1354 //
4128 /* 10638 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4129 /* 10642 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4130 /* 10646 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4131 /* 10650 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4132 /* 10654 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4133 /* 10658 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4134 /* 10662 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4135 /* 10666 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4136 /* 10671 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4137 /* 10676 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4138 /* 10678 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4139 /* 10678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
4140 /* 10681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4141 /* 10683 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4142 /* 10685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4143 /* 10689 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4144 /* 10693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4145 /* 10696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4146 /* 10702 */ GIR_RootConstrainSelectedInstOperands,
4147 /* 10703 */ // GIR_Coverage, 1354,
4148 /* 10703 */ GIR_EraseRootFromParent_Done,
4149 /* 10704 */ // Label 281: @10704
4150 /* 10704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 282*/ GIMT_Encode4(10777), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1357 //
4151 /* 10711 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4152 /* 10715 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4153 /* 10719 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4154 /* 10723 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4155 /* 10727 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4156 /* 10731 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4157 /* 10735 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4158 /* 10739 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4159 /* 10744 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4160 /* 10749 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4161 /* 10751 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4162 /* 10751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
4163 /* 10754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4164 /* 10756 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4165 /* 10758 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4166 /* 10762 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4167 /* 10766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4168 /* 10769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4169 /* 10775 */ GIR_RootConstrainSelectedInstOperands,
4170 /* 10776 */ // GIR_Coverage, 1357,
4171 /* 10776 */ GIR_EraseRootFromParent_Done,
4172 /* 10777 */ // Label 282: @10777
4173 /* 10777 */ GIM_Reject,
4174 /* 10778 */ // Label 280: @10778
4175 /* 10778 */ GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(11115),
4176 /* 10783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4177 /* 10787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 284*/ GIMT_Encode4(10848), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6205 //
4178 /* 10794 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4179 /* 10798 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4180 /* 10802 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4181 /* 10806 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4182 /* 10810 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4183 /* 10815 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4184 /* 10820 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4185 /* 10822 */ // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4186 /* 10822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
4187 /* 10825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4188 /* 10827 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4189 /* 10829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4190 /* 10833 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4191 /* 10837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4192 /* 10840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4193 /* 10846 */ GIR_RootConstrainSelectedInstOperands,
4194 /* 10847 */ // GIR_Coverage, 6205,
4195 /* 10847 */ GIR_EraseRootFromParent_Done,
4196 /* 10848 */ // Label 284: @10848
4197 /* 10848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 285*/ GIMT_Encode4(10909), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6211 //
4198 /* 10855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4199 /* 10859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4200 /* 10863 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4201 /* 10867 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4202 /* 10871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4203 /* 10876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4204 /* 10881 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4205 /* 10883 */ // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4206 /* 10883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
4207 /* 10886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4208 /* 10888 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4209 /* 10890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4210 /* 10894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4211 /* 10898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4212 /* 10901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4213 /* 10907 */ GIR_RootConstrainSelectedInstOperands,
4214 /* 10908 */ // GIR_Coverage, 6211,
4215 /* 10908 */ GIR_EraseRootFromParent_Done,
4216 /* 10909 */ // Label 285: @10909
4217 /* 10909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 286*/ GIMT_Encode4(10970), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6093 //
4218 /* 10916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4219 /* 10920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4220 /* 10924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4221 /* 10928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4222 /* 10932 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4223 /* 10937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4224 /* 10942 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4225 /* 10944 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4226 /* 10944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
4227 /* 10947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4228 /* 10949 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4229 /* 10951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4230 /* 10955 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4231 /* 10959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4232 /* 10962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4233 /* 10968 */ GIR_RootConstrainSelectedInstOperands,
4234 /* 10969 */ // GIR_Coverage, 6093,
4235 /* 10969 */ GIR_EraseRootFromParent_Done,
4236 /* 10970 */ // Label 286: @10970
4237 /* 10970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 287*/ GIMT_Encode4(11018), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6067 //
4238 /* 10977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4239 /* 10981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4240 /* 10985 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4241 /* 10989 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4242 /* 10994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4243 /* 10996 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4244 /* 10996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4245 /* 10999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4246 /* 11001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4247 /* 11003 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4248 /* 11007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4249 /* 11010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4250 /* 11016 */ GIR_RootConstrainSelectedInstOperands,
4251 /* 11017 */ // GIR_Coverage, 6067,
4252 /* 11017 */ GIR_EraseRootFromParent_Done,
4253 /* 11018 */ // Label 287: @11018
4254 /* 11018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 288*/ GIMT_Encode4(11066), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6062 //
4255 /* 11025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4256 /* 11029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4257 /* 11033 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4258 /* 11037 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4259 /* 11042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4260 /* 11044 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4261 /* 11044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
4262 /* 11047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4263 /* 11049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4264 /* 11051 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4265 /* 11055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4266 /* 11058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4267 /* 11064 */ GIR_RootConstrainSelectedInstOperands,
4268 /* 11065 */ // GIR_Coverage, 6062,
4269 /* 11065 */ GIR_EraseRootFromParent_Done,
4270 /* 11066 */ // Label 288: @11066
4271 /* 11066 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 289*/ GIMT_Encode4(11114), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6066 //
4272 /* 11073 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4273 /* 11077 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4274 /* 11081 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4275 /* 11085 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4276 /* 11090 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4277 /* 11092 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4278 /* 11092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4279 /* 11095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4280 /* 11097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4281 /* 11099 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4282 /* 11103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4283 /* 11106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4284 /* 11112 */ GIR_RootConstrainSelectedInstOperands,
4285 /* 11113 */ // GIR_Coverage, 6066,
4286 /* 11113 */ GIR_EraseRootFromParent_Done,
4287 /* 11114 */ // Label 289: @11114
4288 /* 11114 */ GIM_Reject,
4289 /* 11115 */ // Label 283: @11115
4290 /* 11115 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(11483),
4291 /* 11120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4292 /* 11124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 291*/ GIMT_Encode4(11185), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1346 //
4293 /* 11131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4294 /* 11135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4295 /* 11139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4296 /* 11143 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4297 /* 11147 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4298 /* 11152 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4299 /* 11157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4300 /* 11159 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4301 /* 11159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
4302 /* 11162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4303 /* 11164 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4304 /* 11166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4305 /* 11170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4306 /* 11174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4307 /* 11177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4308 /* 11183 */ GIR_RootConstrainSelectedInstOperands,
4309 /* 11184 */ // GIR_Coverage, 1346,
4310 /* 11184 */ GIR_EraseRootFromParent_Done,
4311 /* 11185 */ // Label 291: @11185
4312 /* 11185 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 292*/ GIMT_Encode4(11246), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1352 //
4313 /* 11192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4314 /* 11196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4315 /* 11200 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4316 /* 11204 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4317 /* 11208 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4318 /* 11213 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4319 /* 11218 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4320 /* 11220 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4321 /* 11220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
4322 /* 11223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4323 /* 11225 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4324 /* 11227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4325 /* 11231 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4326 /* 11235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4327 /* 11238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4328 /* 11244 */ GIR_RootConstrainSelectedInstOperands,
4329 /* 11245 */ // GIR_Coverage, 1352,
4330 /* 11245 */ GIR_EraseRootFromParent_Done,
4331 /* 11246 */ // Label 292: @11246
4332 /* 11246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 293*/ GIMT_Encode4(11307), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1012 //
4333 /* 11253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4334 /* 11257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4335 /* 11261 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4336 /* 11265 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4337 /* 11269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4338 /* 11274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4339 /* 11279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4340 /* 11281 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4341 /* 11281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
4342 /* 11284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4343 /* 11286 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4344 /* 11288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4345 /* 11292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4346 /* 11296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4347 /* 11299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4348 /* 11305 */ GIR_RootConstrainSelectedInstOperands,
4349 /* 11306 */ // GIR_Coverage, 1012,
4350 /* 11306 */ GIR_EraseRootFromParent_Done,
4351 /* 11307 */ // Label 293: @11307
4352 /* 11307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 294*/ GIMT_Encode4(11355), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 909 //
4353 /* 11314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4354 /* 11318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4355 /* 11322 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4356 /* 11326 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4357 /* 11331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4358 /* 11333 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4359 /* 11333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4360 /* 11336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4361 /* 11338 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4362 /* 11340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4363 /* 11344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4364 /* 11347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4365 /* 11353 */ GIR_RootConstrainSelectedInstOperands,
4366 /* 11354 */ // GIR_Coverage, 909,
4367 /* 11354 */ GIR_EraseRootFromParent_Done,
4368 /* 11355 */ // Label 294: @11355
4369 /* 11355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 295*/ GIMT_Encode4(11403), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 904 //
4370 /* 11362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4371 /* 11366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4372 /* 11370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4373 /* 11374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4374 /* 11379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4375 /* 11381 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4376 /* 11381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
4377 /* 11384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4378 /* 11386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4379 /* 11388 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4380 /* 11392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4381 /* 11395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4382 /* 11401 */ GIR_RootConstrainSelectedInstOperands,
4383 /* 11402 */ // GIR_Coverage, 904,
4384 /* 11402 */ GIR_EraseRootFromParent_Done,
4385 /* 11403 */ // Label 295: @11403
4386 /* 11403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 296*/ GIMT_Encode4(11451), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 908 //
4387 /* 11410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4388 /* 11414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4389 /* 11418 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4390 /* 11422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4391 /* 11427 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4392 /* 11429 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4393 /* 11429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4394 /* 11432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4395 /* 11434 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4396 /* 11436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4397 /* 11440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4398 /* 11443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4399 /* 11449 */ GIR_RootConstrainSelectedInstOperands,
4400 /* 11450 */ // GIR_Coverage, 908,
4401 /* 11450 */ GIR_EraseRootFromParent_Done,
4402 /* 11451 */ // Label 296: @11451
4403 /* 11451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 297*/ GIMT_Encode4(11482), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 881 //
4404 /* 11458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4405 /* 11462 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4406 /* 11462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32),
4407 /* 11465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4408 /* 11467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4409 /* 11469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4410 /* 11471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4411 /* 11474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4412 /* 11480 */ GIR_RootConstrainSelectedInstOperands,
4413 /* 11481 */ // GIR_Coverage, 881,
4414 /* 11481 */ GIR_EraseRootFromParent_Done,
4415 /* 11482 */ // Label 297: @11482
4416 /* 11482 */ GIM_Reject,
4417 /* 11483 */ // Label 290: @11483
4418 /* 11483 */ GIM_Reject,
4419 /* 11484 */ // Label 271: @11484
4420 /* 11484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 298*/ GIMT_Encode4(11544), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3893 //
4421 /* 11491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4422 /* 11495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4423 /* 11499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4424 /* 11503 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4425 /* 11503 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4426 /* 11506 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
4427 /* 11510 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4428 /* 11515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32),
4429 /* 11518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
4430 /* 11520 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
4431 /* 11522 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
4432 /* 11524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
4433 /* 11527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4434 /* 11533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4435 /* 11539 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4436 /* 11542 */ GIR_RootConstrainSelectedInstOperands,
4437 /* 11543 */ // GIR_Coverage, 3893,
4438 /* 11543 */ GIR_EraseRootFromParent_Done,
4439 /* 11544 */ // Label 298: @11544
4440 /* 11544 */ GIM_Reject,
4441 /* 11545 */ // Label 270: @11545
4442 /* 11545 */ GIM_Reject,
4443 /* 11546 */ // Label 104: @11546
4444 /* 11546 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(12548),
4445 /* 11551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4446 /* 11554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
4447 /* 11557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4448 /* 11561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 300*/ GIMT_Encode4(11628), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 902 //
4449 /* 11568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4450 /* 11572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4451 /* 11576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4452 /* 11580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4453 /* 11585 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4454 /* 11589 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4455 /* 11593 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4456 /* 11597 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4457 /* 11602 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4458 /* 11604 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4459 /* 11604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4460 /* 11607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4461 /* 11609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4462 /* 11613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4463 /* 11617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4464 /* 11620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4465 /* 11626 */ GIR_RootConstrainSelectedInstOperands,
4466 /* 11627 */ // GIR_Coverage, 902,
4467 /* 11627 */ GIR_EraseRootFromParent_Done,
4468 /* 11628 */ // Label 300: @11628
4469 /* 11628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 301*/ GIMT_Encode4(11695), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 901 //
4470 /* 11635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4471 /* 11639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4472 /* 11643 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4473 /* 11647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4474 /* 11652 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4475 /* 11656 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4476 /* 11660 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4477 /* 11664 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4478 /* 11669 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4479 /* 11671 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4480 /* 11671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4481 /* 11674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4482 /* 11676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4483 /* 11680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4484 /* 11684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4485 /* 11687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4486 /* 11693 */ GIR_RootConstrainSelectedInstOperands,
4487 /* 11694 */ // GIR_Coverage, 901,
4488 /* 11694 */ GIR_EraseRootFromParent_Done,
4489 /* 11695 */ // Label 301: @11695
4490 /* 11695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 302*/ GIMT_Encode4(11762), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 890 //
4491 /* 11702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4492 /* 11706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4493 /* 11710 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4494 /* 11714 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4495 /* 11719 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4496 /* 11723 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4497 /* 11727 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4498 /* 11731 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4499 /* 11736 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4500 /* 11738 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4501 /* 11738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64),
4502 /* 11741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4503 /* 11743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4504 /* 11747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4505 /* 11751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4506 /* 11754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4507 /* 11760 */ GIR_RootConstrainSelectedInstOperands,
4508 /* 11761 */ // GIR_Coverage, 890,
4509 /* 11761 */ GIR_EraseRootFromParent_Done,
4510 /* 11762 */ // Label 302: @11762
4511 /* 11762 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(11918),
4512 /* 11767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4513 /* 11771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 304*/ GIMT_Encode4(11844), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6214 //
4514 /* 11778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4515 /* 11782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4516 /* 11786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4517 /* 11790 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4518 /* 11794 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4519 /* 11798 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4520 /* 11802 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4521 /* 11806 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4522 /* 11811 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4523 /* 11816 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4524 /* 11818 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4525 /* 11818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
4526 /* 11821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4527 /* 11823 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4528 /* 11825 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4529 /* 11829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4530 /* 11833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4531 /* 11836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4532 /* 11842 */ GIR_RootConstrainSelectedInstOperands,
4533 /* 11843 */ // GIR_Coverage, 6214,
4534 /* 11843 */ GIR_EraseRootFromParent_Done,
4535 /* 11844 */ // Label 304: @11844
4536 /* 11844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 305*/ GIMT_Encode4(11917), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6217 //
4537 /* 11851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4538 /* 11855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4539 /* 11859 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4540 /* 11863 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4541 /* 11867 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4542 /* 11871 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4543 /* 11875 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4544 /* 11879 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4545 /* 11884 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4546 /* 11889 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4547 /* 11891 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4548 /* 11891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
4549 /* 11894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4550 /* 11896 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4551 /* 11898 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4552 /* 11902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4553 /* 11906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4554 /* 11909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4555 /* 11915 */ GIR_RootConstrainSelectedInstOperands,
4556 /* 11916 */ // GIR_Coverage, 6217,
4557 /* 11916 */ GIR_EraseRootFromParent_Done,
4558 /* 11917 */ // Label 305: @11917
4559 /* 11917 */ GIM_Reject,
4560 /* 11918 */ // Label 303: @11918
4561 /* 11918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 306*/ GIMT_Encode4(11985), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 900 //
4562 /* 11925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4563 /* 11929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4564 /* 11933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4565 /* 11937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4566 /* 11942 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4567 /* 11946 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4568 /* 11950 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4569 /* 11954 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4570 /* 11959 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4571 /* 11961 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4572 /* 11961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4573 /* 11964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4574 /* 11966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4575 /* 11970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4576 /* 11974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4577 /* 11977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4578 /* 11983 */ GIR_RootConstrainSelectedInstOperands,
4579 /* 11984 */ // GIR_Coverage, 900,
4580 /* 11984 */ GIR_EraseRootFromParent_Done,
4581 /* 11985 */ // Label 306: @11985
4582 /* 11985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 307*/ GIMT_Encode4(12052), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 899 //
4583 /* 11992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4584 /* 11996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4585 /* 12000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4586 /* 12004 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4587 /* 12009 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4588 /* 12013 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4589 /* 12017 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4590 /* 12021 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4591 /* 12026 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4592 /* 12028 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4593 /* 12028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4594 /* 12031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4595 /* 12033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4596 /* 12037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4597 /* 12041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4598 /* 12044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4599 /* 12050 */ GIR_RootConstrainSelectedInstOperands,
4600 /* 12051 */ // GIR_Coverage, 899,
4601 /* 12051 */ GIR_EraseRootFromParent_Done,
4602 /* 12052 */ // Label 307: @12052
4603 /* 12052 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(12208),
4604 /* 12057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4605 /* 12061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 309*/ GIMT_Encode4(12134), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1355 //
4606 /* 12068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4607 /* 12072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4608 /* 12076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4609 /* 12080 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4610 /* 12084 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4611 /* 12088 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4612 /* 12092 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4613 /* 12096 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4614 /* 12101 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4615 /* 12106 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4616 /* 12108 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4617 /* 12108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
4618 /* 12111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4619 /* 12113 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4620 /* 12115 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4621 /* 12119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4622 /* 12123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4623 /* 12126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4624 /* 12132 */ GIR_RootConstrainSelectedInstOperands,
4625 /* 12133 */ // GIR_Coverage, 1355,
4626 /* 12133 */ GIR_EraseRootFromParent_Done,
4627 /* 12134 */ // Label 309: @12134
4628 /* 12134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 310*/ GIMT_Encode4(12207), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1358 //
4629 /* 12141 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4630 /* 12145 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4631 /* 12149 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4632 /* 12153 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4633 /* 12157 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4634 /* 12161 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4635 /* 12165 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4636 /* 12169 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4637 /* 12174 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4638 /* 12179 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4639 /* 12181 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4640 /* 12181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
4641 /* 12184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4642 /* 12186 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4643 /* 12188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4644 /* 12192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4645 /* 12196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4646 /* 12199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4647 /* 12205 */ GIR_RootConstrainSelectedInstOperands,
4648 /* 12206 */ // GIR_Coverage, 1358,
4649 /* 12206 */ GIR_EraseRootFromParent_Done,
4650 /* 12207 */ // Label 310: @12207
4651 /* 12207 */ GIM_Reject,
4652 /* 12208 */ // Label 308: @12208
4653 /* 12208 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(12362),
4654 /* 12213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4655 /* 12217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 312*/ GIMT_Encode4(12265), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6069 //
4656 /* 12224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4657 /* 12228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4658 /* 12232 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4659 /* 12236 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4660 /* 12241 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4661 /* 12243 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4662 /* 12243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4663 /* 12246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4664 /* 12248 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4665 /* 12250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4666 /* 12254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4667 /* 12257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4668 /* 12263 */ GIR_RootConstrainSelectedInstOperands,
4669 /* 12264 */ // GIR_Coverage, 6069,
4670 /* 12264 */ GIR_EraseRootFromParent_Done,
4671 /* 12265 */ // Label 312: @12265
4672 /* 12265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 313*/ GIMT_Encode4(12313), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6063 //
4673 /* 12272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4674 /* 12276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4675 /* 12280 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4676 /* 12284 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4677 /* 12289 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4678 /* 12291 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4679 /* 12291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
4680 /* 12294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4681 /* 12296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4682 /* 12298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4683 /* 12302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4684 /* 12305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4685 /* 12311 */ GIR_RootConstrainSelectedInstOperands,
4686 /* 12312 */ // GIR_Coverage, 6063,
4687 /* 12312 */ GIR_EraseRootFromParent_Done,
4688 /* 12313 */ // Label 313: @12313
4689 /* 12313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 314*/ GIMT_Encode4(12361), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6068 //
4690 /* 12320 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4691 /* 12324 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4692 /* 12328 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4693 /* 12332 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4694 /* 12337 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4695 /* 12339 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4696 /* 12339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4697 /* 12342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4698 /* 12344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4699 /* 12346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4700 /* 12350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4701 /* 12353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4702 /* 12359 */ GIR_RootConstrainSelectedInstOperands,
4703 /* 12360 */ // GIR_Coverage, 6068,
4704 /* 12360 */ GIR_EraseRootFromParent_Done,
4705 /* 12361 */ // Label 314: @12361
4706 /* 12361 */ GIM_Reject,
4707 /* 12362 */ // Label 311: @12362
4708 /* 12362 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(12547),
4709 /* 12367 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4710 /* 12371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 316*/ GIMT_Encode4(12419), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 911 //
4711 /* 12378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4712 /* 12382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4713 /* 12386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4714 /* 12390 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4715 /* 12395 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4716 /* 12397 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4717 /* 12397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4718 /* 12400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4719 /* 12402 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4720 /* 12404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4721 /* 12408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4722 /* 12411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4723 /* 12417 */ GIR_RootConstrainSelectedInstOperands,
4724 /* 12418 */ // GIR_Coverage, 911,
4725 /* 12418 */ GIR_EraseRootFromParent_Done,
4726 /* 12419 */ // Label 316: @12419
4727 /* 12419 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 317*/ GIMT_Encode4(12467), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 905 //
4728 /* 12426 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4729 /* 12430 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4730 /* 12434 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4731 /* 12438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4732 /* 12443 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4733 /* 12445 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4734 /* 12445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
4735 /* 12448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4736 /* 12450 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4737 /* 12452 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4738 /* 12456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4739 /* 12459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4740 /* 12465 */ GIR_RootConstrainSelectedInstOperands,
4741 /* 12466 */ // GIR_Coverage, 905,
4742 /* 12466 */ GIR_EraseRootFromParent_Done,
4743 /* 12467 */ // Label 317: @12467
4744 /* 12467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 318*/ GIMT_Encode4(12515), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 910 //
4745 /* 12474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4746 /* 12478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4747 /* 12482 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4748 /* 12486 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4749 /* 12491 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4750 /* 12493 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4751 /* 12493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4752 /* 12496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4753 /* 12498 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4754 /* 12500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4755 /* 12504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4756 /* 12507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4757 /* 12513 */ GIR_RootConstrainSelectedInstOperands,
4758 /* 12514 */ // GIR_Coverage, 910,
4759 /* 12514 */ GIR_EraseRootFromParent_Done,
4760 /* 12515 */ // Label 318: @12515
4761 /* 12515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 319*/ GIMT_Encode4(12546), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 883 //
4762 /* 12522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4763 /* 12526 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
4764 /* 12526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64),
4765 /* 12529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4766 /* 12531 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4767 /* 12533 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4768 /* 12535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4769 /* 12538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4770 /* 12544 */ GIR_RootConstrainSelectedInstOperands,
4771 /* 12545 */ // GIR_Coverage, 883,
4772 /* 12545 */ GIR_EraseRootFromParent_Done,
4773 /* 12546 */ // Label 319: @12546
4774 /* 12546 */ GIM_Reject,
4775 /* 12547 */ // Label 315: @12547
4776 /* 12547 */ GIM_Reject,
4777 /* 12548 */ // Label 299: @12548
4778 /* 12548 */ GIM_Reject,
4779 /* 12549 */ // Label 105: @12549
4780 /* 12549 */ GIM_Reject,
4781 /* 12550 */ // Label 1: @12550
4782 /* 12550 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 329*/ GIMT_Encode4(15647),
4783 /* 12561 */ /*GILLT_s32*//*Label 320*/ GIMT_Encode4(12613),
4784 /* 12565 */ /*GILLT_s64*//*Label 321*/ GIMT_Encode4(13218), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
4785 /* 12585 */ /*GILLT_v8s8*//*Label 322*/ GIMT_Encode4(13264),
4786 /* 12589 */ /*GILLT_v16s8*//*Label 323*/ GIMT_Encode4(13377),
4787 /* 12593 */ /*GILLT_v4s16*//*Label 324*/ GIMT_Encode4(13556),
4788 /* 12597 */ /*GILLT_v8s16*//*Label 325*/ GIMT_Encode4(13669),
4789 /* 12601 */ /*GILLT_v2s32*//*Label 326*/ GIMT_Encode4(14333),
4790 /* 12605 */ /*GILLT_v4s32*//*Label 327*/ GIMT_Encode4(14446),
4791 /* 12609 */ /*GILLT_v2s64*//*Label 328*/ GIMT_Encode4(15110),
4792 /* 12613 */ // Label 320: @12613
4793 /* 12613 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(13217),
4794 /* 12618 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
4795 /* 12621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4796 /* 12624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 331*/ GIMT_Encode4(12667), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 329 //
4797 /* 12631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4798 /* 12635 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
4799 /* 12639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4800 /* 12643 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
4801 /* 12643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB),
4802 /* 12646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4803 /* 12648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
4804 /* 12654 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4805 /* 12656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4806 /* 12659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4807 /* 12665 */ GIR_RootConstrainSelectedInstOperands,
4808 /* 12666 */ // GIR_Coverage, 329,
4809 /* 12666 */ GIR_EraseRootFromParent_Done,
4810 /* 12667 */ // Label 331: @12667
4811 /* 12667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 332*/ GIMT_Encode4(12723), GIMT_Encode2(GIFBS_IsARM), // Rule ID 95 //
4812 /* 12674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4813 /* 12678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4814 /* 12682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4815 /* 12686 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4816 /* 12690 */ // MIs[1] Operand 1
4817 /* 12690 */ // No operand predicates
4818 /* 12690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4819 /* 12694 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4820 /* 12696 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4821 /* 12696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri),
4822 /* 12699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4823 /* 12701 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4824 /* 12703 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4825 /* 12706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4826 /* 12709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4827 /* 12715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4828 /* 12721 */ GIR_RootConstrainSelectedInstOperands,
4829 /* 12722 */ // GIR_Coverage, 95,
4830 /* 12722 */ GIR_EraseRootFromParent_Done,
4831 /* 12723 */ // Label 332: @12723
4832 /* 12723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 333*/ GIMT_Encode4(12779), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 426 //
4833 /* 12730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4834 /* 12734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4835 /* 12738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4836 /* 12742 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
4837 /* 12746 */ // MIs[1] Operand 1
4838 /* 12746 */ // No operand predicates
4839 /* 12746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4840 /* 12750 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4841 /* 12752 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4842 /* 12752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri),
4843 /* 12755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4844 /* 12757 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4845 /* 12759 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4846 /* 12762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4847 /* 12765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4848 /* 12771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4849 /* 12777 */ GIR_RootConstrainSelectedInstOperands,
4850 /* 12778 */ // GIR_Coverage, 426,
4851 /* 12778 */ GIR_EraseRootFromParent_Done,
4852 /* 12779 */ // Label 333: @12779
4853 /* 12779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 334*/ GIMT_Encode4(12835), GIMT_Encode2(GIFBS_IsARM), // Rule ID 75 //
4854 /* 12786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4855 /* 12790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4856 /* 12794 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4857 /* 12798 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4858 /* 12802 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4859 /* 12806 */ // MIs[1] Operand 1
4860 /* 12806 */ // No operand predicates
4861 /* 12806 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4862 /* 12808 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4863 /* 12808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri),
4864 /* 12811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4865 /* 12813 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4866 /* 12815 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4867 /* 12818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4868 /* 12821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4869 /* 12827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4870 /* 12833 */ GIR_RootConstrainSelectedInstOperands,
4871 /* 12834 */ // GIR_Coverage, 75,
4872 /* 12834 */ GIR_EraseRootFromParent_Done,
4873 /* 12835 */ // Label 334: @12835
4874 /* 12835 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(12943),
4875 /* 12840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4876 /* 12844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 336*/ GIMT_Encode4(12896), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 410 //
4877 /* 12851 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4878 /* 12855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4879 /* 12859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4880 /* 12863 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
4881 /* 12867 */ // MIs[1] Operand 1
4882 /* 12867 */ // No operand predicates
4883 /* 12867 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4884 /* 12869 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4885 /* 12869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri),
4886 /* 12872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4887 /* 12874 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4888 /* 12876 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4889 /* 12879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4890 /* 12882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4891 /* 12888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4892 /* 12894 */ GIR_RootConstrainSelectedInstOperands,
4893 /* 12895 */ // GIR_Coverage, 410,
4894 /* 12895 */ GIR_EraseRootFromParent_Done,
4895 /* 12896 */ // Label 336: @12896
4896 /* 12896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 337*/ GIMT_Encode4(12942), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 411 //
4897 /* 12903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4898 /* 12907 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4899 /* 12911 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4900 /* 12915 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
4901 /* 12919 */ // MIs[1] Operand 1
4902 /* 12919 */ // No operand predicates
4903 /* 12919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4904 /* 12921 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4905 /* 12921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12),
4906 /* 12924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4907 /* 12926 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4908 /* 12928 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4909 /* 12931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4910 /* 12934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4911 /* 12940 */ GIR_RootConstrainSelectedInstOperands,
4912 /* 12941 */ // GIR_Coverage, 411,
4913 /* 12941 */ GIR_EraseRootFromParent_Done,
4914 /* 12942 */ // Label 337: @12942
4915 /* 12942 */ GIM_Reject,
4916 /* 12943 */ // Label 335: @12943
4917 /* 12943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 338*/ GIMT_Encode4(13012), GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), // Rule ID 172 //
4918 /* 12950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4919 /* 12954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4920 /* 12958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4921 /* 12962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4922 /* 12966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4923 /* 12970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4924 /* 12974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4925 /* 12979 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4926 /* 12984 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4927 /* 12986 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
4928 /* 12986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS),
4929 /* 12989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4930 /* 12991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4931 /* 12995 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4932 /* 12999 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
4933 /* 13001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4934 /* 13004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4935 /* 13010 */ GIR_RootConstrainSelectedInstOperands,
4936 /* 13011 */ // GIR_Coverage, 172,
4937 /* 13011 */ GIR_EraseRootFromParent_Done,
4938 /* 13012 */ // Label 338: @13012
4939 /* 13012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 339*/ GIMT_Encode4(13081), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 503 //
4940 /* 13019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4941 /* 13023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4942 /* 13027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4943 /* 13031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4944 /* 13035 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4945 /* 13039 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4946 /* 13043 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4947 /* 13048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4948 /* 13053 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4949 /* 13055 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
4950 /* 13055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS),
4951 /* 13058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4952 /* 13060 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4953 /* 13064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4954 /* 13068 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
4955 /* 13070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4956 /* 13073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4957 /* 13079 */ GIR_RootConstrainSelectedInstOperands,
4958 /* 13080 */ // GIR_Coverage, 503,
4959 /* 13080 */ GIR_EraseRootFromParent_Done,
4960 /* 13081 */ // Label 339: @13081
4961 /* 13081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 340*/ GIMT_Encode4(13126), GIMT_Encode2(GIFBS_IsARM), // Rule ID 76 //
4962 /* 13088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4963 /* 13092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4964 /* 13096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4965 /* 13100 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4966 /* 13100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr),
4967 /* 13103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4968 /* 13105 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4969 /* 13107 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
4970 /* 13109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4971 /* 13112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4972 /* 13118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4973 /* 13124 */ GIR_RootConstrainSelectedInstOperands,
4974 /* 13125 */ // GIR_Coverage, 76,
4975 /* 13125 */ GIR_EraseRootFromParent_Done,
4976 /* 13126 */ // Label 340: @13126
4977 /* 13126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 341*/ GIMT_Encode4(13171), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 332 //
4978 /* 13133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4979 /* 13137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4980 /* 13141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4981 /* 13145 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
4982 /* 13145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr),
4983 /* 13148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4984 /* 13150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
4985 /* 13156 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4986 /* 13158 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
4987 /* 13160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4988 /* 13163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4989 /* 13169 */ GIR_RootConstrainSelectedInstOperands,
4990 /* 13170 */ // GIR_Coverage, 332,
4991 /* 13170 */ GIR_EraseRootFromParent_Done,
4992 /* 13171 */ // Label 341: @13171
4993 /* 13171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 342*/ GIMT_Encode4(13216), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 412 //
4994 /* 13178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4995 /* 13182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4996 /* 13186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4997 /* 13190 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4998 /* 13190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr),
4999 /* 13193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5000 /* 13195 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5001 /* 13197 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
5002 /* 13199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5003 /* 13202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5004 /* 13208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5005 /* 13214 */ GIR_RootConstrainSelectedInstOperands,
5006 /* 13215 */ // GIR_Coverage, 412,
5007 /* 13215 */ GIR_EraseRootFromParent_Done,
5008 /* 13216 */ // Label 342: @13216
5009 /* 13216 */ GIM_Reject,
5010 /* 13217 */ // Label 330: @13217
5011 /* 13217 */ GIM_Reject,
5012 /* 13218 */ // Label 321: @13218
5013 /* 13218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 343*/ GIMT_Encode4(13263), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1128 //
5014 /* 13225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
5015 /* 13228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5016 /* 13231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5017 /* 13235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5018 /* 13239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5019 /* 13243 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
5020 /* 13243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64),
5021 /* 13246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5022 /* 13248 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5023 /* 13250 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5024 /* 13252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5025 /* 13255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5026 /* 13261 */ GIR_RootConstrainSelectedInstOperands,
5027 /* 13262 */ // GIR_Coverage, 1128,
5028 /* 13262 */ GIR_EraseRootFromParent_Done,
5029 /* 13263 */ // Label 343: @13263
5030 /* 13263 */ GIM_Reject,
5031 /* 13264 */ // Label 322: @13264
5032 /* 13264 */ GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(13376),
5033 /* 13269 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
5034 /* 13272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
5035 /* 13275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5036 /* 13279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5037 /* 13283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 345*/ GIMT_Encode4(13344), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1053 //
5038 /* 13290 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5039 /* 13294 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5040 /* 13298 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5041 /* 13302 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
5042 /* 13306 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5043 /* 13311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5044 /* 13316 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5045 /* 13318 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5046 /* 13318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8),
5047 /* 13321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5048 /* 13323 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5049 /* 13325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5050 /* 13329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5051 /* 13333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5052 /* 13336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5053 /* 13342 */ GIR_RootConstrainSelectedInstOperands,
5054 /* 13343 */ // GIR_Coverage, 1053,
5055 /* 13343 */ GIR_EraseRootFromParent_Done,
5056 /* 13344 */ // Label 345: @13344
5057 /* 13344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 346*/ GIMT_Encode4(13375), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1122 //
5058 /* 13351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5059 /* 13355 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5060 /* 13355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8),
5061 /* 13358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5062 /* 13360 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5063 /* 13362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5064 /* 13364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5065 /* 13367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5066 /* 13373 */ GIR_RootConstrainSelectedInstOperands,
5067 /* 13374 */ // GIR_Coverage, 1122,
5068 /* 13374 */ GIR_EraseRootFromParent_Done,
5069 /* 13375 */ // Label 346: @13375
5070 /* 13375 */ GIM_Reject,
5071 /* 13376 */ // Label 344: @13376
5072 /* 13376 */ GIM_Reject,
5073 /* 13377 */ // Label 323: @13377
5074 /* 13377 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(13555),
5075 /* 13382 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
5076 /* 13385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
5077 /* 13388 */ GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(13494),
5078 /* 13393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5079 /* 13397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5080 /* 13401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 349*/ GIMT_Encode4(13462), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1056 //
5081 /* 13408 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5082 /* 13412 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5083 /* 13416 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
5084 /* 13420 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
5085 /* 13424 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5086 /* 13429 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5087 /* 13434 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5088 /* 13436 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5089 /* 13436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8),
5090 /* 13439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5091 /* 13441 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5092 /* 13443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5093 /* 13447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5094 /* 13451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5095 /* 13454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5096 /* 13460 */ GIR_RootConstrainSelectedInstOperands,
5097 /* 13461 */ // GIR_Coverage, 1056,
5098 /* 13461 */ GIR_EraseRootFromParent_Done,
5099 /* 13462 */ // Label 349: @13462
5100 /* 13462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 350*/ GIMT_Encode4(13493), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1125 //
5101 /* 13469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5102 /* 13473 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5103 /* 13473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8),
5104 /* 13476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5105 /* 13478 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5106 /* 13480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5107 /* 13482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5108 /* 13485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5109 /* 13491 */ GIR_RootConstrainSelectedInstOperands,
5110 /* 13492 */ // GIR_Coverage, 1125,
5111 /* 13492 */ GIR_EraseRootFromParent_Done,
5112 /* 13493 */ // Label 350: @13493
5113 /* 13493 */ GIM_Reject,
5114 /* 13494 */ // Label 348: @13494
5115 /* 13494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 351*/ GIMT_Encode4(13554), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3897 //
5116 /* 13501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5117 /* 13505 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5118 /* 13509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5119 /* 13513 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5120 /* 13513 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5121 /* 13516 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5122 /* 13520 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5123 /* 13525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8),
5124 /* 13528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5125 /* 13530 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5126 /* 13532 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5127 /* 13534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5128 /* 13537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5129 /* 13543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5130 /* 13549 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5131 /* 13552 */ GIR_RootConstrainSelectedInstOperands,
5132 /* 13553 */ // GIR_Coverage, 3897,
5133 /* 13553 */ GIR_EraseRootFromParent_Done,
5134 /* 13554 */ // Label 351: @13554
5135 /* 13554 */ GIM_Reject,
5136 /* 13555 */ // Label 347: @13555
5137 /* 13555 */ GIM_Reject,
5138 /* 13556 */ // Label 324: @13556
5139 /* 13556 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(13668),
5140 /* 13561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
5141 /* 13564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
5142 /* 13567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5143 /* 13571 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5144 /* 13575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 353*/ GIMT_Encode4(13636), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1054 //
5145 /* 13582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5146 /* 13586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5147 /* 13590 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5148 /* 13594 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5149 /* 13598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5150 /* 13603 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5151 /* 13608 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5152 /* 13610 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5153 /* 13610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16),
5154 /* 13613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5155 /* 13615 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5156 /* 13617 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5157 /* 13621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5158 /* 13625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5159 /* 13628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5160 /* 13634 */ GIR_RootConstrainSelectedInstOperands,
5161 /* 13635 */ // GIR_Coverage, 1054,
5162 /* 13635 */ GIR_EraseRootFromParent_Done,
5163 /* 13636 */ // Label 353: @13636
5164 /* 13636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 354*/ GIMT_Encode4(13667), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1123 //
5165 /* 13643 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5166 /* 13647 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5167 /* 13647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16),
5168 /* 13650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5169 /* 13652 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5170 /* 13654 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5171 /* 13656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5172 /* 13659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5173 /* 13665 */ GIR_RootConstrainSelectedInstOperands,
5174 /* 13666 */ // GIR_Coverage, 1123,
5175 /* 13666 */ GIR_EraseRootFromParent_Done,
5176 /* 13667 */ // Label 354: @13667
5177 /* 13667 */ GIM_Reject,
5178 /* 13668 */ // Label 352: @13668
5179 /* 13668 */ GIM_Reject,
5180 /* 13669 */ // Label 325: @13669
5181 /* 13669 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(14332),
5182 /* 13674 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
5183 /* 13677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
5184 /* 13680 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(14271),
5185 /* 13685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5186 /* 13689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 357*/ GIMT_Encode4(13756), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1140 //
5187 /* 13696 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5188 /* 13700 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5189 /* 13704 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5190 /* 13708 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5191 /* 13713 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5192 /* 13717 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5193 /* 13721 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5194 /* 13725 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5195 /* 13730 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5196 /* 13732 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5197 /* 13732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5198 /* 13735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5199 /* 13737 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5200 /* 13741 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5201 /* 13745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5202 /* 13748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5203 /* 13754 */ GIR_RootConstrainSelectedInstOperands,
5204 /* 13755 */ // GIR_Coverage, 1140,
5205 /* 13755 */ GIR_EraseRootFromParent_Done,
5206 /* 13756 */ // Label 357: @13756
5207 /* 13756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 358*/ GIMT_Encode4(13823), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1139 //
5208 /* 13763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5209 /* 13767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5210 /* 13771 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5211 /* 13775 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5212 /* 13780 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5213 /* 13784 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5214 /* 13788 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5215 /* 13792 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5216 /* 13797 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5217 /* 13799 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5218 /* 13799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5219 /* 13802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5220 /* 13804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5221 /* 13808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5222 /* 13812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5223 /* 13815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5224 /* 13821 */ GIR_RootConstrainSelectedInstOperands,
5225 /* 13822 */ // GIR_Coverage, 1139,
5226 /* 13822 */ GIR_EraseRootFromParent_Done,
5227 /* 13823 */ // Label 358: @13823
5228 /* 13823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 359*/ GIMT_Encode4(13890), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1134 //
5229 /* 13830 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5230 /* 13834 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5231 /* 13838 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5232 /* 13842 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5233 /* 13847 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5234 /* 13851 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5235 /* 13855 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5236 /* 13859 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5237 /* 13864 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5238 /* 13866 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5239 /* 13866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16),
5240 /* 13869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5241 /* 13871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5242 /* 13875 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5243 /* 13879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5244 /* 13882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5245 /* 13888 */ GIR_RootConstrainSelectedInstOperands,
5246 /* 13889 */ // GIR_Coverage, 1134,
5247 /* 13889 */ GIR_EraseRootFromParent_Done,
5248 /* 13890 */ // Label 359: @13890
5249 /* 13890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 360*/ GIMT_Encode4(13957), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1138 //
5250 /* 13897 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5251 /* 13901 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5252 /* 13905 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5253 /* 13909 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5254 /* 13914 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5255 /* 13918 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5256 /* 13922 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5257 /* 13926 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5258 /* 13931 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5259 /* 13933 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5260 /* 13933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5261 /* 13936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5262 /* 13938 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5263 /* 13942 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5264 /* 13946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5265 /* 13949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5266 /* 13955 */ GIR_RootConstrainSelectedInstOperands,
5267 /* 13956 */ // GIR_Coverage, 1138,
5268 /* 13956 */ GIR_EraseRootFromParent_Done,
5269 /* 13957 */ // Label 360: @13957
5270 /* 13957 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 361*/ GIMT_Encode4(14024), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1137 //
5271 /* 13964 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5272 /* 13968 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5273 /* 13972 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5274 /* 13976 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5275 /* 13981 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5276 /* 13985 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5277 /* 13989 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5278 /* 13993 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5279 /* 13998 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5280 /* 14000 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5281 /* 14000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5282 /* 14003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5283 /* 14005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5284 /* 14009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5285 /* 14013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5286 /* 14016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5287 /* 14022 */ GIR_RootConstrainSelectedInstOperands,
5288 /* 14023 */ // GIR_Coverage, 1137,
5289 /* 14023 */ GIR_EraseRootFromParent_Done,
5290 /* 14024 */ // Label 361: @14024
5291 /* 14024 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(14270),
5292 /* 14029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5293 /* 14033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 363*/ GIMT_Encode4(14094), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1057 //
5294 /* 14040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5295 /* 14044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5296 /* 14048 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
5297 /* 14052 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
5298 /* 14056 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5299 /* 14061 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5300 /* 14066 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5301 /* 14068 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5302 /* 14068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16),
5303 /* 14071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5304 /* 14073 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5305 /* 14075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5306 /* 14079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5307 /* 14083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5308 /* 14086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5309 /* 14092 */ GIR_RootConstrainSelectedInstOperands,
5310 /* 14093 */ // GIR_Coverage, 1057,
5311 /* 14093 */ GIR_EraseRootFromParent_Done,
5312 /* 14094 */ // Label 363: @14094
5313 /* 14094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 364*/ GIMT_Encode4(14142), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1153 //
5314 /* 14101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5315 /* 14105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5316 /* 14109 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5317 /* 14113 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5318 /* 14118 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5319 /* 14120 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5320 /* 14120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5321 /* 14123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5322 /* 14125 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5323 /* 14127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5324 /* 14131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5325 /* 14134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5326 /* 14140 */ GIR_RootConstrainSelectedInstOperands,
5327 /* 14141 */ // GIR_Coverage, 1153,
5328 /* 14141 */ GIR_EraseRootFromParent_Done,
5329 /* 14142 */ // Label 364: @14142
5330 /* 14142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 365*/ GIMT_Encode4(14190), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1149 //
5331 /* 14149 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5332 /* 14153 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5333 /* 14157 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5334 /* 14161 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5335 /* 14166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5336 /* 14168 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5337 /* 14168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16),
5338 /* 14171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5339 /* 14173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5340 /* 14175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5341 /* 14179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5342 /* 14182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5343 /* 14188 */ GIR_RootConstrainSelectedInstOperands,
5344 /* 14189 */ // GIR_Coverage, 1149,
5345 /* 14189 */ GIR_EraseRootFromParent_Done,
5346 /* 14190 */ // Label 365: @14190
5347 /* 14190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 366*/ GIMT_Encode4(14238), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1152 //
5348 /* 14197 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5349 /* 14201 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5350 /* 14205 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5351 /* 14209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5352 /* 14214 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5353 /* 14216 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5354 /* 14216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5355 /* 14219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5356 /* 14221 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5357 /* 14223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5358 /* 14227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5359 /* 14230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5360 /* 14236 */ GIR_RootConstrainSelectedInstOperands,
5361 /* 14237 */ // GIR_Coverage, 1152,
5362 /* 14237 */ GIR_EraseRootFromParent_Done,
5363 /* 14238 */ // Label 366: @14238
5364 /* 14238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 367*/ GIMT_Encode4(14269), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1126 //
5365 /* 14245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5366 /* 14249 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5367 /* 14249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16),
5368 /* 14252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5369 /* 14254 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5370 /* 14256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5371 /* 14258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5372 /* 14261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5373 /* 14267 */ GIR_RootConstrainSelectedInstOperands,
5374 /* 14268 */ // GIR_Coverage, 1126,
5375 /* 14268 */ GIR_EraseRootFromParent_Done,
5376 /* 14269 */ // Label 367: @14269
5377 /* 14269 */ GIM_Reject,
5378 /* 14270 */ // Label 362: @14270
5379 /* 14270 */ GIM_Reject,
5380 /* 14271 */ // Label 356: @14271
5381 /* 14271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 368*/ GIMT_Encode4(14331), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3901 //
5382 /* 14278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5383 /* 14282 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5384 /* 14286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5385 /* 14290 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5386 /* 14290 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5387 /* 14293 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5388 /* 14297 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5389 /* 14302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16),
5390 /* 14305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5391 /* 14307 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5392 /* 14309 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5393 /* 14311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5394 /* 14314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5395 /* 14320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5396 /* 14326 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5397 /* 14329 */ GIR_RootConstrainSelectedInstOperands,
5398 /* 14330 */ // GIR_Coverage, 3901,
5399 /* 14330 */ GIR_EraseRootFromParent_Done,
5400 /* 14331 */ // Label 368: @14331
5401 /* 14331 */ GIM_Reject,
5402 /* 14332 */ // Label 355: @14332
5403 /* 14332 */ GIM_Reject,
5404 /* 14333 */ // Label 326: @14333
5405 /* 14333 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(14445),
5406 /* 14338 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
5407 /* 14341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
5408 /* 14344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5409 /* 14348 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5410 /* 14352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 370*/ GIMT_Encode4(14413), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1055 //
5411 /* 14359 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5412 /* 14363 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5413 /* 14367 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5414 /* 14371 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
5415 /* 14375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5416 /* 14380 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5417 /* 14385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5418 /* 14387 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5419 /* 14387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32),
5420 /* 14390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5421 /* 14392 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5422 /* 14394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5423 /* 14398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5424 /* 14402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5425 /* 14405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5426 /* 14411 */ GIR_RootConstrainSelectedInstOperands,
5427 /* 14412 */ // GIR_Coverage, 1055,
5428 /* 14412 */ GIR_EraseRootFromParent_Done,
5429 /* 14413 */ // Label 370: @14413
5430 /* 14413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 371*/ GIMT_Encode4(14444), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1124 //
5431 /* 14420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5432 /* 14424 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5433 /* 14424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32),
5434 /* 14427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5435 /* 14429 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5436 /* 14431 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5437 /* 14433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5438 /* 14436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5439 /* 14442 */ GIR_RootConstrainSelectedInstOperands,
5440 /* 14443 */ // GIR_Coverage, 1124,
5441 /* 14443 */ GIR_EraseRootFromParent_Done,
5442 /* 14444 */ // Label 371: @14444
5443 /* 14444 */ GIM_Reject,
5444 /* 14445 */ // Label 369: @14445
5445 /* 14445 */ GIM_Reject,
5446 /* 14446 */ // Label 327: @14446
5447 /* 14446 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(15109),
5448 /* 14451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
5449 /* 14454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
5450 /* 14457 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(15048),
5451 /* 14462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5452 /* 14466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 374*/ GIMT_Encode4(14533), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1144 //
5453 /* 14473 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5454 /* 14477 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5455 /* 14481 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5456 /* 14485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5457 /* 14490 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5458 /* 14494 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5459 /* 14498 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5460 /* 14502 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5461 /* 14507 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5462 /* 14509 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5463 /* 14509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5464 /* 14512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5465 /* 14514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5466 /* 14518 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5467 /* 14522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5468 /* 14525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5469 /* 14531 */ GIR_RootConstrainSelectedInstOperands,
5470 /* 14532 */ // GIR_Coverage, 1144,
5471 /* 14532 */ GIR_EraseRootFromParent_Done,
5472 /* 14533 */ // Label 374: @14533
5473 /* 14533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 375*/ GIMT_Encode4(14600), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1143 //
5474 /* 14540 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5475 /* 14544 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5476 /* 14548 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5477 /* 14552 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5478 /* 14557 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5479 /* 14561 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5480 /* 14565 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5481 /* 14569 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5482 /* 14574 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5483 /* 14576 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5484 /* 14576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5485 /* 14579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5486 /* 14581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5487 /* 14585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5488 /* 14589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5489 /* 14592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5490 /* 14598 */ GIR_RootConstrainSelectedInstOperands,
5491 /* 14599 */ // GIR_Coverage, 1143,
5492 /* 14599 */ GIR_EraseRootFromParent_Done,
5493 /* 14600 */ // Label 375: @14600
5494 /* 14600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 376*/ GIMT_Encode4(14667), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1135 //
5495 /* 14607 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5496 /* 14611 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5497 /* 14615 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5498 /* 14619 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5499 /* 14624 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5500 /* 14628 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5501 /* 14632 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5502 /* 14636 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5503 /* 14641 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5504 /* 14643 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5505 /* 14643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32),
5506 /* 14646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5507 /* 14648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5508 /* 14652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5509 /* 14656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5510 /* 14659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5511 /* 14665 */ GIR_RootConstrainSelectedInstOperands,
5512 /* 14666 */ // GIR_Coverage, 1135,
5513 /* 14666 */ GIR_EraseRootFromParent_Done,
5514 /* 14667 */ // Label 376: @14667
5515 /* 14667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 377*/ GIMT_Encode4(14734), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1142 //
5516 /* 14674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5517 /* 14678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5518 /* 14682 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5519 /* 14686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5520 /* 14691 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5521 /* 14695 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5522 /* 14699 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5523 /* 14703 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5524 /* 14708 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5525 /* 14710 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5526 /* 14710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5527 /* 14713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5528 /* 14715 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5529 /* 14719 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5530 /* 14723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5531 /* 14726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5532 /* 14732 */ GIR_RootConstrainSelectedInstOperands,
5533 /* 14733 */ // GIR_Coverage, 1142,
5534 /* 14733 */ GIR_EraseRootFromParent_Done,
5535 /* 14734 */ // Label 377: @14734
5536 /* 14734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 378*/ GIMT_Encode4(14801), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1141 //
5537 /* 14741 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5538 /* 14745 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5539 /* 14749 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5540 /* 14753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5541 /* 14758 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5542 /* 14762 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5543 /* 14766 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5544 /* 14770 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5545 /* 14775 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5546 /* 14777 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5547 /* 14777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5548 /* 14780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5549 /* 14782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5550 /* 14786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5551 /* 14790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5552 /* 14793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5553 /* 14799 */ GIR_RootConstrainSelectedInstOperands,
5554 /* 14800 */ // GIR_Coverage, 1141,
5555 /* 14800 */ GIR_EraseRootFromParent_Done,
5556 /* 14801 */ // Label 378: @14801
5557 /* 14801 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(15047),
5558 /* 14806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5559 /* 14810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 380*/ GIMT_Encode4(14871), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1058 //
5560 /* 14817 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5561 /* 14821 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5562 /* 14825 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5563 /* 14829 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5564 /* 14833 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5565 /* 14838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5566 /* 14843 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5567 /* 14845 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5568 /* 14845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32),
5569 /* 14848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5570 /* 14850 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5571 /* 14852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5572 /* 14856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5573 /* 14860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5574 /* 14863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5575 /* 14869 */ GIR_RootConstrainSelectedInstOperands,
5576 /* 14870 */ // GIR_Coverage, 1058,
5577 /* 14870 */ GIR_EraseRootFromParent_Done,
5578 /* 14871 */ // Label 380: @14871
5579 /* 14871 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 381*/ GIMT_Encode4(14919), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1155 //
5580 /* 14878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5581 /* 14882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5582 /* 14886 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5583 /* 14890 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5584 /* 14895 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5585 /* 14897 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5586 /* 14897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5587 /* 14900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5588 /* 14902 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5589 /* 14904 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5590 /* 14908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5591 /* 14911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5592 /* 14917 */ GIR_RootConstrainSelectedInstOperands,
5593 /* 14918 */ // GIR_Coverage, 1155,
5594 /* 14918 */ GIR_EraseRootFromParent_Done,
5595 /* 14919 */ // Label 381: @14919
5596 /* 14919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 382*/ GIMT_Encode4(14967), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1150 //
5597 /* 14926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5598 /* 14930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5599 /* 14934 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5600 /* 14938 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5601 /* 14943 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5602 /* 14945 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5603 /* 14945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32),
5604 /* 14948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5605 /* 14950 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5606 /* 14952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5607 /* 14956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5608 /* 14959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5609 /* 14965 */ GIR_RootConstrainSelectedInstOperands,
5610 /* 14966 */ // GIR_Coverage, 1150,
5611 /* 14966 */ GIR_EraseRootFromParent_Done,
5612 /* 14967 */ // Label 382: @14967
5613 /* 14967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 383*/ GIMT_Encode4(15015), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1154 //
5614 /* 14974 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5615 /* 14978 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5616 /* 14982 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5617 /* 14986 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5618 /* 14991 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5619 /* 14993 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5620 /* 14993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5621 /* 14996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5622 /* 14998 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5623 /* 15000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5624 /* 15004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5625 /* 15007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5626 /* 15013 */ GIR_RootConstrainSelectedInstOperands,
5627 /* 15014 */ // GIR_Coverage, 1154,
5628 /* 15014 */ GIR_EraseRootFromParent_Done,
5629 /* 15015 */ // Label 383: @15015
5630 /* 15015 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 384*/ GIMT_Encode4(15046), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1127 //
5631 /* 15022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5632 /* 15026 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5633 /* 15026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32),
5634 /* 15029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5635 /* 15031 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5636 /* 15033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5637 /* 15035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5638 /* 15038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5639 /* 15044 */ GIR_RootConstrainSelectedInstOperands,
5640 /* 15045 */ // GIR_Coverage, 1127,
5641 /* 15045 */ GIR_EraseRootFromParent_Done,
5642 /* 15046 */ // Label 384: @15046
5643 /* 15046 */ GIM_Reject,
5644 /* 15047 */ // Label 379: @15047
5645 /* 15047 */ GIM_Reject,
5646 /* 15048 */ // Label 373: @15048
5647 /* 15048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 385*/ GIMT_Encode4(15108), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3905 //
5648 /* 15055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5649 /* 15059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5650 /* 15063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5651 /* 15067 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5652 /* 15067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5653 /* 15070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5654 /* 15074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5655 /* 15079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32),
5656 /* 15082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5657 /* 15084 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5658 /* 15086 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5659 /* 15088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5660 /* 15091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5661 /* 15097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5662 /* 15103 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5663 /* 15106 */ GIR_RootConstrainSelectedInstOperands,
5664 /* 15107 */ // GIR_Coverage, 3905,
5665 /* 15107 */ GIR_EraseRootFromParent_Done,
5666 /* 15108 */ // Label 385: @15108
5667 /* 15108 */ GIM_Reject,
5668 /* 15109 */ // Label 372: @15109
5669 /* 15109 */ GIM_Reject,
5670 /* 15110 */ // Label 328: @15110
5671 /* 15110 */ GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(15646),
5672 /* 15115 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
5673 /* 15118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
5674 /* 15121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5675 /* 15125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 387*/ GIMT_Encode4(15192), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1148 //
5676 /* 15132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5677 /* 15136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5678 /* 15140 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5679 /* 15144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5680 /* 15149 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5681 /* 15153 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5682 /* 15157 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5683 /* 15161 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5684 /* 15166 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5685 /* 15168 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5686 /* 15168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5687 /* 15171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5688 /* 15173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5689 /* 15177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5690 /* 15181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5691 /* 15184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5692 /* 15190 */ GIR_RootConstrainSelectedInstOperands,
5693 /* 15191 */ // GIR_Coverage, 1148,
5694 /* 15191 */ GIR_EraseRootFromParent_Done,
5695 /* 15192 */ // Label 387: @15192
5696 /* 15192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 388*/ GIMT_Encode4(15259), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1147 //
5697 /* 15199 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5698 /* 15203 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5699 /* 15207 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5700 /* 15211 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5701 /* 15216 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5702 /* 15220 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5703 /* 15224 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5704 /* 15228 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5705 /* 15233 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5706 /* 15235 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5707 /* 15235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5708 /* 15238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5709 /* 15240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5710 /* 15244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5711 /* 15248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5712 /* 15251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5713 /* 15257 */ GIR_RootConstrainSelectedInstOperands,
5714 /* 15258 */ // GIR_Coverage, 1147,
5715 /* 15258 */ GIR_EraseRootFromParent_Done,
5716 /* 15259 */ // Label 388: @15259
5717 /* 15259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 389*/ GIMT_Encode4(15326), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1136 //
5718 /* 15266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5719 /* 15270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5720 /* 15274 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5721 /* 15278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5722 /* 15283 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5723 /* 15287 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5724 /* 15291 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5725 /* 15295 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5726 /* 15300 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5727 /* 15302 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5728 /* 15302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64),
5729 /* 15305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5730 /* 15307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5731 /* 15311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5732 /* 15315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5733 /* 15318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5734 /* 15324 */ GIR_RootConstrainSelectedInstOperands,
5735 /* 15325 */ // GIR_Coverage, 1136,
5736 /* 15325 */ GIR_EraseRootFromParent_Done,
5737 /* 15326 */ // Label 389: @15326
5738 /* 15326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 390*/ GIMT_Encode4(15393), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1146 //
5739 /* 15333 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5740 /* 15337 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5741 /* 15341 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5742 /* 15345 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5743 /* 15350 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5744 /* 15354 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5745 /* 15358 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5746 /* 15362 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5747 /* 15367 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5748 /* 15369 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5749 /* 15369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5750 /* 15372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5751 /* 15374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5752 /* 15378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5753 /* 15382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5754 /* 15385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5755 /* 15391 */ GIR_RootConstrainSelectedInstOperands,
5756 /* 15392 */ // GIR_Coverage, 1146,
5757 /* 15392 */ GIR_EraseRootFromParent_Done,
5758 /* 15393 */ // Label 390: @15393
5759 /* 15393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 391*/ GIMT_Encode4(15460), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1145 //
5760 /* 15400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5761 /* 15404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5762 /* 15408 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5763 /* 15412 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5764 /* 15417 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5765 /* 15421 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5766 /* 15425 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5767 /* 15429 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5768 /* 15434 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5769 /* 15436 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5770 /* 15436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5771 /* 15439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5772 /* 15441 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5773 /* 15445 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5774 /* 15449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5775 /* 15452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5776 /* 15458 */ GIR_RootConstrainSelectedInstOperands,
5777 /* 15459 */ // GIR_Coverage, 1145,
5778 /* 15459 */ GIR_EraseRootFromParent_Done,
5779 /* 15460 */ // Label 391: @15460
5780 /* 15460 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(15645),
5781 /* 15465 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5782 /* 15469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 393*/ GIMT_Encode4(15517), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1157 //
5783 /* 15476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5784 /* 15480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5785 /* 15484 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5786 /* 15488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5787 /* 15493 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5788 /* 15495 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5789 /* 15495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
5790 /* 15498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5791 /* 15500 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5792 /* 15502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5793 /* 15506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5794 /* 15509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5795 /* 15515 */ GIR_RootConstrainSelectedInstOperands,
5796 /* 15516 */ // GIR_Coverage, 1157,
5797 /* 15516 */ GIR_EraseRootFromParent_Done,
5798 /* 15517 */ // Label 393: @15517
5799 /* 15517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 394*/ GIMT_Encode4(15565), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1151 //
5800 /* 15524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5801 /* 15528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5802 /* 15532 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5803 /* 15536 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5804 /* 15541 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5805 /* 15543 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5806 /* 15543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64),
5807 /* 15546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5808 /* 15548 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5809 /* 15550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5810 /* 15554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5811 /* 15557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5812 /* 15563 */ GIR_RootConstrainSelectedInstOperands,
5813 /* 15564 */ // GIR_Coverage, 1151,
5814 /* 15564 */ GIR_EraseRootFromParent_Done,
5815 /* 15565 */ // Label 394: @15565
5816 /* 15565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 395*/ GIMT_Encode4(15613), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1156 //
5817 /* 15572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5818 /* 15576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5819 /* 15580 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5820 /* 15584 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5821 /* 15589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5822 /* 15591 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5823 /* 15591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
5824 /* 15594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5825 /* 15596 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5826 /* 15598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5827 /* 15602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5828 /* 15605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5829 /* 15611 */ GIR_RootConstrainSelectedInstOperands,
5830 /* 15612 */ // GIR_Coverage, 1156,
5831 /* 15612 */ GIR_EraseRootFromParent_Done,
5832 /* 15613 */ // Label 395: @15613
5833 /* 15613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 396*/ GIMT_Encode4(15644), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1129 //
5834 /* 15620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5835 /* 15624 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
5836 /* 15624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64),
5837 /* 15627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5838 /* 15629 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5839 /* 15631 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5840 /* 15633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5841 /* 15636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5842 /* 15642 */ GIR_RootConstrainSelectedInstOperands,
5843 /* 15643 */ // GIR_Coverage, 1129,
5844 /* 15643 */ GIR_EraseRootFromParent_Done,
5845 /* 15644 */ // Label 396: @15644
5846 /* 15644 */ GIM_Reject,
5847 /* 15645 */ // Label 392: @15645
5848 /* 15645 */ GIM_Reject,
5849 /* 15646 */ // Label 386: @15646
5850 /* 15646 */ GIM_Reject,
5851 /* 15647 */ // Label 329: @15647
5852 /* 15647 */ GIM_Reject,
5853 /* 15648 */ // Label 2: @15648
5854 /* 15648 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 404*/ GIMT_Encode4(17310),
5855 /* 15659 */ /*GILLT_s32*//*Label 397*/ GIMT_Encode4(15707), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
5856 /* 15683 */ /*GILLT_v8s8*//*Label 398*/ GIMT_Encode4(16608),
5857 /* 15687 */ /*GILLT_v16s8*//*Label 399*/ GIMT_Encode4(16654),
5858 /* 15691 */ /*GILLT_v4s16*//*Label 400*/ GIMT_Encode4(16766),
5859 /* 15695 */ /*GILLT_v8s16*//*Label 401*/ GIMT_Encode4(16812),
5860 /* 15699 */ /*GILLT_v2s32*//*Label 402*/ GIMT_Encode4(17038),
5861 /* 15703 */ /*GILLT_v4s32*//*Label 403*/ GIMT_Encode4(17084),
5862 /* 15707 */ // Label 397: @15707
5863 /* 15707 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(16607),
5864 /* 15712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
5865 /* 15715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5866 /* 15718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 406*/ GIMT_Encode4(15805), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 185 //
5867 /* 15725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5868 /* 15729 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5869 /* 15733 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5870 /* 15737 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5871 /* 15741 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5872 /* 15745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5873 /* 15750 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5874 /* 15754 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5875 /* 15758 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5876 /* 15762 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5877 /* 15766 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5878 /* 15770 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5879 /* 15775 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5880 /* 15779 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5881 /* 15781 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5882 /* 15781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
5883 /* 15784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5884 /* 15786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5885 /* 15790 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5886 /* 15794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5887 /* 15797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5888 /* 15803 */ GIR_RootConstrainSelectedInstOperands,
5889 /* 15804 */ // GIR_Coverage, 185,
5890 /* 15804 */ GIR_EraseRootFromParent_Done,
5891 /* 15805 */ // Label 406: @15805
5892 /* 15805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 407*/ GIMT_Encode4(15892), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 514 //
5893 /* 15812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5894 /* 15816 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5895 /* 15820 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5896 /* 15824 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5897 /* 15828 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5898 /* 15832 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5899 /* 15837 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5900 /* 15841 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5901 /* 15845 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5902 /* 15849 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5903 /* 15853 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5904 /* 15857 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5905 /* 15862 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5906 /* 15866 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5907 /* 15868 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5908 /* 15868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
5909 /* 15871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5910 /* 15873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5911 /* 15877 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5912 /* 15881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5913 /* 15884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5914 /* 15890 */ GIR_RootConstrainSelectedInstOperands,
5915 /* 15891 */ // GIR_Coverage, 514,
5916 /* 15891 */ GIR_EraseRootFromParent_Done,
5917 /* 15892 */ // Label 407: @15892
5918 /* 15892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 408*/ GIMT_Encode4(15982), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 184 //
5919 /* 15899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5920 /* 15903 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5921 /* 15907 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5922 /* 15911 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5923 /* 15915 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5924 /* 15919 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5925 /* 15924 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5926 /* 15928 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5927 /* 15932 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
5928 /* 15936 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5929 /* 15940 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5930 /* 15945 */ // MIs[2] Operand 2
5931 /* 15945 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
5932 /* 15956 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5933 /* 15958 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5934 /* 15958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
5935 /* 15961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5936 /* 15963 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5937 /* 15967 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5938 /* 15971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5939 /* 15974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5940 /* 15980 */ GIR_RootConstrainSelectedInstOperands,
5941 /* 15981 */ // GIR_Coverage, 184,
5942 /* 15981 */ GIR_EraseRootFromParent_Done,
5943 /* 15982 */ // Label 408: @15982
5944 /* 15982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 409*/ GIMT_Encode4(16072), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 513 //
5945 /* 15989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5946 /* 15993 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5947 /* 15997 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5948 /* 16001 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5949 /* 16005 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5950 /* 16009 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5951 /* 16014 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5952 /* 16018 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5953 /* 16022 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
5954 /* 16026 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5955 /* 16030 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5956 /* 16035 */ // MIs[2] Operand 2
5957 /* 16035 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
5958 /* 16046 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5959 /* 16048 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5960 /* 16048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
5961 /* 16051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5962 /* 16053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5963 /* 16057 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5964 /* 16061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5965 /* 16064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5966 /* 16070 */ GIR_RootConstrainSelectedInstOperands,
5967 /* 16071 */ // GIR_Coverage, 513,
5968 /* 16071 */ GIR_EraseRootFromParent_Done,
5969 /* 16072 */ // Label 409: @16072
5970 /* 16072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 410*/ GIMT_Encode4(16162), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 183 //
5971 /* 16079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5972 /* 16083 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5973 /* 16087 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
5974 /* 16091 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5975 /* 16095 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5976 /* 16100 */ // MIs[1] Operand 2
5977 /* 16100 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
5978 /* 16111 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5979 /* 16115 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5980 /* 16119 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5981 /* 16123 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5982 /* 16127 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5983 /* 16132 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5984 /* 16136 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5985 /* 16138 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5986 /* 16138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
5987 /* 16141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5988 /* 16143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5989 /* 16147 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5990 /* 16151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5991 /* 16154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5992 /* 16160 */ GIR_RootConstrainSelectedInstOperands,
5993 /* 16161 */ // GIR_Coverage, 183,
5994 /* 16161 */ GIR_EraseRootFromParent_Done,
5995 /* 16162 */ // Label 410: @16162
5996 /* 16162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 411*/ GIMT_Encode4(16252), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 512 //
5997 /* 16169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5998 /* 16173 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5999 /* 16177 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6000 /* 16181 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6001 /* 16185 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6002 /* 16190 */ // MIs[1] Operand 2
6003 /* 16190 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6004 /* 16201 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6005 /* 16205 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6006 /* 16209 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6007 /* 16213 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6008 /* 16217 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6009 /* 16222 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6010 /* 16226 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6011 /* 16228 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6012 /* 16228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
6013 /* 16231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6014 /* 16233 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6015 /* 16237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6016 /* 16241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6017 /* 16244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6018 /* 16250 */ GIR_RootConstrainSelectedInstOperands,
6019 /* 16251 */ // GIR_Coverage, 512,
6020 /* 16251 */ GIR_EraseRootFromParent_Done,
6021 /* 16252 */ // Label 411: @16252
6022 /* 16252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 412*/ GIMT_Encode4(16345), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 182 //
6023 /* 16259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6024 /* 16263 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6025 /* 16267 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6026 /* 16271 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6027 /* 16275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6028 /* 16280 */ // MIs[1] Operand 2
6029 /* 16280 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6030 /* 16291 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6031 /* 16295 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6032 /* 16299 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6033 /* 16303 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6034 /* 16308 */ // MIs[2] Operand 2
6035 /* 16308 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6036 /* 16319 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6037 /* 16321 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6038 /* 16321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
6039 /* 16324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6040 /* 16326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6041 /* 16330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6042 /* 16334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6043 /* 16337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6044 /* 16343 */ GIR_RootConstrainSelectedInstOperands,
6045 /* 16344 */ // GIR_Coverage, 182,
6046 /* 16344 */ GIR_EraseRootFromParent_Done,
6047 /* 16345 */ // Label 412: @16345
6048 /* 16345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 413*/ GIMT_Encode4(16438), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 511 //
6049 /* 16352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6050 /* 16356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6051 /* 16360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6052 /* 16364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6053 /* 16368 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6054 /* 16373 */ // MIs[1] Operand 2
6055 /* 16373 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6056 /* 16384 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6057 /* 16388 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6058 /* 16392 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6059 /* 16396 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6060 /* 16401 */ // MIs[2] Operand 2
6061 /* 16401 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6062 /* 16412 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6063 /* 16414 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6064 /* 16414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
6065 /* 16417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6066 /* 16419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6067 /* 16423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6068 /* 16427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6069 /* 16430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6070 /* 16436 */ GIR_RootConstrainSelectedInstOperands,
6071 /* 16437 */ // GIR_Coverage, 511,
6072 /* 16437 */ GIR_EraseRootFromParent_Done,
6073 /* 16438 */ // Label 413: @16438
6074 /* 16438 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(16522),
6075 /* 16443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6076 /* 16447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6077 /* 16451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6078 /* 16455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 415*/ GIMT_Encode4(16488), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 168 //
6079 /* 16462 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6080 /* 16462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL),
6081 /* 16465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6082 /* 16467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6083 /* 16469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6084 /* 16471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6085 /* 16474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6086 /* 16480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6087 /* 16486 */ GIR_RootConstrainSelectedInstOperands,
6088 /* 16487 */ // GIR_Coverage, 168,
6089 /* 16487 */ GIR_EraseRootFromParent_Done,
6090 /* 16488 */ // Label 415: @16488
6091 /* 16488 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 416*/ GIMT_Encode4(16521), GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), // Rule ID 169 //
6092 /* 16495 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6093 /* 16495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5),
6094 /* 16498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6095 /* 16500 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6096 /* 16502 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6097 /* 16504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6098 /* 16507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6099 /* 16513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6100 /* 16519 */ GIR_RootConstrainSelectedInstOperands,
6101 /* 16520 */ // GIR_Coverage, 169,
6102 /* 16520 */ GIR_EraseRootFromParent_Done,
6103 /* 16521 */ // Label 416: @16521
6104 /* 16521 */ GIM_Reject,
6105 /* 16522 */ // Label 414: @16522
6106 /* 16522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 417*/ GIMT_Encode4(16567), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 322 //
6107 /* 16529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6108 /* 16533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6109 /* 16537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6110 /* 16541 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6111 /* 16541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL),
6112 /* 16544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6113 /* 16546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6114 /* 16552 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6115 /* 16554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6116 /* 16556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6117 /* 16559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6118 /* 16565 */ GIR_RootConstrainSelectedInstOperands,
6119 /* 16566 */ // GIR_Coverage, 322,
6120 /* 16566 */ GIR_EraseRootFromParent_Done,
6121 /* 16567 */ // Label 417: @16567
6122 /* 16567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 418*/ GIMT_Encode4(16606), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 501 //
6123 /* 16574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6124 /* 16578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6125 /* 16582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6126 /* 16586 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6127 /* 16586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL),
6128 /* 16589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6129 /* 16591 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6130 /* 16593 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6131 /* 16595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6132 /* 16598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6133 /* 16604 */ GIR_RootConstrainSelectedInstOperands,
6134 /* 16605 */ // GIR_Coverage, 501,
6135 /* 16605 */ GIR_EraseRootFromParent_Done,
6136 /* 16606 */ // Label 418: @16606
6137 /* 16606 */ GIM_Reject,
6138 /* 16607 */ // Label 405: @16607
6139 /* 16607 */ GIM_Reject,
6140 /* 16608 */ // Label 398: @16608
6141 /* 16608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 419*/ GIMT_Encode4(16653), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 955 //
6142 /* 16615 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
6143 /* 16618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
6144 /* 16621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6145 /* 16625 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6146 /* 16629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6147 /* 16633 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
6148 /* 16633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8),
6149 /* 16636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6150 /* 16638 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6151 /* 16640 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6152 /* 16642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6153 /* 16645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6154 /* 16651 */ GIR_RootConstrainSelectedInstOperands,
6155 /* 16652 */ // GIR_Coverage, 955,
6156 /* 16652 */ GIR_EraseRootFromParent_Done,
6157 /* 16653 */ // Label 419: @16653
6158 /* 16653 */ GIM_Reject,
6159 /* 16654 */ // Label 399: @16654
6160 /* 16654 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(16765),
6161 /* 16659 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
6162 /* 16662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
6163 /* 16665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 421*/ GIMT_Encode4(16704), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 958 //
6164 /* 16672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6165 /* 16676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6166 /* 16680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6167 /* 16684 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
6168 /* 16684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8),
6169 /* 16687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6170 /* 16689 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6171 /* 16691 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6172 /* 16693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6173 /* 16696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6174 /* 16702 */ GIR_RootConstrainSelectedInstOperands,
6175 /* 16703 */ // GIR_Coverage, 958,
6176 /* 16703 */ GIR_EraseRootFromParent_Done,
6177 /* 16704 */ // Label 421: @16704
6178 /* 16704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 422*/ GIMT_Encode4(16764), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3855 //
6179 /* 16711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6180 /* 16715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6181 /* 16719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6182 /* 16723 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6183 /* 16723 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6184 /* 16726 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6185 /* 16730 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6186 /* 16735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8),
6187 /* 16738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6188 /* 16740 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6189 /* 16742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6190 /* 16744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6191 /* 16747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6192 /* 16753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6193 /* 16759 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6194 /* 16762 */ GIR_RootConstrainSelectedInstOperands,
6195 /* 16763 */ // GIR_Coverage, 3855,
6196 /* 16763 */ GIR_EraseRootFromParent_Done,
6197 /* 16764 */ // Label 422: @16764
6198 /* 16764 */ GIM_Reject,
6199 /* 16765 */ // Label 420: @16765
6200 /* 16765 */ GIM_Reject,
6201 /* 16766 */ // Label 400: @16766
6202 /* 16766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 423*/ GIMT_Encode4(16811), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 956 //
6203 /* 16773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
6204 /* 16776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
6205 /* 16779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6206 /* 16783 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6207 /* 16787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6208 /* 16791 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
6209 /* 16791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16),
6210 /* 16794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6211 /* 16796 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6212 /* 16798 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6213 /* 16800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6214 /* 16803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6215 /* 16809 */ GIR_RootConstrainSelectedInstOperands,
6216 /* 16810 */ // GIR_Coverage, 956,
6217 /* 16810 */ GIR_EraseRootFromParent_Done,
6218 /* 16811 */ // Label 423: @16811
6219 /* 16811 */ GIM_Reject,
6220 /* 16812 */ // Label 401: @16812
6221 /* 16812 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(17037),
6222 /* 16817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
6223 /* 16820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6224 /* 16823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 425*/ GIMT_Encode4(16937), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4937 //
6225 /* 16830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6226 /* 16834 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6227 /* 16838 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6228 /* 16842 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6229 /* 16846 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6230 /* 16851 */ // MIs[1] Operand 2
6231 /* 16851 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
6232 /* 16862 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6233 /* 16866 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6234 /* 16870 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
6235 /* 16874 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6236 /* 16879 */ // MIs[2] Operand 2
6237 /* 16879 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
6238 /* 16890 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6239 /* 16892 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)
6240 /* 16892 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6241 /* 16895 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6242 /* 16899 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6243 /* 16904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
6244 /* 16907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6245 /* 16909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6246 /* 16913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6247 /* 16917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6248 /* 16920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6249 /* 16926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6250 /* 16932 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6251 /* 16935 */ GIR_RootConstrainSelectedInstOperands,
6252 /* 16936 */ // GIR_Coverage, 4937,
6253 /* 16936 */ GIR_EraseRootFromParent_Done,
6254 /* 16937 */ // Label 425: @16937
6255 /* 16937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 426*/ GIMT_Encode4(16976), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 959 //
6256 /* 16944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6257 /* 16948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6258 /* 16952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6259 /* 16956 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
6260 /* 16956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16),
6261 /* 16959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6262 /* 16961 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6263 /* 16963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6264 /* 16965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6265 /* 16968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6266 /* 16974 */ GIR_RootConstrainSelectedInstOperands,
6267 /* 16975 */ // GIR_Coverage, 959,
6268 /* 16975 */ GIR_EraseRootFromParent_Done,
6269 /* 16976 */ // Label 426: @16976
6270 /* 16976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 427*/ GIMT_Encode4(17036), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3859 //
6271 /* 16983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6272 /* 16987 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6273 /* 16991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6274 /* 16995 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
6275 /* 16995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6276 /* 16998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6277 /* 17002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6278 /* 17007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16),
6279 /* 17010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6280 /* 17012 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6281 /* 17014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6282 /* 17016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6283 /* 17019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6284 /* 17025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6285 /* 17031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6286 /* 17034 */ GIR_RootConstrainSelectedInstOperands,
6287 /* 17035 */ // GIR_Coverage, 3859,
6288 /* 17035 */ GIR_EraseRootFromParent_Done,
6289 /* 17036 */ // Label 427: @17036
6290 /* 17036 */ GIM_Reject,
6291 /* 17037 */ // Label 424: @17037
6292 /* 17037 */ GIM_Reject,
6293 /* 17038 */ // Label 402: @17038
6294 /* 17038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 428*/ GIMT_Encode4(17083), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 957 //
6295 /* 17045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
6296 /* 17048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
6297 /* 17051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6298 /* 17055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6299 /* 17059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6300 /* 17063 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6301 /* 17063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32),
6302 /* 17066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6303 /* 17068 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6304 /* 17070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6305 /* 17072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6306 /* 17075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6307 /* 17081 */ GIR_RootConstrainSelectedInstOperands,
6308 /* 17082 */ // GIR_Coverage, 957,
6309 /* 17082 */ GIR_EraseRootFromParent_Done,
6310 /* 17083 */ // Label 428: @17083
6311 /* 17083 */ GIM_Reject,
6312 /* 17084 */ // Label 403: @17084
6313 /* 17084 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(17309),
6314 /* 17089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
6315 /* 17092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6316 /* 17095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 430*/ GIMT_Encode4(17209), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4932 //
6317 /* 17102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6318 /* 17106 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6319 /* 17110 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6320 /* 17114 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6321 /* 17118 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6322 /* 17123 */ // MIs[1] Operand 2
6323 /* 17123 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6324 /* 17134 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6325 /* 17138 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6326 /* 17142 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6327 /* 17146 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6328 /* 17151 */ // MIs[2] Operand 2
6329 /* 17151 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6330 /* 17162 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6331 /* 17164 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)
6332 /* 17164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6333 /* 17167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6334 /* 17171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6335 /* 17176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
6336 /* 17179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6337 /* 17181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6338 /* 17185 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6339 /* 17189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6340 /* 17192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6341 /* 17198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6342 /* 17204 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6343 /* 17207 */ GIR_RootConstrainSelectedInstOperands,
6344 /* 17208 */ // GIR_Coverage, 4932,
6345 /* 17208 */ GIR_EraseRootFromParent_Done,
6346 /* 17209 */ // Label 430: @17209
6347 /* 17209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 431*/ GIMT_Encode4(17248), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 960 //
6348 /* 17216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6349 /* 17220 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6350 /* 17224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6351 /* 17228 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6352 /* 17228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32),
6353 /* 17231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6354 /* 17233 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6355 /* 17235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6356 /* 17237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6357 /* 17240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6358 /* 17246 */ GIR_RootConstrainSelectedInstOperands,
6359 /* 17247 */ // GIR_Coverage, 960,
6360 /* 17247 */ GIR_EraseRootFromParent_Done,
6361 /* 17248 */ // Label 431: @17248
6362 /* 17248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 432*/ GIMT_Encode4(17308), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3863 //
6363 /* 17255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6364 /* 17259 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6365 /* 17263 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6366 /* 17267 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
6367 /* 17267 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6368 /* 17270 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6369 /* 17274 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6370 /* 17279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32),
6371 /* 17282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6372 /* 17284 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6373 /* 17286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6374 /* 17288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6375 /* 17291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6376 /* 17297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6377 /* 17303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6378 /* 17306 */ GIR_RootConstrainSelectedInstOperands,
6379 /* 17307 */ // GIR_Coverage, 3863,
6380 /* 17307 */ GIR_EraseRootFromParent_Done,
6381 /* 17308 */ // Label 432: @17308
6382 /* 17308 */ GIM_Reject,
6383 /* 17309 */ // Label 429: @17309
6384 /* 17309 */ GIM_Reject,
6385 /* 17310 */ // Label 404: @17310
6386 /* 17310 */ GIM_Reject,
6387 /* 17311 */ // Label 3: @17311
6388 /* 17311 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(17404),
6389 /* 17316 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6390 /* 17319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6391 /* 17322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6392 /* 17325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 434*/ GIMT_Encode4(17364), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 194 //
6393 /* 17332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6394 /* 17336 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6395 /* 17340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6396 /* 17344 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6397 /* 17344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV),
6398 /* 17347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6399 /* 17349 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6400 /* 17351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6401 /* 17353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6402 /* 17356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6403 /* 17362 */ GIR_RootConstrainSelectedInstOperands,
6404 /* 17363 */ // GIR_Coverage, 194,
6405 /* 17363 */ GIR_EraseRootFromParent_Done,
6406 /* 17364 */ // Label 434: @17364
6407 /* 17364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 435*/ GIMT_Encode4(17403), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 531 //
6408 /* 17371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6409 /* 17375 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6410 /* 17379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6411 /* 17383 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6412 /* 17383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV),
6413 /* 17386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6414 /* 17388 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6415 /* 17390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6416 /* 17392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6417 /* 17395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6418 /* 17401 */ GIR_RootConstrainSelectedInstOperands,
6419 /* 17402 */ // GIR_Coverage, 531,
6420 /* 17402 */ GIR_EraseRootFromParent_Done,
6421 /* 17403 */ // Label 435: @17403
6422 /* 17403 */ GIM_Reject,
6423 /* 17404 */ // Label 433: @17404
6424 /* 17404 */ GIM_Reject,
6425 /* 17405 */ // Label 4: @17405
6426 /* 17405 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(17498),
6427 /* 17410 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6428 /* 17413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6429 /* 17416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6430 /* 17419 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 437*/ GIMT_Encode4(17458), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 195 //
6431 /* 17426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6432 /* 17430 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6433 /* 17434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6434 /* 17438 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6435 /* 17438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV),
6436 /* 17441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6437 /* 17443 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6438 /* 17445 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6439 /* 17447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6440 /* 17450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6441 /* 17456 */ GIR_RootConstrainSelectedInstOperands,
6442 /* 17457 */ // GIR_Coverage, 195,
6443 /* 17457 */ GIR_EraseRootFromParent_Done,
6444 /* 17458 */ // Label 437: @17458
6445 /* 17458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 438*/ GIMT_Encode4(17497), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 532 //
6446 /* 17465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6447 /* 17469 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6448 /* 17473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6449 /* 17477 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6450 /* 17477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV),
6451 /* 17480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6452 /* 17482 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6453 /* 17484 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6454 /* 17486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6455 /* 17489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6456 /* 17495 */ GIR_RootConstrainSelectedInstOperands,
6457 /* 17496 */ // GIR_Coverage, 532,
6458 /* 17496 */ GIR_EraseRootFromParent_Done,
6459 /* 17497 */ // Label 438: @17497
6460 /* 17497 */ GIM_Reject,
6461 /* 17498 */ // Label 436: @17498
6462 /* 17498 */ GIM_Reject,
6463 /* 17499 */ // Label 5: @17499
6464 /* 17499 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 452*/ GIMT_Encode4(20598),
6465 /* 17510 */ /*GILLT_s32*//*Label 439*/ GIMT_Encode4(17562),
6466 /* 17514 */ /*GILLT_s64*//*Label 440*/ GIMT_Encode4(19498),
6467 /* 17518 */ /*GILLT_v2s1*//*Label 441*/ GIMT_Encode4(19544),
6468 /* 17522 */ /*GILLT_v4s1*//*Label 442*/ GIMT_Encode4(19661),
6469 /* 17526 */ /*GILLT_v8s1*//*Label 443*/ GIMT_Encode4(19778),
6470 /* 17530 */ /*GILLT_v16s1*//*Label 444*/ GIMT_Encode4(19895),
6471 /* 17534 */ /*GILLT_v8s8*//*Label 445*/ GIMT_Encode4(20012),
6472 /* 17538 */ /*GILLT_v16s8*//*Label 446*/ GIMT_Encode4(20058),
6473 /* 17542 */ /*GILLT_v4s16*//*Label 447*/ GIMT_Encode4(20170),
6474 /* 17546 */ /*GILLT_v8s16*//*Label 448*/ GIMT_Encode4(20216),
6475 /* 17550 */ /*GILLT_v2s32*//*Label 449*/ GIMT_Encode4(20328),
6476 /* 17554 */ /*GILLT_v4s32*//*Label 450*/ GIMT_Encode4(20374),
6477 /* 17558 */ /*GILLT_v2s64*//*Label 451*/ GIMT_Encode4(20486),
6478 /* 17562 */ // Label 439: @17562
6479 /* 17562 */ GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(19497),
6480 /* 17567 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6481 /* 17570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6482 /* 17573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 454*/ GIMT_Encode4(17645), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2043 //
6483 /* 17580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6484 /* 17584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6485 /* 17588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6486 /* 17592 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6487 /* 17596 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6488 /* 17600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6489 /* 17605 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6490 /* 17609 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6491 /* 17620 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6492 /* 17622 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6493 /* 17622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6494 /* 17625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6495 /* 17627 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6496 /* 17631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6497 /* 17634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6498 /* 17637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6499 /* 17643 */ GIR_RootConstrainSelectedInstOperands,
6500 /* 17644 */ // GIR_Coverage, 2043,
6501 /* 17644 */ GIR_EraseRootFromParent_Done,
6502 /* 17645 */ // Label 454: @17645
6503 /* 17645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 455*/ GIMT_Encode4(17717), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2308 //
6504 /* 17652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6505 /* 17656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6506 /* 17660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6507 /* 17664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6508 /* 17668 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6509 /* 17672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6510 /* 17677 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6511 /* 17681 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6512 /* 17692 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6513 /* 17694 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6514 /* 17694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6515 /* 17697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6516 /* 17699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6517 /* 17703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6518 /* 17706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6519 /* 17709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6520 /* 17715 */ GIR_RootConstrainSelectedInstOperands,
6521 /* 17716 */ // GIR_Coverage, 2308,
6522 /* 17716 */ GIR_EraseRootFromParent_Done,
6523 /* 17717 */ // Label 455: @17717
6524 /* 17717 */ GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(17848),
6525 /* 17722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6526 /* 17726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6527 /* 17730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 457*/ GIMT_Encode4(17769), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2192 //
6528 /* 17737 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6529 /* 17748 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6530 /* 17748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB),
6531 /* 17751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6532 /* 17753 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6533 /* 17755 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6534 /* 17758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6535 /* 17761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6536 /* 17767 */ GIR_RootConstrainSelectedInstOperands,
6537 /* 17768 */ // GIR_Coverage, 2192,
6538 /* 17768 */ GIR_EraseRootFromParent_Done,
6539 /* 17769 */ // Label 457: @17769
6540 /* 17769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 458*/ GIMT_Encode4(17808), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2193 //
6541 /* 17776 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6542 /* 17787 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6543 /* 17787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH),
6544 /* 17790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6545 /* 17792 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6546 /* 17794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6547 /* 17797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6548 /* 17800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6549 /* 17806 */ GIR_RootConstrainSelectedInstOperands,
6550 /* 17807 */ // GIR_Coverage, 2193,
6551 /* 17807 */ GIR_EraseRootFromParent_Done,
6552 /* 17808 */ // Label 458: @17808
6553 /* 17808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 459*/ GIMT_Encode4(17847), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2194 //
6554 /* 17815 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6555 /* 17826 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6556 /* 17826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6557 /* 17829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6558 /* 17831 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6559 /* 17833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6560 /* 17836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6561 /* 17839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6562 /* 17845 */ GIR_RootConstrainSelectedInstOperands,
6563 /* 17846 */ // GIR_Coverage, 2194,
6564 /* 17846 */ GIR_EraseRootFromParent_Done,
6565 /* 17847 */ // Label 459: @17847
6566 /* 17847 */ GIM_Reject,
6567 /* 17848 */ // Label 456: @17848
6568 /* 17848 */ GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(17979),
6569 /* 17853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6570 /* 17857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6571 /* 17861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 461*/ GIMT_Encode4(17900), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2436 //
6572 /* 17868 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6573 /* 17879 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6574 /* 17879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB),
6575 /* 17882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6576 /* 17884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6577 /* 17886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6578 /* 17889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6579 /* 17892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6580 /* 17898 */ GIR_RootConstrainSelectedInstOperands,
6581 /* 17899 */ // GIR_Coverage, 2436,
6582 /* 17899 */ GIR_EraseRootFromParent_Done,
6583 /* 17900 */ // Label 461: @17900
6584 /* 17900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 462*/ GIMT_Encode4(17939), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2437 //
6585 /* 17907 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6586 /* 17918 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6587 /* 17918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH),
6588 /* 17921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6589 /* 17923 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6590 /* 17925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6591 /* 17928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6592 /* 17931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6593 /* 17937 */ GIR_RootConstrainSelectedInstOperands,
6594 /* 17938 */ // GIR_Coverage, 2437,
6595 /* 17938 */ GIR_EraseRootFromParent_Done,
6596 /* 17939 */ // Label 462: @17939
6597 /* 17939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 463*/ GIMT_Encode4(17978), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2438 //
6598 /* 17946 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6599 /* 17957 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6600 /* 17957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6601 /* 17960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6602 /* 17962 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6603 /* 17964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6604 /* 17967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6605 /* 17970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6606 /* 17976 */ GIR_RootConstrainSelectedInstOperands,
6607 /* 17977 */ // GIR_Coverage, 2438,
6608 /* 17977 */ GIR_EraseRootFromParent_Done,
6609 /* 17978 */ // Label 463: @17978
6610 /* 17978 */ GIM_Reject,
6611 /* 17979 */ // Label 460: @17979
6612 /* 17979 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 464*/ GIMT_Encode4(18055), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5974 //
6613 /* 17986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6614 /* 17990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6615 /* 17994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6616 /* 17998 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6617 /* 18002 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6618 /* 18006 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6619 /* 18010 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6620 /* 18014 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6621 /* 18018 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6622 /* 18022 */ // MIs[2] Operand 1
6623 /* 18022 */ // No operand predicates
6624 /* 18022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6625 /* 18026 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6626 /* 18028 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6627 /* 18028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6628 /* 18031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6629 /* 18033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6630 /* 18035 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6631 /* 18038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6632 /* 18041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6633 /* 18047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6634 /* 18053 */ GIR_RootConstrainSelectedInstOperands,
6635 /* 18054 */ // GIR_Coverage, 5974,
6636 /* 18054 */ GIR_EraseRootFromParent_Done,
6637 /* 18055 */ // Label 464: @18055
6638 /* 18055 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 465*/ GIMT_Encode4(18131), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6005 //
6639 /* 18062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6640 /* 18066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6641 /* 18070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6642 /* 18074 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6643 /* 18078 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6644 /* 18082 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6645 /* 18086 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6646 /* 18090 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6647 /* 18094 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6648 /* 18098 */ // MIs[2] Operand 1
6649 /* 18098 */ // No operand predicates
6650 /* 18098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6651 /* 18102 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6652 /* 18104 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6653 /* 18104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6654 /* 18107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6655 /* 18109 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6656 /* 18111 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6657 /* 18114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6658 /* 18117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6659 /* 18123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6660 /* 18129 */ GIR_RootConstrainSelectedInstOperands,
6661 /* 18130 */ // GIR_Coverage, 6005,
6662 /* 18130 */ GIR_EraseRootFromParent_Done,
6663 /* 18131 */ // Label 465: @18131
6664 /* 18131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 466*/ GIMT_Encode4(18207), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5973 //
6665 /* 18138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6666 /* 18142 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6667 /* 18146 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6668 /* 18150 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6669 /* 18154 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6670 /* 18158 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6671 /* 18162 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6672 /* 18166 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6673 /* 18170 */ // MIs[2] Operand 1
6674 /* 18170 */ // No operand predicates
6675 /* 18170 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6676 /* 18174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6677 /* 18178 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6678 /* 18180 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6679 /* 18180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6680 /* 18183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6681 /* 18185 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6682 /* 18187 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6683 /* 18190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6684 /* 18193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6685 /* 18199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6686 /* 18205 */ GIR_RootConstrainSelectedInstOperands,
6687 /* 18206 */ // GIR_Coverage, 5973,
6688 /* 18206 */ GIR_EraseRootFromParent_Done,
6689 /* 18207 */ // Label 466: @18207
6690 /* 18207 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 467*/ GIMT_Encode4(18283), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6004 //
6691 /* 18214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6692 /* 18218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6693 /* 18222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6694 /* 18226 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6695 /* 18230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6696 /* 18234 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6697 /* 18238 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6698 /* 18242 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6699 /* 18246 */ // MIs[2] Operand 1
6700 /* 18246 */ // No operand predicates
6701 /* 18246 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6702 /* 18250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6703 /* 18254 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6704 /* 18256 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6705 /* 18256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6706 /* 18259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6707 /* 18261 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6708 /* 18263 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6709 /* 18266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6710 /* 18269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6711 /* 18275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6712 /* 18281 */ GIR_RootConstrainSelectedInstOperands,
6713 /* 18282 */ // GIR_Coverage, 6004,
6714 /* 18282 */ GIR_EraseRootFromParent_Done,
6715 /* 18283 */ // Label 467: @18283
6716 /* 18283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 468*/ GIMT_Encode4(18359), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5972 //
6717 /* 18290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6718 /* 18294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6719 /* 18298 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6720 /* 18302 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6721 /* 18306 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6722 /* 18310 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6723 /* 18314 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6724 /* 18318 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6725 /* 18322 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6726 /* 18326 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6727 /* 18330 */ // MIs[2] Operand 1
6728 /* 18330 */ // No operand predicates
6729 /* 18330 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6730 /* 18332 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6731 /* 18332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6732 /* 18335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6733 /* 18337 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6734 /* 18339 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6735 /* 18342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6736 /* 18345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6737 /* 18351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6738 /* 18357 */ GIR_RootConstrainSelectedInstOperands,
6739 /* 18358 */ // GIR_Coverage, 5972,
6740 /* 18358 */ GIR_EraseRootFromParent_Done,
6741 /* 18359 */ // Label 468: @18359
6742 /* 18359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 469*/ GIMT_Encode4(18435), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6003 //
6743 /* 18366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6744 /* 18370 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6745 /* 18374 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6746 /* 18378 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6747 /* 18382 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6748 /* 18386 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6749 /* 18390 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6750 /* 18394 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6751 /* 18398 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6752 /* 18402 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6753 /* 18406 */ // MIs[2] Operand 1
6754 /* 18406 */ // No operand predicates
6755 /* 18406 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6756 /* 18408 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6757 /* 18408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6758 /* 18411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6759 /* 18413 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6760 /* 18415 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6761 /* 18418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6762 /* 18421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6763 /* 18427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6764 /* 18433 */ GIR_RootConstrainSelectedInstOperands,
6765 /* 18434 */ // GIR_Coverage, 6003,
6766 /* 18434 */ GIR_EraseRootFromParent_Done,
6767 /* 18435 */ // Label 469: @18435
6768 /* 18435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 470*/ GIMT_Encode4(18511), GIMT_Encode2(GIFBS_IsARM), // Rule ID 158 //
6769 /* 18442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6770 /* 18446 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6771 /* 18450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6772 /* 18454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6773 /* 18458 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6774 /* 18462 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6775 /* 18466 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6776 /* 18470 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6777 /* 18474 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6778 /* 18478 */ // MIs[2] Operand 1
6779 /* 18478 */ // No operand predicates
6780 /* 18478 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6781 /* 18482 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6782 /* 18484 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6783 /* 18484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6784 /* 18487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6785 /* 18489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6786 /* 18491 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6787 /* 18494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6788 /* 18497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6789 /* 18503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6790 /* 18509 */ GIR_RootConstrainSelectedInstOperands,
6791 /* 18510 */ // GIR_Coverage, 158,
6792 /* 18510 */ GIR_EraseRootFromParent_Done,
6793 /* 18511 */ // Label 470: @18511
6794 /* 18511 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 471*/ GIMT_Encode4(18587), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 489 //
6795 /* 18518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6796 /* 18522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6797 /* 18526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6798 /* 18530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6799 /* 18534 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6800 /* 18538 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6801 /* 18542 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6802 /* 18546 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6803 /* 18550 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6804 /* 18554 */ // MIs[2] Operand 1
6805 /* 18554 */ // No operand predicates
6806 /* 18554 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6807 /* 18558 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6808 /* 18560 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6809 /* 18560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6810 /* 18563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6811 /* 18565 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6812 /* 18567 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6813 /* 18570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6814 /* 18573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6815 /* 18579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6816 /* 18585 */ GIR_RootConstrainSelectedInstOperands,
6817 /* 18586 */ // GIR_Coverage, 489,
6818 /* 18586 */ GIR_EraseRootFromParent_Done,
6819 /* 18587 */ // Label 471: @18587
6820 /* 18587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 472*/ GIMT_Encode4(18657), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5975 //
6821 /* 18594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6822 /* 18598 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6823 /* 18602 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6824 /* 18606 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6825 /* 18610 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6826 /* 18614 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6827 /* 18619 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6828 /* 18623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6829 /* 18627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6830 /* 18629 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6831 /* 18629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
6832 /* 18632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6833 /* 18634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6834 /* 18636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6835 /* 18640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6836 /* 18643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6837 /* 18649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6838 /* 18655 */ GIR_RootConstrainSelectedInstOperands,
6839 /* 18656 */ // GIR_Coverage, 5975,
6840 /* 18656 */ GIR_EraseRootFromParent_Done,
6841 /* 18657 */ // Label 472: @18657
6842 /* 18657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 473*/ GIMT_Encode4(18727), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 5995 //
6843 /* 18664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6844 /* 18668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6845 /* 18672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6846 /* 18676 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6847 /* 18680 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6848 /* 18684 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6849 /* 18689 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6850 /* 18693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6851 /* 18697 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6852 /* 18699 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6853 /* 18699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
6854 /* 18702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
6855 /* 18704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6856 /* 18710 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6857 /* 18712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6858 /* 18716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6859 /* 18719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6860 /* 18725 */ GIR_RootConstrainSelectedInstOperands,
6861 /* 18726 */ // GIR_Coverage, 5995,
6862 /* 18726 */ GIR_EraseRootFromParent_Done,
6863 /* 18727 */ // Label 473: @18727
6864 /* 18727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 474*/ GIMT_Encode4(18797), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6006 //
6865 /* 18734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6866 /* 18738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6867 /* 18742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6868 /* 18746 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6869 /* 18750 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6870 /* 18754 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6871 /* 18759 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6872 /* 18763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6873 /* 18767 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6874 /* 18769 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6875 /* 18769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
6876 /* 18772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6877 /* 18774 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6878 /* 18776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6879 /* 18780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6880 /* 18783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6881 /* 18789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6882 /* 18795 */ GIR_RootConstrainSelectedInstOperands,
6883 /* 18796 */ // GIR_Coverage, 6006,
6884 /* 18796 */ GIR_EraseRootFromParent_Done,
6885 /* 18797 */ // Label 474: @18797
6886 /* 18797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 475*/ GIMT_Encode4(18867), GIMT_Encode2(GIFBS_IsARM), // Rule ID 159 //
6887 /* 18804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6888 /* 18808 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6889 /* 18812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6890 /* 18816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6891 /* 18820 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6892 /* 18824 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6893 /* 18828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6894 /* 18833 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6895 /* 18837 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6896 /* 18839 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6897 /* 18839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
6898 /* 18842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6899 /* 18844 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6900 /* 18846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6901 /* 18850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6902 /* 18853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6903 /* 18859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6904 /* 18865 */ GIR_RootConstrainSelectedInstOperands,
6905 /* 18866 */ // GIR_Coverage, 159,
6906 /* 18866 */ GIR_EraseRootFromParent_Done,
6907 /* 18867 */ // Label 475: @18867
6908 /* 18867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 476*/ GIMT_Encode4(18937), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 312 //
6909 /* 18874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6910 /* 18878 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6911 /* 18882 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6912 /* 18886 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6913 /* 18890 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6914 /* 18894 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6915 /* 18898 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6916 /* 18903 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6917 /* 18907 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6918 /* 18909 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6919 /* 18909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
6920 /* 18912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
6921 /* 18914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6922 /* 18920 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6923 /* 18922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6924 /* 18926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6925 /* 18929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6926 /* 18935 */ GIR_RootConstrainSelectedInstOperands,
6927 /* 18936 */ // GIR_Coverage, 312,
6928 /* 18936 */ GIR_EraseRootFromParent_Done,
6929 /* 18937 */ // Label 476: @18937
6930 /* 18937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 477*/ GIMT_Encode4(19007), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 490 //
6931 /* 18944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6932 /* 18948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6933 /* 18952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6934 /* 18956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6935 /* 18960 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6936 /* 18964 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6937 /* 18968 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6938 /* 18973 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6939 /* 18977 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6940 /* 18979 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6941 /* 18979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
6942 /* 18982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6943 /* 18984 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6944 /* 18986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6945 /* 18990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6946 /* 18993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6947 /* 18999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6948 /* 19005 */ GIR_RootConstrainSelectedInstOperands,
6949 /* 19006 */ // GIR_Coverage, 490,
6950 /* 19006 */ GIR_EraseRootFromParent_Done,
6951 /* 19007 */ // Label 477: @19007
6952 /* 19007 */ GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(19093),
6953 /* 19012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6954 /* 19016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6955 /* 19020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 479*/ GIMT_Encode4(19056), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 344 //
6956 /* 19027 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6957 /* 19038 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6958 /* 19038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB),
6959 /* 19041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6960 /* 19043 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6961 /* 19045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6962 /* 19048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6963 /* 19054 */ GIR_RootConstrainSelectedInstOperands,
6964 /* 19055 */ // GIR_Coverage, 344,
6965 /* 19055 */ GIR_EraseRootFromParent_Done,
6966 /* 19056 */ // Label 479: @19056
6967 /* 19056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 480*/ GIMT_Encode4(19092), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 345 //
6968 /* 19063 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6969 /* 19074 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6970 /* 19074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH),
6971 /* 19077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6972 /* 19079 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6973 /* 19081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6974 /* 19084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6975 /* 19090 */ GIR_RootConstrainSelectedInstOperands,
6976 /* 19091 */ // GIR_Coverage, 345,
6977 /* 19091 */ GIR_EraseRootFromParent_Done,
6978 /* 19092 */ // Label 480: @19092
6979 /* 19092 */ GIM_Reject,
6980 /* 19093 */ // Label 478: @19093
6981 /* 19093 */ GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(19205),
6982 /* 19098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6983 /* 19102 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6984 /* 19106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 482*/ GIMT_Encode4(19156), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2082 //
6985 /* 19113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6986 /* 19117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6987 /* 19121 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
6988 /* 19125 */ // MIs[1] Operand 1
6989 /* 19125 */ // No operand predicates
6990 /* 19125 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6991 /* 19127 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm))
6992 /* 19127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6993 /* 19130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6994 /* 19132 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
6995 /* 19134 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
6996 /* 19139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6997 /* 19142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6998 /* 19148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6999 /* 19154 */ GIR_RootConstrainSelectedInstOperands,
7000 /* 19155 */ // GIR_Coverage, 2082,
7001 /* 19155 */ GIR_EraseRootFromParent_Done,
7002 /* 19156 */ // Label 482: @19156
7003 /* 19156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 483*/ GIMT_Encode4(19204), GIMT_Encode2(GIFBS_IsARM), // Rule ID 146 //
7004 /* 19163 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7005 /* 19167 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7006 /* 19171 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
7007 /* 19175 */ // MIs[1] Operand 1
7008 /* 19175 */ // No operand predicates
7009 /* 19175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7010 /* 19177 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7011 /* 19177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri),
7012 /* 19180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7013 /* 19182 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7014 /* 19184 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7015 /* 19187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7016 /* 19190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7017 /* 19196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7018 /* 19202 */ GIR_RootConstrainSelectedInstOperands,
7019 /* 19203 */ // GIR_Coverage, 146,
7020 /* 19203 */ GIR_EraseRootFromParent_Done,
7021 /* 19204 */ // Label 483: @19204
7022 /* 19204 */ GIM_Reject,
7023 /* 19205 */ // Label 481: @19205
7024 /* 19205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 484*/ GIMT_Encode4(19261), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 480 //
7025 /* 19212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7026 /* 19216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7027 /* 19220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7028 /* 19224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7029 /* 19228 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7030 /* 19232 */ // MIs[1] Operand 1
7031 /* 19232 */ // No operand predicates
7032 /* 19232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7033 /* 19234 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7034 /* 19234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri),
7035 /* 19237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7036 /* 19239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7037 /* 19241 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7038 /* 19244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7039 /* 19247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7040 /* 19253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7041 /* 19259 */ GIR_RootConstrainSelectedInstOperands,
7042 /* 19260 */ // GIR_Coverage, 480,
7043 /* 19260 */ GIR_EraseRootFromParent_Done,
7044 /* 19261 */ // Label 484: @19261
7045 /* 19261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 485*/ GIMT_Encode4(19311), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 162 //
7046 /* 19268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7047 /* 19272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7048 /* 19276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7049 /* 19280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7050 /* 19284 */ // MIs[1] Operand 1
7051 /* 19284 */ // No operand predicates
7052 /* 19284 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7053 /* 19288 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7054 /* 19290 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7055 /* 19290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC),
7056 /* 19293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7057 /* 19295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7058 /* 19297 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7059 /* 19300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7060 /* 19303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7061 /* 19309 */ GIR_RootConstrainSelectedInstOperands,
7062 /* 19310 */ // GIR_Coverage, 162,
7063 /* 19310 */ GIR_EraseRootFromParent_Done,
7064 /* 19311 */ // Label 485: @19311
7065 /* 19311 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 486*/ GIMT_Encode4(19361), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 492 //
7066 /* 19318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7067 /* 19322 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7068 /* 19326 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7069 /* 19330 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7070 /* 19334 */ // MIs[1] Operand 1
7071 /* 19334 */ // No operand predicates
7072 /* 19334 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7073 /* 19338 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7074 /* 19340 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7075 /* 19340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC),
7076 /* 19343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7077 /* 19345 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7078 /* 19347 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7079 /* 19350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7080 /* 19353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7081 /* 19359 */ GIR_RootConstrainSelectedInstOperands,
7082 /* 19360 */ // GIR_Coverage, 492,
7083 /* 19360 */ GIR_EraseRootFromParent_Done,
7084 /* 19361 */ // Label 486: @19361
7085 /* 19361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 487*/ GIMT_Encode4(19406), GIMT_Encode2(GIFBS_IsARM), // Rule ID 147 //
7086 /* 19368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7087 /* 19372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7088 /* 19376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7089 /* 19380 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7090 /* 19380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr),
7091 /* 19383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7092 /* 19385 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7093 /* 19387 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7094 /* 19389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7095 /* 19392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7096 /* 19398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7097 /* 19404 */ GIR_RootConstrainSelectedInstOperands,
7098 /* 19405 */ // GIR_Coverage, 147,
7099 /* 19405 */ GIR_EraseRootFromParent_Done,
7100 /* 19406 */ // Label 487: @19406
7101 /* 19406 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 488*/ GIMT_Encode4(19451), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 309 //
7102 /* 19413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7103 /* 19417 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7104 /* 19421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7105 /* 19425 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7106 /* 19425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND),
7107 /* 19428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7108 /* 19430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7109 /* 19436 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7110 /* 19438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7111 /* 19440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7112 /* 19443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7113 /* 19449 */ GIR_RootConstrainSelectedInstOperands,
7114 /* 19450 */ // GIR_Coverage, 309,
7115 /* 19450 */ GIR_EraseRootFromParent_Done,
7116 /* 19451 */ // Label 488: @19451
7117 /* 19451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 489*/ GIMT_Encode4(19496), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 481 //
7118 /* 19458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7119 /* 19462 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7120 /* 19466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7121 /* 19470 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7122 /* 19470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7123 /* 19473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7124 /* 19475 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7125 /* 19477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7126 /* 19479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7127 /* 19482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7128 /* 19488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7129 /* 19494 */ GIR_RootConstrainSelectedInstOperands,
7130 /* 19495 */ // GIR_Coverage, 481,
7131 /* 19495 */ GIR_EraseRootFromParent_Done,
7132 /* 19496 */ // Label 489: @19496
7133 /* 19496 */ GIM_Reject,
7134 /* 19497 */ // Label 453: @19497
7135 /* 19497 */ GIM_Reject,
7136 /* 19498 */ // Label 440: @19498
7137 /* 19498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 490*/ GIMT_Encode4(19543), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2915 //
7138 /* 19505 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
7139 /* 19508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
7140 /* 19511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7141 /* 19515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7142 /* 19519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7143 /* 19523 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
7144 /* 19523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7145 /* 19526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7146 /* 19528 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7147 /* 19530 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7148 /* 19532 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7149 /* 19535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7150 /* 19541 */ GIR_RootConstrainSelectedInstOperands,
7151 /* 19542 */ // GIR_Coverage, 2915,
7152 /* 19542 */ GIR_EraseRootFromParent_Done,
7153 /* 19543 */ // Label 490: @19543
7154 /* 19543 */ GIM_Reject,
7155 /* 19544 */ // Label 441: @19544
7156 /* 19544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 491*/ GIMT_Encode4(19660), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2014 //
7157 /* 19551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
7158 /* 19554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
7159 /* 19557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7160 /* 19561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7161 /* 19565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7162 /* 19569 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7163 /* 19569 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7164 /* 19572 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7165 /* 19576 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7166 /* 19581 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7167 /* 19585 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7168 /* 19590 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7169 /* 19593 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7170 /* 19597 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7171 /* 19602 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7172 /* 19606 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7173 /* 19611 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7174 /* 19614 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7175 /* 19618 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7176 /* 19623 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7177 /* 19626 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7178 /* 19629 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7179 /* 19632 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7180 /* 19638 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7181 /* 19644 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7182 /* 19646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7183 /* 19649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7184 /* 19651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7185 /* 19654 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7186 /* 19659 */ // GIR_Coverage, 2014,
7187 /* 19659 */ GIR_EraseRootFromParent_Done,
7188 /* 19660 */ // Label 491: @19660
7189 /* 19660 */ GIM_Reject,
7190 /* 19661 */ // Label 442: @19661
7191 /* 19661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 492*/ GIMT_Encode4(19777), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2015 //
7192 /* 19668 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
7193 /* 19671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
7194 /* 19674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7195 /* 19678 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7196 /* 19682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7197 /* 19686 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7198 /* 19686 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7199 /* 19689 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7200 /* 19693 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7201 /* 19698 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7202 /* 19702 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7203 /* 19707 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7204 /* 19710 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7205 /* 19714 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7206 /* 19719 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7207 /* 19723 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7208 /* 19728 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7209 /* 19731 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7210 /* 19735 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7211 /* 19740 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7212 /* 19743 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7213 /* 19746 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7214 /* 19749 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7215 /* 19755 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7216 /* 19761 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7217 /* 19763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7218 /* 19766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7219 /* 19768 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7220 /* 19771 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7221 /* 19776 */ // GIR_Coverage, 2015,
7222 /* 19776 */ GIR_EraseRootFromParent_Done,
7223 /* 19777 */ // Label 492: @19777
7224 /* 19777 */ GIM_Reject,
7225 /* 19778 */ // Label 443: @19778
7226 /* 19778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 493*/ GIMT_Encode4(19894), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2016 //
7227 /* 19785 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
7228 /* 19788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
7229 /* 19791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7230 /* 19795 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7231 /* 19799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7232 /* 19803 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7233 /* 19803 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7234 /* 19806 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7235 /* 19810 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7236 /* 19815 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7237 /* 19819 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7238 /* 19824 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7239 /* 19827 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7240 /* 19831 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7241 /* 19836 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7242 /* 19840 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7243 /* 19845 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7244 /* 19848 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7245 /* 19852 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7246 /* 19857 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7247 /* 19860 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7248 /* 19863 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7249 /* 19866 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7250 /* 19872 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7251 /* 19878 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7252 /* 19880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7253 /* 19883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7254 /* 19885 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7255 /* 19888 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7256 /* 19893 */ // GIR_Coverage, 2016,
7257 /* 19893 */ GIR_EraseRootFromParent_Done,
7258 /* 19894 */ // Label 493: @19894
7259 /* 19894 */ GIM_Reject,
7260 /* 19895 */ // Label 444: @19895
7261 /* 19895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 494*/ GIMT_Encode4(20011), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2017 //
7262 /* 19902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
7263 /* 19905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
7264 /* 19908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7265 /* 19912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7266 /* 19916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7267 /* 19920 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7268 /* 19920 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7269 /* 19923 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7270 /* 19927 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7271 /* 19932 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7272 /* 19936 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7273 /* 19941 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7274 /* 19944 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7275 /* 19948 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7276 /* 19953 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7277 /* 19957 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7278 /* 19962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7279 /* 19965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7280 /* 19969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7281 /* 19974 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7282 /* 19977 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7283 /* 19980 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7284 /* 19983 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7285 /* 19989 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7286 /* 19995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7287 /* 19997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7288 /* 20000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7289 /* 20002 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7290 /* 20005 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7291 /* 20010 */ // GIR_Coverage, 2017,
7292 /* 20010 */ GIR_EraseRootFromParent_Done,
7293 /* 20011 */ // Label 494: @20011
7294 /* 20011 */ GIM_Reject,
7295 /* 20012 */ // Label 445: @20012
7296 /* 20012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 495*/ GIMT_Encode4(20057), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2913 //
7297 /* 20019 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
7298 /* 20022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
7299 /* 20025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7300 /* 20029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7301 /* 20033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7302 /* 20037 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
7303 /* 20037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7304 /* 20040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7305 /* 20042 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7306 /* 20044 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7307 /* 20046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7308 /* 20049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7309 /* 20055 */ GIR_RootConstrainSelectedInstOperands,
7310 /* 20056 */ // GIR_Coverage, 2913,
7311 /* 20056 */ GIR_EraseRootFromParent_Done,
7312 /* 20057 */ // Label 495: @20057
7313 /* 20057 */ GIM_Reject,
7314 /* 20058 */ // Label 446: @20058
7315 /* 20058 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(20169),
7316 /* 20063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
7317 /* 20066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7318 /* 20069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 497*/ GIMT_Encode4(20108), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2916 //
7319 /* 20076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7320 /* 20080 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7321 /* 20084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7322 /* 20088 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
7323 /* 20088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7324 /* 20091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7325 /* 20093 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7326 /* 20095 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7327 /* 20097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7328 /* 20100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7329 /* 20106 */ GIR_RootConstrainSelectedInstOperands,
7330 /* 20107 */ // GIR_Coverage, 2916,
7331 /* 20107 */ GIR_EraseRootFromParent_Done,
7332 /* 20108 */ // Label 497: @20108
7333 /* 20108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 498*/ GIMT_Encode4(20168), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3755 //
7334 /* 20115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7335 /* 20119 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7336 /* 20123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7337 /* 20127 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
7338 /* 20127 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7339 /* 20130 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7340 /* 20134 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7341 /* 20139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7342 /* 20142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7343 /* 20144 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7344 /* 20146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7345 /* 20148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7346 /* 20151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7347 /* 20157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7348 /* 20163 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7349 /* 20166 */ GIR_RootConstrainSelectedInstOperands,
7350 /* 20167 */ // GIR_Coverage, 3755,
7351 /* 20167 */ GIR_EraseRootFromParent_Done,
7352 /* 20168 */ // Label 498: @20168
7353 /* 20168 */ GIM_Reject,
7354 /* 20169 */ // Label 496: @20169
7355 /* 20169 */ GIM_Reject,
7356 /* 20170 */ // Label 447: @20170
7357 /* 20170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 499*/ GIMT_Encode4(20215), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2914 //
7358 /* 20177 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
7359 /* 20180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
7360 /* 20183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7361 /* 20187 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7362 /* 20191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7363 /* 20195 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
7364 /* 20195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7365 /* 20198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7366 /* 20200 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7367 /* 20202 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7368 /* 20204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7369 /* 20207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7370 /* 20213 */ GIR_RootConstrainSelectedInstOperands,
7371 /* 20214 */ // GIR_Coverage, 2914,
7372 /* 20214 */ GIR_EraseRootFromParent_Done,
7373 /* 20215 */ // Label 499: @20215
7374 /* 20215 */ GIM_Reject,
7375 /* 20216 */ // Label 448: @20216
7376 /* 20216 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(20327),
7377 /* 20221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
7378 /* 20224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7379 /* 20227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 501*/ GIMT_Encode4(20266), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2917 //
7380 /* 20234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7381 /* 20238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7382 /* 20242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7383 /* 20246 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
7384 /* 20246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7385 /* 20249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7386 /* 20251 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7387 /* 20253 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7388 /* 20255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7389 /* 20258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7390 /* 20264 */ GIR_RootConstrainSelectedInstOperands,
7391 /* 20265 */ // GIR_Coverage, 2917,
7392 /* 20265 */ GIR_EraseRootFromParent_Done,
7393 /* 20266 */ // Label 501: @20266
7394 /* 20266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 502*/ GIMT_Encode4(20326), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3759 //
7395 /* 20273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7396 /* 20277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7397 /* 20281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7398 /* 20285 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
7399 /* 20285 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7400 /* 20288 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7401 /* 20292 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7402 /* 20297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7403 /* 20300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7404 /* 20302 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7405 /* 20304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7406 /* 20306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7407 /* 20309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7408 /* 20315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7409 /* 20321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7410 /* 20324 */ GIR_RootConstrainSelectedInstOperands,
7411 /* 20325 */ // GIR_Coverage, 3759,
7412 /* 20325 */ GIR_EraseRootFromParent_Done,
7413 /* 20326 */ // Label 502: @20326
7414 /* 20326 */ GIM_Reject,
7415 /* 20327 */ // Label 500: @20327
7416 /* 20327 */ GIM_Reject,
7417 /* 20328 */ // Label 449: @20328
7418 /* 20328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 503*/ GIMT_Encode4(20373), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1295 //
7419 /* 20335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
7420 /* 20338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
7421 /* 20341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7422 /* 20345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7423 /* 20349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7424 /* 20353 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
7425 /* 20353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7426 /* 20356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7427 /* 20358 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7428 /* 20360 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7429 /* 20362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7430 /* 20365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7431 /* 20371 */ GIR_RootConstrainSelectedInstOperands,
7432 /* 20372 */ // GIR_Coverage, 1295,
7433 /* 20372 */ GIR_EraseRootFromParent_Done,
7434 /* 20373 */ // Label 503: @20373
7435 /* 20373 */ GIM_Reject,
7436 /* 20374 */ // Label 450: @20374
7437 /* 20374 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(20485),
7438 /* 20379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
7439 /* 20382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7440 /* 20385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 505*/ GIMT_Encode4(20424), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1296 //
7441 /* 20392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7442 /* 20396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7443 /* 20400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7444 /* 20404 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
7445 /* 20404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7446 /* 20407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7447 /* 20409 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7448 /* 20411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7449 /* 20413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7450 /* 20416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7451 /* 20422 */ GIR_RootConstrainSelectedInstOperands,
7452 /* 20423 */ // GIR_Coverage, 1296,
7453 /* 20423 */ GIR_EraseRootFromParent_Done,
7454 /* 20424 */ // Label 505: @20424
7455 /* 20424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 506*/ GIMT_Encode4(20484), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3763 //
7456 /* 20431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7457 /* 20435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7458 /* 20439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7459 /* 20443 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
7460 /* 20443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7461 /* 20446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7462 /* 20450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7463 /* 20455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7464 /* 20458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7465 /* 20460 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7466 /* 20462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7467 /* 20464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7468 /* 20467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7469 /* 20473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7470 /* 20479 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7471 /* 20482 */ GIR_RootConstrainSelectedInstOperands,
7472 /* 20483 */ // GIR_Coverage, 3763,
7473 /* 20483 */ GIR_EraseRootFromParent_Done,
7474 /* 20484 */ // Label 506: @20484
7475 /* 20484 */ GIM_Reject,
7476 /* 20485 */ // Label 504: @20485
7477 /* 20485 */ GIM_Reject,
7478 /* 20486 */ // Label 451: @20486
7479 /* 20486 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(20597),
7480 /* 20491 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
7481 /* 20494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7482 /* 20497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 508*/ GIMT_Encode4(20536), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2918 //
7483 /* 20504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7484 /* 20508 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7485 /* 20512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7486 /* 20516 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
7487 /* 20516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7488 /* 20519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7489 /* 20521 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7490 /* 20523 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7491 /* 20525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7492 /* 20528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7493 /* 20534 */ GIR_RootConstrainSelectedInstOperands,
7494 /* 20535 */ // GIR_Coverage, 2918,
7495 /* 20535 */ GIR_EraseRootFromParent_Done,
7496 /* 20536 */ // Label 508: @20536
7497 /* 20536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 509*/ GIMT_Encode4(20596), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3767 //
7498 /* 20543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7499 /* 20547 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7500 /* 20551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7501 /* 20555 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
7502 /* 20555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7503 /* 20558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7504 /* 20562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7505 /* 20567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7506 /* 20570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7507 /* 20572 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7508 /* 20574 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7509 /* 20576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7510 /* 20579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7511 /* 20585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7512 /* 20591 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7513 /* 20594 */ GIR_RootConstrainSelectedInstOperands,
7514 /* 20595 */ // GIR_Coverage, 3767,
7515 /* 20595 */ GIR_EraseRootFromParent_Done,
7516 /* 20596 */ // Label 509: @20596
7517 /* 20596 */ GIM_Reject,
7518 /* 20597 */ // Label 507: @20597
7519 /* 20597 */ GIM_Reject,
7520 /* 20598 */ // Label 452: @20598
7521 /* 20598 */ GIM_Reject,
7522 /* 20599 */ // Label 6: @20599
7523 /* 20599 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 523*/ GIMT_Encode4(26324),
7524 /* 20610 */ /*GILLT_s32*//*Label 510*/ GIMT_Encode4(20662),
7525 /* 20614 */ /*GILLT_s64*//*Label 511*/ GIMT_Encode4(25224),
7526 /* 20618 */ /*GILLT_v2s1*//*Label 512*/ GIMT_Encode4(25270),
7527 /* 20622 */ /*GILLT_v4s1*//*Label 513*/ GIMT_Encode4(25387),
7528 /* 20626 */ /*GILLT_v8s1*//*Label 514*/ GIMT_Encode4(25504),
7529 /* 20630 */ /*GILLT_v16s1*//*Label 515*/ GIMT_Encode4(25621),
7530 /* 20634 */ /*GILLT_v8s8*//*Label 516*/ GIMT_Encode4(25738),
7531 /* 20638 */ /*GILLT_v16s8*//*Label 517*/ GIMT_Encode4(25784),
7532 /* 20642 */ /*GILLT_v4s16*//*Label 518*/ GIMT_Encode4(25896),
7533 /* 20646 */ /*GILLT_v8s16*//*Label 519*/ GIMT_Encode4(25942),
7534 /* 20650 */ /*GILLT_v2s32*//*Label 520*/ GIMT_Encode4(26054),
7535 /* 20654 */ /*GILLT_v4s32*//*Label 521*/ GIMT_Encode4(26100),
7536 /* 20658 */ /*GILLT_v2s64*//*Label 522*/ GIMT_Encode4(26212),
7537 /* 20662 */ // Label 510: @20662
7538 /* 20662 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(25223),
7539 /* 20667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
7540 /* 20670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7541 /* 20673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 525*/ GIMT_Encode4(20799), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6255 //
7542 /* 20680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7543 /* 20684 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7544 /* 20688 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7545 /* 20692 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7546 /* 20696 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7547 /* 20700 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7548 /* 20704 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7549 /* 20708 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7550 /* 20712 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7551 /* 20716 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7552 /* 20721 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7553 /* 20725 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7554 /* 20736 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7555 /* 20740 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7556 /* 20744 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7557 /* 20748 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7558 /* 20752 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7559 /* 20756 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7560 /* 20760 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7561 /* 20764 */ // MIs[4] Rm
7562 /* 20764 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7563 /* 20769 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7564 /* 20773 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7565 /* 20777 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7566 /* 20779 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7567 /* 20779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7568 /* 20782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7569 /* 20784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7570 /* 20788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7571 /* 20791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7572 /* 20797 */ GIR_RootConstrainSelectedInstOperands,
7573 /* 20798 */ // GIR_Coverage, 6255,
7574 /* 20798 */ GIR_EraseRootFromParent_Done,
7575 /* 20799 */ // Label 525: @20799
7576 /* 20799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 526*/ GIMT_Encode4(20925), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6303 //
7577 /* 20806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7578 /* 20810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7579 /* 20814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7580 /* 20818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7581 /* 20822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7582 /* 20826 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7583 /* 20830 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7584 /* 20834 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7585 /* 20838 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7586 /* 20842 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7587 /* 20847 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7588 /* 20851 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7589 /* 20862 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7590 /* 20866 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7591 /* 20870 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7592 /* 20874 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7593 /* 20878 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7594 /* 20882 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7595 /* 20886 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7596 /* 20890 */ // MIs[4] Rm
7597 /* 20890 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7598 /* 20895 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7599 /* 20899 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7600 /* 20903 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7601 /* 20905 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7602 /* 20905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7603 /* 20908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7604 /* 20910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7605 /* 20914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7606 /* 20917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7607 /* 20923 */ GIR_RootConstrainSelectedInstOperands,
7608 /* 20924 */ // GIR_Coverage, 6303,
7609 /* 20924 */ GIR_EraseRootFromParent_Done,
7610 /* 20925 */ // Label 526: @20925
7611 /* 20925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 527*/ GIMT_Encode4(21051), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2102 //
7612 /* 20932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7613 /* 20936 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7614 /* 20940 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7615 /* 20944 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7616 /* 20948 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7617 /* 20952 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7618 /* 20956 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7619 /* 20960 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7620 /* 20964 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7621 /* 20968 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7622 /* 20973 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7623 /* 20977 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7624 /* 20981 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7625 /* 20985 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7626 /* 20989 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7627 /* 20993 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7628 /* 20997 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7629 /* 21001 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7630 /* 21005 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7631 /* 21009 */ // MIs[4] Rm
7632 /* 21009 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7633 /* 21014 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7634 /* 21018 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7635 /* 21029 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7636 /* 21031 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7637 /* 21031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7638 /* 21034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7639 /* 21036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7640 /* 21040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7641 /* 21043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7642 /* 21049 */ GIR_RootConstrainSelectedInstOperands,
7643 /* 21050 */ // GIR_Coverage, 2102,
7644 /* 21050 */ GIR_EraseRootFromParent_Done,
7645 /* 21051 */ // Label 527: @21051
7646 /* 21051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 528*/ GIMT_Encode4(21177), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2392 //
7647 /* 21058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7648 /* 21062 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7649 /* 21066 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7650 /* 21070 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7651 /* 21074 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7652 /* 21078 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7653 /* 21082 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7654 /* 21086 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7655 /* 21090 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7656 /* 21094 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7657 /* 21099 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7658 /* 21103 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7659 /* 21107 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7660 /* 21111 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7661 /* 21115 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7662 /* 21119 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7663 /* 21123 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7664 /* 21127 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7665 /* 21131 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7666 /* 21135 */ // MIs[4] Rm
7667 /* 21135 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7668 /* 21140 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7669 /* 21144 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7670 /* 21155 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7671 /* 21157 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7672 /* 21157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7673 /* 21160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7674 /* 21162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7675 /* 21166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7676 /* 21169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7677 /* 21175 */ GIR_RootConstrainSelectedInstOperands,
7678 /* 21176 */ // GIR_Coverage, 2392,
7679 /* 21176 */ GIR_EraseRootFromParent_Done,
7680 /* 21177 */ // Label 528: @21177
7681 /* 21177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 529*/ GIMT_Encode4(21309), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5988 //
7682 /* 21184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7683 /* 21188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7684 /* 21192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7685 /* 21196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7686 /* 21200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7687 /* 21204 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7688 /* 21208 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7689 /* 21212 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7690 /* 21216 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7691 /* 21220 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7692 /* 21225 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7693 /* 21229 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7694 /* 21233 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7695 /* 21237 */ // MIs[3] Operand 1
7696 /* 21237 */ // No operand predicates
7697 /* 21237 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7698 /* 21248 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7699 /* 21252 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7700 /* 21256 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7701 /* 21260 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7702 /* 21264 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7703 /* 21269 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7704 /* 21280 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7705 /* 21282 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7706 /* 21282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7707 /* 21285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7708 /* 21287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7709 /* 21291 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7710 /* 21295 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7711 /* 21298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7712 /* 21301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7713 /* 21307 */ GIR_RootConstrainSelectedInstOperands,
7714 /* 21308 */ // GIR_Coverage, 5988,
7715 /* 21308 */ GIR_EraseRootFromParent_Done,
7716 /* 21309 */ // Label 529: @21309
7717 /* 21309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 530*/ GIMT_Encode4(21441), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6023 //
7718 /* 21316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7719 /* 21320 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7720 /* 21324 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7721 /* 21328 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7722 /* 21332 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7723 /* 21336 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7724 /* 21340 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7725 /* 21344 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7726 /* 21348 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7727 /* 21352 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7728 /* 21357 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7729 /* 21361 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7730 /* 21365 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7731 /* 21369 */ // MIs[3] Operand 1
7732 /* 21369 */ // No operand predicates
7733 /* 21369 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7734 /* 21380 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7735 /* 21384 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7736 /* 21388 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7737 /* 21392 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7738 /* 21396 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7739 /* 21401 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7740 /* 21412 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7741 /* 21414 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7742 /* 21414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7743 /* 21417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7744 /* 21419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7745 /* 21423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7746 /* 21427 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7747 /* 21430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7748 /* 21433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7749 /* 21439 */ GIR_RootConstrainSelectedInstOperands,
7750 /* 21440 */ // GIR_Coverage, 6023,
7751 /* 21440 */ GIR_EraseRootFromParent_Done,
7752 /* 21441 */ // Label 530: @21441
7753 /* 21441 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 531*/ GIMT_Encode4(21573), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6260 //
7754 /* 21448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7755 /* 21452 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7756 /* 21456 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7757 /* 21460 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7758 /* 21464 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7759 /* 21468 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7760 /* 21472 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7761 /* 21476 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7762 /* 21480 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7763 /* 21484 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7764 /* 21489 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7765 /* 21493 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7766 /* 21497 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7767 /* 21501 */ // MIs[3] Operand 1
7768 /* 21501 */ // No operand predicates
7769 /* 21501 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7770 /* 21512 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7771 /* 21516 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7772 /* 21520 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7773 /* 21524 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7774 /* 21528 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7775 /* 21533 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7776 /* 21544 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7777 /* 21546 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7778 /* 21546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7779 /* 21549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7780 /* 21551 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
7781 /* 21555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7782 /* 21559 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7783 /* 21562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7784 /* 21565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7785 /* 21571 */ GIR_RootConstrainSelectedInstOperands,
7786 /* 21572 */ // GIR_Coverage, 6260,
7787 /* 21572 */ GIR_EraseRootFromParent_Done,
7788 /* 21573 */ // Label 531: @21573
7789 /* 21573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 532*/ GIMT_Encode4(21705), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6308 //
7790 /* 21580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7791 /* 21584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7792 /* 21588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7793 /* 21592 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7794 /* 21596 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7795 /* 21600 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7796 /* 21604 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7797 /* 21608 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7798 /* 21612 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7799 /* 21616 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7800 /* 21621 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7801 /* 21625 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7802 /* 21629 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7803 /* 21633 */ // MIs[3] Operand 1
7804 /* 21633 */ // No operand predicates
7805 /* 21633 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7806 /* 21644 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7807 /* 21648 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7808 /* 21652 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7809 /* 21656 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7810 /* 21660 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7811 /* 21665 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7812 /* 21676 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7813 /* 21678 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7814 /* 21678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7815 /* 21681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7816 /* 21683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
7817 /* 21687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7818 /* 21691 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7819 /* 21694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7820 /* 21697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7821 /* 21703 */ GIR_RootConstrainSelectedInstOperands,
7822 /* 21704 */ // GIR_Coverage, 6308,
7823 /* 21704 */ GIR_EraseRootFromParent_Done,
7824 /* 21705 */ // Label 532: @21705
7825 /* 21705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 533*/ GIMT_Encode4(21837), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5987 //
7826 /* 21712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7827 /* 21716 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7828 /* 21720 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7829 /* 21724 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7830 /* 21728 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7831 /* 21732 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7832 /* 21736 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7833 /* 21740 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7834 /* 21744 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7835 /* 21748 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7836 /* 21753 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7837 /* 21757 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7838 /* 21761 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
7839 /* 21765 */ // MIs[3] Operand 1
7840 /* 21765 */ // No operand predicates
7841 /* 21765 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7842 /* 21776 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7843 /* 21780 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7844 /* 21784 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7845 /* 21788 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7846 /* 21792 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7847 /* 21797 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
7848 /* 21808 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7849 /* 21810 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7850 /* 21810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
7851 /* 21813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7852 /* 21815 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7853 /* 21819 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7854 /* 21823 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7855 /* 21826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7856 /* 21829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7857 /* 21835 */ GIR_RootConstrainSelectedInstOperands,
7858 /* 21836 */ // GIR_Coverage, 5987,
7859 /* 21836 */ GIR_EraseRootFromParent_Done,
7860 /* 21837 */ // Label 533: @21837
7861 /* 21837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 534*/ GIMT_Encode4(21969), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6022 //
7862 /* 21844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7863 /* 21848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7864 /* 21852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7865 /* 21856 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7866 /* 21860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7867 /* 21864 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7868 /* 21868 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7869 /* 21872 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7870 /* 21876 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7871 /* 21880 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7872 /* 21885 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7873 /* 21889 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7874 /* 21893 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
7875 /* 21897 */ // MIs[3] Operand 1
7876 /* 21897 */ // No operand predicates
7877 /* 21897 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7878 /* 21908 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7879 /* 21912 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7880 /* 21916 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7881 /* 21920 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7882 /* 21924 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7883 /* 21929 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
7884 /* 21940 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7885 /* 21942 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7886 /* 21942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7887 /* 21945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7888 /* 21947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7889 /* 21951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7890 /* 21955 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7891 /* 21958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7892 /* 21961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7893 /* 21967 */ GIR_RootConstrainSelectedInstOperands,
7894 /* 21968 */ // GIR_Coverage, 6022,
7895 /* 21968 */ GIR_EraseRootFromParent_Done,
7896 /* 21969 */ // Label 534: @21969
7897 /* 21969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 535*/ GIMT_Encode4(22101), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 202 //
7898 /* 21976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7899 /* 21980 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7900 /* 21984 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7901 /* 21988 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7902 /* 21992 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7903 /* 21996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7904 /* 22001 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7905 /* 22012 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7906 /* 22016 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7907 /* 22020 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7908 /* 22024 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7909 /* 22028 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7910 /* 22032 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7911 /* 22036 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7912 /* 22040 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7913 /* 22044 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7914 /* 22049 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7915 /* 22053 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7916 /* 22057 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7917 /* 22061 */ // MIs[4] Operand 1
7918 /* 22061 */ // No operand predicates
7919 /* 22061 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7920 /* 22072 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7921 /* 22074 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7922 /* 22074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7923 /* 22077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7924 /* 22079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7925 /* 22083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7926 /* 22087 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7927 /* 22090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7928 /* 22093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7929 /* 22099 */ GIR_RootConstrainSelectedInstOperands,
7930 /* 22100 */ // GIR_Coverage, 202,
7931 /* 22100 */ GIR_EraseRootFromParent_Done,
7932 /* 22101 */ // Label 535: @22101
7933 /* 22101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 536*/ GIMT_Encode4(22233), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 539 //
7934 /* 22108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7935 /* 22112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7936 /* 22116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7937 /* 22120 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7938 /* 22124 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7939 /* 22128 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7940 /* 22133 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7941 /* 22144 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7942 /* 22148 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7943 /* 22152 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7944 /* 22156 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7945 /* 22160 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7946 /* 22164 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7947 /* 22168 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7948 /* 22172 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7949 /* 22176 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7950 /* 22181 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7951 /* 22185 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7952 /* 22189 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7953 /* 22193 */ // MIs[4] Operand 1
7954 /* 22193 */ // No operand predicates
7955 /* 22193 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7956 /* 22204 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7957 /* 22206 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7958 /* 22206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7959 /* 22209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7960 /* 22211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7961 /* 22215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7962 /* 22219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7963 /* 22222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7964 /* 22225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7965 /* 22231 */ GIR_RootConstrainSelectedInstOperands,
7966 /* 22232 */ // GIR_Coverage, 539,
7967 /* 22232 */ GIR_EraseRootFromParent_Done,
7968 /* 22233 */ // Label 536: @22233
7969 /* 22233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 537*/ GIMT_Encode4(22365), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2107 //
7970 /* 22240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7971 /* 22244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7972 /* 22248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7973 /* 22252 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7974 /* 22256 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7975 /* 22260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7976 /* 22265 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7977 /* 22276 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7978 /* 22280 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7979 /* 22284 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7980 /* 22288 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7981 /* 22292 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7982 /* 22296 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
7983 /* 22300 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7984 /* 22304 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7985 /* 22308 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7986 /* 22313 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7987 /* 22317 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7988 /* 22321 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7989 /* 22325 */ // MIs[4] Operand 1
7990 /* 22325 */ // No operand predicates
7991 /* 22325 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7992 /* 22336 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7993 /* 22338 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7994 /* 22338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7995 /* 22341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7996 /* 22343 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7997 /* 22347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
7998 /* 22351 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7999 /* 22354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8000 /* 22357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8001 /* 22363 */ GIR_RootConstrainSelectedInstOperands,
8002 /* 22364 */ // GIR_Coverage, 2107,
8003 /* 22364 */ GIR_EraseRootFromParent_Done,
8004 /* 22365 */ // Label 537: @22365
8005 /* 22365 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 538*/ GIMT_Encode4(22497), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2397 //
8006 /* 22372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8007 /* 22376 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8008 /* 22380 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8009 /* 22384 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8010 /* 22388 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8011 /* 22392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8012 /* 22397 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8013 /* 22408 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8014 /* 22412 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8015 /* 22416 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8016 /* 22420 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8017 /* 22424 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8018 /* 22428 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
8019 /* 22432 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8020 /* 22436 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8021 /* 22440 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8022 /* 22445 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8023 /* 22449 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8024 /* 22453 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8025 /* 22457 */ // MIs[4] Operand 1
8026 /* 22457 */ // No operand predicates
8027 /* 22457 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8028 /* 22468 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8029 /* 22470 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8030 /* 22470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8031 /* 22473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8032 /* 22475 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8033 /* 22479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
8034 /* 22483 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8035 /* 22486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8036 /* 22489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8037 /* 22495 */ GIR_RootConstrainSelectedInstOperands,
8038 /* 22496 */ // GIR_Coverage, 2397,
8039 /* 22496 */ GIR_EraseRootFromParent_Done,
8040 /* 22497 */ // Label 538: @22497
8041 /* 22497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 539*/ GIMT_Encode4(22629), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 201 //
8042 /* 22504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8043 /* 22508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8044 /* 22512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8045 /* 22516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8046 /* 22520 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8047 /* 22524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8048 /* 22529 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8049 /* 22540 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8050 /* 22544 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8051 /* 22548 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8052 /* 22552 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8053 /* 22556 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8054 /* 22560 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8055 /* 22564 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8056 /* 22568 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8057 /* 22572 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8058 /* 22577 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8059 /* 22581 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8060 /* 22585 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8061 /* 22589 */ // MIs[4] Operand 1
8062 /* 22589 */ // No operand predicates
8063 /* 22589 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8064 /* 22600 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8065 /* 22602 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8066 /* 22602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8067 /* 22605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8068 /* 22607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8069 /* 22611 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8070 /* 22615 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8071 /* 22618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8072 /* 22621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8073 /* 22627 */ GIR_RootConstrainSelectedInstOperands,
8074 /* 22628 */ // GIR_Coverage, 201,
8075 /* 22628 */ GIR_EraseRootFromParent_Done,
8076 /* 22629 */ // Label 539: @22629
8077 /* 22629 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 540*/ GIMT_Encode4(22761), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 538 //
8078 /* 22636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8079 /* 22640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8080 /* 22644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8081 /* 22648 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8082 /* 22652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8083 /* 22656 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8084 /* 22661 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8085 /* 22672 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8086 /* 22676 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8087 /* 22680 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8088 /* 22684 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8089 /* 22688 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8090 /* 22692 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8091 /* 22696 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8092 /* 22700 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8093 /* 22704 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8094 /* 22709 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8095 /* 22713 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8096 /* 22717 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8097 /* 22721 */ // MIs[4] Operand 1
8098 /* 22721 */ // No operand predicates
8099 /* 22721 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8100 /* 22732 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8101 /* 22734 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8102 /* 22734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8103 /* 22737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8104 /* 22739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8105 /* 22743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8106 /* 22747 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8107 /* 22750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8108 /* 22753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8109 /* 22759 */ GIR_RootConstrainSelectedInstOperands,
8110 /* 22760 */ // GIR_Coverage, 538,
8111 /* 22760 */ GIR_EraseRootFromParent_Done,
8112 /* 22761 */ // Label 540: @22761
8113 /* 22761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 541*/ GIMT_Encode4(22865), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2103 //
8114 /* 22768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8115 /* 22772 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8116 /* 22776 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8117 /* 22780 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8118 /* 22784 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8119 /* 22788 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8120 /* 22793 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8121 /* 22804 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8122 /* 22808 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8123 /* 22812 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8124 /* 22816 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8125 /* 22820 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8126 /* 22825 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8127 /* 22836 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8128 /* 22838 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8129 /* 22838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8130 /* 22841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8131 /* 22843 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8132 /* 22847 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8133 /* 22851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8134 /* 22854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8135 /* 22857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8136 /* 22863 */ GIR_RootConstrainSelectedInstOperands,
8137 /* 22864 */ // GIR_Coverage, 2103,
8138 /* 22864 */ GIR_EraseRootFromParent_Done,
8139 /* 22865 */ // Label 541: @22865
8140 /* 22865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 542*/ GIMT_Encode4(22969), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2393 //
8141 /* 22872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8142 /* 22876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8143 /* 22880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8144 /* 22884 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8145 /* 22888 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8146 /* 22892 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8147 /* 22897 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8148 /* 22908 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8149 /* 22912 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8150 /* 22916 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8151 /* 22920 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8152 /* 22924 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8153 /* 22929 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8154 /* 22940 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8155 /* 22942 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8156 /* 22942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8157 /* 22945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8158 /* 22947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8159 /* 22951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8160 /* 22955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8161 /* 22958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8162 /* 22961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8163 /* 22967 */ GIR_RootConstrainSelectedInstOperands,
8164 /* 22968 */ // GIR_Coverage, 2393,
8165 /* 22968 */ GIR_EraseRootFromParent_Done,
8166 /* 22969 */ // Label 542: @22969
8167 /* 22969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 543*/ GIMT_Encode4(23073), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6256 //
8168 /* 22976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8169 /* 22980 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8170 /* 22984 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8171 /* 22988 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8172 /* 22992 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8173 /* 22996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8174 /* 23001 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8175 /* 23012 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8176 /* 23016 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8177 /* 23020 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8178 /* 23024 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8179 /* 23028 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8180 /* 23033 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8181 /* 23044 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8182 /* 23046 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8183 /* 23046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8184 /* 23049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8185 /* 23051 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8186 /* 23055 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8187 /* 23059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8188 /* 23062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8189 /* 23065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8190 /* 23071 */ GIR_RootConstrainSelectedInstOperands,
8191 /* 23072 */ // GIR_Coverage, 6256,
8192 /* 23072 */ GIR_EraseRootFromParent_Done,
8193 /* 23073 */ // Label 543: @23073
8194 /* 23073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 544*/ GIMT_Encode4(23177), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6304 //
8195 /* 23080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8196 /* 23084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8197 /* 23088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8198 /* 23092 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8199 /* 23096 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8200 /* 23100 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8201 /* 23105 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8202 /* 23116 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8203 /* 23120 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8204 /* 23124 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8205 /* 23128 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8206 /* 23132 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8207 /* 23137 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8208 /* 23148 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8209 /* 23150 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8210 /* 23150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8211 /* 23153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8212 /* 23155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
8213 /* 23159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8214 /* 23163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8215 /* 23166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8216 /* 23169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8217 /* 23175 */ GIR_RootConstrainSelectedInstOperands,
8218 /* 23176 */ // GIR_Coverage, 6304,
8219 /* 23176 */ GIR_EraseRootFromParent_Done,
8220 /* 23177 */ // Label 544: @23177
8221 /* 23177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 545*/ GIMT_Encode4(23282), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2106 //
8222 /* 23184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8223 /* 23188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8224 /* 23192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8225 /* 23196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8226 /* 23200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8227 /* 23204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8228 /* 23209 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8229 /* 23220 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8230 /* 23224 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8231 /* 23228 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8232 /* 23232 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8233 /* 23236 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8234 /* 23241 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8235 /* 23245 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8236 /* 23249 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8237 /* 23253 */ // MIs[3] Operand 1
8238 /* 23253 */ // No operand predicates
8239 /* 23253 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8240 /* 23255 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8241 /* 23255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8242 /* 23258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8243 /* 23260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8244 /* 23264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8245 /* 23268 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8246 /* 23271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8247 /* 23274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8248 /* 23280 */ GIR_RootConstrainSelectedInstOperands,
8249 /* 23281 */ // GIR_Coverage, 2106,
8250 /* 23281 */ GIR_EraseRootFromParent_Done,
8251 /* 23282 */ // Label 545: @23282
8252 /* 23282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 546*/ GIMT_Encode4(23387), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2396 //
8253 /* 23289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8254 /* 23293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8255 /* 23297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8256 /* 23301 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8257 /* 23305 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8258 /* 23309 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8259 /* 23314 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8260 /* 23325 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8261 /* 23329 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8262 /* 23333 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8263 /* 23337 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8264 /* 23341 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8265 /* 23346 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8266 /* 23350 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8267 /* 23354 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8268 /* 23358 */ // MIs[3] Operand 1
8269 /* 23358 */ // No operand predicates
8270 /* 23358 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8271 /* 23360 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8272 /* 23360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8273 /* 23363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8274 /* 23365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8275 /* 23369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8276 /* 23373 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8277 /* 23376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8278 /* 23379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8279 /* 23385 */ GIR_RootConstrainSelectedInstOperands,
8280 /* 23386 */ // GIR_Coverage, 2396,
8281 /* 23386 */ GIR_EraseRootFromParent_Done,
8282 /* 23387 */ // Label 546: @23387
8283 /* 23387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 547*/ GIMT_Encode4(23492), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2105 //
8284 /* 23394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8285 /* 23398 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8286 /* 23402 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8287 /* 23406 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8288 /* 23410 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8289 /* 23414 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8290 /* 23419 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8291 /* 23430 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8292 /* 23434 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8293 /* 23438 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8294 /* 23442 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8295 /* 23446 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8296 /* 23451 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8297 /* 23455 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8298 /* 23459 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8299 /* 23463 */ // MIs[3] Operand 1
8300 /* 23463 */ // No operand predicates
8301 /* 23463 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8302 /* 23465 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8303 /* 23465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8304 /* 23468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8305 /* 23470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8306 /* 23474 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8307 /* 23478 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8308 /* 23481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8309 /* 23484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8310 /* 23490 */ GIR_RootConstrainSelectedInstOperands,
8311 /* 23491 */ // GIR_Coverage, 2105,
8312 /* 23491 */ GIR_EraseRootFromParent_Done,
8313 /* 23492 */ // Label 547: @23492
8314 /* 23492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 548*/ GIMT_Encode4(23597), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2395 //
8315 /* 23499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8316 /* 23503 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8317 /* 23507 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8318 /* 23511 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8319 /* 23515 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8320 /* 23519 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8321 /* 23524 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8322 /* 23535 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8323 /* 23539 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8324 /* 23543 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8325 /* 23547 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8326 /* 23551 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8327 /* 23556 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8328 /* 23560 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8329 /* 23564 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8330 /* 23568 */ // MIs[3] Operand 1
8331 /* 23568 */ // No operand predicates
8332 /* 23568 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8333 /* 23570 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8334 /* 23570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8335 /* 23573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8336 /* 23575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8337 /* 23579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8338 /* 23583 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8339 /* 23586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8340 /* 23589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8341 /* 23595 */ GIR_RootConstrainSelectedInstOperands,
8342 /* 23596 */ // GIR_Coverage, 2395,
8343 /* 23596 */ GIR_EraseRootFromParent_Done,
8344 /* 23597 */ // Label 548: @23597
8345 /* 23597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 549*/ GIMT_Encode4(23702), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2104 //
8346 /* 23604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8347 /* 23608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8348 /* 23612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8349 /* 23616 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8350 /* 23620 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8351 /* 23624 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8352 /* 23629 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8353 /* 23640 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8354 /* 23644 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8355 /* 23648 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8356 /* 23652 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8357 /* 23656 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8358 /* 23661 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8359 /* 23665 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8360 /* 23669 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8361 /* 23673 */ // MIs[3] Operand 1
8362 /* 23673 */ // No operand predicates
8363 /* 23673 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8364 /* 23675 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8365 /* 23675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8366 /* 23678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8367 /* 23680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8368 /* 23684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8369 /* 23688 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8370 /* 23691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8371 /* 23694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8372 /* 23700 */ GIR_RootConstrainSelectedInstOperands,
8373 /* 23701 */ // GIR_Coverage, 2104,
8374 /* 23701 */ GIR_EraseRootFromParent_Done,
8375 /* 23702 */ // Label 549: @23702
8376 /* 23702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 550*/ GIMT_Encode4(23807), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2394 //
8377 /* 23709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8378 /* 23713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8379 /* 23717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8380 /* 23721 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8381 /* 23725 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8382 /* 23729 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8383 /* 23734 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8384 /* 23745 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8385 /* 23749 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8386 /* 23753 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8387 /* 23757 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8388 /* 23761 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8389 /* 23766 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8390 /* 23770 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8391 /* 23774 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8392 /* 23778 */ // MIs[3] Operand 1
8393 /* 23778 */ // No operand predicates
8394 /* 23778 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8395 /* 23780 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8396 /* 23780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8397 /* 23783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8398 /* 23785 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8399 /* 23789 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8400 /* 23793 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8401 /* 23796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8402 /* 23799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8403 /* 23805 */ GIR_RootConstrainSelectedInstOperands,
8404 /* 23806 */ // GIR_Coverage, 2394,
8405 /* 23806 */ GIR_EraseRootFromParent_Done,
8406 /* 23807 */ // Label 550: @23807
8407 /* 23807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 551*/ GIMT_Encode4(23912), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6259 //
8408 /* 23814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8409 /* 23818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8410 /* 23822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8411 /* 23826 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8412 /* 23830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8413 /* 23834 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8414 /* 23839 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8415 /* 23843 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8416 /* 23847 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8417 /* 23851 */ // MIs[2] Operand 1
8418 /* 23851 */ // No operand predicates
8419 /* 23851 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8420 /* 23855 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8421 /* 23859 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8422 /* 23863 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8423 /* 23867 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8424 /* 23872 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8425 /* 23883 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8426 /* 23885 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8427 /* 23885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8428 /* 23888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8429 /* 23890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8430 /* 23894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8431 /* 23898 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8432 /* 23901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8433 /* 23904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8434 /* 23910 */ GIR_RootConstrainSelectedInstOperands,
8435 /* 23911 */ // GIR_Coverage, 6259,
8436 /* 23911 */ GIR_EraseRootFromParent_Done,
8437 /* 23912 */ // Label 551: @23912
8438 /* 23912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 552*/ GIMT_Encode4(24017), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6307 //
8439 /* 23919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8440 /* 23923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8441 /* 23927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8442 /* 23931 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8443 /* 23935 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8444 /* 23939 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8445 /* 23944 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8446 /* 23948 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8447 /* 23952 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8448 /* 23956 */ // MIs[2] Operand 1
8449 /* 23956 */ // No operand predicates
8450 /* 23956 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8451 /* 23960 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8452 /* 23964 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8453 /* 23968 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8454 /* 23972 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8455 /* 23977 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8456 /* 23988 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8457 /* 23990 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8458 /* 23990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8459 /* 23993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8460 /* 23995 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8461 /* 23999 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8462 /* 24003 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8463 /* 24006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8464 /* 24009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8465 /* 24015 */ GIR_RootConstrainSelectedInstOperands,
8466 /* 24016 */ // GIR_Coverage, 6307,
8467 /* 24016 */ GIR_EraseRootFromParent_Done,
8468 /* 24017 */ // Label 552: @24017
8469 /* 24017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 553*/ GIMT_Encode4(24122), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6258 //
8470 /* 24024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8471 /* 24028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8472 /* 24032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8473 /* 24036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8474 /* 24040 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8475 /* 24044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8476 /* 24049 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8477 /* 24053 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8478 /* 24057 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8479 /* 24061 */ // MIs[2] Operand 1
8480 /* 24061 */ // No operand predicates
8481 /* 24061 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8482 /* 24065 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8483 /* 24069 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8484 /* 24073 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8485 /* 24077 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8486 /* 24082 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8487 /* 24093 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8488 /* 24095 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8489 /* 24095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8490 /* 24098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8491 /* 24100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8492 /* 24104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8493 /* 24108 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8494 /* 24111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8495 /* 24114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8496 /* 24120 */ GIR_RootConstrainSelectedInstOperands,
8497 /* 24121 */ // GIR_Coverage, 6258,
8498 /* 24121 */ GIR_EraseRootFromParent_Done,
8499 /* 24122 */ // Label 553: @24122
8500 /* 24122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 554*/ GIMT_Encode4(24227), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6306 //
8501 /* 24129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8502 /* 24133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8503 /* 24137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8504 /* 24141 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8505 /* 24145 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8506 /* 24149 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8507 /* 24154 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8508 /* 24158 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8509 /* 24162 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8510 /* 24166 */ // MIs[2] Operand 1
8511 /* 24166 */ // No operand predicates
8512 /* 24166 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8513 /* 24170 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8514 /* 24174 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8515 /* 24178 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8516 /* 24182 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8517 /* 24187 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8518 /* 24198 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8519 /* 24200 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8520 /* 24200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8521 /* 24203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8522 /* 24205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8523 /* 24209 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8524 /* 24213 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8525 /* 24216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8526 /* 24219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8527 /* 24225 */ GIR_RootConstrainSelectedInstOperands,
8528 /* 24226 */ // GIR_Coverage, 6306,
8529 /* 24226 */ GIR_EraseRootFromParent_Done,
8530 /* 24227 */ // Label 554: @24227
8531 /* 24227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 555*/ GIMT_Encode4(24332), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6257 //
8532 /* 24234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8533 /* 24238 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8534 /* 24242 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8535 /* 24246 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8536 /* 24250 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8537 /* 24254 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8538 /* 24259 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8539 /* 24263 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8540 /* 24267 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8541 /* 24271 */ // MIs[2] Operand 1
8542 /* 24271 */ // No operand predicates
8543 /* 24271 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8544 /* 24275 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8545 /* 24279 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8546 /* 24283 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8547 /* 24287 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8548 /* 24292 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8549 /* 24303 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8550 /* 24305 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8551 /* 24305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8552 /* 24308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8553 /* 24310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
8554 /* 24314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8555 /* 24318 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8556 /* 24321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8557 /* 24324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8558 /* 24330 */ GIR_RootConstrainSelectedInstOperands,
8559 /* 24331 */ // GIR_Coverage, 6257,
8560 /* 24331 */ GIR_EraseRootFromParent_Done,
8561 /* 24332 */ // Label 555: @24332
8562 /* 24332 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(24867),
8563 /* 24337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8564 /* 24341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 557*/ GIMT_Encode4(24442), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6305 //
8565 /* 24348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8566 /* 24352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8567 /* 24356 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8568 /* 24360 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8569 /* 24364 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8570 /* 24369 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8571 /* 24373 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8572 /* 24377 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8573 /* 24381 */ // MIs[2] Operand 1
8574 /* 24381 */ // No operand predicates
8575 /* 24381 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8576 /* 24385 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8577 /* 24389 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8578 /* 24393 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8579 /* 24397 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8580 /* 24402 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8581 /* 24413 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8582 /* 24415 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8583 /* 24415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8584 /* 24418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8585 /* 24420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8586 /* 24424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8587 /* 24428 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8588 /* 24431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8589 /* 24434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8590 /* 24440 */ GIR_RootConstrainSelectedInstOperands,
8591 /* 24441 */ // GIR_Coverage, 6305,
8592 /* 24441 */ GIR_EraseRootFromParent_Done,
8593 /* 24442 */ // Label 557: @24442
8594 /* 24442 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(24588),
8595 /* 24447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8596 /* 24451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 559*/ GIMT_Encode4(24519), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6010 //
8597 /* 24458 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8598 /* 24462 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8599 /* 24466 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8600 /* 24470 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8601 /* 24474 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8602 /* 24478 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8603 /* 24482 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8604 /* 24486 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8605 /* 24490 */ // MIs[2] Operand 1
8606 /* 24490 */ // No operand predicates
8607 /* 24490 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8608 /* 24492 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8609 /* 24492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8610 /* 24495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8611 /* 24497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8612 /* 24499 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8613 /* 24502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8614 /* 24505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8615 /* 24511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8616 /* 24517 */ GIR_RootConstrainSelectedInstOperands,
8617 /* 24518 */ // GIR_Coverage, 6010,
8618 /* 24518 */ GIR_EraseRootFromParent_Done,
8619 /* 24519 */ // Label 559: @24519
8620 /* 24519 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 560*/ GIMT_Encode4(24587), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6009 //
8621 /* 24526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8622 /* 24530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8623 /* 24534 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8624 /* 24538 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8625 /* 24542 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8626 /* 24546 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8627 /* 24550 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8628 /* 24554 */ // MIs[2] Operand 1
8629 /* 24554 */ // No operand predicates
8630 /* 24554 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8631 /* 24558 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8632 /* 24560 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8633 /* 24560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8634 /* 24563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8635 /* 24565 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8636 /* 24567 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8637 /* 24570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8638 /* 24573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8639 /* 24579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8640 /* 24585 */ GIR_RootConstrainSelectedInstOperands,
8641 /* 24586 */ // GIR_Coverage, 6009,
8642 /* 24586 */ GIR_EraseRootFromParent_Done,
8643 /* 24587 */ // Label 560: @24587
8644 /* 24587 */ GIM_Reject,
8645 /* 24588 */ // Label 558: @24588
8646 /* 24588 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(24734),
8647 /* 24593 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8648 /* 24597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 562*/ GIMT_Encode4(24665), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6008 //
8649 /* 24604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8650 /* 24608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8651 /* 24612 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8652 /* 24616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8653 /* 24620 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8654 /* 24624 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8655 /* 24628 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8656 /* 24632 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8657 /* 24636 */ // MIs[2] Operand 1
8658 /* 24636 */ // No operand predicates
8659 /* 24636 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8660 /* 24638 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8661 /* 24638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8662 /* 24641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8663 /* 24643 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8664 /* 24645 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8665 /* 24648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8666 /* 24651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8667 /* 24657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8668 /* 24663 */ GIR_RootConstrainSelectedInstOperands,
8669 /* 24664 */ // GIR_Coverage, 6008,
8670 /* 24664 */ GIR_EraseRootFromParent_Done,
8671 /* 24665 */ // Label 562: @24665
8672 /* 24665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 563*/ GIMT_Encode4(24733), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 495 //
8673 /* 24672 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8674 /* 24676 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8675 /* 24680 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8676 /* 24684 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8677 /* 24688 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8678 /* 24692 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8679 /* 24696 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8680 /* 24700 */ // MIs[2] Operand 1
8681 /* 24700 */ // No operand predicates
8682 /* 24700 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8683 /* 24704 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8684 /* 24706 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8685 /* 24706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8686 /* 24709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8687 /* 24711 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8688 /* 24713 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8689 /* 24716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8690 /* 24719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8691 /* 24725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8692 /* 24731 */ GIR_RootConstrainSelectedInstOperands,
8693 /* 24732 */ // GIR_Coverage, 495,
8694 /* 24732 */ GIR_EraseRootFromParent_Done,
8695 /* 24733 */ // Label 563: @24733
8696 /* 24733 */ GIM_Reject,
8697 /* 24734 */ // Label 561: @24734
8698 /* 24734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 564*/ GIMT_Encode4(24800), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6011 //
8699 /* 24741 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8700 /* 24745 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8701 /* 24749 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8702 /* 24753 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8703 /* 24757 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8704 /* 24762 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8705 /* 24766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8706 /* 24770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8707 /* 24772 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8708 /* 24772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
8709 /* 24775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8710 /* 24777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8711 /* 24779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8712 /* 24783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8713 /* 24786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8714 /* 24792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8715 /* 24798 */ GIR_RootConstrainSelectedInstOperands,
8716 /* 24799 */ // GIR_Coverage, 6011,
8717 /* 24799 */ GIR_EraseRootFromParent_Done,
8718 /* 24800 */ // Label 564: @24800
8719 /* 24800 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 565*/ GIMT_Encode4(24866), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 496 //
8720 /* 24807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8721 /* 24811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8722 /* 24815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8723 /* 24819 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8724 /* 24823 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8725 /* 24827 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8726 /* 24832 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8727 /* 24836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8728 /* 24838 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8729 /* 24838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
8730 /* 24841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8731 /* 24843 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8732 /* 24845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8733 /* 24849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8734 /* 24852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8735 /* 24858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8736 /* 24864 */ GIR_RootConstrainSelectedInstOperands,
8737 /* 24865 */ // GIR_Coverage, 496,
8738 /* 24865 */ GIR_EraseRootFromParent_Done,
8739 /* 24866 */ // Label 565: @24866
8740 /* 24866 */ GIM_Reject,
8741 /* 24867 */ // Label 556: @24867
8742 /* 24867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 566*/ GIMT_Encode4(24921), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 2036 //
8743 /* 24874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8744 /* 24878 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8745 /* 24882 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
8746 /* 24893 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
8747 /* 24893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16),
8748 /* 24896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8749 /* 24898 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
8750 /* 24900 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
8751 /* 24910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8752 /* 24913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8753 /* 24919 */ GIR_RootConstrainSelectedInstOperands,
8754 /* 24920 */ // GIR_Coverage, 2036,
8755 /* 24920 */ GIR_EraseRootFromParent_Done,
8756 /* 24921 */ // Label 566: @24921
8757 /* 24921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 567*/ GIMT_Encode4(24975), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2290 //
8758 /* 24928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8759 /* 24932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8760 /* 24936 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
8761 /* 24947 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
8762 /* 24947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16),
8763 /* 24950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8764 /* 24952 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
8765 /* 24954 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
8766 /* 24964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8767 /* 24967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8768 /* 24973 */ GIR_RootConstrainSelectedInstOperands,
8769 /* 24974 */ // GIR_Coverage, 2290,
8770 /* 24974 */ GIR_EraseRootFromParent_Done,
8771 /* 24975 */ // Label 567: @24975
8772 /* 24975 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 568*/ GIMT_Encode4(25031), GIMT_Encode2(GIFBS_IsARM), // Rule ID 150 //
8773 /* 24982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8774 /* 24986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8775 /* 24990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8776 /* 24994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8777 /* 24998 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
8778 /* 25002 */ // MIs[1] Operand 1
8779 /* 25002 */ // No operand predicates
8780 /* 25002 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8781 /* 25004 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8782 /* 25004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri),
8783 /* 25007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8784 /* 25009 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8785 /* 25011 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8786 /* 25014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8787 /* 25017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8788 /* 25023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8789 /* 25029 */ GIR_RootConstrainSelectedInstOperands,
8790 /* 25030 */ // GIR_Coverage, 150,
8791 /* 25030 */ GIR_EraseRootFromParent_Done,
8792 /* 25031 */ // Label 568: @25031
8793 /* 25031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 569*/ GIMT_Encode4(25087), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 483 //
8794 /* 25038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8795 /* 25042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8796 /* 25046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8797 /* 25050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8798 /* 25054 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8799 /* 25058 */ // MIs[1] Operand 1
8800 /* 25058 */ // No operand predicates
8801 /* 25058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8802 /* 25060 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8803 /* 25060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri),
8804 /* 25063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8805 /* 25065 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8806 /* 25067 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8807 /* 25070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8808 /* 25073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8809 /* 25079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8810 /* 25085 */ GIR_RootConstrainSelectedInstOperands,
8811 /* 25086 */ // GIR_Coverage, 483,
8812 /* 25086 */ GIR_EraseRootFromParent_Done,
8813 /* 25087 */ // Label 569: @25087
8814 /* 25087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 570*/ GIMT_Encode4(25132), GIMT_Encode2(GIFBS_IsARM), // Rule ID 151 //
8815 /* 25094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8816 /* 25098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8817 /* 25102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8818 /* 25106 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
8819 /* 25106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr),
8820 /* 25109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8821 /* 25111 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8822 /* 25113 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
8823 /* 25115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8824 /* 25118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8825 /* 25124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8826 /* 25130 */ GIR_RootConstrainSelectedInstOperands,
8827 /* 25131 */ // GIR_Coverage, 151,
8828 /* 25131 */ GIR_EraseRootFromParent_Done,
8829 /* 25132 */ // Label 570: @25132
8830 /* 25132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 571*/ GIMT_Encode4(25177), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 324 //
8831 /* 25139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
8832 /* 25143 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
8833 /* 25147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
8834 /* 25151 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
8835 /* 25151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR),
8836 /* 25154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
8837 /* 25156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
8838 /* 25162 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8839 /* 25164 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
8840 /* 25166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8841 /* 25169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8842 /* 25175 */ GIR_RootConstrainSelectedInstOperands,
8843 /* 25176 */ // GIR_Coverage, 324,
8844 /* 25176 */ GIR_EraseRootFromParent_Done,
8845 /* 25177 */ // Label 571: @25177
8846 /* 25177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 572*/ GIMT_Encode4(25222), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 484 //
8847 /* 25184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8848 /* 25188 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8849 /* 25192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8850 /* 25196 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8851 /* 25196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8852 /* 25199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8853 /* 25201 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8854 /* 25203 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
8855 /* 25205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8856 /* 25208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8857 /* 25214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8858 /* 25220 */ GIR_RootConstrainSelectedInstOperands,
8859 /* 25221 */ // GIR_Coverage, 484,
8860 /* 25221 */ GIR_EraseRootFromParent_Done,
8861 /* 25222 */ // Label 572: @25222
8862 /* 25222 */ GIM_Reject,
8863 /* 25223 */ // Label 524: @25223
8864 /* 25223 */ GIM_Reject,
8865 /* 25224 */ // Label 511: @25224
8866 /* 25224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 573*/ GIMT_Encode4(25269), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2921 //
8867 /* 25231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
8868 /* 25234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
8869 /* 25237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8870 /* 25241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8871 /* 25245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8872 /* 25249 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
8873 /* 25249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
8874 /* 25252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
8875 /* 25254 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
8876 /* 25256 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
8877 /* 25258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8878 /* 25261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8879 /* 25267 */ GIR_RootConstrainSelectedInstOperands,
8880 /* 25268 */ // GIR_Coverage, 2921,
8881 /* 25268 */ GIR_EraseRootFromParent_Done,
8882 /* 25269 */ // Label 573: @25269
8883 /* 25269 */ GIM_Reject,
8884 /* 25270 */ // Label 512: @25270
8885 /* 25270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 574*/ GIMT_Encode4(25386), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2022 //
8886 /* 25277 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
8887 /* 25280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
8888 /* 25283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8889 /* 25287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8890 /* 25291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8891 /* 25295 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8892 /* 25295 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8893 /* 25298 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8894 /* 25302 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8895 /* 25307 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8896 /* 25311 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8897 /* 25316 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8898 /* 25319 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8899 /* 25323 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8900 /* 25328 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8901 /* 25332 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8902 /* 25337 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8903 /* 25340 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8904 /* 25344 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8905 /* 25349 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8906 /* 25352 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8907 /* 25355 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8908 /* 25358 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8909 /* 25364 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8910 /* 25370 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8911 /* 25372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8912 /* 25375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8913 /* 25377 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8914 /* 25380 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8915 /* 25385 */ // GIR_Coverage, 2022,
8916 /* 25385 */ GIR_EraseRootFromParent_Done,
8917 /* 25386 */ // Label 574: @25386
8918 /* 25386 */ GIM_Reject,
8919 /* 25387 */ // Label 513: @25387
8920 /* 25387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 575*/ GIMT_Encode4(25503), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2023 //
8921 /* 25394 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
8922 /* 25397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
8923 /* 25400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8924 /* 25404 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8925 /* 25408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8926 /* 25412 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8927 /* 25412 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8928 /* 25415 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8929 /* 25419 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8930 /* 25424 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8931 /* 25428 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8932 /* 25433 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8933 /* 25436 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8934 /* 25440 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8935 /* 25445 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8936 /* 25449 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8937 /* 25454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8938 /* 25457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8939 /* 25461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8940 /* 25466 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8941 /* 25469 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8942 /* 25472 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8943 /* 25475 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8944 /* 25481 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8945 /* 25487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8946 /* 25489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8947 /* 25492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8948 /* 25494 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8949 /* 25497 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8950 /* 25502 */ // GIR_Coverage, 2023,
8951 /* 25502 */ GIR_EraseRootFromParent_Done,
8952 /* 25503 */ // Label 575: @25503
8953 /* 25503 */ GIM_Reject,
8954 /* 25504 */ // Label 514: @25504
8955 /* 25504 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 576*/ GIMT_Encode4(25620), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2024 //
8956 /* 25511 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
8957 /* 25514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
8958 /* 25517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8959 /* 25521 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8960 /* 25525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8961 /* 25529 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8962 /* 25529 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8963 /* 25532 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8964 /* 25536 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8965 /* 25541 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8966 /* 25545 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8967 /* 25550 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8968 /* 25553 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8969 /* 25557 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8970 /* 25562 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8971 /* 25566 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8972 /* 25571 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8973 /* 25574 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8974 /* 25578 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8975 /* 25583 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8976 /* 25586 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8977 /* 25589 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8978 /* 25592 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8979 /* 25598 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8980 /* 25604 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8981 /* 25606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8982 /* 25609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8983 /* 25611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8984 /* 25614 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8985 /* 25619 */ // GIR_Coverage, 2024,
8986 /* 25619 */ GIR_EraseRootFromParent_Done,
8987 /* 25620 */ // Label 576: @25620
8988 /* 25620 */ GIM_Reject,
8989 /* 25621 */ // Label 515: @25621
8990 /* 25621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 577*/ GIMT_Encode4(25737), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2025 //
8991 /* 25628 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
8992 /* 25631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
8993 /* 25634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8994 /* 25638 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8995 /* 25642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8996 /* 25646 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8997 /* 25646 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8998 /* 25649 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8999 /* 25653 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9000 /* 25658 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9001 /* 25662 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9002 /* 25667 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9003 /* 25670 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9004 /* 25674 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9005 /* 25679 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9006 /* 25683 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9007 /* 25688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9008 /* 25691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9009 /* 25695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9010 /* 25700 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9011 /* 25703 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9012 /* 25706 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9013 /* 25709 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9014 /* 25715 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9015 /* 25721 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9016 /* 25723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9017 /* 25726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9018 /* 25728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9019 /* 25731 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9020 /* 25736 */ // GIR_Coverage, 2025,
9021 /* 25736 */ GIR_EraseRootFromParent_Done,
9022 /* 25737 */ // Label 577: @25737
9023 /* 25737 */ GIM_Reject,
9024 /* 25738 */ // Label 516: @25738
9025 /* 25738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 578*/ GIMT_Encode4(25783), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2919 //
9026 /* 25745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9027 /* 25748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9028 /* 25751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9029 /* 25755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9030 /* 25759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9031 /* 25763 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9032 /* 25763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9033 /* 25766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9034 /* 25768 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9035 /* 25770 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9036 /* 25772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9037 /* 25775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9038 /* 25781 */ GIR_RootConstrainSelectedInstOperands,
9039 /* 25782 */ // GIR_Coverage, 2919,
9040 /* 25782 */ GIR_EraseRootFromParent_Done,
9041 /* 25783 */ // Label 578: @25783
9042 /* 25783 */ GIM_Reject,
9043 /* 25784 */ // Label 517: @25784
9044 /* 25784 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(25895),
9045 /* 25789 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9046 /* 25792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9047 /* 25795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 580*/ GIMT_Encode4(25834), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2922 //
9048 /* 25802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9049 /* 25806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9050 /* 25810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9051 /* 25814 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9052 /* 25814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9053 /* 25817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9054 /* 25819 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9055 /* 25821 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9056 /* 25823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9057 /* 25826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9058 /* 25832 */ GIR_RootConstrainSelectedInstOperands,
9059 /* 25833 */ // GIR_Coverage, 2922,
9060 /* 25833 */ GIR_EraseRootFromParent_Done,
9061 /* 25834 */ // Label 580: @25834
9062 /* 25834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 581*/ GIMT_Encode4(25894), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3769 //
9063 /* 25841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9064 /* 25845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9065 /* 25849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9066 /* 25853 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9067 /* 25853 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9068 /* 25856 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9069 /* 25860 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9070 /* 25865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9071 /* 25868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9072 /* 25870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9073 /* 25872 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9074 /* 25874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9075 /* 25877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9076 /* 25883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9077 /* 25889 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9078 /* 25892 */ GIR_RootConstrainSelectedInstOperands,
9079 /* 25893 */ // GIR_Coverage, 3769,
9080 /* 25893 */ GIR_EraseRootFromParent_Done,
9081 /* 25894 */ // Label 581: @25894
9082 /* 25894 */ GIM_Reject,
9083 /* 25895 */ // Label 579: @25895
9084 /* 25895 */ GIM_Reject,
9085 /* 25896 */ // Label 518: @25896
9086 /* 25896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 582*/ GIMT_Encode4(25941), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2920 //
9087 /* 25903 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9088 /* 25906 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9089 /* 25909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9090 /* 25913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9091 /* 25917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9092 /* 25921 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
9093 /* 25921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9094 /* 25924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9095 /* 25926 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9096 /* 25928 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9097 /* 25930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9098 /* 25933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9099 /* 25939 */ GIR_RootConstrainSelectedInstOperands,
9100 /* 25940 */ // GIR_Coverage, 2920,
9101 /* 25940 */ GIR_EraseRootFromParent_Done,
9102 /* 25941 */ // Label 582: @25941
9103 /* 25941 */ GIM_Reject,
9104 /* 25942 */ // Label 519: @25942
9105 /* 25942 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(26053),
9106 /* 25947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9107 /* 25950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9108 /* 25953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 584*/ GIMT_Encode4(25992), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2923 //
9109 /* 25960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9110 /* 25964 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9111 /* 25968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9112 /* 25972 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
9113 /* 25972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9114 /* 25975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9115 /* 25977 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9116 /* 25979 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9117 /* 25981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9118 /* 25984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9119 /* 25990 */ GIR_RootConstrainSelectedInstOperands,
9120 /* 25991 */ // GIR_Coverage, 2923,
9121 /* 25991 */ GIR_EraseRootFromParent_Done,
9122 /* 25992 */ // Label 584: @25992
9123 /* 25992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 585*/ GIMT_Encode4(26052), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3773 //
9124 /* 25999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9125 /* 26003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9126 /* 26007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9127 /* 26011 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9128 /* 26011 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9129 /* 26014 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9130 /* 26018 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9131 /* 26023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9132 /* 26026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9133 /* 26028 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9134 /* 26030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9135 /* 26032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9136 /* 26035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9137 /* 26041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9138 /* 26047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9139 /* 26050 */ GIR_RootConstrainSelectedInstOperands,
9140 /* 26051 */ // GIR_Coverage, 3773,
9141 /* 26051 */ GIR_EraseRootFromParent_Done,
9142 /* 26052 */ // Label 585: @26052
9143 /* 26052 */ GIM_Reject,
9144 /* 26053 */ // Label 583: @26053
9145 /* 26053 */ GIM_Reject,
9146 /* 26054 */ // Label 520: @26054
9147 /* 26054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 586*/ GIMT_Encode4(26099), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1299 //
9148 /* 26061 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9149 /* 26064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9150 /* 26067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9151 /* 26071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9152 /* 26075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9153 /* 26079 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9154 /* 26079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9155 /* 26082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9156 /* 26084 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9157 /* 26086 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9158 /* 26088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9159 /* 26091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9160 /* 26097 */ GIR_RootConstrainSelectedInstOperands,
9161 /* 26098 */ // GIR_Coverage, 1299,
9162 /* 26098 */ GIR_EraseRootFromParent_Done,
9163 /* 26099 */ // Label 586: @26099
9164 /* 26099 */ GIM_Reject,
9165 /* 26100 */ // Label 521: @26100
9166 /* 26100 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(26211),
9167 /* 26105 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9168 /* 26108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9169 /* 26111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 588*/ GIMT_Encode4(26150), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1300 //
9170 /* 26118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9171 /* 26122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9172 /* 26126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9173 /* 26130 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9174 /* 26130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9175 /* 26133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9176 /* 26135 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9177 /* 26137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9178 /* 26139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9179 /* 26142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9180 /* 26148 */ GIR_RootConstrainSelectedInstOperands,
9181 /* 26149 */ // GIR_Coverage, 1300,
9182 /* 26149 */ GIR_EraseRootFromParent_Done,
9183 /* 26150 */ // Label 588: @26150
9184 /* 26150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 589*/ GIMT_Encode4(26210), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3777 //
9185 /* 26157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9186 /* 26161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9187 /* 26165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9188 /* 26169 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9189 /* 26169 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9190 /* 26172 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9191 /* 26176 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9192 /* 26181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9193 /* 26184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9194 /* 26186 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9195 /* 26188 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9196 /* 26190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9197 /* 26193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9198 /* 26199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9199 /* 26205 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9200 /* 26208 */ GIR_RootConstrainSelectedInstOperands,
9201 /* 26209 */ // GIR_Coverage, 3777,
9202 /* 26209 */ GIR_EraseRootFromParent_Done,
9203 /* 26210 */ // Label 589: @26210
9204 /* 26210 */ GIM_Reject,
9205 /* 26211 */ // Label 587: @26211
9206 /* 26211 */ GIM_Reject,
9207 /* 26212 */ // Label 522: @26212
9208 /* 26212 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(26323),
9209 /* 26217 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9210 /* 26220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9211 /* 26223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 591*/ GIMT_Encode4(26262), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2924 //
9212 /* 26230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9213 /* 26234 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9214 /* 26238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9215 /* 26242 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
9216 /* 26242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9217 /* 26245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9218 /* 26247 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9219 /* 26249 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9220 /* 26251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9221 /* 26254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9222 /* 26260 */ GIR_RootConstrainSelectedInstOperands,
9223 /* 26261 */ // GIR_Coverage, 2924,
9224 /* 26261 */ GIR_EraseRootFromParent_Done,
9225 /* 26262 */ // Label 591: @26262
9226 /* 26262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 592*/ GIMT_Encode4(26322), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3781 //
9227 /* 26269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9228 /* 26273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9229 /* 26277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9230 /* 26281 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
9231 /* 26281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9232 /* 26284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9233 /* 26288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9234 /* 26293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9235 /* 26296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9236 /* 26298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9237 /* 26300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9238 /* 26302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9239 /* 26305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9240 /* 26311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9241 /* 26317 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9242 /* 26320 */ GIR_RootConstrainSelectedInstOperands,
9243 /* 26321 */ // GIR_Coverage, 3781,
9244 /* 26321 */ GIR_EraseRootFromParent_Done,
9245 /* 26322 */ // Label 592: @26322
9246 /* 26322 */ GIM_Reject,
9247 /* 26323 */ // Label 590: @26323
9248 /* 26323 */ GIM_Reject,
9249 /* 26324 */ // Label 523: @26324
9250 /* 26324 */ GIM_Reject,
9251 /* 26325 */ // Label 7: @26325
9252 /* 26325 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 606*/ GIMT_Encode4(27983),
9253 /* 26336 */ /*GILLT_s32*//*Label 593*/ GIMT_Encode4(26388),
9254 /* 26340 */ /*GILLT_s64*//*Label 594*/ GIMT_Encode4(26883),
9255 /* 26344 */ /*GILLT_v2s1*//*Label 595*/ GIMT_Encode4(26929),
9256 /* 26348 */ /*GILLT_v4s1*//*Label 596*/ GIMT_Encode4(27046),
9257 /* 26352 */ /*GILLT_v8s1*//*Label 597*/ GIMT_Encode4(27163),
9258 /* 26356 */ /*GILLT_v16s1*//*Label 598*/ GIMT_Encode4(27280),
9259 /* 26360 */ /*GILLT_v8s8*//*Label 599*/ GIMT_Encode4(27397),
9260 /* 26364 */ /*GILLT_v16s8*//*Label 600*/ GIMT_Encode4(27443),
9261 /* 26368 */ /*GILLT_v4s16*//*Label 601*/ GIMT_Encode4(27555),
9262 /* 26372 */ /*GILLT_v8s16*//*Label 602*/ GIMT_Encode4(27601),
9263 /* 26376 */ /*GILLT_v2s32*//*Label 603*/ GIMT_Encode4(27713),
9264 /* 26380 */ /*GILLT_v4s32*//*Label 604*/ GIMT_Encode4(27759),
9265 /* 26384 */ /*GILLT_v2s64*//*Label 605*/ GIMT_Encode4(27871),
9266 /* 26388 */ // Label 593: @26388
9267 /* 26388 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(26882),
9268 /* 26393 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
9269 /* 26396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9270 /* 26399 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(26548),
9271 /* 26404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9272 /* 26408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 609*/ GIMT_Encode4(26458), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6013 //
9273 /* 26415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 255,
9274 /* 26419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9275 /* 26423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9276 /* 26427 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9277 /* 26431 */ // MIs[1] Operand 1
9278 /* 26431 */ // No operand predicates
9279 /* 26431 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9280 /* 26433 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9281 /* 26433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9282 /* 26436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9283 /* 26438 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9284 /* 26441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9285 /* 26444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9286 /* 26450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9287 /* 26456 */ GIR_RootConstrainSelectedInstOperands,
9288 /* 26457 */ // GIR_Coverage, 6013,
9289 /* 26457 */ GIR_EraseRootFromParent_Done,
9290 /* 26458 */ // Label 609: @26458
9291 /* 26458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 610*/ GIMT_Encode4(26508), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 498 //
9292 /* 26465 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9293 /* 26469 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9294 /* 26473 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9295 /* 26477 */ // MIs[1] Operand 1
9296 /* 26477 */ // No operand predicates
9297 /* 26477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9298 /* 26481 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9299 /* 26483 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9300 /* 26483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9301 /* 26486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9302 /* 26488 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9303 /* 26491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9304 /* 26494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9305 /* 26500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9306 /* 26506 */ GIR_RootConstrainSelectedInstOperands,
9307 /* 26507 */ // GIR_Coverage, 498,
9308 /* 26507 */ GIR_EraseRootFromParent_Done,
9309 /* 26508 */ // Label 610: @26508
9310 /* 26508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 611*/ GIMT_Encode4(26547), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 499 //
9311 /* 26515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9312 /* 26519 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9313 /* 26523 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
9314 /* 26523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr),
9315 /* 26526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9316 /* 26528 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9317 /* 26530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9318 /* 26533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9319 /* 26539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9320 /* 26545 */ GIR_RootConstrainSelectedInstOperands,
9321 /* 26546 */ // GIR_Coverage, 499,
9322 /* 26546 */ GIR_EraseRootFromParent_Done,
9323 /* 26547 */ // Label 611: @26547
9324 /* 26547 */ GIM_Reject,
9325 /* 26548 */ // Label 608: @26548
9326 /* 26548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 612*/ GIMT_Encode4(26591), GIMT_Encode2(GIFBS_IsARM), // Rule ID 164 //
9327 /* 26555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9328 /* 26559 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9329 /* 26563 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9330 /* 26567 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
9331 /* 26567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr),
9332 /* 26570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9333 /* 26572 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9334 /* 26574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9335 /* 26577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9336 /* 26583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9337 /* 26589 */ GIR_RootConstrainSelectedInstOperands,
9338 /* 26590 */ // GIR_Coverage, 164,
9339 /* 26590 */ GIR_EraseRootFromParent_Done,
9340 /* 26591 */ // Label 612: @26591
9341 /* 26591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 613*/ GIMT_Encode4(26634), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 323 //
9342 /* 26598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9343 /* 26602 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9344 /* 26606 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9345 /* 26610 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
9346 /* 26610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN),
9347 /* 26613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9348 /* 26615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9349 /* 26621 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9350 /* 26623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9351 /* 26626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9352 /* 26632 */ GIR_RootConstrainSelectedInstOperands,
9353 /* 26633 */ // GIR_Coverage, 323,
9354 /* 26633 */ GIR_EraseRootFromParent_Done,
9355 /* 26634 */ // Label 613: @26634
9356 /* 26634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 614*/ GIMT_Encode4(26690), GIMT_Encode2(GIFBS_IsARM), // Rule ID 154 //
9357 /* 26641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9358 /* 26645 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9359 /* 26649 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9360 /* 26653 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9361 /* 26657 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
9362 /* 26661 */ // MIs[1] Operand 1
9363 /* 26661 */ // No operand predicates
9364 /* 26661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9365 /* 26663 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9366 /* 26663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri),
9367 /* 26666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9368 /* 26668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9369 /* 26670 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9370 /* 26673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9371 /* 26676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9372 /* 26682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9373 /* 26688 */ GIR_RootConstrainSelectedInstOperands,
9374 /* 26689 */ // GIR_Coverage, 154,
9375 /* 26689 */ GIR_EraseRootFromParent_Done,
9376 /* 26690 */ // Label 614: @26690
9377 /* 26690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 615*/ GIMT_Encode4(26746), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 486 //
9378 /* 26697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9379 /* 26701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9380 /* 26705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9381 /* 26709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9382 /* 26713 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9383 /* 26717 */ // MIs[1] Operand 1
9384 /* 26717 */ // No operand predicates
9385 /* 26717 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9386 /* 26719 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9387 /* 26719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri),
9388 /* 26722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9389 /* 26724 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9390 /* 26726 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9391 /* 26729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9392 /* 26732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9393 /* 26738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9394 /* 26744 */ GIR_RootConstrainSelectedInstOperands,
9395 /* 26745 */ // GIR_Coverage, 486,
9396 /* 26745 */ GIR_EraseRootFromParent_Done,
9397 /* 26746 */ // Label 615: @26746
9398 /* 26746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 616*/ GIMT_Encode4(26791), GIMT_Encode2(GIFBS_IsARM), // Rule ID 155 //
9399 /* 26753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9400 /* 26757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9401 /* 26761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9402 /* 26765 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
9403 /* 26765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr),
9404 /* 26768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9405 /* 26770 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9406 /* 26772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9407 /* 26774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9408 /* 26777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9409 /* 26783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9410 /* 26789 */ GIR_RootConstrainSelectedInstOperands,
9411 /* 26790 */ // GIR_Coverage, 155,
9412 /* 26790 */ GIR_EraseRootFromParent_Done,
9413 /* 26791 */ // Label 616: @26791
9414 /* 26791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 617*/ GIMT_Encode4(26836), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 316 //
9415 /* 26798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9416 /* 26802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9417 /* 26806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9418 /* 26810 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
9419 /* 26810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR),
9420 /* 26813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
9421 /* 26815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9422 /* 26821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9423 /* 26823 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9424 /* 26825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9425 /* 26828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9426 /* 26834 */ GIR_RootConstrainSelectedInstOperands,
9427 /* 26835 */ // GIR_Coverage, 316,
9428 /* 26835 */ GIR_EraseRootFromParent_Done,
9429 /* 26836 */ // Label 617: @26836
9430 /* 26836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 618*/ GIMT_Encode4(26881), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 487 //
9431 /* 26843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9432 /* 26847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9433 /* 26851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9434 /* 26855 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9435 /* 26855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9436 /* 26858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9437 /* 26860 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9438 /* 26862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9439 /* 26864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9440 /* 26867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9441 /* 26873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9442 /* 26879 */ GIR_RootConstrainSelectedInstOperands,
9443 /* 26880 */ // GIR_Coverage, 487,
9444 /* 26880 */ GIR_EraseRootFromParent_Done,
9445 /* 26881 */ // Label 618: @26881
9446 /* 26881 */ GIM_Reject,
9447 /* 26882 */ // Label 607: @26882
9448 /* 26882 */ GIM_Reject,
9449 /* 26883 */ // Label 594: @26883
9450 /* 26883 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 619*/ GIMT_Encode4(26928), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2927 //
9451 /* 26890 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
9452 /* 26893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
9453 /* 26896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9454 /* 26900 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9455 /* 26904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9456 /* 26908 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
9457 /* 26908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9458 /* 26911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9459 /* 26913 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9460 /* 26915 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9461 /* 26917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9462 /* 26920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9463 /* 26926 */ GIR_RootConstrainSelectedInstOperands,
9464 /* 26927 */ // GIR_Coverage, 2927,
9465 /* 26927 */ GIR_EraseRootFromParent_Done,
9466 /* 26928 */ // Label 619: @26928
9467 /* 26928 */ GIM_Reject,
9468 /* 26929 */ // Label 595: @26929
9469 /* 26929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 620*/ GIMT_Encode4(27045), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2018 //
9470 /* 26936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
9471 /* 26939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
9472 /* 26942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9473 /* 26946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9474 /* 26950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9475 /* 26954 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9476 /* 26954 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9477 /* 26957 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9478 /* 26961 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9479 /* 26966 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9480 /* 26970 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9481 /* 26975 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9482 /* 26978 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9483 /* 26982 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9484 /* 26987 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9485 /* 26991 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9486 /* 26996 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9487 /* 26999 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9488 /* 27003 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9489 /* 27008 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9490 /* 27011 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9491 /* 27014 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9492 /* 27017 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9493 /* 27023 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9494 /* 27029 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9495 /* 27031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9496 /* 27034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9497 /* 27036 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9498 /* 27039 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9499 /* 27044 */ // GIR_Coverage, 2018,
9500 /* 27044 */ GIR_EraseRootFromParent_Done,
9501 /* 27045 */ // Label 620: @27045
9502 /* 27045 */ GIM_Reject,
9503 /* 27046 */ // Label 596: @27046
9504 /* 27046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 621*/ GIMT_Encode4(27162), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2019 //
9505 /* 27053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
9506 /* 27056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
9507 /* 27059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9508 /* 27063 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9509 /* 27067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9510 /* 27071 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9511 /* 27071 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9512 /* 27074 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9513 /* 27078 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9514 /* 27083 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9515 /* 27087 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9516 /* 27092 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9517 /* 27095 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9518 /* 27099 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9519 /* 27104 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9520 /* 27108 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9521 /* 27113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9522 /* 27116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9523 /* 27120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9524 /* 27125 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9525 /* 27128 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9526 /* 27131 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9527 /* 27134 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9528 /* 27140 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9529 /* 27146 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9530 /* 27148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9531 /* 27151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9532 /* 27153 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9533 /* 27156 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9534 /* 27161 */ // GIR_Coverage, 2019,
9535 /* 27161 */ GIR_EraseRootFromParent_Done,
9536 /* 27162 */ // Label 621: @27162
9537 /* 27162 */ GIM_Reject,
9538 /* 27163 */ // Label 597: @27163
9539 /* 27163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 622*/ GIMT_Encode4(27279), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2020 //
9540 /* 27170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
9541 /* 27173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
9542 /* 27176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9543 /* 27180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9544 /* 27184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9545 /* 27188 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9546 /* 27188 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9547 /* 27191 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9548 /* 27195 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9549 /* 27200 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9550 /* 27204 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9551 /* 27209 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9552 /* 27212 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9553 /* 27216 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9554 /* 27221 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9555 /* 27225 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9556 /* 27230 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9557 /* 27233 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9558 /* 27237 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9559 /* 27242 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9560 /* 27245 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9561 /* 27248 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9562 /* 27251 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9563 /* 27257 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9564 /* 27263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9565 /* 27265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9566 /* 27268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9567 /* 27270 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9568 /* 27273 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9569 /* 27278 */ // GIR_Coverage, 2020,
9570 /* 27278 */ GIR_EraseRootFromParent_Done,
9571 /* 27279 */ // Label 622: @27279
9572 /* 27279 */ GIM_Reject,
9573 /* 27280 */ // Label 598: @27280
9574 /* 27280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 623*/ GIMT_Encode4(27396), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2021 //
9575 /* 27287 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
9576 /* 27290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
9577 /* 27293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9578 /* 27297 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9579 /* 27301 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9580 /* 27305 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9581 /* 27305 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9582 /* 27308 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9583 /* 27312 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9584 /* 27317 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9585 /* 27321 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9586 /* 27326 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9587 /* 27329 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9588 /* 27333 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9589 /* 27338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9590 /* 27342 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9591 /* 27347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9592 /* 27350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9593 /* 27354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9594 /* 27359 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9595 /* 27362 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9596 /* 27365 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9597 /* 27368 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9598 /* 27374 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9599 /* 27380 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9600 /* 27382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9601 /* 27385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9602 /* 27387 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9603 /* 27390 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9604 /* 27395 */ // GIR_Coverage, 2021,
9605 /* 27395 */ GIR_EraseRootFromParent_Done,
9606 /* 27396 */ // Label 623: @27396
9607 /* 27396 */ GIM_Reject,
9608 /* 27397 */ // Label 599: @27397
9609 /* 27397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 624*/ GIMT_Encode4(27442), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2925 //
9610 /* 27404 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9611 /* 27407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9612 /* 27410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9613 /* 27414 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9614 /* 27418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9615 /* 27422 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9616 /* 27422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9617 /* 27425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9618 /* 27427 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9619 /* 27429 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9620 /* 27431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9621 /* 27434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9622 /* 27440 */ GIR_RootConstrainSelectedInstOperands,
9623 /* 27441 */ // GIR_Coverage, 2925,
9624 /* 27441 */ GIR_EraseRootFromParent_Done,
9625 /* 27442 */ // Label 624: @27442
9626 /* 27442 */ GIM_Reject,
9627 /* 27443 */ // Label 600: @27443
9628 /* 27443 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(27554),
9629 /* 27448 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9630 /* 27451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9631 /* 27454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 626*/ GIMT_Encode4(27493), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2928 //
9632 /* 27461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9633 /* 27465 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9634 /* 27469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9635 /* 27473 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9636 /* 27473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9637 /* 27476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9638 /* 27478 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9639 /* 27480 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9640 /* 27482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9641 /* 27485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9642 /* 27491 */ GIR_RootConstrainSelectedInstOperands,
9643 /* 27492 */ // GIR_Coverage, 2928,
9644 /* 27492 */ GIR_EraseRootFromParent_Done,
9645 /* 27493 */ // Label 626: @27493
9646 /* 27493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 627*/ GIMT_Encode4(27553), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3783 //
9647 /* 27500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9648 /* 27504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9649 /* 27508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9650 /* 27512 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9651 /* 27512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9652 /* 27515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9653 /* 27519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9654 /* 27524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9655 /* 27527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9656 /* 27529 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9657 /* 27531 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9658 /* 27533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9659 /* 27536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9660 /* 27542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9661 /* 27548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9662 /* 27551 */ GIR_RootConstrainSelectedInstOperands,
9663 /* 27552 */ // GIR_Coverage, 3783,
9664 /* 27552 */ GIR_EraseRootFromParent_Done,
9665 /* 27553 */ // Label 627: @27553
9666 /* 27553 */ GIM_Reject,
9667 /* 27554 */ // Label 625: @27554
9668 /* 27554 */ GIM_Reject,
9669 /* 27555 */ // Label 601: @27555
9670 /* 27555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 628*/ GIMT_Encode4(27600), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2926 //
9671 /* 27562 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9672 /* 27565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9673 /* 27568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9674 /* 27572 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9675 /* 27576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9676 /* 27580 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
9677 /* 27580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9678 /* 27583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9679 /* 27585 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9680 /* 27587 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9681 /* 27589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9682 /* 27592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9683 /* 27598 */ GIR_RootConstrainSelectedInstOperands,
9684 /* 27599 */ // GIR_Coverage, 2926,
9685 /* 27599 */ GIR_EraseRootFromParent_Done,
9686 /* 27600 */ // Label 628: @27600
9687 /* 27600 */ GIM_Reject,
9688 /* 27601 */ // Label 602: @27601
9689 /* 27601 */ GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(27712),
9690 /* 27606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9691 /* 27609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9692 /* 27612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 630*/ GIMT_Encode4(27651), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2929 //
9693 /* 27619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9694 /* 27623 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9695 /* 27627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9696 /* 27631 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
9697 /* 27631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9698 /* 27634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9699 /* 27636 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9700 /* 27638 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9701 /* 27640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9702 /* 27643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9703 /* 27649 */ GIR_RootConstrainSelectedInstOperands,
9704 /* 27650 */ // GIR_Coverage, 2929,
9705 /* 27650 */ GIR_EraseRootFromParent_Done,
9706 /* 27651 */ // Label 630: @27651
9707 /* 27651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 631*/ GIMT_Encode4(27711), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3787 //
9708 /* 27658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9709 /* 27662 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9710 /* 27666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9711 /* 27670 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9712 /* 27670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9713 /* 27673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9714 /* 27677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9715 /* 27682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9716 /* 27685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9717 /* 27687 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9718 /* 27689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9719 /* 27691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9720 /* 27694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9721 /* 27700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9722 /* 27706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9723 /* 27709 */ GIR_RootConstrainSelectedInstOperands,
9724 /* 27710 */ // GIR_Coverage, 3787,
9725 /* 27710 */ GIR_EraseRootFromParent_Done,
9726 /* 27711 */ // Label 631: @27711
9727 /* 27711 */ GIM_Reject,
9728 /* 27712 */ // Label 629: @27712
9729 /* 27712 */ GIM_Reject,
9730 /* 27713 */ // Label 603: @27713
9731 /* 27713 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 632*/ GIMT_Encode4(27758), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1297 //
9732 /* 27720 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9733 /* 27723 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9734 /* 27726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9735 /* 27730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9736 /* 27734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9737 /* 27738 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9738 /* 27738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9739 /* 27741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9740 /* 27743 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9741 /* 27745 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9742 /* 27747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9743 /* 27750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9744 /* 27756 */ GIR_RootConstrainSelectedInstOperands,
9745 /* 27757 */ // GIR_Coverage, 1297,
9746 /* 27757 */ GIR_EraseRootFromParent_Done,
9747 /* 27758 */ // Label 632: @27758
9748 /* 27758 */ GIM_Reject,
9749 /* 27759 */ // Label 604: @27759
9750 /* 27759 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(27870),
9751 /* 27764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9752 /* 27767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9753 /* 27770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 634*/ GIMT_Encode4(27809), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1298 //
9754 /* 27777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9755 /* 27781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9756 /* 27785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9757 /* 27789 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9758 /* 27789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9759 /* 27792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9760 /* 27794 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9761 /* 27796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9762 /* 27798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9763 /* 27801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9764 /* 27807 */ GIR_RootConstrainSelectedInstOperands,
9765 /* 27808 */ // GIR_Coverage, 1298,
9766 /* 27808 */ GIR_EraseRootFromParent_Done,
9767 /* 27809 */ // Label 634: @27809
9768 /* 27809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 635*/ GIMT_Encode4(27869), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3791 //
9769 /* 27816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9770 /* 27820 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9771 /* 27824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9772 /* 27828 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9773 /* 27828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9774 /* 27831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9775 /* 27835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9776 /* 27840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9777 /* 27843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9778 /* 27845 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9779 /* 27847 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9780 /* 27849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9781 /* 27852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9782 /* 27858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9783 /* 27864 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9784 /* 27867 */ GIR_RootConstrainSelectedInstOperands,
9785 /* 27868 */ // GIR_Coverage, 3791,
9786 /* 27868 */ GIR_EraseRootFromParent_Done,
9787 /* 27869 */ // Label 635: @27869
9788 /* 27869 */ GIM_Reject,
9789 /* 27870 */ // Label 633: @27870
9790 /* 27870 */ GIM_Reject,
9791 /* 27871 */ // Label 605: @27871
9792 /* 27871 */ GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(27982),
9793 /* 27876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9794 /* 27879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9795 /* 27882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 637*/ GIMT_Encode4(27921), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2930 //
9796 /* 27889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9797 /* 27893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9798 /* 27897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9799 /* 27901 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
9800 /* 27901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9801 /* 27904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9802 /* 27906 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9803 /* 27908 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9804 /* 27910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9805 /* 27913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9806 /* 27919 */ GIR_RootConstrainSelectedInstOperands,
9807 /* 27920 */ // GIR_Coverage, 2930,
9808 /* 27920 */ GIR_EraseRootFromParent_Done,
9809 /* 27921 */ // Label 637: @27921
9810 /* 27921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 638*/ GIMT_Encode4(27981), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3795 //
9811 /* 27928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9812 /* 27932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9813 /* 27936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9814 /* 27940 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
9815 /* 27940 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9816 /* 27943 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9817 /* 27947 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9818 /* 27952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9819 /* 27955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9820 /* 27957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9821 /* 27959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9822 /* 27961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9823 /* 27964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9824 /* 27970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9825 /* 27976 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9826 /* 27979 */ GIR_RootConstrainSelectedInstOperands,
9827 /* 27980 */ // GIR_Coverage, 3795,
9828 /* 27980 */ GIR_EraseRootFromParent_Done,
9829 /* 27981 */ // Label 638: @27981
9830 /* 27981 */ GIM_Reject,
9831 /* 27982 */ // Label 636: @27982
9832 /* 27982 */ GIM_Reject,
9833 /* 27983 */ // Label 606: @27983
9834 /* 27983 */ GIM_Reject,
9835 /* 27984 */ // Label 8: @27984
9836 /* 27984 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 645*/ GIMT_Encode4(28493),
9837 /* 27995 */ /*GILLT_v8s8*//*Label 639*/ GIMT_Encode4(28019),
9838 /* 27999 */ /*GILLT_v16s8*//*Label 640*/ GIMT_Encode4(28065),
9839 /* 28003 */ /*GILLT_v4s16*//*Label 641*/ GIMT_Encode4(28177),
9840 /* 28007 */ /*GILLT_v8s16*//*Label 642*/ GIMT_Encode4(28223),
9841 /* 28011 */ /*GILLT_v2s32*//*Label 643*/ GIMT_Encode4(28335),
9842 /* 28015 */ /*GILLT_v4s32*//*Label 644*/ GIMT_Encode4(28381),
9843 /* 28019 */ // Label 639: @28019
9844 /* 28019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 646*/ GIMT_Encode4(28064), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1323 //
9845 /* 28026 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9846 /* 28029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9847 /* 28032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9848 /* 28036 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9849 /* 28040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9850 /* 28044 */ // (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
9851 /* 28044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8),
9852 /* 28047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9853 /* 28049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9854 /* 28051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9855 /* 28053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9856 /* 28056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9857 /* 28062 */ GIR_RootConstrainSelectedInstOperands,
9858 /* 28063 */ // GIR_Coverage, 1323,
9859 /* 28063 */ GIR_EraseRootFromParent_Done,
9860 /* 28064 */ // Label 646: @28064
9861 /* 28064 */ GIM_Reject,
9862 /* 28065 */ // Label 640: @28065
9863 /* 28065 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(28176),
9864 /* 28070 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9865 /* 28073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9866 /* 28076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 648*/ GIMT_Encode4(28115), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1324 //
9867 /* 28083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9868 /* 28087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9869 /* 28091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9870 /* 28095 */ // (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
9871 /* 28095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8),
9872 /* 28098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9873 /* 28100 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9874 /* 28102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9875 /* 28104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9876 /* 28107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9877 /* 28113 */ GIR_RootConstrainSelectedInstOperands,
9878 /* 28114 */ // GIR_Coverage, 1324,
9879 /* 28114 */ GIR_EraseRootFromParent_Done,
9880 /* 28115 */ // Label 648: @28115
9881 /* 28115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 649*/ GIMT_Encode4(28175), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3946 //
9882 /* 28122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9883 /* 28126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9884 /* 28130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9885 /* 28134 */ // (abds:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9886 /* 28134 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9887 /* 28137 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9888 /* 28141 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9889 /* 28146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
9890 /* 28149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9891 /* 28151 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9892 /* 28153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9893 /* 28155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9894 /* 28158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9895 /* 28164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9896 /* 28170 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9897 /* 28173 */ GIR_RootConstrainSelectedInstOperands,
9898 /* 28174 */ // GIR_Coverage, 3946,
9899 /* 28174 */ GIR_EraseRootFromParent_Done,
9900 /* 28175 */ // Label 649: @28175
9901 /* 28175 */ GIM_Reject,
9902 /* 28176 */ // Label 647: @28176
9903 /* 28176 */ GIM_Reject,
9904 /* 28177 */ // Label 641: @28177
9905 /* 28177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 650*/ GIMT_Encode4(28222), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1319 //
9906 /* 28184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9907 /* 28187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9908 /* 28190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9909 /* 28194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9910 /* 28198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9911 /* 28202 */ // (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
9912 /* 28202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16),
9913 /* 28205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9914 /* 28207 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9915 /* 28209 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9916 /* 28211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9917 /* 28214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9918 /* 28220 */ GIR_RootConstrainSelectedInstOperands,
9919 /* 28221 */ // GIR_Coverage, 1319,
9920 /* 28221 */ GIR_EraseRootFromParent_Done,
9921 /* 28222 */ // Label 650: @28222
9922 /* 28222 */ GIM_Reject,
9923 /* 28223 */ // Label 642: @28223
9924 /* 28223 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(28334),
9925 /* 28228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9926 /* 28231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9927 /* 28234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 652*/ GIMT_Encode4(28273), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1321 //
9928 /* 28241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9929 /* 28245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9930 /* 28249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9931 /* 28253 */ // (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
9932 /* 28253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16),
9933 /* 28256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9934 /* 28258 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9935 /* 28260 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9936 /* 28262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9937 /* 28265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9938 /* 28271 */ GIR_RootConstrainSelectedInstOperands,
9939 /* 28272 */ // GIR_Coverage, 1321,
9940 /* 28272 */ GIR_EraseRootFromParent_Done,
9941 /* 28273 */ // Label 652: @28273
9942 /* 28273 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 653*/ GIMT_Encode4(28333), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3949 //
9943 /* 28280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9944 /* 28284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9945 /* 28288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9946 /* 28292 */ // (abds:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9947 /* 28292 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9948 /* 28295 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9949 /* 28299 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9950 /* 28304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
9951 /* 28307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9952 /* 28309 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9953 /* 28311 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9954 /* 28313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9955 /* 28316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9956 /* 28322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9957 /* 28328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9958 /* 28331 */ GIR_RootConstrainSelectedInstOperands,
9959 /* 28332 */ // GIR_Coverage, 3949,
9960 /* 28332 */ GIR_EraseRootFromParent_Done,
9961 /* 28333 */ // Label 653: @28333
9962 /* 28333 */ GIM_Reject,
9963 /* 28334 */ // Label 651: @28334
9964 /* 28334 */ GIM_Reject,
9965 /* 28335 */ // Label 643: @28335
9966 /* 28335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 654*/ GIMT_Encode4(28380), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1320 //
9967 /* 28342 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9968 /* 28345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9969 /* 28348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9970 /* 28352 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9971 /* 28356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9972 /* 28360 */ // (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9973 /* 28360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32),
9974 /* 28363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9975 /* 28365 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9976 /* 28367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9977 /* 28369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9978 /* 28372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9979 /* 28378 */ GIR_RootConstrainSelectedInstOperands,
9980 /* 28379 */ // GIR_Coverage, 1320,
9981 /* 28379 */ GIR_EraseRootFromParent_Done,
9982 /* 28380 */ // Label 654: @28380
9983 /* 28380 */ GIM_Reject,
9984 /* 28381 */ // Label 644: @28381
9985 /* 28381 */ GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(28492),
9986 /* 28386 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9987 /* 28389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9988 /* 28392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 656*/ GIMT_Encode4(28431), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1322 //
9989 /* 28399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9990 /* 28403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9991 /* 28407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9992 /* 28411 */ // (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9993 /* 28411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32),
9994 /* 28414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9995 /* 28416 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9996 /* 28418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9997 /* 28420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9998 /* 28423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9999 /* 28429 */ GIR_RootConstrainSelectedInstOperands,
10000 /* 28430 */ // GIR_Coverage, 1322,
10001 /* 28430 */ GIR_EraseRootFromParent_Done,
10002 /* 28431 */ // Label 656: @28431
10003 /* 28431 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 657*/ GIMT_Encode4(28491), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3953 //
10004 /* 28438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10005 /* 28442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10006 /* 28446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10007 /* 28450 */ // (abds:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10008 /* 28450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10009 /* 28453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10010 /* 28457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10011 /* 28462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
10012 /* 28465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10013 /* 28467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10014 /* 28469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10015 /* 28471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10016 /* 28474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10017 /* 28480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10018 /* 28486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10019 /* 28489 */ GIR_RootConstrainSelectedInstOperands,
10020 /* 28490 */ // GIR_Coverage, 3953,
10021 /* 28490 */ GIR_EraseRootFromParent_Done,
10022 /* 28491 */ // Label 657: @28491
10023 /* 28491 */ GIM_Reject,
10024 /* 28492 */ // Label 655: @28492
10025 /* 28492 */ GIM_Reject,
10026 /* 28493 */ // Label 645: @28493
10027 /* 28493 */ GIM_Reject,
10028 /* 28494 */ // Label 9: @28494
10029 /* 28494 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 664*/ GIMT_Encode4(29003),
10030 /* 28505 */ /*GILLT_v8s8*//*Label 658*/ GIMT_Encode4(28529),
10031 /* 28509 */ /*GILLT_v16s8*//*Label 659*/ GIMT_Encode4(28575),
10032 /* 28513 */ /*GILLT_v4s16*//*Label 660*/ GIMT_Encode4(28687),
10033 /* 28517 */ /*GILLT_v8s16*//*Label 661*/ GIMT_Encode4(28733),
10034 /* 28521 */ /*GILLT_v2s32*//*Label 662*/ GIMT_Encode4(28845),
10035 /* 28525 */ /*GILLT_v4s32*//*Label 663*/ GIMT_Encode4(28891),
10036 /* 28529 */ // Label 658: @28529
10037 /* 28529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 665*/ GIMT_Encode4(28574), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1329 //
10038 /* 28536 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10039 /* 28539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10040 /* 28542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10041 /* 28546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10042 /* 28550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10043 /* 28554 */ // (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
10044 /* 28554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8),
10045 /* 28557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10046 /* 28559 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10047 /* 28561 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10048 /* 28563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10049 /* 28566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10050 /* 28572 */ GIR_RootConstrainSelectedInstOperands,
10051 /* 28573 */ // GIR_Coverage, 1329,
10052 /* 28573 */ GIR_EraseRootFromParent_Done,
10053 /* 28574 */ // Label 665: @28574
10054 /* 28574 */ GIM_Reject,
10055 /* 28575 */ // Label 659: @28575
10056 /* 28575 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(28686),
10057 /* 28580 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10058 /* 28583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10059 /* 28586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 667*/ GIMT_Encode4(28625), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1330 //
10060 /* 28593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10061 /* 28597 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10062 /* 28601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10063 /* 28605 */ // (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
10064 /* 28605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8),
10065 /* 28608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10066 /* 28610 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10067 /* 28612 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10068 /* 28614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10069 /* 28617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10070 /* 28623 */ GIR_RootConstrainSelectedInstOperands,
10071 /* 28624 */ // GIR_Coverage, 1330,
10072 /* 28624 */ GIR_EraseRootFromParent_Done,
10073 /* 28625 */ // Label 667: @28625
10074 /* 28625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 668*/ GIMT_Encode4(28685), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3957 //
10075 /* 28632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10076 /* 28636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10077 /* 28640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10078 /* 28644 */ // (abdu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10079 /* 28644 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10080 /* 28647 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10081 /* 28651 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10082 /* 28656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
10083 /* 28659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10084 /* 28661 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10085 /* 28663 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10086 /* 28665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10087 /* 28668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10088 /* 28674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10089 /* 28680 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10090 /* 28683 */ GIR_RootConstrainSelectedInstOperands,
10091 /* 28684 */ // GIR_Coverage, 3957,
10092 /* 28684 */ GIR_EraseRootFromParent_Done,
10093 /* 28685 */ // Label 668: @28685
10094 /* 28685 */ GIM_Reject,
10095 /* 28686 */ // Label 666: @28686
10096 /* 28686 */ GIM_Reject,
10097 /* 28687 */ // Label 660: @28687
10098 /* 28687 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 669*/ GIMT_Encode4(28732), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1325 //
10099 /* 28694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10100 /* 28697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10101 /* 28700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10102 /* 28704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10103 /* 28708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10104 /* 28712 */ // (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10105 /* 28712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16),
10106 /* 28715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10107 /* 28717 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10108 /* 28719 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10109 /* 28721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10110 /* 28724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10111 /* 28730 */ GIR_RootConstrainSelectedInstOperands,
10112 /* 28731 */ // GIR_Coverage, 1325,
10113 /* 28731 */ GIR_EraseRootFromParent_Done,
10114 /* 28732 */ // Label 669: @28732
10115 /* 28732 */ GIM_Reject,
10116 /* 28733 */ // Label 661: @28733
10117 /* 28733 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(28844),
10118 /* 28738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10119 /* 28741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10120 /* 28744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 671*/ GIMT_Encode4(28783), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1327 //
10121 /* 28751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10122 /* 28755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10123 /* 28759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10124 /* 28763 */ // (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
10125 /* 28763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16),
10126 /* 28766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10127 /* 28768 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10128 /* 28770 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10129 /* 28772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10130 /* 28775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10131 /* 28781 */ GIR_RootConstrainSelectedInstOperands,
10132 /* 28782 */ // GIR_Coverage, 1327,
10133 /* 28782 */ GIR_EraseRootFromParent_Done,
10134 /* 28783 */ // Label 671: @28783
10135 /* 28783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 672*/ GIMT_Encode4(28843), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3961 //
10136 /* 28790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10137 /* 28794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10138 /* 28798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10139 /* 28802 */ // (abdu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10140 /* 28802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10141 /* 28805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10142 /* 28809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10143 /* 28814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
10144 /* 28817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10145 /* 28819 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10146 /* 28821 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10147 /* 28823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10148 /* 28826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10149 /* 28832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10150 /* 28838 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10151 /* 28841 */ GIR_RootConstrainSelectedInstOperands,
10152 /* 28842 */ // GIR_Coverage, 3961,
10153 /* 28842 */ GIR_EraseRootFromParent_Done,
10154 /* 28843 */ // Label 672: @28843
10155 /* 28843 */ GIM_Reject,
10156 /* 28844 */ // Label 670: @28844
10157 /* 28844 */ GIM_Reject,
10158 /* 28845 */ // Label 662: @28845
10159 /* 28845 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 673*/ GIMT_Encode4(28890), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1326 //
10160 /* 28852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10161 /* 28855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10162 /* 28858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10163 /* 28862 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10164 /* 28866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10165 /* 28870 */ // (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10166 /* 28870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32),
10167 /* 28873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10168 /* 28875 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10169 /* 28877 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10170 /* 28879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10171 /* 28882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10172 /* 28888 */ GIR_RootConstrainSelectedInstOperands,
10173 /* 28889 */ // GIR_Coverage, 1326,
10174 /* 28889 */ GIR_EraseRootFromParent_Done,
10175 /* 28890 */ // Label 673: @28890
10176 /* 28890 */ GIM_Reject,
10177 /* 28891 */ // Label 663: @28891
10178 /* 28891 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(29002),
10179 /* 28896 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10180 /* 28899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10181 /* 28902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 675*/ GIMT_Encode4(28941), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1328 //
10182 /* 28909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10183 /* 28913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10184 /* 28917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10185 /* 28921 */ // (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10186 /* 28921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32),
10187 /* 28924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10188 /* 28926 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10189 /* 28928 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10190 /* 28930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10191 /* 28933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10192 /* 28939 */ GIR_RootConstrainSelectedInstOperands,
10193 /* 28940 */ // GIR_Coverage, 1328,
10194 /* 28940 */ GIR_EraseRootFromParent_Done,
10195 /* 28941 */ // Label 675: @28941
10196 /* 28941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 676*/ GIMT_Encode4(29001), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3965 //
10197 /* 28948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10198 /* 28952 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10199 /* 28956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10200 /* 28960 */ // (abdu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10201 /* 28960 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10202 /* 28963 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10203 /* 28967 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10204 /* 28972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
10205 /* 28975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10206 /* 28977 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10207 /* 28979 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10208 /* 28981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10209 /* 28984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10210 /* 28990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10211 /* 28996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10212 /* 28999 */ GIR_RootConstrainSelectedInstOperands,
10213 /* 29000 */ // GIR_Coverage, 3965,
10214 /* 29000 */ GIR_EraseRootFromParent_Done,
10215 /* 29001 */ // Label 676: @29001
10216 /* 29001 */ GIM_Reject,
10217 /* 29002 */ // Label 674: @29002
10218 /* 29002 */ GIM_Reject,
10219 /* 29003 */ // Label 664: @29003
10220 /* 29003 */ GIM_Reject,
10221 /* 29004 */ // Label 10: @29004
10222 /* 29004 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 680*/ GIMT_Encode4(29230),
10223 /* 29015 */ /*GILLT_v16s8*//*Label 677*/ GIMT_Encode4(29035), GIMT_Encode4(0),
10224 /* 29023 */ /*GILLT_v8s16*//*Label 678*/ GIMT_Encode4(29100), GIMT_Encode4(0),
10225 /* 29031 */ /*GILLT_v4s32*//*Label 679*/ GIMT_Encode4(29165),
10226 /* 29035 */ // Label 677: @29035
10227 /* 29035 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(29099), // Rule ID 4005 //
10228 /* 29040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10229 /* 29043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10230 /* 29046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10231 /* 29050 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10232 /* 29054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10233 /* 29058 */ // (avgflooru:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10234 /* 29058 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10235 /* 29061 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10236 /* 29065 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10237 /* 29070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
10238 /* 29073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10239 /* 29075 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10240 /* 29077 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10241 /* 29079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10242 /* 29082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10243 /* 29088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10244 /* 29094 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10245 /* 29097 */ GIR_RootConstrainSelectedInstOperands,
10246 /* 29098 */ // GIR_Coverage, 4005,
10247 /* 29098 */ GIR_EraseRootFromParent_Done,
10248 /* 29099 */ // Label 681: @29099
10249 /* 29099 */ GIM_Reject,
10250 /* 29100 */ // Label 678: @29100
10251 /* 29100 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(29164), // Rule ID 4009 //
10252 /* 29105 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10253 /* 29108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10254 /* 29111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10255 /* 29115 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10256 /* 29119 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10257 /* 29123 */ // (avgflooru:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10258 /* 29123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10259 /* 29126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10260 /* 29130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10261 /* 29135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
10262 /* 29138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10263 /* 29140 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10264 /* 29142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10265 /* 29144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10266 /* 29147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10267 /* 29153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10268 /* 29159 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10269 /* 29162 */ GIR_RootConstrainSelectedInstOperands,
10270 /* 29163 */ // GIR_Coverage, 4009,
10271 /* 29163 */ GIR_EraseRootFromParent_Done,
10272 /* 29164 */ // Label 682: @29164
10273 /* 29164 */ GIM_Reject,
10274 /* 29165 */ // Label 679: @29165
10275 /* 29165 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(29229), // Rule ID 4013 //
10276 /* 29170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10277 /* 29173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10278 /* 29176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10279 /* 29180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10280 /* 29184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10281 /* 29188 */ // (avgflooru:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10282 /* 29188 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10283 /* 29191 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10284 /* 29195 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10285 /* 29200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
10286 /* 29203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10287 /* 29205 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10288 /* 29207 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10289 /* 29209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10290 /* 29212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10291 /* 29218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10292 /* 29224 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10293 /* 29227 */ GIR_RootConstrainSelectedInstOperands,
10294 /* 29228 */ // GIR_Coverage, 4013,
10295 /* 29228 */ GIR_EraseRootFromParent_Done,
10296 /* 29229 */ // Label 683: @29229
10297 /* 29229 */ GIM_Reject,
10298 /* 29230 */ // Label 680: @29230
10299 /* 29230 */ GIM_Reject,
10300 /* 29231 */ // Label 11: @29231
10301 /* 29231 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 687*/ GIMT_Encode4(29457),
10302 /* 29242 */ /*GILLT_v16s8*//*Label 684*/ GIMT_Encode4(29262), GIMT_Encode4(0),
10303 /* 29250 */ /*GILLT_v8s16*//*Label 685*/ GIMT_Encode4(29327), GIMT_Encode4(0),
10304 /* 29258 */ /*GILLT_v4s32*//*Label 686*/ GIMT_Encode4(29392),
10305 /* 29262 */ // Label 684: @29262
10306 /* 29262 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(29326), // Rule ID 3981 //
10307 /* 29267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10308 /* 29270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10309 /* 29273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10310 /* 29277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10311 /* 29281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10312 /* 29285 */ // (avgceilu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10313 /* 29285 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10314 /* 29288 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10315 /* 29292 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10316 /* 29297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
10317 /* 29300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10318 /* 29302 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10319 /* 29304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10320 /* 29306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10321 /* 29309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10322 /* 29315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10323 /* 29321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10324 /* 29324 */ GIR_RootConstrainSelectedInstOperands,
10325 /* 29325 */ // GIR_Coverage, 3981,
10326 /* 29325 */ GIR_EraseRootFromParent_Done,
10327 /* 29326 */ // Label 688: @29326
10328 /* 29326 */ GIM_Reject,
10329 /* 29327 */ // Label 685: @29327
10330 /* 29327 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(29391), // Rule ID 3985 //
10331 /* 29332 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10332 /* 29335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10333 /* 29338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10334 /* 29342 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10335 /* 29346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10336 /* 29350 */ // (avgceilu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10337 /* 29350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10338 /* 29353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10339 /* 29357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10340 /* 29362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
10341 /* 29365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10342 /* 29367 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10343 /* 29369 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10344 /* 29371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10345 /* 29374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10346 /* 29380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10347 /* 29386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10348 /* 29389 */ GIR_RootConstrainSelectedInstOperands,
10349 /* 29390 */ // GIR_Coverage, 3985,
10350 /* 29390 */ GIR_EraseRootFromParent_Done,
10351 /* 29391 */ // Label 689: @29391
10352 /* 29391 */ GIM_Reject,
10353 /* 29392 */ // Label 686: @29392
10354 /* 29392 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(29456), // Rule ID 3989 //
10355 /* 29397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10356 /* 29400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10357 /* 29403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10358 /* 29407 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10359 /* 29411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10360 /* 29415 */ // (avgceilu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10361 /* 29415 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10362 /* 29418 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10363 /* 29422 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10364 /* 29427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
10365 /* 29430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10366 /* 29432 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10367 /* 29434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10368 /* 29436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10369 /* 29439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10370 /* 29445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10371 /* 29451 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10372 /* 29454 */ GIR_RootConstrainSelectedInstOperands,
10373 /* 29455 */ // GIR_Coverage, 3989,
10374 /* 29455 */ GIR_EraseRootFromParent_Done,
10375 /* 29456 */ // Label 690: @29456
10376 /* 29456 */ GIM_Reject,
10377 /* 29457 */ // Label 687: @29457
10378 /* 29457 */ GIM_Reject,
10379 /* 29458 */ // Label 12: @29458
10380 /* 29458 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 694*/ GIMT_Encode4(29684),
10381 /* 29469 */ /*GILLT_v16s8*//*Label 691*/ GIMT_Encode4(29489), GIMT_Encode4(0),
10382 /* 29477 */ /*GILLT_v8s16*//*Label 692*/ GIMT_Encode4(29554), GIMT_Encode4(0),
10383 /* 29485 */ /*GILLT_v4s32*//*Label 693*/ GIMT_Encode4(29619),
10384 /* 29489 */ // Label 691: @29489
10385 /* 29489 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(29553), // Rule ID 3994 //
10386 /* 29494 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10387 /* 29497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10388 /* 29500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10389 /* 29504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10390 /* 29508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10391 /* 29512 */ // (avgfloors:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10392 /* 29512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10393 /* 29515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10394 /* 29519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10395 /* 29524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
10396 /* 29527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10397 /* 29529 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10398 /* 29531 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10399 /* 29533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10400 /* 29536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10401 /* 29542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10402 /* 29548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10403 /* 29551 */ GIR_RootConstrainSelectedInstOperands,
10404 /* 29552 */ // GIR_Coverage, 3994,
10405 /* 29552 */ GIR_EraseRootFromParent_Done,
10406 /* 29553 */ // Label 695: @29553
10407 /* 29553 */ GIM_Reject,
10408 /* 29554 */ // Label 692: @29554
10409 /* 29554 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(29618), // Rule ID 3997 //
10410 /* 29559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10411 /* 29562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10412 /* 29565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10413 /* 29569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10414 /* 29573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10415 /* 29577 */ // (avgfloors:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10416 /* 29577 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10417 /* 29580 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10418 /* 29584 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10419 /* 29589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
10420 /* 29592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10421 /* 29594 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10422 /* 29596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10423 /* 29598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10424 /* 29601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10425 /* 29607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10426 /* 29613 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10427 /* 29616 */ GIR_RootConstrainSelectedInstOperands,
10428 /* 29617 */ // GIR_Coverage, 3997,
10429 /* 29617 */ GIR_EraseRootFromParent_Done,
10430 /* 29618 */ // Label 696: @29618
10431 /* 29618 */ GIM_Reject,
10432 /* 29619 */ // Label 693: @29619
10433 /* 29619 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(29683), // Rule ID 4001 //
10434 /* 29624 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10435 /* 29627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10436 /* 29630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10437 /* 29634 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10438 /* 29638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10439 /* 29642 */ // (avgfloors:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10440 /* 29642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10441 /* 29645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10442 /* 29649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10443 /* 29654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
10444 /* 29657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10445 /* 29659 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10446 /* 29661 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10447 /* 29663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10448 /* 29666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10449 /* 29672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10450 /* 29678 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10451 /* 29681 */ GIR_RootConstrainSelectedInstOperands,
10452 /* 29682 */ // GIR_Coverage, 4001,
10453 /* 29682 */ GIR_EraseRootFromParent_Done,
10454 /* 29683 */ // Label 697: @29683
10455 /* 29683 */ GIM_Reject,
10456 /* 29684 */ // Label 694: @29684
10457 /* 29684 */ GIM_Reject,
10458 /* 29685 */ // Label 13: @29685
10459 /* 29685 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 701*/ GIMT_Encode4(29911),
10460 /* 29696 */ /*GILLT_v16s8*//*Label 698*/ GIMT_Encode4(29716), GIMT_Encode4(0),
10461 /* 29704 */ /*GILLT_v8s16*//*Label 699*/ GIMT_Encode4(29781), GIMT_Encode4(0),
10462 /* 29712 */ /*GILLT_v4s32*//*Label 700*/ GIMT_Encode4(29846),
10463 /* 29716 */ // Label 698: @29716
10464 /* 29716 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(29780), // Rule ID 3970 //
10465 /* 29721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10466 /* 29724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10467 /* 29727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10468 /* 29731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10469 /* 29735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10470 /* 29739 */ // (avgceils:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10471 /* 29739 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10472 /* 29742 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10473 /* 29746 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10474 /* 29751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
10475 /* 29754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10476 /* 29756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10477 /* 29758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10478 /* 29760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10479 /* 29763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10480 /* 29769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10481 /* 29775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10482 /* 29778 */ GIR_RootConstrainSelectedInstOperands,
10483 /* 29779 */ // GIR_Coverage, 3970,
10484 /* 29779 */ GIR_EraseRootFromParent_Done,
10485 /* 29780 */ // Label 702: @29780
10486 /* 29780 */ GIM_Reject,
10487 /* 29781 */ // Label 699: @29781
10488 /* 29781 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(29845), // Rule ID 3973 //
10489 /* 29786 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10490 /* 29789 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10491 /* 29792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10492 /* 29796 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10493 /* 29800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10494 /* 29804 */ // (avgceils:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10495 /* 29804 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10496 /* 29807 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10497 /* 29811 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10498 /* 29816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
10499 /* 29819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10500 /* 29821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10501 /* 29823 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10502 /* 29825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10503 /* 29828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10504 /* 29834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10505 /* 29840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10506 /* 29843 */ GIR_RootConstrainSelectedInstOperands,
10507 /* 29844 */ // GIR_Coverage, 3973,
10508 /* 29844 */ GIR_EraseRootFromParent_Done,
10509 /* 29845 */ // Label 703: @29845
10510 /* 29845 */ GIM_Reject,
10511 /* 29846 */ // Label 700: @29846
10512 /* 29846 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(29910), // Rule ID 3977 //
10513 /* 29851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10514 /* 29854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10515 /* 29857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10516 /* 29861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10517 /* 29865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10518 /* 29869 */ // (avgceils:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10519 /* 29869 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10520 /* 29872 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10521 /* 29876 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10522 /* 29881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
10523 /* 29884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10524 /* 29886 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10525 /* 29888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10526 /* 29890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10527 /* 29893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10528 /* 29899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10529 /* 29905 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10530 /* 29908 */ GIR_RootConstrainSelectedInstOperands,
10531 /* 29909 */ // GIR_Coverage, 3977,
10532 /* 29909 */ GIR_EraseRootFromParent_Done,
10533 /* 29910 */ // Label 704: @29910
10534 /* 29910 */ GIM_Reject,
10535 /* 29911 */ // Label 701: @29911
10536 /* 29911 */ GIM_Reject,
10537 /* 29912 */ // Label 14: @29912
10538 /* 29912 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(30578),
10539 /* 29917 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
10540 /* 29920 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 710*/ GIMT_Encode4(30577),
10541 /* 29931 */ /*GILLT_v16s8*//*Label 706*/ GIMT_Encode4(29955), GIMT_Encode4(0),
10542 /* 29939 */ /*GILLT_v8s16*//*Label 707*/ GIMT_Encode4(30061), GIMT_Encode4(0),
10543 /* 29947 */ /*GILLT_v4s32*//*Label 708*/ GIMT_Encode4(30272),
10544 /* 29951 */ /*GILLT_v2s64*//*Label 709*/ GIMT_Encode4(30471),
10545 /* 29955 */ // Label 706: @29955
10546 /* 29955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 711*/ GIMT_Encode4(30060), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3416 //
10547 /* 29962 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10548 /* 29965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10549 /* 29968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10550 /* 29972 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10551 /* 29976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10552 /* 29980 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (INSERT_SUBREG:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
10553 /* 29980 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
10554 /* 29983 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10555 /* 29987 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10556 /* 29992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10557 /* 29994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
10558 /* 29997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10559 /* 30001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10560 /* 30006 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10561 /* 30009 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10562 /* 30013 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10563 /* 30016 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10564 /* 30021 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10565 /* 30026 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10566 /* 30031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10567 /* 30034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10568 /* 30036 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10569 /* 30039 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10570 /* 30041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10571 /* 30044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10572 /* 30049 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10573 /* 30054 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10574 /* 30059 */ // GIR_Coverage, 3416,
10575 /* 30059 */ GIR_EraseRootFromParent_Done,
10576 /* 30060 */ // Label 711: @30060
10577 /* 30060 */ GIM_Reject,
10578 /* 30061 */ // Label 707: @30061
10579 /* 30061 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(30271),
10580 /* 30066 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10581 /* 30069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10582 /* 30072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 713*/ GIMT_Encode4(30171), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3415 //
10583 /* 30079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10584 /* 30083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10585 /* 30087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10586 /* 30091 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (INSERT_SUBREG:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
10587 /* 30091 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
10588 /* 30094 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10589 /* 30098 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10590 /* 30103 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10591 /* 30105 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
10592 /* 30108 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10593 /* 30112 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10594 /* 30117 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10595 /* 30120 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10596 /* 30124 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10597 /* 30127 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10598 /* 30132 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10599 /* 30137 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10600 /* 30142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10601 /* 30145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10602 /* 30147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10603 /* 30150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10604 /* 30152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10605 /* 30155 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10606 /* 30160 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10607 /* 30165 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10608 /* 30170 */ // GIR_Coverage, 3415,
10609 /* 30170 */ GIR_EraseRootFromParent_Done,
10610 /* 30171 */ // Label 713: @30171
10611 /* 30171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 714*/ GIMT_Encode4(30270), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3418 //
10612 /* 30178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10613 /* 30182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10614 /* 30186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10615 /* 30190 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (INSERT_SUBREG:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
10616 /* 30190 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
10617 /* 30193 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10618 /* 30197 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10619 /* 30202 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10620 /* 30204 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
10621 /* 30207 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10622 /* 30211 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10623 /* 30216 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10624 /* 30219 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10625 /* 30223 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10626 /* 30226 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10627 /* 30231 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID),
10628 /* 30236 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10629 /* 30241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10630 /* 30244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10631 /* 30246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10632 /* 30249 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10633 /* 30251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10634 /* 30254 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10635 /* 30259 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID),
10636 /* 30264 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10637 /* 30269 */ // GIR_Coverage, 3418,
10638 /* 30269 */ GIR_EraseRootFromParent_Done,
10639 /* 30270 */ // Label 714: @30270
10640 /* 30270 */ GIM_Reject,
10641 /* 30271 */ // Label 712: @30271
10642 /* 30271 */ GIM_Reject,
10643 /* 30272 */ // Label 708: @30272
10644 /* 30272 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(30470),
10645 /* 30277 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10646 /* 30280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10647 /* 30283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10648 /* 30287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10649 /* 30291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10650 /* 30295 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 716*/ GIMT_Encode4(30382), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3414 //
10651 /* 30302 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (INSERT_SUBREG:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
10652 /* 30302 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
10653 /* 30305 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10654 /* 30309 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10655 /* 30314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10656 /* 30316 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10657 /* 30319 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10658 /* 30323 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10659 /* 30328 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10660 /* 30331 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10661 /* 30335 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10662 /* 30338 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10663 /* 30343 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10664 /* 30348 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10665 /* 30353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10666 /* 30356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10667 /* 30358 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10668 /* 30361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10669 /* 30363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10670 /* 30366 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10671 /* 30371 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10672 /* 30376 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10673 /* 30381 */ // GIR_Coverage, 3414,
10674 /* 30381 */ GIR_EraseRootFromParent_Done,
10675 /* 30382 */ // Label 716: @30382
10676 /* 30382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 717*/ GIMT_Encode4(30469), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3417 //
10677 /* 30389 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (INSERT_SUBREG:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
10678 /* 30389 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
10679 /* 30392 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10680 /* 30396 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10681 /* 30401 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10682 /* 30403 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10683 /* 30406 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10684 /* 30410 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10685 /* 30415 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10686 /* 30418 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10687 /* 30422 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10688 /* 30425 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10689 /* 30430 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10690 /* 30435 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10691 /* 30440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10692 /* 30443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10693 /* 30445 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10694 /* 30448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10695 /* 30450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10696 /* 30453 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10697 /* 30458 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10698 /* 30463 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10699 /* 30468 */ // GIR_Coverage, 3417,
10700 /* 30468 */ GIR_EraseRootFromParent_Done,
10701 /* 30469 */ // Label 717: @30469
10702 /* 30469 */ GIM_Reject,
10703 /* 30470 */ // Label 715: @30470
10704 /* 30470 */ GIM_Reject,
10705 /* 30471 */ // Label 709: @30471
10706 /* 30471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 718*/ GIMT_Encode4(30576), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3413 //
10707 /* 30478 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
10708 /* 30481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
10709 /* 30484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10710 /* 30488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10711 /* 30492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10712 /* 30496 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (INSERT_SUBREG:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
10713 /* 30496 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
10714 /* 30499 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10715 /* 30503 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10716 /* 30508 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10717 /* 30510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
10718 /* 30513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10719 /* 30517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10720 /* 30522 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10721 /* 30525 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10722 /* 30529 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10723 /* 30532 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10724 /* 30537 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10725 /* 30542 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10726 /* 30547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10727 /* 30550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10728 /* 30552 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10729 /* 30555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10730 /* 30557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10731 /* 30560 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10732 /* 30565 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10733 /* 30570 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10734 /* 30575 */ // GIR_Coverage, 3413,
10735 /* 30575 */ GIR_EraseRootFromParent_Done,
10736 /* 30576 */ // Label 718: @30576
10737 /* 30576 */ GIM_Reject,
10738 /* 30577 */ // Label 710: @30577
10739 /* 30577 */ GIM_Reject,
10740 /* 30578 */ // Label 705: @30578
10741 /* 30578 */ GIM_Reject,
10742 /* 30579 */ // Label 15: @30579
10743 /* 30579 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 728*/ GIMT_Encode4(37765),
10744 /* 30590 */ /*GILLT_s32*//*Label 719*/ GIMT_Encode4(30642),
10745 /* 30594 */ /*GILLT_s64*//*Label 720*/ GIMT_Encode4(30785), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10746 /* 30614 */ /*GILLT_v8s8*//*Label 721*/ GIMT_Encode4(31387),
10747 /* 30618 */ /*GILLT_v16s8*//*Label 722*/ GIMT_Encode4(31754),
10748 /* 30622 */ /*GILLT_v4s16*//*Label 723*/ GIMT_Encode4(32535),
10749 /* 30626 */ /*GILLT_v8s16*//*Label 724*/ GIMT_Encode4(33137),
10750 /* 30630 */ /*GILLT_v2s32*//*Label 725*/ GIMT_Encode4(34479),
10751 /* 30634 */ /*GILLT_v4s32*//*Label 726*/ GIMT_Encode4(35081),
10752 /* 30638 */ /*GILLT_v2s64*//*Label 727*/ GIMT_Encode4(36423),
10753 /* 30642 */ // Label 719: @30642
10754 /* 30642 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(30784),
10755 /* 30647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
10756 /* 30650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 730*/ GIMT_Encode4(30683), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 740 //
10757 /* 30657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
10758 /* 30661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
10759 /* 30665 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
10760 /* 30665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS),
10761 /* 30668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
10762 /* 30670 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
10763 /* 30672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10764 /* 30675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10765 /* 30681 */ GIR_RootConstrainSelectedInstOperands,
10766 /* 30682 */ // GIR_Coverage, 740,
10767 /* 30682 */ GIR_EraseRootFromParent_Done,
10768 /* 30683 */ // Label 730: @30683
10769 /* 30683 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(30783),
10770 /* 30688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
10771 /* 30692 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
10772 /* 30696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 732*/ GIMT_Encode4(30721), GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), // Rule ID 741 //
10773 /* 30703 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
10774 /* 30703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR),
10775 /* 30706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn]
10776 /* 30708 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
10777 /* 30710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10778 /* 30713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10779 /* 30719 */ GIR_RootConstrainSelectedInstOperands,
10780 /* 30720 */ // GIR_Coverage, 741,
10781 /* 30720 */ GIR_EraseRootFromParent_Done,
10782 /* 30721 */ // Label 732: @30721
10783 /* 30721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 733*/ GIMT_Encode4(30782), GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), // Rule ID 3107 //
10784 /* 30728 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] })
10785 /* 30728 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
10786 /* 30731 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR),
10787 /* 30735 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10788 /* 30740 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
10789 /* 30744 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
10790 /* 30748 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
10791 /* 30751 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10792 /* 30757 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
10793 /* 30759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10794 /* 30762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10795 /* 30764 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
10796 /* 30771 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
10797 /* 30776 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
10798 /* 30781 */ // GIR_Coverage, 3107,
10799 /* 30781 */ GIR_EraseRootFromParent_Done,
10800 /* 30782 */ // Label 733: @30782
10801 /* 30782 */ GIM_Reject,
10802 /* 30783 */ // Label 731: @30783
10803 /* 30783 */ GIM_Reject,
10804 /* 30784 */ // Label 729: @30784
10805 /* 30784 */ GIM_Reject,
10806 /* 30785 */ // Label 720: @30785
10807 /* 30785 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 738*/ GIMT_Encode4(31386),
10808 /* 30796 */ /*GILLT_s64*//*Label 734*/ GIMT_Encode4(30836), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10809 /* 30816 */ /*GILLT_v8s8*//*Label 735*/ GIMT_Encode4(30891), GIMT_Encode4(0),
10810 /* 30824 */ /*GILLT_v4s16*//*Label 736*/ GIMT_Encode4(30996), GIMT_Encode4(0),
10811 /* 30832 */ /*GILLT_v2s32*//*Label 737*/ GIMT_Encode4(31191),
10812 /* 30836 */ // Label 734: @30836
10813 /* 30836 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(30890),
10814 /* 30841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10815 /* 30845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10816 /* 30849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 740*/ GIMT_Encode4(30869), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3109 //
10817 /* 30856 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src
10818 /* 30856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10819 /* 30859 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10820 /* 30861 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10821 /* 30863 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10822 /* 30868 */ // GIR_Coverage, 3109,
10823 /* 30868 */ GIR_EraseRootFromParent_Done,
10824 /* 30869 */ // Label 740: @30869
10825 /* 30869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 741*/ GIMT_Encode4(30889), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3110 //
10826 /* 30876 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src
10827 /* 30876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10828 /* 30879 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10829 /* 30881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10830 /* 30883 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10831 /* 30888 */ // GIR_Coverage, 3110,
10832 /* 30888 */ GIR_EraseRootFromParent_Done,
10833 /* 30889 */ // Label 741: @30889
10834 /* 30889 */ GIM_Reject,
10835 /* 30890 */ // Label 739: @30890
10836 /* 30890 */ GIM_Reject,
10837 /* 30891 */ // Label 735: @30891
10838 /* 30891 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(30995),
10839 /* 30896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10840 /* 30900 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10841 /* 30904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 743*/ GIMT_Encode4(30924), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3125 //
10842 /* 30911 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src
10843 /* 30911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10844 /* 30914 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10845 /* 30916 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10846 /* 30918 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10847 /* 30923 */ // GIR_Coverage, 3125,
10848 /* 30923 */ GIR_EraseRootFromParent_Done,
10849 /* 30924 */ // Label 743: @30924
10850 /* 30924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 744*/ GIMT_Encode4(30944), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3130 //
10851 /* 30931 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src
10852 /* 30931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10853 /* 30934 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10854 /* 30936 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10855 /* 30938 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10856 /* 30943 */ // GIR_Coverage, 3130,
10857 /* 30943 */ GIR_EraseRootFromParent_Done,
10858 /* 30944 */ // Label 744: @30944
10859 /* 30944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 745*/ GIMT_Encode4(30969), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3197 //
10860 /* 30951 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
10861 /* 30951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
10862 /* 30954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10863 /* 30956 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10864 /* 30958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10865 /* 30961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10866 /* 30967 */ GIR_RootConstrainSelectedInstOperands,
10867 /* 30968 */ // GIR_Coverage, 3197,
10868 /* 30968 */ GIR_EraseRootFromParent_Done,
10869 /* 30969 */ // Label 745: @30969
10870 /* 30969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 746*/ GIMT_Encode4(30994), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3202 //
10871 /* 30976 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
10872 /* 30976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
10873 /* 30979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10874 /* 30981 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10875 /* 30983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10876 /* 30986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10877 /* 30992 */ GIR_RootConstrainSelectedInstOperands,
10878 /* 30993 */ // GIR_Coverage, 3202,
10879 /* 30993 */ GIR_EraseRootFromParent_Done,
10880 /* 30994 */ // Label 746: @30994
10881 /* 30994 */ GIM_Reject,
10882 /* 30995 */ // Label 742: @30995
10883 /* 30995 */ GIM_Reject,
10884 /* 30996 */ // Label 736: @30996
10885 /* 30996 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(31190),
10886 /* 31001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10887 /* 31005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10888 /* 31009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 748*/ GIMT_Encode4(31029), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3123 //
10889 /* 31016 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src
10890 /* 31016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10891 /* 31019 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10892 /* 31021 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10893 /* 31023 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10894 /* 31028 */ // GIR_Coverage, 3123,
10895 /* 31028 */ GIR_EraseRootFromParent_Done,
10896 /* 31029 */ // Label 748: @31029
10897 /* 31029 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 749*/ GIMT_Encode4(31049), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3124 //
10898 /* 31036 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src
10899 /* 31036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10900 /* 31039 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10901 /* 31041 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10902 /* 31043 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10903 /* 31048 */ // GIR_Coverage, 3124,
10904 /* 31048 */ GIR_EraseRootFromParent_Done,
10905 /* 31049 */ // Label 749: @31049
10906 /* 31049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 750*/ GIMT_Encode4(31069), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3128 //
10907 /* 31056 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src
10908 /* 31056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10909 /* 31059 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10910 /* 31061 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10911 /* 31063 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10912 /* 31068 */ // GIR_Coverage, 3128,
10913 /* 31068 */ GIR_EraseRootFromParent_Done,
10914 /* 31069 */ // Label 750: @31069
10915 /* 31069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 751*/ GIMT_Encode4(31089), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3129 //
10916 /* 31076 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src
10917 /* 31076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10918 /* 31079 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10919 /* 31081 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10920 /* 31083 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10921 /* 31088 */ // GIR_Coverage, 3129,
10922 /* 31088 */ GIR_EraseRootFromParent_Done,
10923 /* 31089 */ // Label 751: @31089
10924 /* 31089 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 752*/ GIMT_Encode4(31114), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3195 //
10925 /* 31096 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
10926 /* 31096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10927 /* 31099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10928 /* 31101 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10929 /* 31103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10930 /* 31106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10931 /* 31112 */ GIR_RootConstrainSelectedInstOperands,
10932 /* 31113 */ // GIR_Coverage, 3195,
10933 /* 31113 */ GIR_EraseRootFromParent_Done,
10934 /* 31114 */ // Label 752: @31114
10935 /* 31114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 753*/ GIMT_Encode4(31139), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3196 //
10936 /* 31121 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
10937 /* 31121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10938 /* 31124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10939 /* 31126 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10940 /* 31128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10941 /* 31131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10942 /* 31137 */ GIR_RootConstrainSelectedInstOperands,
10943 /* 31138 */ // GIR_Coverage, 3196,
10944 /* 31138 */ GIR_EraseRootFromParent_Done,
10945 /* 31139 */ // Label 753: @31139
10946 /* 31139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 754*/ GIMT_Encode4(31164), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3200 //
10947 /* 31146 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
10948 /* 31146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10949 /* 31149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10950 /* 31151 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10951 /* 31153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10952 /* 31156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10953 /* 31162 */ GIR_RootConstrainSelectedInstOperands,
10954 /* 31163 */ // GIR_Coverage, 3200,
10955 /* 31163 */ GIR_EraseRootFromParent_Done,
10956 /* 31164 */ // Label 754: @31164
10957 /* 31164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 755*/ GIMT_Encode4(31189), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3201 //
10958 /* 31171 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
10959 /* 31171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10960 /* 31174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10961 /* 31176 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10962 /* 31178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10963 /* 31181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10964 /* 31187 */ GIR_RootConstrainSelectedInstOperands,
10965 /* 31188 */ // GIR_Coverage, 3201,
10966 /* 31188 */ GIR_EraseRootFromParent_Done,
10967 /* 31189 */ // Label 755: @31189
10968 /* 31189 */ GIM_Reject,
10969 /* 31190 */ // Label 747: @31190
10970 /* 31190 */ GIM_Reject,
10971 /* 31191 */ // Label 737: @31191
10972 /* 31191 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(31385),
10973 /* 31196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10974 /* 31200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10975 /* 31204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 757*/ GIMT_Encode4(31224), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3121 //
10976 /* 31211 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src
10977 /* 31211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10978 /* 31214 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10979 /* 31216 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10980 /* 31218 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10981 /* 31223 */ // GIR_Coverage, 3121,
10982 /* 31223 */ GIR_EraseRootFromParent_Done,
10983 /* 31224 */ // Label 757: @31224
10984 /* 31224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 758*/ GIMT_Encode4(31244), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3122 //
10985 /* 31231 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src
10986 /* 31231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10987 /* 31234 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10988 /* 31236 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10989 /* 31238 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10990 /* 31243 */ // GIR_Coverage, 3122,
10991 /* 31243 */ GIR_EraseRootFromParent_Done,
10992 /* 31244 */ // Label 758: @31244
10993 /* 31244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 759*/ GIMT_Encode4(31264), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3126 //
10994 /* 31251 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src
10995 /* 31251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10996 /* 31254 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10997 /* 31256 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10998 /* 31258 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10999 /* 31263 */ // GIR_Coverage, 3126,
11000 /* 31263 */ GIR_EraseRootFromParent_Done,
11001 /* 31264 */ // Label 759: @31264
11002 /* 31264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 760*/ GIMT_Encode4(31284), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3127 //
11003 /* 31271 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src
11004 /* 31271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11005 /* 31274 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11006 /* 31276 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11007 /* 31278 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11008 /* 31283 */ // GIR_Coverage, 3127,
11009 /* 31283 */ GIR_EraseRootFromParent_Done,
11010 /* 31284 */ // Label 760: @31284
11011 /* 31284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 761*/ GIMT_Encode4(31309), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3193 //
11012 /* 31291 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
11013 /* 31291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11014 /* 31294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11015 /* 31296 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11016 /* 31298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11017 /* 31301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11018 /* 31307 */ GIR_RootConstrainSelectedInstOperands,
11019 /* 31308 */ // GIR_Coverage, 3193,
11020 /* 31308 */ GIR_EraseRootFromParent_Done,
11021 /* 31309 */ // Label 761: @31309
11022 /* 31309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 762*/ GIMT_Encode4(31334), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3194 //
11023 /* 31316 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
11024 /* 31316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11025 /* 31319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11026 /* 31321 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11027 /* 31323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11028 /* 31326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11029 /* 31332 */ GIR_RootConstrainSelectedInstOperands,
11030 /* 31333 */ // GIR_Coverage, 3194,
11031 /* 31333 */ GIR_EraseRootFromParent_Done,
11032 /* 31334 */ // Label 762: @31334
11033 /* 31334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 763*/ GIMT_Encode4(31359), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3198 //
11034 /* 31341 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
11035 /* 31341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11036 /* 31344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11037 /* 31346 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11038 /* 31348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11039 /* 31351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11040 /* 31357 */ GIR_RootConstrainSelectedInstOperands,
11041 /* 31358 */ // GIR_Coverage, 3198,
11042 /* 31358 */ GIR_EraseRootFromParent_Done,
11043 /* 31359 */ // Label 763: @31359
11044 /* 31359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 764*/ GIMT_Encode4(31384), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3199 //
11045 /* 31366 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
11046 /* 31366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11047 /* 31369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11048 /* 31371 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11049 /* 31373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11050 /* 31376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11051 /* 31382 */ GIR_RootConstrainSelectedInstOperands,
11052 /* 31383 */ // GIR_Coverage, 3199,
11053 /* 31383 */ GIR_EraseRootFromParent_Done,
11054 /* 31384 */ // Label 764: @31384
11055 /* 31384 */ GIM_Reject,
11056 /* 31385 */ // Label 756: @31385
11057 /* 31385 */ GIM_Reject,
11058 /* 31386 */ // Label 738: @31386
11059 /* 31386 */ GIM_Reject,
11060 /* 31387 */ // Label 721: @31387
11061 /* 31387 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 768*/ GIMT_Encode4(31753),
11062 /* 31398 */ /*GILLT_s64*//*Label 765*/ GIMT_Encode4(31438), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
11063 /* 31426 */ /*GILLT_v4s16*//*Label 766*/ GIMT_Encode4(31543), GIMT_Encode4(0),
11064 /* 31434 */ /*GILLT_v2s32*//*Label 767*/ GIMT_Encode4(31648),
11065 /* 31438 */ // Label 765: @31438
11066 /* 31438 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(31542),
11067 /* 31443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11068 /* 31447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11069 /* 31451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 770*/ GIMT_Encode4(31471), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3151 //
11070 /* 31458 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src
11071 /* 31458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11072 /* 31461 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11073 /* 31463 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11074 /* 31465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11075 /* 31470 */ // GIR_Coverage, 3151,
11076 /* 31470 */ GIR_EraseRootFromParent_Done,
11077 /* 31471 */ // Label 770: @31471
11078 /* 31471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 771*/ GIMT_Encode4(31491), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3152 //
11079 /* 31478 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src
11080 /* 31478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11081 /* 31481 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11082 /* 31483 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11083 /* 31485 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11084 /* 31490 */ // GIR_Coverage, 3152,
11085 /* 31490 */ GIR_EraseRootFromParent_Done,
11086 /* 31491 */ // Label 771: @31491
11087 /* 31491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 772*/ GIMT_Encode4(31516), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3223 //
11088 /* 31498 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
11089 /* 31498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11090 /* 31501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11091 /* 31503 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11092 /* 31505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11093 /* 31508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11094 /* 31514 */ GIR_RootConstrainSelectedInstOperands,
11095 /* 31515 */ // GIR_Coverage, 3223,
11096 /* 31515 */ GIR_EraseRootFromParent_Done,
11097 /* 31516 */ // Label 772: @31516
11098 /* 31516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 773*/ GIMT_Encode4(31541), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3224 //
11099 /* 31523 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
11100 /* 31523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11101 /* 31526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11102 /* 31528 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11103 /* 31530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11104 /* 31533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11105 /* 31539 */ GIR_RootConstrainSelectedInstOperands,
11106 /* 31540 */ // GIR_Coverage, 3224,
11107 /* 31540 */ GIR_EraseRootFromParent_Done,
11108 /* 31541 */ // Label 773: @31541
11109 /* 31541 */ GIM_Reject,
11110 /* 31542 */ // Label 769: @31542
11111 /* 31542 */ GIM_Reject,
11112 /* 31543 */ // Label 766: @31543
11113 /* 31543 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(31647),
11114 /* 31548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11115 /* 31552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11116 /* 31556 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 775*/ GIMT_Encode4(31576), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3155 //
11117 /* 31563 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src
11118 /* 31563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11119 /* 31566 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11120 /* 31568 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11121 /* 31570 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11122 /* 31575 */ // GIR_Coverage, 3155,
11123 /* 31575 */ GIR_EraseRootFromParent_Done,
11124 /* 31576 */ // Label 775: @31576
11125 /* 31576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 776*/ GIMT_Encode4(31596), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3156 //
11126 /* 31583 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src
11127 /* 31583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11128 /* 31586 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11129 /* 31588 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11130 /* 31590 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11131 /* 31595 */ // GIR_Coverage, 3156,
11132 /* 31595 */ GIR_EraseRootFromParent_Done,
11133 /* 31596 */ // Label 776: @31596
11134 /* 31596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 777*/ GIMT_Encode4(31621), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3227 //
11135 /* 31603 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
11136 /* 31603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11137 /* 31606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11138 /* 31608 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11139 /* 31610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11140 /* 31613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11141 /* 31619 */ GIR_RootConstrainSelectedInstOperands,
11142 /* 31620 */ // GIR_Coverage, 3227,
11143 /* 31620 */ GIR_EraseRootFromParent_Done,
11144 /* 31621 */ // Label 777: @31621
11145 /* 31621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 778*/ GIMT_Encode4(31646), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3228 //
11146 /* 31628 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
11147 /* 31628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11148 /* 31631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11149 /* 31633 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11150 /* 31635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11151 /* 31638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11152 /* 31644 */ GIR_RootConstrainSelectedInstOperands,
11153 /* 31645 */ // GIR_Coverage, 3228,
11154 /* 31645 */ GIR_EraseRootFromParent_Done,
11155 /* 31646 */ // Label 778: @31646
11156 /* 31646 */ GIM_Reject,
11157 /* 31647 */ // Label 774: @31647
11158 /* 31647 */ GIM_Reject,
11159 /* 31648 */ // Label 767: @31648
11160 /* 31648 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(31752),
11161 /* 31653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11162 /* 31657 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11163 /* 31661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 780*/ GIMT_Encode4(31681), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3153 //
11164 /* 31668 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src
11165 /* 31668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11166 /* 31671 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11167 /* 31673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11168 /* 31675 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11169 /* 31680 */ // GIR_Coverage, 3153,
11170 /* 31680 */ GIR_EraseRootFromParent_Done,
11171 /* 31681 */ // Label 780: @31681
11172 /* 31681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 781*/ GIMT_Encode4(31701), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3154 //
11173 /* 31688 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src
11174 /* 31688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11175 /* 31691 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11176 /* 31693 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11177 /* 31695 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11178 /* 31700 */ // GIR_Coverage, 3154,
11179 /* 31700 */ GIR_EraseRootFromParent_Done,
11180 /* 31701 */ // Label 781: @31701
11181 /* 31701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 782*/ GIMT_Encode4(31726), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3225 //
11182 /* 31708 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
11183 /* 31708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11184 /* 31711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11185 /* 31713 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11186 /* 31715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11187 /* 31718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11188 /* 31724 */ GIR_RootConstrainSelectedInstOperands,
11189 /* 31725 */ // GIR_Coverage, 3225,
11190 /* 31725 */ GIR_EraseRootFromParent_Done,
11191 /* 31726 */ // Label 782: @31726
11192 /* 31726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 783*/ GIMT_Encode4(31751), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3226 //
11193 /* 31733 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
11194 /* 31733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11195 /* 31736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11196 /* 31738 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11197 /* 31740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11198 /* 31743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11199 /* 31749 */ GIR_RootConstrainSelectedInstOperands,
11200 /* 31750 */ // GIR_Coverage, 3226,
11201 /* 31750 */ GIR_EraseRootFromParent_Done,
11202 /* 31751 */ // Label 783: @31751
11203 /* 31751 */ GIM_Reject,
11204 /* 31752 */ // Label 779: @31752
11205 /* 31752 */ GIM_Reject,
11206 /* 31753 */ // Label 768: @31753
11207 /* 31753 */ GIM_Reject,
11208 /* 31754 */ // Label 722: @31754
11209 /* 31754 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 787*/ GIMT_Encode4(32534),
11210 /* 31765 */ /*GILLT_v8s16*//*Label 784*/ GIMT_Encode4(31781), GIMT_Encode4(0),
11211 /* 31773 */ /*GILLT_v4s32*//*Label 785*/ GIMT_Encode4(32032),
11212 /* 31777 */ /*GILLT_v2s64*//*Label 786*/ GIMT_Encode4(32283),
11213 /* 31781 */ // Label 784: @31781
11214 /* 31781 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(31885),
11215 /* 31786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11216 /* 31790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11217 /* 31794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 789*/ GIMT_Encode4(31814), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3191 //
11218 /* 31801 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src
11219 /* 31801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11220 /* 31804 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11221 /* 31806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11222 /* 31808 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11223 /* 31813 */ // GIR_Coverage, 3191,
11224 /* 31813 */ GIR_EraseRootFromParent_Done,
11225 /* 31814 */ // Label 789: @31814
11226 /* 31814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 790*/ GIMT_Encode4(31834), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3192 //
11227 /* 31821 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src
11228 /* 31821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11229 /* 31824 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11230 /* 31826 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11231 /* 31828 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11232 /* 31833 */ // GIR_Coverage, 3192,
11233 /* 31833 */ GIR_EraseRootFromParent_Done,
11234 /* 31834 */ // Label 790: @31834
11235 /* 31834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 791*/ GIMT_Encode4(31859), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3263 //
11236 /* 31841 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
11237 /* 31841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11238 /* 31844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11239 /* 31846 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11240 /* 31848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11241 /* 31851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11242 /* 31857 */ GIR_RootConstrainSelectedInstOperands,
11243 /* 31858 */ // GIR_Coverage, 3263,
11244 /* 31858 */ GIR_EraseRootFromParent_Done,
11245 /* 31859 */ // Label 791: @31859
11246 /* 31859 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 792*/ GIMT_Encode4(31884), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3264 //
11247 /* 31866 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
11248 /* 31866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11249 /* 31869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11250 /* 31871 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11251 /* 31873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11252 /* 31876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11253 /* 31882 */ GIR_RootConstrainSelectedInstOperands,
11254 /* 31883 */ // GIR_Coverage, 3264,
11255 /* 31883 */ GIR_EraseRootFromParent_Done,
11256 /* 31884 */ // Label 792: @31884
11257 /* 31884 */ GIM_Reject,
11258 /* 31885 */ // Label 788: @31885
11259 /* 31885 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(32031),
11260 /* 31890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11261 /* 31894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11262 /* 31898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 794*/ GIMT_Encode4(31918), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5858 //
11263 /* 31905 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src
11264 /* 31905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11265 /* 31908 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11266 /* 31910 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11267 /* 31912 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11268 /* 31917 */ // GIR_Coverage, 5858,
11269 /* 31917 */ GIR_EraseRootFromParent_Done,
11270 /* 31918 */ // Label 794: @31918
11271 /* 31918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 795*/ GIMT_Encode4(31938), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5859 //
11272 /* 31925 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src
11273 /* 31925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11274 /* 31928 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11275 /* 31930 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11276 /* 31932 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11277 /* 31937 */ // GIR_Coverage, 5859,
11278 /* 31937 */ GIR_EraseRootFromParent_Done,
11279 /* 31938 */ // Label 795: @31938
11280 /* 31938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 796*/ GIMT_Encode4(31984), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5894 //
11281 /* 31945 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
11282 /* 31945 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11283 /* 31948 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11284 /* 31952 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11285 /* 31957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11286 /* 31960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11287 /* 31962 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11288 /* 31964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11289 /* 31967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11290 /* 31973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11291 /* 31979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11292 /* 31982 */ GIR_RootConstrainSelectedInstOperands,
11293 /* 31983 */ // GIR_Coverage, 5894,
11294 /* 31983 */ GIR_EraseRootFromParent_Done,
11295 /* 31984 */ // Label 796: @31984
11296 /* 31984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 797*/ GIMT_Encode4(32030), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5895 //
11297 /* 31991 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
11298 /* 31991 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11299 /* 31994 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11300 /* 31998 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11301 /* 32003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11302 /* 32006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11303 /* 32008 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11304 /* 32010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11305 /* 32013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11306 /* 32019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11307 /* 32025 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11308 /* 32028 */ GIR_RootConstrainSelectedInstOperands,
11309 /* 32029 */ // GIR_Coverage, 5895,
11310 /* 32029 */ GIR_EraseRootFromParent_Done,
11311 /* 32030 */ // Label 797: @32030
11312 /* 32030 */ GIM_Reject,
11313 /* 32031 */ // Label 793: @32031
11314 /* 32031 */ GIM_Reject,
11315 /* 32032 */ // Label 785: @32032
11316 /* 32032 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(32136),
11317 /* 32037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11318 /* 32041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11319 /* 32045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 799*/ GIMT_Encode4(32065), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3189 //
11320 /* 32052 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src
11321 /* 32052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11322 /* 32055 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11323 /* 32057 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11324 /* 32059 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11325 /* 32064 */ // GIR_Coverage, 3189,
11326 /* 32064 */ GIR_EraseRootFromParent_Done,
11327 /* 32065 */ // Label 799: @32065
11328 /* 32065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 800*/ GIMT_Encode4(32085), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3190 //
11329 /* 32072 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src
11330 /* 32072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11331 /* 32075 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11332 /* 32077 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11333 /* 32079 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11334 /* 32084 */ // GIR_Coverage, 3190,
11335 /* 32084 */ GIR_EraseRootFromParent_Done,
11336 /* 32085 */ // Label 800: @32085
11337 /* 32085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 801*/ GIMT_Encode4(32110), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3261 //
11338 /* 32092 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
11339 /* 32092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11340 /* 32095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11341 /* 32097 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11342 /* 32099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11343 /* 32102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11344 /* 32108 */ GIR_RootConstrainSelectedInstOperands,
11345 /* 32109 */ // GIR_Coverage, 3261,
11346 /* 32109 */ GIR_EraseRootFromParent_Done,
11347 /* 32110 */ // Label 801: @32110
11348 /* 32110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 802*/ GIMT_Encode4(32135), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3262 //
11349 /* 32117 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
11350 /* 32117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11351 /* 32120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11352 /* 32122 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11353 /* 32124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11354 /* 32127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11355 /* 32133 */ GIR_RootConstrainSelectedInstOperands,
11356 /* 32134 */ // GIR_Coverage, 3262,
11357 /* 32134 */ GIR_EraseRootFromParent_Done,
11358 /* 32135 */ // Label 802: @32135
11359 /* 32135 */ GIM_Reject,
11360 /* 32136 */ // Label 798: @32136
11361 /* 32136 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(32282),
11362 /* 32141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11363 /* 32145 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11364 /* 32149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 804*/ GIMT_Encode4(32169), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5856 //
11365 /* 32156 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src
11366 /* 32156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11367 /* 32159 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11368 /* 32161 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11369 /* 32163 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11370 /* 32168 */ // GIR_Coverage, 5856,
11371 /* 32168 */ GIR_EraseRootFromParent_Done,
11372 /* 32169 */ // Label 804: @32169
11373 /* 32169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 805*/ GIMT_Encode4(32189), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5857 //
11374 /* 32176 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src
11375 /* 32176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11376 /* 32179 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11377 /* 32181 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11378 /* 32183 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11379 /* 32188 */ // GIR_Coverage, 5857,
11380 /* 32188 */ GIR_EraseRootFromParent_Done,
11381 /* 32189 */ // Label 805: @32189
11382 /* 32189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 806*/ GIMT_Encode4(32235), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5892 //
11383 /* 32196 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
11384 /* 32196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11385 /* 32199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11386 /* 32203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11387 /* 32208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
11388 /* 32211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11389 /* 32213 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11390 /* 32215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11391 /* 32218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11392 /* 32224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11393 /* 32230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11394 /* 32233 */ GIR_RootConstrainSelectedInstOperands,
11395 /* 32234 */ // GIR_Coverage, 5892,
11396 /* 32234 */ GIR_EraseRootFromParent_Done,
11397 /* 32235 */ // Label 806: @32235
11398 /* 32235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 807*/ GIMT_Encode4(32281), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5893 //
11399 /* 32242 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
11400 /* 32242 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11401 /* 32245 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11402 /* 32249 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11403 /* 32254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
11404 /* 32257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11405 /* 32259 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11406 /* 32261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11407 /* 32264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11408 /* 32270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11409 /* 32276 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11410 /* 32279 */ GIR_RootConstrainSelectedInstOperands,
11411 /* 32280 */ // GIR_Coverage, 5893,
11412 /* 32280 */ GIR_EraseRootFromParent_Done,
11413 /* 32281 */ // Label 807: @32281
11414 /* 32281 */ GIM_Reject,
11415 /* 32282 */ // Label 803: @32282
11416 /* 32282 */ GIM_Reject,
11417 /* 32283 */ // Label 786: @32283
11418 /* 32283 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(32387),
11419 /* 32288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11420 /* 32292 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11421 /* 32296 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 809*/ GIMT_Encode4(32316), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3187 //
11422 /* 32303 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src
11423 /* 32303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11424 /* 32306 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11425 /* 32308 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11426 /* 32310 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11427 /* 32315 */ // GIR_Coverage, 3187,
11428 /* 32315 */ GIR_EraseRootFromParent_Done,
11429 /* 32316 */ // Label 809: @32316
11430 /* 32316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 810*/ GIMT_Encode4(32336), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3188 //
11431 /* 32323 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src
11432 /* 32323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11433 /* 32326 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11434 /* 32328 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11435 /* 32330 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11436 /* 32335 */ // GIR_Coverage, 3188,
11437 /* 32335 */ GIR_EraseRootFromParent_Done,
11438 /* 32336 */ // Label 810: @32336
11439 /* 32336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 811*/ GIMT_Encode4(32361), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3259 //
11440 /* 32343 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
11441 /* 32343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
11442 /* 32346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11443 /* 32348 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11444 /* 32350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11445 /* 32353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11446 /* 32359 */ GIR_RootConstrainSelectedInstOperands,
11447 /* 32360 */ // GIR_Coverage, 3259,
11448 /* 32360 */ GIR_EraseRootFromParent_Done,
11449 /* 32361 */ // Label 811: @32361
11450 /* 32361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 812*/ GIMT_Encode4(32386), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3260 //
11451 /* 32368 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
11452 /* 32368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
11453 /* 32371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11454 /* 32373 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11455 /* 32375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11456 /* 32378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11457 /* 32384 */ GIR_RootConstrainSelectedInstOperands,
11458 /* 32385 */ // GIR_Coverage, 3260,
11459 /* 32385 */ GIR_EraseRootFromParent_Done,
11460 /* 32386 */ // Label 812: @32386
11461 /* 32386 */ GIM_Reject,
11462 /* 32387 */ // Label 808: @32387
11463 /* 32387 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(32533),
11464 /* 32392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11465 /* 32396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11466 /* 32400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 814*/ GIMT_Encode4(32420), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5854 //
11467 /* 32407 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src
11468 /* 32407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11469 /* 32410 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11470 /* 32412 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11471 /* 32414 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11472 /* 32419 */ // GIR_Coverage, 5854,
11473 /* 32419 */ GIR_EraseRootFromParent_Done,
11474 /* 32420 */ // Label 814: @32420
11475 /* 32420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 815*/ GIMT_Encode4(32440), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5855 //
11476 /* 32427 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src
11477 /* 32427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11478 /* 32430 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11479 /* 32432 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11480 /* 32434 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11481 /* 32439 */ // GIR_Coverage, 5855,
11482 /* 32439 */ GIR_EraseRootFromParent_Done,
11483 /* 32440 */ // Label 815: @32440
11484 /* 32440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 816*/ GIMT_Encode4(32486), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5890 //
11485 /* 32447 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
11486 /* 32447 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11487 /* 32450 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11488 /* 32454 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11489 /* 32459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
11490 /* 32462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11491 /* 32464 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11492 /* 32466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11493 /* 32469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11494 /* 32475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11495 /* 32481 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11496 /* 32484 */ GIR_RootConstrainSelectedInstOperands,
11497 /* 32485 */ // GIR_Coverage, 5890,
11498 /* 32485 */ GIR_EraseRootFromParent_Done,
11499 /* 32486 */ // Label 816: @32486
11500 /* 32486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 817*/ GIMT_Encode4(32532), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5891 //
11501 /* 32493 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
11502 /* 32493 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11503 /* 32496 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11504 /* 32500 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11505 /* 32505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
11506 /* 32508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11507 /* 32510 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11508 /* 32512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11509 /* 32515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11510 /* 32521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11511 /* 32527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11512 /* 32530 */ GIR_RootConstrainSelectedInstOperands,
11513 /* 32531 */ // GIR_Coverage, 5891,
11514 /* 32531 */ GIR_EraseRootFromParent_Done,
11515 /* 32532 */ // Label 817: @32532
11516 /* 32532 */ GIM_Reject,
11517 /* 32533 */ // Label 813: @32533
11518 /* 32533 */ GIM_Reject,
11519 /* 32534 */ // Label 787: @32534
11520 /* 32534 */ GIM_Reject,
11521 /* 32535 */ // Label 723: @32535
11522 /* 32535 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 822*/ GIMT_Encode4(33136),
11523 /* 32546 */ /*GILLT_s64*//*Label 818*/ GIMT_Encode4(32586), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
11524 /* 32566 */ /*GILLT_v8s8*//*Label 819*/ GIMT_Encode4(32781), GIMT_Encode4(0),
11525 /* 32574 */ /*GILLT_v4s16*//*Label 820*/ GIMT_Encode4(32886), GIMT_Encode4(0),
11526 /* 32582 */ /*GILLT_v2s32*//*Label 821*/ GIMT_Encode4(32941),
11527 /* 32586 */ // Label 818: @32586
11528 /* 32586 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(32780),
11529 /* 32591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11530 /* 32595 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11531 /* 32599 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 824*/ GIMT_Encode4(32619), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3141 //
11532 /* 32606 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src
11533 /* 32606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11534 /* 32609 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11535 /* 32611 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11536 /* 32613 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11537 /* 32618 */ // GIR_Coverage, 3141,
11538 /* 32618 */ GIR_EraseRootFromParent_Done,
11539 /* 32619 */ // Label 824: @32619
11540 /* 32619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 825*/ GIMT_Encode4(32639), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3142 //
11541 /* 32626 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src
11542 /* 32626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11543 /* 32629 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11544 /* 32631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11545 /* 32633 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11546 /* 32638 */ // GIR_Coverage, 3142,
11547 /* 32638 */ GIR_EraseRootFromParent_Done,
11548 /* 32639 */ // Label 825: @32639
11549 /* 32639 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 826*/ GIMT_Encode4(32659), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3146 //
11550 /* 32646 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src
11551 /* 32646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11552 /* 32649 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11553 /* 32651 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11554 /* 32653 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11555 /* 32658 */ // GIR_Coverage, 3146,
11556 /* 32658 */ GIR_EraseRootFromParent_Done,
11557 /* 32659 */ // Label 826: @32659
11558 /* 32659 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 827*/ GIMT_Encode4(32679), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3147 //
11559 /* 32666 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src
11560 /* 32666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11561 /* 32669 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11562 /* 32671 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11563 /* 32673 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11564 /* 32678 */ // GIR_Coverage, 3147,
11565 /* 32678 */ GIR_EraseRootFromParent_Done,
11566 /* 32679 */ // Label 827: @32679
11567 /* 32679 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 828*/ GIMT_Encode4(32704), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3213 //
11568 /* 32686 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
11569 /* 32686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11570 /* 32689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11571 /* 32691 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11572 /* 32693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11573 /* 32696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11574 /* 32702 */ GIR_RootConstrainSelectedInstOperands,
11575 /* 32703 */ // GIR_Coverage, 3213,
11576 /* 32703 */ GIR_EraseRootFromParent_Done,
11577 /* 32704 */ // Label 828: @32704
11578 /* 32704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 829*/ GIMT_Encode4(32729), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3214 //
11579 /* 32711 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
11580 /* 32711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11581 /* 32714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11582 /* 32716 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11583 /* 32718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11584 /* 32721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11585 /* 32727 */ GIR_RootConstrainSelectedInstOperands,
11586 /* 32728 */ // GIR_Coverage, 3214,
11587 /* 32728 */ GIR_EraseRootFromParent_Done,
11588 /* 32729 */ // Label 829: @32729
11589 /* 32729 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 830*/ GIMT_Encode4(32754), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3218 //
11590 /* 32736 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
11591 /* 32736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11592 /* 32739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11593 /* 32741 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11594 /* 32743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11595 /* 32746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11596 /* 32752 */ GIR_RootConstrainSelectedInstOperands,
11597 /* 32753 */ // GIR_Coverage, 3218,
11598 /* 32753 */ GIR_EraseRootFromParent_Done,
11599 /* 32754 */ // Label 830: @32754
11600 /* 32754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 831*/ GIMT_Encode4(32779), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3219 //
11601 /* 32761 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
11602 /* 32761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11603 /* 32764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11604 /* 32766 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11605 /* 32768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11606 /* 32771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11607 /* 32777 */ GIR_RootConstrainSelectedInstOperands,
11608 /* 32778 */ // GIR_Coverage, 3219,
11609 /* 32778 */ GIR_EraseRootFromParent_Done,
11610 /* 32779 */ // Label 831: @32779
11611 /* 32779 */ GIM_Reject,
11612 /* 32780 */ // Label 823: @32780
11613 /* 32780 */ GIM_Reject,
11614 /* 32781 */ // Label 819: @32781
11615 /* 32781 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(32885),
11616 /* 32786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11617 /* 32790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11618 /* 32794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 833*/ GIMT_Encode4(32814), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3145 //
11619 /* 32801 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src
11620 /* 32801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11621 /* 32804 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11622 /* 32806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11623 /* 32808 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11624 /* 32813 */ // GIR_Coverage, 3145,
11625 /* 32813 */ GIR_EraseRootFromParent_Done,
11626 /* 32814 */ // Label 833: @32814
11627 /* 32814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 834*/ GIMT_Encode4(32834), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3150 //
11628 /* 32821 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src
11629 /* 32821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11630 /* 32824 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11631 /* 32826 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11632 /* 32828 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11633 /* 32833 */ // GIR_Coverage, 3150,
11634 /* 32833 */ GIR_EraseRootFromParent_Done,
11635 /* 32834 */ // Label 834: @32834
11636 /* 32834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 835*/ GIMT_Encode4(32859), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3217 //
11637 /* 32841 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
11638 /* 32841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11639 /* 32844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11640 /* 32846 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11641 /* 32848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11642 /* 32851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11643 /* 32857 */ GIR_RootConstrainSelectedInstOperands,
11644 /* 32858 */ // GIR_Coverage, 3217,
11645 /* 32858 */ GIR_EraseRootFromParent_Done,
11646 /* 32859 */ // Label 835: @32859
11647 /* 32859 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 836*/ GIMT_Encode4(32884), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3222 //
11648 /* 32866 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
11649 /* 32866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11650 /* 32869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11651 /* 32871 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11652 /* 32873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11653 /* 32876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11654 /* 32882 */ GIR_RootConstrainSelectedInstOperands,
11655 /* 32883 */ // GIR_Coverage, 3222,
11656 /* 32883 */ GIR_EraseRootFromParent_Done,
11657 /* 32884 */ // Label 836: @32884
11658 /* 32884 */ GIM_Reject,
11659 /* 32885 */ // Label 832: @32885
11660 /* 32885 */ GIM_Reject,
11661 /* 32886 */ // Label 820: @32886
11662 /* 32886 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(32940),
11663 /* 32891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11664 /* 32895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11665 /* 32899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 838*/ GIMT_Encode4(32919), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3113 //
11666 /* 32906 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src
11667 /* 32906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11668 /* 32909 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11669 /* 32911 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11670 /* 32913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11671 /* 32918 */ // GIR_Coverage, 3113,
11672 /* 32918 */ GIR_EraseRootFromParent_Done,
11673 /* 32919 */ // Label 838: @32919
11674 /* 32919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 839*/ GIMT_Encode4(32939), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3114 //
11675 /* 32926 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src
11676 /* 32926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11677 /* 32929 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11678 /* 32931 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11679 /* 32933 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11680 /* 32938 */ // GIR_Coverage, 3114,
11681 /* 32938 */ GIR_EraseRootFromParent_Done,
11682 /* 32939 */ // Label 839: @32939
11683 /* 32939 */ GIM_Reject,
11684 /* 32940 */ // Label 837: @32940
11685 /* 32940 */ GIM_Reject,
11686 /* 32941 */ // Label 821: @32941
11687 /* 32941 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(33135),
11688 /* 32946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11689 /* 32950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11690 /* 32954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 841*/ GIMT_Encode4(32974), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3143 //
11691 /* 32961 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src
11692 /* 32961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11693 /* 32964 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11694 /* 32966 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11695 /* 32968 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11696 /* 32973 */ // GIR_Coverage, 3143,
11697 /* 32973 */ GIR_EraseRootFromParent_Done,
11698 /* 32974 */ // Label 841: @32974
11699 /* 32974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 842*/ GIMT_Encode4(32994), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3144 //
11700 /* 32981 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src
11701 /* 32981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11702 /* 32984 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11703 /* 32986 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11704 /* 32988 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11705 /* 32993 */ // GIR_Coverage, 3144,
11706 /* 32993 */ GIR_EraseRootFromParent_Done,
11707 /* 32994 */ // Label 842: @32994
11708 /* 32994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 843*/ GIMT_Encode4(33014), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3148 //
11709 /* 33001 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src
11710 /* 33001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11711 /* 33004 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11712 /* 33006 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11713 /* 33008 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11714 /* 33013 */ // GIR_Coverage, 3148,
11715 /* 33013 */ GIR_EraseRootFromParent_Done,
11716 /* 33014 */ // Label 843: @33014
11717 /* 33014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 844*/ GIMT_Encode4(33034), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3149 //
11718 /* 33021 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src
11719 /* 33021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11720 /* 33024 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11721 /* 33026 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11722 /* 33028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11723 /* 33033 */ // GIR_Coverage, 3149,
11724 /* 33033 */ GIR_EraseRootFromParent_Done,
11725 /* 33034 */ // Label 844: @33034
11726 /* 33034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 845*/ GIMT_Encode4(33059), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3215 //
11727 /* 33041 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
11728 /* 33041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11729 /* 33044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11730 /* 33046 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11731 /* 33048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11732 /* 33051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11733 /* 33057 */ GIR_RootConstrainSelectedInstOperands,
11734 /* 33058 */ // GIR_Coverage, 3215,
11735 /* 33058 */ GIR_EraseRootFromParent_Done,
11736 /* 33059 */ // Label 845: @33059
11737 /* 33059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 846*/ GIMT_Encode4(33084), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3216 //
11738 /* 33066 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
11739 /* 33066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11740 /* 33069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11741 /* 33071 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11742 /* 33073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11743 /* 33076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11744 /* 33082 */ GIR_RootConstrainSelectedInstOperands,
11745 /* 33083 */ // GIR_Coverage, 3216,
11746 /* 33083 */ GIR_EraseRootFromParent_Done,
11747 /* 33084 */ // Label 846: @33084
11748 /* 33084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 847*/ GIMT_Encode4(33109), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3220 //
11749 /* 33091 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
11750 /* 33091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11751 /* 33094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11752 /* 33096 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11753 /* 33098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11754 /* 33101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11755 /* 33107 */ GIR_RootConstrainSelectedInstOperands,
11756 /* 33108 */ // GIR_Coverage, 3220,
11757 /* 33108 */ GIR_EraseRootFromParent_Done,
11758 /* 33109 */ // Label 847: @33109
11759 /* 33109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 848*/ GIMT_Encode4(33134), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3221 //
11760 /* 33116 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
11761 /* 33116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11762 /* 33119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11763 /* 33121 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11764 /* 33123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11765 /* 33126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11766 /* 33132 */ GIR_RootConstrainSelectedInstOperands,
11767 /* 33133 */ // GIR_Coverage, 3221,
11768 /* 33133 */ GIR_EraseRootFromParent_Done,
11769 /* 33134 */ // Label 848: @33134
11770 /* 33134 */ GIM_Reject,
11771 /* 33135 */ // Label 840: @33135
11772 /* 33135 */ GIM_Reject,
11773 /* 33136 */ // Label 822: @33136
11774 /* 33136 */ GIM_Reject,
11775 /* 33137 */ // Label 724: @33137
11776 /* 33137 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 853*/ GIMT_Encode4(34478),
11777 /* 33148 */ /*GILLT_v16s8*//*Label 849*/ GIMT_Encode4(33172), GIMT_Encode4(0),
11778 /* 33156 */ /*GILLT_v8s16*//*Label 850*/ GIMT_Encode4(33423), GIMT_Encode4(0),
11779 /* 33164 */ /*GILLT_v4s32*//*Label 851*/ GIMT_Encode4(33532),
11780 /* 33168 */ /*GILLT_v2s64*//*Label 852*/ GIMT_Encode4(34005),
11781 /* 33172 */ // Label 849: @33172
11782 /* 33172 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(33276),
11783 /* 33177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11784 /* 33181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11785 /* 33185 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 855*/ GIMT_Encode4(33205), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3181 //
11786 /* 33192 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src
11787 /* 33192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11788 /* 33195 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11789 /* 33197 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11790 /* 33199 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11791 /* 33204 */ // GIR_Coverage, 3181,
11792 /* 33204 */ GIR_EraseRootFromParent_Done,
11793 /* 33205 */ // Label 855: @33205
11794 /* 33205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 856*/ GIMT_Encode4(33225), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3186 //
11795 /* 33212 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src
11796 /* 33212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11797 /* 33215 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11798 /* 33217 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11799 /* 33219 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11800 /* 33224 */ // GIR_Coverage, 3186,
11801 /* 33224 */ GIR_EraseRootFromParent_Done,
11802 /* 33225 */ // Label 856: @33225
11803 /* 33225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 857*/ GIMT_Encode4(33250), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3253 //
11804 /* 33232 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
11805 /* 33232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11806 /* 33235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11807 /* 33237 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11808 /* 33239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11809 /* 33242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11810 /* 33248 */ GIR_RootConstrainSelectedInstOperands,
11811 /* 33249 */ // GIR_Coverage, 3253,
11812 /* 33249 */ GIR_EraseRootFromParent_Done,
11813 /* 33250 */ // Label 857: @33250
11814 /* 33250 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 858*/ GIMT_Encode4(33275), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3258 //
11815 /* 33257 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
11816 /* 33257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11817 /* 33260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11818 /* 33262 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11819 /* 33264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11820 /* 33267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11821 /* 33273 */ GIR_RootConstrainSelectedInstOperands,
11822 /* 33274 */ // GIR_Coverage, 3258,
11823 /* 33274 */ GIR_EraseRootFromParent_Done,
11824 /* 33275 */ // Label 858: @33275
11825 /* 33275 */ GIM_Reject,
11826 /* 33276 */ // Label 854: @33276
11827 /* 33276 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(33422),
11828 /* 33281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11829 /* 33285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11830 /* 33289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 860*/ GIMT_Encode4(33309), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5848 //
11831 /* 33296 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src
11832 /* 33296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11833 /* 33299 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11834 /* 33301 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11835 /* 33303 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11836 /* 33308 */ // GIR_Coverage, 5848,
11837 /* 33308 */ GIR_EraseRootFromParent_Done,
11838 /* 33309 */ // Label 860: @33309
11839 /* 33309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 861*/ GIMT_Encode4(33329), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5853 //
11840 /* 33316 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src
11841 /* 33316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11842 /* 33319 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11843 /* 33321 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11844 /* 33323 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11845 /* 33328 */ // GIR_Coverage, 5853,
11846 /* 33328 */ GIR_EraseRootFromParent_Done,
11847 /* 33329 */ // Label 861: @33329
11848 /* 33329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 862*/ GIMT_Encode4(33375), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5884 //
11849 /* 33336 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
11850 /* 33336 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11851 /* 33339 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11852 /* 33343 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11853 /* 33348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11854 /* 33351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11855 /* 33353 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11856 /* 33355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11857 /* 33358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11858 /* 33364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11859 /* 33370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11860 /* 33373 */ GIR_RootConstrainSelectedInstOperands,
11861 /* 33374 */ // GIR_Coverage, 5884,
11862 /* 33374 */ GIR_EraseRootFromParent_Done,
11863 /* 33375 */ // Label 862: @33375
11864 /* 33375 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 863*/ GIMT_Encode4(33421), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5889 //
11865 /* 33382 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
11866 /* 33382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11867 /* 33385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11868 /* 33389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11869 /* 33394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11870 /* 33397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11871 /* 33399 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11872 /* 33401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11873 /* 33404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11874 /* 33410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11875 /* 33416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11876 /* 33419 */ GIR_RootConstrainSelectedInstOperands,
11877 /* 33420 */ // GIR_Coverage, 5889,
11878 /* 33420 */ GIR_EraseRootFromParent_Done,
11879 /* 33421 */ // Label 863: @33421
11880 /* 33421 */ GIM_Reject,
11881 /* 33422 */ // Label 859: @33422
11882 /* 33422 */ GIM_Reject,
11883 /* 33423 */ // Label 850: @33423
11884 /* 33423 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(33477),
11885 /* 33428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11886 /* 33432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11887 /* 33436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 865*/ GIMT_Encode4(33456), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3119 //
11888 /* 33443 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src
11889 /* 33443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11890 /* 33446 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11891 /* 33448 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11892 /* 33450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11893 /* 33455 */ // GIR_Coverage, 3119,
11894 /* 33455 */ GIR_EraseRootFromParent_Done,
11895 /* 33456 */ // Label 865: @33456
11896 /* 33456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 866*/ GIMT_Encode4(33476), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3120 //
11897 /* 33463 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src
11898 /* 33463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11899 /* 33466 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11900 /* 33468 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11901 /* 33470 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11902 /* 33475 */ // GIR_Coverage, 3120,
11903 /* 33475 */ GIR_EraseRootFromParent_Done,
11904 /* 33476 */ // Label 866: @33476
11905 /* 33476 */ GIM_Reject,
11906 /* 33477 */ // Label 864: @33477
11907 /* 33477 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(33531),
11908 /* 33482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11909 /* 33486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11910 /* 33490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 868*/ GIMT_Encode4(33510), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5822 //
11911 /* 33497 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src
11912 /* 33497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11913 /* 33500 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11914 /* 33502 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11915 /* 33504 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11916 /* 33509 */ // GIR_Coverage, 5822,
11917 /* 33509 */ GIR_EraseRootFromParent_Done,
11918 /* 33510 */ // Label 868: @33510
11919 /* 33510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 869*/ GIMT_Encode4(33530), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5823 //
11920 /* 33517 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src
11921 /* 33517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11922 /* 33520 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11923 /* 33522 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11924 /* 33524 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11925 /* 33529 */ // GIR_Coverage, 5823,
11926 /* 33529 */ GIR_EraseRootFromParent_Done,
11927 /* 33530 */ // Label 869: @33530
11928 /* 33530 */ GIM_Reject,
11929 /* 33531 */ // Label 867: @33531
11930 /* 33531 */ GIM_Reject,
11931 /* 33532 */ // Label 851: @33532
11932 /* 33532 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(33726),
11933 /* 33537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11934 /* 33541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11935 /* 33545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 871*/ GIMT_Encode4(33565), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3179 //
11936 /* 33552 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src
11937 /* 33552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11938 /* 33555 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11939 /* 33557 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11940 /* 33559 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11941 /* 33564 */ // GIR_Coverage, 3179,
11942 /* 33564 */ GIR_EraseRootFromParent_Done,
11943 /* 33565 */ // Label 871: @33565
11944 /* 33565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 872*/ GIMT_Encode4(33585), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3180 //
11945 /* 33572 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src
11946 /* 33572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11947 /* 33575 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11948 /* 33577 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11949 /* 33579 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11950 /* 33584 */ // GIR_Coverage, 3180,
11951 /* 33584 */ GIR_EraseRootFromParent_Done,
11952 /* 33585 */ // Label 872: @33585
11953 /* 33585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 873*/ GIMT_Encode4(33605), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3184 //
11954 /* 33592 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src
11955 /* 33592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11956 /* 33595 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11957 /* 33597 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11958 /* 33599 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11959 /* 33604 */ // GIR_Coverage, 3184,
11960 /* 33604 */ GIR_EraseRootFromParent_Done,
11961 /* 33605 */ // Label 873: @33605
11962 /* 33605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 874*/ GIMT_Encode4(33625), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3185 //
11963 /* 33612 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src
11964 /* 33612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11965 /* 33615 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11966 /* 33617 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11967 /* 33619 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11968 /* 33624 */ // GIR_Coverage, 3185,
11969 /* 33624 */ GIR_EraseRootFromParent_Done,
11970 /* 33625 */ // Label 874: @33625
11971 /* 33625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 875*/ GIMT_Encode4(33650), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3251 //
11972 /* 33632 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
11973 /* 33632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11974 /* 33635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11975 /* 33637 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11976 /* 33639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11977 /* 33642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11978 /* 33648 */ GIR_RootConstrainSelectedInstOperands,
11979 /* 33649 */ // GIR_Coverage, 3251,
11980 /* 33649 */ GIR_EraseRootFromParent_Done,
11981 /* 33650 */ // Label 875: @33650
11982 /* 33650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 876*/ GIMT_Encode4(33675), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3252 //
11983 /* 33657 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
11984 /* 33657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11985 /* 33660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11986 /* 33662 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11987 /* 33664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11988 /* 33667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11989 /* 33673 */ GIR_RootConstrainSelectedInstOperands,
11990 /* 33674 */ // GIR_Coverage, 3252,
11991 /* 33674 */ GIR_EraseRootFromParent_Done,
11992 /* 33675 */ // Label 876: @33675
11993 /* 33675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 877*/ GIMT_Encode4(33700), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3256 //
11994 /* 33682 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
11995 /* 33682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11996 /* 33685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11997 /* 33687 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11998 /* 33689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11999 /* 33692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12000 /* 33698 */ GIR_RootConstrainSelectedInstOperands,
12001 /* 33699 */ // GIR_Coverage, 3256,
12002 /* 33699 */ GIR_EraseRootFromParent_Done,
12003 /* 33700 */ // Label 877: @33700
12004 /* 33700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 878*/ GIMT_Encode4(33725), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3257 //
12005 /* 33707 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
12006 /* 33707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12007 /* 33710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12008 /* 33712 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12009 /* 33714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12010 /* 33717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12011 /* 33723 */ GIR_RootConstrainSelectedInstOperands,
12012 /* 33724 */ // GIR_Coverage, 3257,
12013 /* 33724 */ GIR_EraseRootFromParent_Done,
12014 /* 33725 */ // Label 878: @33725
12015 /* 33725 */ GIM_Reject,
12016 /* 33726 */ // Label 870: @33726
12017 /* 33726 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(34004),
12018 /* 33731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12019 /* 33735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12020 /* 33739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 880*/ GIMT_Encode4(33759), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5846 //
12021 /* 33746 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src
12022 /* 33746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12023 /* 33749 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12024 /* 33751 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12025 /* 33753 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12026 /* 33758 */ // GIR_Coverage, 5846,
12027 /* 33758 */ GIR_EraseRootFromParent_Done,
12028 /* 33759 */ // Label 880: @33759
12029 /* 33759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 881*/ GIMT_Encode4(33779), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5847 //
12030 /* 33766 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src
12031 /* 33766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12032 /* 33769 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12033 /* 33771 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12034 /* 33773 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12035 /* 33778 */ // GIR_Coverage, 5847,
12036 /* 33778 */ GIR_EraseRootFromParent_Done,
12037 /* 33779 */ // Label 881: @33779
12038 /* 33779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 882*/ GIMT_Encode4(33799), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5851 //
12039 /* 33786 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src
12040 /* 33786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12041 /* 33789 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12042 /* 33791 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12043 /* 33793 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12044 /* 33798 */ // GIR_Coverage, 5851,
12045 /* 33798 */ GIR_EraseRootFromParent_Done,
12046 /* 33799 */ // Label 882: @33799
12047 /* 33799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 883*/ GIMT_Encode4(33819), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5852 //
12048 /* 33806 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src
12049 /* 33806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12050 /* 33809 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12051 /* 33811 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12052 /* 33813 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12053 /* 33818 */ // GIR_Coverage, 5852,
12054 /* 33818 */ GIR_EraseRootFromParent_Done,
12055 /* 33819 */ // Label 883: @33819
12056 /* 33819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 884*/ GIMT_Encode4(33865), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5882 //
12057 /* 33826 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
12058 /* 33826 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12059 /* 33829 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12060 /* 33833 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12061 /* 33838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12062 /* 33841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12063 /* 33843 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12064 /* 33845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12065 /* 33848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12066 /* 33854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12067 /* 33860 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12068 /* 33863 */ GIR_RootConstrainSelectedInstOperands,
12069 /* 33864 */ // GIR_Coverage, 5882,
12070 /* 33864 */ GIR_EraseRootFromParent_Done,
12071 /* 33865 */ // Label 884: @33865
12072 /* 33865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 885*/ GIMT_Encode4(33911), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5883 //
12073 /* 33872 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
12074 /* 33872 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12075 /* 33875 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12076 /* 33879 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12077 /* 33884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12078 /* 33887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12079 /* 33889 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12080 /* 33891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12081 /* 33894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12082 /* 33900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12083 /* 33906 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12084 /* 33909 */ GIR_RootConstrainSelectedInstOperands,
12085 /* 33910 */ // GIR_Coverage, 5883,
12086 /* 33910 */ GIR_EraseRootFromParent_Done,
12087 /* 33911 */ // Label 885: @33911
12088 /* 33911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 886*/ GIMT_Encode4(33957), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5887 //
12089 /* 33918 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
12090 /* 33918 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12091 /* 33921 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12092 /* 33925 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12093 /* 33930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12094 /* 33933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12095 /* 33935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12096 /* 33937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12097 /* 33940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12098 /* 33946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12099 /* 33952 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12100 /* 33955 */ GIR_RootConstrainSelectedInstOperands,
12101 /* 33956 */ // GIR_Coverage, 5887,
12102 /* 33956 */ GIR_EraseRootFromParent_Done,
12103 /* 33957 */ // Label 886: @33957
12104 /* 33957 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 887*/ GIMT_Encode4(34003), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5888 //
12105 /* 33964 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
12106 /* 33964 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12107 /* 33967 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12108 /* 33971 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12109 /* 33976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12110 /* 33979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12111 /* 33981 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12112 /* 33983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12113 /* 33986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12114 /* 33992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12115 /* 33998 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12116 /* 34001 */ GIR_RootConstrainSelectedInstOperands,
12117 /* 34002 */ // GIR_Coverage, 5888,
12118 /* 34002 */ GIR_EraseRootFromParent_Done,
12119 /* 34003 */ // Label 887: @34003
12120 /* 34003 */ GIM_Reject,
12121 /* 34004 */ // Label 879: @34004
12122 /* 34004 */ GIM_Reject,
12123 /* 34005 */ // Label 852: @34005
12124 /* 34005 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(34199),
12125 /* 34010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12126 /* 34014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12127 /* 34018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 889*/ GIMT_Encode4(34038), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3177 //
12128 /* 34025 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src
12129 /* 34025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12130 /* 34028 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12131 /* 34030 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12132 /* 34032 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12133 /* 34037 */ // GIR_Coverage, 3177,
12134 /* 34037 */ GIR_EraseRootFromParent_Done,
12135 /* 34038 */ // Label 889: @34038
12136 /* 34038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 890*/ GIMT_Encode4(34058), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3178 //
12137 /* 34045 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src
12138 /* 34045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12139 /* 34048 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12140 /* 34050 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12141 /* 34052 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12142 /* 34057 */ // GIR_Coverage, 3178,
12143 /* 34057 */ GIR_EraseRootFromParent_Done,
12144 /* 34058 */ // Label 890: @34058
12145 /* 34058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 891*/ GIMT_Encode4(34078), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3182 //
12146 /* 34065 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src
12147 /* 34065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12148 /* 34068 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12149 /* 34070 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12150 /* 34072 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12151 /* 34077 */ // GIR_Coverage, 3182,
12152 /* 34077 */ GIR_EraseRootFromParent_Done,
12153 /* 34078 */ // Label 891: @34078
12154 /* 34078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 892*/ GIMT_Encode4(34098), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3183 //
12155 /* 34085 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src
12156 /* 34085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12157 /* 34088 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12158 /* 34090 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12159 /* 34092 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12160 /* 34097 */ // GIR_Coverage, 3183,
12161 /* 34097 */ GIR_EraseRootFromParent_Done,
12162 /* 34098 */ // Label 892: @34098
12163 /* 34098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 893*/ GIMT_Encode4(34123), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3249 //
12164 /* 34105 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
12165 /* 34105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12166 /* 34108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12167 /* 34110 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12168 /* 34112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12169 /* 34115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12170 /* 34121 */ GIR_RootConstrainSelectedInstOperands,
12171 /* 34122 */ // GIR_Coverage, 3249,
12172 /* 34122 */ GIR_EraseRootFromParent_Done,
12173 /* 34123 */ // Label 893: @34123
12174 /* 34123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 894*/ GIMT_Encode4(34148), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3250 //
12175 /* 34130 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
12176 /* 34130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12177 /* 34133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12178 /* 34135 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12179 /* 34137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12180 /* 34140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12181 /* 34146 */ GIR_RootConstrainSelectedInstOperands,
12182 /* 34147 */ // GIR_Coverage, 3250,
12183 /* 34147 */ GIR_EraseRootFromParent_Done,
12184 /* 34148 */ // Label 894: @34148
12185 /* 34148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 895*/ GIMT_Encode4(34173), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3254 //
12186 /* 34155 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
12187 /* 34155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12188 /* 34158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12189 /* 34160 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12190 /* 34162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12191 /* 34165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12192 /* 34171 */ GIR_RootConstrainSelectedInstOperands,
12193 /* 34172 */ // GIR_Coverage, 3254,
12194 /* 34172 */ GIR_EraseRootFromParent_Done,
12195 /* 34173 */ // Label 895: @34173
12196 /* 34173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 896*/ GIMT_Encode4(34198), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3255 //
12197 /* 34180 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
12198 /* 34180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12199 /* 34183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12200 /* 34185 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12201 /* 34187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12202 /* 34190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12203 /* 34196 */ GIR_RootConstrainSelectedInstOperands,
12204 /* 34197 */ // GIR_Coverage, 3255,
12205 /* 34197 */ GIR_EraseRootFromParent_Done,
12206 /* 34198 */ // Label 896: @34198
12207 /* 34198 */ GIM_Reject,
12208 /* 34199 */ // Label 888: @34199
12209 /* 34199 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(34477),
12210 /* 34204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12211 /* 34208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12212 /* 34212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 898*/ GIMT_Encode4(34232), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5844 //
12213 /* 34219 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src
12214 /* 34219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12215 /* 34222 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12216 /* 34224 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12217 /* 34226 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12218 /* 34231 */ // GIR_Coverage, 5844,
12219 /* 34231 */ GIR_EraseRootFromParent_Done,
12220 /* 34232 */ // Label 898: @34232
12221 /* 34232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 899*/ GIMT_Encode4(34252), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5845 //
12222 /* 34239 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src
12223 /* 34239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12224 /* 34242 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12225 /* 34244 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12226 /* 34246 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12227 /* 34251 */ // GIR_Coverage, 5845,
12228 /* 34251 */ GIR_EraseRootFromParent_Done,
12229 /* 34252 */ // Label 899: @34252
12230 /* 34252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 900*/ GIMT_Encode4(34272), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5849 //
12231 /* 34259 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src
12232 /* 34259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12233 /* 34262 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12234 /* 34264 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12235 /* 34266 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12236 /* 34271 */ // GIR_Coverage, 5849,
12237 /* 34271 */ GIR_EraseRootFromParent_Done,
12238 /* 34272 */ // Label 900: @34272
12239 /* 34272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 901*/ GIMT_Encode4(34292), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5850 //
12240 /* 34279 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src
12241 /* 34279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12242 /* 34282 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12243 /* 34284 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12244 /* 34286 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12245 /* 34291 */ // GIR_Coverage, 5850,
12246 /* 34291 */ GIR_EraseRootFromParent_Done,
12247 /* 34292 */ // Label 901: @34292
12248 /* 34292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 902*/ GIMT_Encode4(34338), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5880 //
12249 /* 34299 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
12250 /* 34299 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12251 /* 34302 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12252 /* 34306 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12253 /* 34311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12254 /* 34314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12255 /* 34316 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12256 /* 34318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12257 /* 34321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12258 /* 34327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12259 /* 34333 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12260 /* 34336 */ GIR_RootConstrainSelectedInstOperands,
12261 /* 34337 */ // GIR_Coverage, 5880,
12262 /* 34337 */ GIR_EraseRootFromParent_Done,
12263 /* 34338 */ // Label 902: @34338
12264 /* 34338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 903*/ GIMT_Encode4(34384), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5881 //
12265 /* 34345 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
12266 /* 34345 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12267 /* 34348 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12268 /* 34352 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12269 /* 34357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12270 /* 34360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12271 /* 34362 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12272 /* 34364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12273 /* 34367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12274 /* 34373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12275 /* 34379 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12276 /* 34382 */ GIR_RootConstrainSelectedInstOperands,
12277 /* 34383 */ // GIR_Coverage, 5881,
12278 /* 34383 */ GIR_EraseRootFromParent_Done,
12279 /* 34384 */ // Label 903: @34384
12280 /* 34384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 904*/ GIMT_Encode4(34430), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5885 //
12281 /* 34391 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
12282 /* 34391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12283 /* 34394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12284 /* 34398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12285 /* 34403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12286 /* 34406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12287 /* 34408 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12288 /* 34410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12289 /* 34413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12290 /* 34419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12291 /* 34425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12292 /* 34428 */ GIR_RootConstrainSelectedInstOperands,
12293 /* 34429 */ // GIR_Coverage, 5885,
12294 /* 34429 */ GIR_EraseRootFromParent_Done,
12295 /* 34430 */ // Label 904: @34430
12296 /* 34430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 905*/ GIMT_Encode4(34476), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5886 //
12297 /* 34437 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
12298 /* 34437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12299 /* 34440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12300 /* 34444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12301 /* 34449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12302 /* 34452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12303 /* 34454 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12304 /* 34456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12305 /* 34459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12306 /* 34465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12307 /* 34471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12308 /* 34474 */ GIR_RootConstrainSelectedInstOperands,
12309 /* 34475 */ // GIR_Coverage, 5886,
12310 /* 34475 */ GIR_EraseRootFromParent_Done,
12311 /* 34476 */ // Label 905: @34476
12312 /* 34476 */ GIM_Reject,
12313 /* 34477 */ // Label 897: @34477
12314 /* 34477 */ GIM_Reject,
12315 /* 34478 */ // Label 853: @34478
12316 /* 34478 */ GIM_Reject,
12317 /* 34479 */ // Label 725: @34479
12318 /* 34479 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 910*/ GIMT_Encode4(35080),
12319 /* 34490 */ /*GILLT_s64*//*Label 906*/ GIMT_Encode4(34530), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
12320 /* 34510 */ /*GILLT_v8s8*//*Label 907*/ GIMT_Encode4(34725), GIMT_Encode4(0),
12321 /* 34518 */ /*GILLT_v4s16*//*Label 908*/ GIMT_Encode4(34830), GIMT_Encode4(0),
12322 /* 34526 */ /*GILLT_v2s32*//*Label 909*/ GIMT_Encode4(35025),
12323 /* 34530 */ // Label 906: @34530
12324 /* 34530 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(34724),
12325 /* 34535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12326 /* 34539 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12327 /* 34543 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 912*/ GIMT_Encode4(34563), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3131 //
12328 /* 34550 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src
12329 /* 34550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12330 /* 34553 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12331 /* 34555 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12332 /* 34557 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12333 /* 34562 */ // GIR_Coverage, 3131,
12334 /* 34562 */ GIR_EraseRootFromParent_Done,
12335 /* 34563 */ // Label 912: @34563
12336 /* 34563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 913*/ GIMT_Encode4(34583), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3132 //
12337 /* 34570 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src
12338 /* 34570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12339 /* 34573 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12340 /* 34575 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12341 /* 34577 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12342 /* 34582 */ // GIR_Coverage, 3132,
12343 /* 34582 */ GIR_EraseRootFromParent_Done,
12344 /* 34583 */ // Label 913: @34583
12345 /* 34583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 914*/ GIMT_Encode4(34603), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3136 //
12346 /* 34590 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src
12347 /* 34590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12348 /* 34593 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12349 /* 34595 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12350 /* 34597 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12351 /* 34602 */ // GIR_Coverage, 3136,
12352 /* 34602 */ GIR_EraseRootFromParent_Done,
12353 /* 34603 */ // Label 914: @34603
12354 /* 34603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 915*/ GIMT_Encode4(34623), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3137 //
12355 /* 34610 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src
12356 /* 34610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12357 /* 34613 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12358 /* 34615 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12359 /* 34617 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12360 /* 34622 */ // GIR_Coverage, 3137,
12361 /* 34622 */ GIR_EraseRootFromParent_Done,
12362 /* 34623 */ // Label 915: @34623
12363 /* 34623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 916*/ GIMT_Encode4(34648), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3203 //
12364 /* 34630 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
12365 /* 34630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12366 /* 34633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12367 /* 34635 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12368 /* 34637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12369 /* 34640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12370 /* 34646 */ GIR_RootConstrainSelectedInstOperands,
12371 /* 34647 */ // GIR_Coverage, 3203,
12372 /* 34647 */ GIR_EraseRootFromParent_Done,
12373 /* 34648 */ // Label 916: @34648
12374 /* 34648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 917*/ GIMT_Encode4(34673), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3204 //
12375 /* 34655 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
12376 /* 34655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12377 /* 34658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12378 /* 34660 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12379 /* 34662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12380 /* 34665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12381 /* 34671 */ GIR_RootConstrainSelectedInstOperands,
12382 /* 34672 */ // GIR_Coverage, 3204,
12383 /* 34672 */ GIR_EraseRootFromParent_Done,
12384 /* 34673 */ // Label 917: @34673
12385 /* 34673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 918*/ GIMT_Encode4(34698), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3208 //
12386 /* 34680 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
12387 /* 34680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12388 /* 34683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12389 /* 34685 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12390 /* 34687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12391 /* 34690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12392 /* 34696 */ GIR_RootConstrainSelectedInstOperands,
12393 /* 34697 */ // GIR_Coverage, 3208,
12394 /* 34697 */ GIR_EraseRootFromParent_Done,
12395 /* 34698 */ // Label 918: @34698
12396 /* 34698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 919*/ GIMT_Encode4(34723), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3209 //
12397 /* 34705 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
12398 /* 34705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12399 /* 34708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12400 /* 34710 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12401 /* 34712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12402 /* 34715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12403 /* 34721 */ GIR_RootConstrainSelectedInstOperands,
12404 /* 34722 */ // GIR_Coverage, 3209,
12405 /* 34722 */ GIR_EraseRootFromParent_Done,
12406 /* 34723 */ // Label 919: @34723
12407 /* 34723 */ GIM_Reject,
12408 /* 34724 */ // Label 911: @34724
12409 /* 34724 */ GIM_Reject,
12410 /* 34725 */ // Label 907: @34725
12411 /* 34725 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(34829),
12412 /* 34730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12413 /* 34734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12414 /* 34738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 921*/ GIMT_Encode4(34758), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3135 //
12415 /* 34745 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src
12416 /* 34745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12417 /* 34748 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12418 /* 34750 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12419 /* 34752 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12420 /* 34757 */ // GIR_Coverage, 3135,
12421 /* 34757 */ GIR_EraseRootFromParent_Done,
12422 /* 34758 */ // Label 921: @34758
12423 /* 34758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 922*/ GIMT_Encode4(34778), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3140 //
12424 /* 34765 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src
12425 /* 34765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12426 /* 34768 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12427 /* 34770 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12428 /* 34772 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12429 /* 34777 */ // GIR_Coverage, 3140,
12430 /* 34777 */ GIR_EraseRootFromParent_Done,
12431 /* 34778 */ // Label 922: @34778
12432 /* 34778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 923*/ GIMT_Encode4(34803), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3207 //
12433 /* 34785 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
12434 /* 34785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
12435 /* 34788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12436 /* 34790 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12437 /* 34792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12438 /* 34795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12439 /* 34801 */ GIR_RootConstrainSelectedInstOperands,
12440 /* 34802 */ // GIR_Coverage, 3207,
12441 /* 34802 */ GIR_EraseRootFromParent_Done,
12442 /* 34803 */ // Label 923: @34803
12443 /* 34803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 924*/ GIMT_Encode4(34828), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3212 //
12444 /* 34810 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
12445 /* 34810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
12446 /* 34813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12447 /* 34815 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12448 /* 34817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12449 /* 34820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12450 /* 34826 */ GIR_RootConstrainSelectedInstOperands,
12451 /* 34827 */ // GIR_Coverage, 3212,
12452 /* 34827 */ GIR_EraseRootFromParent_Done,
12453 /* 34828 */ // Label 924: @34828
12454 /* 34828 */ GIM_Reject,
12455 /* 34829 */ // Label 920: @34829
12456 /* 34829 */ GIM_Reject,
12457 /* 34830 */ // Label 908: @34830
12458 /* 34830 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(35024),
12459 /* 34835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12460 /* 34839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12461 /* 34843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 926*/ GIMT_Encode4(34863), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3133 //
12462 /* 34850 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src
12463 /* 34850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12464 /* 34853 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12465 /* 34855 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12466 /* 34857 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12467 /* 34862 */ // GIR_Coverage, 3133,
12468 /* 34862 */ GIR_EraseRootFromParent_Done,
12469 /* 34863 */ // Label 926: @34863
12470 /* 34863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 927*/ GIMT_Encode4(34883), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3134 //
12471 /* 34870 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src
12472 /* 34870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12473 /* 34873 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12474 /* 34875 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12475 /* 34877 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12476 /* 34882 */ // GIR_Coverage, 3134,
12477 /* 34882 */ GIR_EraseRootFromParent_Done,
12478 /* 34883 */ // Label 927: @34883
12479 /* 34883 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 928*/ GIMT_Encode4(34903), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3138 //
12480 /* 34890 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src
12481 /* 34890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12482 /* 34893 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12483 /* 34895 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12484 /* 34897 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12485 /* 34902 */ // GIR_Coverage, 3138,
12486 /* 34902 */ GIR_EraseRootFromParent_Done,
12487 /* 34903 */ // Label 928: @34903
12488 /* 34903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 929*/ GIMT_Encode4(34923), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3139 //
12489 /* 34910 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src
12490 /* 34910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12491 /* 34913 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12492 /* 34915 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12493 /* 34917 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12494 /* 34922 */ // GIR_Coverage, 3139,
12495 /* 34922 */ GIR_EraseRootFromParent_Done,
12496 /* 34923 */ // Label 929: @34923
12497 /* 34923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 930*/ GIMT_Encode4(34948), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3205 //
12498 /* 34930 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
12499 /* 34930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12500 /* 34933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12501 /* 34935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12502 /* 34937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12503 /* 34940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12504 /* 34946 */ GIR_RootConstrainSelectedInstOperands,
12505 /* 34947 */ // GIR_Coverage, 3205,
12506 /* 34947 */ GIR_EraseRootFromParent_Done,
12507 /* 34948 */ // Label 930: @34948
12508 /* 34948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 931*/ GIMT_Encode4(34973), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3206 //
12509 /* 34955 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
12510 /* 34955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12511 /* 34958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12512 /* 34960 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12513 /* 34962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12514 /* 34965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12515 /* 34971 */ GIR_RootConstrainSelectedInstOperands,
12516 /* 34972 */ // GIR_Coverage, 3206,
12517 /* 34972 */ GIR_EraseRootFromParent_Done,
12518 /* 34973 */ // Label 931: @34973
12519 /* 34973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 932*/ GIMT_Encode4(34998), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3210 //
12520 /* 34980 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
12521 /* 34980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12522 /* 34983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12523 /* 34985 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12524 /* 34987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12525 /* 34990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12526 /* 34996 */ GIR_RootConstrainSelectedInstOperands,
12527 /* 34997 */ // GIR_Coverage, 3210,
12528 /* 34997 */ GIR_EraseRootFromParent_Done,
12529 /* 34998 */ // Label 932: @34998
12530 /* 34998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 933*/ GIMT_Encode4(35023), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3211 //
12531 /* 35005 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
12532 /* 35005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12533 /* 35008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12534 /* 35010 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12535 /* 35012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12536 /* 35015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12537 /* 35021 */ GIR_RootConstrainSelectedInstOperands,
12538 /* 35022 */ // GIR_Coverage, 3211,
12539 /* 35022 */ GIR_EraseRootFromParent_Done,
12540 /* 35023 */ // Label 933: @35023
12541 /* 35023 */ GIM_Reject,
12542 /* 35024 */ // Label 925: @35024
12543 /* 35024 */ GIM_Reject,
12544 /* 35025 */ // Label 909: @35025
12545 /* 35025 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(35079),
12546 /* 35030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12547 /* 35034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12548 /* 35038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 935*/ GIMT_Encode4(35058), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3111 //
12549 /* 35045 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src
12550 /* 35045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12551 /* 35048 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12552 /* 35050 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12553 /* 35052 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12554 /* 35057 */ // GIR_Coverage, 3111,
12555 /* 35057 */ GIR_EraseRootFromParent_Done,
12556 /* 35058 */ // Label 935: @35058
12557 /* 35058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 936*/ GIMT_Encode4(35078), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3112 //
12558 /* 35065 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src
12559 /* 35065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12560 /* 35068 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12561 /* 35070 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12562 /* 35072 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12563 /* 35077 */ // GIR_Coverage, 3112,
12564 /* 35077 */ GIR_EraseRootFromParent_Done,
12565 /* 35078 */ // Label 936: @35078
12566 /* 35078 */ GIM_Reject,
12567 /* 35079 */ // Label 934: @35079
12568 /* 35079 */ GIM_Reject,
12569 /* 35080 */ // Label 910: @35080
12570 /* 35080 */ GIM_Reject,
12571 /* 35081 */ // Label 726: @35081
12572 /* 35081 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 941*/ GIMT_Encode4(36422),
12573 /* 35092 */ /*GILLT_v16s8*//*Label 937*/ GIMT_Encode4(35116), GIMT_Encode4(0),
12574 /* 35100 */ /*GILLT_v8s16*//*Label 938*/ GIMT_Encode4(35367), GIMT_Encode4(0),
12575 /* 35108 */ /*GILLT_v4s32*//*Label 939*/ GIMT_Encode4(35840),
12576 /* 35112 */ /*GILLT_v2s64*//*Label 940*/ GIMT_Encode4(35949),
12577 /* 35116 */ // Label 937: @35116
12578 /* 35116 */ GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(35220),
12579 /* 35121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12580 /* 35125 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12581 /* 35129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 943*/ GIMT_Encode4(35149), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3171 //
12582 /* 35136 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src
12583 /* 35136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12584 /* 35139 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12585 /* 35141 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12586 /* 35143 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12587 /* 35148 */ // GIR_Coverage, 3171,
12588 /* 35148 */ GIR_EraseRootFromParent_Done,
12589 /* 35149 */ // Label 943: @35149
12590 /* 35149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 944*/ GIMT_Encode4(35169), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3176 //
12591 /* 35156 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src
12592 /* 35156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12593 /* 35159 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12594 /* 35161 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12595 /* 35163 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12596 /* 35168 */ // GIR_Coverage, 3176,
12597 /* 35168 */ GIR_EraseRootFromParent_Done,
12598 /* 35169 */ // Label 944: @35169
12599 /* 35169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 945*/ GIMT_Encode4(35194), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3243 //
12600 /* 35176 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
12601 /* 35176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
12602 /* 35179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12603 /* 35181 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12604 /* 35183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12605 /* 35186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12606 /* 35192 */ GIR_RootConstrainSelectedInstOperands,
12607 /* 35193 */ // GIR_Coverage, 3243,
12608 /* 35193 */ GIR_EraseRootFromParent_Done,
12609 /* 35194 */ // Label 945: @35194
12610 /* 35194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 946*/ GIMT_Encode4(35219), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3248 //
12611 /* 35201 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
12612 /* 35201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
12613 /* 35204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12614 /* 35206 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12615 /* 35208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12616 /* 35211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12617 /* 35217 */ GIR_RootConstrainSelectedInstOperands,
12618 /* 35218 */ // GIR_Coverage, 3248,
12619 /* 35218 */ GIR_EraseRootFromParent_Done,
12620 /* 35219 */ // Label 946: @35219
12621 /* 35219 */ GIM_Reject,
12622 /* 35220 */ // Label 942: @35220
12623 /* 35220 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(35366),
12624 /* 35225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12625 /* 35229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12626 /* 35233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 948*/ GIMT_Encode4(35253), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5838 //
12627 /* 35240 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src
12628 /* 35240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12629 /* 35243 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12630 /* 35245 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12631 /* 35247 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12632 /* 35252 */ // GIR_Coverage, 5838,
12633 /* 35252 */ GIR_EraseRootFromParent_Done,
12634 /* 35253 */ // Label 948: @35253
12635 /* 35253 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 949*/ GIMT_Encode4(35273), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5843 //
12636 /* 35260 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src
12637 /* 35260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12638 /* 35263 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12639 /* 35265 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12640 /* 35267 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12641 /* 35272 */ // GIR_Coverage, 5843,
12642 /* 35272 */ GIR_EraseRootFromParent_Done,
12643 /* 35273 */ // Label 949: @35273
12644 /* 35273 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 950*/ GIMT_Encode4(35319), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5874 //
12645 /* 35280 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
12646 /* 35280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12647 /* 35283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12648 /* 35287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12649 /* 35292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
12650 /* 35295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12651 /* 35297 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12652 /* 35299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12653 /* 35302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12654 /* 35308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12655 /* 35314 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12656 /* 35317 */ GIR_RootConstrainSelectedInstOperands,
12657 /* 35318 */ // GIR_Coverage, 5874,
12658 /* 35318 */ GIR_EraseRootFromParent_Done,
12659 /* 35319 */ // Label 950: @35319
12660 /* 35319 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 951*/ GIMT_Encode4(35365), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5879 //
12661 /* 35326 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
12662 /* 35326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12663 /* 35329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12664 /* 35333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12665 /* 35338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
12666 /* 35341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12667 /* 35343 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12668 /* 35345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12669 /* 35348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12670 /* 35354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12671 /* 35360 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12672 /* 35363 */ GIR_RootConstrainSelectedInstOperands,
12673 /* 35364 */ // GIR_Coverage, 5879,
12674 /* 35364 */ GIR_EraseRootFromParent_Done,
12675 /* 35365 */ // Label 951: @35365
12676 /* 35365 */ GIM_Reject,
12677 /* 35366 */ // Label 947: @35366
12678 /* 35366 */ GIM_Reject,
12679 /* 35367 */ // Label 938: @35367
12680 /* 35367 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(35561),
12681 /* 35372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12682 /* 35376 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12683 /* 35380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 953*/ GIMT_Encode4(35400), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3169 //
12684 /* 35387 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src
12685 /* 35387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12686 /* 35390 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12687 /* 35392 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12688 /* 35394 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12689 /* 35399 */ // GIR_Coverage, 3169,
12690 /* 35399 */ GIR_EraseRootFromParent_Done,
12691 /* 35400 */ // Label 953: @35400
12692 /* 35400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 954*/ GIMT_Encode4(35420), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3170 //
12693 /* 35407 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src
12694 /* 35407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12695 /* 35410 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12696 /* 35412 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12697 /* 35414 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12698 /* 35419 */ // GIR_Coverage, 3170,
12699 /* 35419 */ GIR_EraseRootFromParent_Done,
12700 /* 35420 */ // Label 954: @35420
12701 /* 35420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 955*/ GIMT_Encode4(35440), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3174 //
12702 /* 35427 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src
12703 /* 35427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12704 /* 35430 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12705 /* 35432 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12706 /* 35434 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12707 /* 35439 */ // GIR_Coverage, 3174,
12708 /* 35439 */ GIR_EraseRootFromParent_Done,
12709 /* 35440 */ // Label 955: @35440
12710 /* 35440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 956*/ GIMT_Encode4(35460), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3175 //
12711 /* 35447 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src
12712 /* 35447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12713 /* 35450 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12714 /* 35452 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12715 /* 35454 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12716 /* 35459 */ // GIR_Coverage, 3175,
12717 /* 35459 */ GIR_EraseRootFromParent_Done,
12718 /* 35460 */ // Label 956: @35460
12719 /* 35460 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 957*/ GIMT_Encode4(35485), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3241 //
12720 /* 35467 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
12721 /* 35467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12722 /* 35470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12723 /* 35472 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12724 /* 35474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12725 /* 35477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12726 /* 35483 */ GIR_RootConstrainSelectedInstOperands,
12727 /* 35484 */ // GIR_Coverage, 3241,
12728 /* 35484 */ GIR_EraseRootFromParent_Done,
12729 /* 35485 */ // Label 957: @35485
12730 /* 35485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 958*/ GIMT_Encode4(35510), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3242 //
12731 /* 35492 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
12732 /* 35492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12733 /* 35495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12734 /* 35497 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12735 /* 35499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12736 /* 35502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12737 /* 35508 */ GIR_RootConstrainSelectedInstOperands,
12738 /* 35509 */ // GIR_Coverage, 3242,
12739 /* 35509 */ GIR_EraseRootFromParent_Done,
12740 /* 35510 */ // Label 958: @35510
12741 /* 35510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 959*/ GIMT_Encode4(35535), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3246 //
12742 /* 35517 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
12743 /* 35517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12744 /* 35520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12745 /* 35522 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12746 /* 35524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12747 /* 35527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12748 /* 35533 */ GIR_RootConstrainSelectedInstOperands,
12749 /* 35534 */ // GIR_Coverage, 3246,
12750 /* 35534 */ GIR_EraseRootFromParent_Done,
12751 /* 35535 */ // Label 959: @35535
12752 /* 35535 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 960*/ GIMT_Encode4(35560), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3247 //
12753 /* 35542 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
12754 /* 35542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12755 /* 35545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12756 /* 35547 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12757 /* 35549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12758 /* 35552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12759 /* 35558 */ GIR_RootConstrainSelectedInstOperands,
12760 /* 35559 */ // GIR_Coverage, 3247,
12761 /* 35559 */ GIR_EraseRootFromParent_Done,
12762 /* 35560 */ // Label 960: @35560
12763 /* 35560 */ GIM_Reject,
12764 /* 35561 */ // Label 952: @35561
12765 /* 35561 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(35839),
12766 /* 35566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12767 /* 35570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12768 /* 35574 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 962*/ GIMT_Encode4(35594), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5836 //
12769 /* 35581 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src
12770 /* 35581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12771 /* 35584 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12772 /* 35586 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12773 /* 35588 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12774 /* 35593 */ // GIR_Coverage, 5836,
12775 /* 35593 */ GIR_EraseRootFromParent_Done,
12776 /* 35594 */ // Label 962: @35594
12777 /* 35594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 963*/ GIMT_Encode4(35614), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5837 //
12778 /* 35601 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src
12779 /* 35601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12780 /* 35604 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12781 /* 35606 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12782 /* 35608 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12783 /* 35613 */ // GIR_Coverage, 5837,
12784 /* 35613 */ GIR_EraseRootFromParent_Done,
12785 /* 35614 */ // Label 963: @35614
12786 /* 35614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 964*/ GIMT_Encode4(35634), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5841 //
12787 /* 35621 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src
12788 /* 35621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12789 /* 35624 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12790 /* 35626 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12791 /* 35628 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12792 /* 35633 */ // GIR_Coverage, 5841,
12793 /* 35633 */ GIR_EraseRootFromParent_Done,
12794 /* 35634 */ // Label 964: @35634
12795 /* 35634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 965*/ GIMT_Encode4(35654), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5842 //
12796 /* 35641 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src
12797 /* 35641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12798 /* 35644 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12799 /* 35646 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12800 /* 35648 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12801 /* 35653 */ // GIR_Coverage, 5842,
12802 /* 35653 */ GIR_EraseRootFromParent_Done,
12803 /* 35654 */ // Label 965: @35654
12804 /* 35654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 966*/ GIMT_Encode4(35700), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5872 //
12805 /* 35661 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
12806 /* 35661 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12807 /* 35664 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12808 /* 35668 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12809 /* 35673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12810 /* 35676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12811 /* 35678 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12812 /* 35680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12813 /* 35683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12814 /* 35689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12815 /* 35695 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12816 /* 35698 */ GIR_RootConstrainSelectedInstOperands,
12817 /* 35699 */ // GIR_Coverage, 5872,
12818 /* 35699 */ GIR_EraseRootFromParent_Done,
12819 /* 35700 */ // Label 966: @35700
12820 /* 35700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 967*/ GIMT_Encode4(35746), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5873 //
12821 /* 35707 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
12822 /* 35707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12823 /* 35710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12824 /* 35714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12825 /* 35719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12826 /* 35722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12827 /* 35724 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12828 /* 35726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12829 /* 35729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12830 /* 35735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12831 /* 35741 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12832 /* 35744 */ GIR_RootConstrainSelectedInstOperands,
12833 /* 35745 */ // GIR_Coverage, 5873,
12834 /* 35745 */ GIR_EraseRootFromParent_Done,
12835 /* 35746 */ // Label 967: @35746
12836 /* 35746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 968*/ GIMT_Encode4(35792), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5877 //
12837 /* 35753 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
12838 /* 35753 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12839 /* 35756 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12840 /* 35760 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12841 /* 35765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12842 /* 35768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12843 /* 35770 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12844 /* 35772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12845 /* 35775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12846 /* 35781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12847 /* 35787 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12848 /* 35790 */ GIR_RootConstrainSelectedInstOperands,
12849 /* 35791 */ // GIR_Coverage, 5877,
12850 /* 35791 */ GIR_EraseRootFromParent_Done,
12851 /* 35792 */ // Label 968: @35792
12852 /* 35792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 969*/ GIMT_Encode4(35838), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5878 //
12853 /* 35799 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
12854 /* 35799 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12855 /* 35802 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12856 /* 35806 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12857 /* 35811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12858 /* 35814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12859 /* 35816 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12860 /* 35818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12861 /* 35821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12862 /* 35827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12863 /* 35833 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12864 /* 35836 */ GIR_RootConstrainSelectedInstOperands,
12865 /* 35837 */ // GIR_Coverage, 5878,
12866 /* 35837 */ GIR_EraseRootFromParent_Done,
12867 /* 35838 */ // Label 969: @35838
12868 /* 35838 */ GIM_Reject,
12869 /* 35839 */ // Label 961: @35839
12870 /* 35839 */ GIM_Reject,
12871 /* 35840 */ // Label 939: @35840
12872 /* 35840 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(35894),
12873 /* 35845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12874 /* 35849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12875 /* 35853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 971*/ GIMT_Encode4(35873), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3117 //
12876 /* 35860 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src
12877 /* 35860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12878 /* 35863 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12879 /* 35865 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12880 /* 35867 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12881 /* 35872 */ // GIR_Coverage, 3117,
12882 /* 35872 */ GIR_EraseRootFromParent_Done,
12883 /* 35873 */ // Label 971: @35873
12884 /* 35873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 972*/ GIMT_Encode4(35893), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3118 //
12885 /* 35880 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src
12886 /* 35880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12887 /* 35883 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12888 /* 35885 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12889 /* 35887 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12890 /* 35892 */ // GIR_Coverage, 3118,
12891 /* 35892 */ GIR_EraseRootFromParent_Done,
12892 /* 35893 */ // Label 972: @35893
12893 /* 35893 */ GIM_Reject,
12894 /* 35894 */ // Label 970: @35894
12895 /* 35894 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(35948),
12896 /* 35899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12897 /* 35903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12898 /* 35907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 974*/ GIMT_Encode4(35927), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5820 //
12899 /* 35914 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src
12900 /* 35914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12901 /* 35917 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12902 /* 35919 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12903 /* 35921 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12904 /* 35926 */ // GIR_Coverage, 5820,
12905 /* 35926 */ GIR_EraseRootFromParent_Done,
12906 /* 35927 */ // Label 974: @35927
12907 /* 35927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 975*/ GIMT_Encode4(35947), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5821 //
12908 /* 35934 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src
12909 /* 35934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12910 /* 35937 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12911 /* 35939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12912 /* 35941 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12913 /* 35946 */ // GIR_Coverage, 5821,
12914 /* 35946 */ GIR_EraseRootFromParent_Done,
12915 /* 35947 */ // Label 975: @35947
12916 /* 35947 */ GIM_Reject,
12917 /* 35948 */ // Label 973: @35948
12918 /* 35948 */ GIM_Reject,
12919 /* 35949 */ // Label 940: @35949
12920 /* 35949 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(36143),
12921 /* 35954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12922 /* 35958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12923 /* 35962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 977*/ GIMT_Encode4(35982), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3167 //
12924 /* 35969 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src
12925 /* 35969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12926 /* 35972 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12927 /* 35974 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12928 /* 35976 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12929 /* 35981 */ // GIR_Coverage, 3167,
12930 /* 35981 */ GIR_EraseRootFromParent_Done,
12931 /* 35982 */ // Label 977: @35982
12932 /* 35982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 978*/ GIMT_Encode4(36002), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3168 //
12933 /* 35989 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src
12934 /* 35989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12935 /* 35992 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12936 /* 35994 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12937 /* 35996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12938 /* 36001 */ // GIR_Coverage, 3168,
12939 /* 36001 */ GIR_EraseRootFromParent_Done,
12940 /* 36002 */ // Label 978: @36002
12941 /* 36002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 979*/ GIMT_Encode4(36022), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3172 //
12942 /* 36009 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src
12943 /* 36009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12944 /* 36012 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12945 /* 36014 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12946 /* 36016 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12947 /* 36021 */ // GIR_Coverage, 3172,
12948 /* 36021 */ GIR_EraseRootFromParent_Done,
12949 /* 36022 */ // Label 979: @36022
12950 /* 36022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 980*/ GIMT_Encode4(36042), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3173 //
12951 /* 36029 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src
12952 /* 36029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12953 /* 36032 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12954 /* 36034 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12955 /* 36036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12956 /* 36041 */ // GIR_Coverage, 3173,
12957 /* 36041 */ GIR_EraseRootFromParent_Done,
12958 /* 36042 */ // Label 980: @36042
12959 /* 36042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 981*/ GIMT_Encode4(36067), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3239 //
12960 /* 36049 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
12961 /* 36049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12962 /* 36052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12963 /* 36054 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12964 /* 36056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12965 /* 36059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12966 /* 36065 */ GIR_RootConstrainSelectedInstOperands,
12967 /* 36066 */ // GIR_Coverage, 3239,
12968 /* 36066 */ GIR_EraseRootFromParent_Done,
12969 /* 36067 */ // Label 981: @36067
12970 /* 36067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 982*/ GIMT_Encode4(36092), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3240 //
12971 /* 36074 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
12972 /* 36074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12973 /* 36077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12974 /* 36079 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12975 /* 36081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12976 /* 36084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12977 /* 36090 */ GIR_RootConstrainSelectedInstOperands,
12978 /* 36091 */ // GIR_Coverage, 3240,
12979 /* 36091 */ GIR_EraseRootFromParent_Done,
12980 /* 36092 */ // Label 982: @36092
12981 /* 36092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 983*/ GIMT_Encode4(36117), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3244 //
12982 /* 36099 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
12983 /* 36099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12984 /* 36102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12985 /* 36104 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12986 /* 36106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12987 /* 36109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12988 /* 36115 */ GIR_RootConstrainSelectedInstOperands,
12989 /* 36116 */ // GIR_Coverage, 3244,
12990 /* 36116 */ GIR_EraseRootFromParent_Done,
12991 /* 36117 */ // Label 983: @36117
12992 /* 36117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 984*/ GIMT_Encode4(36142), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3245 //
12993 /* 36124 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
12994 /* 36124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12995 /* 36127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12996 /* 36129 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12997 /* 36131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12998 /* 36134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12999 /* 36140 */ GIR_RootConstrainSelectedInstOperands,
13000 /* 36141 */ // GIR_Coverage, 3245,
13001 /* 36141 */ GIR_EraseRootFromParent_Done,
13002 /* 36142 */ // Label 984: @36142
13003 /* 36142 */ GIM_Reject,
13004 /* 36143 */ // Label 976: @36143
13005 /* 36143 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(36421),
13006 /* 36148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13007 /* 36152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13008 /* 36156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 986*/ GIMT_Encode4(36176), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5834 //
13009 /* 36163 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src
13010 /* 36163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13011 /* 36166 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13012 /* 36168 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13013 /* 36170 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13014 /* 36175 */ // GIR_Coverage, 5834,
13015 /* 36175 */ GIR_EraseRootFromParent_Done,
13016 /* 36176 */ // Label 986: @36176
13017 /* 36176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 987*/ GIMT_Encode4(36196), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5835 //
13018 /* 36183 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src
13019 /* 36183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13020 /* 36186 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13021 /* 36188 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13022 /* 36190 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13023 /* 36195 */ // GIR_Coverage, 5835,
13024 /* 36195 */ GIR_EraseRootFromParent_Done,
13025 /* 36196 */ // Label 987: @36196
13026 /* 36196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 988*/ GIMT_Encode4(36216), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5839 //
13027 /* 36203 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src
13028 /* 36203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13029 /* 36206 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13030 /* 36208 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13031 /* 36210 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13032 /* 36215 */ // GIR_Coverage, 5839,
13033 /* 36215 */ GIR_EraseRootFromParent_Done,
13034 /* 36216 */ // Label 988: @36216
13035 /* 36216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 989*/ GIMT_Encode4(36236), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5840 //
13036 /* 36223 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src
13037 /* 36223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13038 /* 36226 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13039 /* 36228 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13040 /* 36230 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13041 /* 36235 */ // GIR_Coverage, 5840,
13042 /* 36235 */ GIR_EraseRootFromParent_Done,
13043 /* 36236 */ // Label 989: @36236
13044 /* 36236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 990*/ GIMT_Encode4(36282), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5870 //
13045 /* 36243 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
13046 /* 36243 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13047 /* 36246 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13048 /* 36250 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13049 /* 36255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13050 /* 36258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13051 /* 36260 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13052 /* 36262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13053 /* 36265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13054 /* 36271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13055 /* 36277 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13056 /* 36280 */ GIR_RootConstrainSelectedInstOperands,
13057 /* 36281 */ // GIR_Coverage, 5870,
13058 /* 36281 */ GIR_EraseRootFromParent_Done,
13059 /* 36282 */ // Label 990: @36282
13060 /* 36282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 991*/ GIMT_Encode4(36328), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5871 //
13061 /* 36289 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
13062 /* 36289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13063 /* 36292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13064 /* 36296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13065 /* 36301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13066 /* 36304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13067 /* 36306 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13068 /* 36308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13069 /* 36311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13070 /* 36317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13071 /* 36323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13072 /* 36326 */ GIR_RootConstrainSelectedInstOperands,
13073 /* 36327 */ // GIR_Coverage, 5871,
13074 /* 36327 */ GIR_EraseRootFromParent_Done,
13075 /* 36328 */ // Label 991: @36328
13076 /* 36328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 992*/ GIMT_Encode4(36374), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5875 //
13077 /* 36335 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
13078 /* 36335 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13079 /* 36338 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13080 /* 36342 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13081 /* 36347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13082 /* 36350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13083 /* 36352 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13084 /* 36354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13085 /* 36357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13086 /* 36363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13087 /* 36369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13088 /* 36372 */ GIR_RootConstrainSelectedInstOperands,
13089 /* 36373 */ // GIR_Coverage, 5875,
13090 /* 36373 */ GIR_EraseRootFromParent_Done,
13091 /* 36374 */ // Label 992: @36374
13092 /* 36374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 993*/ GIMT_Encode4(36420), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5876 //
13093 /* 36381 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
13094 /* 36381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13095 /* 36384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13096 /* 36388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13097 /* 36393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13098 /* 36396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13099 /* 36398 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13100 /* 36400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13101 /* 36403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13102 /* 36409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13103 /* 36415 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13104 /* 36418 */ GIR_RootConstrainSelectedInstOperands,
13105 /* 36419 */ // GIR_Coverage, 5876,
13106 /* 36419 */ GIR_EraseRootFromParent_Done,
13107 /* 36420 */ // Label 993: @36420
13108 /* 36420 */ GIM_Reject,
13109 /* 36421 */ // Label 985: @36421
13110 /* 36421 */ GIM_Reject,
13111 /* 36422 */ // Label 941: @36422
13112 /* 36422 */ GIM_Reject,
13113 /* 36423 */ // Label 727: @36423
13114 /* 36423 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 998*/ GIMT_Encode4(37764),
13115 /* 36434 */ /*GILLT_v16s8*//*Label 994*/ GIMT_Encode4(36458), GIMT_Encode4(0),
13116 /* 36442 */ /*GILLT_v8s16*//*Label 995*/ GIMT_Encode4(36709), GIMT_Encode4(0),
13117 /* 36450 */ /*GILLT_v4s32*//*Label 996*/ GIMT_Encode4(37182),
13118 /* 36454 */ /*GILLT_v2s64*//*Label 997*/ GIMT_Encode4(37655),
13119 /* 36458 */ // Label 994: @36458
13120 /* 36458 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(36562),
13121 /* 36463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13122 /* 36467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13123 /* 36471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36491), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3161 //
13124 /* 36478 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src
13125 /* 36478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13126 /* 36481 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13127 /* 36483 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13128 /* 36485 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13129 /* 36490 */ // GIR_Coverage, 3161,
13130 /* 36490 */ GIR_EraseRootFromParent_Done,
13131 /* 36491 */ // Label 1000: @36491
13132 /* 36491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36511), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3166 //
13133 /* 36498 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src
13134 /* 36498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13135 /* 36501 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13136 /* 36503 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13137 /* 36505 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13138 /* 36510 */ // GIR_Coverage, 3166,
13139 /* 36510 */ GIR_EraseRootFromParent_Done,
13140 /* 36511 */ // Label 1001: @36511
13141 /* 36511 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36536), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3233 //
13142 /* 36518 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
13143 /* 36518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
13144 /* 36521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13145 /* 36523 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13146 /* 36525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13147 /* 36528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13148 /* 36534 */ GIR_RootConstrainSelectedInstOperands,
13149 /* 36535 */ // GIR_Coverage, 3233,
13150 /* 36535 */ GIR_EraseRootFromParent_Done,
13151 /* 36536 */ // Label 1002: @36536
13152 /* 36536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36561), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3238 //
13153 /* 36543 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
13154 /* 36543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
13155 /* 36546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13156 /* 36548 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13157 /* 36550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13158 /* 36553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13159 /* 36559 */ GIR_RootConstrainSelectedInstOperands,
13160 /* 36560 */ // GIR_Coverage, 3238,
13161 /* 36560 */ GIR_EraseRootFromParent_Done,
13162 /* 36561 */ // Label 1003: @36561
13163 /* 36561 */ GIM_Reject,
13164 /* 36562 */ // Label 999: @36562
13165 /* 36562 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36708),
13166 /* 36567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13167 /* 36571 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13168 /* 36575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1005*/ GIMT_Encode4(36595), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5828 //
13169 /* 36582 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src
13170 /* 36582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13171 /* 36585 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13172 /* 36587 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13173 /* 36589 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13174 /* 36594 */ // GIR_Coverage, 5828,
13175 /* 36594 */ GIR_EraseRootFromParent_Done,
13176 /* 36595 */ // Label 1005: @36595
13177 /* 36595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1006*/ GIMT_Encode4(36615), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5833 //
13178 /* 36602 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src
13179 /* 36602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13180 /* 36605 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13181 /* 36607 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13182 /* 36609 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13183 /* 36614 */ // GIR_Coverage, 5833,
13184 /* 36614 */ GIR_EraseRootFromParent_Done,
13185 /* 36615 */ // Label 1006: @36615
13186 /* 36615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1007*/ GIMT_Encode4(36661), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5864 //
13187 /* 36622 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
13188 /* 36622 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13189 /* 36625 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13190 /* 36629 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13191 /* 36634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
13192 /* 36637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13193 /* 36639 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13194 /* 36641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13195 /* 36644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13196 /* 36650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13197 /* 36656 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13198 /* 36659 */ GIR_RootConstrainSelectedInstOperands,
13199 /* 36660 */ // GIR_Coverage, 5864,
13200 /* 36660 */ GIR_EraseRootFromParent_Done,
13201 /* 36661 */ // Label 1007: @36661
13202 /* 36661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1008*/ GIMT_Encode4(36707), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5869 //
13203 /* 36668 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
13204 /* 36668 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13205 /* 36671 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13206 /* 36675 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13207 /* 36680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
13208 /* 36683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13209 /* 36685 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13210 /* 36687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13211 /* 36690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13212 /* 36696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13213 /* 36702 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13214 /* 36705 */ GIR_RootConstrainSelectedInstOperands,
13215 /* 36706 */ // GIR_Coverage, 5869,
13216 /* 36706 */ GIR_EraseRootFromParent_Done,
13217 /* 36707 */ // Label 1008: @36707
13218 /* 36707 */ GIM_Reject,
13219 /* 36708 */ // Label 1004: @36708
13220 /* 36708 */ GIM_Reject,
13221 /* 36709 */ // Label 995: @36709
13222 /* 36709 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(36903),
13223 /* 36714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13224 /* 36718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13225 /* 36722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1010*/ GIMT_Encode4(36742), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3159 //
13226 /* 36729 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src
13227 /* 36729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13228 /* 36732 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13229 /* 36734 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13230 /* 36736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13231 /* 36741 */ // GIR_Coverage, 3159,
13232 /* 36741 */ GIR_EraseRootFromParent_Done,
13233 /* 36742 */ // Label 1010: @36742
13234 /* 36742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1011*/ GIMT_Encode4(36762), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3160 //
13235 /* 36749 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src
13236 /* 36749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13237 /* 36752 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13238 /* 36754 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13239 /* 36756 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13240 /* 36761 */ // GIR_Coverage, 3160,
13241 /* 36761 */ GIR_EraseRootFromParent_Done,
13242 /* 36762 */ // Label 1011: @36762
13243 /* 36762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1012*/ GIMT_Encode4(36782), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3164 //
13244 /* 36769 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src
13245 /* 36769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13246 /* 36772 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13247 /* 36774 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13248 /* 36776 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13249 /* 36781 */ // GIR_Coverage, 3164,
13250 /* 36781 */ GIR_EraseRootFromParent_Done,
13251 /* 36782 */ // Label 1012: @36782
13252 /* 36782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1013*/ GIMT_Encode4(36802), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3165 //
13253 /* 36789 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src
13254 /* 36789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13255 /* 36792 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13256 /* 36794 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13257 /* 36796 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13258 /* 36801 */ // GIR_Coverage, 3165,
13259 /* 36801 */ GIR_EraseRootFromParent_Done,
13260 /* 36802 */ // Label 1013: @36802
13261 /* 36802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1014*/ GIMT_Encode4(36827), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3231 //
13262 /* 36809 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
13263 /* 36809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13264 /* 36812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13265 /* 36814 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13266 /* 36816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13267 /* 36819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13268 /* 36825 */ GIR_RootConstrainSelectedInstOperands,
13269 /* 36826 */ // GIR_Coverage, 3231,
13270 /* 36826 */ GIR_EraseRootFromParent_Done,
13271 /* 36827 */ // Label 1014: @36827
13272 /* 36827 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1015*/ GIMT_Encode4(36852), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3232 //
13273 /* 36834 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
13274 /* 36834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13275 /* 36837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13276 /* 36839 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13277 /* 36841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13278 /* 36844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13279 /* 36850 */ GIR_RootConstrainSelectedInstOperands,
13280 /* 36851 */ // GIR_Coverage, 3232,
13281 /* 36851 */ GIR_EraseRootFromParent_Done,
13282 /* 36852 */ // Label 1015: @36852
13283 /* 36852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1016*/ GIMT_Encode4(36877), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3236 //
13284 /* 36859 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
13285 /* 36859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13286 /* 36862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13287 /* 36864 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13288 /* 36866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13289 /* 36869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13290 /* 36875 */ GIR_RootConstrainSelectedInstOperands,
13291 /* 36876 */ // GIR_Coverage, 3236,
13292 /* 36876 */ GIR_EraseRootFromParent_Done,
13293 /* 36877 */ // Label 1016: @36877
13294 /* 36877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1017*/ GIMT_Encode4(36902), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3237 //
13295 /* 36884 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
13296 /* 36884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13297 /* 36887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13298 /* 36889 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13299 /* 36891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13300 /* 36894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13301 /* 36900 */ GIR_RootConstrainSelectedInstOperands,
13302 /* 36901 */ // GIR_Coverage, 3237,
13303 /* 36901 */ GIR_EraseRootFromParent_Done,
13304 /* 36902 */ // Label 1017: @36902
13305 /* 36902 */ GIM_Reject,
13306 /* 36903 */ // Label 1009: @36903
13307 /* 36903 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(37181),
13308 /* 36908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13309 /* 36912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13310 /* 36916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1019*/ GIMT_Encode4(36936), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5826 //
13311 /* 36923 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src
13312 /* 36923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13313 /* 36926 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13314 /* 36928 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13315 /* 36930 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13316 /* 36935 */ // GIR_Coverage, 5826,
13317 /* 36935 */ GIR_EraseRootFromParent_Done,
13318 /* 36936 */ // Label 1019: @36936
13319 /* 36936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1020*/ GIMT_Encode4(36956), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5827 //
13320 /* 36943 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src
13321 /* 36943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13322 /* 36946 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13323 /* 36948 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13324 /* 36950 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13325 /* 36955 */ // GIR_Coverage, 5827,
13326 /* 36955 */ GIR_EraseRootFromParent_Done,
13327 /* 36956 */ // Label 1020: @36956
13328 /* 36956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1021*/ GIMT_Encode4(36976), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5831 //
13329 /* 36963 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src
13330 /* 36963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13331 /* 36966 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13332 /* 36968 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13333 /* 36970 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13334 /* 36975 */ // GIR_Coverage, 5831,
13335 /* 36975 */ GIR_EraseRootFromParent_Done,
13336 /* 36976 */ // Label 1021: @36976
13337 /* 36976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1022*/ GIMT_Encode4(36996), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5832 //
13338 /* 36983 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src
13339 /* 36983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13340 /* 36986 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13341 /* 36988 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13342 /* 36990 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13343 /* 36995 */ // GIR_Coverage, 5832,
13344 /* 36995 */ GIR_EraseRootFromParent_Done,
13345 /* 36996 */ // Label 1022: @36996
13346 /* 36996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37042), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5862 //
13347 /* 37003 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
13348 /* 37003 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13349 /* 37006 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13350 /* 37010 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13351 /* 37015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13352 /* 37018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13353 /* 37020 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13354 /* 37022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13355 /* 37025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13356 /* 37031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13357 /* 37037 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13358 /* 37040 */ GIR_RootConstrainSelectedInstOperands,
13359 /* 37041 */ // GIR_Coverage, 5862,
13360 /* 37041 */ GIR_EraseRootFromParent_Done,
13361 /* 37042 */ // Label 1023: @37042
13362 /* 37042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1024*/ GIMT_Encode4(37088), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5863 //
13363 /* 37049 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
13364 /* 37049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13365 /* 37052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13366 /* 37056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13367 /* 37061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13368 /* 37064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13369 /* 37066 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13370 /* 37068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13371 /* 37071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13372 /* 37077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13373 /* 37083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13374 /* 37086 */ GIR_RootConstrainSelectedInstOperands,
13375 /* 37087 */ // GIR_Coverage, 5863,
13376 /* 37087 */ GIR_EraseRootFromParent_Done,
13377 /* 37088 */ // Label 1024: @37088
13378 /* 37088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1025*/ GIMT_Encode4(37134), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5867 //
13379 /* 37095 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
13380 /* 37095 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13381 /* 37098 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13382 /* 37102 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13383 /* 37107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13384 /* 37110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13385 /* 37112 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13386 /* 37114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13387 /* 37117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13388 /* 37123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13389 /* 37129 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13390 /* 37132 */ GIR_RootConstrainSelectedInstOperands,
13391 /* 37133 */ // GIR_Coverage, 5867,
13392 /* 37133 */ GIR_EraseRootFromParent_Done,
13393 /* 37134 */ // Label 1025: @37134
13394 /* 37134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1026*/ GIMT_Encode4(37180), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5868 //
13395 /* 37141 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
13396 /* 37141 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13397 /* 37144 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13398 /* 37148 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13399 /* 37153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13400 /* 37156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13401 /* 37158 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13402 /* 37160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13403 /* 37163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13404 /* 37169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13405 /* 37175 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13406 /* 37178 */ GIR_RootConstrainSelectedInstOperands,
13407 /* 37179 */ // GIR_Coverage, 5868,
13408 /* 37179 */ GIR_EraseRootFromParent_Done,
13409 /* 37180 */ // Label 1026: @37180
13410 /* 37180 */ GIM_Reject,
13411 /* 37181 */ // Label 1018: @37181
13412 /* 37181 */ GIM_Reject,
13413 /* 37182 */ // Label 996: @37182
13414 /* 37182 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(37376),
13415 /* 37187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13416 /* 37191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13417 /* 37195 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1028*/ GIMT_Encode4(37215), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3157 //
13418 /* 37202 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src
13419 /* 37202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13420 /* 37205 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13421 /* 37207 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13422 /* 37209 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13423 /* 37214 */ // GIR_Coverage, 3157,
13424 /* 37214 */ GIR_EraseRootFromParent_Done,
13425 /* 37215 */ // Label 1028: @37215
13426 /* 37215 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1029*/ GIMT_Encode4(37235), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3158 //
13427 /* 37222 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src
13428 /* 37222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13429 /* 37225 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13430 /* 37227 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13431 /* 37229 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13432 /* 37234 */ // GIR_Coverage, 3158,
13433 /* 37234 */ GIR_EraseRootFromParent_Done,
13434 /* 37235 */ // Label 1029: @37235
13435 /* 37235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1030*/ GIMT_Encode4(37255), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3162 //
13436 /* 37242 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src
13437 /* 37242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13438 /* 37245 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13439 /* 37247 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13440 /* 37249 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13441 /* 37254 */ // GIR_Coverage, 3162,
13442 /* 37254 */ GIR_EraseRootFromParent_Done,
13443 /* 37255 */ // Label 1030: @37255
13444 /* 37255 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1031*/ GIMT_Encode4(37275), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3163 //
13445 /* 37262 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src
13446 /* 37262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13447 /* 37265 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13448 /* 37267 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13449 /* 37269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13450 /* 37274 */ // GIR_Coverage, 3163,
13451 /* 37274 */ GIR_EraseRootFromParent_Done,
13452 /* 37275 */ // Label 1031: @37275
13453 /* 37275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1032*/ GIMT_Encode4(37300), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3229 //
13454 /* 37282 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
13455 /* 37282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13456 /* 37285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13457 /* 37287 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13458 /* 37289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13459 /* 37292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13460 /* 37298 */ GIR_RootConstrainSelectedInstOperands,
13461 /* 37299 */ // GIR_Coverage, 3229,
13462 /* 37299 */ GIR_EraseRootFromParent_Done,
13463 /* 37300 */ // Label 1032: @37300
13464 /* 37300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1033*/ GIMT_Encode4(37325), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3230 //
13465 /* 37307 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
13466 /* 37307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13467 /* 37310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13468 /* 37312 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13469 /* 37314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13470 /* 37317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13471 /* 37323 */ GIR_RootConstrainSelectedInstOperands,
13472 /* 37324 */ // GIR_Coverage, 3230,
13473 /* 37324 */ GIR_EraseRootFromParent_Done,
13474 /* 37325 */ // Label 1033: @37325
13475 /* 37325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1034*/ GIMT_Encode4(37350), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3234 //
13476 /* 37332 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
13477 /* 37332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13478 /* 37335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13479 /* 37337 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13480 /* 37339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13481 /* 37342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13482 /* 37348 */ GIR_RootConstrainSelectedInstOperands,
13483 /* 37349 */ // GIR_Coverage, 3234,
13484 /* 37349 */ GIR_EraseRootFromParent_Done,
13485 /* 37350 */ // Label 1034: @37350
13486 /* 37350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1035*/ GIMT_Encode4(37375), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3235 //
13487 /* 37357 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
13488 /* 37357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13489 /* 37360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13490 /* 37362 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13491 /* 37364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13492 /* 37367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13493 /* 37373 */ GIR_RootConstrainSelectedInstOperands,
13494 /* 37374 */ // GIR_Coverage, 3235,
13495 /* 37374 */ GIR_EraseRootFromParent_Done,
13496 /* 37375 */ // Label 1035: @37375
13497 /* 37375 */ GIM_Reject,
13498 /* 37376 */ // Label 1027: @37376
13499 /* 37376 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(37654),
13500 /* 37381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13501 /* 37385 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13502 /* 37389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1037*/ GIMT_Encode4(37409), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5824 //
13503 /* 37396 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src
13504 /* 37396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13505 /* 37399 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13506 /* 37401 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13507 /* 37403 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13508 /* 37408 */ // GIR_Coverage, 5824,
13509 /* 37408 */ GIR_EraseRootFromParent_Done,
13510 /* 37409 */ // Label 1037: @37409
13511 /* 37409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1038*/ GIMT_Encode4(37429), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5825 //
13512 /* 37416 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src
13513 /* 37416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13514 /* 37419 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13515 /* 37421 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13516 /* 37423 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13517 /* 37428 */ // GIR_Coverage, 5825,
13518 /* 37428 */ GIR_EraseRootFromParent_Done,
13519 /* 37429 */ // Label 1038: @37429
13520 /* 37429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1039*/ GIMT_Encode4(37449), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5829 //
13521 /* 37436 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src
13522 /* 37436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13523 /* 37439 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13524 /* 37441 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13525 /* 37443 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13526 /* 37448 */ // GIR_Coverage, 5829,
13527 /* 37448 */ GIR_EraseRootFromParent_Done,
13528 /* 37449 */ // Label 1039: @37449
13529 /* 37449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1040*/ GIMT_Encode4(37469), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5830 //
13530 /* 37456 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src
13531 /* 37456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13532 /* 37459 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13533 /* 37461 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13534 /* 37463 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13535 /* 37468 */ // GIR_Coverage, 5830,
13536 /* 37468 */ GIR_EraseRootFromParent_Done,
13537 /* 37469 */ // Label 1040: @37469
13538 /* 37469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1041*/ GIMT_Encode4(37515), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5860 //
13539 /* 37476 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
13540 /* 37476 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13541 /* 37479 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13542 /* 37483 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13543 /* 37488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13544 /* 37491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13545 /* 37493 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13546 /* 37495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13547 /* 37498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13548 /* 37504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13549 /* 37510 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13550 /* 37513 */ GIR_RootConstrainSelectedInstOperands,
13551 /* 37514 */ // GIR_Coverage, 5860,
13552 /* 37514 */ GIR_EraseRootFromParent_Done,
13553 /* 37515 */ // Label 1041: @37515
13554 /* 37515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1042*/ GIMT_Encode4(37561), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5861 //
13555 /* 37522 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
13556 /* 37522 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13557 /* 37525 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13558 /* 37529 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13559 /* 37534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13560 /* 37537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13561 /* 37539 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13562 /* 37541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13563 /* 37544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13564 /* 37550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13565 /* 37556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13566 /* 37559 */ GIR_RootConstrainSelectedInstOperands,
13567 /* 37560 */ // GIR_Coverage, 5861,
13568 /* 37560 */ GIR_EraseRootFromParent_Done,
13569 /* 37561 */ // Label 1042: @37561
13570 /* 37561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1043*/ GIMT_Encode4(37607), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5865 //
13571 /* 37568 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
13572 /* 37568 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13573 /* 37571 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13574 /* 37575 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13575 /* 37580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13576 /* 37583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13577 /* 37585 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13578 /* 37587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13579 /* 37590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13580 /* 37596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13581 /* 37602 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13582 /* 37605 */ GIR_RootConstrainSelectedInstOperands,
13583 /* 37606 */ // GIR_Coverage, 5865,
13584 /* 37606 */ GIR_EraseRootFromParent_Done,
13585 /* 37607 */ // Label 1043: @37607
13586 /* 37607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1044*/ GIMT_Encode4(37653), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5866 //
13587 /* 37614 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
13588 /* 37614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13589 /* 37617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13590 /* 37621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13591 /* 37626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13592 /* 37629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13593 /* 37631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13594 /* 37633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13595 /* 37636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13596 /* 37642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13597 /* 37648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13598 /* 37651 */ GIR_RootConstrainSelectedInstOperands,
13599 /* 37652 */ // GIR_Coverage, 5866,
13600 /* 37652 */ GIR_EraseRootFromParent_Done,
13601 /* 37653 */ // Label 1044: @37653
13602 /* 37653 */ GIM_Reject,
13603 /* 37654 */ // Label 1036: @37654
13604 /* 37654 */ GIM_Reject,
13605 /* 37655 */ // Label 997: @37655
13606 /* 37655 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(37709),
13607 /* 37660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13608 /* 37664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13609 /* 37668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1046*/ GIMT_Encode4(37688), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3115 //
13610 /* 37675 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src
13611 /* 37675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13612 /* 37678 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13613 /* 37680 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13614 /* 37682 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13615 /* 37687 */ // GIR_Coverage, 3115,
13616 /* 37687 */ GIR_EraseRootFromParent_Done,
13617 /* 37688 */ // Label 1046: @37688
13618 /* 37688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1047*/ GIMT_Encode4(37708), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3116 //
13619 /* 37695 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src
13620 /* 37695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13621 /* 37698 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13622 /* 37700 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13623 /* 37702 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13624 /* 37707 */ // GIR_Coverage, 3116,
13625 /* 37707 */ GIR_EraseRootFromParent_Done,
13626 /* 37708 */ // Label 1047: @37708
13627 /* 37708 */ GIM_Reject,
13628 /* 37709 */ // Label 1045: @37709
13629 /* 37709 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(37763),
13630 /* 37714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13631 /* 37718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13632 /* 37722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1049*/ GIMT_Encode4(37742), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5818 //
13633 /* 37729 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src
13634 /* 37729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13635 /* 37732 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13636 /* 37734 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13637 /* 37736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13638 /* 37741 */ // GIR_Coverage, 5818,
13639 /* 37741 */ GIR_EraseRootFromParent_Done,
13640 /* 37742 */ // Label 1049: @37742
13641 /* 37742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1050*/ GIMT_Encode4(37762), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5819 //
13642 /* 37749 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src
13643 /* 37749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13644 /* 37752 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13645 /* 37754 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13646 /* 37756 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13647 /* 37761 */ // GIR_Coverage, 5819,
13648 /* 37761 */ GIR_EraseRootFromParent_Done,
13649 /* 37762 */ // Label 1050: @37762
13650 /* 37762 */ GIM_Reject,
13651 /* 37763 */ // Label 1048: @37763
13652 /* 37763 */ GIM_Reject,
13653 /* 37764 */ // Label 998: @37764
13654 /* 37764 */ GIM_Reject,
13655 /* 37765 */ // Label 728: @37765
13656 /* 37765 */ GIM_Reject,
13657 /* 37766 */ // Label 16: @37766
13658 /* 37766 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1058*/ GIMT_Encode4(38164),
13659 /* 37777 */ /*GILLT_s16*//*Label 1051*/ GIMT_Encode4(37829),
13660 /* 37781 */ /*GILLT_s32*//*Label 1052*/ GIMT_Encode4(37866),
13661 /* 37785 */ /*GILLT_s64*//*Label 1053*/ GIMT_Encode4(37903), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13662 /* 37813 */ /*GILLT_v4s16*//*Label 1054*/ GIMT_Encode4(37940),
13663 /* 37817 */ /*GILLT_v8s16*//*Label 1055*/ GIMT_Encode4(37966),
13664 /* 37821 */ /*GILLT_v2s32*//*Label 1056*/ GIMT_Encode4(38052),
13665 /* 37825 */ /*GILLT_v4s32*//*Label 1057*/ GIMT_Encode4(38078),
13666 /* 37829 */ // Label 1051: @37829
13667 /* 37829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1059*/ GIMT_Encode4(37865), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 693 //
13668 /* 37836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
13669 /* 37839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13670 /* 37843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13671 /* 37847 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13672 /* 37847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH),
13673 /* 37850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
13674 /* 37852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
13675 /* 37854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13676 /* 37857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13677 /* 37863 */ GIR_RootConstrainSelectedInstOperands,
13678 /* 37864 */ // GIR_Coverage, 693,
13679 /* 37864 */ GIR_EraseRootFromParent_Done,
13680 /* 37865 */ // Label 1059: @37865
13681 /* 37865 */ GIM_Reject,
13682 /* 37866 */ // Label 1052: @37866
13683 /* 37866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1060*/ GIMT_Encode4(37902), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 695 //
13684 /* 37873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13685 /* 37876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13686 /* 37880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13687 /* 37884 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13688 /* 37884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS),
13689 /* 37887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
13690 /* 37889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
13691 /* 37891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13692 /* 37894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13693 /* 37900 */ GIR_RootConstrainSelectedInstOperands,
13694 /* 37901 */ // GIR_Coverage, 695,
13695 /* 37901 */ GIR_EraseRootFromParent_Done,
13696 /* 37902 */ // Label 1060: @37902
13697 /* 37902 */ GIM_Reject,
13698 /* 37903 */ // Label 1053: @37903
13699 /* 37903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1061*/ GIMT_Encode4(37939), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 697 //
13700 /* 37910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13701 /* 37913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13702 /* 37917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13703 /* 37921 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13704 /* 37921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD),
13705 /* 37924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
13706 /* 37926 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
13707 /* 37928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13708 /* 37931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13709 /* 37937 */ GIR_RootConstrainSelectedInstOperands,
13710 /* 37938 */ // GIR_Coverage, 697,
13711 /* 37938 */ GIR_EraseRootFromParent_Done,
13712 /* 37939 */ // Label 1061: @37939
13713 /* 37939 */ GIM_Reject,
13714 /* 37940 */ // Label 1054: @37940
13715 /* 37940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1062*/ GIMT_Encode4(37965), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1882 //
13716 /* 37947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13717 /* 37950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13718 /* 37954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13719 /* 37958 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13720 /* 37958 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh),
13721 /* 37963 */ GIR_RootConstrainSelectedInstOperands,
13722 /* 37964 */ // GIR_Coverage, 1882,
13723 /* 37964 */ GIR_Done,
13724 /* 37965 */ // Label 1062: @37965
13725 /* 37965 */ GIM_Reject,
13726 /* 37966 */ // Label 1055: @37966
13727 /* 37966 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(38051),
13728 /* 37971 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13729 /* 37974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1064*/ GIMT_Encode4(37996), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1884 //
13730 /* 37981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13731 /* 37985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13732 /* 37989 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13733 /* 37989 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh),
13734 /* 37994 */ GIR_RootConstrainSelectedInstOperands,
13735 /* 37995 */ // GIR_Coverage, 1884,
13736 /* 37995 */ GIR_Done,
13737 /* 37996 */ // Label 1064: @37996
13738 /* 37996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1065*/ GIMT_Encode4(38050), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4380 //
13739 /* 38003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13740 /* 38007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13741 /* 38011 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13742 /* 38011 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13743 /* 38014 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13744 /* 38018 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13745 /* 38023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
13746 /* 38026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13747 /* 38028 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13748 /* 38030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13749 /* 38033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13750 /* 38039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13751 /* 38045 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13752 /* 38048 */ GIR_RootConstrainSelectedInstOperands,
13753 /* 38049 */ // GIR_Coverage, 4380,
13754 /* 38049 */ GIR_EraseRootFromParent_Done,
13755 /* 38050 */ // Label 1065: @38050
13756 /* 38050 */ GIM_Reject,
13757 /* 38051 */ // Label 1063: @38051
13758 /* 38051 */ GIM_Reject,
13759 /* 38052 */ // Label 1056: @38052
13760 /* 38052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1066*/ GIMT_Encode4(38077), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1878 //
13761 /* 38059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13762 /* 38062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13763 /* 38066 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13764 /* 38070 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13765 /* 38070 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf),
13766 /* 38075 */ GIR_RootConstrainSelectedInstOperands,
13767 /* 38076 */ // GIR_Coverage, 1878,
13768 /* 38076 */ GIR_Done,
13769 /* 38077 */ // Label 1066: @38077
13770 /* 38077 */ GIM_Reject,
13771 /* 38078 */ // Label 1057: @38078
13772 /* 38078 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(38163),
13773 /* 38083 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13774 /* 38086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1068*/ GIMT_Encode4(38108), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1880 //
13775 /* 38093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13776 /* 38097 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13777 /* 38101 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13778 /* 38101 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf),
13779 /* 38106 */ GIR_RootConstrainSelectedInstOperands,
13780 /* 38107 */ // GIR_Coverage, 1880,
13781 /* 38107 */ GIR_Done,
13782 /* 38108 */ // Label 1068: @38108
13783 /* 38108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1069*/ GIMT_Encode4(38162), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4404 //
13784 /* 38115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13785 /* 38119 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13786 /* 38123 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13787 /* 38123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13788 /* 38126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13789 /* 38130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13790 /* 38135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
13791 /* 38138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13792 /* 38140 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13793 /* 38142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13794 /* 38145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13795 /* 38151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13796 /* 38157 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13797 /* 38160 */ GIR_RootConstrainSelectedInstOperands,
13798 /* 38161 */ // GIR_Coverage, 4404,
13799 /* 38161 */ GIR_EraseRootFromParent_Done,
13800 /* 38162 */ // Label 1069: @38162
13801 /* 38162 */ GIM_Reject,
13802 /* 38163 */ // Label 1067: @38163
13803 /* 38163 */ GIM_Reject,
13804 /* 38164 */ // Label 1058: @38164
13805 /* 38164 */ GIM_Reject,
13806 /* 38165 */ // Label 17: @38165
13807 /* 38165 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1077*/ GIMT_Encode4(38530),
13808 /* 38176 */ /*GILLT_s16*//*Label 1070*/ GIMT_Encode4(38228),
13809 /* 38180 */ /*GILLT_s32*//*Label 1071*/ GIMT_Encode4(38254),
13810 /* 38184 */ /*GILLT_s64*//*Label 1072*/ GIMT_Encode4(38280), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13811 /* 38212 */ /*GILLT_v4s16*//*Label 1073*/ GIMT_Encode4(38306),
13812 /* 38216 */ /*GILLT_v8s16*//*Label 1074*/ GIMT_Encode4(38332),
13813 /* 38220 */ /*GILLT_v2s32*//*Label 1075*/ GIMT_Encode4(38418),
13814 /* 38224 */ /*GILLT_v4s32*//*Label 1076*/ GIMT_Encode4(38444),
13815 /* 38228 */ // Label 1070: @38228
13816 /* 38228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1078*/ GIMT_Encode4(38253), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 711 //
13817 /* 38235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
13818 /* 38238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13819 /* 38242 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13820 /* 38246 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13821 /* 38246 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH),
13822 /* 38251 */ GIR_RootConstrainSelectedInstOperands,
13823 /* 38252 */ // GIR_Coverage, 711,
13824 /* 38252 */ GIR_Done,
13825 /* 38253 */ // Label 1078: @38253
13826 /* 38253 */ GIM_Reject,
13827 /* 38254 */ // Label 1071: @38254
13828 /* 38254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1079*/ GIMT_Encode4(38279), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 713 //
13829 /* 38261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13830 /* 38264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13831 /* 38268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13832 /* 38272 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13833 /* 38272 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS),
13834 /* 38277 */ GIR_RootConstrainSelectedInstOperands,
13835 /* 38278 */ // GIR_Coverage, 713,
13836 /* 38278 */ GIR_Done,
13837 /* 38279 */ // Label 1079: @38279
13838 /* 38279 */ GIM_Reject,
13839 /* 38280 */ // Label 1072: @38280
13840 /* 38280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1080*/ GIMT_Encode4(38305), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 715 //
13841 /* 38287 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13842 /* 38290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13843 /* 38294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13844 /* 38298 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13845 /* 38298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD),
13846 /* 38303 */ GIR_RootConstrainSelectedInstOperands,
13847 /* 38304 */ // GIR_Coverage, 715,
13848 /* 38304 */ GIR_Done,
13849 /* 38305 */ // Label 1080: @38305
13850 /* 38305 */ GIM_Reject,
13851 /* 38306 */ // Label 1073: @38306
13852 /* 38306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1081*/ GIMT_Encode4(38331), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1874 //
13853 /* 38313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13854 /* 38316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13855 /* 38320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13856 /* 38324 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13857 /* 38324 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh),
13858 /* 38329 */ GIR_RootConstrainSelectedInstOperands,
13859 /* 38330 */ // GIR_Coverage, 1874,
13860 /* 38330 */ GIR_Done,
13861 /* 38331 */ // Label 1081: @38331
13862 /* 38331 */ GIM_Reject,
13863 /* 38332 */ // Label 1074: @38332
13864 /* 38332 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(38417),
13865 /* 38337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13866 /* 38340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1083*/ GIMT_Encode4(38362), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1876 //
13867 /* 38347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13868 /* 38351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13869 /* 38355 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13870 /* 38355 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh),
13871 /* 38360 */ GIR_RootConstrainSelectedInstOperands,
13872 /* 38361 */ // GIR_Coverage, 1876,
13873 /* 38361 */ GIR_Done,
13874 /* 38362 */ // Label 1083: @38362
13875 /* 38362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1084*/ GIMT_Encode4(38416), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4376 //
13876 /* 38369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13877 /* 38373 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13878 /* 38377 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13879 /* 38377 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13880 /* 38380 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13881 /* 38384 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13882 /* 38389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
13883 /* 38392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13884 /* 38394 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13885 /* 38396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13886 /* 38399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13887 /* 38405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13888 /* 38411 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13889 /* 38414 */ GIR_RootConstrainSelectedInstOperands,
13890 /* 38415 */ // GIR_Coverage, 4376,
13891 /* 38415 */ GIR_EraseRootFromParent_Done,
13892 /* 38416 */ // Label 1084: @38416
13893 /* 38416 */ GIM_Reject,
13894 /* 38417 */ // Label 1082: @38417
13895 /* 38417 */ GIM_Reject,
13896 /* 38418 */ // Label 1075: @38418
13897 /* 38418 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1085*/ GIMT_Encode4(38443), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1870 //
13898 /* 38425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13899 /* 38428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13900 /* 38432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13901 /* 38436 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13902 /* 38436 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf),
13903 /* 38441 */ GIR_RootConstrainSelectedInstOperands,
13904 /* 38442 */ // GIR_Coverage, 1870,
13905 /* 38442 */ GIR_Done,
13906 /* 38443 */ // Label 1085: @38443
13907 /* 38443 */ GIM_Reject,
13908 /* 38444 */ // Label 1076: @38444
13909 /* 38444 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(38529),
13910 /* 38449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13911 /* 38452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1087*/ GIMT_Encode4(38474), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1872 //
13912 /* 38459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13913 /* 38463 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13914 /* 38467 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13915 /* 38467 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf),
13916 /* 38472 */ GIR_RootConstrainSelectedInstOperands,
13917 /* 38473 */ // GIR_Coverage, 1872,
13918 /* 38473 */ GIR_Done,
13919 /* 38474 */ // Label 1087: @38474
13920 /* 38474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1088*/ GIMT_Encode4(38528), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4400 //
13921 /* 38481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13922 /* 38485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13923 /* 38489 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13924 /* 38489 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13925 /* 38492 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13926 /* 38496 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13927 /* 38501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
13928 /* 38504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13929 /* 38506 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13930 /* 38508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13931 /* 38511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13932 /* 38517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13933 /* 38523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13934 /* 38526 */ GIR_RootConstrainSelectedInstOperands,
13935 /* 38527 */ // GIR_Coverage, 4400,
13936 /* 38527 */ GIR_EraseRootFromParent_Done,
13937 /* 38528 */ // Label 1088: @38528
13938 /* 38528 */ GIM_Reject,
13939 /* 38529 */ // Label 1086: @38529
13940 /* 38529 */ GIM_Reject,
13941 /* 38530 */ // Label 1077: @38530
13942 /* 38530 */ GIM_Reject,
13943 /* 38531 */ // Label 18: @38531
13944 /* 38531 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1096*/ GIMT_Encode4(38896),
13945 /* 38542 */ /*GILLT_s16*//*Label 1089*/ GIMT_Encode4(38594),
13946 /* 38546 */ /*GILLT_s32*//*Label 1090*/ GIMT_Encode4(38620),
13947 /* 38550 */ /*GILLT_s64*//*Label 1091*/ GIMT_Encode4(38646), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13948 /* 38578 */ /*GILLT_v4s16*//*Label 1092*/ GIMT_Encode4(38672),
13949 /* 38582 */ /*GILLT_v8s16*//*Label 1093*/ GIMT_Encode4(38698),
13950 /* 38586 */ /*GILLT_v2s32*//*Label 1094*/ GIMT_Encode4(38784),
13951 /* 38590 */ /*GILLT_v4s32*//*Label 1095*/ GIMT_Encode4(38810),
13952 /* 38594 */ // Label 1089: @38594
13953 /* 38594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1097*/ GIMT_Encode4(38619), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 717 //
13954 /* 38601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
13955 /* 38604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13956 /* 38608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13957 /* 38612 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13958 /* 38612 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH),
13959 /* 38617 */ GIR_RootConstrainSelectedInstOperands,
13960 /* 38618 */ // GIR_Coverage, 717,
13961 /* 38618 */ GIR_Done,
13962 /* 38619 */ // Label 1097: @38619
13963 /* 38619 */ GIM_Reject,
13964 /* 38620 */ // Label 1090: @38620
13965 /* 38620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1098*/ GIMT_Encode4(38645), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 719 //
13966 /* 38627 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13967 /* 38630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13968 /* 38634 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13969 /* 38638 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13970 /* 38638 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS),
13971 /* 38643 */ GIR_RootConstrainSelectedInstOperands,
13972 /* 38644 */ // GIR_Coverage, 719,
13973 /* 38644 */ GIR_Done,
13974 /* 38645 */ // Label 1098: @38645
13975 /* 38645 */ GIM_Reject,
13976 /* 38646 */ // Label 1091: @38646
13977 /* 38646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1099*/ GIMT_Encode4(38671), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 721 //
13978 /* 38653 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13979 /* 38656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13980 /* 38660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13981 /* 38664 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13982 /* 38664 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND),
13983 /* 38669 */ GIR_RootConstrainSelectedInstOperands,
13984 /* 38670 */ // GIR_Coverage, 721,
13985 /* 38670 */ GIR_Done,
13986 /* 38671 */ // Label 1099: @38671
13987 /* 38671 */ GIM_Reject,
13988 /* 38672 */ // Label 1092: @38672
13989 /* 38672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1100*/ GIMT_Encode4(38697), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1858 //
13990 /* 38679 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13991 /* 38682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13992 /* 38686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13993 /* 38690 */ // (froundeven:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13994 /* 38690 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh),
13995 /* 38695 */ GIR_RootConstrainSelectedInstOperands,
13996 /* 38696 */ // GIR_Coverage, 1858,
13997 /* 38696 */ GIR_Done,
13998 /* 38697 */ // Label 1100: @38697
13999 /* 38697 */ GIM_Reject,
14000 /* 38698 */ // Label 1093: @38698
14001 /* 38698 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(38783),
14002 /* 38703 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14003 /* 38706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1102*/ GIMT_Encode4(38728), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1860 //
14004 /* 38713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14005 /* 38717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14006 /* 38721 */ // (froundeven:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14007 /* 38721 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh),
14008 /* 38726 */ GIR_RootConstrainSelectedInstOperands,
14009 /* 38727 */ // GIR_Coverage, 1860,
14010 /* 38727 */ GIR_Done,
14011 /* 38728 */ // Label 1102: @38728
14012 /* 38728 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1103*/ GIMT_Encode4(38782), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4368 //
14013 /* 38735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14014 /* 38739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14015 /* 38743 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
14016 /* 38743 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14017 /* 38746 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14018 /* 38750 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14019 /* 38755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
14020 /* 38758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14021 /* 38760 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14022 /* 38762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14023 /* 38765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14024 /* 38771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14025 /* 38777 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14026 /* 38780 */ GIR_RootConstrainSelectedInstOperands,
14027 /* 38781 */ // GIR_Coverage, 4368,
14028 /* 38781 */ GIR_EraseRootFromParent_Done,
14029 /* 38782 */ // Label 1103: @38782
14030 /* 38782 */ GIM_Reject,
14031 /* 38783 */ // Label 1101: @38783
14032 /* 38783 */ GIM_Reject,
14033 /* 38784 */ // Label 1094: @38784
14034 /* 38784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1104*/ GIMT_Encode4(38809), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1854 //
14035 /* 38791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14036 /* 38794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14037 /* 38798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14038 /* 38802 */ // (froundeven:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14039 /* 38802 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf),
14040 /* 38807 */ GIR_RootConstrainSelectedInstOperands,
14041 /* 38808 */ // GIR_Coverage, 1854,
14042 /* 38808 */ GIR_Done,
14043 /* 38809 */ // Label 1104: @38809
14044 /* 38809 */ GIM_Reject,
14045 /* 38810 */ // Label 1095: @38810
14046 /* 38810 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(38895),
14047 /* 38815 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14048 /* 38818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1106*/ GIMT_Encode4(38840), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1856 //
14049 /* 38825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14050 /* 38829 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14051 /* 38833 */ // (froundeven:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14052 /* 38833 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf),
14053 /* 38838 */ GIR_RootConstrainSelectedInstOperands,
14054 /* 38839 */ // GIR_Coverage, 1856,
14055 /* 38839 */ GIR_Done,
14056 /* 38840 */ // Label 1106: @38840
14057 /* 38840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1107*/ GIMT_Encode4(38894), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4392 //
14058 /* 38847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14059 /* 38851 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14060 /* 38855 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
14061 /* 38855 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14062 /* 38858 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14063 /* 38862 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14064 /* 38867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
14065 /* 38870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14066 /* 38872 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14067 /* 38874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14068 /* 38877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14069 /* 38883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14070 /* 38889 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14071 /* 38892 */ GIR_RootConstrainSelectedInstOperands,
14072 /* 38893 */ // GIR_Coverage, 4392,
14073 /* 38893 */ GIR_EraseRootFromParent_Done,
14074 /* 38894 */ // Label 1107: @38894
14075 /* 38894 */ GIM_Reject,
14076 /* 38895 */ // Label 1105: @38895
14077 /* 38895 */ GIM_Reject,
14078 /* 38896 */ // Label 1096: @38896
14079 /* 38896 */ GIM_Reject,
14080 /* 38897 */ // Label 19: @38897
14081 /* 38897 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(39057),
14082 /* 38902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14083 /* 38905 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
14084 /* 38908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1109*/ GIMT_Encode4(38982), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2249 //
14085 /* 38915 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
14086 /* 38922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14087 /* 38926 */ // MIs[0] Rn
14088 /* 38926 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
14089 /* 38930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14090 /* 38934 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
14091 /* 38934 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14092 /* 38937 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
14093 /* 38941 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14094 /* 38946 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
14095 /* 38952 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
14096 /* 38955 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
14097 /* 38958 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14098 /* 38964 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14099 /* 38966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB),
14100 /* 38969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
14101 /* 38971 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
14102 /* 38973 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14103 /* 38976 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14104 /* 38980 */ GIR_RootConstrainSelectedInstOperands,
14105 /* 38981 */ // GIR_Coverage, 2249,
14106 /* 38981 */ GIR_EraseRootFromParent_Done,
14107 /* 38982 */ // Label 1109: @38982
14108 /* 38982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1110*/ GIMT_Encode4(39056), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2250 //
14109 /* 38989 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
14110 /* 38996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14111 /* 39000 */ // MIs[0] Rn
14112 /* 39000 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
14113 /* 39004 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14114 /* 39008 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
14115 /* 39008 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14116 /* 39011 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
14117 /* 39015 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14118 /* 39020 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
14119 /* 39026 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
14120 /* 39029 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
14121 /* 39032 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14122 /* 39038 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14123 /* 39040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH),
14124 /* 39043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
14125 /* 39045 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
14126 /* 39047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14127 /* 39050 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14128 /* 39054 */ GIR_RootConstrainSelectedInstOperands,
14129 /* 39055 */ // GIR_Coverage, 2250,
14130 /* 39055 */ GIR_EraseRootFromParent_Done,
14131 /* 39056 */ // Label 1110: @39056
14132 /* 39056 */ GIM_Reject,
14133 /* 39057 */ // Label 1108: @39057
14134 /* 39057 */ GIM_Reject,
14135 /* 39058 */ // Label 20: @39058
14136 /* 39058 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(39078), // Rule ID 5956 //
14137 /* 39063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14138 /* 39066 */ // MIs[0] Operand 0
14139 /* 39066 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0,
14140 /* 39069 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
14141 /* 39073 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER)
14142 /* 39073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER),
14143 /* 39076 */ GIR_RootConstrainSelectedInstOperands,
14144 /* 39077 */ // GIR_Coverage, 5956,
14145 /* 39077 */ GIR_EraseRootFromParent_Done,
14146 /* 39078 */ // Label 1111: @39078
14147 /* 39078 */ GIM_Reject,
14148 /* 39079 */ // Label 21: @39079
14149 /* 39079 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(39144),
14150 /* 39084 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
14151 /* 39088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
14152 /* 39092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1113*/ GIMT_Encode4(39106), GIMT_Encode2(GIFBS_HasV4T_IsARM), // Rule ID 25 //
14153 /* 39099 */ // (brind GPR:{ *:[i32] }:$dst) => (BX GPR:{ *:[i32] }:$dst)
14154 /* 39099 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::BX),
14155 /* 39104 */ GIR_RootConstrainSelectedInstOperands,
14156 /* 39105 */ // GIR_Coverage, 25,
14157 /* 39105 */ GIR_Done,
14158 /* 39106 */ // Label 1113: @39106
14159 /* 39106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1114*/ GIMT_Encode4(39120), GIMT_Encode2(GIFBS_IsARM_NoV4T), // Rule ID 266 //
14160 /* 39113 */ // (brind GPR:{ *:[i32] }:$dst) => (MOVPCRX GPR:{ *:[i32] }:$dst)
14161 /* 39113 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::MOVPCRX),
14162 /* 39118 */ GIR_RootConstrainSelectedInstOperands,
14163 /* 39119 */ // GIR_Coverage, 266,
14164 /* 39119 */ GIR_Done,
14165 /* 39120 */ // Label 1114: @39120
14166 /* 39120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1115*/ GIMT_Encode4(39143), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 354 //
14167 /* 39127 */ // (brind GPR:{ *:[i32] }:$Rm) => (tBRIND GPR:{ *:[i32] }:$Rm)
14168 /* 39127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBRIND),
14169 /* 39130 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rm
14170 /* 39132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14171 /* 39135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14172 /* 39141 */ GIR_RootConstrainSelectedInstOperands,
14173 /* 39142 */ // GIR_Coverage, 354,
14174 /* 39142 */ GIR_EraseRootFromParent_Done,
14175 /* 39143 */ // Label 1115: @39143
14176 /* 39143 */ GIM_Reject,
14177 /* 39144 */ // Label 1112: @39144
14178 /* 39144 */ GIM_Reject,
14179 /* 39145 */ // Label 22: @39145
14180 /* 39145 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(44456),
14181 /* 39150 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
14182 /* 39153 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(39242),
14183 /* 39158 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
14184 /* 39163 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14185 /* 39166 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14186 /* 39169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1118*/ GIMT_Encode4(39205), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2044 //
14187 /* 39176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
14188 /* 39180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
14189 /* 39184 */ // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
14190 /* 39184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
14191 /* 39187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14192 /* 39189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
14193 /* 39191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14194 /* 39194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14195 /* 39197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14196 /* 39203 */ GIR_RootConstrainSelectedInstOperands,
14197 /* 39204 */ // GIR_Coverage, 2044,
14198 /* 39204 */ GIR_EraseRootFromParent_Done,
14199 /* 39205 */ // Label 1118: @39205
14200 /* 39205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1119*/ GIMT_Encode4(39241), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2306 //
14201 /* 39212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
14202 /* 39216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
14203 /* 39220 */ // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
14204 /* 39220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
14205 /* 39223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14206 /* 39225 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
14207 /* 39227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14208 /* 39230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14209 /* 39233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14210 /* 39239 */ GIR_RootConstrainSelectedInstOperands,
14211 /* 39240 */ // GIR_Coverage, 2306,
14212 /* 39240 */ GIR_EraseRootFromParent_Done,
14213 /* 39241 */ // Label 1119: @39241
14214 /* 39241 */ GIM_Reject,
14215 /* 39242 */ // Label 1117: @39242
14216 /* 39242 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(39343),
14217 /* 39247 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
14218 /* 39252 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14219 /* 39255 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1123*/ GIMT_Encode4(39342),
14220 /* 39266 */ /*GILLT_s32*//*Label 1121*/ GIMT_Encode4(39274),
14221 /* 39270 */ /*GILLT_s64*//*Label 1122*/ GIMT_Encode4(39308),
14222 /* 39274 */ // Label 1121: @39274
14223 /* 39274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1124*/ GIMT_Encode4(39307), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 745 //
14224 /* 39281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14225 /* 39285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14226 /* 39289 */ // (intrinsic_wo_chain:{ *:[f32] } 4196:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14227 /* 39289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS),
14228 /* 39292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14229 /* 39294 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
14230 /* 39296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14231 /* 39299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14232 /* 39305 */ GIR_RootConstrainSelectedInstOperands,
14233 /* 39306 */ // GIR_Coverage, 745,
14234 /* 39306 */ GIR_EraseRootFromParent_Done,
14235 /* 39307 */ // Label 1124: @39307
14236 /* 39307 */ GIM_Reject,
14237 /* 39308 */ // Label 1122: @39308
14238 /* 39308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1125*/ GIMT_Encode4(39341), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 744 //
14239 /* 39315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14240 /* 39319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14241 /* 39323 */ // (intrinsic_wo_chain:{ *:[f32] } 4196:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14242 /* 39323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD),
14243 /* 39326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14244 /* 39328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
14245 /* 39330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14246 /* 39333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14247 /* 39339 */ GIR_RootConstrainSelectedInstOperands,
14248 /* 39340 */ // GIR_Coverage, 744,
14249 /* 39340 */ GIR_EraseRootFromParent_Done,
14250 /* 39341 */ // Label 1125: @39341
14251 /* 39341 */ GIM_Reject,
14252 /* 39342 */ // Label 1123: @39342
14253 /* 39342 */ GIM_Reject,
14254 /* 39343 */ // Label 1120: @39343
14255 /* 39343 */ GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(39444),
14256 /* 39348 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
14257 /* 39353 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14258 /* 39356 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1129*/ GIMT_Encode4(39443),
14259 /* 39367 */ /*GILLT_s32*//*Label 1127*/ GIMT_Encode4(39375),
14260 /* 39371 */ /*GILLT_s64*//*Label 1128*/ GIMT_Encode4(39409),
14261 /* 39375 */ // Label 1127: @39375
14262 /* 39375 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1130*/ GIMT_Encode4(39408), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 747 //
14263 /* 39382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14264 /* 39386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14265 /* 39390 */ // (intrinsic_wo_chain:{ *:[f32] } 4197:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14266 /* 39390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS),
14267 /* 39393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14268 /* 39395 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
14269 /* 39397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14270 /* 39400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14271 /* 39406 */ GIR_RootConstrainSelectedInstOperands,
14272 /* 39407 */ // GIR_Coverage, 747,
14273 /* 39407 */ GIR_EraseRootFromParent_Done,
14274 /* 39408 */ // Label 1130: @39408
14275 /* 39408 */ GIM_Reject,
14276 /* 39409 */ // Label 1128: @39409
14277 /* 39409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1131*/ GIMT_Encode4(39442), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 746 //
14278 /* 39416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14279 /* 39420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14280 /* 39424 */ // (intrinsic_wo_chain:{ *:[f32] } 4197:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14281 /* 39424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD),
14282 /* 39427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14283 /* 39429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
14284 /* 39431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14285 /* 39434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14286 /* 39440 */ GIR_RootConstrainSelectedInstOperands,
14287 /* 39441 */ // GIR_Coverage, 746,
14288 /* 39441 */ GIR_EraseRootFromParent_Done,
14289 /* 39442 */ // Label 1131: @39442
14290 /* 39442 */ GIM_Reject,
14291 /* 39443 */ // Label 1129: @39443
14292 /* 39443 */ GIM_Reject,
14293 /* 39444 */ // Label 1126: @39444
14294 /* 39444 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(39736),
14295 /* 39449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14296 /* 39454 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1139*/ GIMT_Encode4(39735),
14297 /* 39465 */ /*GILLT_s64*//*Label 1133*/ GIMT_Encode4(39513), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14298 /* 39493 */ /*GILLT_v4s16*//*Label 1134*/ GIMT_Encode4(39550),
14299 /* 39497 */ /*GILLT_v8s16*//*Label 1135*/ GIMT_Encode4(39587),
14300 /* 39501 */ /*GILLT_v2s32*//*Label 1136*/ GIMT_Encode4(39624),
14301 /* 39505 */ /*GILLT_v4s32*//*Label 1137*/ GIMT_Encode4(39661),
14302 /* 39509 */ /*GILLT_v2s64*//*Label 1138*/ GIMT_Encode4(39698),
14303 /* 39513 */ // Label 1133: @39513
14304 /* 39513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1140*/ GIMT_Encode4(39549), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1406 //
14305 /* 39520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14306 /* 39523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14307 /* 39527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14308 /* 39531 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4053:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14309 /* 39531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32),
14310 /* 39534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14311 /* 39536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14312 /* 39538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14313 /* 39541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14314 /* 39547 */ GIR_RootConstrainSelectedInstOperands,
14315 /* 39548 */ // GIR_Coverage, 1406,
14316 /* 39548 */ GIR_EraseRootFromParent_Done,
14317 /* 39549 */ // Label 1140: @39549
14318 /* 39549 */ GIM_Reject,
14319 /* 39550 */ // Label 1134: @39550
14320 /* 39550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1141*/ GIMT_Encode4(39586), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1404 //
14321 /* 39557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14322 /* 39560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14323 /* 39564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14324 /* 39568 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4053:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14325 /* 39568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8),
14326 /* 39571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14327 /* 39573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14328 /* 39575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14329 /* 39578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14330 /* 39584 */ GIR_RootConstrainSelectedInstOperands,
14331 /* 39585 */ // GIR_Coverage, 1404,
14332 /* 39585 */ GIR_EraseRootFromParent_Done,
14333 /* 39586 */ // Label 1141: @39586
14334 /* 39586 */ GIM_Reject,
14335 /* 39587 */ // Label 1135: @39587
14336 /* 39587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1142*/ GIMT_Encode4(39623), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1407 //
14337 /* 39594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14338 /* 39597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14339 /* 39601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14340 /* 39605 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4053:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14341 /* 39605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8),
14342 /* 39608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14343 /* 39610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14344 /* 39612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14345 /* 39615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14346 /* 39621 */ GIR_RootConstrainSelectedInstOperands,
14347 /* 39622 */ // GIR_Coverage, 1407,
14348 /* 39622 */ GIR_EraseRootFromParent_Done,
14349 /* 39623 */ // Label 1142: @39623
14350 /* 39623 */ GIM_Reject,
14351 /* 39624 */ // Label 1136: @39624
14352 /* 39624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1143*/ GIMT_Encode4(39660), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1405 //
14353 /* 39631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14354 /* 39634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14355 /* 39638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14356 /* 39642 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4053:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14357 /* 39642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16),
14358 /* 39645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14359 /* 39647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14360 /* 39649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14361 /* 39652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14362 /* 39658 */ GIR_RootConstrainSelectedInstOperands,
14363 /* 39659 */ // GIR_Coverage, 1405,
14364 /* 39659 */ GIR_EraseRootFromParent_Done,
14365 /* 39660 */ // Label 1143: @39660
14366 /* 39660 */ GIM_Reject,
14367 /* 39661 */ // Label 1137: @39661
14368 /* 39661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1144*/ GIMT_Encode4(39697), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1408 //
14369 /* 39668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14370 /* 39671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14371 /* 39675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14372 /* 39679 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4053:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14373 /* 39679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16),
14374 /* 39682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14375 /* 39684 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14376 /* 39686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14377 /* 39689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14378 /* 39695 */ GIR_RootConstrainSelectedInstOperands,
14379 /* 39696 */ // GIR_Coverage, 1408,
14380 /* 39696 */ GIR_EraseRootFromParent_Done,
14381 /* 39697 */ // Label 1144: @39697
14382 /* 39697 */ GIM_Reject,
14383 /* 39698 */ // Label 1138: @39698
14384 /* 39698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1145*/ GIMT_Encode4(39734), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1409 //
14385 /* 39705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14386 /* 39708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14387 /* 39712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14388 /* 39716 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4053:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14389 /* 39716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32),
14390 /* 39719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14391 /* 39721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14392 /* 39723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14393 /* 39726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14394 /* 39732 */ GIR_RootConstrainSelectedInstOperands,
14395 /* 39733 */ // GIR_Coverage, 1409,
14396 /* 39733 */ GIR_EraseRootFromParent_Done,
14397 /* 39734 */ // Label 1145: @39734
14398 /* 39734 */ GIM_Reject,
14399 /* 39735 */ // Label 1139: @39735
14400 /* 39735 */ GIM_Reject,
14401 /* 39736 */ // Label 1132: @39736
14402 /* 39736 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(40028),
14403 /* 39741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14404 /* 39746 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1153*/ GIMT_Encode4(40027),
14405 /* 39757 */ /*GILLT_s64*//*Label 1147*/ GIMT_Encode4(39805), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14406 /* 39785 */ /*GILLT_v4s16*//*Label 1148*/ GIMT_Encode4(39842),
14407 /* 39789 */ /*GILLT_v8s16*//*Label 1149*/ GIMT_Encode4(39879),
14408 /* 39793 */ /*GILLT_v2s32*//*Label 1150*/ GIMT_Encode4(39916),
14409 /* 39797 */ /*GILLT_v4s32*//*Label 1151*/ GIMT_Encode4(39953),
14410 /* 39801 */ /*GILLT_v2s64*//*Label 1152*/ GIMT_Encode4(39990),
14411 /* 39805 */ // Label 1147: @39805
14412 /* 39805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1154*/ GIMT_Encode4(39841), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1412 //
14413 /* 39812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14414 /* 39815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14415 /* 39819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14416 /* 39823 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4054:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14417 /* 39823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32),
14418 /* 39826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14419 /* 39828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14420 /* 39830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14421 /* 39833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14422 /* 39839 */ GIR_RootConstrainSelectedInstOperands,
14423 /* 39840 */ // GIR_Coverage, 1412,
14424 /* 39840 */ GIR_EraseRootFromParent_Done,
14425 /* 39841 */ // Label 1154: @39841
14426 /* 39841 */ GIM_Reject,
14427 /* 39842 */ // Label 1148: @39842
14428 /* 39842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1155*/ GIMT_Encode4(39878), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1410 //
14429 /* 39849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14430 /* 39852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14431 /* 39856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14432 /* 39860 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4054:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14433 /* 39860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8),
14434 /* 39863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14435 /* 39865 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14436 /* 39867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14437 /* 39870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14438 /* 39876 */ GIR_RootConstrainSelectedInstOperands,
14439 /* 39877 */ // GIR_Coverage, 1410,
14440 /* 39877 */ GIR_EraseRootFromParent_Done,
14441 /* 39878 */ // Label 1155: @39878
14442 /* 39878 */ GIM_Reject,
14443 /* 39879 */ // Label 1149: @39879
14444 /* 39879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1156*/ GIMT_Encode4(39915), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1413 //
14445 /* 39886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14446 /* 39889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14447 /* 39893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14448 /* 39897 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4054:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14449 /* 39897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8),
14450 /* 39900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14451 /* 39902 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14452 /* 39904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14453 /* 39907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14454 /* 39913 */ GIR_RootConstrainSelectedInstOperands,
14455 /* 39914 */ // GIR_Coverage, 1413,
14456 /* 39914 */ GIR_EraseRootFromParent_Done,
14457 /* 39915 */ // Label 1156: @39915
14458 /* 39915 */ GIM_Reject,
14459 /* 39916 */ // Label 1150: @39916
14460 /* 39916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1157*/ GIMT_Encode4(39952), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1411 //
14461 /* 39923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14462 /* 39926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14463 /* 39930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14464 /* 39934 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4054:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14465 /* 39934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16),
14466 /* 39937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14467 /* 39939 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14468 /* 39941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14469 /* 39944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14470 /* 39950 */ GIR_RootConstrainSelectedInstOperands,
14471 /* 39951 */ // GIR_Coverage, 1411,
14472 /* 39951 */ GIR_EraseRootFromParent_Done,
14473 /* 39952 */ // Label 1157: @39952
14474 /* 39952 */ GIM_Reject,
14475 /* 39953 */ // Label 1151: @39953
14476 /* 39953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1158*/ GIMT_Encode4(39989), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1414 //
14477 /* 39960 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14478 /* 39963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14479 /* 39967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14480 /* 39971 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4054:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14481 /* 39971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16),
14482 /* 39974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14483 /* 39976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14484 /* 39978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14485 /* 39981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14486 /* 39987 */ GIR_RootConstrainSelectedInstOperands,
14487 /* 39988 */ // GIR_Coverage, 1414,
14488 /* 39988 */ GIR_EraseRootFromParent_Done,
14489 /* 39989 */ // Label 1158: @39989
14490 /* 39989 */ GIM_Reject,
14491 /* 39990 */ // Label 1152: @39990
14492 /* 39990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1159*/ GIMT_Encode4(40026), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1415 //
14493 /* 39997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14494 /* 40000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14495 /* 40004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14496 /* 40008 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4054:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14497 /* 40008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32),
14498 /* 40011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14499 /* 40013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14500 /* 40015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14501 /* 40018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14502 /* 40024 */ GIR_RootConstrainSelectedInstOperands,
14503 /* 40025 */ // GIR_Coverage, 1415,
14504 /* 40025 */ GIR_EraseRootFromParent_Done,
14505 /* 40026 */ // Label 1159: @40026
14506 /* 40026 */ GIM_Reject,
14507 /* 40027 */ // Label 1153: @40027
14508 /* 40027 */ GIM_Reject,
14509 /* 40028 */ // Label 1146: @40028
14510 /* 40028 */ GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(40276),
14511 /* 40033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14512 /* 40038 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1165*/ GIMT_Encode4(40275),
14513 /* 40049 */ /*GILLT_v4s16*//*Label 1161*/ GIMT_Encode4(40065),
14514 /* 40053 */ /*GILLT_v8s16*//*Label 1162*/ GIMT_Encode4(40102),
14515 /* 40057 */ /*GILLT_v2s32*//*Label 1163*/ GIMT_Encode4(40139),
14516 /* 40061 */ /*GILLT_v4s32*//*Label 1164*/ GIMT_Encode4(40207),
14517 /* 40065 */ // Label 1161: @40065
14518 /* 40065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1166*/ GIMT_Encode4(40101), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1448 //
14519 /* 40072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14520 /* 40075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14521 /* 40079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14522 /* 40083 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4081:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14523 /* 40083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd),
14524 /* 40086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14525 /* 40088 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14526 /* 40090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14527 /* 40093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14528 /* 40099 */ GIR_RootConstrainSelectedInstOperands,
14529 /* 40100 */ // GIR_Coverage, 1448,
14530 /* 40100 */ GIR_EraseRootFromParent_Done,
14531 /* 40101 */ // Label 1166: @40101
14532 /* 40101 */ GIM_Reject,
14533 /* 40102 */ // Label 1162: @40102
14534 /* 40102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1167*/ GIMT_Encode4(40138), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1449 //
14535 /* 40109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14536 /* 40112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14537 /* 40116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14538 /* 40120 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4081:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14539 /* 40120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq),
14540 /* 40123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14541 /* 40125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14542 /* 40127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14543 /* 40130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14544 /* 40136 */ GIR_RootConstrainSelectedInstOperands,
14545 /* 40137 */ // GIR_Coverage, 1449,
14546 /* 40137 */ GIR_EraseRootFromParent_Done,
14547 /* 40138 */ // Label 1167: @40138
14548 /* 40138 */ GIM_Reject,
14549 /* 40139 */ // Label 1163: @40139
14550 /* 40139 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(40206),
14551 /* 40144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14552 /* 40147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14553 /* 40151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14554 /* 40155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1169*/ GIMT_Encode4(40180), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1444 //
14555 /* 40162 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4081:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14556 /* 40162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd),
14557 /* 40165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14558 /* 40167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14559 /* 40169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14560 /* 40172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14561 /* 40178 */ GIR_RootConstrainSelectedInstOperands,
14562 /* 40179 */ // GIR_Coverage, 1444,
14563 /* 40179 */ GIR_EraseRootFromParent_Done,
14564 /* 40180 */ // Label 1169: @40180
14565 /* 40180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1170*/ GIMT_Encode4(40205), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1446 //
14566 /* 40187 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4081:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14567 /* 40187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd),
14568 /* 40190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14569 /* 40192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14570 /* 40194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14571 /* 40197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14572 /* 40203 */ GIR_RootConstrainSelectedInstOperands,
14573 /* 40204 */ // GIR_Coverage, 1446,
14574 /* 40204 */ GIR_EraseRootFromParent_Done,
14575 /* 40205 */ // Label 1170: @40205
14576 /* 40205 */ GIM_Reject,
14577 /* 40206 */ // Label 1168: @40206
14578 /* 40206 */ GIM_Reject,
14579 /* 40207 */ // Label 1164: @40207
14580 /* 40207 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(40274),
14581 /* 40212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14582 /* 40215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14583 /* 40219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14584 /* 40223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1172*/ GIMT_Encode4(40248), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1445 //
14585 /* 40230 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4081:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14586 /* 40230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq),
14587 /* 40233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14588 /* 40235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14589 /* 40237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14590 /* 40240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14591 /* 40246 */ GIR_RootConstrainSelectedInstOperands,
14592 /* 40247 */ // GIR_Coverage, 1445,
14593 /* 40247 */ GIR_EraseRootFromParent_Done,
14594 /* 40248 */ // Label 1172: @40248
14595 /* 40248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1173*/ GIMT_Encode4(40273), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1447 //
14596 /* 40255 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4081:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14597 /* 40255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq),
14598 /* 40258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14599 /* 40260 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14600 /* 40262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14601 /* 40265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14602 /* 40271 */ GIR_RootConstrainSelectedInstOperands,
14603 /* 40272 */ // GIR_Coverage, 1447,
14604 /* 40272 */ GIR_EraseRootFromParent_Done,
14605 /* 40273 */ // Label 1173: @40273
14606 /* 40273 */ GIM_Reject,
14607 /* 40274 */ // Label 1171: @40274
14608 /* 40274 */ GIM_Reject,
14609 /* 40275 */ // Label 1165: @40275
14610 /* 40275 */ GIM_Reject,
14611 /* 40276 */ // Label 1160: @40276
14612 /* 40276 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(40524),
14613 /* 40281 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14614 /* 40286 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1179*/ GIMT_Encode4(40523),
14615 /* 40297 */ /*GILLT_v4s16*//*Label 1175*/ GIMT_Encode4(40313),
14616 /* 40301 */ /*GILLT_v8s16*//*Label 1176*/ GIMT_Encode4(40350),
14617 /* 40305 */ /*GILLT_v2s32*//*Label 1177*/ GIMT_Encode4(40387),
14618 /* 40309 */ /*GILLT_v4s32*//*Label 1178*/ GIMT_Encode4(40455),
14619 /* 40313 */ // Label 1175: @40313
14620 /* 40313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1180*/ GIMT_Encode4(40349), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1458 //
14621 /* 40320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14622 /* 40323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14623 /* 40327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14624 /* 40331 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4088:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14625 /* 40331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd),
14626 /* 40334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14627 /* 40336 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14628 /* 40338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14629 /* 40341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14630 /* 40347 */ GIR_RootConstrainSelectedInstOperands,
14631 /* 40348 */ // GIR_Coverage, 1458,
14632 /* 40348 */ GIR_EraseRootFromParent_Done,
14633 /* 40349 */ // Label 1180: @40349
14634 /* 40349 */ GIM_Reject,
14635 /* 40350 */ // Label 1176: @40350
14636 /* 40350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1181*/ GIMT_Encode4(40386), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1459 //
14637 /* 40357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14638 /* 40360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14639 /* 40364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14640 /* 40368 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4088:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14641 /* 40368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq),
14642 /* 40371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14643 /* 40373 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14644 /* 40375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14645 /* 40378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14646 /* 40384 */ GIR_RootConstrainSelectedInstOperands,
14647 /* 40385 */ // GIR_Coverage, 1459,
14648 /* 40385 */ GIR_EraseRootFromParent_Done,
14649 /* 40386 */ // Label 1181: @40386
14650 /* 40386 */ GIM_Reject,
14651 /* 40387 */ // Label 1177: @40387
14652 /* 40387 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(40454),
14653 /* 40392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14654 /* 40395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14655 /* 40399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14656 /* 40403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1183*/ GIMT_Encode4(40428), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1454 //
14657 /* 40410 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4088:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14658 /* 40410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd),
14659 /* 40413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14660 /* 40415 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14661 /* 40417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14662 /* 40420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14663 /* 40426 */ GIR_RootConstrainSelectedInstOperands,
14664 /* 40427 */ // GIR_Coverage, 1454,
14665 /* 40427 */ GIR_EraseRootFromParent_Done,
14666 /* 40428 */ // Label 1183: @40428
14667 /* 40428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1184*/ GIMT_Encode4(40453), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1456 //
14668 /* 40435 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4088:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14669 /* 40435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd),
14670 /* 40438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14671 /* 40440 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14672 /* 40442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14673 /* 40445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14674 /* 40451 */ GIR_RootConstrainSelectedInstOperands,
14675 /* 40452 */ // GIR_Coverage, 1456,
14676 /* 40452 */ GIR_EraseRootFromParent_Done,
14677 /* 40453 */ // Label 1184: @40453
14678 /* 40453 */ GIM_Reject,
14679 /* 40454 */ // Label 1182: @40454
14680 /* 40454 */ GIM_Reject,
14681 /* 40455 */ // Label 1178: @40455
14682 /* 40455 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(40522),
14683 /* 40460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14684 /* 40463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14685 /* 40467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14686 /* 40471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1186*/ GIMT_Encode4(40496), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1455 //
14687 /* 40478 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4088:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14688 /* 40478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq),
14689 /* 40481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14690 /* 40483 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14691 /* 40485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14692 /* 40488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14693 /* 40494 */ GIR_RootConstrainSelectedInstOperands,
14694 /* 40495 */ // GIR_Coverage, 1455,
14695 /* 40495 */ GIR_EraseRootFromParent_Done,
14696 /* 40496 */ // Label 1186: @40496
14697 /* 40496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1187*/ GIMT_Encode4(40521), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1457 //
14698 /* 40503 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4088:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14699 /* 40503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq),
14700 /* 40506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14701 /* 40508 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14702 /* 40510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14703 /* 40513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14704 /* 40519 */ GIR_RootConstrainSelectedInstOperands,
14705 /* 40520 */ // GIR_Coverage, 1457,
14706 /* 40520 */ GIR_EraseRootFromParent_Done,
14707 /* 40521 */ // Label 1187: @40521
14708 /* 40521 */ GIM_Reject,
14709 /* 40522 */ // Label 1185: @40522
14710 /* 40522 */ GIM_Reject,
14711 /* 40523 */ // Label 1179: @40523
14712 /* 40523 */ GIM_Reject,
14713 /* 40524 */ // Label 1174: @40524
14714 /* 40524 */ GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(40792),
14715 /* 40529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14716 /* 40534 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1195*/ GIMT_Encode4(40791),
14717 /* 40545 */ /*GILLT_v8s8*//*Label 1189*/ GIMT_Encode4(40569),
14718 /* 40549 */ /*GILLT_v16s8*//*Label 1190*/ GIMT_Encode4(40606),
14719 /* 40553 */ /*GILLT_v4s16*//*Label 1191*/ GIMT_Encode4(40643),
14720 /* 40557 */ /*GILLT_v8s16*//*Label 1192*/ GIMT_Encode4(40680),
14721 /* 40561 */ /*GILLT_v2s32*//*Label 1193*/ GIMT_Encode4(40717),
14722 /* 40565 */ /*GILLT_v4s32*//*Label 1194*/ GIMT_Encode4(40754),
14723 /* 40569 */ // Label 1189: @40569
14724 /* 40569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1196*/ GIMT_Encode4(40605), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1680 //
14725 /* 40576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14726 /* 40579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14727 /* 40583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14728 /* 40587 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4059:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14729 /* 40587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8),
14730 /* 40590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14731 /* 40592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14732 /* 40594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14733 /* 40597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14734 /* 40603 */ GIR_RootConstrainSelectedInstOperands,
14735 /* 40604 */ // GIR_Coverage, 1680,
14736 /* 40604 */ GIR_EraseRootFromParent_Done,
14737 /* 40605 */ // Label 1196: @40605
14738 /* 40605 */ GIM_Reject,
14739 /* 40606 */ // Label 1190: @40606
14740 /* 40606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1197*/ GIMT_Encode4(40642), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1683 //
14741 /* 40613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14742 /* 40616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14743 /* 40620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14744 /* 40624 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4059:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14745 /* 40624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8),
14746 /* 40627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14747 /* 40629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14748 /* 40631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14749 /* 40634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14750 /* 40640 */ GIR_RootConstrainSelectedInstOperands,
14751 /* 40641 */ // GIR_Coverage, 1683,
14752 /* 40641 */ GIR_EraseRootFromParent_Done,
14753 /* 40642 */ // Label 1197: @40642
14754 /* 40642 */ GIM_Reject,
14755 /* 40643 */ // Label 1191: @40643
14756 /* 40643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1198*/ GIMT_Encode4(40679), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1681 //
14757 /* 40650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14758 /* 40653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14759 /* 40657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14760 /* 40661 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4059:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14761 /* 40661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16),
14762 /* 40664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14763 /* 40666 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14764 /* 40668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14765 /* 40671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14766 /* 40677 */ GIR_RootConstrainSelectedInstOperands,
14767 /* 40678 */ // GIR_Coverage, 1681,
14768 /* 40678 */ GIR_EraseRootFromParent_Done,
14769 /* 40679 */ // Label 1198: @40679
14770 /* 40679 */ GIM_Reject,
14771 /* 40680 */ // Label 1192: @40680
14772 /* 40680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1199*/ GIMT_Encode4(40716), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1684 //
14773 /* 40687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14774 /* 40690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14775 /* 40694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14776 /* 40698 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4059:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14777 /* 40698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16),
14778 /* 40701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14779 /* 40703 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14780 /* 40705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14781 /* 40708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14782 /* 40714 */ GIR_RootConstrainSelectedInstOperands,
14783 /* 40715 */ // GIR_Coverage, 1684,
14784 /* 40715 */ GIR_EraseRootFromParent_Done,
14785 /* 40716 */ // Label 1199: @40716
14786 /* 40716 */ GIM_Reject,
14787 /* 40717 */ // Label 1193: @40717
14788 /* 40717 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1200*/ GIMT_Encode4(40753), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1682 //
14789 /* 40724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14790 /* 40727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14791 /* 40731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14792 /* 40735 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4059:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14793 /* 40735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32),
14794 /* 40738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14795 /* 40740 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14796 /* 40742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14797 /* 40745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14798 /* 40751 */ GIR_RootConstrainSelectedInstOperands,
14799 /* 40752 */ // GIR_Coverage, 1682,
14800 /* 40752 */ GIR_EraseRootFromParent_Done,
14801 /* 40753 */ // Label 1200: @40753
14802 /* 40753 */ GIM_Reject,
14803 /* 40754 */ // Label 1194: @40754
14804 /* 40754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1201*/ GIMT_Encode4(40790), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1685 //
14805 /* 40761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14806 /* 40764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14807 /* 40768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14808 /* 40772 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4059:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14809 /* 40772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32),
14810 /* 40775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14811 /* 40777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14812 /* 40779 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14813 /* 40782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14814 /* 40788 */ GIR_RootConstrainSelectedInstOperands,
14815 /* 40789 */ // GIR_Coverage, 1685,
14816 /* 40789 */ GIR_EraseRootFromParent_Done,
14817 /* 40790 */ // Label 1201: @40790
14818 /* 40790 */ GIM_Reject,
14819 /* 40791 */ // Label 1195: @40791
14820 /* 40791 */ GIM_Reject,
14821 /* 40792 */ // Label 1188: @40792
14822 /* 40792 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(41060),
14823 /* 40797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14824 /* 40802 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1209*/ GIMT_Encode4(41059),
14825 /* 40813 */ /*GILLT_v8s8*//*Label 1203*/ GIMT_Encode4(40837),
14826 /* 40817 */ /*GILLT_v16s8*//*Label 1204*/ GIMT_Encode4(40874),
14827 /* 40821 */ /*GILLT_v4s16*//*Label 1205*/ GIMT_Encode4(40911),
14828 /* 40825 */ /*GILLT_v8s16*//*Label 1206*/ GIMT_Encode4(40948),
14829 /* 40829 */ /*GILLT_v2s32*//*Label 1207*/ GIMT_Encode4(40985),
14830 /* 40833 */ /*GILLT_v4s32*//*Label 1208*/ GIMT_Encode4(41022),
14831 /* 40837 */ // Label 1203: @40837
14832 /* 40837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1210*/ GIMT_Encode4(40873), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1696 //
14833 /* 40844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14834 /* 40847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14835 /* 40851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14836 /* 40855 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4065:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14837 /* 40855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8),
14838 /* 40858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14839 /* 40860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14840 /* 40862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14841 /* 40865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14842 /* 40871 */ GIR_RootConstrainSelectedInstOperands,
14843 /* 40872 */ // GIR_Coverage, 1696,
14844 /* 40872 */ GIR_EraseRootFromParent_Done,
14845 /* 40873 */ // Label 1210: @40873
14846 /* 40873 */ GIM_Reject,
14847 /* 40874 */ // Label 1204: @40874
14848 /* 40874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1211*/ GIMT_Encode4(40910), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1699 //
14849 /* 40881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14850 /* 40884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14851 /* 40888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14852 /* 40892 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4065:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14853 /* 40892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8),
14854 /* 40895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14855 /* 40897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14856 /* 40899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14857 /* 40902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14858 /* 40908 */ GIR_RootConstrainSelectedInstOperands,
14859 /* 40909 */ // GIR_Coverage, 1699,
14860 /* 40909 */ GIR_EraseRootFromParent_Done,
14861 /* 40910 */ // Label 1211: @40910
14862 /* 40910 */ GIM_Reject,
14863 /* 40911 */ // Label 1205: @40911
14864 /* 40911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1212*/ GIMT_Encode4(40947), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1697 //
14865 /* 40918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14866 /* 40921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14867 /* 40925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14868 /* 40929 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4065:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14869 /* 40929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16),
14870 /* 40932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14871 /* 40934 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14872 /* 40936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14873 /* 40939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14874 /* 40945 */ GIR_RootConstrainSelectedInstOperands,
14875 /* 40946 */ // GIR_Coverage, 1697,
14876 /* 40946 */ GIR_EraseRootFromParent_Done,
14877 /* 40947 */ // Label 1212: @40947
14878 /* 40947 */ GIM_Reject,
14879 /* 40948 */ // Label 1206: @40948
14880 /* 40948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1213*/ GIMT_Encode4(40984), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1700 //
14881 /* 40955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14882 /* 40958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14883 /* 40962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14884 /* 40966 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4065:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14885 /* 40966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16),
14886 /* 40969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14887 /* 40971 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14888 /* 40973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14889 /* 40976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14890 /* 40982 */ GIR_RootConstrainSelectedInstOperands,
14891 /* 40983 */ // GIR_Coverage, 1700,
14892 /* 40983 */ GIR_EraseRootFromParent_Done,
14893 /* 40984 */ // Label 1213: @40984
14894 /* 40984 */ GIM_Reject,
14895 /* 40985 */ // Label 1207: @40985
14896 /* 40985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1214*/ GIMT_Encode4(41021), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1698 //
14897 /* 40992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14898 /* 40995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14899 /* 40999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14900 /* 41003 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4065:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14901 /* 41003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32),
14902 /* 41006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14903 /* 41008 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14904 /* 41010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14905 /* 41013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14906 /* 41019 */ GIR_RootConstrainSelectedInstOperands,
14907 /* 41020 */ // GIR_Coverage, 1698,
14908 /* 41020 */ GIR_EraseRootFromParent_Done,
14909 /* 41021 */ // Label 1214: @41021
14910 /* 41021 */ GIM_Reject,
14911 /* 41022 */ // Label 1208: @41022
14912 /* 41022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1215*/ GIMT_Encode4(41058), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1701 //
14913 /* 41029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14914 /* 41032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14915 /* 41036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14916 /* 41040 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4065:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14917 /* 41040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32),
14918 /* 41043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14919 /* 41045 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14920 /* 41047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14921 /* 41050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14922 /* 41056 */ GIR_RootConstrainSelectedInstOperands,
14923 /* 41057 */ // GIR_Coverage, 1701,
14924 /* 41057 */ GIR_EraseRootFromParent_Done,
14925 /* 41058 */ // Label 1215: @41058
14926 /* 41058 */ GIM_Reject,
14927 /* 41059 */ // Label 1209: @41059
14928 /* 41059 */ GIM_Reject,
14929 /* 41060 */ // Label 1202: @41060
14930 /* 41060 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(41213),
14931 /* 41065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
14932 /* 41070 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1220*/ GIMT_Encode4(41212),
14933 /* 41081 */ /*GILLT_v8s8*//*Label 1217*/ GIMT_Encode4(41101), GIMT_Encode4(0),
14934 /* 41089 */ /*GILLT_v4s16*//*Label 1218*/ GIMT_Encode4(41138), GIMT_Encode4(0),
14935 /* 41097 */ /*GILLT_v2s32*//*Label 1219*/ GIMT_Encode4(41175),
14936 /* 41101 */ // Label 1217: @41101
14937 /* 41101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1221*/ GIMT_Encode4(41137), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1751 //
14938 /* 41108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14939 /* 41111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14940 /* 41115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14941 /* 41119 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4062:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14942 /* 41119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8),
14943 /* 41122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14944 /* 41124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14945 /* 41126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14946 /* 41129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14947 /* 41135 */ GIR_RootConstrainSelectedInstOperands,
14948 /* 41136 */ // GIR_Coverage, 1751,
14949 /* 41136 */ GIR_EraseRootFromParent_Done,
14950 /* 41137 */ // Label 1221: @41137
14951 /* 41137 */ GIM_Reject,
14952 /* 41138 */ // Label 1218: @41138
14953 /* 41138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1222*/ GIMT_Encode4(41174), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1752 //
14954 /* 41145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14955 /* 41148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14956 /* 41152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14957 /* 41156 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4062:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14958 /* 41156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16),
14959 /* 41159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14960 /* 41161 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14961 /* 41163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14962 /* 41166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14963 /* 41172 */ GIR_RootConstrainSelectedInstOperands,
14964 /* 41173 */ // GIR_Coverage, 1752,
14965 /* 41173 */ GIR_EraseRootFromParent_Done,
14966 /* 41174 */ // Label 1222: @41174
14967 /* 41174 */ GIM_Reject,
14968 /* 41175 */ // Label 1219: @41175
14969 /* 41175 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1223*/ GIMT_Encode4(41211), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1753 //
14970 /* 41182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
14971 /* 41185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14972 /* 41189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14973 /* 41193 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4062:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14974 /* 41193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32),
14975 /* 41196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14976 /* 41198 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14977 /* 41200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14978 /* 41203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14979 /* 41209 */ GIR_RootConstrainSelectedInstOperands,
14980 /* 41210 */ // GIR_Coverage, 1753,
14981 /* 41210 */ GIR_EraseRootFromParent_Done,
14982 /* 41211 */ // Label 1223: @41211
14983 /* 41211 */ GIM_Reject,
14984 /* 41212 */ // Label 1220: @41212
14985 /* 41212 */ GIM_Reject,
14986 /* 41213 */ // Label 1216: @41213
14987 /* 41213 */ GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(41366),
14988 /* 41218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
14989 /* 41223 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1228*/ GIMT_Encode4(41365),
14990 /* 41234 */ /*GILLT_v8s8*//*Label 1225*/ GIMT_Encode4(41254), GIMT_Encode4(0),
14991 /* 41242 */ /*GILLT_v4s16*//*Label 1226*/ GIMT_Encode4(41291), GIMT_Encode4(0),
14992 /* 41250 */ /*GILLT_v2s32*//*Label 1227*/ GIMT_Encode4(41328),
14993 /* 41254 */ // Label 1225: @41254
14994 /* 41254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1229*/ GIMT_Encode4(41290), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1754 //
14995 /* 41261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14996 /* 41264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14997 /* 41268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14998 /* 41272 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4064:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14999 /* 41272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8),
15000 /* 41275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15001 /* 41277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15002 /* 41279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15003 /* 41282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15004 /* 41288 */ GIR_RootConstrainSelectedInstOperands,
15005 /* 41289 */ // GIR_Coverage, 1754,
15006 /* 41289 */ GIR_EraseRootFromParent_Done,
15007 /* 41290 */ // Label 1229: @41290
15008 /* 41290 */ GIM_Reject,
15009 /* 41291 */ // Label 1226: @41291
15010 /* 41291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1230*/ GIMT_Encode4(41327), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1755 //
15011 /* 41298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15012 /* 41301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15013 /* 41305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15014 /* 41309 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4064:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15015 /* 41309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16),
15016 /* 41312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15017 /* 41314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15018 /* 41316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15019 /* 41319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15020 /* 41325 */ GIR_RootConstrainSelectedInstOperands,
15021 /* 41326 */ // GIR_Coverage, 1755,
15022 /* 41326 */ GIR_EraseRootFromParent_Done,
15023 /* 41327 */ // Label 1230: @41327
15024 /* 41327 */ GIM_Reject,
15025 /* 41328 */ // Label 1227: @41328
15026 /* 41328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1231*/ GIMT_Encode4(41364), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1756 //
15027 /* 41335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15028 /* 41338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15029 /* 41342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15030 /* 41346 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4064:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15031 /* 41346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32),
15032 /* 41349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15033 /* 41351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15034 /* 41353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15035 /* 41356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15036 /* 41362 */ GIR_RootConstrainSelectedInstOperands,
15037 /* 41363 */ // GIR_Coverage, 1756,
15038 /* 41363 */ GIR_EraseRootFromParent_Done,
15039 /* 41364 */ // Label 1231: @41364
15040 /* 41364 */ GIM_Reject,
15041 /* 41365 */ // Label 1228: @41365
15042 /* 41365 */ GIM_Reject,
15043 /* 41366 */ // Label 1224: @41366
15044 /* 41366 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(41519),
15045 /* 41371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
15046 /* 41376 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1236*/ GIMT_Encode4(41518),
15047 /* 41387 */ /*GILLT_v8s8*//*Label 1233*/ GIMT_Encode4(41407), GIMT_Encode4(0),
15048 /* 41395 */ /*GILLT_v4s16*//*Label 1234*/ GIMT_Encode4(41444), GIMT_Encode4(0),
15049 /* 41403 */ /*GILLT_v2s32*//*Label 1235*/ GIMT_Encode4(41481),
15050 /* 41407 */ // Label 1233: @41407
15051 /* 41407 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1237*/ GIMT_Encode4(41443), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1757 //
15052 /* 41414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15053 /* 41417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15054 /* 41421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15055 /* 41425 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4063:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15056 /* 41425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8),
15057 /* 41428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15058 /* 41430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15059 /* 41432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15060 /* 41435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15061 /* 41441 */ GIR_RootConstrainSelectedInstOperands,
15062 /* 41442 */ // GIR_Coverage, 1757,
15063 /* 41442 */ GIR_EraseRootFromParent_Done,
15064 /* 41443 */ // Label 1237: @41443
15065 /* 41443 */ GIM_Reject,
15066 /* 41444 */ // Label 1234: @41444
15067 /* 41444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1238*/ GIMT_Encode4(41480), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1758 //
15068 /* 41451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15069 /* 41454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15070 /* 41458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15071 /* 41462 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4063:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15072 /* 41462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16),
15073 /* 41465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15074 /* 41467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15075 /* 41469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15076 /* 41472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15077 /* 41478 */ GIR_RootConstrainSelectedInstOperands,
15078 /* 41479 */ // GIR_Coverage, 1758,
15079 /* 41479 */ GIR_EraseRootFromParent_Done,
15080 /* 41480 */ // Label 1238: @41480
15081 /* 41480 */ GIM_Reject,
15082 /* 41481 */ // Label 1235: @41481
15083 /* 41481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1239*/ GIMT_Encode4(41517), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1759 //
15084 /* 41488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15085 /* 41491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15086 /* 41495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15087 /* 41499 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4063:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15088 /* 41499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32),
15089 /* 41502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15090 /* 41504 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15091 /* 41506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15092 /* 41509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15093 /* 41515 */ GIR_RootConstrainSelectedInstOperands,
15094 /* 41516 */ // GIR_Coverage, 1759,
15095 /* 41516 */ GIR_EraseRootFromParent_Done,
15096 /* 41517 */ // Label 1239: @41517
15097 /* 41517 */ GIM_Reject,
15098 /* 41518 */ // Label 1236: @41518
15099 /* 41518 */ GIM_Reject,
15100 /* 41519 */ // Label 1232: @41519
15101 /* 41519 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(41605),
15102 /* 41524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15103 /* 41529 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1243*/ GIMT_Encode4(41604),
15104 /* 41540 */ /*GILLT_v2s32*//*Label 1241*/ GIMT_Encode4(41548),
15105 /* 41544 */ /*GILLT_v4s32*//*Label 1242*/ GIMT_Encode4(41576),
15106 /* 41548 */ // Label 1241: @41548
15107 /* 41548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1244*/ GIMT_Encode4(41575), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1782 //
15108 /* 41555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15109 /* 41558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15110 /* 41562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15111 /* 41566 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4007:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15112 /* 41566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf),
15113 /* 41569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15114 /* 41571 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15115 /* 41573 */ GIR_RootConstrainSelectedInstOperands,
15116 /* 41574 */ // GIR_Coverage, 1782,
15117 /* 41574 */ GIR_EraseRootFromParent_Done,
15118 /* 41575 */ // Label 1244: @41575
15119 /* 41575 */ GIM_Reject,
15120 /* 41576 */ // Label 1242: @41576
15121 /* 41576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1245*/ GIMT_Encode4(41603), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1783 //
15122 /* 41583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15123 /* 41586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15124 /* 41590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15125 /* 41594 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4007:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15126 /* 41594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf),
15127 /* 41597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15128 /* 41599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15129 /* 41601 */ GIR_RootConstrainSelectedInstOperands,
15130 /* 41602 */ // GIR_Coverage, 1783,
15131 /* 41602 */ GIR_EraseRootFromParent_Done,
15132 /* 41603 */ // Label 1245: @41603
15133 /* 41603 */ GIM_Reject,
15134 /* 41604 */ // Label 1243: @41604
15135 /* 41604 */ GIM_Reject,
15136 /* 41605 */ // Label 1240: @41605
15137 /* 41605 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(41691),
15138 /* 41610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15139 /* 41615 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1249*/ GIMT_Encode4(41690),
15140 /* 41626 */ /*GILLT_v2s32*//*Label 1247*/ GIMT_Encode4(41634),
15141 /* 41630 */ /*GILLT_v4s32*//*Label 1248*/ GIMT_Encode4(41662),
15142 /* 41634 */ // Label 1247: @41634
15143 /* 41634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1250*/ GIMT_Encode4(41661), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1784 //
15144 /* 41641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15145 /* 41644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15146 /* 41648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15147 /* 41652 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4008:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15148 /* 41652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf),
15149 /* 41655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15150 /* 41657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15151 /* 41659 */ GIR_RootConstrainSelectedInstOperands,
15152 /* 41660 */ // GIR_Coverage, 1784,
15153 /* 41660 */ GIR_EraseRootFromParent_Done,
15154 /* 41661 */ // Label 1250: @41661
15155 /* 41661 */ GIM_Reject,
15156 /* 41662 */ // Label 1248: @41662
15157 /* 41662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1251*/ GIMT_Encode4(41689), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1785 //
15158 /* 41669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15159 /* 41672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15160 /* 41676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15161 /* 41680 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4008:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15162 /* 41680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf),
15163 /* 41683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15164 /* 41685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15165 /* 41687 */ GIR_RootConstrainSelectedInstOperands,
15166 /* 41688 */ // GIR_Coverage, 1785,
15167 /* 41688 */ GIR_EraseRootFromParent_Done,
15168 /* 41689 */ // Label 1251: @41689
15169 /* 41689 */ GIM_Reject,
15170 /* 41690 */ // Label 1249: @41690
15171 /* 41690 */ GIM_Reject,
15172 /* 41691 */ // Label 1246: @41691
15173 /* 41691 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(41777),
15174 /* 41696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15175 /* 41701 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1255*/ GIMT_Encode4(41776),
15176 /* 41712 */ /*GILLT_v4s16*//*Label 1253*/ GIMT_Encode4(41720),
15177 /* 41716 */ /*GILLT_v8s16*//*Label 1254*/ GIMT_Encode4(41748),
15178 /* 41720 */ // Label 1253: @41720
15179 /* 41720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1256*/ GIMT_Encode4(41747), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1786 //
15180 /* 41727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15181 /* 41730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15182 /* 41734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15183 /* 41738 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4007:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15184 /* 41738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh),
15185 /* 41741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15186 /* 41743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15187 /* 41745 */ GIR_RootConstrainSelectedInstOperands,
15188 /* 41746 */ // GIR_Coverage, 1786,
15189 /* 41746 */ GIR_EraseRootFromParent_Done,
15190 /* 41747 */ // Label 1256: @41747
15191 /* 41747 */ GIM_Reject,
15192 /* 41748 */ // Label 1254: @41748
15193 /* 41748 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1257*/ GIMT_Encode4(41775), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1787 //
15194 /* 41755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15195 /* 41758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15196 /* 41762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15197 /* 41766 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4007:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15198 /* 41766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh),
15199 /* 41769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15200 /* 41771 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15201 /* 41773 */ GIR_RootConstrainSelectedInstOperands,
15202 /* 41774 */ // GIR_Coverage, 1787,
15203 /* 41774 */ GIR_EraseRootFromParent_Done,
15204 /* 41775 */ // Label 1257: @41775
15205 /* 41775 */ GIM_Reject,
15206 /* 41776 */ // Label 1255: @41776
15207 /* 41776 */ GIM_Reject,
15208 /* 41777 */ // Label 1252: @41777
15209 /* 41777 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(41863),
15210 /* 41782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15211 /* 41787 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1261*/ GIMT_Encode4(41862),
15212 /* 41798 */ /*GILLT_v4s16*//*Label 1259*/ GIMT_Encode4(41806),
15213 /* 41802 */ /*GILLT_v8s16*//*Label 1260*/ GIMT_Encode4(41834),
15214 /* 41806 */ // Label 1259: @41806
15215 /* 41806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1262*/ GIMT_Encode4(41833), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1788 //
15216 /* 41813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15217 /* 41816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15218 /* 41820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15219 /* 41824 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4008:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15220 /* 41824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh),
15221 /* 41827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15222 /* 41829 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15223 /* 41831 */ GIR_RootConstrainSelectedInstOperands,
15224 /* 41832 */ // GIR_Coverage, 1788,
15225 /* 41832 */ GIR_EraseRootFromParent_Done,
15226 /* 41833 */ // Label 1262: @41833
15227 /* 41833 */ GIM_Reject,
15228 /* 41834 */ // Label 1260: @41834
15229 /* 41834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1263*/ GIMT_Encode4(41861), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1789 //
15230 /* 41841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15231 /* 41844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15232 /* 41848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15233 /* 41852 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4008:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15234 /* 41852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh),
15235 /* 41855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15236 /* 41857 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15237 /* 41859 */ GIR_RootConstrainSelectedInstOperands,
15238 /* 41860 */ // GIR_Coverage, 1789,
15239 /* 41860 */ GIR_EraseRootFromParent_Done,
15240 /* 41861 */ // Label 1263: @41861
15241 /* 41861 */ GIM_Reject,
15242 /* 41862 */ // Label 1261: @41862
15243 /* 41862 */ GIM_Reject,
15244 /* 41863 */ // Label 1258: @41863
15245 /* 41863 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(41949),
15246 /* 41868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15247 /* 41873 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1267*/ GIMT_Encode4(41948),
15248 /* 41884 */ /*GILLT_v2s32*//*Label 1265*/ GIMT_Encode4(41892),
15249 /* 41888 */ /*GILLT_v4s32*//*Label 1266*/ GIMT_Encode4(41920),
15250 /* 41892 */ // Label 1265: @41892
15251 /* 41892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1268*/ GIMT_Encode4(41919), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1790 //
15252 /* 41899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15253 /* 41902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15254 /* 41906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15255 /* 41910 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4019:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15256 /* 41910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf),
15257 /* 41913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15258 /* 41915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15259 /* 41917 */ GIR_RootConstrainSelectedInstOperands,
15260 /* 41918 */ // GIR_Coverage, 1790,
15261 /* 41918 */ GIR_EraseRootFromParent_Done,
15262 /* 41919 */ // Label 1268: @41919
15263 /* 41919 */ GIM_Reject,
15264 /* 41920 */ // Label 1266: @41920
15265 /* 41920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1269*/ GIMT_Encode4(41947), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1791 //
15266 /* 41927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15267 /* 41930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15268 /* 41934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15269 /* 41938 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4019:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15270 /* 41938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf),
15271 /* 41941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15272 /* 41943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15273 /* 41945 */ GIR_RootConstrainSelectedInstOperands,
15274 /* 41946 */ // GIR_Coverage, 1791,
15275 /* 41946 */ GIR_EraseRootFromParent_Done,
15276 /* 41947 */ // Label 1269: @41947
15277 /* 41947 */ GIM_Reject,
15278 /* 41948 */ // Label 1267: @41948
15279 /* 41948 */ GIM_Reject,
15280 /* 41949 */ // Label 1264: @41949
15281 /* 41949 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(42035),
15282 /* 41954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15283 /* 41959 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1273*/ GIMT_Encode4(42034),
15284 /* 41970 */ /*GILLT_v2s32*//*Label 1271*/ GIMT_Encode4(41978),
15285 /* 41974 */ /*GILLT_v4s32*//*Label 1272*/ GIMT_Encode4(42006),
15286 /* 41978 */ // Label 1271: @41978
15287 /* 41978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1274*/ GIMT_Encode4(42005), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1792 //
15288 /* 41985 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15289 /* 41988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15290 /* 41992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15291 /* 41996 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4020:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15292 /* 41996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf),
15293 /* 41999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15294 /* 42001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15295 /* 42003 */ GIR_RootConstrainSelectedInstOperands,
15296 /* 42004 */ // GIR_Coverage, 1792,
15297 /* 42004 */ GIR_EraseRootFromParent_Done,
15298 /* 42005 */ // Label 1274: @42005
15299 /* 42005 */ GIM_Reject,
15300 /* 42006 */ // Label 1272: @42006
15301 /* 42006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1275*/ GIMT_Encode4(42033), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1793 //
15302 /* 42013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15303 /* 42016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15304 /* 42020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15305 /* 42024 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4020:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15306 /* 42024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf),
15307 /* 42027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15308 /* 42029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15309 /* 42031 */ GIR_RootConstrainSelectedInstOperands,
15310 /* 42032 */ // GIR_Coverage, 1793,
15311 /* 42032 */ GIR_EraseRootFromParent_Done,
15312 /* 42033 */ // Label 1275: @42033
15313 /* 42033 */ GIM_Reject,
15314 /* 42034 */ // Label 1273: @42034
15315 /* 42034 */ GIM_Reject,
15316 /* 42035 */ // Label 1270: @42035
15317 /* 42035 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(42121),
15318 /* 42040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15319 /* 42045 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1279*/ GIMT_Encode4(42120),
15320 /* 42056 */ /*GILLT_v4s16*//*Label 1277*/ GIMT_Encode4(42064),
15321 /* 42060 */ /*GILLT_v8s16*//*Label 1278*/ GIMT_Encode4(42092),
15322 /* 42064 */ // Label 1277: @42064
15323 /* 42064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1280*/ GIMT_Encode4(42091), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1794 //
15324 /* 42071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15325 /* 42074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15326 /* 42078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15327 /* 42082 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4019:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15328 /* 42082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh),
15329 /* 42085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15330 /* 42087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15331 /* 42089 */ GIR_RootConstrainSelectedInstOperands,
15332 /* 42090 */ // GIR_Coverage, 1794,
15333 /* 42090 */ GIR_EraseRootFromParent_Done,
15334 /* 42091 */ // Label 1280: @42091
15335 /* 42091 */ GIM_Reject,
15336 /* 42092 */ // Label 1278: @42092
15337 /* 42092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1281*/ GIMT_Encode4(42119), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1795 //
15338 /* 42099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15339 /* 42102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15340 /* 42106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15341 /* 42110 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4019:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15342 /* 42110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh),
15343 /* 42113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15344 /* 42115 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15345 /* 42117 */ GIR_RootConstrainSelectedInstOperands,
15346 /* 42118 */ // GIR_Coverage, 1795,
15347 /* 42118 */ GIR_EraseRootFromParent_Done,
15348 /* 42119 */ // Label 1281: @42119
15349 /* 42119 */ GIM_Reject,
15350 /* 42120 */ // Label 1279: @42120
15351 /* 42120 */ GIM_Reject,
15352 /* 42121 */ // Label 1276: @42121
15353 /* 42121 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(42207),
15354 /* 42126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15355 /* 42131 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1285*/ GIMT_Encode4(42206),
15356 /* 42142 */ /*GILLT_v4s16*//*Label 1283*/ GIMT_Encode4(42150),
15357 /* 42146 */ /*GILLT_v8s16*//*Label 1284*/ GIMT_Encode4(42178),
15358 /* 42150 */ // Label 1283: @42150
15359 /* 42150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1286*/ GIMT_Encode4(42177), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1796 //
15360 /* 42157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15361 /* 42160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15362 /* 42164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15363 /* 42168 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4020:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15364 /* 42168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh),
15365 /* 42171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15366 /* 42173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15367 /* 42175 */ GIR_RootConstrainSelectedInstOperands,
15368 /* 42176 */ // GIR_Coverage, 1796,
15369 /* 42176 */ GIR_EraseRootFromParent_Done,
15370 /* 42177 */ // Label 1286: @42177
15371 /* 42177 */ GIM_Reject,
15372 /* 42178 */ // Label 1284: @42178
15373 /* 42178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1287*/ GIMT_Encode4(42205), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1797 //
15374 /* 42185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15375 /* 42188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15376 /* 42192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15377 /* 42196 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4020:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15378 /* 42196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh),
15379 /* 42199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15380 /* 42201 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15381 /* 42203 */ GIR_RootConstrainSelectedInstOperands,
15382 /* 42204 */ // GIR_Coverage, 1797,
15383 /* 42204 */ GIR_EraseRootFromParent_Done,
15384 /* 42205 */ // Label 1287: @42205
15385 /* 42205 */ GIM_Reject,
15386 /* 42206 */ // Label 1285: @42206
15387 /* 42206 */ GIM_Reject,
15388 /* 42207 */ // Label 1282: @42207
15389 /* 42207 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(42293),
15390 /* 42212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15391 /* 42217 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1291*/ GIMT_Encode4(42292),
15392 /* 42228 */ /*GILLT_v2s32*//*Label 1289*/ GIMT_Encode4(42236),
15393 /* 42232 */ /*GILLT_v4s32*//*Label 1290*/ GIMT_Encode4(42264),
15394 /* 42236 */ // Label 1289: @42236
15395 /* 42236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1292*/ GIMT_Encode4(42263), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1798 //
15396 /* 42243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15397 /* 42246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15398 /* 42250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15399 /* 42254 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4021:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15400 /* 42254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf),
15401 /* 42257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15402 /* 42259 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15403 /* 42261 */ GIR_RootConstrainSelectedInstOperands,
15404 /* 42262 */ // GIR_Coverage, 1798,
15405 /* 42262 */ GIR_EraseRootFromParent_Done,
15406 /* 42263 */ // Label 1292: @42263
15407 /* 42263 */ GIM_Reject,
15408 /* 42264 */ // Label 1290: @42264
15409 /* 42264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1293*/ GIMT_Encode4(42291), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1799 //
15410 /* 42271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15411 /* 42274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15412 /* 42278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15413 /* 42282 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4021:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15414 /* 42282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf),
15415 /* 42285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15416 /* 42287 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15417 /* 42289 */ GIR_RootConstrainSelectedInstOperands,
15418 /* 42290 */ // GIR_Coverage, 1799,
15419 /* 42290 */ GIR_EraseRootFromParent_Done,
15420 /* 42291 */ // Label 1293: @42291
15421 /* 42291 */ GIM_Reject,
15422 /* 42292 */ // Label 1291: @42292
15423 /* 42292 */ GIM_Reject,
15424 /* 42293 */ // Label 1288: @42293
15425 /* 42293 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(42379),
15426 /* 42298 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15427 /* 42303 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1297*/ GIMT_Encode4(42378),
15428 /* 42314 */ /*GILLT_v2s32*//*Label 1295*/ GIMT_Encode4(42322),
15429 /* 42318 */ /*GILLT_v4s32*//*Label 1296*/ GIMT_Encode4(42350),
15430 /* 42322 */ // Label 1295: @42322
15431 /* 42322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1298*/ GIMT_Encode4(42349), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1800 //
15432 /* 42329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15433 /* 42332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15434 /* 42336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15435 /* 42340 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4022:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15436 /* 42340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf),
15437 /* 42343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15438 /* 42345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15439 /* 42347 */ GIR_RootConstrainSelectedInstOperands,
15440 /* 42348 */ // GIR_Coverage, 1800,
15441 /* 42348 */ GIR_EraseRootFromParent_Done,
15442 /* 42349 */ // Label 1298: @42349
15443 /* 42349 */ GIM_Reject,
15444 /* 42350 */ // Label 1296: @42350
15445 /* 42350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1299*/ GIMT_Encode4(42377), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1801 //
15446 /* 42357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15447 /* 42360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15448 /* 42364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15449 /* 42368 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4022:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15450 /* 42368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf),
15451 /* 42371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15452 /* 42373 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15453 /* 42375 */ GIR_RootConstrainSelectedInstOperands,
15454 /* 42376 */ // GIR_Coverage, 1801,
15455 /* 42376 */ GIR_EraseRootFromParent_Done,
15456 /* 42377 */ // Label 1299: @42377
15457 /* 42377 */ GIM_Reject,
15458 /* 42378 */ // Label 1297: @42378
15459 /* 42378 */ GIM_Reject,
15460 /* 42379 */ // Label 1294: @42379
15461 /* 42379 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(42465),
15462 /* 42384 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15463 /* 42389 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1303*/ GIMT_Encode4(42464),
15464 /* 42400 */ /*GILLT_v4s16*//*Label 1301*/ GIMT_Encode4(42408),
15465 /* 42404 */ /*GILLT_v8s16*//*Label 1302*/ GIMT_Encode4(42436),
15466 /* 42408 */ // Label 1301: @42408
15467 /* 42408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1304*/ GIMT_Encode4(42435), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1802 //
15468 /* 42415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15469 /* 42418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15470 /* 42422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15471 /* 42426 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4021:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15472 /* 42426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh),
15473 /* 42429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15474 /* 42431 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15475 /* 42433 */ GIR_RootConstrainSelectedInstOperands,
15476 /* 42434 */ // GIR_Coverage, 1802,
15477 /* 42434 */ GIR_EraseRootFromParent_Done,
15478 /* 42435 */ // Label 1304: @42435
15479 /* 42435 */ GIM_Reject,
15480 /* 42436 */ // Label 1302: @42436
15481 /* 42436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1305*/ GIMT_Encode4(42463), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1803 //
15482 /* 42443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15483 /* 42446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15484 /* 42450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15485 /* 42454 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4021:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15486 /* 42454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh),
15487 /* 42457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15488 /* 42459 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15489 /* 42461 */ GIR_RootConstrainSelectedInstOperands,
15490 /* 42462 */ // GIR_Coverage, 1803,
15491 /* 42462 */ GIR_EraseRootFromParent_Done,
15492 /* 42463 */ // Label 1305: @42463
15493 /* 42463 */ GIM_Reject,
15494 /* 42464 */ // Label 1303: @42464
15495 /* 42464 */ GIM_Reject,
15496 /* 42465 */ // Label 1300: @42465
15497 /* 42465 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(42551),
15498 /* 42470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15499 /* 42475 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1309*/ GIMT_Encode4(42550),
15500 /* 42486 */ /*GILLT_v4s16*//*Label 1307*/ GIMT_Encode4(42494),
15501 /* 42490 */ /*GILLT_v8s16*//*Label 1308*/ GIMT_Encode4(42522),
15502 /* 42494 */ // Label 1307: @42494
15503 /* 42494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1310*/ GIMT_Encode4(42521), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1804 //
15504 /* 42501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15505 /* 42504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15506 /* 42508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15507 /* 42512 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4022:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15508 /* 42512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh),
15509 /* 42515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15510 /* 42517 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15511 /* 42519 */ GIR_RootConstrainSelectedInstOperands,
15512 /* 42520 */ // GIR_Coverage, 1804,
15513 /* 42520 */ GIR_EraseRootFromParent_Done,
15514 /* 42521 */ // Label 1310: @42521
15515 /* 42521 */ GIM_Reject,
15516 /* 42522 */ // Label 1308: @42522
15517 /* 42522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1311*/ GIMT_Encode4(42549), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1805 //
15518 /* 42529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15519 /* 42532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15520 /* 42536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15521 /* 42540 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4022:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15522 /* 42540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh),
15523 /* 42543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15524 /* 42545 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15525 /* 42547 */ GIR_RootConstrainSelectedInstOperands,
15526 /* 42548 */ // GIR_Coverage, 1805,
15527 /* 42548 */ GIR_EraseRootFromParent_Done,
15528 /* 42549 */ // Label 1311: @42549
15529 /* 42549 */ GIM_Reject,
15530 /* 42550 */ // Label 1309: @42550
15531 /* 42550 */ GIM_Reject,
15532 /* 42551 */ // Label 1306: @42551
15533 /* 42551 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(42637),
15534 /* 42556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15535 /* 42561 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1315*/ GIMT_Encode4(42636),
15536 /* 42572 */ /*GILLT_v2s32*//*Label 1313*/ GIMT_Encode4(42580),
15537 /* 42576 */ /*GILLT_v4s32*//*Label 1314*/ GIMT_Encode4(42608),
15538 /* 42580 */ // Label 1313: @42580
15539 /* 42580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1316*/ GIMT_Encode4(42607), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1806 //
15540 /* 42587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15541 /* 42590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15542 /* 42594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15543 /* 42598 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4017:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15544 /* 42598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf),
15545 /* 42601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15546 /* 42603 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15547 /* 42605 */ GIR_RootConstrainSelectedInstOperands,
15548 /* 42606 */ // GIR_Coverage, 1806,
15549 /* 42606 */ GIR_EraseRootFromParent_Done,
15550 /* 42607 */ // Label 1316: @42607
15551 /* 42607 */ GIM_Reject,
15552 /* 42608 */ // Label 1314: @42608
15553 /* 42608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1317*/ GIMT_Encode4(42635), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1807 //
15554 /* 42615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15555 /* 42618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15556 /* 42622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15557 /* 42626 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4017:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15558 /* 42626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf),
15559 /* 42629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15560 /* 42631 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15561 /* 42633 */ GIR_RootConstrainSelectedInstOperands,
15562 /* 42634 */ // GIR_Coverage, 1807,
15563 /* 42634 */ GIR_EraseRootFromParent_Done,
15564 /* 42635 */ // Label 1317: @42635
15565 /* 42635 */ GIM_Reject,
15566 /* 42636 */ // Label 1315: @42636
15567 /* 42636 */ GIM_Reject,
15568 /* 42637 */ // Label 1312: @42637
15569 /* 42637 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(42723),
15570 /* 42642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15571 /* 42647 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1321*/ GIMT_Encode4(42722),
15572 /* 42658 */ /*GILLT_v2s32*//*Label 1319*/ GIMT_Encode4(42666),
15573 /* 42662 */ /*GILLT_v4s32*//*Label 1320*/ GIMT_Encode4(42694),
15574 /* 42666 */ // Label 1319: @42666
15575 /* 42666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1322*/ GIMT_Encode4(42693), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1808 //
15576 /* 42673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15577 /* 42676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15578 /* 42680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15579 /* 42684 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4018:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15580 /* 42684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf),
15581 /* 42687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15582 /* 42689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15583 /* 42691 */ GIR_RootConstrainSelectedInstOperands,
15584 /* 42692 */ // GIR_Coverage, 1808,
15585 /* 42692 */ GIR_EraseRootFromParent_Done,
15586 /* 42693 */ // Label 1322: @42693
15587 /* 42693 */ GIM_Reject,
15588 /* 42694 */ // Label 1320: @42694
15589 /* 42694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1323*/ GIMT_Encode4(42721), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1809 //
15590 /* 42701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15591 /* 42704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15592 /* 42708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15593 /* 42712 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4018:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15594 /* 42712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf),
15595 /* 42715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15596 /* 42717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15597 /* 42719 */ GIR_RootConstrainSelectedInstOperands,
15598 /* 42720 */ // GIR_Coverage, 1809,
15599 /* 42720 */ GIR_EraseRootFromParent_Done,
15600 /* 42721 */ // Label 1323: @42721
15601 /* 42721 */ GIM_Reject,
15602 /* 42722 */ // Label 1321: @42722
15603 /* 42722 */ GIM_Reject,
15604 /* 42723 */ // Label 1318: @42723
15605 /* 42723 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(42809),
15606 /* 42728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15607 /* 42733 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1327*/ GIMT_Encode4(42808),
15608 /* 42744 */ /*GILLT_v4s16*//*Label 1325*/ GIMT_Encode4(42752),
15609 /* 42748 */ /*GILLT_v8s16*//*Label 1326*/ GIMT_Encode4(42780),
15610 /* 42752 */ // Label 1325: @42752
15611 /* 42752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1328*/ GIMT_Encode4(42779), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1810 //
15612 /* 42759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15613 /* 42762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15614 /* 42766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15615 /* 42770 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4017:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15616 /* 42770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh),
15617 /* 42773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15618 /* 42775 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15619 /* 42777 */ GIR_RootConstrainSelectedInstOperands,
15620 /* 42778 */ // GIR_Coverage, 1810,
15621 /* 42778 */ GIR_EraseRootFromParent_Done,
15622 /* 42779 */ // Label 1328: @42779
15623 /* 42779 */ GIM_Reject,
15624 /* 42780 */ // Label 1326: @42780
15625 /* 42780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1329*/ GIMT_Encode4(42807), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1811 //
15626 /* 42787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15627 /* 42790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15628 /* 42794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15629 /* 42798 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4017:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15630 /* 42798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh),
15631 /* 42801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15632 /* 42803 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15633 /* 42805 */ GIR_RootConstrainSelectedInstOperands,
15634 /* 42806 */ // GIR_Coverage, 1811,
15635 /* 42806 */ GIR_EraseRootFromParent_Done,
15636 /* 42807 */ // Label 1329: @42807
15637 /* 42807 */ GIM_Reject,
15638 /* 42808 */ // Label 1327: @42808
15639 /* 42808 */ GIM_Reject,
15640 /* 42809 */ // Label 1324: @42809
15641 /* 42809 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(42895),
15642 /* 42814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15643 /* 42819 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1333*/ GIMT_Encode4(42894),
15644 /* 42830 */ /*GILLT_v4s16*//*Label 1331*/ GIMT_Encode4(42838),
15645 /* 42834 */ /*GILLT_v8s16*//*Label 1332*/ GIMT_Encode4(42866),
15646 /* 42838 */ // Label 1331: @42838
15647 /* 42838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1334*/ GIMT_Encode4(42865), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1812 //
15648 /* 42845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15649 /* 42848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15650 /* 42852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15651 /* 42856 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4018:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15652 /* 42856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh),
15653 /* 42859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15654 /* 42861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15655 /* 42863 */ GIR_RootConstrainSelectedInstOperands,
15656 /* 42864 */ // GIR_Coverage, 1812,
15657 /* 42864 */ GIR_EraseRootFromParent_Done,
15658 /* 42865 */ // Label 1334: @42865
15659 /* 42865 */ GIM_Reject,
15660 /* 42866 */ // Label 1332: @42866
15661 /* 42866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1335*/ GIMT_Encode4(42893), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1813 //
15662 /* 42873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15663 /* 42876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15664 /* 42880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15665 /* 42884 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4018:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15666 /* 42884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh),
15667 /* 42887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15668 /* 42889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15669 /* 42891 */ GIR_RootConstrainSelectedInstOperands,
15670 /* 42892 */ // GIR_Coverage, 1813,
15671 /* 42892 */ GIR_EraseRootFromParent_Done,
15672 /* 42893 */ // Label 1335: @42893
15673 /* 42893 */ GIM_Reject,
15674 /* 42894 */ // Label 1333: @42894
15675 /* 42894 */ GIM_Reject,
15676 /* 42895 */ // Label 1330: @42895
15677 /* 42895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1336*/ GIMT_Encode4(42939), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1830 //
15678 /* 42902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf),
15679 /* 42907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15680 /* 42910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15681 /* 42913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15682 /* 42917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15683 /* 42921 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4013:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
15684 /* 42921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
15685 /* 42924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15686 /* 42926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15687 /* 42928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15688 /* 42931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15689 /* 42937 */ GIR_RootConstrainSelectedInstOperands,
15690 /* 42938 */ // GIR_Coverage, 1830,
15691 /* 42938 */ GIR_EraseRootFromParent_Done,
15692 /* 42939 */ // Label 1336: @42939
15693 /* 42939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1337*/ GIMT_Encode4(42983), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1831 //
15694 /* 42946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp),
15695 /* 42951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15696 /* 42954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15697 /* 42957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15698 /* 42961 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15699 /* 42965 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
15700 /* 42965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
15701 /* 42968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15702 /* 42970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15703 /* 42972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15704 /* 42975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15705 /* 42981 */ GIR_RootConstrainSelectedInstOperands,
15706 /* 42982 */ // GIR_Coverage, 1831,
15707 /* 42982 */ GIR_EraseRootFromParent_Done,
15708 /* 42983 */ // Label 1337: @42983
15709 /* 42983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1338*/ GIMT_Encode4(43018), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1903 //
15710 /* 42990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc),
15711 /* 42995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15712 /* 42998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15713 /* 43001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15714 /* 43005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15715 /* 43009 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3976:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15716 /* 43009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC),
15717 /* 43012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15718 /* 43014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15719 /* 43016 */ GIR_RootConstrainSelectedInstOperands,
15720 /* 43017 */ // GIR_Coverage, 1903,
15721 /* 43017 */ GIR_EraseRootFromParent_Done,
15722 /* 43018 */ // Label 1338: @43018
15723 /* 43018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1339*/ GIMT_Encode4(43053), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1904 //
15724 /* 43025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc),
15725 /* 43030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15726 /* 43033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15727 /* 43036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15728 /* 43040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15729 /* 43044 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3977:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15730 /* 43044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC),
15731 /* 43047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15732 /* 43049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15733 /* 43051 */ GIR_RootConstrainSelectedInstOperands,
15734 /* 43052 */ // GIR_Coverage, 1904,
15735 /* 43052 */ GIR_EraseRootFromParent_Done,
15736 /* 43053 */ // Label 1339: @43053
15737 /* 43053 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(43142),
15738 /* 43058 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
15739 /* 43063 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15740 /* 43066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15741 /* 43069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1341*/ GIMT_Encode4(43105), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2039 //
15742 /* 43076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
15743 /* 43080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
15744 /* 43084 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
15745 /* 43084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16),
15746 /* 43087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15747 /* 43089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
15748 /* 43091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15749 /* 43094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15750 /* 43097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15751 /* 43103 */ GIR_RootConstrainSelectedInstOperands,
15752 /* 43104 */ // GIR_Coverage, 2039,
15753 /* 43104 */ GIR_EraseRootFromParent_Done,
15754 /* 43105 */ // Label 1341: @43105
15755 /* 43105 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1342*/ GIMT_Encode4(43141), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2295 //
15756 /* 43112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15757 /* 43116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15758 /* 43120 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
15759 /* 43120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16),
15760 /* 43123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15761 /* 43125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
15762 /* 43127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15763 /* 43130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15764 /* 43133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15765 /* 43139 */ GIR_RootConstrainSelectedInstOperands,
15766 /* 43140 */ // GIR_Coverage, 2295,
15767 /* 43140 */ GIR_EraseRootFromParent_Done,
15768 /* 43141 */ // Label 1342: @43141
15769 /* 43141 */ GIM_Reject,
15770 /* 43142 */ // Label 1340: @43142
15771 /* 43142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1343*/ GIMT_Encode4(43207), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4369 //
15772 /* 43149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
15773 /* 43154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15774 /* 43157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15775 /* 43160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15776 /* 43164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15777 /* 43168 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15778 /* 43168 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15779 /* 43171 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15780 /* 43175 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15781 /* 43180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
15782 /* 43183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15783 /* 43185 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15784 /* 43187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15785 /* 43190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15786 /* 43196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15787 /* 43202 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15788 /* 43205 */ GIR_RootConstrainSelectedInstOperands,
15789 /* 43206 */ // GIR_Coverage, 4369,
15790 /* 43206 */ GIR_EraseRootFromParent_Done,
15791 /* 43207 */ // Label 1343: @43207
15792 /* 43207 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1344*/ GIMT_Encode4(43272), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4373 //
15793 /* 43214 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
15794 /* 43219 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15795 /* 43222 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15796 /* 43225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15797 /* 43229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15798 /* 43233 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3940:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15799 /* 43233 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15800 /* 43236 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15801 /* 43240 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15802 /* 43245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
15803 /* 43248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15804 /* 43250 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15805 /* 43252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15806 /* 43255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15807 /* 43261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15808 /* 43267 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15809 /* 43270 */ GIR_RootConstrainSelectedInstOperands,
15810 /* 43271 */ // GIR_Coverage, 4373,
15811 /* 43271 */ GIR_EraseRootFromParent_Done,
15812 /* 43272 */ // Label 1344: @43272
15813 /* 43272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1345*/ GIMT_Encode4(43337), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4377 //
15814 /* 43279 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
15815 /* 43284 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15816 /* 43287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15817 /* 43290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15818 /* 43294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15819 /* 43298 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3932:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15820 /* 43298 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15821 /* 43301 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15822 /* 43305 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15823 /* 43310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
15824 /* 43313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15825 /* 43315 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15826 /* 43317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15827 /* 43320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15828 /* 43326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15829 /* 43332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15830 /* 43335 */ GIR_RootConstrainSelectedInstOperands,
15831 /* 43336 */ // GIR_Coverage, 4377,
15832 /* 43336 */ GIR_EraseRootFromParent_Done,
15833 /* 43337 */ // Label 1345: @43337
15834 /* 43337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1346*/ GIMT_Encode4(43402), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4381 //
15835 /* 43344 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
15836 /* 43349 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15837 /* 43352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15838 /* 43355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15839 /* 43359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15840 /* 43363 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15841 /* 43363 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15842 /* 43366 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15843 /* 43370 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15844 /* 43375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
15845 /* 43378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15846 /* 43380 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15847 /* 43382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15848 /* 43385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15849 /* 43391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15850 /* 43397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15851 /* 43400 */ GIR_RootConstrainSelectedInstOperands,
15852 /* 43401 */ // GIR_Coverage, 4381,
15853 /* 43401 */ GIR_EraseRootFromParent_Done,
15854 /* 43402 */ // Label 1346: @43402
15855 /* 43402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1347*/ GIMT_Encode4(43467), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4385 //
15856 /* 43409 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
15857 /* 43414 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15858 /* 43417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15859 /* 43420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15860 /* 43424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15861 /* 43428 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15862 /* 43428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15863 /* 43431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15864 /* 43435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15865 /* 43440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
15866 /* 43443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15867 /* 43445 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15868 /* 43447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15869 /* 43450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15870 /* 43456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15871 /* 43462 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15872 /* 43465 */ GIR_RootConstrainSelectedInstOperands,
15873 /* 43466 */ // GIR_Coverage, 4385,
15874 /* 43466 */ GIR_EraseRootFromParent_Done,
15875 /* 43467 */ // Label 1347: @43467
15876 /* 43467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1348*/ GIMT_Encode4(43532), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4389 //
15877 /* 43474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
15878 /* 43479 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15879 /* 43482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15880 /* 43485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15881 /* 43489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15882 /* 43493 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3938:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15883 /* 43493 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15884 /* 43496 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15885 /* 43500 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15886 /* 43505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
15887 /* 43508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15888 /* 43510 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15889 /* 43512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15890 /* 43515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15891 /* 43521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15892 /* 43527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15893 /* 43530 */ GIR_RootConstrainSelectedInstOperands,
15894 /* 43531 */ // GIR_Coverage, 4389,
15895 /* 43531 */ GIR_EraseRootFromParent_Done,
15896 /* 43532 */ // Label 1348: @43532
15897 /* 43532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1349*/ GIMT_Encode4(43597), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4393 //
15898 /* 43539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
15899 /* 43544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15900 /* 43547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15901 /* 43550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15902 /* 43554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15903 /* 43558 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15904 /* 43558 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15905 /* 43561 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15906 /* 43565 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15907 /* 43570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
15908 /* 43573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15909 /* 43575 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15910 /* 43577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15911 /* 43580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15912 /* 43586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15913 /* 43592 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15914 /* 43595 */ GIR_RootConstrainSelectedInstOperands,
15915 /* 43596 */ // GIR_Coverage, 4393,
15916 /* 43596 */ GIR_EraseRootFromParent_Done,
15917 /* 43597 */ // Label 1349: @43597
15918 /* 43597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1350*/ GIMT_Encode4(43662), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4397 //
15919 /* 43604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
15920 /* 43609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15921 /* 43612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15922 /* 43615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15923 /* 43619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15924 /* 43623 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3940:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15925 /* 43623 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15926 /* 43626 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15927 /* 43630 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15928 /* 43635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
15929 /* 43638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15930 /* 43640 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15931 /* 43642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15932 /* 43645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15933 /* 43651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15934 /* 43657 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15935 /* 43660 */ GIR_RootConstrainSelectedInstOperands,
15936 /* 43661 */ // GIR_Coverage, 4397,
15937 /* 43661 */ GIR_EraseRootFromParent_Done,
15938 /* 43662 */ // Label 1350: @43662
15939 /* 43662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1351*/ GIMT_Encode4(43727), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4401 //
15940 /* 43669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
15941 /* 43674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15942 /* 43677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15943 /* 43680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15944 /* 43684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15945 /* 43688 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3932:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15946 /* 43688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15947 /* 43691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15948 /* 43695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15949 /* 43700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
15950 /* 43703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15951 /* 43705 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15952 /* 43707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15953 /* 43710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15954 /* 43716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15955 /* 43722 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15956 /* 43725 */ GIR_RootConstrainSelectedInstOperands,
15957 /* 43726 */ // GIR_Coverage, 4401,
15958 /* 43726 */ GIR_EraseRootFromParent_Done,
15959 /* 43727 */ // Label 1351: @43727
15960 /* 43727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1352*/ GIMT_Encode4(43792), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4405 //
15961 /* 43734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
15962 /* 43739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15963 /* 43742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15964 /* 43745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15965 /* 43749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15966 /* 43753 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15967 /* 43753 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15968 /* 43756 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15969 /* 43760 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15970 /* 43765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
15971 /* 43768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15972 /* 43770 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15973 /* 43772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15974 /* 43775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15975 /* 43781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15976 /* 43787 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15977 /* 43790 */ GIR_RootConstrainSelectedInstOperands,
15978 /* 43791 */ // GIR_Coverage, 4405,
15979 /* 43791 */ GIR_EraseRootFromParent_Done,
15980 /* 43792 */ // Label 1352: @43792
15981 /* 43792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1353*/ GIMT_Encode4(43857), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4409 //
15982 /* 43799 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
15983 /* 43804 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15984 /* 43807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15985 /* 43810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15986 /* 43814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15987 /* 43818 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15988 /* 43818 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15989 /* 43821 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15990 /* 43825 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15991 /* 43830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
15992 /* 43833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15993 /* 43835 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15994 /* 43837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15995 /* 43840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15996 /* 43846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15997 /* 43852 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15998 /* 43855 */ GIR_RootConstrainSelectedInstOperands,
15999 /* 43856 */ // GIR_Coverage, 4409,
16000 /* 43856 */ GIR_EraseRootFromParent_Done,
16001 /* 43857 */ // Label 1353: @43857
16002 /* 43857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1354*/ GIMT_Encode4(43922), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4413 //
16003 /* 43864 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
16004 /* 43869 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16005 /* 43872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16006 /* 43875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16007 /* 43879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16008 /* 43883 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3938:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16009 /* 43883 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16010 /* 43886 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16011 /* 43890 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16012 /* 43895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
16013 /* 43898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16014 /* 43900 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16015 /* 43902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16016 /* 43905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16017 /* 43911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16018 /* 43917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16019 /* 43920 */ GIR_RootConstrainSelectedInstOperands,
16020 /* 43921 */ // GIR_Coverage, 4413,
16021 /* 43921 */ GIR_EraseRootFromParent_Done,
16022 /* 43922 */ // Label 1354: @43922
16023 /* 43922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1355*/ GIMT_Encode4(43972), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5399 //
16024 /* 43929 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8),
16025 /* 43934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1,
16026 /* 43937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16027 /* 43940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16028 /* 43944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16029 /* 43948 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3855:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
16030 /* 43948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8),
16031 /* 43951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16032 /* 43953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16033 /* 43955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16034 /* 43958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16035 /* 43964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16036 /* 43970 */ GIR_RootConstrainSelectedInstOperands,
16037 /* 43971 */ // GIR_Coverage, 5399,
16038 /* 43971 */ GIR_EraseRootFromParent_Done,
16039 /* 43972 */ // Label 1355: @43972
16040 /* 43972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1356*/ GIMT_Encode4(44022), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5401 //
16041 /* 43979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16),
16042 /* 43984 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
16043 /* 43987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16044 /* 43990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16045 /* 43994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16046 /* 43998 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3852:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
16047 /* 43998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16),
16048 /* 44001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16049 /* 44003 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16050 /* 44005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16051 /* 44008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16052 /* 44014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16053 /* 44020 */ GIR_RootConstrainSelectedInstOperands,
16054 /* 44021 */ // GIR_Coverage, 5401,
16055 /* 44021 */ GIR_EraseRootFromParent_Done,
16056 /* 44022 */ // Label 1356: @44022
16057 /* 44022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1357*/ GIMT_Encode4(44072), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5403 //
16058 /* 44029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32),
16059 /* 44034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
16060 /* 44037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16061 /* 44040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16062 /* 44044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16063 /* 44048 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3853:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
16064 /* 44048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32),
16065 /* 44051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16066 /* 44053 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16067 /* 44055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16068 /* 44058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16069 /* 44064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16070 /* 44070 */ GIR_RootConstrainSelectedInstOperands,
16071 /* 44071 */ // GIR_Coverage, 5403,
16072 /* 44071 */ GIR_EraseRootFromParent_Done,
16073 /* 44072 */ // Label 1357: @44072
16074 /* 44072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1358*/ GIMT_Encode4(44122), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5405 //
16075 /* 44079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64),
16076 /* 44084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1,
16077 /* 44087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16078 /* 44090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16079 /* 44094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16080 /* 44098 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3854:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn)
16081 /* 44098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64),
16082 /* 44101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16083 /* 44103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16084 /* 44105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16085 /* 44108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16086 /* 44114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16087 /* 44120 */ GIR_RootConstrainSelectedInstOperands,
16088 /* 44121 */ // GIR_Coverage, 5405,
16089 /* 44121 */ GIR_EraseRootFromParent_Done,
16090 /* 44122 */ // Label 1358: @44122
16091 /* 44122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1359*/ GIMT_Encode4(44167), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 599 //
16092 /* 44129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt),
16093 /* 44134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16094 /* 44137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16095 /* 44141 */ // MIs[0] Rn
16096 /* 44141 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16097 /* 44145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16098 /* 44149 */ // (intrinsic_wo_chain:{ *:[i32] } 3729:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16099 /* 44149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT),
16100 /* 44152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16101 /* 44154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16102 /* 44156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16103 /* 44159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16104 /* 44165 */ GIR_RootConstrainSelectedInstOperands,
16105 /* 44166 */ // GIR_Coverage, 599,
16106 /* 44166 */ GIR_EraseRootFromParent_Done,
16107 /* 44167 */ // Label 1359: @44167
16108 /* 44167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1360*/ GIMT_Encode4(44212), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 600 //
16109 /* 44174 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt),
16110 /* 44179 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16111 /* 44182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16112 /* 44186 */ // MIs[0] Rn
16113 /* 44186 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16114 /* 44190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16115 /* 44194 */ // (intrinsic_wo_chain:{ *:[i32] } 3732:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16116 /* 44194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT),
16117 /* 44197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16118 /* 44199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16119 /* 44201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16120 /* 44204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16121 /* 44210 */ GIR_RootConstrainSelectedInstOperands,
16122 /* 44211 */ // GIR_Coverage, 600,
16123 /* 44211 */ GIR_EraseRootFromParent_Done,
16124 /* 44212 */ // Label 1360: @44212
16125 /* 44212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1361*/ GIMT_Encode4(44257), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 601 //
16126 /* 44219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta),
16127 /* 44224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16128 /* 44227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16129 /* 44231 */ // MIs[0] Rn
16130 /* 44231 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16131 /* 44235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16132 /* 44239 */ // (intrinsic_wo_chain:{ *:[i32] } 3730:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16133 /* 44239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA),
16134 /* 44242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16135 /* 44244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16136 /* 44246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16137 /* 44249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16138 /* 44255 */ GIR_RootConstrainSelectedInstOperands,
16139 /* 44256 */ // GIR_Coverage, 601,
16140 /* 44256 */ GIR_EraseRootFromParent_Done,
16141 /* 44257 */ // Label 1361: @44257
16142 /* 44257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1362*/ GIMT_Encode4(44302), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 602 //
16143 /* 44264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat),
16144 /* 44269 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16145 /* 44272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16146 /* 44276 */ // MIs[0] Rn
16147 /* 44276 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16148 /* 44280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16149 /* 44284 */ // (intrinsic_wo_chain:{ *:[i32] } 3731:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16150 /* 44284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT),
16151 /* 44287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16152 /* 44289 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16153 /* 44291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16154 /* 44294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16155 /* 44300 */ GIR_RootConstrainSelectedInstOperands,
16156 /* 44301 */ // GIR_Coverage, 602,
16157 /* 44301 */ GIR_EraseRootFromParent_Done,
16158 /* 44302 */ // Label 1362: @44302
16159 /* 44302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1363*/ GIMT_Encode4(44455), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3082 //
16160 /* 44309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h),
16161 /* 44314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16162 /* 44317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16163 /* 44320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
16164 /* 44324 */ // (intrinsic_wo_chain:{ *:[i32] } 3984:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] })
16165 /* 44324 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
16166 /* 44327 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16167 /* 44331 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16168 /* 44336 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16169 /* 44340 */ GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
16170 /* 44345 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
16171 /* 44348 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16172 /* 44352 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16173 /* 44357 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
16174 /* 44359 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
16175 /* 44362 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16176 /* 44366 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16177 /* 44371 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
16178 /* 44374 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
16179 /* 44377 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
16180 /* 44380 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
16181 /* 44385 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
16182 /* 44390 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
16183 /* 44395 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
16184 /* 44398 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H),
16185 /* 44402 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16186 /* 44407 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
16187 /* 44410 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16188 /* 44412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16189 /* 44415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16190 /* 44419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16191 /* 44424 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
16192 /* 44431 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
16193 /* 44436 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID),
16194 /* 44441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16195 /* 44444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16196 /* 44446 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16197 /* 44449 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
16198 /* 44454 */ // GIR_Coverage, 3082,
16199 /* 44454 */ GIR_EraseRootFromParent_Done,
16200 /* 44455 */ // Label 1363: @44455
16201 /* 44455 */ GIM_Reject,
16202 /* 44456 */ // Label 1116: @44456
16203 /* 44456 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(67819),
16204 /* 44461 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
16205 /* 44464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1365*/ GIMT_Encode4(44520), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2313 //
16206 /* 44471 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
16207 /* 44476 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16208 /* 44479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16209 /* 44482 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16210 /* 44485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16211 /* 44489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16212 /* 44493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16213 /* 44497 */ // (intrinsic_wo_chain:{ *:[i32] } 4194:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
16214 /* 44497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16),
16215 /* 44500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16216 /* 44502 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16217 /* 44504 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
16218 /* 44506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16219 /* 44509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16220 /* 44512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16221 /* 44518 */ GIR_RootConstrainSelectedInstOperands,
16222 /* 44519 */ // GIR_Coverage, 2313,
16223 /* 44519 */ GIR_EraseRootFromParent_Done,
16224 /* 44520 */ // Label 1365: @44520
16225 /* 44520 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(44708),
16226 /* 44525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
16227 /* 44530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16228 /* 44533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16229 /* 44536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16230 /* 44539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1367*/ GIMT_Encode4(44623), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2076 //
16231 /* 44546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16232 /* 44550 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16233 /* 44554 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
16234 /* 44558 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16235 /* 44562 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16236 /* 44566 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16237 /* 44571 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16238 /* 44575 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16239 /* 44579 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16240 /* 44583 */ // MIs[2] Operand 1
16241 /* 44583 */ // No operand predicates
16242 /* 44583 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16243 /* 44587 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16244 /* 44591 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16245 /* 44595 */ // MIs[3] Operand 1
16246 /* 44595 */ // No operand predicates
16247 /* 44595 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
16248 /* 44597 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16249 /* 44597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
16250 /* 44600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16251 /* 44602 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16252 /* 44605 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16253 /* 44609 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16254 /* 44612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16255 /* 44615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16256 /* 44621 */ GIR_RootConstrainSelectedInstOperands,
16257 /* 44622 */ // GIR_Coverage, 2076,
16258 /* 44622 */ GIR_EraseRootFromParent_Done,
16259 /* 44623 */ // Label 1367: @44623
16260 /* 44623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1368*/ GIMT_Encode4(44707), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2350 //
16261 /* 44630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16262 /* 44634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16263 /* 44638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
16264 /* 44642 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16265 /* 44646 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16266 /* 44650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16267 /* 44655 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16268 /* 44659 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16269 /* 44663 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16270 /* 44667 */ // MIs[2] Operand 1
16271 /* 44667 */ // No operand predicates
16272 /* 44667 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16273 /* 44671 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16274 /* 44675 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16275 /* 44679 */ // MIs[3] Operand 1
16276 /* 44679 */ // No operand predicates
16277 /* 44679 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
16278 /* 44681 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16279 /* 44681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
16280 /* 44684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16281 /* 44686 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16282 /* 44689 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16283 /* 44693 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16284 /* 44696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16285 /* 44699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16286 /* 44705 */ GIR_RootConstrainSelectedInstOperands,
16287 /* 44706 */ // GIR_Coverage, 2350,
16288 /* 44706 */ GIR_EraseRootFromParent_Done,
16289 /* 44707 */ // Label 1368: @44707
16290 /* 44707 */ GIM_Reject,
16291 /* 44708 */ // Label 1366: @44708
16292 /* 44708 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(44935),
16293 /* 44713 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16294 /* 44718 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16295 /* 44721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16296 /* 44724 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16297 /* 44727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1370*/ GIMT_Encode4(44796), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5965 //
16298 /* 44734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16299 /* 44738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16300 /* 44742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16301 /* 44746 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16302 /* 44749 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16303 /* 44754 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16304 /* 44758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16305 /* 44763 */ // MIs[1] Rn
16306 /* 44763 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16307 /* 44768 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16308 /* 44772 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16309 /* 44774 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16310 /* 44774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
16311 /* 44777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16312 /* 44779 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
16313 /* 44781 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16314 /* 44785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16315 /* 44788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16316 /* 44794 */ GIR_RootConstrainSelectedInstOperands,
16317 /* 44795 */ // GIR_Coverage, 5965,
16318 /* 44795 */ GIR_EraseRootFromParent_Done,
16319 /* 44796 */ // Label 1370: @44796
16320 /* 44796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1371*/ GIMT_Encode4(44865), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6293 //
16321 /* 44803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16322 /* 44807 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16323 /* 44811 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16324 /* 44815 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16325 /* 44818 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16326 /* 44823 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16327 /* 44827 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16328 /* 44832 */ // MIs[1] Rn
16329 /* 44832 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16330 /* 44837 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16331 /* 44841 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16332 /* 44843 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16333 /* 44843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
16334 /* 44846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16335 /* 44848 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
16336 /* 44850 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16337 /* 44854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16338 /* 44857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16339 /* 44863 */ GIR_RootConstrainSelectedInstOperands,
16340 /* 44864 */ // GIR_Coverage, 6293,
16341 /* 44864 */ GIR_EraseRootFromParent_Done,
16342 /* 44865 */ // Label 1371: @44865
16343 /* 44865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1372*/ GIMT_Encode4(44934), GIMT_Encode2(GIFBS_IsARM), // Rule ID 108 //
16344 /* 44872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16345 /* 44876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16346 /* 44880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16347 /* 44884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16348 /* 44888 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16349 /* 44891 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16350 /* 44896 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16351 /* 44900 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16352 /* 44905 */ // MIs[1] Rn
16353 /* 44905 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16354 /* 44910 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16355 /* 44912 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16356 /* 44912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
16357 /* 44915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16358 /* 44917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16359 /* 44919 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16360 /* 44923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16361 /* 44926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16362 /* 44932 */ GIR_RootConstrainSelectedInstOperands,
16363 /* 44933 */ // GIR_Coverage, 108,
16364 /* 44933 */ GIR_EraseRootFromParent_Done,
16365 /* 44934 */ // Label 1372: @44934
16366 /* 44934 */ GIM_Reject,
16367 /* 44935 */ // Label 1369: @44935
16368 /* 44935 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1373*/ GIMT_Encode4(45018), GIMT_Encode2(GIFBS_IsARM), // Rule ID 109 //
16369 /* 44942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
16370 /* 44947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16371 /* 44950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16372 /* 44953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16373 /* 44956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16374 /* 44960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16375 /* 44964 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16376 /* 44968 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16377 /* 44972 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16378 /* 44975 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16379 /* 44980 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16380 /* 44984 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16381 /* 44989 */ // MIs[1] Rn
16382 /* 44989 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16383 /* 44994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16384 /* 44996 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16385 /* 44996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
16386 /* 44999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16387 /* 45001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16388 /* 45003 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16389 /* 45007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16390 /* 45010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16391 /* 45016 */ GIR_RootConstrainSelectedInstOperands,
16392 /* 45017 */ // GIR_Coverage, 109,
16393 /* 45017 */ GIR_EraseRootFromParent_Done,
16394 /* 45018 */ // Label 1373: @45018
16395 /* 45018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1374*/ GIMT_Encode4(45101), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2328 //
16396 /* 45025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16397 /* 45030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16398 /* 45033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16399 /* 45036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16400 /* 45039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16401 /* 45043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16402 /* 45047 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16403 /* 45051 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16404 /* 45055 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16405 /* 45058 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16406 /* 45063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16407 /* 45067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16408 /* 45072 */ // MIs[1] Rn
16409 /* 45072 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16410 /* 45077 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16411 /* 45079 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16412 /* 45079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
16413 /* 45082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16414 /* 45084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16415 /* 45086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16416 /* 45090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16417 /* 45093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16418 /* 45099 */ GIR_RootConstrainSelectedInstOperands,
16419 /* 45100 */ // GIR_Coverage, 2328,
16420 /* 45100 */ GIR_EraseRootFromParent_Done,
16421 /* 45101 */ // Label 1374: @45101
16422 /* 45101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1375*/ GIMT_Encode4(45184), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2329 //
16423 /* 45108 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
16424 /* 45113 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16425 /* 45116 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16426 /* 45119 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16427 /* 45122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16428 /* 45126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16429 /* 45130 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16430 /* 45134 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16431 /* 45138 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16432 /* 45141 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16433 /* 45146 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16434 /* 45150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16435 /* 45155 */ // MIs[1] Rn
16436 /* 45155 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16437 /* 45160 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16438 /* 45162 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16439 /* 45162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
16440 /* 45165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16441 /* 45167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16442 /* 45169 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16443 /* 45173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16444 /* 45176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16445 /* 45182 */ GIR_RootConstrainSelectedInstOperands,
16446 /* 45183 */ // GIR_Coverage, 2329,
16447 /* 45183 */ GIR_EraseRootFromParent_Done,
16448 /* 45184 */ // Label 1375: @45184
16449 /* 45184 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(45386),
16450 /* 45189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
16451 /* 45194 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1379*/ GIMT_Encode4(45385),
16452 /* 45205 */ /*GILLT_v8s16*//*Label 1377*/ GIMT_Encode4(45217), GIMT_Encode4(0),
16453 /* 45213 */ /*GILLT_v4s32*//*Label 1378*/ GIMT_Encode4(45301),
16454 /* 45217 */ // Label 1377: @45217
16455 /* 45217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1380*/ GIMT_Encode4(45300), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4581 //
16456 /* 45224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16457 /* 45227 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16458 /* 45230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16459 /* 45234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16460 /* 45238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16461 /* 45242 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16462 /* 45246 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16463 /* 45251 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16464 /* 45255 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16465 /* 45259 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
16466 /* 45263 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16467 /* 45268 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16468 /* 45270 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3892:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
16469 /* 45270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
16470 /* 45273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16471 /* 45275 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16472 /* 45279 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16473 /* 45283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16474 /* 45286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16475 /* 45292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16476 /* 45298 */ GIR_RootConstrainSelectedInstOperands,
16477 /* 45299 */ // GIR_Coverage, 4581,
16478 /* 45299 */ GIR_EraseRootFromParent_Done,
16479 /* 45300 */ // Label 1380: @45300
16480 /* 45300 */ GIM_Reject,
16481 /* 45301 */ // Label 1378: @45301
16482 /* 45301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1381*/ GIMT_Encode4(45384), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4578 //
16483 /* 45308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16484 /* 45311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16485 /* 45314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16486 /* 45318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16487 /* 45322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16488 /* 45326 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16489 /* 45330 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16490 /* 45335 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16491 /* 45339 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16492 /* 45343 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
16493 /* 45347 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16494 /* 45352 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16495 /* 45354 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3892:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
16496 /* 45354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
16497 /* 45357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16498 /* 45359 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16499 /* 45363 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16500 /* 45367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16501 /* 45370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16502 /* 45376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16503 /* 45382 */ GIR_RootConstrainSelectedInstOperands,
16504 /* 45383 */ // GIR_Coverage, 4578,
16505 /* 45383 */ GIR_EraseRootFromParent_Done,
16506 /* 45384 */ // Label 1381: @45384
16507 /* 45384 */ GIM_Reject,
16508 /* 45385 */ // Label 1379: @45385
16509 /* 45385 */ GIM_Reject,
16510 /* 45386 */ // Label 1376: @45386
16511 /* 45386 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(45588),
16512 /* 45391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
16513 /* 45396 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1385*/ GIMT_Encode4(45587),
16514 /* 45407 */ /*GILLT_v8s16*//*Label 1383*/ GIMT_Encode4(45419), GIMT_Encode4(0),
16515 /* 45415 */ /*GILLT_v4s32*//*Label 1384*/ GIMT_Encode4(45503),
16516 /* 45419 */ // Label 1383: @45419
16517 /* 45419 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1386*/ GIMT_Encode4(45502), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4587 //
16518 /* 45426 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16519 /* 45429 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16520 /* 45432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16521 /* 45436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16522 /* 45440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16523 /* 45444 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16524 /* 45448 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16525 /* 45453 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16526 /* 45457 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16527 /* 45461 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
16528 /* 45465 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16529 /* 45470 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16530 /* 45472 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3895:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
16531 /* 45472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
16532 /* 45475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16533 /* 45477 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16534 /* 45481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16535 /* 45485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16536 /* 45488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16537 /* 45494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16538 /* 45500 */ GIR_RootConstrainSelectedInstOperands,
16539 /* 45501 */ // GIR_Coverage, 4587,
16540 /* 45501 */ GIR_EraseRootFromParent_Done,
16541 /* 45502 */ // Label 1386: @45502
16542 /* 45502 */ GIM_Reject,
16543 /* 45503 */ // Label 1384: @45503
16544 /* 45503 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1387*/ GIMT_Encode4(45586), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4584 //
16545 /* 45510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16546 /* 45513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16547 /* 45516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16548 /* 45520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16549 /* 45524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16550 /* 45528 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16551 /* 45532 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16552 /* 45537 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16553 /* 45541 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16554 /* 45545 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
16555 /* 45549 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16556 /* 45554 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16557 /* 45556 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3895:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
16558 /* 45556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
16559 /* 45559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16560 /* 45561 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16561 /* 45565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16562 /* 45569 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16563 /* 45572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16564 /* 45578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16565 /* 45584 */ GIR_RootConstrainSelectedInstOperands,
16566 /* 45585 */ // GIR_Coverage, 4584,
16567 /* 45585 */ GIR_EraseRootFromParent_Done,
16568 /* 45586 */ // Label 1387: @45586
16569 /* 45586 */ GIM_Reject,
16570 /* 45587 */ // Label 1385: @45587
16571 /* 45587 */ GIM_Reject,
16572 /* 45588 */ // Label 1382: @45588
16573 /* 45588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1388*/ GIMT_Encode4(45660), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4509 //
16574 /* 45595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16575 /* 45600 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16576 /* 45603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16577 /* 45606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16578 /* 45609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16579 /* 45613 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16580 /* 45617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16581 /* 45621 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3865:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16582 /* 45621 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16583 /* 45624 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16584 /* 45628 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16585 /* 45633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a),
16586 /* 45636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16587 /* 45638 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16588 /* 45640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16589 /* 45643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16590 /* 45649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16591 /* 45655 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16592 /* 45658 */ GIR_RootConstrainSelectedInstOperands,
16593 /* 45659 */ // GIR_Coverage, 4509,
16594 /* 45659 */ GIR_EraseRootFromParent_Done,
16595 /* 45660 */ // Label 1388: @45660
16596 /* 45660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1389*/ GIMT_Encode4(45732), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4511 //
16597 /* 45667 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16598 /* 45672 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16599 /* 45675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16600 /* 45678 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16601 /* 45681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16602 /* 45685 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16603 /* 45689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16604 /* 45693 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16605 /* 45693 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16606 /* 45696 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16607 /* 45700 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16608 /* 45705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n),
16609 /* 45708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16610 /* 45710 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16611 /* 45712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16612 /* 45715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16613 /* 45721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16614 /* 45727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16615 /* 45730 */ GIR_RootConstrainSelectedInstOperands,
16616 /* 45731 */ // GIR_Coverage, 4511,
16617 /* 45731 */ GIR_EraseRootFromParent_Done,
16618 /* 45732 */ // Label 1389: @45732
16619 /* 45732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1390*/ GIMT_Encode4(45804), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4513 //
16620 /* 45739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16621 /* 45744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16622 /* 45747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16623 /* 45750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16624 /* 45753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16625 /* 45757 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16626 /* 45761 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16627 /* 45765 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3871:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16628 /* 45765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16629 /* 45768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16630 /* 45772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16631 /* 45777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p),
16632 /* 45780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16633 /* 45782 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16634 /* 45784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16635 /* 45787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16636 /* 45793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16637 /* 45799 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16638 /* 45802 */ GIR_RootConstrainSelectedInstOperands,
16639 /* 45803 */ // GIR_Coverage, 4513,
16640 /* 45803 */ GIR_EraseRootFromParent_Done,
16641 /* 45804 */ // Label 1390: @45804
16642 /* 45804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1391*/ GIMT_Encode4(45876), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4515 //
16643 /* 45811 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16644 /* 45816 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16645 /* 45819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16646 /* 45822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16647 /* 45825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16648 /* 45829 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16649 /* 45833 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16650 /* 45837 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3867:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16651 /* 45837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16652 /* 45840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16653 /* 45844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16654 /* 45849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m),
16655 /* 45852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16656 /* 45854 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16657 /* 45856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16658 /* 45859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16659 /* 45865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16660 /* 45871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16661 /* 45874 */ GIR_RootConstrainSelectedInstOperands,
16662 /* 45875 */ // GIR_Coverage, 4515,
16663 /* 45875 */ GIR_EraseRootFromParent_Done,
16664 /* 45876 */ // Label 1391: @45876
16665 /* 45876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1392*/ GIMT_Encode4(45948), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4517 //
16666 /* 45883 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16667 /* 45888 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16668 /* 45891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16669 /* 45894 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16670 /* 45897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16671 /* 45901 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16672 /* 45905 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16673 /* 45909 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3865:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16674 /* 45909 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16675 /* 45912 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16676 /* 45916 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16677 /* 45921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a),
16678 /* 45924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16679 /* 45926 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16680 /* 45928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16681 /* 45931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16682 /* 45937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16683 /* 45943 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16684 /* 45946 */ GIR_RootConstrainSelectedInstOperands,
16685 /* 45947 */ // GIR_Coverage, 4517,
16686 /* 45947 */ GIR_EraseRootFromParent_Done,
16687 /* 45948 */ // Label 1392: @45948
16688 /* 45948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1393*/ GIMT_Encode4(46020), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4519 //
16689 /* 45955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16690 /* 45960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16691 /* 45963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16692 /* 45966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16693 /* 45969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16694 /* 45973 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16695 /* 45977 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16696 /* 45981 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16697 /* 45981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16698 /* 45984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16699 /* 45988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16700 /* 45993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n),
16701 /* 45996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16702 /* 45998 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16703 /* 46000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16704 /* 46003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16705 /* 46009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16706 /* 46015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16707 /* 46018 */ GIR_RootConstrainSelectedInstOperands,
16708 /* 46019 */ // GIR_Coverage, 4519,
16709 /* 46019 */ GIR_EraseRootFromParent_Done,
16710 /* 46020 */ // Label 1393: @46020
16711 /* 46020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1394*/ GIMT_Encode4(46092), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4521 //
16712 /* 46027 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16713 /* 46032 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16714 /* 46035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16715 /* 46038 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16716 /* 46041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16717 /* 46045 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16718 /* 46049 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16719 /* 46053 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3871:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16720 /* 46053 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16721 /* 46056 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16722 /* 46060 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16723 /* 46065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p),
16724 /* 46068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16725 /* 46070 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16726 /* 46072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16727 /* 46075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16728 /* 46081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16729 /* 46087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16730 /* 46090 */ GIR_RootConstrainSelectedInstOperands,
16731 /* 46091 */ // GIR_Coverage, 4521,
16732 /* 46091 */ GIR_EraseRootFromParent_Done,
16733 /* 46092 */ // Label 1394: @46092
16734 /* 46092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1395*/ GIMT_Encode4(46164), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4523 //
16735 /* 46099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16736 /* 46104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16737 /* 46107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16738 /* 46110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16739 /* 46113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16740 /* 46117 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16741 /* 46121 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16742 /* 46125 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3867:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16743 /* 46125 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16744 /* 46128 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16745 /* 46132 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16746 /* 46137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m),
16747 /* 46140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16748 /* 46142 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16749 /* 46144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16750 /* 46147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16751 /* 46153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16752 /* 46159 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16753 /* 46162 */ GIR_RootConstrainSelectedInstOperands,
16754 /* 46163 */ // GIR_Coverage, 4523,
16755 /* 46163 */ GIR_EraseRootFromParent_Done,
16756 /* 46164 */ // Label 1395: @46164
16757 /* 46164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1396*/ GIMT_Encode4(46236), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4525 //
16758 /* 46171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16759 /* 46176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16760 /* 46179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16761 /* 46182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16762 /* 46185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16763 /* 46189 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16764 /* 46193 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16765 /* 46197 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3865:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16766 /* 46197 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16767 /* 46200 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16768 /* 46204 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16769 /* 46209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a),
16770 /* 46212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16771 /* 46214 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16772 /* 46216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16773 /* 46219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16774 /* 46225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16775 /* 46231 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16776 /* 46234 */ GIR_RootConstrainSelectedInstOperands,
16777 /* 46235 */ // GIR_Coverage, 4525,
16778 /* 46235 */ GIR_EraseRootFromParent_Done,
16779 /* 46236 */ // Label 1396: @46236
16780 /* 46236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1397*/ GIMT_Encode4(46308), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4527 //
16781 /* 46243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16782 /* 46248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16783 /* 46251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16784 /* 46254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16785 /* 46257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16786 /* 46261 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16787 /* 46265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16788 /* 46269 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16789 /* 46269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16790 /* 46272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16791 /* 46276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16792 /* 46281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n),
16793 /* 46284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16794 /* 46286 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16795 /* 46288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16796 /* 46291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16797 /* 46297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16798 /* 46303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16799 /* 46306 */ GIR_RootConstrainSelectedInstOperands,
16800 /* 46307 */ // GIR_Coverage, 4527,
16801 /* 46307 */ GIR_EraseRootFromParent_Done,
16802 /* 46308 */ // Label 1397: @46308
16803 /* 46308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1398*/ GIMT_Encode4(46380), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4529 //
16804 /* 46315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16805 /* 46320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16806 /* 46323 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16807 /* 46326 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16808 /* 46329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16809 /* 46333 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16810 /* 46337 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16811 /* 46341 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3871:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16812 /* 46341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16813 /* 46344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16814 /* 46348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16815 /* 46353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p),
16816 /* 46356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16817 /* 46358 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16818 /* 46360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16819 /* 46363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16820 /* 46369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16821 /* 46375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16822 /* 46378 */ GIR_RootConstrainSelectedInstOperands,
16823 /* 46379 */ // GIR_Coverage, 4529,
16824 /* 46379 */ GIR_EraseRootFromParent_Done,
16825 /* 46380 */ // Label 1398: @46380
16826 /* 46380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1399*/ GIMT_Encode4(46452), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4531 //
16827 /* 46387 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16828 /* 46392 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16829 /* 46395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16830 /* 46398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16831 /* 46401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16832 /* 46405 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16833 /* 46409 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16834 /* 46413 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3867:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16835 /* 46413 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16836 /* 46416 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16837 /* 46420 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16838 /* 46425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m),
16839 /* 46428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16840 /* 46430 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16841 /* 46432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16842 /* 46435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16843 /* 46441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16844 /* 46447 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16845 /* 46450 */ GIR_RootConstrainSelectedInstOperands,
16846 /* 46451 */ // GIR_Coverage, 4531,
16847 /* 46451 */ GIR_EraseRootFromParent_Done,
16848 /* 46452 */ // Label 1399: @46452
16849 /* 46452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1400*/ GIMT_Encode4(46524), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4533 //
16850 /* 46459 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16851 /* 46464 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16852 /* 46467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16853 /* 46470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16854 /* 46473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16855 /* 46477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16856 /* 46481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16857 /* 46485 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3865:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16858 /* 46485 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16859 /* 46488 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16860 /* 46492 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16861 /* 46497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a),
16862 /* 46500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16863 /* 46502 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16864 /* 46504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16865 /* 46507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16866 /* 46513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16867 /* 46519 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16868 /* 46522 */ GIR_RootConstrainSelectedInstOperands,
16869 /* 46523 */ // GIR_Coverage, 4533,
16870 /* 46523 */ GIR_EraseRootFromParent_Done,
16871 /* 46524 */ // Label 1400: @46524
16872 /* 46524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1401*/ GIMT_Encode4(46596), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4535 //
16873 /* 46531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16874 /* 46536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16875 /* 46539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16876 /* 46542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16877 /* 46545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16878 /* 46549 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16879 /* 46553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16880 /* 46557 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16881 /* 46557 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16882 /* 46560 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16883 /* 46564 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16884 /* 46569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n),
16885 /* 46572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16886 /* 46574 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16887 /* 46576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16888 /* 46579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16889 /* 46585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16890 /* 46591 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16891 /* 46594 */ GIR_RootConstrainSelectedInstOperands,
16892 /* 46595 */ // GIR_Coverage, 4535,
16893 /* 46595 */ GIR_EraseRootFromParent_Done,
16894 /* 46596 */ // Label 1401: @46596
16895 /* 46596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1402*/ GIMT_Encode4(46668), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4537 //
16896 /* 46603 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16897 /* 46608 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16898 /* 46611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16899 /* 46614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16900 /* 46617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16901 /* 46621 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16902 /* 46625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16903 /* 46629 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3871:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16904 /* 46629 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16905 /* 46632 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16906 /* 46636 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16907 /* 46641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p),
16908 /* 46644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16909 /* 46646 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16910 /* 46648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16911 /* 46651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16912 /* 46657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16913 /* 46663 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16914 /* 46666 */ GIR_RootConstrainSelectedInstOperands,
16915 /* 46667 */ // GIR_Coverage, 4537,
16916 /* 46667 */ GIR_EraseRootFromParent_Done,
16917 /* 46668 */ // Label 1402: @46668
16918 /* 46668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1403*/ GIMT_Encode4(46740), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4539 //
16919 /* 46675 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16920 /* 46680 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16921 /* 46683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16922 /* 46686 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16923 /* 46689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16924 /* 46693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16925 /* 46697 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16926 /* 46701 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3867:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16927 /* 46701 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16928 /* 46704 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16929 /* 46708 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16930 /* 46713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m),
16931 /* 46716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16932 /* 46718 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16933 /* 46720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16934 /* 46723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16935 /* 46729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16936 /* 46735 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16937 /* 46738 */ GIR_RootConstrainSelectedInstOperands,
16938 /* 46739 */ // GIR_Coverage, 4539,
16939 /* 46739 */ GIR_EraseRootFromParent_Done,
16940 /* 46740 */ // Label 1403: @46740
16941 /* 46740 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(47016),
16942 /* 46745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
16943 /* 46750 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1407*/ GIMT_Encode4(47015),
16944 /* 46761 */ /*GILLT_v8s16*//*Label 1405*/ GIMT_Encode4(46773), GIMT_Encode4(0),
16945 /* 46769 */ /*GILLT_v4s32*//*Label 1406*/ GIMT_Encode4(46894),
16946 /* 46773 */ // Label 1405: @46773
16947 /* 46773 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(46893),
16948 /* 46778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16949 /* 46781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16950 /* 46784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16951 /* 46788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16952 /* 46792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1409*/ GIMT_Encode4(46842), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4542 //
16953 /* 46799 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16954 /* 46803 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3860:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
16955 /* 46803 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16956 /* 46806 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16957 /* 46810 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16958 /* 46815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
16959 /* 46818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16960 /* 46820 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
16961 /* 46822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16962 /* 46825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16963 /* 46831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16964 /* 46837 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16965 /* 46840 */ GIR_RootConstrainSelectedInstOperands,
16966 /* 46841 */ // GIR_Coverage, 4542,
16967 /* 46841 */ GIR_EraseRootFromParent_Done,
16968 /* 46842 */ // Label 1409: @46842
16969 /* 46842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1410*/ GIMT_Encode4(46892), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4545 //
16970 /* 46849 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
16971 /* 46853 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3860:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
16972 /* 46853 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16973 /* 46856 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16974 /* 46860 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16975 /* 46865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
16976 /* 46868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16977 /* 46870 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
16978 /* 46872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16979 /* 46875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16980 /* 46881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16981 /* 46887 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16982 /* 46890 */ GIR_RootConstrainSelectedInstOperands,
16983 /* 46891 */ // GIR_Coverage, 4545,
16984 /* 46891 */ GIR_EraseRootFromParent_Done,
16985 /* 46892 */ // Label 1410: @46892
16986 /* 46892 */ GIM_Reject,
16987 /* 46893 */ // Label 1408: @46893
16988 /* 46893 */ GIM_Reject,
16989 /* 46894 */ // Label 1406: @46894
16990 /* 46894 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(47014),
16991 /* 46899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16992 /* 46902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16993 /* 46905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16994 /* 46909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16995 /* 46913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1412*/ GIMT_Encode4(46963), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4548 //
16996 /* 46920 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16997 /* 46924 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3860:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
16998 /* 46924 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16999 /* 46927 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17000 /* 46931 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17001 /* 46936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
17002 /* 46939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17003 /* 46941 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17004 /* 46943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17005 /* 46946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17006 /* 46952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17007 /* 46958 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17008 /* 46961 */ GIR_RootConstrainSelectedInstOperands,
17009 /* 46962 */ // GIR_Coverage, 4548,
17010 /* 46962 */ GIR_EraseRootFromParent_Done,
17011 /* 46963 */ // Label 1412: @46963
17012 /* 46963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1413*/ GIMT_Encode4(47013), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4551 //
17013 /* 46970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17014 /* 46974 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3860:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
17015 /* 46974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17016 /* 46977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17017 /* 46981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17018 /* 46986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
17019 /* 46989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17020 /* 46991 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17021 /* 46993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17022 /* 46996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17023 /* 47002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17024 /* 47008 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17025 /* 47011 */ GIR_RootConstrainSelectedInstOperands,
17026 /* 47012 */ // GIR_Coverage, 4551,
17027 /* 47012 */ GIR_EraseRootFromParent_Done,
17028 /* 47013 */ // Label 1413: @47013
17029 /* 47013 */ GIM_Reject,
17030 /* 47014 */ // Label 1411: @47014
17031 /* 47014 */ GIM_Reject,
17032 /* 47015 */ // Label 1407: @47015
17033 /* 47015 */ GIM_Reject,
17034 /* 47016 */ // Label 1404: @47016
17035 /* 47016 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(47292),
17036 /* 47021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
17037 /* 47026 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1417*/ GIMT_Encode4(47291),
17038 /* 47037 */ /*GILLT_v8s16*//*Label 1415*/ GIMT_Encode4(47049), GIMT_Encode4(0),
17039 /* 47045 */ /*GILLT_v4s32*//*Label 1416*/ GIMT_Encode4(47170),
17040 /* 47049 */ // Label 1415: @47049
17041 /* 47049 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(47169),
17042 /* 47054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17043 /* 47057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17044 /* 47060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17045 /* 47064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17046 /* 47068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1419*/ GIMT_Encode4(47118), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4554 //
17047 /* 47075 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17048 /* 47079 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3858:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
17049 /* 47079 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17050 /* 47082 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17051 /* 47086 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17052 /* 47091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
17053 /* 47094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17054 /* 47096 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17055 /* 47098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17056 /* 47101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17057 /* 47107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17058 /* 47113 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17059 /* 47116 */ GIR_RootConstrainSelectedInstOperands,
17060 /* 47117 */ // GIR_Coverage, 4554,
17061 /* 47117 */ GIR_EraseRootFromParent_Done,
17062 /* 47118 */ // Label 1419: @47118
17063 /* 47118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1420*/ GIMT_Encode4(47168), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4557 //
17064 /* 47125 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17065 /* 47129 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3858:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
17066 /* 47129 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17067 /* 47132 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17068 /* 47136 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17069 /* 47141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
17070 /* 47144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17071 /* 47146 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17072 /* 47148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17073 /* 47151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17074 /* 47157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17075 /* 47163 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17076 /* 47166 */ GIR_RootConstrainSelectedInstOperands,
17077 /* 47167 */ // GIR_Coverage, 4557,
17078 /* 47167 */ GIR_EraseRootFromParent_Done,
17079 /* 47168 */ // Label 1420: @47168
17080 /* 47168 */ GIM_Reject,
17081 /* 47169 */ // Label 1418: @47169
17082 /* 47169 */ GIM_Reject,
17083 /* 47170 */ // Label 1416: @47170
17084 /* 47170 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(47290),
17085 /* 47175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17086 /* 47178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17087 /* 47181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17088 /* 47185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17089 /* 47189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1422*/ GIMT_Encode4(47239), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4560 //
17090 /* 47196 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17091 /* 47200 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3858:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
17092 /* 47200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17093 /* 47203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17094 /* 47207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17095 /* 47212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
17096 /* 47215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17097 /* 47217 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17098 /* 47219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17099 /* 47222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17100 /* 47228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17101 /* 47234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17102 /* 47237 */ GIR_RootConstrainSelectedInstOperands,
17103 /* 47238 */ // GIR_Coverage, 4560,
17104 /* 47238 */ GIR_EraseRootFromParent_Done,
17105 /* 47239 */ // Label 1422: @47239
17106 /* 47239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1423*/ GIMT_Encode4(47289), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4563 //
17107 /* 47246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17108 /* 47250 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3858:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
17109 /* 47250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17110 /* 47253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17111 /* 47257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17112 /* 47262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
17113 /* 47265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17114 /* 47267 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17115 /* 47269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17116 /* 47272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17117 /* 47278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17118 /* 47284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17119 /* 47287 */ GIR_RootConstrainSelectedInstOperands,
17120 /* 47288 */ // GIR_Coverage, 4563,
17121 /* 47288 */ GIR_EraseRootFromParent_Done,
17122 /* 47289 */ // Label 1423: @47289
17123 /* 47289 */ GIM_Reject,
17124 /* 47290 */ // Label 1421: @47290
17125 /* 47290 */ GIM_Reject,
17126 /* 47291 */ // Label 1417: @47291
17127 /* 47291 */ GIM_Reject,
17128 /* 47292 */ // Label 1414: @47292
17129 /* 47292 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(47420),
17130 /* 47297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
17131 /* 47302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17132 /* 47305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17133 /* 47308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17134 /* 47311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17135 /* 47315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17136 /* 47319 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1425*/ GIMT_Encode4(47369), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5043 //
17137 /* 47326 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17138 /* 47330 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3863:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17139 /* 47330 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17140 /* 47333 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17141 /* 47337 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17142 /* 47342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh),
17143 /* 47345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17144 /* 47347 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
17145 /* 47349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17146 /* 47352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17147 /* 47358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17148 /* 47364 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17149 /* 47367 */ GIR_RootConstrainSelectedInstOperands,
17150 /* 47368 */ // GIR_Coverage, 5043,
17151 /* 47368 */ GIR_EraseRootFromParent_Done,
17152 /* 47369 */ // Label 1425: @47369
17153 /* 47369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1426*/ GIMT_Encode4(47419), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5049 //
17154 /* 47376 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17155 /* 47380 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3863:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17156 /* 47380 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17157 /* 47383 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17158 /* 47387 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17159 /* 47392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th),
17160 /* 47395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17161 /* 47397 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
17162 /* 47399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17163 /* 47402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17164 /* 47408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17165 /* 47414 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17166 /* 47417 */ GIR_RootConstrainSelectedInstOperands,
17167 /* 47418 */ // GIR_Coverage, 5049,
17168 /* 47418 */ GIR_EraseRootFromParent_Done,
17169 /* 47419 */ // Label 1426: @47419
17170 /* 47419 */ GIM_Reject,
17171 /* 47420 */ // Label 1424: @47420
17172 /* 47420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1427*/ GIMT_Encode4(47487), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2069 //
17173 /* 47427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17174 /* 47432 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17175 /* 47435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17176 /* 47438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17177 /* 47441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17178 /* 47445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17179 /* 47449 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17180 /* 47453 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17181 /* 47457 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17182 /* 47461 */ // MIs[1] Operand 1
17183 /* 47461 */ // No operand predicates
17184 /* 47461 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17185 /* 47463 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
17186 /* 47463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
17187 /* 47466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17188 /* 47468 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17189 /* 47471 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17190 /* 47473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17191 /* 47476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17192 /* 47479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17193 /* 47485 */ GIR_RootConstrainSelectedInstOperands,
17194 /* 47486 */ // GIR_Coverage, 2069,
17195 /* 47486 */ GIR_EraseRootFromParent_Done,
17196 /* 47487 */ // Label 1427: @47487
17197 /* 47487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1428*/ GIMT_Encode4(47551), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2073 //
17198 /* 47494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
17199 /* 47499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17200 /* 47502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17201 /* 47505 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17202 /* 47508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17203 /* 47512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17204 /* 47516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17205 /* 47520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17206 /* 47524 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17207 /* 47528 */ // MIs[1] Operand 1
17208 /* 47528 */ // No operand predicates
17209 /* 47528 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17210 /* 47530 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
17211 /* 47530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16),
17212 /* 47533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17213 /* 47535 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17214 /* 47538 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17215 /* 47540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17216 /* 47543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17217 /* 47549 */ GIR_RootConstrainSelectedInstOperands,
17218 /* 47550 */ // GIR_Coverage, 2073,
17219 /* 47550 */ GIR_EraseRootFromParent_Done,
17220 /* 47551 */ // Label 1428: @47551
17221 /* 47551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1429*/ GIMT_Encode4(47618), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2345 //
17222 /* 47558 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17223 /* 47563 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17224 /* 47566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17225 /* 47569 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17226 /* 47572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17227 /* 47576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
17228 /* 47580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17229 /* 47584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17230 /* 47588 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17231 /* 47592 */ // MIs[1] Operand 1
17232 /* 47592 */ // No operand predicates
17233 /* 47592 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17234 /* 47594 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
17235 /* 47594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
17236 /* 47597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17237 /* 47599 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17238 /* 47602 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17239 /* 47604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17240 /* 47607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17241 /* 47610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17242 /* 47616 */ GIR_RootConstrainSelectedInstOperands,
17243 /* 47617 */ // GIR_Coverage, 2345,
17244 /* 47617 */ GIR_EraseRootFromParent_Done,
17245 /* 47618 */ // Label 1429: @47618
17246 /* 47618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1430*/ GIMT_Encode4(47682), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2347 //
17247 /* 47625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
17248 /* 47630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17249 /* 47633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17250 /* 47636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17251 /* 47639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17252 /* 47643 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
17253 /* 47647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17254 /* 47651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17255 /* 47655 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17256 /* 47659 */ // MIs[1] Operand 1
17257 /* 47659 */ // No operand predicates
17258 /* 47659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17259 /* 47661 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
17260 /* 47661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16),
17261 /* 47664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17262 /* 47666 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17263 /* 47669 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17264 /* 47671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17265 /* 47674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17266 /* 47680 */ GIR_RootConstrainSelectedInstOperands,
17267 /* 47681 */ // GIR_Coverage, 2347,
17268 /* 47681 */ GIR_EraseRootFromParent_Done,
17269 /* 47682 */ // Label 1430: @47682
17270 /* 47682 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(47952),
17271 /* 47687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
17272 /* 47692 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 1435*/ GIMT_Encode4(47951),
17273 /* 47703 */ /*GILLT_v16s8*//*Label 1432*/ GIMT_Encode4(47723), GIMT_Encode4(0),
17274 /* 47711 */ /*GILLT_v8s16*//*Label 1433*/ GIMT_Encode4(47799), GIMT_Encode4(0),
17275 /* 47719 */ /*GILLT_v4s32*//*Label 1434*/ GIMT_Encode4(47875),
17276 /* 47723 */ // Label 1432: @47723
17277 /* 47723 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(47798), // Rule ID 4331 //
17278 /* 47728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17279 /* 47731 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17280 /* 47734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17281 /* 47738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17282 /* 47742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17283 /* 47746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17284 /* 47750 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
17285 /* 47754 */ // MIs[1] Operand 1
17286 /* 47754 */ // No operand predicates
17287 /* 47754 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17288 /* 47756 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3927:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
17289 /* 47756 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17290 /* 47759 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17291 /* 47763 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17292 /* 47768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8),
17293 /* 47771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17294 /* 47773 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17295 /* 47775 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17296 /* 47778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17297 /* 47781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17298 /* 47787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17299 /* 47793 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17300 /* 47796 */ GIR_RootConstrainSelectedInstOperands,
17301 /* 47797 */ // GIR_Coverage, 4331,
17302 /* 47797 */ GIR_EraseRootFromParent_Done,
17303 /* 47798 */ // Label 1436: @47798
17304 /* 47798 */ GIM_Reject,
17305 /* 47799 */ // Label 1433: @47799
17306 /* 47799 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(47874), // Rule ID 4333 //
17307 /* 47804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17308 /* 47807 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17309 /* 47810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17310 /* 47814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17311 /* 47818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17312 /* 47822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17313 /* 47826 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17314 /* 47830 */ // MIs[1] Operand 1
17315 /* 47830 */ // No operand predicates
17316 /* 47830 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17317 /* 47832 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3927:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
17318 /* 47832 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17319 /* 47835 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17320 /* 47839 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17321 /* 47844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16),
17322 /* 47847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17323 /* 47849 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17324 /* 47851 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17325 /* 47854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17326 /* 47857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17327 /* 47863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17328 /* 47869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17329 /* 47872 */ GIR_RootConstrainSelectedInstOperands,
17330 /* 47873 */ // GIR_Coverage, 4333,
17331 /* 47873 */ GIR_EraseRootFromParent_Done,
17332 /* 47874 */ // Label 1437: @47874
17333 /* 47874 */ GIM_Reject,
17334 /* 47875 */ // Label 1434: @47875
17335 /* 47875 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(47950), // Rule ID 4335 //
17336 /* 47880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17337 /* 47883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17338 /* 47886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17339 /* 47890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17340 /* 47894 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17341 /* 47898 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17342 /* 47902 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17343 /* 47906 */ // MIs[1] Operand 1
17344 /* 47906 */ // No operand predicates
17345 /* 47906 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17346 /* 47908 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3927:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
17347 /* 47908 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17348 /* 47911 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17349 /* 47915 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17350 /* 47920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32),
17351 /* 47923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17352 /* 47925 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17353 /* 47927 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17354 /* 47930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17355 /* 47933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17356 /* 47939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17357 /* 47945 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17358 /* 47948 */ GIR_RootConstrainSelectedInstOperands,
17359 /* 47949 */ // GIR_Coverage, 4335,
17360 /* 47949 */ GIR_EraseRootFromParent_Done,
17361 /* 47950 */ // Label 1438: @47950
17362 /* 47950 */ GIM_Reject,
17363 /* 47951 */ // Label 1435: @47951
17364 /* 47951 */ GIM_Reject,
17365 /* 47952 */ // Label 1431: @47952
17366 /* 47952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1439*/ GIMT_Encode4(48012), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1814 //
17367 /* 47959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17368 /* 47964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17369 /* 47967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17370 /* 47970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17371 /* 47973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17372 /* 47977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17373 /* 47981 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17374 /* 47985 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17375 /* 47989 */ // MIs[1] Operand 1
17376 /* 47989 */ // No operand predicates
17377 /* 47989 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17378 /* 47991 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4011:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17379 /* 47991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd),
17380 /* 47994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17381 /* 47996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17382 /* 47998 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17383 /* 48001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17384 /* 48004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17385 /* 48010 */ GIR_RootConstrainSelectedInstOperands,
17386 /* 48011 */ // GIR_Coverage, 1814,
17387 /* 48011 */ GIR_EraseRootFromParent_Done,
17388 /* 48012 */ // Label 1439: @48012
17389 /* 48012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1440*/ GIMT_Encode4(48072), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1815 //
17390 /* 48019 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17391 /* 48024 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17392 /* 48027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17393 /* 48030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17394 /* 48033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17395 /* 48037 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17396 /* 48041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17397 /* 48045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17398 /* 48049 */ // MIs[1] Operand 1
17399 /* 48049 */ // No operand predicates
17400 /* 48049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17401 /* 48051 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4012:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17402 /* 48051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud),
17403 /* 48054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17404 /* 48056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17405 /* 48058 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17406 /* 48061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17407 /* 48064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17408 /* 48070 */ GIR_RootConstrainSelectedInstOperands,
17409 /* 48071 */ // GIR_Coverage, 1815,
17410 /* 48071 */ GIR_EraseRootFromParent_Done,
17411 /* 48072 */ // Label 1440: @48072
17412 /* 48072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1441*/ GIMT_Encode4(48132), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1816 //
17413 /* 48079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17414 /* 48084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17415 /* 48087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17416 /* 48090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17417 /* 48093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17418 /* 48097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17419 /* 48101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17420 /* 48105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17421 /* 48109 */ // MIs[1] Operand 1
17422 /* 48109 */ // No operand predicates
17423 /* 48109 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17424 /* 48111 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4014:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17425 /* 48111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd),
17426 /* 48114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17427 /* 48116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17428 /* 48118 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17429 /* 48121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17430 /* 48124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17431 /* 48130 */ GIR_RootConstrainSelectedInstOperands,
17432 /* 48131 */ // GIR_Coverage, 1816,
17433 /* 48131 */ GIR_EraseRootFromParent_Done,
17434 /* 48132 */ // Label 1441: @48132
17435 /* 48132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1442*/ GIMT_Encode4(48192), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1817 //
17436 /* 48139 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17437 /* 48144 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17438 /* 48147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17439 /* 48150 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17440 /* 48153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17441 /* 48157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17442 /* 48161 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17443 /* 48165 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17444 /* 48169 */ // MIs[1] Operand 1
17445 /* 48169 */ // No operand predicates
17446 /* 48169 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17447 /* 48171 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4015:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17448 /* 48171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd),
17449 /* 48174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17450 /* 48176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17451 /* 48178 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17452 /* 48181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17453 /* 48184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17454 /* 48190 */ GIR_RootConstrainSelectedInstOperands,
17455 /* 48191 */ // GIR_Coverage, 1817,
17456 /* 48191 */ GIR_EraseRootFromParent_Done,
17457 /* 48192 */ // Label 1442: @48192
17458 /* 48192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1443*/ GIMT_Encode4(48252), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1818 //
17459 /* 48199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17460 /* 48204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17461 /* 48207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17462 /* 48210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17463 /* 48213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17464 /* 48217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17465 /* 48221 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17466 /* 48225 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17467 /* 48229 */ // MIs[1] Operand 1
17468 /* 48229 */ // No operand predicates
17469 /* 48229 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17470 /* 48231 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4011:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17471 /* 48231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd),
17472 /* 48234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17473 /* 48236 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17474 /* 48238 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17475 /* 48241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17476 /* 48244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17477 /* 48250 */ GIR_RootConstrainSelectedInstOperands,
17478 /* 48251 */ // GIR_Coverage, 1818,
17479 /* 48251 */ GIR_EraseRootFromParent_Done,
17480 /* 48252 */ // Label 1443: @48252
17481 /* 48252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1444*/ GIMT_Encode4(48312), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1819 //
17482 /* 48259 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17483 /* 48264 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17484 /* 48267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17485 /* 48270 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17486 /* 48273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17487 /* 48277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17488 /* 48281 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17489 /* 48285 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17490 /* 48289 */ // MIs[1] Operand 1
17491 /* 48289 */ // No operand predicates
17492 /* 48289 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17493 /* 48291 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4012:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17494 /* 48291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud),
17495 /* 48294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17496 /* 48296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17497 /* 48298 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17498 /* 48301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17499 /* 48304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17500 /* 48310 */ GIR_RootConstrainSelectedInstOperands,
17501 /* 48311 */ // GIR_Coverage, 1819,
17502 /* 48311 */ GIR_EraseRootFromParent_Done,
17503 /* 48312 */ // Label 1444: @48312
17504 /* 48312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1445*/ GIMT_Encode4(48372), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1820 //
17505 /* 48319 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17506 /* 48324 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17507 /* 48327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17508 /* 48330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17509 /* 48333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17510 /* 48337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17511 /* 48341 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17512 /* 48345 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17513 /* 48349 */ // MIs[1] Operand 1
17514 /* 48349 */ // No operand predicates
17515 /* 48349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17516 /* 48351 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4014:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17517 /* 48351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd),
17518 /* 48354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17519 /* 48356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17520 /* 48358 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17521 /* 48361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17522 /* 48364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17523 /* 48370 */ GIR_RootConstrainSelectedInstOperands,
17524 /* 48371 */ // GIR_Coverage, 1820,
17525 /* 48371 */ GIR_EraseRootFromParent_Done,
17526 /* 48372 */ // Label 1445: @48372
17527 /* 48372 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1446*/ GIMT_Encode4(48432), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1821 //
17528 /* 48379 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17529 /* 48384 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17530 /* 48387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17531 /* 48390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17532 /* 48393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17533 /* 48397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17534 /* 48401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17535 /* 48405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17536 /* 48409 */ // MIs[1] Operand 1
17537 /* 48409 */ // No operand predicates
17538 /* 48409 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17539 /* 48411 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4015:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17540 /* 48411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd),
17541 /* 48414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17542 /* 48416 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17543 /* 48418 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17544 /* 48421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17545 /* 48424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17546 /* 48430 */ GIR_RootConstrainSelectedInstOperands,
17547 /* 48431 */ // GIR_Coverage, 1821,
17548 /* 48431 */ GIR_EraseRootFromParent_Done,
17549 /* 48432 */ // Label 1446: @48432
17550 /* 48432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1447*/ GIMT_Encode4(48492), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1822 //
17551 /* 48439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17552 /* 48444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17553 /* 48447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17554 /* 48450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17555 /* 48453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17556 /* 48457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17557 /* 48461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17558 /* 48465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17559 /* 48469 */ // MIs[1] Operand 1
17560 /* 48469 */ // No operand predicates
17561 /* 48469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17562 /* 48471 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4011:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17563 /* 48471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq),
17564 /* 48474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17565 /* 48476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17566 /* 48478 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17567 /* 48481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17568 /* 48484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17569 /* 48490 */ GIR_RootConstrainSelectedInstOperands,
17570 /* 48491 */ // GIR_Coverage, 1822,
17571 /* 48491 */ GIR_EraseRootFromParent_Done,
17572 /* 48492 */ // Label 1447: @48492
17573 /* 48492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1448*/ GIMT_Encode4(48552), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1823 //
17574 /* 48499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17575 /* 48504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17576 /* 48507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17577 /* 48510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17578 /* 48513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17579 /* 48517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17580 /* 48521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17581 /* 48525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17582 /* 48529 */ // MIs[1] Operand 1
17583 /* 48529 */ // No operand predicates
17584 /* 48529 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17585 /* 48531 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4012:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17586 /* 48531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq),
17587 /* 48534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17588 /* 48536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17589 /* 48538 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17590 /* 48541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17591 /* 48544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17592 /* 48550 */ GIR_RootConstrainSelectedInstOperands,
17593 /* 48551 */ // GIR_Coverage, 1823,
17594 /* 48551 */ GIR_EraseRootFromParent_Done,
17595 /* 48552 */ // Label 1448: @48552
17596 /* 48552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1449*/ GIMT_Encode4(48612), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1824 //
17597 /* 48559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17598 /* 48564 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17599 /* 48567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17600 /* 48570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17601 /* 48573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17602 /* 48577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17603 /* 48581 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17604 /* 48585 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17605 /* 48589 */ // MIs[1] Operand 1
17606 /* 48589 */ // No operand predicates
17607 /* 48589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17608 /* 48591 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4014:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17609 /* 48591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq),
17610 /* 48594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17611 /* 48596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17612 /* 48598 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17613 /* 48601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17614 /* 48604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17615 /* 48610 */ GIR_RootConstrainSelectedInstOperands,
17616 /* 48611 */ // GIR_Coverage, 1824,
17617 /* 48611 */ GIR_EraseRootFromParent_Done,
17618 /* 48612 */ // Label 1449: @48612
17619 /* 48612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1450*/ GIMT_Encode4(48672), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1825 //
17620 /* 48619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17621 /* 48624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17622 /* 48627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17623 /* 48630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17624 /* 48633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17625 /* 48637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17626 /* 48641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17627 /* 48645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17628 /* 48649 */ // MIs[1] Operand 1
17629 /* 48649 */ // No operand predicates
17630 /* 48649 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17631 /* 48651 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4015:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17632 /* 48651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq),
17633 /* 48654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17634 /* 48656 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17635 /* 48658 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17636 /* 48661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17637 /* 48664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17638 /* 48670 */ GIR_RootConstrainSelectedInstOperands,
17639 /* 48671 */ // GIR_Coverage, 1825,
17640 /* 48671 */ GIR_EraseRootFromParent_Done,
17641 /* 48672 */ // Label 1450: @48672
17642 /* 48672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1451*/ GIMT_Encode4(48732), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1826 //
17643 /* 48679 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17644 /* 48684 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17645 /* 48687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17646 /* 48690 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17647 /* 48693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17648 /* 48697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17649 /* 48701 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17650 /* 48705 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17651 /* 48709 */ // MIs[1] Operand 1
17652 /* 48709 */ // No operand predicates
17653 /* 48709 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17654 /* 48711 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4011:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17655 /* 48711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq),
17656 /* 48714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17657 /* 48716 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17658 /* 48718 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17659 /* 48721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17660 /* 48724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17661 /* 48730 */ GIR_RootConstrainSelectedInstOperands,
17662 /* 48731 */ // GIR_Coverage, 1826,
17663 /* 48731 */ GIR_EraseRootFromParent_Done,
17664 /* 48732 */ // Label 1451: @48732
17665 /* 48732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1452*/ GIMT_Encode4(48792), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1827 //
17666 /* 48739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17667 /* 48744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17668 /* 48747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17669 /* 48750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17670 /* 48753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17671 /* 48757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17672 /* 48761 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17673 /* 48765 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17674 /* 48769 */ // MIs[1] Operand 1
17675 /* 48769 */ // No operand predicates
17676 /* 48769 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17677 /* 48771 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4012:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17678 /* 48771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq),
17679 /* 48774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17680 /* 48776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17681 /* 48778 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17682 /* 48781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17683 /* 48784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17684 /* 48790 */ GIR_RootConstrainSelectedInstOperands,
17685 /* 48791 */ // GIR_Coverage, 1827,
17686 /* 48791 */ GIR_EraseRootFromParent_Done,
17687 /* 48792 */ // Label 1452: @48792
17688 /* 48792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1453*/ GIMT_Encode4(48852), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1828 //
17689 /* 48799 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17690 /* 48804 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17691 /* 48807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17692 /* 48810 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17693 /* 48813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17694 /* 48817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17695 /* 48821 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17696 /* 48825 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17697 /* 48829 */ // MIs[1] Operand 1
17698 /* 48829 */ // No operand predicates
17699 /* 48829 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17700 /* 48831 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4014:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17701 /* 48831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq),
17702 /* 48834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17703 /* 48836 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17704 /* 48838 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17705 /* 48841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17706 /* 48844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17707 /* 48850 */ GIR_RootConstrainSelectedInstOperands,
17708 /* 48851 */ // GIR_Coverage, 1828,
17709 /* 48851 */ GIR_EraseRootFromParent_Done,
17710 /* 48852 */ // Label 1453: @48852
17711 /* 48852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1454*/ GIMT_Encode4(48912), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1829 //
17712 /* 48859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17713 /* 48864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17714 /* 48867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17715 /* 48870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17716 /* 48873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17717 /* 48877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17718 /* 48881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17719 /* 48885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17720 /* 48889 */ // MIs[1] Operand 1
17721 /* 48889 */ // No operand predicates
17722 /* 48889 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17723 /* 48891 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4015:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17724 /* 48891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq),
17725 /* 48894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17726 /* 48896 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17727 /* 48898 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17728 /* 48901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17729 /* 48904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17730 /* 48910 */ GIR_RootConstrainSelectedInstOperands,
17731 /* 48911 */ // GIR_Coverage, 1829,
17732 /* 48911 */ GIR_EraseRootFromParent_Done,
17733 /* 48912 */ // Label 1454: @48912
17734 /* 48912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1455*/ GIMT_Encode4(48972), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1911 //
17735 /* 48919 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl),
17736 /* 48924 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17737 /* 48927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17738 /* 48930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17739 /* 48933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17740 /* 48937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17741 /* 48941 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17742 /* 48945 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17743 /* 48949 */ // MIs[1] Operand 1
17744 /* 48949 */ // No operand predicates
17745 /* 48949 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17746 /* 48951 */ // (intrinsic_wo_chain:{ *:[i32] } 3826:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17747 /* 48951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL),
17748 /* 48954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17749 /* 48956 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17750 /* 48958 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17751 /* 48961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17752 /* 48964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17753 /* 48970 */ GIR_RootConstrainSelectedInstOperands,
17754 /* 48971 */ // GIR_Coverage, 1911,
17755 /* 48971 */ GIR_EraseRootFromParent_Done,
17756 /* 48972 */ // Label 1455: @48972
17757 /* 48972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1456*/ GIMT_Encode4(49032), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1912 //
17758 /* 48979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr),
17759 /* 48984 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17760 /* 48987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17761 /* 48990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17762 /* 48993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17763 /* 48997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17764 /* 49001 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17765 /* 49005 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17766 /* 49009 */ // MIs[1] Operand 1
17767 /* 49009 */ // No operand predicates
17768 /* 49009 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17769 /* 49011 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17770 /* 49011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR),
17771 /* 49014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17772 /* 49016 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17773 /* 49018 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17774 /* 49021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17775 /* 49024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17776 /* 49030 */ GIR_RootConstrainSelectedInstOperands,
17777 /* 49031 */ // GIR_Coverage, 1912,
17778 /* 49031 */ GIR_EraseRootFromParent_Done,
17779 /* 49032 */ // Label 1456: @49032
17780 /* 49032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1457*/ GIMT_Encode4(49092), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1913 //
17781 /* 49039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl),
17782 /* 49044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17783 /* 49047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17784 /* 49050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17785 /* 49053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17786 /* 49057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17787 /* 49061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17788 /* 49065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17789 /* 49069 */ // MIs[1] Operand 1
17790 /* 49069 */ // No operand predicates
17791 /* 49069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17792 /* 49071 */ // (intrinsic_wo_chain:{ *:[i32] } 3833:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17793 /* 49071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL),
17794 /* 49074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17795 /* 49076 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17796 /* 49078 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17797 /* 49081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17798 /* 49084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17799 /* 49090 */ GIR_RootConstrainSelectedInstOperands,
17800 /* 49091 */ // GIR_Coverage, 1913,
17801 /* 49091 */ GIR_EraseRootFromParent_Done,
17802 /* 49092 */ // Label 1457: @49092
17803 /* 49092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1458*/ GIMT_Encode4(49152), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1914 //
17804 /* 49099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr),
17805 /* 49104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17806 /* 49107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17807 /* 49110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17808 /* 49113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17809 /* 49117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17810 /* 49121 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17811 /* 49125 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17812 /* 49129 */ // MIs[1] Operand 1
17813 /* 49129 */ // No operand predicates
17814 /* 49129 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17815 /* 49131 */ // (intrinsic_wo_chain:{ *:[i32] } 3835:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17816 /* 49131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR),
17817 /* 49134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17818 /* 49136 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17819 /* 49138 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17820 /* 49141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17821 /* 49144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17822 /* 49150 */ GIR_RootConstrainSelectedInstOperands,
17823 /* 49151 */ // GIR_Coverage, 1914,
17824 /* 49151 */ GIR_EraseRootFromParent_Done,
17825 /* 49152 */ // Label 1458: @49152
17826 /* 49152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1459*/ GIMT_Encode4(49205), GIMT_Encode2(GIFBS_IsARM), // Rule ID 104 //
17827 /* 49159 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
17828 /* 49164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17829 /* 49167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17830 /* 49170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17831 /* 49173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17832 /* 49177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17833 /* 49181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17834 /* 49185 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17835 /* 49185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8),
17836 /* 49188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17837 /* 49190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17838 /* 49192 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17839 /* 49194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17840 /* 49197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17841 /* 49203 */ GIR_RootConstrainSelectedInstOperands,
17842 /* 49204 */ // GIR_Coverage, 104,
17843 /* 49204 */ GIR_EraseRootFromParent_Done,
17844 /* 49205 */ // Label 1459: @49205
17845 /* 49205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1460*/ GIMT_Encode4(49258), GIMT_Encode2(GIFBS_IsARM), // Rule ID 105 //
17846 /* 49212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
17847 /* 49217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17848 /* 49220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17849 /* 49223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17850 /* 49226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17851 /* 49230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17852 /* 49234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17853 /* 49238 */ // (intrinsic_wo_chain:{ *:[i32] } 4113:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17854 /* 49238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16),
17855 /* 49241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17856 /* 49243 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17857 /* 49245 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17858 /* 49247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17859 /* 49250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17860 /* 49256 */ GIR_RootConstrainSelectedInstOperands,
17861 /* 49257 */ // GIR_Coverage, 105,
17862 /* 49257 */ GIR_EraseRootFromParent_Done,
17863 /* 49258 */ // Label 1460: @49258
17864 /* 49258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1461*/ GIMT_Encode4(49311), GIMT_Encode2(GIFBS_IsARM), // Rule ID 106 //
17865 /* 49265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
17866 /* 49270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17867 /* 49273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17868 /* 49276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17869 /* 49279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17870 /* 49283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17871 /* 49287 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17872 /* 49291 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17873 /* 49291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16),
17874 /* 49294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17875 /* 49296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17876 /* 49298 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17877 /* 49300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17878 /* 49303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17879 /* 49309 */ GIR_RootConstrainSelectedInstOperands,
17880 /* 49310 */ // GIR_Coverage, 106,
17881 /* 49310 */ GIR_EraseRootFromParent_Done,
17882 /* 49311 */ // Label 1461: @49311
17883 /* 49311 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1462*/ GIMT_Encode4(49364), GIMT_Encode2(GIFBS_IsARM), // Rule ID 107 //
17884 /* 49318 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
17885 /* 49323 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17886 /* 49326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17887 /* 49329 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17888 /* 49332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17889 /* 49336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17890 /* 49340 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17891 /* 49344 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17892 /* 49344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8),
17893 /* 49347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17894 /* 49349 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17895 /* 49351 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17896 /* 49353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17897 /* 49356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17898 /* 49362 */ GIR_RootConstrainSelectedInstOperands,
17899 /* 49363 */ // GIR_Coverage, 107,
17900 /* 49363 */ GIR_EraseRootFromParent_Done,
17901 /* 49364 */ // Label 1462: @49364
17902 /* 49364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1463*/ GIMT_Encode4(49417), GIMT_Encode2(GIFBS_IsARM), // Rule ID 110 //
17903 /* 49371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
17904 /* 49376 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17905 /* 49379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17906 /* 49382 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17907 /* 49385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17908 /* 49389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17909 /* 49393 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17910 /* 49397 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17911 /* 49397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
17912 /* 49400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17913 /* 49402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17914 /* 49404 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
17915 /* 49406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17916 /* 49409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17917 /* 49415 */ GIR_RootConstrainSelectedInstOperands,
17918 /* 49416 */ // GIR_Coverage, 110,
17919 /* 49416 */ GIR_EraseRootFromParent_Done,
17920 /* 49417 */ // Label 1463: @49417
17921 /* 49417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1464*/ GIMT_Encode4(49470), GIMT_Encode2(GIFBS_IsARM), // Rule ID 111 //
17922 /* 49424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17923 /* 49429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17924 /* 49432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17925 /* 49435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17926 /* 49438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17927 /* 49442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17928 /* 49446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17929 /* 49450 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17930 /* 49450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
17931 /* 49453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17932 /* 49455 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17933 /* 49457 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
17934 /* 49459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17935 /* 49462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17936 /* 49468 */ GIR_RootConstrainSelectedInstOperands,
17937 /* 49469 */ // GIR_Coverage, 111,
17938 /* 49469 */ GIR_EraseRootFromParent_Done,
17939 /* 49470 */ // Label 1464: @49470
17940 /* 49470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1465*/ GIMT_Encode4(49523), GIMT_Encode2(GIFBS_IsARM), // Rule ID 112 //
17941 /* 49477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
17942 /* 49482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17943 /* 49485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17944 /* 49488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17945 /* 49491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17946 /* 49495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17947 /* 49499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17948 /* 49503 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17949 /* 49503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16),
17950 /* 49506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17951 /* 49508 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17952 /* 49510 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17953 /* 49512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17954 /* 49515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17955 /* 49521 */ GIR_RootConstrainSelectedInstOperands,
17956 /* 49522 */ // GIR_Coverage, 112,
17957 /* 49522 */ GIR_EraseRootFromParent_Done,
17958 /* 49523 */ // Label 1465: @49523
17959 /* 49523 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1466*/ GIMT_Encode4(49576), GIMT_Encode2(GIFBS_IsARM), // Rule ID 113 //
17960 /* 49530 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
17961 /* 49535 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17962 /* 49538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17963 /* 49541 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17964 /* 49544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17965 /* 49548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17966 /* 49552 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17967 /* 49556 */ // (intrinsic_wo_chain:{ *:[i32] } 4182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17968 /* 49556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8),
17969 /* 49559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17970 /* 49561 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17971 /* 49563 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17972 /* 49565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17973 /* 49568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17974 /* 49574 */ GIR_RootConstrainSelectedInstOperands,
17975 /* 49575 */ // GIR_Coverage, 113,
17976 /* 49575 */ GIR_EraseRootFromParent_Done,
17977 /* 49576 */ // Label 1466: @49576
17978 /* 49576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1467*/ GIMT_Encode4(49629), GIMT_Encode2(GIFBS_IsARM), // Rule ID 114 //
17979 /* 49583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
17980 /* 49588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17981 /* 49591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17982 /* 49594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17983 /* 49597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17984 /* 49601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17985 /* 49605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17986 /* 49609 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17987 /* 49609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16),
17988 /* 49612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17989 /* 49614 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17990 /* 49616 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17991 /* 49618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17992 /* 49621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17993 /* 49627 */ GIR_RootConstrainSelectedInstOperands,
17994 /* 49628 */ // GIR_Coverage, 114,
17995 /* 49628 */ GIR_EraseRootFromParent_Done,
17996 /* 49629 */ // Label 1467: @49629
17997 /* 49629 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1468*/ GIMT_Encode4(49682), GIMT_Encode2(GIFBS_IsARM), // Rule ID 115 //
17998 /* 49636 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
17999 /* 49641 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18000 /* 49644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18001 /* 49647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18002 /* 49650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18003 /* 49654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18004 /* 49658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18005 /* 49662 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18006 /* 49662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8),
18007 /* 49665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18008 /* 49667 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18009 /* 49669 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18010 /* 49671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18011 /* 49674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18012 /* 49680 */ GIR_RootConstrainSelectedInstOperands,
18013 /* 49681 */ // GIR_Coverage, 115,
18014 /* 49681 */ GIR_EraseRootFromParent_Done,
18015 /* 49682 */ // Label 1468: @49682
18016 /* 49682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1469*/ GIMT_Encode4(49735), GIMT_Encode2(GIFBS_IsARM), // Rule ID 116 //
18017 /* 49689 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
18018 /* 49694 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18019 /* 49697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18020 /* 49700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18021 /* 49703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18022 /* 49707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18023 /* 49711 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18024 /* 49715 */ // (intrinsic_wo_chain:{ *:[i32] } 4115:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18025 /* 49715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX),
18026 /* 49718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18027 /* 49720 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18028 /* 49722 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18029 /* 49724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18030 /* 49727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18031 /* 49733 */ GIR_RootConstrainSelectedInstOperands,
18032 /* 49734 */ // GIR_Coverage, 116,
18033 /* 49734 */ GIR_EraseRootFromParent_Done,
18034 /* 49735 */ // Label 1469: @49735
18035 /* 49735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1470*/ GIMT_Encode4(49788), GIMT_Encode2(GIFBS_IsARM), // Rule ID 117 //
18036 /* 49742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
18037 /* 49747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18038 /* 49750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18039 /* 49753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18040 /* 49756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18041 /* 49760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18042 /* 49764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18043 /* 49768 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18044 /* 49768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX),
18045 /* 49771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18046 /* 49773 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18047 /* 49775 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18048 /* 49777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18049 /* 49780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18050 /* 49786 */ GIR_RootConstrainSelectedInstOperands,
18051 /* 49787 */ // GIR_Coverage, 117,
18052 /* 49787 */ GIR_EraseRootFromParent_Done,
18053 /* 49788 */ // Label 1470: @49788
18054 /* 49788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1471*/ GIMT_Encode4(49841), GIMT_Encode2(GIFBS_IsARM), // Rule ID 118 //
18055 /* 49795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
18056 /* 49800 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18057 /* 49803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18058 /* 49806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18059 /* 49809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18060 /* 49813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18061 /* 49817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18062 /* 49821 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18063 /* 49821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX),
18064 /* 49824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18065 /* 49826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18066 /* 49828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18067 /* 49830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18068 /* 49833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18069 /* 49839 */ GIR_RootConstrainSelectedInstOperands,
18070 /* 49840 */ // GIR_Coverage, 118,
18071 /* 49840 */ GIR_EraseRootFromParent_Done,
18072 /* 49841 */ // Label 1471: @49841
18073 /* 49841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1472*/ GIMT_Encode4(49894), GIMT_Encode2(GIFBS_IsARM), // Rule ID 119 //
18074 /* 49848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
18075 /* 49853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18076 /* 49856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18077 /* 49859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18078 /* 49862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18079 /* 49866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18080 /* 49870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18081 /* 49874 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18082 /* 49874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX),
18083 /* 49877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18084 /* 49879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18085 /* 49881 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18086 /* 49883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18087 /* 49886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18088 /* 49892 */ GIR_RootConstrainSelectedInstOperands,
18089 /* 49893 */ // GIR_Coverage, 119,
18090 /* 49893 */ GIR_EraseRootFromParent_Done,
18091 /* 49894 */ // Label 1472: @49894
18092 /* 49894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1473*/ GIMT_Encode4(49947), GIMT_Encode2(GIFBS_IsARM), // Rule ID 132 //
18093 /* 49901 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
18094 /* 49906 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18095 /* 49909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18096 /* 49912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18097 /* 49915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18098 /* 49919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18099 /* 49923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18100 /* 49927 */ // (intrinsic_wo_chain:{ *:[i32] } 4127:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18101 /* 49927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX),
18102 /* 49930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18103 /* 49932 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18104 /* 49934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18105 /* 49936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18106 /* 49939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18107 /* 49945 */ GIR_RootConstrainSelectedInstOperands,
18108 /* 49946 */ // GIR_Coverage, 132,
18109 /* 49946 */ GIR_EraseRootFromParent_Done,
18110 /* 49947 */ // Label 1473: @49947
18111 /* 49947 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1474*/ GIMT_Encode4(50000), GIMT_Encode2(GIFBS_IsARM), // Rule ID 133 //
18112 /* 49954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
18113 /* 49959 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18114 /* 49962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18115 /* 49965 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18116 /* 49968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18117 /* 49972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18118 /* 49976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18119 /* 49980 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18120 /* 49980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16),
18121 /* 49983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18122 /* 49985 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18123 /* 49987 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18124 /* 49989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18125 /* 49992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18126 /* 49998 */ GIR_RootConstrainSelectedInstOperands,
18127 /* 49999 */ // GIR_Coverage, 133,
18128 /* 49999 */ GIR_EraseRootFromParent_Done,
18129 /* 50000 */ // Label 1474: @50000
18130 /* 50000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1475*/ GIMT_Encode4(50053), GIMT_Encode2(GIFBS_IsARM), // Rule ID 134 //
18131 /* 50007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
18132 /* 50012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18133 /* 50015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18134 /* 50018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18135 /* 50021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18136 /* 50025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18137 /* 50029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18138 /* 50033 */ // (intrinsic_wo_chain:{ *:[i32] } 4126:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18139 /* 50033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8),
18140 /* 50036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18141 /* 50038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18142 /* 50040 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18143 /* 50042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18144 /* 50045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18145 /* 50051 */ GIR_RootConstrainSelectedInstOperands,
18146 /* 50052 */ // GIR_Coverage, 134,
18147 /* 50052 */ GIR_EraseRootFromParent_Done,
18148 /* 50053 */ // Label 1475: @50053
18149 /* 50053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1476*/ GIMT_Encode4(50106), GIMT_Encode2(GIFBS_IsARM), // Rule ID 135 //
18150 /* 50060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
18151 /* 50065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18152 /* 50068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18153 /* 50071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18154 /* 50074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18155 /* 50078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18156 /* 50082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18157 /* 50086 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18158 /* 50086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX),
18159 /* 50089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18160 /* 50091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18161 /* 50093 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18162 /* 50095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18163 /* 50098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18164 /* 50104 */ GIR_RootConstrainSelectedInstOperands,
18165 /* 50105 */ // GIR_Coverage, 135,
18166 /* 50105 */ GIR_EraseRootFromParent_Done,
18167 /* 50106 */ // Label 1476: @50106
18168 /* 50106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1477*/ GIMT_Encode4(50159), GIMT_Encode2(GIFBS_IsARM), // Rule ID 136 //
18169 /* 50113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
18170 /* 50118 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18171 /* 50121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18172 /* 50124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18173 /* 50127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18174 /* 50131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18175 /* 50135 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18176 /* 50139 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18177 /* 50139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16),
18178 /* 50142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18179 /* 50144 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18180 /* 50146 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18181 /* 50148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18182 /* 50151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18183 /* 50157 */ GIR_RootConstrainSelectedInstOperands,
18184 /* 50158 */ // GIR_Coverage, 136,
18185 /* 50158 */ GIR_EraseRootFromParent_Done,
18186 /* 50159 */ // Label 1477: @50159
18187 /* 50159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1478*/ GIMT_Encode4(50212), GIMT_Encode2(GIFBS_IsARM), // Rule ID 137 //
18188 /* 50166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
18189 /* 50171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18190 /* 50174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18191 /* 50177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18192 /* 50180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18193 /* 50184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18194 /* 50188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18195 /* 50192 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18196 /* 50192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8),
18197 /* 50195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18198 /* 50197 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18199 /* 50199 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18200 /* 50201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18201 /* 50204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18202 /* 50210 */ GIR_RootConstrainSelectedInstOperands,
18203 /* 50211 */ // GIR_Coverage, 137,
18204 /* 50211 */ GIR_EraseRootFromParent_Done,
18205 /* 50212 */ // Label 1478: @50212
18206 /* 50212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1479*/ GIMT_Encode4(50265), GIMT_Encode2(GIFBS_IsARM), // Rule ID 138 //
18207 /* 50219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
18208 /* 50224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18209 /* 50227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18210 /* 50230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18211 /* 50233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18212 /* 50237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18213 /* 50241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18214 /* 50245 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18215 /* 50245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX),
18216 /* 50248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18217 /* 50250 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18218 /* 50252 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18219 /* 50254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18220 /* 50257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18221 /* 50263 */ GIR_RootConstrainSelectedInstOperands,
18222 /* 50264 */ // GIR_Coverage, 138,
18223 /* 50264 */ GIR_EraseRootFromParent_Done,
18224 /* 50265 */ // Label 1479: @50265
18225 /* 50265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1480*/ GIMT_Encode4(50318), GIMT_Encode2(GIFBS_IsARM), // Rule ID 139 //
18226 /* 50272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
18227 /* 50277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18228 /* 50280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18229 /* 50283 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18230 /* 50286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18231 /* 50290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18232 /* 50294 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18233 /* 50298 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18234 /* 50298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16),
18235 /* 50301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18236 /* 50303 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18237 /* 50305 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18238 /* 50307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18239 /* 50310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18240 /* 50316 */ GIR_RootConstrainSelectedInstOperands,
18241 /* 50317 */ // GIR_Coverage, 139,
18242 /* 50317 */ GIR_EraseRootFromParent_Done,
18243 /* 50318 */ // Label 1480: @50318
18244 /* 50318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1481*/ GIMT_Encode4(50371), GIMT_Encode2(GIFBS_IsARM), // Rule ID 140 //
18245 /* 50325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
18246 /* 50330 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18247 /* 50333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18248 /* 50336 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18249 /* 50339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18250 /* 50343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18251 /* 50347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18252 /* 50351 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18253 /* 50351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8),
18254 /* 50354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18255 /* 50356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18256 /* 50358 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18257 /* 50360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18258 /* 50363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18259 /* 50369 */ GIR_RootConstrainSelectedInstOperands,
18260 /* 50370 */ // GIR_Coverage, 140,
18261 /* 50370 */ GIR_EraseRootFromParent_Done,
18262 /* 50371 */ // Label 1481: @50371
18263 /* 50371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1482*/ GIMT_Encode4(50424), GIMT_Encode2(GIFBS_IsARM), // Rule ID 141 //
18264 /* 50378 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
18265 /* 50383 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18266 /* 50386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18267 /* 50389 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18268 /* 50392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18269 /* 50396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18270 /* 50400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18271 /* 50404 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18272 /* 50404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX),
18273 /* 50407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18274 /* 50409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18275 /* 50411 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18276 /* 50413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18277 /* 50416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18278 /* 50422 */ GIR_RootConstrainSelectedInstOperands,
18279 /* 50423 */ // GIR_Coverage, 141,
18280 /* 50423 */ GIR_EraseRootFromParent_Done,
18281 /* 50424 */ // Label 1482: @50424
18282 /* 50424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1483*/ GIMT_Encode4(50477), GIMT_Encode2(GIFBS_IsARM), // Rule ID 142 //
18283 /* 50431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
18284 /* 50436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18285 /* 50439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18286 /* 50442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18287 /* 50445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18288 /* 50449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18289 /* 50453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18290 /* 50457 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18291 /* 50457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16),
18292 /* 50460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18293 /* 50462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18294 /* 50464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18295 /* 50466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18296 /* 50469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18297 /* 50475 */ GIR_RootConstrainSelectedInstOperands,
18298 /* 50476 */ // GIR_Coverage, 142,
18299 /* 50476 */ GIR_EraseRootFromParent_Done,
18300 /* 50477 */ // Label 1483: @50477
18301 /* 50477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1484*/ GIMT_Encode4(50530), GIMT_Encode2(GIFBS_IsARM), // Rule ID 143 //
18302 /* 50484 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
18303 /* 50489 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18304 /* 50492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18305 /* 50495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18306 /* 50498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18307 /* 50502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18308 /* 50506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18309 /* 50510 */ // (intrinsic_wo_chain:{ *:[i32] } 4179:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18310 /* 50510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8),
18311 /* 50513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18312 /* 50515 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18313 /* 50517 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18314 /* 50519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18315 /* 50522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18316 /* 50528 */ GIR_RootConstrainSelectedInstOperands,
18317 /* 50529 */ // GIR_Coverage, 143,
18318 /* 50529 */ GIR_EraseRootFromParent_Done,
18319 /* 50530 */ // Label 1484: @50530
18320 /* 50530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1485*/ GIMT_Encode4(50583), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 144 //
18321 /* 50537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
18322 /* 50542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18323 /* 50545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18324 /* 50548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18325 /* 50551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18326 /* 50555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18327 /* 50559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18328 /* 50563 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
18329 /* 50563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8),
18330 /* 50566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18331 /* 50568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18332 /* 50570 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18333 /* 50572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18334 /* 50575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18335 /* 50581 */ GIR_RootConstrainSelectedInstOperands,
18336 /* 50582 */ // GIR_Coverage, 144,
18337 /* 50582 */ GIR_EraseRootFromParent_Done,
18338 /* 50583 */ // Label 1485: @50583
18339 /* 50583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1486*/ GIMT_Encode4(50627), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 203 //
18340 /* 50590 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
18341 /* 50595 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18342 /* 50598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18343 /* 50601 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18344 /* 50604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18345 /* 50608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18346 /* 50612 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18347 /* 50616 */ // (intrinsic_wo_chain:{ *:[i32] } 3733:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18348 /* 50616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B),
18349 /* 50619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18350 /* 50621 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18351 /* 50623 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18352 /* 50625 */ GIR_RootConstrainSelectedInstOperands,
18353 /* 50626 */ // GIR_Coverage, 203,
18354 /* 50626 */ GIR_EraseRootFromParent_Done,
18355 /* 50627 */ // Label 1486: @50627
18356 /* 50627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1487*/ GIMT_Encode4(50671), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 204 //
18357 /* 50634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
18358 /* 50639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18359 /* 50642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18360 /* 50645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18361 /* 50648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18362 /* 50652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18363 /* 50656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18364 /* 50660 */ // (intrinsic_wo_chain:{ *:[i32] } 3734:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18365 /* 50660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB),
18366 /* 50663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18367 /* 50665 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18368 /* 50667 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18369 /* 50669 */ GIR_RootConstrainSelectedInstOperands,
18370 /* 50670 */ // GIR_Coverage, 204,
18371 /* 50670 */ GIR_EraseRootFromParent_Done,
18372 /* 50671 */ // Label 1487: @50671
18373 /* 50671 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1488*/ GIMT_Encode4(50715), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 205 //
18374 /* 50678 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
18375 /* 50683 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18376 /* 50686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18377 /* 50689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18378 /* 50692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18379 /* 50696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18380 /* 50700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18381 /* 50704 */ // (intrinsic_wo_chain:{ *:[i32] } 3737:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18382 /* 50704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H),
18383 /* 50707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18384 /* 50709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18385 /* 50711 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18386 /* 50713 */ GIR_RootConstrainSelectedInstOperands,
18387 /* 50714 */ // GIR_Coverage, 205,
18388 /* 50714 */ GIR_EraseRootFromParent_Done,
18389 /* 50715 */ // Label 1488: @50715
18390 /* 50715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1489*/ GIMT_Encode4(50759), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 206 //
18391 /* 50722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
18392 /* 50727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18393 /* 50730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18394 /* 50733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18395 /* 50736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18396 /* 50740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18397 /* 50744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18398 /* 50748 */ // (intrinsic_wo_chain:{ *:[i32] } 3735:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18399 /* 50748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH),
18400 /* 50751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18401 /* 50753 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18402 /* 50755 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18403 /* 50757 */ GIR_RootConstrainSelectedInstOperands,
18404 /* 50758 */ // GIR_Coverage, 206,
18405 /* 50758 */ GIR_EraseRootFromParent_Done,
18406 /* 50759 */ // Label 1489: @50759
18407 /* 50759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1490*/ GIMT_Encode4(50803), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 207 //
18408 /* 50766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
18409 /* 50771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18410 /* 50774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18411 /* 50777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18412 /* 50780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18413 /* 50784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18414 /* 50788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18415 /* 50792 */ // (intrinsic_wo_chain:{ *:[i32] } 3738:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18416 /* 50792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W),
18417 /* 50795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18418 /* 50797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18419 /* 50799 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18420 /* 50801 */ GIR_RootConstrainSelectedInstOperands,
18421 /* 50802 */ // GIR_Coverage, 207,
18422 /* 50802 */ GIR_EraseRootFromParent_Done,
18423 /* 50803 */ // Label 1490: @50803
18424 /* 50803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1491*/ GIMT_Encode4(50847), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 208 //
18425 /* 50810 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
18426 /* 50815 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18427 /* 50818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18428 /* 50821 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18429 /* 50824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18430 /* 50828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18431 /* 50832 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18432 /* 50836 */ // (intrinsic_wo_chain:{ *:[i32] } 3736:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18433 /* 50836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW),
18434 /* 50839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18435 /* 50841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18436 /* 50843 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18437 /* 50845 */ GIR_RootConstrainSelectedInstOperands,
18438 /* 50846 */ // GIR_Coverage, 208,
18439 /* 50846 */ GIR_EraseRootFromParent_Done,
18440 /* 50847 */ // Label 1491: @50847
18441 /* 50847 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1492*/ GIMT_Encode4(50900), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 431 //
18442 /* 50854 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
18443 /* 50859 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18444 /* 50862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18445 /* 50865 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18446 /* 50868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18447 /* 50872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18448 /* 50876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18449 /* 50880 */ // (intrinsic_wo_chain:{ *:[i32] } 4113:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18450 /* 50880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16),
18451 /* 50883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18452 /* 50885 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18453 /* 50887 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18454 /* 50889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18455 /* 50892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18456 /* 50898 */ GIR_RootConstrainSelectedInstOperands,
18457 /* 50899 */ // GIR_Coverage, 431,
18458 /* 50899 */ GIR_EraseRootFromParent_Done,
18459 /* 50900 */ // Label 1492: @50900
18460 /* 50900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1493*/ GIMT_Encode4(50953), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 432 //
18461 /* 50907 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
18462 /* 50912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18463 /* 50915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18464 /* 50918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18465 /* 50921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18466 /* 50925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18467 /* 50929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18468 /* 50933 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18469 /* 50933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8),
18470 /* 50936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18471 /* 50938 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18472 /* 50940 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18473 /* 50942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18474 /* 50945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18475 /* 50951 */ GIR_RootConstrainSelectedInstOperands,
18476 /* 50952 */ // GIR_Coverage, 432,
18477 /* 50952 */ GIR_EraseRootFromParent_Done,
18478 /* 50953 */ // Label 1493: @50953
18479 /* 50953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1494*/ GIMT_Encode4(51006), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 433 //
18480 /* 50960 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
18481 /* 50965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18482 /* 50968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18483 /* 50971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18484 /* 50974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18485 /* 50978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18486 /* 50982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18487 /* 50986 */ // (intrinsic_wo_chain:{ *:[i32] } 4115:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18488 /* 50986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX),
18489 /* 50989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18490 /* 50991 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18491 /* 50993 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18492 /* 50995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18493 /* 50998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18494 /* 51004 */ GIR_RootConstrainSelectedInstOperands,
18495 /* 51005 */ // GIR_Coverage, 433,
18496 /* 51005 */ GIR_EraseRootFromParent_Done,
18497 /* 51006 */ // Label 1494: @51006
18498 /* 51006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1495*/ GIMT_Encode4(51059), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 434 //
18499 /* 51013 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
18500 /* 51018 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18501 /* 51021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18502 /* 51024 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18503 /* 51027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18504 /* 51031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18505 /* 51035 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18506 /* 51039 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18507 /* 51039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8),
18508 /* 51042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18509 /* 51044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18510 /* 51046 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18511 /* 51048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18512 /* 51051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18513 /* 51057 */ GIR_RootConstrainSelectedInstOperands,
18514 /* 51058 */ // GIR_Coverage, 434,
18515 /* 51058 */ GIR_EraseRootFromParent_Done,
18516 /* 51059 */ // Label 1495: @51059
18517 /* 51059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1496*/ GIMT_Encode4(51112), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 435 //
18518 /* 51066 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
18519 /* 51071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18520 /* 51074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18521 /* 51077 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18522 /* 51080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18523 /* 51084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18524 /* 51088 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18525 /* 51092 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18526 /* 51092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX),
18527 /* 51095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18528 /* 51097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18529 /* 51099 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18530 /* 51101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18531 /* 51104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18532 /* 51110 */ GIR_RootConstrainSelectedInstOperands,
18533 /* 51111 */ // GIR_Coverage, 435,
18534 /* 51111 */ GIR_EraseRootFromParent_Done,
18535 /* 51112 */ // Label 1496: @51112
18536 /* 51112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1497*/ GIMT_Encode4(51165), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 436 //
18537 /* 51119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
18538 /* 51124 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18539 /* 51127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18540 /* 51130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18541 /* 51133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18542 /* 51137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18543 /* 51141 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18544 /* 51145 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18545 /* 51145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16),
18546 /* 51148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18547 /* 51150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18548 /* 51152 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18549 /* 51154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18550 /* 51157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18551 /* 51163 */ GIR_RootConstrainSelectedInstOperands,
18552 /* 51164 */ // GIR_Coverage, 436,
18553 /* 51164 */ GIR_EraseRootFromParent_Done,
18554 /* 51165 */ // Label 1497: @51165
18555 /* 51165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1498*/ GIMT_Encode4(51218), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 437 //
18556 /* 51172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
18557 /* 51177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18558 /* 51180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18559 /* 51183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18560 /* 51186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18561 /* 51190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18562 /* 51194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18563 /* 51198 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18564 /* 51198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8),
18565 /* 51201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18566 /* 51203 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18567 /* 51205 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18568 /* 51207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18569 /* 51210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18570 /* 51216 */ GIR_RootConstrainSelectedInstOperands,
18571 /* 51217 */ // GIR_Coverage, 437,
18572 /* 51217 */ GIR_EraseRootFromParent_Done,
18573 /* 51218 */ // Label 1498: @51218
18574 /* 51218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1499*/ GIMT_Encode4(51271), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 438 //
18575 /* 51225 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
18576 /* 51230 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18577 /* 51233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18578 /* 51236 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18579 /* 51239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18580 /* 51243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18581 /* 51247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18582 /* 51251 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18583 /* 51251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16),
18584 /* 51254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18585 /* 51256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18586 /* 51258 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18587 /* 51260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18588 /* 51263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18589 /* 51269 */ GIR_RootConstrainSelectedInstOperands,
18590 /* 51270 */ // GIR_Coverage, 438,
18591 /* 51270 */ GIR_EraseRootFromParent_Done,
18592 /* 51271 */ // Label 1499: @51271
18593 /* 51271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1500*/ GIMT_Encode4(51324), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 439 //
18594 /* 51278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
18595 /* 51283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18596 /* 51286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18597 /* 51289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18598 /* 51292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18599 /* 51296 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18600 /* 51300 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18601 /* 51304 */ // (intrinsic_wo_chain:{ *:[i32] } 4182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18602 /* 51304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8),
18603 /* 51307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18604 /* 51309 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18605 /* 51311 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18606 /* 51313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18607 /* 51316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18608 /* 51322 */ GIR_RootConstrainSelectedInstOperands,
18609 /* 51323 */ // GIR_Coverage, 439,
18610 /* 51323 */ GIR_EraseRootFromParent_Done,
18611 /* 51324 */ // Label 1500: @51324
18612 /* 51324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1501*/ GIMT_Encode4(51377), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 440 //
18613 /* 51331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
18614 /* 51336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18615 /* 51339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18616 /* 51342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18617 /* 51345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18618 /* 51349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18619 /* 51353 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18620 /* 51357 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18621 /* 51357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX),
18622 /* 51360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18623 /* 51362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18624 /* 51364 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18625 /* 51366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18626 /* 51369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18627 /* 51375 */ GIR_RootConstrainSelectedInstOperands,
18628 /* 51376 */ // GIR_Coverage, 440,
18629 /* 51376 */ GIR_EraseRootFromParent_Done,
18630 /* 51377 */ // Label 1501: @51377
18631 /* 51377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1502*/ GIMT_Encode4(51430), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 441 //
18632 /* 51384 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
18633 /* 51389 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18634 /* 51392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18635 /* 51395 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18636 /* 51398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18637 /* 51402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18638 /* 51406 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18639 /* 51410 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18640 /* 51410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX),
18641 /* 51413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18642 /* 51415 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18643 /* 51417 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18644 /* 51419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18645 /* 51422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18646 /* 51428 */ GIR_RootConstrainSelectedInstOperands,
18647 /* 51429 */ // GIR_Coverage, 441,
18648 /* 51429 */ GIR_EraseRootFromParent_Done,
18649 /* 51430 */ // Label 1502: @51430
18650 /* 51430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1503*/ GIMT_Encode4(51483), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 442 //
18651 /* 51437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
18652 /* 51442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18653 /* 51445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18654 /* 51448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18655 /* 51451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18656 /* 51455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18657 /* 51459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18658 /* 51463 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18659 /* 51463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16),
18660 /* 51466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18661 /* 51468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18662 /* 51470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18663 /* 51472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18664 /* 51475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18665 /* 51481 */ GIR_RootConstrainSelectedInstOperands,
18666 /* 51482 */ // GIR_Coverage, 442,
18667 /* 51482 */ GIR_EraseRootFromParent_Done,
18668 /* 51483 */ // Label 1503: @51483
18669 /* 51483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1504*/ GIMT_Encode4(51536), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 455 //
18670 /* 51490 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
18671 /* 51495 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18672 /* 51498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18673 /* 51501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18674 /* 51504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18675 /* 51508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18676 /* 51512 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18677 /* 51516 */ // (intrinsic_wo_chain:{ *:[i32] } 4127:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18678 /* 51516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX),
18679 /* 51519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18680 /* 51521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18681 /* 51523 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18682 /* 51525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18683 /* 51528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18684 /* 51534 */ GIR_RootConstrainSelectedInstOperands,
18685 /* 51535 */ // GIR_Coverage, 455,
18686 /* 51535 */ GIR_EraseRootFromParent_Done,
18687 /* 51536 */ // Label 1504: @51536
18688 /* 51536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1505*/ GIMT_Encode4(51589), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 456 //
18689 /* 51543 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
18690 /* 51548 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18691 /* 51551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18692 /* 51554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18693 /* 51557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18694 /* 51561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18695 /* 51565 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18696 /* 51569 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18697 /* 51569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16),
18698 /* 51572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18699 /* 51574 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18700 /* 51576 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18701 /* 51578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18702 /* 51581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18703 /* 51587 */ GIR_RootConstrainSelectedInstOperands,
18704 /* 51588 */ // GIR_Coverage, 456,
18705 /* 51588 */ GIR_EraseRootFromParent_Done,
18706 /* 51589 */ // Label 1505: @51589
18707 /* 51589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1506*/ GIMT_Encode4(51642), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 457 //
18708 /* 51596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
18709 /* 51601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18710 /* 51604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18711 /* 51607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18712 /* 51610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18713 /* 51614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18714 /* 51618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18715 /* 51622 */ // (intrinsic_wo_chain:{ *:[i32] } 4126:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18716 /* 51622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8),
18717 /* 51625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18718 /* 51627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18719 /* 51629 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18720 /* 51631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18721 /* 51634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18722 /* 51640 */ GIR_RootConstrainSelectedInstOperands,
18723 /* 51641 */ // GIR_Coverage, 457,
18724 /* 51641 */ GIR_EraseRootFromParent_Done,
18725 /* 51642 */ // Label 1506: @51642
18726 /* 51642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1507*/ GIMT_Encode4(51695), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 458 //
18727 /* 51649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
18728 /* 51654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18729 /* 51657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18730 /* 51660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18731 /* 51663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18732 /* 51667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18733 /* 51671 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18734 /* 51675 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18735 /* 51675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX),
18736 /* 51678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18737 /* 51680 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18738 /* 51682 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18739 /* 51684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18740 /* 51687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18741 /* 51693 */ GIR_RootConstrainSelectedInstOperands,
18742 /* 51694 */ // GIR_Coverage, 458,
18743 /* 51694 */ GIR_EraseRootFromParent_Done,
18744 /* 51695 */ // Label 1507: @51695
18745 /* 51695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1508*/ GIMT_Encode4(51748), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 459 //
18746 /* 51702 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
18747 /* 51707 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18748 /* 51710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18749 /* 51713 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18750 /* 51716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18751 /* 51720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18752 /* 51724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18753 /* 51728 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18754 /* 51728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16),
18755 /* 51731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18756 /* 51733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18757 /* 51735 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18758 /* 51737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18759 /* 51740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18760 /* 51746 */ GIR_RootConstrainSelectedInstOperands,
18761 /* 51747 */ // GIR_Coverage, 459,
18762 /* 51747 */ GIR_EraseRootFromParent_Done,
18763 /* 51748 */ // Label 1508: @51748
18764 /* 51748 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1509*/ GIMT_Encode4(51801), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 460 //
18765 /* 51755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
18766 /* 51760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18767 /* 51763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18768 /* 51766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18769 /* 51769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18770 /* 51773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18771 /* 51777 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18772 /* 51781 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18773 /* 51781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8),
18774 /* 51784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18775 /* 51786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18776 /* 51788 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18777 /* 51790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18778 /* 51793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18779 /* 51799 */ GIR_RootConstrainSelectedInstOperands,
18780 /* 51800 */ // GIR_Coverage, 460,
18781 /* 51800 */ GIR_EraseRootFromParent_Done,
18782 /* 51801 */ // Label 1509: @51801
18783 /* 51801 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1510*/ GIMT_Encode4(51854), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 461 //
18784 /* 51808 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
18785 /* 51813 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18786 /* 51816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18787 /* 51819 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18788 /* 51822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18789 /* 51826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18790 /* 51830 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18791 /* 51834 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18792 /* 51834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX),
18793 /* 51837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18794 /* 51839 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18795 /* 51841 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18796 /* 51843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18797 /* 51846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18798 /* 51852 */ GIR_RootConstrainSelectedInstOperands,
18799 /* 51853 */ // GIR_Coverage, 461,
18800 /* 51853 */ GIR_EraseRootFromParent_Done,
18801 /* 51854 */ // Label 1510: @51854
18802 /* 51854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1511*/ GIMT_Encode4(51907), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 462 //
18803 /* 51861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
18804 /* 51866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18805 /* 51869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18806 /* 51872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18807 /* 51875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18808 /* 51879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18809 /* 51883 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18810 /* 51887 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18811 /* 51887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16),
18812 /* 51890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18813 /* 51892 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18814 /* 51894 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18815 /* 51896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18816 /* 51899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18817 /* 51905 */ GIR_RootConstrainSelectedInstOperands,
18818 /* 51906 */ // GIR_Coverage, 462,
18819 /* 51906 */ GIR_EraseRootFromParent_Done,
18820 /* 51907 */ // Label 1511: @51907
18821 /* 51907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1512*/ GIMT_Encode4(51960), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 463 //
18822 /* 51914 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
18823 /* 51919 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18824 /* 51922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18825 /* 51925 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18826 /* 51928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18827 /* 51932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18828 /* 51936 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18829 /* 51940 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18830 /* 51940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8),
18831 /* 51943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18832 /* 51945 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18833 /* 51947 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18834 /* 51949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18835 /* 51952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18836 /* 51958 */ GIR_RootConstrainSelectedInstOperands,
18837 /* 51959 */ // GIR_Coverage, 463,
18838 /* 51959 */ GIR_EraseRootFromParent_Done,
18839 /* 51960 */ // Label 1512: @51960
18840 /* 51960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1513*/ GIMT_Encode4(52013), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 464 //
18841 /* 51967 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
18842 /* 51972 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18843 /* 51975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18844 /* 51978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18845 /* 51981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18846 /* 51985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18847 /* 51989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18848 /* 51993 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18849 /* 51993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX),
18850 /* 51996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18851 /* 51998 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18852 /* 52000 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18853 /* 52002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18854 /* 52005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18855 /* 52011 */ GIR_RootConstrainSelectedInstOperands,
18856 /* 52012 */ // GIR_Coverage, 464,
18857 /* 52012 */ GIR_EraseRootFromParent_Done,
18858 /* 52013 */ // Label 1513: @52013
18859 /* 52013 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1514*/ GIMT_Encode4(52066), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 465 //
18860 /* 52020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
18861 /* 52025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18862 /* 52028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18863 /* 52031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18864 /* 52034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18865 /* 52038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18866 /* 52042 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18867 /* 52046 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18868 /* 52046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16),
18869 /* 52049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18870 /* 52051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18871 /* 52053 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18872 /* 52055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18873 /* 52058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18874 /* 52064 */ GIR_RootConstrainSelectedInstOperands,
18875 /* 52065 */ // GIR_Coverage, 465,
18876 /* 52065 */ GIR_EraseRootFromParent_Done,
18877 /* 52066 */ // Label 1514: @52066
18878 /* 52066 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1515*/ GIMT_Encode4(52119), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 466 //
18879 /* 52073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
18880 /* 52078 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18881 /* 52081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18882 /* 52084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18883 /* 52087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18884 /* 52091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18885 /* 52095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18886 /* 52099 */ // (intrinsic_wo_chain:{ *:[i32] } 4179:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18887 /* 52099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8),
18888 /* 52102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18889 /* 52104 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18890 /* 52106 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18891 /* 52108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18892 /* 52111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18893 /* 52117 */ GIR_RootConstrainSelectedInstOperands,
18894 /* 52118 */ // GIR_Coverage, 466,
18895 /* 52118 */ GIR_EraseRootFromParent_Done,
18896 /* 52119 */ // Label 1515: @52119
18897 /* 52119 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1516*/ GIMT_Encode4(52172), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 467 //
18898 /* 52126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
18899 /* 52131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18900 /* 52134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18901 /* 52137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18902 /* 52140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18903 /* 52144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18904 /* 52148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18905 /* 52152 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18906 /* 52152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8),
18907 /* 52155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18908 /* 52157 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18909 /* 52159 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18910 /* 52161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18911 /* 52164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18912 /* 52170 */ GIR_RootConstrainSelectedInstOperands,
18913 /* 52171 */ // GIR_Coverage, 467,
18914 /* 52171 */ GIR_EraseRootFromParent_Done,
18915 /* 52172 */ // Label 1516: @52172
18916 /* 52172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1517*/ GIMT_Encode4(52225), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 523 //
18917 /* 52179 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
18918 /* 52184 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18919 /* 52187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18920 /* 52190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18921 /* 52193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18922 /* 52197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18923 /* 52201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18924 /* 52205 */ // (intrinsic_wo_chain:{ *:[i32] } 4145:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18925 /* 52205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD),
18926 /* 52208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18927 /* 52210 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18928 /* 52212 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18929 /* 52214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18930 /* 52217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18931 /* 52223 */ GIR_RootConstrainSelectedInstOperands,
18932 /* 52224 */ // GIR_Coverage, 523,
18933 /* 52224 */ GIR_EraseRootFromParent_Done,
18934 /* 52225 */ // Label 1517: @52225
18935 /* 52225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1518*/ GIMT_Encode4(52278), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 524 //
18936 /* 52232 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
18937 /* 52237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18938 /* 52240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18939 /* 52243 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18940 /* 52246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18941 /* 52250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18942 /* 52254 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18943 /* 52258 */ // (intrinsic_wo_chain:{ *:[i32] } 4146:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18944 /* 52258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX),
18945 /* 52261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18946 /* 52263 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18947 /* 52265 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18948 /* 52267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18949 /* 52270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18950 /* 52276 */ GIR_RootConstrainSelectedInstOperands,
18951 /* 52277 */ // GIR_Coverage, 524,
18952 /* 52277 */ GIR_EraseRootFromParent_Done,
18953 /* 52278 */ // Label 1518: @52278
18954 /* 52278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1519*/ GIMT_Encode4(52331), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 525 //
18955 /* 52285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
18956 /* 52290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18957 /* 52293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18958 /* 52296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18959 /* 52299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18960 /* 52303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18961 /* 52307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18962 /* 52311 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18963 /* 52311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD),
18964 /* 52314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18965 /* 52316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18966 /* 52318 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18967 /* 52320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18968 /* 52323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18969 /* 52329 */ GIR_RootConstrainSelectedInstOperands,
18970 /* 52330 */ // GIR_Coverage, 525,
18971 /* 52330 */ GIR_EraseRootFromParent_Done,
18972 /* 52331 */ // Label 1519: @52331
18973 /* 52331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1520*/ GIMT_Encode4(52384), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 526 //
18974 /* 52338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
18975 /* 52343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18976 /* 52346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18977 /* 52349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18978 /* 52352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18979 /* 52356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18980 /* 52360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18981 /* 52364 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18982 /* 52364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX),
18983 /* 52367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18984 /* 52369 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18985 /* 52371 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18986 /* 52373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18987 /* 52376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18988 /* 52382 */ GIR_RootConstrainSelectedInstOperands,
18989 /* 52383 */ // GIR_Coverage, 526,
18990 /* 52383 */ GIR_EraseRootFromParent_Done,
18991 /* 52384 */ // Label 1520: @52384
18992 /* 52384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1521*/ GIMT_Encode4(52428), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 540 //
18993 /* 52391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
18994 /* 52396 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18995 /* 52399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18996 /* 52402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18997 /* 52405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18998 /* 52409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18999 /* 52413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19000 /* 52417 */ // (intrinsic_wo_chain:{ *:[i32] } 3733:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19001 /* 52417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B),
19002 /* 52420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19003 /* 52422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19004 /* 52424 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19005 /* 52426 */ GIR_RootConstrainSelectedInstOperands,
19006 /* 52427 */ // GIR_Coverage, 540,
19007 /* 52427 */ GIR_EraseRootFromParent_Done,
19008 /* 52428 */ // Label 1521: @52428
19009 /* 52428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1522*/ GIMT_Encode4(52472), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 541 //
19010 /* 52435 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
19011 /* 52440 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19012 /* 52443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19013 /* 52446 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19014 /* 52449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19015 /* 52453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19016 /* 52457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19017 /* 52461 */ // (intrinsic_wo_chain:{ *:[i32] } 3734:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19018 /* 52461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB),
19019 /* 52464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19020 /* 52466 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19021 /* 52468 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19022 /* 52470 */ GIR_RootConstrainSelectedInstOperands,
19023 /* 52471 */ // GIR_Coverage, 541,
19024 /* 52471 */ GIR_EraseRootFromParent_Done,
19025 /* 52472 */ // Label 1522: @52472
19026 /* 52472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1523*/ GIMT_Encode4(52516), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 542 //
19027 /* 52479 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
19028 /* 52484 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19029 /* 52487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19030 /* 52490 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19031 /* 52493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19032 /* 52497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19033 /* 52501 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19034 /* 52505 */ // (intrinsic_wo_chain:{ *:[i32] } 3737:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19035 /* 52505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H),
19036 /* 52508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19037 /* 52510 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19038 /* 52512 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19039 /* 52514 */ GIR_RootConstrainSelectedInstOperands,
19040 /* 52515 */ // GIR_Coverage, 542,
19041 /* 52515 */ GIR_EraseRootFromParent_Done,
19042 /* 52516 */ // Label 1523: @52516
19043 /* 52516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1524*/ GIMT_Encode4(52560), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 543 //
19044 /* 52523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
19045 /* 52528 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19046 /* 52531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19047 /* 52534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19048 /* 52537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19049 /* 52541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19050 /* 52545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19051 /* 52549 */ // (intrinsic_wo_chain:{ *:[i32] } 3735:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19052 /* 52549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH),
19053 /* 52552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19054 /* 52554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19055 /* 52556 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19056 /* 52558 */ GIR_RootConstrainSelectedInstOperands,
19057 /* 52559 */ // GIR_Coverage, 543,
19058 /* 52559 */ GIR_EraseRootFromParent_Done,
19059 /* 52560 */ // Label 1524: @52560
19060 /* 52560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1525*/ GIMT_Encode4(52604), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 544 //
19061 /* 52567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
19062 /* 52572 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19063 /* 52575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19064 /* 52578 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19065 /* 52581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19066 /* 52585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19067 /* 52589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19068 /* 52593 */ // (intrinsic_wo_chain:{ *:[i32] } 3738:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19069 /* 52593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W),
19070 /* 52596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19071 /* 52598 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19072 /* 52600 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19073 /* 52602 */ GIR_RootConstrainSelectedInstOperands,
19074 /* 52603 */ // GIR_Coverage, 544,
19075 /* 52603 */ GIR_EraseRootFromParent_Done,
19076 /* 52604 */ // Label 1525: @52604
19077 /* 52604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1526*/ GIMT_Encode4(52648), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 545 //
19078 /* 52611 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
19079 /* 52616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19080 /* 52619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19081 /* 52622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19082 /* 52625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19083 /* 52629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19084 /* 52633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19085 /* 52637 */ // (intrinsic_wo_chain:{ *:[i32] } 3736:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19086 /* 52637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW),
19087 /* 52640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19088 /* 52642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19089 /* 52644 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19090 /* 52646 */ GIR_RootConstrainSelectedInstOperands,
19091 /* 52647 */ // GIR_Coverage, 545,
19092 /* 52647 */ GIR_EraseRootFromParent_Done,
19093 /* 52648 */ // Label 1526: @52648
19094 /* 52648 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(52970),
19095 /* 52653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19096 /* 52658 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1534*/ GIMT_Encode4(52969),
19097 /* 52669 */ /*GILLT_v8s8*//*Label 1528*/ GIMT_Encode4(52693),
19098 /* 52673 */ /*GILLT_v16s8*//*Label 1529*/ GIMT_Encode4(52739),
19099 /* 52677 */ /*GILLT_v4s16*//*Label 1530*/ GIMT_Encode4(52785),
19100 /* 52681 */ /*GILLT_v8s16*//*Label 1531*/ GIMT_Encode4(52831),
19101 /* 52685 */ /*GILLT_v2s32*//*Label 1532*/ GIMT_Encode4(52877),
19102 /* 52689 */ /*GILLT_v4s32*//*Label 1533*/ GIMT_Encode4(52923),
19103 /* 52693 */ // Label 1528: @52693
19104 /* 52693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1535*/ GIMT_Encode4(52738), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 916 //
19105 /* 52700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19106 /* 52703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19107 /* 52706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19108 /* 52710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19109 /* 52714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19110 /* 52718 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4023:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19111 /* 52718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8),
19112 /* 52721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19113 /* 52723 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19114 /* 52725 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19115 /* 52727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19116 /* 52730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19117 /* 52736 */ GIR_RootConstrainSelectedInstOperands,
19118 /* 52737 */ // GIR_Coverage, 916,
19119 /* 52737 */ GIR_EraseRootFromParent_Done,
19120 /* 52738 */ // Label 1535: @52738
19121 /* 52738 */ GIM_Reject,
19122 /* 52739 */ // Label 1529: @52739
19123 /* 52739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1536*/ GIMT_Encode4(52784), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 917 //
19124 /* 52746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19125 /* 52749 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19126 /* 52752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19127 /* 52756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19128 /* 52760 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19129 /* 52764 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4023:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19130 /* 52764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8),
19131 /* 52767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19132 /* 52769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19133 /* 52771 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19134 /* 52773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19135 /* 52776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19136 /* 52782 */ GIR_RootConstrainSelectedInstOperands,
19137 /* 52783 */ // GIR_Coverage, 917,
19138 /* 52783 */ GIR_EraseRootFromParent_Done,
19139 /* 52784 */ // Label 1536: @52784
19140 /* 52784 */ GIM_Reject,
19141 /* 52785 */ // Label 1530: @52785
19142 /* 52785 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1537*/ GIMT_Encode4(52830), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 912 //
19143 /* 52792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19144 /* 52795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19145 /* 52798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19146 /* 52802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19147 /* 52806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19148 /* 52810 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4023:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19149 /* 52810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16),
19150 /* 52813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19151 /* 52815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19152 /* 52817 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19153 /* 52819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19154 /* 52822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19155 /* 52828 */ GIR_RootConstrainSelectedInstOperands,
19156 /* 52829 */ // GIR_Coverage, 912,
19157 /* 52829 */ GIR_EraseRootFromParent_Done,
19158 /* 52830 */ // Label 1537: @52830
19159 /* 52830 */ GIM_Reject,
19160 /* 52831 */ // Label 1531: @52831
19161 /* 52831 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1538*/ GIMT_Encode4(52876), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 914 //
19162 /* 52838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19163 /* 52841 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19164 /* 52844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19165 /* 52848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19166 /* 52852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19167 /* 52856 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4023:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19168 /* 52856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16),
19169 /* 52859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19170 /* 52861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19171 /* 52863 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19172 /* 52865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19173 /* 52868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19174 /* 52874 */ GIR_RootConstrainSelectedInstOperands,
19175 /* 52875 */ // GIR_Coverage, 914,
19176 /* 52875 */ GIR_EraseRootFromParent_Done,
19177 /* 52876 */ // Label 1538: @52876
19178 /* 52876 */ GIM_Reject,
19179 /* 52877 */ // Label 1532: @52877
19180 /* 52877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1539*/ GIMT_Encode4(52922), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 913 //
19181 /* 52884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19182 /* 52887 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19183 /* 52890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19184 /* 52894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19185 /* 52898 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19186 /* 52902 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4023:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19187 /* 52902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32),
19188 /* 52905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19189 /* 52907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19190 /* 52909 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19191 /* 52911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19192 /* 52914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19193 /* 52920 */ GIR_RootConstrainSelectedInstOperands,
19194 /* 52921 */ // GIR_Coverage, 913,
19195 /* 52921 */ GIR_EraseRootFromParent_Done,
19196 /* 52922 */ // Label 1539: @52922
19197 /* 52922 */ GIM_Reject,
19198 /* 52923 */ // Label 1533: @52923
19199 /* 52923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1540*/ GIMT_Encode4(52968), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 915 //
19200 /* 52930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19201 /* 52933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19202 /* 52936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19203 /* 52940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19204 /* 52944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19205 /* 52948 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4023:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19206 /* 52948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32),
19207 /* 52951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19208 /* 52953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19209 /* 52955 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19210 /* 52957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19211 /* 52960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19212 /* 52966 */ GIR_RootConstrainSelectedInstOperands,
19213 /* 52967 */ // GIR_Coverage, 915,
19214 /* 52967 */ GIR_EraseRootFromParent_Done,
19215 /* 52968 */ // Label 1540: @52968
19216 /* 52968 */ GIM_Reject,
19217 /* 52969 */ // Label 1534: @52969
19218 /* 52969 */ GIM_Reject,
19219 /* 52970 */ // Label 1527: @52970
19220 /* 52970 */ GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(53292),
19221 /* 52975 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19222 /* 52980 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1548*/ GIMT_Encode4(53291),
19223 /* 52991 */ /*GILLT_v8s8*//*Label 1542*/ GIMT_Encode4(53015),
19224 /* 52995 */ /*GILLT_v16s8*//*Label 1543*/ GIMT_Encode4(53061),
19225 /* 52999 */ /*GILLT_v4s16*//*Label 1544*/ GIMT_Encode4(53107),
19226 /* 53003 */ /*GILLT_v8s16*//*Label 1545*/ GIMT_Encode4(53153),
19227 /* 53007 */ /*GILLT_v2s32*//*Label 1546*/ GIMT_Encode4(53199),
19228 /* 53011 */ /*GILLT_v4s32*//*Label 1547*/ GIMT_Encode4(53245),
19229 /* 53015 */ // Label 1542: @53015
19230 /* 53015 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1549*/ GIMT_Encode4(53060), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 922 //
19231 /* 53022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19232 /* 53025 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19233 /* 53028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19234 /* 53032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19235 /* 53036 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19236 /* 53040 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4024:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19237 /* 53040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8),
19238 /* 53043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19239 /* 53045 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19240 /* 53047 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19241 /* 53049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19242 /* 53052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19243 /* 53058 */ GIR_RootConstrainSelectedInstOperands,
19244 /* 53059 */ // GIR_Coverage, 922,
19245 /* 53059 */ GIR_EraseRootFromParent_Done,
19246 /* 53060 */ // Label 1549: @53060
19247 /* 53060 */ GIM_Reject,
19248 /* 53061 */ // Label 1543: @53061
19249 /* 53061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1550*/ GIMT_Encode4(53106), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 923 //
19250 /* 53068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19251 /* 53071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19252 /* 53074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19253 /* 53078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19254 /* 53082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19255 /* 53086 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4024:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19256 /* 53086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8),
19257 /* 53089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19258 /* 53091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19259 /* 53093 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19260 /* 53095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19261 /* 53098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19262 /* 53104 */ GIR_RootConstrainSelectedInstOperands,
19263 /* 53105 */ // GIR_Coverage, 923,
19264 /* 53105 */ GIR_EraseRootFromParent_Done,
19265 /* 53106 */ // Label 1550: @53106
19266 /* 53106 */ GIM_Reject,
19267 /* 53107 */ // Label 1544: @53107
19268 /* 53107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1551*/ GIMT_Encode4(53152), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 918 //
19269 /* 53114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19270 /* 53117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19271 /* 53120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19272 /* 53124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19273 /* 53128 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19274 /* 53132 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4024:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19275 /* 53132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16),
19276 /* 53135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19277 /* 53137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19278 /* 53139 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19279 /* 53141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19280 /* 53144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19281 /* 53150 */ GIR_RootConstrainSelectedInstOperands,
19282 /* 53151 */ // GIR_Coverage, 918,
19283 /* 53151 */ GIR_EraseRootFromParent_Done,
19284 /* 53152 */ // Label 1551: @53152
19285 /* 53152 */ GIM_Reject,
19286 /* 53153 */ // Label 1545: @53153
19287 /* 53153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1552*/ GIMT_Encode4(53198), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 920 //
19288 /* 53160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19289 /* 53163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19290 /* 53166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19291 /* 53170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19292 /* 53174 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19293 /* 53178 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4024:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19294 /* 53178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16),
19295 /* 53181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19296 /* 53183 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19297 /* 53185 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19298 /* 53187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19299 /* 53190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19300 /* 53196 */ GIR_RootConstrainSelectedInstOperands,
19301 /* 53197 */ // GIR_Coverage, 920,
19302 /* 53197 */ GIR_EraseRootFromParent_Done,
19303 /* 53198 */ // Label 1552: @53198
19304 /* 53198 */ GIM_Reject,
19305 /* 53199 */ // Label 1546: @53199
19306 /* 53199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1553*/ GIMT_Encode4(53244), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 919 //
19307 /* 53206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19308 /* 53209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19309 /* 53212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19310 /* 53216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19311 /* 53220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19312 /* 53224 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4024:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19313 /* 53224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32),
19314 /* 53227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19315 /* 53229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19316 /* 53231 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19317 /* 53233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19318 /* 53236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19319 /* 53242 */ GIR_RootConstrainSelectedInstOperands,
19320 /* 53243 */ // GIR_Coverage, 919,
19321 /* 53243 */ GIR_EraseRootFromParent_Done,
19322 /* 53244 */ // Label 1553: @53244
19323 /* 53244 */ GIM_Reject,
19324 /* 53245 */ // Label 1547: @53245
19325 /* 53245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1554*/ GIMT_Encode4(53290), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 921 //
19326 /* 53252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19327 /* 53255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19328 /* 53258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19329 /* 53262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19330 /* 53266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19331 /* 53270 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4024:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19332 /* 53270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32),
19333 /* 53273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19334 /* 53275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19335 /* 53277 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19336 /* 53279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19337 /* 53282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19338 /* 53288 */ GIR_RootConstrainSelectedInstOperands,
19339 /* 53289 */ // GIR_Coverage, 921,
19340 /* 53289 */ GIR_EraseRootFromParent_Done,
19341 /* 53290 */ // Label 1554: @53290
19342 /* 53290 */ GIM_Reject,
19343 /* 53291 */ // Label 1548: @53291
19344 /* 53291 */ GIM_Reject,
19345 /* 53292 */ // Label 1541: @53292
19346 /* 53292 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(53614),
19347 /* 53297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19348 /* 53302 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1562*/ GIMT_Encode4(53613),
19349 /* 53313 */ /*GILLT_v8s8*//*Label 1556*/ GIMT_Encode4(53337),
19350 /* 53317 */ /*GILLT_v16s8*//*Label 1557*/ GIMT_Encode4(53383),
19351 /* 53321 */ /*GILLT_v4s16*//*Label 1558*/ GIMT_Encode4(53429),
19352 /* 53325 */ /*GILLT_v8s16*//*Label 1559*/ GIMT_Encode4(53475),
19353 /* 53329 */ /*GILLT_v2s32*//*Label 1560*/ GIMT_Encode4(53521),
19354 /* 53333 */ /*GILLT_v4s32*//*Label 1561*/ GIMT_Encode4(53567),
19355 /* 53337 */ // Label 1556: @53337
19356 /* 53337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1563*/ GIMT_Encode4(53382), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 928 //
19357 /* 53344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19358 /* 53347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19359 /* 53350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19360 /* 53354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19361 /* 53358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19362 /* 53362 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4083:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19363 /* 53362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8),
19364 /* 53365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19365 /* 53367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19366 /* 53369 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19367 /* 53371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19368 /* 53374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19369 /* 53380 */ GIR_RootConstrainSelectedInstOperands,
19370 /* 53381 */ // GIR_Coverage, 928,
19371 /* 53381 */ GIR_EraseRootFromParent_Done,
19372 /* 53382 */ // Label 1563: @53382
19373 /* 53382 */ GIM_Reject,
19374 /* 53383 */ // Label 1557: @53383
19375 /* 53383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1564*/ GIMT_Encode4(53428), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 929 //
19376 /* 53390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19377 /* 53393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19378 /* 53396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19379 /* 53400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19380 /* 53404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19381 /* 53408 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4083:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19382 /* 53408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8),
19383 /* 53411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19384 /* 53413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19385 /* 53415 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19386 /* 53417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19387 /* 53420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19388 /* 53426 */ GIR_RootConstrainSelectedInstOperands,
19389 /* 53427 */ // GIR_Coverage, 929,
19390 /* 53427 */ GIR_EraseRootFromParent_Done,
19391 /* 53428 */ // Label 1564: @53428
19392 /* 53428 */ GIM_Reject,
19393 /* 53429 */ // Label 1558: @53429
19394 /* 53429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1565*/ GIMT_Encode4(53474), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 924 //
19395 /* 53436 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19396 /* 53439 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19397 /* 53442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19398 /* 53446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19399 /* 53450 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19400 /* 53454 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4083:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19401 /* 53454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16),
19402 /* 53457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19403 /* 53459 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19404 /* 53461 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19405 /* 53463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19406 /* 53466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19407 /* 53472 */ GIR_RootConstrainSelectedInstOperands,
19408 /* 53473 */ // GIR_Coverage, 924,
19409 /* 53473 */ GIR_EraseRootFromParent_Done,
19410 /* 53474 */ // Label 1565: @53474
19411 /* 53474 */ GIM_Reject,
19412 /* 53475 */ // Label 1559: @53475
19413 /* 53475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1566*/ GIMT_Encode4(53520), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 926 //
19414 /* 53482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19415 /* 53485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19416 /* 53488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19417 /* 53492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19418 /* 53496 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19419 /* 53500 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4083:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19420 /* 53500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16),
19421 /* 53503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19422 /* 53505 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19423 /* 53507 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19424 /* 53509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19425 /* 53512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19426 /* 53518 */ GIR_RootConstrainSelectedInstOperands,
19427 /* 53519 */ // GIR_Coverage, 926,
19428 /* 53519 */ GIR_EraseRootFromParent_Done,
19429 /* 53520 */ // Label 1566: @53520
19430 /* 53520 */ GIM_Reject,
19431 /* 53521 */ // Label 1560: @53521
19432 /* 53521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1567*/ GIMT_Encode4(53566), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 925 //
19433 /* 53528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19434 /* 53531 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19435 /* 53534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19436 /* 53538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19437 /* 53542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19438 /* 53546 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4083:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19439 /* 53546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32),
19440 /* 53549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19441 /* 53551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19442 /* 53553 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19443 /* 53555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19444 /* 53558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19445 /* 53564 */ GIR_RootConstrainSelectedInstOperands,
19446 /* 53565 */ // GIR_Coverage, 925,
19447 /* 53565 */ GIR_EraseRootFromParent_Done,
19448 /* 53566 */ // Label 1567: @53566
19449 /* 53566 */ GIM_Reject,
19450 /* 53567 */ // Label 1561: @53567
19451 /* 53567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1568*/ GIMT_Encode4(53612), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 927 //
19452 /* 53574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19453 /* 53577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19454 /* 53580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19455 /* 53584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19456 /* 53588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19457 /* 53592 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4083:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19458 /* 53592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32),
19459 /* 53595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19460 /* 53597 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19461 /* 53599 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19462 /* 53601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19463 /* 53604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19464 /* 53610 */ GIR_RootConstrainSelectedInstOperands,
19465 /* 53611 */ // GIR_Coverage, 927,
19466 /* 53611 */ GIR_EraseRootFromParent_Done,
19467 /* 53612 */ // Label 1568: @53612
19468 /* 53612 */ GIM_Reject,
19469 /* 53613 */ // Label 1562: @53613
19470 /* 53613 */ GIM_Reject,
19471 /* 53614 */ // Label 1555: @53614
19472 /* 53614 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(53936),
19473 /* 53619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19474 /* 53624 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1576*/ GIMT_Encode4(53935),
19475 /* 53635 */ /*GILLT_v8s8*//*Label 1570*/ GIMT_Encode4(53659),
19476 /* 53639 */ /*GILLT_v16s8*//*Label 1571*/ GIMT_Encode4(53705),
19477 /* 53643 */ /*GILLT_v4s16*//*Label 1572*/ GIMT_Encode4(53751),
19478 /* 53647 */ /*GILLT_v8s16*//*Label 1573*/ GIMT_Encode4(53797),
19479 /* 53651 */ /*GILLT_v2s32*//*Label 1574*/ GIMT_Encode4(53843),
19480 /* 53655 */ /*GILLT_v4s32*//*Label 1575*/ GIMT_Encode4(53889),
19481 /* 53659 */ // Label 1570: @53659
19482 /* 53659 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1577*/ GIMT_Encode4(53704), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 934 //
19483 /* 53666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19484 /* 53669 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19485 /* 53672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19486 /* 53676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19487 /* 53680 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19488 /* 53684 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4084:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19489 /* 53684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8),
19490 /* 53687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19491 /* 53689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19492 /* 53691 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19493 /* 53693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19494 /* 53696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19495 /* 53702 */ GIR_RootConstrainSelectedInstOperands,
19496 /* 53703 */ // GIR_Coverage, 934,
19497 /* 53703 */ GIR_EraseRootFromParent_Done,
19498 /* 53704 */ // Label 1577: @53704
19499 /* 53704 */ GIM_Reject,
19500 /* 53705 */ // Label 1571: @53705
19501 /* 53705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1578*/ GIMT_Encode4(53750), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 935 //
19502 /* 53712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19503 /* 53715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19504 /* 53718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19505 /* 53722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19506 /* 53726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19507 /* 53730 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4084:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19508 /* 53730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8),
19509 /* 53733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19510 /* 53735 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19511 /* 53737 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19512 /* 53739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19513 /* 53742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19514 /* 53748 */ GIR_RootConstrainSelectedInstOperands,
19515 /* 53749 */ // GIR_Coverage, 935,
19516 /* 53749 */ GIR_EraseRootFromParent_Done,
19517 /* 53750 */ // Label 1578: @53750
19518 /* 53750 */ GIM_Reject,
19519 /* 53751 */ // Label 1572: @53751
19520 /* 53751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1579*/ GIMT_Encode4(53796), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 930 //
19521 /* 53758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19522 /* 53761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19523 /* 53764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19524 /* 53768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19525 /* 53772 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19526 /* 53776 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4084:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19527 /* 53776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16),
19528 /* 53779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19529 /* 53781 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19530 /* 53783 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19531 /* 53785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19532 /* 53788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19533 /* 53794 */ GIR_RootConstrainSelectedInstOperands,
19534 /* 53795 */ // GIR_Coverage, 930,
19535 /* 53795 */ GIR_EraseRootFromParent_Done,
19536 /* 53796 */ // Label 1579: @53796
19537 /* 53796 */ GIM_Reject,
19538 /* 53797 */ // Label 1573: @53797
19539 /* 53797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1580*/ GIMT_Encode4(53842), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 932 //
19540 /* 53804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19541 /* 53807 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19542 /* 53810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19543 /* 53814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19544 /* 53818 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19545 /* 53822 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4084:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19546 /* 53822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16),
19547 /* 53825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19548 /* 53827 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19549 /* 53829 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19550 /* 53831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19551 /* 53834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19552 /* 53840 */ GIR_RootConstrainSelectedInstOperands,
19553 /* 53841 */ // GIR_Coverage, 932,
19554 /* 53841 */ GIR_EraseRootFromParent_Done,
19555 /* 53842 */ // Label 1580: @53842
19556 /* 53842 */ GIM_Reject,
19557 /* 53843 */ // Label 1574: @53843
19558 /* 53843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1581*/ GIMT_Encode4(53888), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 931 //
19559 /* 53850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19560 /* 53853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19561 /* 53856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19562 /* 53860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19563 /* 53864 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19564 /* 53868 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4084:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19565 /* 53868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32),
19566 /* 53871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19567 /* 53873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19568 /* 53875 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19569 /* 53877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19570 /* 53880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19571 /* 53886 */ GIR_RootConstrainSelectedInstOperands,
19572 /* 53887 */ // GIR_Coverage, 931,
19573 /* 53887 */ GIR_EraseRootFromParent_Done,
19574 /* 53888 */ // Label 1581: @53888
19575 /* 53888 */ GIM_Reject,
19576 /* 53889 */ // Label 1575: @53889
19577 /* 53889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1582*/ GIMT_Encode4(53934), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 933 //
19578 /* 53896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19579 /* 53899 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19580 /* 53902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19581 /* 53906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19582 /* 53910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19583 /* 53914 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4084:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19584 /* 53914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32),
19585 /* 53917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19586 /* 53919 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19587 /* 53921 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19588 /* 53923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19589 /* 53926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19590 /* 53932 */ GIR_RootConstrainSelectedInstOperands,
19591 /* 53933 */ // GIR_Coverage, 933,
19592 /* 53933 */ GIR_EraseRootFromParent_Done,
19593 /* 53934 */ // Label 1582: @53934
19594 /* 53934 */ GIM_Reject,
19595 /* 53935 */ // Label 1576: @53935
19596 /* 53935 */ GIM_Reject,
19597 /* 53936 */ // Label 1569: @53936
19598 /* 53936 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(54116),
19599 /* 53941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
19600 /* 53946 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1587*/ GIMT_Encode4(54115),
19601 /* 53957 */ /*GILLT_v8s8*//*Label 1584*/ GIMT_Encode4(53977), GIMT_Encode4(0),
19602 /* 53965 */ /*GILLT_v4s16*//*Label 1585*/ GIMT_Encode4(54023), GIMT_Encode4(0),
19603 /* 53973 */ /*GILLT_v2s32*//*Label 1586*/ GIMT_Encode4(54069),
19604 /* 53977 */ // Label 1584: @53977
19605 /* 53977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1588*/ GIMT_Encode4(54022), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 952 //
19606 /* 53984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19607 /* 53987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19608 /* 53990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19609 /* 53994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19610 /* 53998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19611 /* 54002 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4080:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19612 /* 54002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8),
19613 /* 54005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19614 /* 54007 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19615 /* 54009 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19616 /* 54011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19617 /* 54014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19618 /* 54020 */ GIR_RootConstrainSelectedInstOperands,
19619 /* 54021 */ // GIR_Coverage, 952,
19620 /* 54021 */ GIR_EraseRootFromParent_Done,
19621 /* 54022 */ // Label 1588: @54022
19622 /* 54022 */ GIM_Reject,
19623 /* 54023 */ // Label 1585: @54023
19624 /* 54023 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1589*/ GIMT_Encode4(54068), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 953 //
19625 /* 54030 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19626 /* 54033 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19627 /* 54036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19628 /* 54040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19629 /* 54044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19630 /* 54048 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4080:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19631 /* 54048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16),
19632 /* 54051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19633 /* 54053 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19634 /* 54055 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19635 /* 54057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19636 /* 54060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19637 /* 54066 */ GIR_RootConstrainSelectedInstOperands,
19638 /* 54067 */ // GIR_Coverage, 953,
19639 /* 54067 */ GIR_EraseRootFromParent_Done,
19640 /* 54068 */ // Label 1589: @54068
19641 /* 54068 */ GIM_Reject,
19642 /* 54069 */ // Label 1586: @54069
19643 /* 54069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1590*/ GIMT_Encode4(54114), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 954 //
19644 /* 54076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
19645 /* 54079 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
19646 /* 54082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19647 /* 54086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19648 /* 54090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19649 /* 54094 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4080:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
19650 /* 54094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32),
19651 /* 54097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19652 /* 54099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19653 /* 54101 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19654 /* 54103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19655 /* 54106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19656 /* 54112 */ GIR_RootConstrainSelectedInstOperands,
19657 /* 54113 */ // GIR_Coverage, 954,
19658 /* 54113 */ GIR_EraseRootFromParent_Done,
19659 /* 54114 */ // Label 1590: @54114
19660 /* 54114 */ GIM_Reject,
19661 /* 54115 */ // Label 1587: @54115
19662 /* 54115 */ GIM_Reject,
19663 /* 54116 */ // Label 1583: @54116
19664 /* 54116 */ GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(54238),
19665 /* 54121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
19666 /* 54126 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1594*/ GIMT_Encode4(54237),
19667 /* 54137 */ /*GILLT_v8s8*//*Label 1592*/ GIMT_Encode4(54145),
19668 /* 54141 */ /*GILLT_v16s8*//*Label 1593*/ GIMT_Encode4(54191),
19669 /* 54145 */ // Label 1592: @54145
19670 /* 54145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1595*/ GIMT_Encode4(54190), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 961 //
19671 /* 54152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19672 /* 54155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19673 /* 54158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19674 /* 54162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19675 /* 54166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19676 /* 54170 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4049:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19677 /* 54170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd),
19678 /* 54173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19679 /* 54175 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19680 /* 54177 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19681 /* 54179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19682 /* 54182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19683 /* 54188 */ GIR_RootConstrainSelectedInstOperands,
19684 /* 54189 */ // GIR_Coverage, 961,
19685 /* 54189 */ GIR_EraseRootFromParent_Done,
19686 /* 54190 */ // Label 1595: @54190
19687 /* 54190 */ GIM_Reject,
19688 /* 54191 */ // Label 1593: @54191
19689 /* 54191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1596*/ GIMT_Encode4(54236), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 962 //
19690 /* 54198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19691 /* 54201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19692 /* 54204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19693 /* 54208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19694 /* 54212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19695 /* 54216 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4049:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19696 /* 54216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq),
19697 /* 54219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19698 /* 54221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19699 /* 54223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19700 /* 54225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19701 /* 54228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19702 /* 54234 */ GIR_RootConstrainSelectedInstOperands,
19703 /* 54235 */ // GIR_Coverage, 962,
19704 /* 54235 */ GIR_EraseRootFromParent_Done,
19705 /* 54236 */ // Label 1596: @54236
19706 /* 54236 */ GIM_Reject,
19707 /* 54237 */ // Label 1594: @54237
19708 /* 54237 */ GIM_Reject,
19709 /* 54238 */ // Label 1591: @54238
19710 /* 54238 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(54460),
19711 /* 54243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
19712 /* 54248 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1602*/ GIMT_Encode4(54459),
19713 /* 54259 */ /*GILLT_v4s16*//*Label 1598*/ GIMT_Encode4(54275),
19714 /* 54263 */ /*GILLT_v8s16*//*Label 1599*/ GIMT_Encode4(54321),
19715 /* 54267 */ /*GILLT_v2s32*//*Label 1600*/ GIMT_Encode4(54367),
19716 /* 54271 */ /*GILLT_v4s32*//*Label 1601*/ GIMT_Encode4(54413),
19717 /* 54275 */ // Label 1598: @54275
19718 /* 54275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1603*/ GIMT_Encode4(54320), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 975 //
19719 /* 54282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19720 /* 54285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19721 /* 54288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19722 /* 54292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19723 /* 54296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19724 /* 54300 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4060:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19725 /* 54300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16),
19726 /* 54303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19727 /* 54305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19728 /* 54307 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19729 /* 54309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19730 /* 54312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19731 /* 54318 */ GIR_RootConstrainSelectedInstOperands,
19732 /* 54319 */ // GIR_Coverage, 975,
19733 /* 54319 */ GIR_EraseRootFromParent_Done,
19734 /* 54320 */ // Label 1603: @54320
19735 /* 54320 */ GIM_Reject,
19736 /* 54321 */ // Label 1599: @54321
19737 /* 54321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1604*/ GIMT_Encode4(54366), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 977 //
19738 /* 54328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19739 /* 54331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19740 /* 54334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19741 /* 54338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19742 /* 54342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19743 /* 54346 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4060:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19744 /* 54346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16),
19745 /* 54349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19746 /* 54351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19747 /* 54353 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19748 /* 54355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19749 /* 54358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19750 /* 54364 */ GIR_RootConstrainSelectedInstOperands,
19751 /* 54365 */ // GIR_Coverage, 977,
19752 /* 54365 */ GIR_EraseRootFromParent_Done,
19753 /* 54366 */ // Label 1604: @54366
19754 /* 54366 */ GIM_Reject,
19755 /* 54367 */ // Label 1600: @54367
19756 /* 54367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1605*/ GIMT_Encode4(54412), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 976 //
19757 /* 54374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19758 /* 54377 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19759 /* 54380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19760 /* 54384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19761 /* 54388 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19762 /* 54392 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4060:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19763 /* 54392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32),
19764 /* 54395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19765 /* 54397 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19766 /* 54399 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19767 /* 54401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19768 /* 54404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19769 /* 54410 */ GIR_RootConstrainSelectedInstOperands,
19770 /* 54411 */ // GIR_Coverage, 976,
19771 /* 54411 */ GIR_EraseRootFromParent_Done,
19772 /* 54412 */ // Label 1605: @54412
19773 /* 54412 */ GIM_Reject,
19774 /* 54413 */ // Label 1601: @54413
19775 /* 54413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1606*/ GIMT_Encode4(54458), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 978 //
19776 /* 54420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19777 /* 54423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19778 /* 54426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19779 /* 54430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19780 /* 54434 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19781 /* 54438 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4060:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19782 /* 54438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32),
19783 /* 54441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19784 /* 54443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19785 /* 54445 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19786 /* 54447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19787 /* 54450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19788 /* 54456 */ GIR_RootConstrainSelectedInstOperands,
19789 /* 54457 */ // GIR_Coverage, 978,
19790 /* 54457 */ GIR_EraseRootFromParent_Done,
19791 /* 54458 */ // Label 1606: @54458
19792 /* 54458 */ GIM_Reject,
19793 /* 54459 */ // Label 1602: @54459
19794 /* 54459 */ GIM_Reject,
19795 /* 54460 */ // Label 1597: @54460
19796 /* 54460 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(54682),
19797 /* 54465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
19798 /* 54470 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1612*/ GIMT_Encode4(54681),
19799 /* 54481 */ /*GILLT_v4s16*//*Label 1608*/ GIMT_Encode4(54497),
19800 /* 54485 */ /*GILLT_v8s16*//*Label 1609*/ GIMT_Encode4(54543),
19801 /* 54489 */ /*GILLT_v2s32*//*Label 1610*/ GIMT_Encode4(54589),
19802 /* 54493 */ /*GILLT_v4s32*//*Label 1611*/ GIMT_Encode4(54635),
19803 /* 54497 */ // Label 1608: @54497
19804 /* 54497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1613*/ GIMT_Encode4(54542), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 983 //
19805 /* 54504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19806 /* 54507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19807 /* 54510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19808 /* 54514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19809 /* 54518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19810 /* 54522 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4068:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19811 /* 54522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16),
19812 /* 54525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19813 /* 54527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19814 /* 54529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19815 /* 54531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19816 /* 54534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19817 /* 54540 */ GIR_RootConstrainSelectedInstOperands,
19818 /* 54541 */ // GIR_Coverage, 983,
19819 /* 54541 */ GIR_EraseRootFromParent_Done,
19820 /* 54542 */ // Label 1613: @54542
19821 /* 54542 */ GIM_Reject,
19822 /* 54543 */ // Label 1609: @54543
19823 /* 54543 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1614*/ GIMT_Encode4(54588), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 985 //
19824 /* 54550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19825 /* 54553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19826 /* 54556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19827 /* 54560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19828 /* 54564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19829 /* 54568 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4068:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19830 /* 54568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16),
19831 /* 54571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19832 /* 54573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19833 /* 54575 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19834 /* 54577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19835 /* 54580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19836 /* 54586 */ GIR_RootConstrainSelectedInstOperands,
19837 /* 54587 */ // GIR_Coverage, 985,
19838 /* 54587 */ GIR_EraseRootFromParent_Done,
19839 /* 54588 */ // Label 1614: @54588
19840 /* 54588 */ GIM_Reject,
19841 /* 54589 */ // Label 1610: @54589
19842 /* 54589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1615*/ GIMT_Encode4(54634), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 984 //
19843 /* 54596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19844 /* 54599 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19845 /* 54602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19846 /* 54606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19847 /* 54610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19848 /* 54614 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4068:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19849 /* 54614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32),
19850 /* 54617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19851 /* 54619 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19852 /* 54621 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19853 /* 54623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19854 /* 54626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19855 /* 54632 */ GIR_RootConstrainSelectedInstOperands,
19856 /* 54633 */ // GIR_Coverage, 984,
19857 /* 54633 */ GIR_EraseRootFromParent_Done,
19858 /* 54634 */ // Label 1615: @54634
19859 /* 54634 */ GIM_Reject,
19860 /* 54635 */ // Label 1611: @54635
19861 /* 54635 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1616*/ GIMT_Encode4(54680), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 986 //
19862 /* 54642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19863 /* 54645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19864 /* 54648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19865 /* 54652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19866 /* 54656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19867 /* 54660 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4068:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19868 /* 54660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32),
19869 /* 54663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19870 /* 54665 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19871 /* 54667 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19872 /* 54669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19873 /* 54672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19874 /* 54678 */ GIR_RootConstrainSelectedInstOperands,
19875 /* 54679 */ // GIR_Coverage, 986,
19876 /* 54679 */ GIR_EraseRootFromParent_Done,
19877 /* 54680 */ // Label 1616: @54680
19878 /* 54680 */ GIM_Reject,
19879 /* 54681 */ // Label 1612: @54681
19880 /* 54681 */ GIM_Reject,
19881 /* 54682 */ // Label 1607: @54682
19882 /* 54682 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(54803),
19883 /* 54687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
19884 /* 54692 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 1620*/ GIMT_Encode4(54802),
19885 /* 54703 */ /*GILLT_v8s16*//*Label 1618*/ GIMT_Encode4(54719), GIMT_Encode4(0), GIMT_Encode4(0),
19886 /* 54715 */ /*GILLT_v2s64*//*Label 1619*/ GIMT_Encode4(54765),
19887 /* 54719 */ // Label 1618: @54719
19888 /* 54719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1621*/ GIMT_Encode4(54764), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 997 //
19889 /* 54726 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19890 /* 54729 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19891 /* 54732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19892 /* 54736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19893 /* 54740 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19894 /* 54744 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4046:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19895 /* 54744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8),
19896 /* 54747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19897 /* 54749 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19898 /* 54751 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19899 /* 54753 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19900 /* 54756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19901 /* 54762 */ GIR_RootConstrainSelectedInstOperands,
19902 /* 54763 */ // GIR_Coverage, 997,
19903 /* 54763 */ GIR_EraseRootFromParent_Done,
19904 /* 54764 */ // Label 1621: @54764
19905 /* 54764 */ GIM_Reject,
19906 /* 54765 */ // Label 1619: @54765
19907 /* 54765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1622*/ GIMT_Encode4(54801), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 998 //
19908 /* 54772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
19909 /* 54775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19910 /* 54778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19911 /* 54782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19912 /* 54786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19913 /* 54790 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4046:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
19914 /* 54790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64),
19915 /* 54793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19916 /* 54795 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19917 /* 54797 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19918 /* 54799 */ GIR_RootConstrainSelectedInstOperands,
19919 /* 54800 */ // GIR_Coverage, 998,
19920 /* 54800 */ GIR_EraseRootFromParent_Done,
19921 /* 54801 */ // Label 1622: @54801
19922 /* 54801 */ GIM_Reject,
19923 /* 54802 */ // Label 1620: @54802
19924 /* 54802 */ GIM_Reject,
19925 /* 54803 */ // Label 1617: @54803
19926 /* 54803 */ GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(54925),
19927 /* 54808 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
19928 /* 54813 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 1626*/ GIMT_Encode4(54924),
19929 /* 54824 */ /*GILLT_v4s32*//*Label 1624*/ GIMT_Encode4(54832),
19930 /* 54828 */ /*GILLT_v2s64*//*Label 1625*/ GIMT_Encode4(54878),
19931 /* 54832 */ // Label 1624: @54832
19932 /* 54832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1627*/ GIMT_Encode4(54877), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1003 //
19933 /* 54839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19934 /* 54842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19935 /* 54845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19936 /* 54849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19937 /* 54853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19938 /* 54857 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19939 /* 54857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32),
19940 /* 54860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19941 /* 54862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19942 /* 54864 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19943 /* 54866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19944 /* 54869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19945 /* 54875 */ GIR_RootConstrainSelectedInstOperands,
19946 /* 54876 */ // GIR_Coverage, 1003,
19947 /* 54876 */ GIR_EraseRootFromParent_Done,
19948 /* 54877 */ // Label 1627: @54877
19949 /* 54877 */ GIM_Reject,
19950 /* 54878 */ // Label 1625: @54878
19951 /* 54878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1628*/ GIMT_Encode4(54923), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1004 //
19952 /* 54885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19953 /* 54888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19954 /* 54891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19955 /* 54895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19956 /* 54899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19957 /* 54903 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19958 /* 54903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64),
19959 /* 54906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19960 /* 54908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19961 /* 54910 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19962 /* 54912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19963 /* 54915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19964 /* 54921 */ GIR_RootConstrainSelectedInstOperands,
19965 /* 54922 */ // GIR_Coverage, 1004,
19966 /* 54922 */ GIR_EraseRootFromParent_Done,
19967 /* 54923 */ // Label 1628: @54923
19968 /* 54923 */ GIM_Reject,
19969 /* 54924 */ // Label 1626: @54924
19970 /* 54924 */ GIM_Reject,
19971 /* 54925 */ // Label 1623: @54925
19972 /* 54925 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(55247),
19973 /* 54930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
19974 /* 54935 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1636*/ GIMT_Encode4(55246),
19975 /* 54946 */ /*GILLT_v8s8*//*Label 1630*/ GIMT_Encode4(54970),
19976 /* 54950 */ /*GILLT_v16s8*//*Label 1631*/ GIMT_Encode4(55016),
19977 /* 54954 */ /*GILLT_v4s16*//*Label 1632*/ GIMT_Encode4(55062),
19978 /* 54958 */ /*GILLT_v8s16*//*Label 1633*/ GIMT_Encode4(55108),
19979 /* 54962 */ /*GILLT_v2s32*//*Label 1634*/ GIMT_Encode4(55154),
19980 /* 54966 */ /*GILLT_v4s32*//*Label 1635*/ GIMT_Encode4(55200),
19981 /* 54970 */ // Label 1630: @54970
19982 /* 54970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1637*/ GIMT_Encode4(55015), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1162 //
19983 /* 54977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19984 /* 54980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19985 /* 54983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19986 /* 54987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19987 /* 54991 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19988 /* 54995 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4025:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19989 /* 54995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8),
19990 /* 54998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19991 /* 55000 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19992 /* 55002 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19993 /* 55004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19994 /* 55007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19995 /* 55013 */ GIR_RootConstrainSelectedInstOperands,
19996 /* 55014 */ // GIR_Coverage, 1162,
19997 /* 55014 */ GIR_EraseRootFromParent_Done,
19998 /* 55015 */ // Label 1637: @55015
19999 /* 55015 */ GIM_Reject,
20000 /* 55016 */ // Label 1631: @55016
20001 /* 55016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1638*/ GIMT_Encode4(55061), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1163 //
20002 /* 55023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20003 /* 55026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20004 /* 55029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20005 /* 55033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20006 /* 55037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20007 /* 55041 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4025:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20008 /* 55041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8),
20009 /* 55044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20010 /* 55046 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20011 /* 55048 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20012 /* 55050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20013 /* 55053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20014 /* 55059 */ GIR_RootConstrainSelectedInstOperands,
20015 /* 55060 */ // GIR_Coverage, 1163,
20016 /* 55060 */ GIR_EraseRootFromParent_Done,
20017 /* 55061 */ // Label 1638: @55061
20018 /* 55061 */ GIM_Reject,
20019 /* 55062 */ // Label 1632: @55062
20020 /* 55062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1639*/ GIMT_Encode4(55107), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1158 //
20021 /* 55069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20022 /* 55072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20023 /* 55075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20024 /* 55079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20025 /* 55083 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20026 /* 55087 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4025:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20027 /* 55087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16),
20028 /* 55090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20029 /* 55092 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20030 /* 55094 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20031 /* 55096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20032 /* 55099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20033 /* 55105 */ GIR_RootConstrainSelectedInstOperands,
20034 /* 55106 */ // GIR_Coverage, 1158,
20035 /* 55106 */ GIR_EraseRootFromParent_Done,
20036 /* 55107 */ // Label 1639: @55107
20037 /* 55107 */ GIM_Reject,
20038 /* 55108 */ // Label 1633: @55108
20039 /* 55108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1640*/ GIMT_Encode4(55153), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1160 //
20040 /* 55115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20041 /* 55118 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20042 /* 55121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20043 /* 55125 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20044 /* 55129 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20045 /* 55133 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4025:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20046 /* 55133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16),
20047 /* 55136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20048 /* 55138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20049 /* 55140 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20050 /* 55142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20051 /* 55145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20052 /* 55151 */ GIR_RootConstrainSelectedInstOperands,
20053 /* 55152 */ // GIR_Coverage, 1160,
20054 /* 55152 */ GIR_EraseRootFromParent_Done,
20055 /* 55153 */ // Label 1640: @55153
20056 /* 55153 */ GIM_Reject,
20057 /* 55154 */ // Label 1634: @55154
20058 /* 55154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1641*/ GIMT_Encode4(55199), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1159 //
20059 /* 55161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20060 /* 55164 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20061 /* 55167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20062 /* 55171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20063 /* 55175 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20064 /* 55179 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4025:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20065 /* 55179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32),
20066 /* 55182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20067 /* 55184 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20068 /* 55186 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20069 /* 55188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20070 /* 55191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20071 /* 55197 */ GIR_RootConstrainSelectedInstOperands,
20072 /* 55198 */ // GIR_Coverage, 1159,
20073 /* 55198 */ GIR_EraseRootFromParent_Done,
20074 /* 55199 */ // Label 1641: @55199
20075 /* 55199 */ GIM_Reject,
20076 /* 55200 */ // Label 1635: @55200
20077 /* 55200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1642*/ GIMT_Encode4(55245), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1161 //
20078 /* 55207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20079 /* 55210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20080 /* 55213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20081 /* 55217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20082 /* 55221 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20083 /* 55225 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4025:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20084 /* 55225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32),
20085 /* 55228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20086 /* 55230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20087 /* 55232 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20088 /* 55234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20089 /* 55237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20090 /* 55243 */ GIR_RootConstrainSelectedInstOperands,
20091 /* 55244 */ // GIR_Coverage, 1161,
20092 /* 55244 */ GIR_EraseRootFromParent_Done,
20093 /* 55245 */ // Label 1642: @55245
20094 /* 55245 */ GIM_Reject,
20095 /* 55246 */ // Label 1636: @55246
20096 /* 55246 */ GIM_Reject,
20097 /* 55247 */ // Label 1629: @55247
20098 /* 55247 */ GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(55569),
20099 /* 55252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20100 /* 55257 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1650*/ GIMT_Encode4(55568),
20101 /* 55268 */ /*GILLT_v8s8*//*Label 1644*/ GIMT_Encode4(55292),
20102 /* 55272 */ /*GILLT_v16s8*//*Label 1645*/ GIMT_Encode4(55338),
20103 /* 55276 */ /*GILLT_v4s16*//*Label 1646*/ GIMT_Encode4(55384),
20104 /* 55280 */ /*GILLT_v8s16*//*Label 1647*/ GIMT_Encode4(55430),
20105 /* 55284 */ /*GILLT_v2s32*//*Label 1648*/ GIMT_Encode4(55476),
20106 /* 55288 */ /*GILLT_v4s32*//*Label 1649*/ GIMT_Encode4(55522),
20107 /* 55292 */ // Label 1644: @55292
20108 /* 55292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1651*/ GIMT_Encode4(55337), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1168 //
20109 /* 55299 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20110 /* 55302 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20111 /* 55305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20112 /* 55309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20113 /* 55313 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20114 /* 55317 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4026:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20115 /* 55317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8),
20116 /* 55320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20117 /* 55322 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20118 /* 55324 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20119 /* 55326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20120 /* 55329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20121 /* 55335 */ GIR_RootConstrainSelectedInstOperands,
20122 /* 55336 */ // GIR_Coverage, 1168,
20123 /* 55336 */ GIR_EraseRootFromParent_Done,
20124 /* 55337 */ // Label 1651: @55337
20125 /* 55337 */ GIM_Reject,
20126 /* 55338 */ // Label 1645: @55338
20127 /* 55338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1652*/ GIMT_Encode4(55383), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1169 //
20128 /* 55345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20129 /* 55348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20130 /* 55351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20131 /* 55355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20132 /* 55359 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20133 /* 55363 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4026:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20134 /* 55363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8),
20135 /* 55366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20136 /* 55368 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20137 /* 55370 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20138 /* 55372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20139 /* 55375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20140 /* 55381 */ GIR_RootConstrainSelectedInstOperands,
20141 /* 55382 */ // GIR_Coverage, 1169,
20142 /* 55382 */ GIR_EraseRootFromParent_Done,
20143 /* 55383 */ // Label 1652: @55383
20144 /* 55383 */ GIM_Reject,
20145 /* 55384 */ // Label 1646: @55384
20146 /* 55384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1653*/ GIMT_Encode4(55429), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1164 //
20147 /* 55391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20148 /* 55394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20149 /* 55397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20150 /* 55401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20151 /* 55405 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20152 /* 55409 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4026:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20153 /* 55409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16),
20154 /* 55412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20155 /* 55414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20156 /* 55416 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20157 /* 55418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20158 /* 55421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20159 /* 55427 */ GIR_RootConstrainSelectedInstOperands,
20160 /* 55428 */ // GIR_Coverage, 1164,
20161 /* 55428 */ GIR_EraseRootFromParent_Done,
20162 /* 55429 */ // Label 1653: @55429
20163 /* 55429 */ GIM_Reject,
20164 /* 55430 */ // Label 1647: @55430
20165 /* 55430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1654*/ GIMT_Encode4(55475), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1166 //
20166 /* 55437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20167 /* 55440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20168 /* 55443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20169 /* 55447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20170 /* 55451 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20171 /* 55455 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4026:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20172 /* 55455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16),
20173 /* 55458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20174 /* 55460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20175 /* 55462 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20176 /* 55464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20177 /* 55467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20178 /* 55473 */ GIR_RootConstrainSelectedInstOperands,
20179 /* 55474 */ // GIR_Coverage, 1166,
20180 /* 55474 */ GIR_EraseRootFromParent_Done,
20181 /* 55475 */ // Label 1654: @55475
20182 /* 55475 */ GIM_Reject,
20183 /* 55476 */ // Label 1648: @55476
20184 /* 55476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1655*/ GIMT_Encode4(55521), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1165 //
20185 /* 55483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20186 /* 55486 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20187 /* 55489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20188 /* 55493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20189 /* 55497 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20190 /* 55501 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4026:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20191 /* 55501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32),
20192 /* 55504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20193 /* 55506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20194 /* 55508 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20195 /* 55510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20196 /* 55513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20197 /* 55519 */ GIR_RootConstrainSelectedInstOperands,
20198 /* 55520 */ // GIR_Coverage, 1165,
20199 /* 55520 */ GIR_EraseRootFromParent_Done,
20200 /* 55521 */ // Label 1655: @55521
20201 /* 55521 */ GIM_Reject,
20202 /* 55522 */ // Label 1649: @55522
20203 /* 55522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1656*/ GIMT_Encode4(55567), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1167 //
20204 /* 55529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20205 /* 55532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20206 /* 55535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20207 /* 55539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20208 /* 55543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20209 /* 55547 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4026:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20210 /* 55547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32),
20211 /* 55550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20212 /* 55552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20213 /* 55554 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20214 /* 55556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20215 /* 55559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20216 /* 55565 */ GIR_RootConstrainSelectedInstOperands,
20217 /* 55566 */ // GIR_Coverage, 1167,
20218 /* 55566 */ GIR_EraseRootFromParent_Done,
20219 /* 55567 */ // Label 1656: @55567
20220 /* 55567 */ GIM_Reject,
20221 /* 55568 */ // Label 1650: @55568
20222 /* 55568 */ GIM_Reject,
20223 /* 55569 */ // Label 1643: @55569
20224 /* 55569 */ GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(55749),
20225 /* 55574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
20226 /* 55579 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1661*/ GIMT_Encode4(55748),
20227 /* 55590 */ /*GILLT_v8s8*//*Label 1658*/ GIMT_Encode4(55610), GIMT_Encode4(0),
20228 /* 55598 */ /*GILLT_v4s16*//*Label 1659*/ GIMT_Encode4(55656), GIMT_Encode4(0),
20229 /* 55606 */ /*GILLT_v2s32*//*Label 1660*/ GIMT_Encode4(55702),
20230 /* 55610 */ // Label 1658: @55610
20231 /* 55610 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1662*/ GIMT_Encode4(55655), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1186 //
20232 /* 55617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20233 /* 55620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20234 /* 55623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20235 /* 55627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20236 /* 55631 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20237 /* 55635 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4090:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20238 /* 55635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8),
20239 /* 55638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20240 /* 55640 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20241 /* 55642 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20242 /* 55644 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20243 /* 55647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20244 /* 55653 */ GIR_RootConstrainSelectedInstOperands,
20245 /* 55654 */ // GIR_Coverage, 1186,
20246 /* 55654 */ GIR_EraseRootFromParent_Done,
20247 /* 55655 */ // Label 1662: @55655
20248 /* 55655 */ GIM_Reject,
20249 /* 55656 */ // Label 1659: @55656
20250 /* 55656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1663*/ GIMT_Encode4(55701), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1187 //
20251 /* 55663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20252 /* 55666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20253 /* 55669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20254 /* 55673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20255 /* 55677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20256 /* 55681 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4090:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20257 /* 55681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16),
20258 /* 55684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20259 /* 55686 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20260 /* 55688 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20261 /* 55690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20262 /* 55693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20263 /* 55699 */ GIR_RootConstrainSelectedInstOperands,
20264 /* 55700 */ // GIR_Coverage, 1187,
20265 /* 55700 */ GIR_EraseRootFromParent_Done,
20266 /* 55701 */ // Label 1663: @55701
20267 /* 55701 */ GIM_Reject,
20268 /* 55702 */ // Label 1660: @55702
20269 /* 55702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1664*/ GIMT_Encode4(55747), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1188 //
20270 /* 55709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20271 /* 55712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
20272 /* 55715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20273 /* 55719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20274 /* 55723 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20275 /* 55727 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4090:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
20276 /* 55727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32),
20277 /* 55730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20278 /* 55732 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20279 /* 55734 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20280 /* 55736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20281 /* 55739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20282 /* 55745 */ GIR_RootConstrainSelectedInstOperands,
20283 /* 55746 */ // GIR_Coverage, 1188,
20284 /* 55746 */ GIR_EraseRootFromParent_Done,
20285 /* 55747 */ // Label 1664: @55747
20286 /* 55747 */ GIM_Reject,
20287 /* 55748 */ // Label 1661: @55748
20288 /* 55748 */ GIM_Reject,
20289 /* 55749 */ // Label 1657: @55749
20290 /* 55749 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(55971),
20291 /* 55754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
20292 /* 55759 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1670*/ GIMT_Encode4(55970),
20293 /* 55770 */ /*GILLT_v4s16*//*Label 1666*/ GIMT_Encode4(55786),
20294 /* 55774 */ /*GILLT_v8s16*//*Label 1667*/ GIMT_Encode4(55832),
20295 /* 55778 */ /*GILLT_v2s32*//*Label 1668*/ GIMT_Encode4(55878),
20296 /* 55782 */ /*GILLT_v4s32*//*Label 1669*/ GIMT_Encode4(55924),
20297 /* 55786 */ // Label 1666: @55786
20298 /* 55786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1671*/ GIMT_Encode4(55831), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1283 //
20299 /* 55793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20300 /* 55796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20301 /* 55799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20302 /* 55803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20303 /* 55807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20304 /* 55811 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4001:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20305 /* 55811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd),
20306 /* 55814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20307 /* 55816 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20308 /* 55818 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20309 /* 55820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20310 /* 55823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20311 /* 55829 */ GIR_RootConstrainSelectedInstOperands,
20312 /* 55830 */ // GIR_Coverage, 1283,
20313 /* 55830 */ GIR_EraseRootFromParent_Done,
20314 /* 55831 */ // Label 1671: @55831
20315 /* 55831 */ GIM_Reject,
20316 /* 55832 */ // Label 1667: @55832
20317 /* 55832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1672*/ GIMT_Encode4(55877), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1284 //
20318 /* 55839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20319 /* 55842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20320 /* 55845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20321 /* 55849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20322 /* 55853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20323 /* 55857 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4001:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20324 /* 55857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq),
20325 /* 55860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20326 /* 55862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20327 /* 55864 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20328 /* 55866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20329 /* 55869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20330 /* 55875 */ GIR_RootConstrainSelectedInstOperands,
20331 /* 55876 */ // GIR_Coverage, 1284,
20332 /* 55876 */ GIR_EraseRootFromParent_Done,
20333 /* 55877 */ // Label 1672: @55877
20334 /* 55877 */ GIM_Reject,
20335 /* 55878 */ // Label 1668: @55878
20336 /* 55878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1673*/ GIMT_Encode4(55923), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1281 //
20337 /* 55885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20338 /* 55888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20339 /* 55891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20340 /* 55895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20341 /* 55899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20342 /* 55903 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4001:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20343 /* 55903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd),
20344 /* 55906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20345 /* 55908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20346 /* 55910 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20347 /* 55912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20348 /* 55915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20349 /* 55921 */ GIR_RootConstrainSelectedInstOperands,
20350 /* 55922 */ // GIR_Coverage, 1281,
20351 /* 55922 */ GIR_EraseRootFromParent_Done,
20352 /* 55923 */ // Label 1673: @55923
20353 /* 55923 */ GIM_Reject,
20354 /* 55924 */ // Label 1669: @55924
20355 /* 55924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1674*/ GIMT_Encode4(55969), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1282 //
20356 /* 55931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20357 /* 55934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20358 /* 55937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20359 /* 55941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20360 /* 55945 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20361 /* 55949 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4001:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20362 /* 55949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq),
20363 /* 55952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20364 /* 55954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20365 /* 55956 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20366 /* 55958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20367 /* 55961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20368 /* 55967 */ GIR_RootConstrainSelectedInstOperands,
20369 /* 55968 */ // GIR_Coverage, 1282,
20370 /* 55968 */ GIR_EraseRootFromParent_Done,
20371 /* 55969 */ // Label 1674: @55969
20372 /* 55969 */ GIM_Reject,
20373 /* 55970 */ // Label 1670: @55970
20374 /* 55970 */ GIM_Reject,
20375 /* 55971 */ // Label 1665: @55971
20376 /* 55971 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(56193),
20377 /* 55976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
20378 /* 55981 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1680*/ GIMT_Encode4(56192),
20379 /* 55992 */ /*GILLT_v4s16*//*Label 1676*/ GIMT_Encode4(56008),
20380 /* 55996 */ /*GILLT_v8s16*//*Label 1677*/ GIMT_Encode4(56054),
20381 /* 56000 */ /*GILLT_v2s32*//*Label 1678*/ GIMT_Encode4(56100),
20382 /* 56004 */ /*GILLT_v4s32*//*Label 1679*/ GIMT_Encode4(56146),
20383 /* 56008 */ // Label 1676: @56008
20384 /* 56008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1681*/ GIMT_Encode4(56053), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1287 //
20385 /* 56015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20386 /* 56018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20387 /* 56021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20388 /* 56025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20389 /* 56029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20390 /* 56033 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4002:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20391 /* 56033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd),
20392 /* 56036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20393 /* 56038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20394 /* 56040 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20395 /* 56042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20396 /* 56045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20397 /* 56051 */ GIR_RootConstrainSelectedInstOperands,
20398 /* 56052 */ // GIR_Coverage, 1287,
20399 /* 56052 */ GIR_EraseRootFromParent_Done,
20400 /* 56053 */ // Label 1681: @56053
20401 /* 56053 */ GIM_Reject,
20402 /* 56054 */ // Label 1677: @56054
20403 /* 56054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1682*/ GIMT_Encode4(56099), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1288 //
20404 /* 56061 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20405 /* 56064 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20406 /* 56067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20407 /* 56071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20408 /* 56075 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20409 /* 56079 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4002:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20410 /* 56079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq),
20411 /* 56082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20412 /* 56084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20413 /* 56086 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20414 /* 56088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20415 /* 56091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20416 /* 56097 */ GIR_RootConstrainSelectedInstOperands,
20417 /* 56098 */ // GIR_Coverage, 1288,
20418 /* 56098 */ GIR_EraseRootFromParent_Done,
20419 /* 56099 */ // Label 1682: @56099
20420 /* 56099 */ GIM_Reject,
20421 /* 56100 */ // Label 1678: @56100
20422 /* 56100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1683*/ GIMT_Encode4(56145), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1285 //
20423 /* 56107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20424 /* 56110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20425 /* 56113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20426 /* 56117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20427 /* 56121 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20428 /* 56125 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4002:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20429 /* 56125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd),
20430 /* 56128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20431 /* 56130 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20432 /* 56132 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20433 /* 56134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20434 /* 56137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20435 /* 56143 */ GIR_RootConstrainSelectedInstOperands,
20436 /* 56144 */ // GIR_Coverage, 1285,
20437 /* 56144 */ GIR_EraseRootFromParent_Done,
20438 /* 56145 */ // Label 1683: @56145
20439 /* 56145 */ GIM_Reject,
20440 /* 56146 */ // Label 1679: @56146
20441 /* 56146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1684*/ GIMT_Encode4(56191), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1286 //
20442 /* 56153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20443 /* 56156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20444 /* 56159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20445 /* 56163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20446 /* 56167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20447 /* 56171 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4002:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20448 /* 56171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq),
20449 /* 56174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20450 /* 56176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20451 /* 56178 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20452 /* 56180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20453 /* 56183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20454 /* 56189 */ GIR_RootConstrainSelectedInstOperands,
20455 /* 56190 */ // GIR_Coverage, 1286,
20456 /* 56190 */ GIR_EraseRootFromParent_Done,
20457 /* 56191 */ // Label 1684: @56191
20458 /* 56191 */ GIM_Reject,
20459 /* 56192 */ // Label 1680: @56192
20460 /* 56192 */ GIM_Reject,
20461 /* 56193 */ // Label 1675: @56193
20462 /* 56193 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(56415),
20463 /* 56198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20464 /* 56203 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1690*/ GIMT_Encode4(56414),
20465 /* 56214 */ /*GILLT_v4s16*//*Label 1686*/ GIMT_Encode4(56230),
20466 /* 56218 */ /*GILLT_v8s16*//*Label 1687*/ GIMT_Encode4(56276),
20467 /* 56222 */ /*GILLT_v2s32*//*Label 1688*/ GIMT_Encode4(56322),
20468 /* 56226 */ /*GILLT_v4s32*//*Label 1689*/ GIMT_Encode4(56368),
20469 /* 56230 */ // Label 1686: @56230
20470 /* 56230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1691*/ GIMT_Encode4(56275), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1333 //
20471 /* 56237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20472 /* 56240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20473 /* 56243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20474 /* 56247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20475 /* 56251 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20476 /* 56255 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3998:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20477 /* 56255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd),
20478 /* 56258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20479 /* 56260 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20480 /* 56262 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20481 /* 56264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20482 /* 56267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20483 /* 56273 */ GIR_RootConstrainSelectedInstOperands,
20484 /* 56274 */ // GIR_Coverage, 1333,
20485 /* 56274 */ GIR_EraseRootFromParent_Done,
20486 /* 56275 */ // Label 1691: @56275
20487 /* 56275 */ GIM_Reject,
20488 /* 56276 */ // Label 1687: @56276
20489 /* 56276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1692*/ GIMT_Encode4(56321), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1334 //
20490 /* 56283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20491 /* 56286 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20492 /* 56289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20493 /* 56293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20494 /* 56297 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20495 /* 56301 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3998:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20496 /* 56301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq),
20497 /* 56304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20498 /* 56306 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20499 /* 56308 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20500 /* 56310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20501 /* 56313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20502 /* 56319 */ GIR_RootConstrainSelectedInstOperands,
20503 /* 56320 */ // GIR_Coverage, 1334,
20504 /* 56320 */ GIR_EraseRootFromParent_Done,
20505 /* 56321 */ // Label 1692: @56321
20506 /* 56321 */ GIM_Reject,
20507 /* 56322 */ // Label 1688: @56322
20508 /* 56322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1693*/ GIMT_Encode4(56367), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1331 //
20509 /* 56329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20510 /* 56332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20511 /* 56335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20512 /* 56339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20513 /* 56343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20514 /* 56347 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3998:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20515 /* 56347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd),
20516 /* 56350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20517 /* 56352 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20518 /* 56354 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20519 /* 56356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20520 /* 56359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20521 /* 56365 */ GIR_RootConstrainSelectedInstOperands,
20522 /* 56366 */ // GIR_Coverage, 1331,
20523 /* 56366 */ GIR_EraseRootFromParent_Done,
20524 /* 56367 */ // Label 1693: @56367
20525 /* 56367 */ GIM_Reject,
20526 /* 56368 */ // Label 1689: @56368
20527 /* 56368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1694*/ GIMT_Encode4(56413), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1332 //
20528 /* 56375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20529 /* 56378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20530 /* 56381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20531 /* 56385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20532 /* 56389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20533 /* 56393 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3998:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20534 /* 56393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq),
20535 /* 56396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20536 /* 56398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20537 /* 56400 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20538 /* 56402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20539 /* 56405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20540 /* 56411 */ GIR_RootConstrainSelectedInstOperands,
20541 /* 56412 */ // GIR_Coverage, 1332,
20542 /* 56412 */ GIR_EraseRootFromParent_Done,
20543 /* 56413 */ // Label 1694: @56413
20544 /* 56413 */ GIM_Reject,
20545 /* 56414 */ // Label 1690: @56414
20546 /* 56414 */ GIM_Reject,
20547 /* 56415 */ // Label 1685: @56415
20548 /* 56415 */ GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(56661),
20549 /* 56420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
20550 /* 56425 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1699*/ GIMT_Encode4(56660),
20551 /* 56436 */ /*GILLT_v8s8*//*Label 1696*/ GIMT_Encode4(56456), GIMT_Encode4(0),
20552 /* 56444 */ /*GILLT_v4s16*//*Label 1697*/ GIMT_Encode4(56502), GIMT_Encode4(0),
20553 /* 56452 */ /*GILLT_v2s32*//*Label 1698*/ GIMT_Encode4(56581),
20554 /* 56456 */ // Label 1696: @56456
20555 /* 56456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1700*/ GIMT_Encode4(56501), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1399 //
20556 /* 56463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20557 /* 56466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20558 /* 56469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20559 /* 56473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20560 /* 56477 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20561 /* 56481 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4052:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20562 /* 56481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8),
20563 /* 56484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20564 /* 56486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20565 /* 56488 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20566 /* 56490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20567 /* 56493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20568 /* 56499 */ GIR_RootConstrainSelectedInstOperands,
20569 /* 56500 */ // GIR_Coverage, 1399,
20570 /* 56500 */ GIR_EraseRootFromParent_Done,
20571 /* 56501 */ // Label 1700: @56501
20572 /* 56501 */ GIM_Reject,
20573 /* 56502 */ // Label 1697: @56502
20574 /* 56502 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(56580),
20575 /* 56507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20576 /* 56510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20577 /* 56513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20578 /* 56517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20579 /* 56521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20580 /* 56525 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1702*/ GIMT_Encode4(56552), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1400 //
20581 /* 56532 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20582 /* 56532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16),
20583 /* 56535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20584 /* 56537 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20585 /* 56539 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20586 /* 56541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20587 /* 56544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20588 /* 56550 */ GIR_RootConstrainSelectedInstOperands,
20589 /* 56551 */ // GIR_Coverage, 1400,
20590 /* 56551 */ GIR_EraseRootFromParent_Done,
20591 /* 56552 */ // Label 1702: @56552
20592 /* 56552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1703*/ GIMT_Encode4(56579), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1403 //
20593 /* 56559 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4052:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20594 /* 56559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh),
20595 /* 56562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20596 /* 56564 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20597 /* 56566 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20598 /* 56568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20599 /* 56571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20600 /* 56577 */ GIR_RootConstrainSelectedInstOperands,
20601 /* 56578 */ // GIR_Coverage, 1403,
20602 /* 56578 */ GIR_EraseRootFromParent_Done,
20603 /* 56579 */ // Label 1703: @56579
20604 /* 56579 */ GIM_Reject,
20605 /* 56580 */ // Label 1701: @56580
20606 /* 56580 */ GIM_Reject,
20607 /* 56581 */ // Label 1698: @56581
20608 /* 56581 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(56659),
20609 /* 56586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20610 /* 56589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20611 /* 56592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20612 /* 56596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20613 /* 56600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20614 /* 56604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1705*/ GIMT_Encode4(56631), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1401 //
20615 /* 56611 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4052:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20616 /* 56611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32),
20617 /* 56614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20618 /* 56616 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20619 /* 56618 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20620 /* 56620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20621 /* 56623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20622 /* 56629 */ GIR_RootConstrainSelectedInstOperands,
20623 /* 56630 */ // GIR_Coverage, 1401,
20624 /* 56630 */ GIR_EraseRootFromParent_Done,
20625 /* 56631 */ // Label 1705: @56631
20626 /* 56631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1706*/ GIMT_Encode4(56658), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1402 //
20627 /* 56638 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4052:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20628 /* 56638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf),
20629 /* 56641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20630 /* 56643 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20631 /* 56645 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20632 /* 56647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20633 /* 56650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20634 /* 56656 */ GIR_RootConstrainSelectedInstOperands,
20635 /* 56657 */ // GIR_Coverage, 1402,
20636 /* 56657 */ GIR_EraseRootFromParent_Done,
20637 /* 56658 */ // Label 1706: @56658
20638 /* 56658 */ GIM_Reject,
20639 /* 56659 */ // Label 1704: @56659
20640 /* 56659 */ GIM_Reject,
20641 /* 56660 */ // Label 1699: @56660
20642 /* 56660 */ GIM_Reject,
20643 /* 56661 */ // Label 1695: @56661
20644 /* 56661 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(57007),
20645 /* 56666 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
20646 /* 56671 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1714*/ GIMT_Encode4(57006),
20647 /* 56682 */ /*GILLT_s64*//*Label 1708*/ GIMT_Encode4(56730), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
20648 /* 56710 */ /*GILLT_v4s16*//*Label 1709*/ GIMT_Encode4(56776),
20649 /* 56714 */ /*GILLT_v8s16*//*Label 1710*/ GIMT_Encode4(56822),
20650 /* 56718 */ /*GILLT_v2s32*//*Label 1711*/ GIMT_Encode4(56868),
20651 /* 56722 */ /*GILLT_v4s32*//*Label 1712*/ GIMT_Encode4(56914),
20652 /* 56726 */ /*GILLT_v2s64*//*Label 1713*/ GIMT_Encode4(56960),
20653 /* 56730 */ // Label 1708: @56730
20654 /* 56730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1715*/ GIMT_Encode4(56775), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1418 //
20655 /* 56737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20656 /* 56740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20657 /* 56743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20658 /* 56747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20659 /* 56751 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20660 /* 56755 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4050:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
20661 /* 56755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32),
20662 /* 56758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20663 /* 56760 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20664 /* 56762 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20665 /* 56764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20666 /* 56767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20667 /* 56773 */ GIR_RootConstrainSelectedInstOperands,
20668 /* 56774 */ // GIR_Coverage, 1418,
20669 /* 56774 */ GIR_EraseRootFromParent_Done,
20670 /* 56775 */ // Label 1715: @56775
20671 /* 56775 */ GIM_Reject,
20672 /* 56776 */ // Label 1709: @56776
20673 /* 56776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1716*/ GIMT_Encode4(56821), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1416 //
20674 /* 56783 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20675 /* 56786 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20676 /* 56789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20677 /* 56793 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20678 /* 56797 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20679 /* 56801 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4050:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20680 /* 56801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8),
20681 /* 56804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20682 /* 56806 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20683 /* 56808 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20684 /* 56810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20685 /* 56813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20686 /* 56819 */ GIR_RootConstrainSelectedInstOperands,
20687 /* 56820 */ // GIR_Coverage, 1416,
20688 /* 56820 */ GIR_EraseRootFromParent_Done,
20689 /* 56821 */ // Label 1716: @56821
20690 /* 56821 */ GIM_Reject,
20691 /* 56822 */ // Label 1710: @56822
20692 /* 56822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1717*/ GIMT_Encode4(56867), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1419 //
20693 /* 56829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20694 /* 56832 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20695 /* 56835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20696 /* 56839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20697 /* 56843 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20698 /* 56847 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4050:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
20699 /* 56847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8),
20700 /* 56850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20701 /* 56852 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20702 /* 56854 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20703 /* 56856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20704 /* 56859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20705 /* 56865 */ GIR_RootConstrainSelectedInstOperands,
20706 /* 56866 */ // GIR_Coverage, 1419,
20707 /* 56866 */ GIR_EraseRootFromParent_Done,
20708 /* 56867 */ // Label 1717: @56867
20709 /* 56867 */ GIM_Reject,
20710 /* 56868 */ // Label 1711: @56868
20711 /* 56868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1718*/ GIMT_Encode4(56913), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1417 //
20712 /* 56875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20713 /* 56878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20714 /* 56881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20715 /* 56885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20716 /* 56889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20717 /* 56893 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4050:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
20718 /* 56893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16),
20719 /* 56896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20720 /* 56898 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20721 /* 56900 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20722 /* 56902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20723 /* 56905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20724 /* 56911 */ GIR_RootConstrainSelectedInstOperands,
20725 /* 56912 */ // GIR_Coverage, 1417,
20726 /* 56912 */ GIR_EraseRootFromParent_Done,
20727 /* 56913 */ // Label 1718: @56913
20728 /* 56913 */ GIM_Reject,
20729 /* 56914 */ // Label 1712: @56914
20730 /* 56914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1719*/ GIMT_Encode4(56959), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1420 //
20731 /* 56921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20732 /* 56924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20733 /* 56927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20734 /* 56931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20735 /* 56935 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20736 /* 56939 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4050:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
20737 /* 56939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16),
20738 /* 56942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20739 /* 56944 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20740 /* 56946 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20741 /* 56948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20742 /* 56951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20743 /* 56957 */ GIR_RootConstrainSelectedInstOperands,
20744 /* 56958 */ // GIR_Coverage, 1420,
20745 /* 56958 */ GIR_EraseRootFromParent_Done,
20746 /* 56959 */ // Label 1719: @56959
20747 /* 56959 */ GIM_Reject,
20748 /* 56960 */ // Label 1713: @56960
20749 /* 56960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1720*/ GIMT_Encode4(57005), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1421 //
20750 /* 56967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20751 /* 56970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20752 /* 56973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20753 /* 56977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20754 /* 56981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20755 /* 56985 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4050:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
20756 /* 56985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32),
20757 /* 56988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20758 /* 56990 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20759 /* 56992 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20760 /* 56994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20761 /* 56997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20762 /* 57003 */ GIR_RootConstrainSelectedInstOperands,
20763 /* 57004 */ // GIR_Coverage, 1421,
20764 /* 57004 */ GIR_EraseRootFromParent_Done,
20765 /* 57005 */ // Label 1720: @57005
20766 /* 57005 */ GIM_Reject,
20767 /* 57006 */ // Label 1714: @57006
20768 /* 57006 */ GIM_Reject,
20769 /* 57007 */ // Label 1707: @57007
20770 /* 57007 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(57353),
20771 /* 57012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
20772 /* 57017 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1728*/ GIMT_Encode4(57352),
20773 /* 57028 */ /*GILLT_s64*//*Label 1722*/ GIMT_Encode4(57076), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
20774 /* 57056 */ /*GILLT_v4s16*//*Label 1723*/ GIMT_Encode4(57122),
20775 /* 57060 */ /*GILLT_v8s16*//*Label 1724*/ GIMT_Encode4(57168),
20776 /* 57064 */ /*GILLT_v2s32*//*Label 1725*/ GIMT_Encode4(57214),
20777 /* 57068 */ /*GILLT_v4s32*//*Label 1726*/ GIMT_Encode4(57260),
20778 /* 57072 */ /*GILLT_v2s64*//*Label 1727*/ GIMT_Encode4(57306),
20779 /* 57076 */ // Label 1722: @57076
20780 /* 57076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1729*/ GIMT_Encode4(57121), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1424 //
20781 /* 57083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20782 /* 57086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20783 /* 57089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20784 /* 57093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20785 /* 57097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20786 /* 57101 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4051:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
20787 /* 57101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32),
20788 /* 57104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20789 /* 57106 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20790 /* 57108 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20791 /* 57110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20792 /* 57113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20793 /* 57119 */ GIR_RootConstrainSelectedInstOperands,
20794 /* 57120 */ // GIR_Coverage, 1424,
20795 /* 57120 */ GIR_EraseRootFromParent_Done,
20796 /* 57121 */ // Label 1729: @57121
20797 /* 57121 */ GIM_Reject,
20798 /* 57122 */ // Label 1723: @57122
20799 /* 57122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1730*/ GIMT_Encode4(57167), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1422 //
20800 /* 57129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20801 /* 57132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20802 /* 57135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20803 /* 57139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20804 /* 57143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20805 /* 57147 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4051:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20806 /* 57147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8),
20807 /* 57150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20808 /* 57152 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20809 /* 57154 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20810 /* 57156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20811 /* 57159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20812 /* 57165 */ GIR_RootConstrainSelectedInstOperands,
20813 /* 57166 */ // GIR_Coverage, 1422,
20814 /* 57166 */ GIR_EraseRootFromParent_Done,
20815 /* 57167 */ // Label 1730: @57167
20816 /* 57167 */ GIM_Reject,
20817 /* 57168 */ // Label 1724: @57168
20818 /* 57168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1731*/ GIMT_Encode4(57213), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1425 //
20819 /* 57175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20820 /* 57178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20821 /* 57181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20822 /* 57185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20823 /* 57189 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20824 /* 57193 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4051:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
20825 /* 57193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8),
20826 /* 57196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20827 /* 57198 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20828 /* 57200 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20829 /* 57202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20830 /* 57205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20831 /* 57211 */ GIR_RootConstrainSelectedInstOperands,
20832 /* 57212 */ // GIR_Coverage, 1425,
20833 /* 57212 */ GIR_EraseRootFromParent_Done,
20834 /* 57213 */ // Label 1731: @57213
20835 /* 57213 */ GIM_Reject,
20836 /* 57214 */ // Label 1725: @57214
20837 /* 57214 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1732*/ GIMT_Encode4(57259), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1423 //
20838 /* 57221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20839 /* 57224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20840 /* 57227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20841 /* 57231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20842 /* 57235 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20843 /* 57239 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4051:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
20844 /* 57239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16),
20845 /* 57242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20846 /* 57244 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20847 /* 57246 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20848 /* 57248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20849 /* 57251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20850 /* 57257 */ GIR_RootConstrainSelectedInstOperands,
20851 /* 57258 */ // GIR_Coverage, 1423,
20852 /* 57258 */ GIR_EraseRootFromParent_Done,
20853 /* 57259 */ // Label 1732: @57259
20854 /* 57259 */ GIM_Reject,
20855 /* 57260 */ // Label 1726: @57260
20856 /* 57260 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1733*/ GIMT_Encode4(57305), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1426 //
20857 /* 57267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20858 /* 57270 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20859 /* 57273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20860 /* 57277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20861 /* 57281 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20862 /* 57285 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4051:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
20863 /* 57285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16),
20864 /* 57288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20865 /* 57290 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20866 /* 57292 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20867 /* 57294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20868 /* 57297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20869 /* 57303 */ GIR_RootConstrainSelectedInstOperands,
20870 /* 57304 */ // GIR_Coverage, 1426,
20871 /* 57304 */ GIR_EraseRootFromParent_Done,
20872 /* 57305 */ // Label 1733: @57305
20873 /* 57305 */ GIM_Reject,
20874 /* 57306 */ // Label 1727: @57306
20875 /* 57306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1734*/ GIMT_Encode4(57351), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1427 //
20876 /* 57313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20877 /* 57316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20878 /* 57319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20879 /* 57323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20880 /* 57327 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20881 /* 57331 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4051:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
20882 /* 57331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32),
20883 /* 57334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20884 /* 57336 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20885 /* 57338 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20886 /* 57340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20887 /* 57343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20888 /* 57349 */ GIR_RootConstrainSelectedInstOperands,
20889 /* 57350 */ // GIR_Coverage, 1427,
20890 /* 57350 */ GIR_EraseRootFromParent_Done,
20891 /* 57351 */ // Label 1734: @57351
20892 /* 57351 */ GIM_Reject,
20893 /* 57352 */ // Label 1728: @57352
20894 /* 57352 */ GIM_Reject,
20895 /* 57353 */ // Label 1721: @57353
20896 /* 57353 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(57533),
20897 /* 57358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
20898 /* 57363 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1739*/ GIMT_Encode4(57532),
20899 /* 57374 */ /*GILLT_v8s8*//*Label 1736*/ GIMT_Encode4(57394), GIMT_Encode4(0),
20900 /* 57382 */ /*GILLT_v4s16*//*Label 1737*/ GIMT_Encode4(57440), GIMT_Encode4(0),
20901 /* 57390 */ /*GILLT_v2s32*//*Label 1738*/ GIMT_Encode4(57486),
20902 /* 57394 */ // Label 1736: @57394
20903 /* 57394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1740*/ GIMT_Encode4(57439), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1428 //
20904 /* 57401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20905 /* 57404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20906 /* 57407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20907 /* 57411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20908 /* 57415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20909 /* 57419 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4055:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20910 /* 57419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8),
20911 /* 57422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20912 /* 57424 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20913 /* 57426 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20914 /* 57428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20915 /* 57431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20916 /* 57437 */ GIR_RootConstrainSelectedInstOperands,
20917 /* 57438 */ // GIR_Coverage, 1428,
20918 /* 57438 */ GIR_EraseRootFromParent_Done,
20919 /* 57439 */ // Label 1740: @57439
20920 /* 57439 */ GIM_Reject,
20921 /* 57440 */ // Label 1737: @57440
20922 /* 57440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1741*/ GIMT_Encode4(57485), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1429 //
20923 /* 57447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20924 /* 57450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20925 /* 57453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20926 /* 57457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20927 /* 57461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20928 /* 57465 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4055:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20929 /* 57465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16),
20930 /* 57468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20931 /* 57470 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20932 /* 57472 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20933 /* 57474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20934 /* 57477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20935 /* 57483 */ GIR_RootConstrainSelectedInstOperands,
20936 /* 57484 */ // GIR_Coverage, 1429,
20937 /* 57484 */ GIR_EraseRootFromParent_Done,
20938 /* 57485 */ // Label 1741: @57485
20939 /* 57485 */ GIM_Reject,
20940 /* 57486 */ // Label 1738: @57486
20941 /* 57486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1742*/ GIMT_Encode4(57531), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1430 //
20942 /* 57493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20943 /* 57496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20944 /* 57499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20945 /* 57503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20946 /* 57507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20947 /* 57511 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4055:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20948 /* 57511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32),
20949 /* 57514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20950 /* 57516 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20951 /* 57518 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20952 /* 57520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20953 /* 57523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20954 /* 57529 */ GIR_RootConstrainSelectedInstOperands,
20955 /* 57530 */ // GIR_Coverage, 1430,
20956 /* 57530 */ GIR_EraseRootFromParent_Done,
20957 /* 57531 */ // Label 1742: @57531
20958 /* 57531 */ GIM_Reject,
20959 /* 57532 */ // Label 1739: @57532
20960 /* 57532 */ GIM_Reject,
20961 /* 57533 */ // Label 1735: @57533
20962 /* 57533 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(57713),
20963 /* 57538 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
20964 /* 57543 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1747*/ GIMT_Encode4(57712),
20965 /* 57554 */ /*GILLT_v8s8*//*Label 1744*/ GIMT_Encode4(57574), GIMT_Encode4(0),
20966 /* 57562 */ /*GILLT_v4s16*//*Label 1745*/ GIMT_Encode4(57620), GIMT_Encode4(0),
20967 /* 57570 */ /*GILLT_v2s32*//*Label 1746*/ GIMT_Encode4(57666),
20968 /* 57574 */ // Label 1744: @57574
20969 /* 57574 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1748*/ GIMT_Encode4(57619), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1431 //
20970 /* 57581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20971 /* 57584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20972 /* 57587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20973 /* 57591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20974 /* 57595 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20975 /* 57599 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4056:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20976 /* 57599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8),
20977 /* 57602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20978 /* 57604 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20979 /* 57606 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20980 /* 57608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20981 /* 57611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20982 /* 57617 */ GIR_RootConstrainSelectedInstOperands,
20983 /* 57618 */ // GIR_Coverage, 1431,
20984 /* 57618 */ GIR_EraseRootFromParent_Done,
20985 /* 57619 */ // Label 1748: @57619
20986 /* 57619 */ GIM_Reject,
20987 /* 57620 */ // Label 1745: @57620
20988 /* 57620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1749*/ GIMT_Encode4(57665), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1432 //
20989 /* 57627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20990 /* 57630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20991 /* 57633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20992 /* 57637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20993 /* 57641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20994 /* 57645 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4056:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20995 /* 57645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16),
20996 /* 57648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20997 /* 57650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20998 /* 57652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20999 /* 57654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21000 /* 57657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21001 /* 57663 */ GIR_RootConstrainSelectedInstOperands,
21002 /* 57664 */ // GIR_Coverage, 1432,
21003 /* 57664 */ GIR_EraseRootFromParent_Done,
21004 /* 57665 */ // Label 1749: @57665
21005 /* 57665 */ GIM_Reject,
21006 /* 57666 */ // Label 1746: @57666
21007 /* 57666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1750*/ GIMT_Encode4(57711), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1433 //
21008 /* 57673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21009 /* 57676 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21010 /* 57679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21011 /* 57683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21012 /* 57687 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21013 /* 57691 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4056:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21014 /* 57691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32),
21015 /* 57694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21016 /* 57696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21017 /* 57698 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21018 /* 57700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21019 /* 57703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21020 /* 57709 */ GIR_RootConstrainSelectedInstOperands,
21021 /* 57710 */ // GIR_Coverage, 1433,
21022 /* 57710 */ GIR_EraseRootFromParent_Done,
21023 /* 57711 */ // Label 1750: @57711
21024 /* 57711 */ GIM_Reject,
21025 /* 57712 */ // Label 1747: @57712
21026 /* 57712 */ GIM_Reject,
21027 /* 57713 */ // Label 1743: @57713
21028 /* 57713 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(57839),
21029 /* 57718 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21030 /* 57723 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1754*/ GIMT_Encode4(57838),
21031 /* 57734 */ /*GILLT_v4s16*//*Label 1752*/ GIMT_Encode4(57746), GIMT_Encode4(0),
21032 /* 57742 */ /*GILLT_v2s32*//*Label 1753*/ GIMT_Encode4(57792),
21033 /* 57746 */ // Label 1752: @57746
21034 /* 57746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1755*/ GIMT_Encode4(57791), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1435 //
21035 /* 57753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21036 /* 57756 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21037 /* 57759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21038 /* 57763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21039 /* 57767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21040 /* 57771 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4055:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21041 /* 57771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh),
21042 /* 57774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21043 /* 57776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21044 /* 57778 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21045 /* 57780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21046 /* 57783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21047 /* 57789 */ GIR_RootConstrainSelectedInstOperands,
21048 /* 57790 */ // GIR_Coverage, 1435,
21049 /* 57790 */ GIR_EraseRootFromParent_Done,
21050 /* 57791 */ // Label 1755: @57791
21051 /* 57791 */ GIM_Reject,
21052 /* 57792 */ // Label 1753: @57792
21053 /* 57792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1756*/ GIMT_Encode4(57837), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1434 //
21054 /* 57799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21055 /* 57802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21056 /* 57805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21057 /* 57809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21058 /* 57813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21059 /* 57817 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4055:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21060 /* 57817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf),
21061 /* 57820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21062 /* 57822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21063 /* 57824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21064 /* 57826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21065 /* 57829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21066 /* 57835 */ GIR_RootConstrainSelectedInstOperands,
21067 /* 57836 */ // GIR_Coverage, 1434,
21068 /* 57836 */ GIR_EraseRootFromParent_Done,
21069 /* 57837 */ // Label 1756: @57837
21070 /* 57837 */ GIM_Reject,
21071 /* 57838 */ // Label 1754: @57838
21072 /* 57838 */ GIM_Reject,
21073 /* 57839 */ // Label 1751: @57839
21074 /* 57839 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(58019),
21075 /* 57844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21076 /* 57849 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1761*/ GIMT_Encode4(58018),
21077 /* 57860 */ /*GILLT_v8s8*//*Label 1758*/ GIMT_Encode4(57880), GIMT_Encode4(0),
21078 /* 57868 */ /*GILLT_v4s16*//*Label 1759*/ GIMT_Encode4(57926), GIMT_Encode4(0),
21079 /* 57876 */ /*GILLT_v2s32*//*Label 1760*/ GIMT_Encode4(57972),
21080 /* 57880 */ // Label 1758: @57880
21081 /* 57880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1762*/ GIMT_Encode4(57925), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1436 //
21082 /* 57887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21083 /* 57890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21084 /* 57893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21085 /* 57897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21086 /* 57901 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21087 /* 57905 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4057:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21088 /* 57905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8),
21089 /* 57908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21090 /* 57910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21091 /* 57912 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21092 /* 57914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21093 /* 57917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21094 /* 57923 */ GIR_RootConstrainSelectedInstOperands,
21095 /* 57924 */ // GIR_Coverage, 1436,
21096 /* 57924 */ GIR_EraseRootFromParent_Done,
21097 /* 57925 */ // Label 1762: @57925
21098 /* 57925 */ GIM_Reject,
21099 /* 57926 */ // Label 1759: @57926
21100 /* 57926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1763*/ GIMT_Encode4(57971), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1437 //
21101 /* 57933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21102 /* 57936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21103 /* 57939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21104 /* 57943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21105 /* 57947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21106 /* 57951 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21107 /* 57951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16),
21108 /* 57954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21109 /* 57956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21110 /* 57958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21111 /* 57960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21112 /* 57963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21113 /* 57969 */ GIR_RootConstrainSelectedInstOperands,
21114 /* 57970 */ // GIR_Coverage, 1437,
21115 /* 57970 */ GIR_EraseRootFromParent_Done,
21116 /* 57971 */ // Label 1763: @57971
21117 /* 57971 */ GIM_Reject,
21118 /* 57972 */ // Label 1760: @57972
21119 /* 57972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1764*/ GIMT_Encode4(58017), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1438 //
21120 /* 57979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21121 /* 57982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21122 /* 57985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21123 /* 57989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21124 /* 57993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21125 /* 57997 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21126 /* 57997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32),
21127 /* 58000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21128 /* 58002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21129 /* 58004 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21130 /* 58006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21131 /* 58009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21132 /* 58015 */ GIR_RootConstrainSelectedInstOperands,
21133 /* 58016 */ // GIR_Coverage, 1438,
21134 /* 58016 */ GIR_EraseRootFromParent_Done,
21135 /* 58017 */ // Label 1764: @58017
21136 /* 58017 */ GIM_Reject,
21137 /* 58018 */ // Label 1761: @58018
21138 /* 58018 */ GIM_Reject,
21139 /* 58019 */ // Label 1757: @58019
21140 /* 58019 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(58199),
21141 /* 58024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21142 /* 58029 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1769*/ GIMT_Encode4(58198),
21143 /* 58040 */ /*GILLT_v8s8*//*Label 1766*/ GIMT_Encode4(58060), GIMT_Encode4(0),
21144 /* 58048 */ /*GILLT_v4s16*//*Label 1767*/ GIMT_Encode4(58106), GIMT_Encode4(0),
21145 /* 58056 */ /*GILLT_v2s32*//*Label 1768*/ GIMT_Encode4(58152),
21146 /* 58060 */ // Label 1766: @58060
21147 /* 58060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1770*/ GIMT_Encode4(58105), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1439 //
21148 /* 58067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21149 /* 58070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21150 /* 58073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21151 /* 58077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21152 /* 58081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21153 /* 58085 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4058:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21154 /* 58085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8),
21155 /* 58088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21156 /* 58090 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21157 /* 58092 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21158 /* 58094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21159 /* 58097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21160 /* 58103 */ GIR_RootConstrainSelectedInstOperands,
21161 /* 58104 */ // GIR_Coverage, 1439,
21162 /* 58104 */ GIR_EraseRootFromParent_Done,
21163 /* 58105 */ // Label 1770: @58105
21164 /* 58105 */ GIM_Reject,
21165 /* 58106 */ // Label 1767: @58106
21166 /* 58106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1771*/ GIMT_Encode4(58151), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1440 //
21167 /* 58113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21168 /* 58116 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21169 /* 58119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21170 /* 58123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21171 /* 58127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21172 /* 58131 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4058:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21173 /* 58131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16),
21174 /* 58134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21175 /* 58136 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21176 /* 58138 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21177 /* 58140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21178 /* 58143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21179 /* 58149 */ GIR_RootConstrainSelectedInstOperands,
21180 /* 58150 */ // GIR_Coverage, 1440,
21181 /* 58150 */ GIR_EraseRootFromParent_Done,
21182 /* 58151 */ // Label 1771: @58151
21183 /* 58151 */ GIM_Reject,
21184 /* 58152 */ // Label 1768: @58152
21185 /* 58152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1772*/ GIMT_Encode4(58197), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1441 //
21186 /* 58159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21187 /* 58162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21188 /* 58165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21189 /* 58169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21190 /* 58173 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21191 /* 58177 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4058:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21192 /* 58177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32),
21193 /* 58180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21194 /* 58182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21195 /* 58184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21196 /* 58186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21197 /* 58189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21198 /* 58195 */ GIR_RootConstrainSelectedInstOperands,
21199 /* 58196 */ // GIR_Coverage, 1441,
21200 /* 58196 */ GIR_EraseRootFromParent_Done,
21201 /* 58197 */ // Label 1772: @58197
21202 /* 58197 */ GIM_Reject,
21203 /* 58198 */ // Label 1769: @58198
21204 /* 58198 */ GIM_Reject,
21205 /* 58199 */ // Label 1765: @58199
21206 /* 58199 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(58325),
21207 /* 58204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21208 /* 58209 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1776*/ GIMT_Encode4(58324),
21209 /* 58220 */ /*GILLT_v4s16*//*Label 1774*/ GIMT_Encode4(58232), GIMT_Encode4(0),
21210 /* 58228 */ /*GILLT_v2s32*//*Label 1775*/ GIMT_Encode4(58278),
21211 /* 58232 */ // Label 1774: @58232
21212 /* 58232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1777*/ GIMT_Encode4(58277), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1443 //
21213 /* 58239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21214 /* 58242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21215 /* 58245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21216 /* 58249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21217 /* 58253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21218 /* 58257 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21219 /* 58257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh),
21220 /* 58260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21221 /* 58262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21222 /* 58264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21223 /* 58266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21224 /* 58269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21225 /* 58275 */ GIR_RootConstrainSelectedInstOperands,
21226 /* 58276 */ // GIR_Coverage, 1443,
21227 /* 58276 */ GIR_EraseRootFromParent_Done,
21228 /* 58277 */ // Label 1777: @58277
21229 /* 58277 */ GIM_Reject,
21230 /* 58278 */ // Label 1775: @58278
21231 /* 58278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1778*/ GIMT_Encode4(58323), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1442 //
21232 /* 58285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21233 /* 58288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21234 /* 58291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21235 /* 58295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21236 /* 58299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21237 /* 58303 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21238 /* 58303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf),
21239 /* 58306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21240 /* 58308 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21241 /* 58310 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21242 /* 58312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21243 /* 58315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21244 /* 58321 */ GIR_RootConstrainSelectedInstOperands,
21245 /* 58322 */ // GIR_Coverage, 1442,
21246 /* 58322 */ GIR_EraseRootFromParent_Done,
21247 /* 58323 */ // Label 1778: @58323
21248 /* 58323 */ GIM_Reject,
21249 /* 58324 */ // Label 1776: @58324
21250 /* 58324 */ GIM_Reject,
21251 /* 58325 */ // Label 1773: @58325
21252 /* 58325 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(58547),
21253 /* 58330 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
21254 /* 58335 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1784*/ GIMT_Encode4(58546),
21255 /* 58346 */ /*GILLT_v4s16*//*Label 1780*/ GIMT_Encode4(58362),
21256 /* 58350 */ /*GILLT_v8s16*//*Label 1781*/ GIMT_Encode4(58408),
21257 /* 58354 */ /*GILLT_v2s32*//*Label 1782*/ GIMT_Encode4(58454),
21258 /* 58358 */ /*GILLT_v4s32*//*Label 1783*/ GIMT_Encode4(58500),
21259 /* 58362 */ // Label 1780: @58362
21260 /* 58362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1785*/ GIMT_Encode4(58407), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1452 //
21261 /* 58369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21262 /* 58372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21263 /* 58375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21264 /* 58379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21265 /* 58383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21266 /* 58387 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4082:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21267 /* 58387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd),
21268 /* 58390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21269 /* 58392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21270 /* 58394 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21271 /* 58396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21272 /* 58399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21273 /* 58405 */ GIR_RootConstrainSelectedInstOperands,
21274 /* 58406 */ // GIR_Coverage, 1452,
21275 /* 58406 */ GIR_EraseRootFromParent_Done,
21276 /* 58407 */ // Label 1785: @58407
21277 /* 58407 */ GIM_Reject,
21278 /* 58408 */ // Label 1781: @58408
21279 /* 58408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1786*/ GIMT_Encode4(58453), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1453 //
21280 /* 58415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21281 /* 58418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21282 /* 58421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21283 /* 58425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21284 /* 58429 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21285 /* 58433 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4082:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21286 /* 58433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq),
21287 /* 58436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21288 /* 58438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21289 /* 58440 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21290 /* 58442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21291 /* 58445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21292 /* 58451 */ GIR_RootConstrainSelectedInstOperands,
21293 /* 58452 */ // GIR_Coverage, 1453,
21294 /* 58452 */ GIR_EraseRootFromParent_Done,
21295 /* 58453 */ // Label 1786: @58453
21296 /* 58453 */ GIM_Reject,
21297 /* 58454 */ // Label 1782: @58454
21298 /* 58454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1787*/ GIMT_Encode4(58499), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1450 //
21299 /* 58461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21300 /* 58464 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21301 /* 58467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21302 /* 58471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21303 /* 58475 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21304 /* 58479 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4082:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21305 /* 58479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd),
21306 /* 58482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21307 /* 58484 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21308 /* 58486 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21309 /* 58488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21310 /* 58491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21311 /* 58497 */ GIR_RootConstrainSelectedInstOperands,
21312 /* 58498 */ // GIR_Coverage, 1450,
21313 /* 58498 */ GIR_EraseRootFromParent_Done,
21314 /* 58499 */ // Label 1787: @58499
21315 /* 58499 */ GIM_Reject,
21316 /* 58500 */ // Label 1783: @58500
21317 /* 58500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1788*/ GIMT_Encode4(58545), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1451 //
21318 /* 58507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21319 /* 58510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21320 /* 58513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21321 /* 58517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21322 /* 58521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21323 /* 58525 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4082:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21324 /* 58525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq),
21325 /* 58528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21326 /* 58530 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21327 /* 58532 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21328 /* 58534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21329 /* 58537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21330 /* 58543 */ GIR_RootConstrainSelectedInstOperands,
21331 /* 58544 */ // GIR_Coverage, 1451,
21332 /* 58544 */ GIR_EraseRootFromParent_Done,
21333 /* 58545 */ // Label 1788: @58545
21334 /* 58545 */ GIM_Reject,
21335 /* 58546 */ // Label 1784: @58546
21336 /* 58546 */ GIM_Reject,
21337 /* 58547 */ // Label 1779: @58547
21338 /* 58547 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(58769),
21339 /* 58552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
21340 /* 58557 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1794*/ GIMT_Encode4(58768),
21341 /* 58568 */ /*GILLT_v4s16*//*Label 1790*/ GIMT_Encode4(58584),
21342 /* 58572 */ /*GILLT_v8s16*//*Label 1791*/ GIMT_Encode4(58630),
21343 /* 58576 */ /*GILLT_v2s32*//*Label 1792*/ GIMT_Encode4(58676),
21344 /* 58580 */ /*GILLT_v4s32*//*Label 1793*/ GIMT_Encode4(58722),
21345 /* 58584 */ // Label 1790: @58584
21346 /* 58584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1795*/ GIMT_Encode4(58629), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1462 //
21347 /* 58591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21348 /* 58594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21349 /* 58597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21350 /* 58601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21351 /* 58605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21352 /* 58609 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4089:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21353 /* 58609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd),
21354 /* 58612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21355 /* 58614 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21356 /* 58616 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21357 /* 58618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21358 /* 58621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21359 /* 58627 */ GIR_RootConstrainSelectedInstOperands,
21360 /* 58628 */ // GIR_Coverage, 1462,
21361 /* 58628 */ GIR_EraseRootFromParent_Done,
21362 /* 58629 */ // Label 1795: @58629
21363 /* 58629 */ GIM_Reject,
21364 /* 58630 */ // Label 1791: @58630
21365 /* 58630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1796*/ GIMT_Encode4(58675), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1463 //
21366 /* 58637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21367 /* 58640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21368 /* 58643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21369 /* 58647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21370 /* 58651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21371 /* 58655 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4089:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21372 /* 58655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq),
21373 /* 58658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21374 /* 58660 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21375 /* 58662 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21376 /* 58664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21377 /* 58667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21378 /* 58673 */ GIR_RootConstrainSelectedInstOperands,
21379 /* 58674 */ // GIR_Coverage, 1463,
21380 /* 58674 */ GIR_EraseRootFromParent_Done,
21381 /* 58675 */ // Label 1796: @58675
21382 /* 58675 */ GIM_Reject,
21383 /* 58676 */ // Label 1792: @58676
21384 /* 58676 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1797*/ GIMT_Encode4(58721), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1460 //
21385 /* 58683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21386 /* 58686 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21387 /* 58689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21388 /* 58693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21389 /* 58697 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21390 /* 58701 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4089:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21391 /* 58701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd),
21392 /* 58704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21393 /* 58706 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21394 /* 58708 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21395 /* 58710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21396 /* 58713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21397 /* 58719 */ GIR_RootConstrainSelectedInstOperands,
21398 /* 58720 */ // GIR_Coverage, 1460,
21399 /* 58720 */ GIR_EraseRootFromParent_Done,
21400 /* 58721 */ // Label 1797: @58721
21401 /* 58721 */ GIM_Reject,
21402 /* 58722 */ // Label 1793: @58722
21403 /* 58722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1798*/ GIMT_Encode4(58767), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1461 //
21404 /* 58729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21405 /* 58732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21406 /* 58735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21407 /* 58739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21408 /* 58743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21409 /* 58747 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4089:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21410 /* 58747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq),
21411 /* 58750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21412 /* 58752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21413 /* 58754 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21414 /* 58756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21415 /* 58759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21416 /* 58765 */ GIR_RootConstrainSelectedInstOperands,
21417 /* 58766 */ // GIR_Coverage, 1461,
21418 /* 58766 */ GIR_EraseRootFromParent_Done,
21419 /* 58767 */ // Label 1798: @58767
21420 /* 58767 */ GIM_Reject,
21421 /* 58768 */ // Label 1794: @58768
21422 /* 58768 */ GIM_Reject,
21423 /* 58769 */ // Label 1789: @58769
21424 /* 58769 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(59207),
21425 /* 58774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21426 /* 58779 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1808*/ GIMT_Encode4(59206),
21427 /* 58790 */ /*GILLT_s64*//*Label 1800*/ GIMT_Encode4(58838), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21428 /* 58810 */ /*GILLT_v8s8*//*Label 1801*/ GIMT_Encode4(58884),
21429 /* 58814 */ /*GILLT_v16s8*//*Label 1802*/ GIMT_Encode4(58930),
21430 /* 58818 */ /*GILLT_v4s16*//*Label 1803*/ GIMT_Encode4(58976),
21431 /* 58822 */ /*GILLT_v8s16*//*Label 1804*/ GIMT_Encode4(59022),
21432 /* 58826 */ /*GILLT_v2s32*//*Label 1805*/ GIMT_Encode4(59068),
21433 /* 58830 */ /*GILLT_v4s32*//*Label 1806*/ GIMT_Encode4(59114),
21434 /* 58834 */ /*GILLT_v2s64*//*Label 1807*/ GIMT_Encode4(59160),
21435 /* 58838 */ // Label 1800: @58838
21436 /* 58838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1809*/ GIMT_Encode4(58883), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1470 //
21437 /* 58845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21438 /* 58848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21439 /* 58851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21440 /* 58855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21441 /* 58859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21442 /* 58863 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4092:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21443 /* 58863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64),
21444 /* 58866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21445 /* 58868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21446 /* 58870 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21447 /* 58872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21448 /* 58875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21449 /* 58881 */ GIR_RootConstrainSelectedInstOperands,
21450 /* 58882 */ // GIR_Coverage, 1470,
21451 /* 58882 */ GIR_EraseRootFromParent_Done,
21452 /* 58883 */ // Label 1809: @58883
21453 /* 58883 */ GIM_Reject,
21454 /* 58884 */ // Label 1801: @58884
21455 /* 58884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1810*/ GIMT_Encode4(58929), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1468 //
21456 /* 58891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21457 /* 58894 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21458 /* 58897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21459 /* 58901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21460 /* 58905 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21461 /* 58909 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4092:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21462 /* 58909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8),
21463 /* 58912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21464 /* 58914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21465 /* 58916 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21466 /* 58918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21467 /* 58921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21468 /* 58927 */ GIR_RootConstrainSelectedInstOperands,
21469 /* 58928 */ // GIR_Coverage, 1468,
21470 /* 58928 */ GIR_EraseRootFromParent_Done,
21471 /* 58929 */ // Label 1810: @58929
21472 /* 58929 */ GIM_Reject,
21473 /* 58930 */ // Label 1802: @58930
21474 /* 58930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1811*/ GIMT_Encode4(58975), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1469 //
21475 /* 58937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21476 /* 58940 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21477 /* 58943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21478 /* 58947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21479 /* 58951 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21480 /* 58955 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4092:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21481 /* 58955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8),
21482 /* 58958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21483 /* 58960 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21484 /* 58962 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21485 /* 58964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21486 /* 58967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21487 /* 58973 */ GIR_RootConstrainSelectedInstOperands,
21488 /* 58974 */ // GIR_Coverage, 1469,
21489 /* 58974 */ GIR_EraseRootFromParent_Done,
21490 /* 58975 */ // Label 1811: @58975
21491 /* 58975 */ GIM_Reject,
21492 /* 58976 */ // Label 1803: @58976
21493 /* 58976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1812*/ GIMT_Encode4(59021), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1464 //
21494 /* 58983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21495 /* 58986 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21496 /* 58989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21497 /* 58993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21498 /* 58997 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21499 /* 59001 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4092:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21500 /* 59001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16),
21501 /* 59004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21502 /* 59006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21503 /* 59008 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21504 /* 59010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21505 /* 59013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21506 /* 59019 */ GIR_RootConstrainSelectedInstOperands,
21507 /* 59020 */ // GIR_Coverage, 1464,
21508 /* 59020 */ GIR_EraseRootFromParent_Done,
21509 /* 59021 */ // Label 1812: @59021
21510 /* 59021 */ GIM_Reject,
21511 /* 59022 */ // Label 1804: @59022
21512 /* 59022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1813*/ GIMT_Encode4(59067), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1466 //
21513 /* 59029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21514 /* 59032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21515 /* 59035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21516 /* 59039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21517 /* 59043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21518 /* 59047 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4092:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21519 /* 59047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16),
21520 /* 59050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21521 /* 59052 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21522 /* 59054 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21523 /* 59056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21524 /* 59059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21525 /* 59065 */ GIR_RootConstrainSelectedInstOperands,
21526 /* 59066 */ // GIR_Coverage, 1466,
21527 /* 59066 */ GIR_EraseRootFromParent_Done,
21528 /* 59067 */ // Label 1813: @59067
21529 /* 59067 */ GIM_Reject,
21530 /* 59068 */ // Label 1805: @59068
21531 /* 59068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1814*/ GIMT_Encode4(59113), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1465 //
21532 /* 59075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21533 /* 59078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21534 /* 59081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21535 /* 59085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21536 /* 59089 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21537 /* 59093 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4092:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21538 /* 59093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32),
21539 /* 59096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21540 /* 59098 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21541 /* 59100 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21542 /* 59102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21543 /* 59105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21544 /* 59111 */ GIR_RootConstrainSelectedInstOperands,
21545 /* 59112 */ // GIR_Coverage, 1465,
21546 /* 59112 */ GIR_EraseRootFromParent_Done,
21547 /* 59113 */ // Label 1814: @59113
21548 /* 59113 */ GIM_Reject,
21549 /* 59114 */ // Label 1806: @59114
21550 /* 59114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1815*/ GIMT_Encode4(59159), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1467 //
21551 /* 59121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21552 /* 59124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21553 /* 59127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21554 /* 59131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21555 /* 59135 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21556 /* 59139 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4092:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21557 /* 59139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32),
21558 /* 59142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21559 /* 59144 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21560 /* 59146 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21561 /* 59148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21562 /* 59151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21563 /* 59157 */ GIR_RootConstrainSelectedInstOperands,
21564 /* 59158 */ // GIR_Coverage, 1467,
21565 /* 59158 */ GIR_EraseRootFromParent_Done,
21566 /* 59159 */ // Label 1815: @59159
21567 /* 59159 */ GIM_Reject,
21568 /* 59160 */ // Label 1807: @59160
21569 /* 59160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1816*/ GIMT_Encode4(59205), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1471 //
21570 /* 59167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21571 /* 59170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21572 /* 59173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21573 /* 59177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21574 /* 59181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21575 /* 59185 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4092:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21576 /* 59185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64),
21577 /* 59188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21578 /* 59190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21579 /* 59192 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21580 /* 59194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21581 /* 59197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21582 /* 59203 */ GIR_RootConstrainSelectedInstOperands,
21583 /* 59204 */ // GIR_Coverage, 1471,
21584 /* 59204 */ GIR_EraseRootFromParent_Done,
21585 /* 59205 */ // Label 1816: @59205
21586 /* 59205 */ GIM_Reject,
21587 /* 59206 */ // Label 1808: @59206
21588 /* 59206 */ GIM_Reject,
21589 /* 59207 */ // Label 1799: @59207
21590 /* 59207 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(59645),
21591 /* 59212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21592 /* 59217 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1826*/ GIMT_Encode4(59644),
21593 /* 59228 */ /*GILLT_s64*//*Label 1818*/ GIMT_Encode4(59276), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21594 /* 59248 */ /*GILLT_v8s8*//*Label 1819*/ GIMT_Encode4(59322),
21595 /* 59252 */ /*GILLT_v16s8*//*Label 1820*/ GIMT_Encode4(59368),
21596 /* 59256 */ /*GILLT_v4s16*//*Label 1821*/ GIMT_Encode4(59414),
21597 /* 59260 */ /*GILLT_v8s16*//*Label 1822*/ GIMT_Encode4(59460),
21598 /* 59264 */ /*GILLT_v2s32*//*Label 1823*/ GIMT_Encode4(59506),
21599 /* 59268 */ /*GILLT_v4s32*//*Label 1824*/ GIMT_Encode4(59552),
21600 /* 59272 */ /*GILLT_v2s64*//*Label 1825*/ GIMT_Encode4(59598),
21601 /* 59276 */ // Label 1818: @59276
21602 /* 59276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1827*/ GIMT_Encode4(59321), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1478 //
21603 /* 59283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21604 /* 59286 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21605 /* 59289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21606 /* 59293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21607 /* 59297 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21608 /* 59301 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4093:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21609 /* 59301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64),
21610 /* 59304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21611 /* 59306 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21612 /* 59308 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21613 /* 59310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21614 /* 59313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21615 /* 59319 */ GIR_RootConstrainSelectedInstOperands,
21616 /* 59320 */ // GIR_Coverage, 1478,
21617 /* 59320 */ GIR_EraseRootFromParent_Done,
21618 /* 59321 */ // Label 1827: @59321
21619 /* 59321 */ GIM_Reject,
21620 /* 59322 */ // Label 1819: @59322
21621 /* 59322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1828*/ GIMT_Encode4(59367), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1476 //
21622 /* 59329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21623 /* 59332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21624 /* 59335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21625 /* 59339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21626 /* 59343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21627 /* 59347 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4093:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21628 /* 59347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8),
21629 /* 59350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21630 /* 59352 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21631 /* 59354 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21632 /* 59356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21633 /* 59359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21634 /* 59365 */ GIR_RootConstrainSelectedInstOperands,
21635 /* 59366 */ // GIR_Coverage, 1476,
21636 /* 59366 */ GIR_EraseRootFromParent_Done,
21637 /* 59367 */ // Label 1828: @59367
21638 /* 59367 */ GIM_Reject,
21639 /* 59368 */ // Label 1820: @59368
21640 /* 59368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1829*/ GIMT_Encode4(59413), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1477 //
21641 /* 59375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21642 /* 59378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21643 /* 59381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21644 /* 59385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21645 /* 59389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21646 /* 59393 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4093:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21647 /* 59393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8),
21648 /* 59396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21649 /* 59398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21650 /* 59400 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21651 /* 59402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21652 /* 59405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21653 /* 59411 */ GIR_RootConstrainSelectedInstOperands,
21654 /* 59412 */ // GIR_Coverage, 1477,
21655 /* 59412 */ GIR_EraseRootFromParent_Done,
21656 /* 59413 */ // Label 1829: @59413
21657 /* 59413 */ GIM_Reject,
21658 /* 59414 */ // Label 1821: @59414
21659 /* 59414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1830*/ GIMT_Encode4(59459), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1472 //
21660 /* 59421 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21661 /* 59424 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21662 /* 59427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21663 /* 59431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21664 /* 59435 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21665 /* 59439 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4093:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21666 /* 59439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16),
21667 /* 59442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21668 /* 59444 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21669 /* 59446 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21670 /* 59448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21671 /* 59451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21672 /* 59457 */ GIR_RootConstrainSelectedInstOperands,
21673 /* 59458 */ // GIR_Coverage, 1472,
21674 /* 59458 */ GIR_EraseRootFromParent_Done,
21675 /* 59459 */ // Label 1830: @59459
21676 /* 59459 */ GIM_Reject,
21677 /* 59460 */ // Label 1822: @59460
21678 /* 59460 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1831*/ GIMT_Encode4(59505), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1474 //
21679 /* 59467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21680 /* 59470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21681 /* 59473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21682 /* 59477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21683 /* 59481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21684 /* 59485 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4093:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21685 /* 59485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16),
21686 /* 59488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21687 /* 59490 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21688 /* 59492 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21689 /* 59494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21690 /* 59497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21691 /* 59503 */ GIR_RootConstrainSelectedInstOperands,
21692 /* 59504 */ // GIR_Coverage, 1474,
21693 /* 59504 */ GIR_EraseRootFromParent_Done,
21694 /* 59505 */ // Label 1831: @59505
21695 /* 59505 */ GIM_Reject,
21696 /* 59506 */ // Label 1823: @59506
21697 /* 59506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1832*/ GIMT_Encode4(59551), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1473 //
21698 /* 59513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21699 /* 59516 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21700 /* 59519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21701 /* 59523 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21702 /* 59527 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21703 /* 59531 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4093:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21704 /* 59531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32),
21705 /* 59534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21706 /* 59536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21707 /* 59538 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21708 /* 59540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21709 /* 59543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21710 /* 59549 */ GIR_RootConstrainSelectedInstOperands,
21711 /* 59550 */ // GIR_Coverage, 1473,
21712 /* 59550 */ GIR_EraseRootFromParent_Done,
21713 /* 59551 */ // Label 1832: @59551
21714 /* 59551 */ GIM_Reject,
21715 /* 59552 */ // Label 1824: @59552
21716 /* 59552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1833*/ GIMT_Encode4(59597), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1475 //
21717 /* 59559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21718 /* 59562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21719 /* 59565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21720 /* 59569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21721 /* 59573 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21722 /* 59577 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4093:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21723 /* 59577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32),
21724 /* 59580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21725 /* 59582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21726 /* 59584 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21727 /* 59586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21728 /* 59589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21729 /* 59595 */ GIR_RootConstrainSelectedInstOperands,
21730 /* 59596 */ // GIR_Coverage, 1475,
21731 /* 59596 */ GIR_EraseRootFromParent_Done,
21732 /* 59597 */ // Label 1833: @59597
21733 /* 59597 */ GIM_Reject,
21734 /* 59598 */ // Label 1825: @59598
21735 /* 59598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1834*/ GIMT_Encode4(59643), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1479 //
21736 /* 59605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21737 /* 59608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21738 /* 59611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21739 /* 59615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21740 /* 59619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21741 /* 59623 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4093:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21742 /* 59623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64),
21743 /* 59626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21744 /* 59628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21745 /* 59630 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21746 /* 59632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21747 /* 59635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21748 /* 59641 */ GIR_RootConstrainSelectedInstOperands,
21749 /* 59642 */ // GIR_Coverage, 1479,
21750 /* 59642 */ GIR_EraseRootFromParent_Done,
21751 /* 59643 */ // Label 1834: @59643
21752 /* 59643 */ GIM_Reject,
21753 /* 59644 */ // Label 1826: @59644
21754 /* 59644 */ GIM_Reject,
21755 /* 59645 */ // Label 1817: @59645
21756 /* 59645 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(60083),
21757 /* 59650 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
21758 /* 59655 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1844*/ GIMT_Encode4(60082),
21759 /* 59666 */ /*GILLT_s64*//*Label 1836*/ GIMT_Encode4(59714), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21760 /* 59686 */ /*GILLT_v8s8*//*Label 1837*/ GIMT_Encode4(59760),
21761 /* 59690 */ /*GILLT_v16s8*//*Label 1838*/ GIMT_Encode4(59806),
21762 /* 59694 */ /*GILLT_v4s16*//*Label 1839*/ GIMT_Encode4(59852),
21763 /* 59698 */ /*GILLT_v8s16*//*Label 1840*/ GIMT_Encode4(59898),
21764 /* 59702 */ /*GILLT_v2s32*//*Label 1841*/ GIMT_Encode4(59944),
21765 /* 59706 */ /*GILLT_v4s32*//*Label 1842*/ GIMT_Encode4(59990),
21766 /* 59710 */ /*GILLT_v2s64*//*Label 1843*/ GIMT_Encode4(60036),
21767 /* 59714 */ // Label 1836: @59714
21768 /* 59714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1845*/ GIMT_Encode4(59759), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1519 //
21769 /* 59721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21770 /* 59724 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21771 /* 59727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21772 /* 59731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21773 /* 59735 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21774 /* 59739 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4086:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21775 /* 59739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64),
21776 /* 59742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21777 /* 59744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21778 /* 59746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21779 /* 59748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21780 /* 59751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21781 /* 59757 */ GIR_RootConstrainSelectedInstOperands,
21782 /* 59758 */ // GIR_Coverage, 1519,
21783 /* 59758 */ GIR_EraseRootFromParent_Done,
21784 /* 59759 */ // Label 1845: @59759
21785 /* 59759 */ GIM_Reject,
21786 /* 59760 */ // Label 1837: @59760
21787 /* 59760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1846*/ GIMT_Encode4(59805), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1517 //
21788 /* 59767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21789 /* 59770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21790 /* 59773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21791 /* 59777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21792 /* 59781 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21793 /* 59785 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4086:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21794 /* 59785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8),
21795 /* 59788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21796 /* 59790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21797 /* 59792 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21798 /* 59794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21799 /* 59797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21800 /* 59803 */ GIR_RootConstrainSelectedInstOperands,
21801 /* 59804 */ // GIR_Coverage, 1517,
21802 /* 59804 */ GIR_EraseRootFromParent_Done,
21803 /* 59805 */ // Label 1846: @59805
21804 /* 59805 */ GIM_Reject,
21805 /* 59806 */ // Label 1838: @59806
21806 /* 59806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1847*/ GIMT_Encode4(59851), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1518 //
21807 /* 59813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21808 /* 59816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21809 /* 59819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21810 /* 59823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21811 /* 59827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21812 /* 59831 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4086:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21813 /* 59831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8),
21814 /* 59834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21815 /* 59836 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21816 /* 59838 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21817 /* 59840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21818 /* 59843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21819 /* 59849 */ GIR_RootConstrainSelectedInstOperands,
21820 /* 59850 */ // GIR_Coverage, 1518,
21821 /* 59850 */ GIR_EraseRootFromParent_Done,
21822 /* 59851 */ // Label 1847: @59851
21823 /* 59851 */ GIM_Reject,
21824 /* 59852 */ // Label 1839: @59852
21825 /* 59852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1848*/ GIMT_Encode4(59897), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1513 //
21826 /* 59859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21827 /* 59862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21828 /* 59865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21829 /* 59869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21830 /* 59873 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21831 /* 59877 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4086:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21832 /* 59877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16),
21833 /* 59880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21834 /* 59882 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21835 /* 59884 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21836 /* 59886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21837 /* 59889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21838 /* 59895 */ GIR_RootConstrainSelectedInstOperands,
21839 /* 59896 */ // GIR_Coverage, 1513,
21840 /* 59896 */ GIR_EraseRootFromParent_Done,
21841 /* 59897 */ // Label 1848: @59897
21842 /* 59897 */ GIM_Reject,
21843 /* 59898 */ // Label 1840: @59898
21844 /* 59898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1849*/ GIMT_Encode4(59943), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1515 //
21845 /* 59905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21846 /* 59908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21847 /* 59911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21848 /* 59915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21849 /* 59919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21850 /* 59923 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4086:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21851 /* 59923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16),
21852 /* 59926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21853 /* 59928 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21854 /* 59930 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21855 /* 59932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21856 /* 59935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21857 /* 59941 */ GIR_RootConstrainSelectedInstOperands,
21858 /* 59942 */ // GIR_Coverage, 1515,
21859 /* 59942 */ GIR_EraseRootFromParent_Done,
21860 /* 59943 */ // Label 1849: @59943
21861 /* 59943 */ GIM_Reject,
21862 /* 59944 */ // Label 1841: @59944
21863 /* 59944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1850*/ GIMT_Encode4(59989), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1514 //
21864 /* 59951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21865 /* 59954 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21866 /* 59957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21867 /* 59961 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21868 /* 59965 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21869 /* 59969 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4086:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21870 /* 59969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32),
21871 /* 59972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21872 /* 59974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21873 /* 59976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21874 /* 59978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21875 /* 59981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21876 /* 59987 */ GIR_RootConstrainSelectedInstOperands,
21877 /* 59988 */ // GIR_Coverage, 1514,
21878 /* 59988 */ GIR_EraseRootFromParent_Done,
21879 /* 59989 */ // Label 1850: @59989
21880 /* 59989 */ GIM_Reject,
21881 /* 59990 */ // Label 1842: @59990
21882 /* 59990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1851*/ GIMT_Encode4(60035), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1516 //
21883 /* 59997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21884 /* 60000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21885 /* 60003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21886 /* 60007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21887 /* 60011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21888 /* 60015 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4086:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21889 /* 60015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32),
21890 /* 60018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21891 /* 60020 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21892 /* 60022 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21893 /* 60024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21894 /* 60027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21895 /* 60033 */ GIR_RootConstrainSelectedInstOperands,
21896 /* 60034 */ // GIR_Coverage, 1516,
21897 /* 60034 */ GIR_EraseRootFromParent_Done,
21898 /* 60035 */ // Label 1851: @60035
21899 /* 60035 */ GIM_Reject,
21900 /* 60036 */ // Label 1843: @60036
21901 /* 60036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1852*/ GIMT_Encode4(60081), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1520 //
21902 /* 60043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21903 /* 60046 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21904 /* 60049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21905 /* 60053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21906 /* 60057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21907 /* 60061 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4086:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21908 /* 60061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64),
21909 /* 60064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21910 /* 60066 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21911 /* 60068 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21912 /* 60070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21913 /* 60073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21914 /* 60079 */ GIR_RootConstrainSelectedInstOperands,
21915 /* 60080 */ // GIR_Coverage, 1520,
21916 /* 60080 */ GIR_EraseRootFromParent_Done,
21917 /* 60081 */ // Label 1852: @60081
21918 /* 60081 */ GIM_Reject,
21919 /* 60082 */ // Label 1844: @60082
21920 /* 60082 */ GIM_Reject,
21921 /* 60083 */ // Label 1835: @60083
21922 /* 60083 */ GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(60521),
21923 /* 60088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
21924 /* 60093 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1862*/ GIMT_Encode4(60520),
21925 /* 60104 */ /*GILLT_s64*//*Label 1854*/ GIMT_Encode4(60152), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21926 /* 60124 */ /*GILLT_v8s8*//*Label 1855*/ GIMT_Encode4(60198),
21927 /* 60128 */ /*GILLT_v16s8*//*Label 1856*/ GIMT_Encode4(60244),
21928 /* 60132 */ /*GILLT_v4s16*//*Label 1857*/ GIMT_Encode4(60290),
21929 /* 60136 */ /*GILLT_v8s16*//*Label 1858*/ GIMT_Encode4(60336),
21930 /* 60140 */ /*GILLT_v2s32*//*Label 1859*/ GIMT_Encode4(60382),
21931 /* 60144 */ /*GILLT_v4s32*//*Label 1860*/ GIMT_Encode4(60428),
21932 /* 60148 */ /*GILLT_v2s64*//*Label 1861*/ GIMT_Encode4(60474),
21933 /* 60152 */ // Label 1854: @60152
21934 /* 60152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1863*/ GIMT_Encode4(60197), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1527 //
21935 /* 60159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21936 /* 60162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21937 /* 60165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21938 /* 60169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21939 /* 60173 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21940 /* 60177 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4087:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21941 /* 60177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64),
21942 /* 60180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21943 /* 60182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21944 /* 60184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21945 /* 60186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21946 /* 60189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21947 /* 60195 */ GIR_RootConstrainSelectedInstOperands,
21948 /* 60196 */ // GIR_Coverage, 1527,
21949 /* 60196 */ GIR_EraseRootFromParent_Done,
21950 /* 60197 */ // Label 1863: @60197
21951 /* 60197 */ GIM_Reject,
21952 /* 60198 */ // Label 1855: @60198
21953 /* 60198 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1864*/ GIMT_Encode4(60243), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1525 //
21954 /* 60205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21955 /* 60208 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21956 /* 60211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21957 /* 60215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21958 /* 60219 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21959 /* 60223 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4087:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21960 /* 60223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8),
21961 /* 60226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21962 /* 60228 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21963 /* 60230 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21964 /* 60232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21965 /* 60235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21966 /* 60241 */ GIR_RootConstrainSelectedInstOperands,
21967 /* 60242 */ // GIR_Coverage, 1525,
21968 /* 60242 */ GIR_EraseRootFromParent_Done,
21969 /* 60243 */ // Label 1864: @60243
21970 /* 60243 */ GIM_Reject,
21971 /* 60244 */ // Label 1856: @60244
21972 /* 60244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1865*/ GIMT_Encode4(60289), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1526 //
21973 /* 60251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21974 /* 60254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21975 /* 60257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21976 /* 60261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21977 /* 60265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21978 /* 60269 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4087:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21979 /* 60269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8),
21980 /* 60272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21981 /* 60274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21982 /* 60276 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21983 /* 60278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21984 /* 60281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21985 /* 60287 */ GIR_RootConstrainSelectedInstOperands,
21986 /* 60288 */ // GIR_Coverage, 1526,
21987 /* 60288 */ GIR_EraseRootFromParent_Done,
21988 /* 60289 */ // Label 1865: @60289
21989 /* 60289 */ GIM_Reject,
21990 /* 60290 */ // Label 1857: @60290
21991 /* 60290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1866*/ GIMT_Encode4(60335), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1521 //
21992 /* 60297 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21993 /* 60300 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21994 /* 60303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21995 /* 60307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21996 /* 60311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21997 /* 60315 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4087:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21998 /* 60315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16),
21999 /* 60318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22000 /* 60320 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22001 /* 60322 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22002 /* 60324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22003 /* 60327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22004 /* 60333 */ GIR_RootConstrainSelectedInstOperands,
22005 /* 60334 */ // GIR_Coverage, 1521,
22006 /* 60334 */ GIR_EraseRootFromParent_Done,
22007 /* 60335 */ // Label 1866: @60335
22008 /* 60335 */ GIM_Reject,
22009 /* 60336 */ // Label 1858: @60336
22010 /* 60336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1867*/ GIMT_Encode4(60381), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1523 //
22011 /* 60343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22012 /* 60346 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22013 /* 60349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22014 /* 60353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22015 /* 60357 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22016 /* 60361 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4087:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22017 /* 60361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16),
22018 /* 60364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22019 /* 60366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22020 /* 60368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22021 /* 60370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22022 /* 60373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22023 /* 60379 */ GIR_RootConstrainSelectedInstOperands,
22024 /* 60380 */ // GIR_Coverage, 1523,
22025 /* 60380 */ GIR_EraseRootFromParent_Done,
22026 /* 60381 */ // Label 1867: @60381
22027 /* 60381 */ GIM_Reject,
22028 /* 60382 */ // Label 1859: @60382
22029 /* 60382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1868*/ GIMT_Encode4(60427), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1522 //
22030 /* 60389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22031 /* 60392 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22032 /* 60395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22033 /* 60399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22034 /* 60403 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22035 /* 60407 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4087:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22036 /* 60407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32),
22037 /* 60410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22038 /* 60412 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22039 /* 60414 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22040 /* 60416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22041 /* 60419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22042 /* 60425 */ GIR_RootConstrainSelectedInstOperands,
22043 /* 60426 */ // GIR_Coverage, 1522,
22044 /* 60426 */ GIR_EraseRootFromParent_Done,
22045 /* 60427 */ // Label 1868: @60427
22046 /* 60427 */ GIM_Reject,
22047 /* 60428 */ // Label 1860: @60428
22048 /* 60428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1869*/ GIMT_Encode4(60473), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1524 //
22049 /* 60435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22050 /* 60438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22051 /* 60441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22052 /* 60445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22053 /* 60449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22054 /* 60453 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4087:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22055 /* 60453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32),
22056 /* 60456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22057 /* 60458 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22058 /* 60460 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22059 /* 60462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22060 /* 60465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22061 /* 60471 */ GIR_RootConstrainSelectedInstOperands,
22062 /* 60472 */ // GIR_Coverage, 1524,
22063 /* 60472 */ GIR_EraseRootFromParent_Done,
22064 /* 60473 */ // Label 1869: @60473
22065 /* 60473 */ GIM_Reject,
22066 /* 60474 */ // Label 1861: @60474
22067 /* 60474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1870*/ GIMT_Encode4(60519), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1528 //
22068 /* 60481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22069 /* 60484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22070 /* 60487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22071 /* 60491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22072 /* 60495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22073 /* 60499 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4087:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22074 /* 60499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64),
22075 /* 60502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22076 /* 60504 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22077 /* 60506 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22078 /* 60508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22079 /* 60511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22080 /* 60517 */ GIR_RootConstrainSelectedInstOperands,
22081 /* 60518 */ // GIR_Coverage, 1528,
22082 /* 60518 */ GIR_EraseRootFromParent_Done,
22083 /* 60519 */ // Label 1870: @60519
22084 /* 60519 */ GIM_Reject,
22085 /* 60520 */ // Label 1862: @60520
22086 /* 60520 */ GIM_Reject,
22087 /* 60521 */ // Label 1853: @60521
22088 /* 60521 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(60959),
22089 /* 60526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22090 /* 60531 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1880*/ GIMT_Encode4(60958),
22091 /* 60542 */ /*GILLT_s64*//*Label 1872*/ GIMT_Encode4(60590), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22092 /* 60562 */ /*GILLT_v8s8*//*Label 1873*/ GIMT_Encode4(60636),
22093 /* 60566 */ /*GILLT_v16s8*//*Label 1874*/ GIMT_Encode4(60682),
22094 /* 60570 */ /*GILLT_v4s16*//*Label 1875*/ GIMT_Encode4(60728),
22095 /* 60574 */ /*GILLT_v8s16*//*Label 1876*/ GIMT_Encode4(60774),
22096 /* 60578 */ /*GILLT_v2s32*//*Label 1877*/ GIMT_Encode4(60820),
22097 /* 60582 */ /*GILLT_v4s32*//*Label 1878*/ GIMT_Encode4(60866),
22098 /* 60586 */ /*GILLT_v2s64*//*Label 1879*/ GIMT_Encode4(60912),
22099 /* 60590 */ // Label 1872: @60590
22100 /* 60590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1881*/ GIMT_Encode4(60635), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1554 //
22101 /* 60597 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22102 /* 60600 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22103 /* 60603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22104 /* 60607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22105 /* 60611 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22106 /* 60615 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4077:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22107 /* 60615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64),
22108 /* 60618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22109 /* 60620 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22110 /* 60622 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22111 /* 60624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22112 /* 60627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22113 /* 60633 */ GIR_RootConstrainSelectedInstOperands,
22114 /* 60634 */ // GIR_Coverage, 1554,
22115 /* 60634 */ GIR_EraseRootFromParent_Done,
22116 /* 60635 */ // Label 1881: @60635
22117 /* 60635 */ GIM_Reject,
22118 /* 60636 */ // Label 1873: @60636
22119 /* 60636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1882*/ GIMT_Encode4(60681), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1552 //
22120 /* 60643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22121 /* 60646 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22122 /* 60649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22123 /* 60653 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22124 /* 60657 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22125 /* 60661 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4077:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22126 /* 60661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8),
22127 /* 60664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22128 /* 60666 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22129 /* 60668 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22130 /* 60670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22131 /* 60673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22132 /* 60679 */ GIR_RootConstrainSelectedInstOperands,
22133 /* 60680 */ // GIR_Coverage, 1552,
22134 /* 60680 */ GIR_EraseRootFromParent_Done,
22135 /* 60681 */ // Label 1882: @60681
22136 /* 60681 */ GIM_Reject,
22137 /* 60682 */ // Label 1874: @60682
22138 /* 60682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1883*/ GIMT_Encode4(60727), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1553 //
22139 /* 60689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22140 /* 60692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22141 /* 60695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22142 /* 60699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22143 /* 60703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22144 /* 60707 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4077:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22145 /* 60707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8),
22146 /* 60710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22147 /* 60712 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22148 /* 60714 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22149 /* 60716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22150 /* 60719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22151 /* 60725 */ GIR_RootConstrainSelectedInstOperands,
22152 /* 60726 */ // GIR_Coverage, 1553,
22153 /* 60726 */ GIR_EraseRootFromParent_Done,
22154 /* 60727 */ // Label 1883: @60727
22155 /* 60727 */ GIM_Reject,
22156 /* 60728 */ // Label 1875: @60728
22157 /* 60728 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1884*/ GIMT_Encode4(60773), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1548 //
22158 /* 60735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22159 /* 60738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22160 /* 60741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22161 /* 60745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22162 /* 60749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22163 /* 60753 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4077:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22164 /* 60753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16),
22165 /* 60756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22166 /* 60758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22167 /* 60760 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22168 /* 60762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22169 /* 60765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22170 /* 60771 */ GIR_RootConstrainSelectedInstOperands,
22171 /* 60772 */ // GIR_Coverage, 1548,
22172 /* 60772 */ GIR_EraseRootFromParent_Done,
22173 /* 60773 */ // Label 1884: @60773
22174 /* 60773 */ GIM_Reject,
22175 /* 60774 */ // Label 1876: @60774
22176 /* 60774 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1885*/ GIMT_Encode4(60819), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1550 //
22177 /* 60781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22178 /* 60784 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22179 /* 60787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22180 /* 60791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22181 /* 60795 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22182 /* 60799 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4077:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22183 /* 60799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16),
22184 /* 60802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22185 /* 60804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22186 /* 60806 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22187 /* 60808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22188 /* 60811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22189 /* 60817 */ GIR_RootConstrainSelectedInstOperands,
22190 /* 60818 */ // GIR_Coverage, 1550,
22191 /* 60818 */ GIR_EraseRootFromParent_Done,
22192 /* 60819 */ // Label 1885: @60819
22193 /* 60819 */ GIM_Reject,
22194 /* 60820 */ // Label 1877: @60820
22195 /* 60820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1886*/ GIMT_Encode4(60865), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1549 //
22196 /* 60827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22197 /* 60830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22198 /* 60833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22199 /* 60837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22200 /* 60841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22201 /* 60845 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4077:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22202 /* 60845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32),
22203 /* 60848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22204 /* 60850 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22205 /* 60852 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22206 /* 60854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22207 /* 60857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22208 /* 60863 */ GIR_RootConstrainSelectedInstOperands,
22209 /* 60864 */ // GIR_Coverage, 1549,
22210 /* 60864 */ GIR_EraseRootFromParent_Done,
22211 /* 60865 */ // Label 1886: @60865
22212 /* 60865 */ GIM_Reject,
22213 /* 60866 */ // Label 1878: @60866
22214 /* 60866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1887*/ GIMT_Encode4(60911), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1551 //
22215 /* 60873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22216 /* 60876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22217 /* 60879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22218 /* 60883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22219 /* 60887 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22220 /* 60891 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4077:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22221 /* 60891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32),
22222 /* 60894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22223 /* 60896 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22224 /* 60898 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22225 /* 60900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22226 /* 60903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22227 /* 60909 */ GIR_RootConstrainSelectedInstOperands,
22228 /* 60910 */ // GIR_Coverage, 1551,
22229 /* 60910 */ GIR_EraseRootFromParent_Done,
22230 /* 60911 */ // Label 1887: @60911
22231 /* 60911 */ GIM_Reject,
22232 /* 60912 */ // Label 1879: @60912
22233 /* 60912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1888*/ GIMT_Encode4(60957), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1555 //
22234 /* 60919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22235 /* 60922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22236 /* 60925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22237 /* 60929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22238 /* 60933 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22239 /* 60937 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4077:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22240 /* 60937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64),
22241 /* 60940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22242 /* 60942 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22243 /* 60944 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22244 /* 60946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22245 /* 60949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22246 /* 60955 */ GIR_RootConstrainSelectedInstOperands,
22247 /* 60956 */ // GIR_Coverage, 1555,
22248 /* 60956 */ GIR_EraseRootFromParent_Done,
22249 /* 60957 */ // Label 1888: @60957
22250 /* 60957 */ GIM_Reject,
22251 /* 60958 */ // Label 1880: @60958
22252 /* 60958 */ GIM_Reject,
22253 /* 60959 */ // Label 1871: @60959
22254 /* 60959 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(61397),
22255 /* 60964 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22256 /* 60969 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1898*/ GIMT_Encode4(61396),
22257 /* 60980 */ /*GILLT_s64*//*Label 1890*/ GIMT_Encode4(61028), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22258 /* 61000 */ /*GILLT_v8s8*//*Label 1891*/ GIMT_Encode4(61074),
22259 /* 61004 */ /*GILLT_v16s8*//*Label 1892*/ GIMT_Encode4(61120),
22260 /* 61008 */ /*GILLT_v4s16*//*Label 1893*/ GIMT_Encode4(61166),
22261 /* 61012 */ /*GILLT_v8s16*//*Label 1894*/ GIMT_Encode4(61212),
22262 /* 61016 */ /*GILLT_v2s32*//*Label 1895*/ GIMT_Encode4(61258),
22263 /* 61020 */ /*GILLT_v4s32*//*Label 1896*/ GIMT_Encode4(61304),
22264 /* 61024 */ /*GILLT_v2s64*//*Label 1897*/ GIMT_Encode4(61350),
22265 /* 61028 */ // Label 1890: @61028
22266 /* 61028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1899*/ GIMT_Encode4(61073), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1562 //
22267 /* 61035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22268 /* 61038 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22269 /* 61041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22270 /* 61045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22271 /* 61049 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22272 /* 61053 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4079:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22273 /* 61053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64),
22274 /* 61056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22275 /* 61058 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22276 /* 61060 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22277 /* 61062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22278 /* 61065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22279 /* 61071 */ GIR_RootConstrainSelectedInstOperands,
22280 /* 61072 */ // GIR_Coverage, 1562,
22281 /* 61072 */ GIR_EraseRootFromParent_Done,
22282 /* 61073 */ // Label 1899: @61073
22283 /* 61073 */ GIM_Reject,
22284 /* 61074 */ // Label 1891: @61074
22285 /* 61074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1900*/ GIMT_Encode4(61119), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1560 //
22286 /* 61081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22287 /* 61084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22288 /* 61087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22289 /* 61091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22290 /* 61095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22291 /* 61099 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4079:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22292 /* 61099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8),
22293 /* 61102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22294 /* 61104 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22295 /* 61106 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22296 /* 61108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22297 /* 61111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22298 /* 61117 */ GIR_RootConstrainSelectedInstOperands,
22299 /* 61118 */ // GIR_Coverage, 1560,
22300 /* 61118 */ GIR_EraseRootFromParent_Done,
22301 /* 61119 */ // Label 1900: @61119
22302 /* 61119 */ GIM_Reject,
22303 /* 61120 */ // Label 1892: @61120
22304 /* 61120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1901*/ GIMT_Encode4(61165), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1561 //
22305 /* 61127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22306 /* 61130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22307 /* 61133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22308 /* 61137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22309 /* 61141 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22310 /* 61145 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4079:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22311 /* 61145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8),
22312 /* 61148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22313 /* 61150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22314 /* 61152 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22315 /* 61154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22316 /* 61157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22317 /* 61163 */ GIR_RootConstrainSelectedInstOperands,
22318 /* 61164 */ // GIR_Coverage, 1561,
22319 /* 61164 */ GIR_EraseRootFromParent_Done,
22320 /* 61165 */ // Label 1901: @61165
22321 /* 61165 */ GIM_Reject,
22322 /* 61166 */ // Label 1893: @61166
22323 /* 61166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1902*/ GIMT_Encode4(61211), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1556 //
22324 /* 61173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22325 /* 61176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22326 /* 61179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22327 /* 61183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22328 /* 61187 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22329 /* 61191 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4079:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22330 /* 61191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16),
22331 /* 61194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22332 /* 61196 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22333 /* 61198 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22334 /* 61200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22335 /* 61203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22336 /* 61209 */ GIR_RootConstrainSelectedInstOperands,
22337 /* 61210 */ // GIR_Coverage, 1556,
22338 /* 61210 */ GIR_EraseRootFromParent_Done,
22339 /* 61211 */ // Label 1902: @61211
22340 /* 61211 */ GIM_Reject,
22341 /* 61212 */ // Label 1894: @61212
22342 /* 61212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1903*/ GIMT_Encode4(61257), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1558 //
22343 /* 61219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22344 /* 61222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22345 /* 61225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22346 /* 61229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22347 /* 61233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22348 /* 61237 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4079:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22349 /* 61237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16),
22350 /* 61240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22351 /* 61242 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22352 /* 61244 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22353 /* 61246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22354 /* 61249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22355 /* 61255 */ GIR_RootConstrainSelectedInstOperands,
22356 /* 61256 */ // GIR_Coverage, 1558,
22357 /* 61256 */ GIR_EraseRootFromParent_Done,
22358 /* 61257 */ // Label 1903: @61257
22359 /* 61257 */ GIM_Reject,
22360 /* 61258 */ // Label 1895: @61258
22361 /* 61258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1904*/ GIMT_Encode4(61303), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1557 //
22362 /* 61265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22363 /* 61268 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22364 /* 61271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22365 /* 61275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22366 /* 61279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22367 /* 61283 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4079:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22368 /* 61283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32),
22369 /* 61286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22370 /* 61288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22371 /* 61290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22372 /* 61292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22373 /* 61295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22374 /* 61301 */ GIR_RootConstrainSelectedInstOperands,
22375 /* 61302 */ // GIR_Coverage, 1557,
22376 /* 61302 */ GIR_EraseRootFromParent_Done,
22377 /* 61303 */ // Label 1904: @61303
22378 /* 61303 */ GIM_Reject,
22379 /* 61304 */ // Label 1896: @61304
22380 /* 61304 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1905*/ GIMT_Encode4(61349), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1559 //
22381 /* 61311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22382 /* 61314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22383 /* 61317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22384 /* 61321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22385 /* 61325 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22386 /* 61329 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4079:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22387 /* 61329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32),
22388 /* 61332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22389 /* 61334 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22390 /* 61336 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22391 /* 61338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22392 /* 61341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22393 /* 61347 */ GIR_RootConstrainSelectedInstOperands,
22394 /* 61348 */ // GIR_Coverage, 1559,
22395 /* 61348 */ GIR_EraseRootFromParent_Done,
22396 /* 61349 */ // Label 1905: @61349
22397 /* 61349 */ GIM_Reject,
22398 /* 61350 */ // Label 1897: @61350
22399 /* 61350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1906*/ GIMT_Encode4(61395), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1563 //
22400 /* 61357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22401 /* 61360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22402 /* 61363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22403 /* 61367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22404 /* 61371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22405 /* 61375 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4079:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22406 /* 61375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64),
22407 /* 61378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22408 /* 61380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22409 /* 61382 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22410 /* 61384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22411 /* 61387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22412 /* 61393 */ GIR_RootConstrainSelectedInstOperands,
22413 /* 61394 */ // GIR_Coverage, 1563,
22414 /* 61394 */ GIR_EraseRootFromParent_Done,
22415 /* 61395 */ // Label 1906: @61395
22416 /* 61395 */ GIM_Reject,
22417 /* 61396 */ // Label 1898: @61396
22418 /* 61396 */ GIM_Reject,
22419 /* 61397 */ // Label 1889: @61397
22420 /* 61397 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(61835),
22421 /* 61402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22422 /* 61407 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1916*/ GIMT_Encode4(61834),
22423 /* 61418 */ /*GILLT_s64*//*Label 1908*/ GIMT_Encode4(61466), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22424 /* 61438 */ /*GILLT_v8s8*//*Label 1909*/ GIMT_Encode4(61512),
22425 /* 61442 */ /*GILLT_v16s8*//*Label 1910*/ GIMT_Encode4(61558),
22426 /* 61446 */ /*GILLT_v4s16*//*Label 1911*/ GIMT_Encode4(61604),
22427 /* 61450 */ /*GILLT_v8s16*//*Label 1912*/ GIMT_Encode4(61650),
22428 /* 61454 */ /*GILLT_v2s32*//*Label 1913*/ GIMT_Encode4(61696),
22429 /* 61458 */ /*GILLT_v4s32*//*Label 1914*/ GIMT_Encode4(61742),
22430 /* 61462 */ /*GILLT_v2s64*//*Label 1915*/ GIMT_Encode4(61788),
22431 /* 61466 */ // Label 1908: @61466
22432 /* 61466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1917*/ GIMT_Encode4(61511), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1603 //
22433 /* 61473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22434 /* 61476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22435 /* 61479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22436 /* 61483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22437 /* 61487 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22438 /* 61491 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4072:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22439 /* 61491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64),
22440 /* 61494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22441 /* 61496 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22442 /* 61498 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22443 /* 61500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22444 /* 61503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22445 /* 61509 */ GIR_RootConstrainSelectedInstOperands,
22446 /* 61510 */ // GIR_Coverage, 1603,
22447 /* 61510 */ GIR_EraseRootFromParent_Done,
22448 /* 61511 */ // Label 1917: @61511
22449 /* 61511 */ GIM_Reject,
22450 /* 61512 */ // Label 1909: @61512
22451 /* 61512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1918*/ GIMT_Encode4(61557), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1601 //
22452 /* 61519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22453 /* 61522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22454 /* 61525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22455 /* 61529 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22456 /* 61533 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22457 /* 61537 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4072:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22458 /* 61537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8),
22459 /* 61540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22460 /* 61542 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22461 /* 61544 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22462 /* 61546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22463 /* 61549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22464 /* 61555 */ GIR_RootConstrainSelectedInstOperands,
22465 /* 61556 */ // GIR_Coverage, 1601,
22466 /* 61556 */ GIR_EraseRootFromParent_Done,
22467 /* 61557 */ // Label 1918: @61557
22468 /* 61557 */ GIM_Reject,
22469 /* 61558 */ // Label 1910: @61558
22470 /* 61558 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1919*/ GIMT_Encode4(61603), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1602 //
22471 /* 61565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22472 /* 61568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22473 /* 61571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22474 /* 61575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22475 /* 61579 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22476 /* 61583 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4072:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22477 /* 61583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8),
22478 /* 61586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22479 /* 61588 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22480 /* 61590 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22481 /* 61592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22482 /* 61595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22483 /* 61601 */ GIR_RootConstrainSelectedInstOperands,
22484 /* 61602 */ // GIR_Coverage, 1602,
22485 /* 61602 */ GIR_EraseRootFromParent_Done,
22486 /* 61603 */ // Label 1919: @61603
22487 /* 61603 */ GIM_Reject,
22488 /* 61604 */ // Label 1911: @61604
22489 /* 61604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1920*/ GIMT_Encode4(61649), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1597 //
22490 /* 61611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22491 /* 61614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22492 /* 61617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22493 /* 61621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22494 /* 61625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22495 /* 61629 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4072:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22496 /* 61629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16),
22497 /* 61632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22498 /* 61634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22499 /* 61636 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22500 /* 61638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22501 /* 61641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22502 /* 61647 */ GIR_RootConstrainSelectedInstOperands,
22503 /* 61648 */ // GIR_Coverage, 1597,
22504 /* 61648 */ GIR_EraseRootFromParent_Done,
22505 /* 61649 */ // Label 1920: @61649
22506 /* 61649 */ GIM_Reject,
22507 /* 61650 */ // Label 1912: @61650
22508 /* 61650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1921*/ GIMT_Encode4(61695), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1599 //
22509 /* 61657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22510 /* 61660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22511 /* 61663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22512 /* 61667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22513 /* 61671 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22514 /* 61675 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4072:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22515 /* 61675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16),
22516 /* 61678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22517 /* 61680 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22518 /* 61682 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22519 /* 61684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22520 /* 61687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22521 /* 61693 */ GIR_RootConstrainSelectedInstOperands,
22522 /* 61694 */ // GIR_Coverage, 1599,
22523 /* 61694 */ GIR_EraseRootFromParent_Done,
22524 /* 61695 */ // Label 1921: @61695
22525 /* 61695 */ GIM_Reject,
22526 /* 61696 */ // Label 1913: @61696
22527 /* 61696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1922*/ GIMT_Encode4(61741), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1598 //
22528 /* 61703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22529 /* 61706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22530 /* 61709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22531 /* 61713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22532 /* 61717 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22533 /* 61721 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4072:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22534 /* 61721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32),
22535 /* 61724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22536 /* 61726 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22537 /* 61728 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22538 /* 61730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22539 /* 61733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22540 /* 61739 */ GIR_RootConstrainSelectedInstOperands,
22541 /* 61740 */ // GIR_Coverage, 1598,
22542 /* 61740 */ GIR_EraseRootFromParent_Done,
22543 /* 61741 */ // Label 1922: @61741
22544 /* 61741 */ GIM_Reject,
22545 /* 61742 */ // Label 1914: @61742
22546 /* 61742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1923*/ GIMT_Encode4(61787), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1600 //
22547 /* 61749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22548 /* 61752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22549 /* 61755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22550 /* 61759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22551 /* 61763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22552 /* 61767 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4072:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22553 /* 61767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32),
22554 /* 61770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22555 /* 61772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22556 /* 61774 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22557 /* 61776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22558 /* 61779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22559 /* 61785 */ GIR_RootConstrainSelectedInstOperands,
22560 /* 61786 */ // GIR_Coverage, 1600,
22561 /* 61786 */ GIR_EraseRootFromParent_Done,
22562 /* 61787 */ // Label 1923: @61787
22563 /* 61787 */ GIM_Reject,
22564 /* 61788 */ // Label 1915: @61788
22565 /* 61788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1924*/ GIMT_Encode4(61833), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1604 //
22566 /* 61795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22567 /* 61798 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22568 /* 61801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22569 /* 61805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22570 /* 61809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22571 /* 61813 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4072:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22572 /* 61813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64),
22573 /* 61816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22574 /* 61818 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22575 /* 61820 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22576 /* 61822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22577 /* 61825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22578 /* 61831 */ GIR_RootConstrainSelectedInstOperands,
22579 /* 61832 */ // GIR_Coverage, 1604,
22580 /* 61832 */ GIR_EraseRootFromParent_Done,
22581 /* 61833 */ // Label 1924: @61833
22582 /* 61833 */ GIM_Reject,
22583 /* 61834 */ // Label 1916: @61834
22584 /* 61834 */ GIM_Reject,
22585 /* 61835 */ // Label 1907: @61835
22586 /* 61835 */ GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(62273),
22587 /* 61840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22588 /* 61845 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1934*/ GIMT_Encode4(62272),
22589 /* 61856 */ /*GILLT_s64*//*Label 1926*/ GIMT_Encode4(61904), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22590 /* 61876 */ /*GILLT_v8s8*//*Label 1927*/ GIMT_Encode4(61950),
22591 /* 61880 */ /*GILLT_v16s8*//*Label 1928*/ GIMT_Encode4(61996),
22592 /* 61884 */ /*GILLT_v4s16*//*Label 1929*/ GIMT_Encode4(62042),
22593 /* 61888 */ /*GILLT_v8s16*//*Label 1930*/ GIMT_Encode4(62088),
22594 /* 61892 */ /*GILLT_v2s32*//*Label 1931*/ GIMT_Encode4(62134),
22595 /* 61896 */ /*GILLT_v4s32*//*Label 1932*/ GIMT_Encode4(62180),
22596 /* 61900 */ /*GILLT_v2s64*//*Label 1933*/ GIMT_Encode4(62226),
22597 /* 61904 */ // Label 1926: @61904
22598 /* 61904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1935*/ GIMT_Encode4(61949), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1611 //
22599 /* 61911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22600 /* 61914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22601 /* 61917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22602 /* 61921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22603 /* 61925 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22604 /* 61929 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4073:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22605 /* 61929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64),
22606 /* 61932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22607 /* 61934 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22608 /* 61936 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22609 /* 61938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22610 /* 61941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22611 /* 61947 */ GIR_RootConstrainSelectedInstOperands,
22612 /* 61948 */ // GIR_Coverage, 1611,
22613 /* 61948 */ GIR_EraseRootFromParent_Done,
22614 /* 61949 */ // Label 1935: @61949
22615 /* 61949 */ GIM_Reject,
22616 /* 61950 */ // Label 1927: @61950
22617 /* 61950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1936*/ GIMT_Encode4(61995), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1609 //
22618 /* 61957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22619 /* 61960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22620 /* 61963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22621 /* 61967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22622 /* 61971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22623 /* 61975 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4073:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22624 /* 61975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8),
22625 /* 61978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22626 /* 61980 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22627 /* 61982 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22628 /* 61984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22629 /* 61987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22630 /* 61993 */ GIR_RootConstrainSelectedInstOperands,
22631 /* 61994 */ // GIR_Coverage, 1609,
22632 /* 61994 */ GIR_EraseRootFromParent_Done,
22633 /* 61995 */ // Label 1936: @61995
22634 /* 61995 */ GIM_Reject,
22635 /* 61996 */ // Label 1928: @61996
22636 /* 61996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1937*/ GIMT_Encode4(62041), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1610 //
22637 /* 62003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22638 /* 62006 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22639 /* 62009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22640 /* 62013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22641 /* 62017 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22642 /* 62021 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4073:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22643 /* 62021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8),
22644 /* 62024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22645 /* 62026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22646 /* 62028 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22647 /* 62030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22648 /* 62033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22649 /* 62039 */ GIR_RootConstrainSelectedInstOperands,
22650 /* 62040 */ // GIR_Coverage, 1610,
22651 /* 62040 */ GIR_EraseRootFromParent_Done,
22652 /* 62041 */ // Label 1937: @62041
22653 /* 62041 */ GIM_Reject,
22654 /* 62042 */ // Label 1929: @62042
22655 /* 62042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1938*/ GIMT_Encode4(62087), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1605 //
22656 /* 62049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22657 /* 62052 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22658 /* 62055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22659 /* 62059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22660 /* 62063 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22661 /* 62067 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4073:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22662 /* 62067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16),
22663 /* 62070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22664 /* 62072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22665 /* 62074 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22666 /* 62076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22667 /* 62079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22668 /* 62085 */ GIR_RootConstrainSelectedInstOperands,
22669 /* 62086 */ // GIR_Coverage, 1605,
22670 /* 62086 */ GIR_EraseRootFromParent_Done,
22671 /* 62087 */ // Label 1938: @62087
22672 /* 62087 */ GIM_Reject,
22673 /* 62088 */ // Label 1930: @62088
22674 /* 62088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1939*/ GIMT_Encode4(62133), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1607 //
22675 /* 62095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22676 /* 62098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22677 /* 62101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22678 /* 62105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22679 /* 62109 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22680 /* 62113 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4073:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22681 /* 62113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16),
22682 /* 62116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22683 /* 62118 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22684 /* 62120 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22685 /* 62122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22686 /* 62125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22687 /* 62131 */ GIR_RootConstrainSelectedInstOperands,
22688 /* 62132 */ // GIR_Coverage, 1607,
22689 /* 62132 */ GIR_EraseRootFromParent_Done,
22690 /* 62133 */ // Label 1939: @62133
22691 /* 62133 */ GIM_Reject,
22692 /* 62134 */ // Label 1931: @62134
22693 /* 62134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1940*/ GIMT_Encode4(62179), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1606 //
22694 /* 62141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22695 /* 62144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22696 /* 62147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22697 /* 62151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22698 /* 62155 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22699 /* 62159 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4073:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22700 /* 62159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32),
22701 /* 62162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22702 /* 62164 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22703 /* 62166 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22704 /* 62168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22705 /* 62171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22706 /* 62177 */ GIR_RootConstrainSelectedInstOperands,
22707 /* 62178 */ // GIR_Coverage, 1606,
22708 /* 62178 */ GIR_EraseRootFromParent_Done,
22709 /* 62179 */ // Label 1940: @62179
22710 /* 62179 */ GIM_Reject,
22711 /* 62180 */ // Label 1932: @62180
22712 /* 62180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1941*/ GIMT_Encode4(62225), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1608 //
22713 /* 62187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22714 /* 62190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22715 /* 62193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22716 /* 62197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22717 /* 62201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22718 /* 62205 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4073:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22719 /* 62205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32),
22720 /* 62208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22721 /* 62210 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22722 /* 62212 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22723 /* 62214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22724 /* 62217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22725 /* 62223 */ GIR_RootConstrainSelectedInstOperands,
22726 /* 62224 */ // GIR_Coverage, 1608,
22727 /* 62224 */ GIR_EraseRootFromParent_Done,
22728 /* 62225 */ // Label 1941: @62225
22729 /* 62225 */ GIM_Reject,
22730 /* 62226 */ // Label 1933: @62226
22731 /* 62226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1942*/ GIMT_Encode4(62271), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1612 //
22732 /* 62233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22733 /* 62236 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22734 /* 62239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22735 /* 62243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22736 /* 62247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22737 /* 62251 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4073:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22738 /* 62251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64),
22739 /* 62254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22740 /* 62256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22741 /* 62258 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22742 /* 62260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22743 /* 62263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22744 /* 62269 */ GIR_RootConstrainSelectedInstOperands,
22745 /* 62270 */ // GIR_Coverage, 1612,
22746 /* 62270 */ GIR_EraseRootFromParent_Done,
22747 /* 62271 */ // Label 1942: @62271
22748 /* 62271 */ GIM_Reject,
22749 /* 62272 */ // Label 1934: @62272
22750 /* 62272 */ GIM_Reject,
22751 /* 62273 */ // Label 1925: @62273
22752 /* 62273 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1943*/ GIMT_Encode4(62317), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1901 //
22753 /* 62280 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd),
22754 /* 62285 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22755 /* 62288 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22756 /* 62291 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22757 /* 62294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22758 /* 62298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22759 /* 62302 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22760 /* 62306 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3974:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
22761 /* 62306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD),
22762 /* 62309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22763 /* 62311 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22764 /* 62313 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22765 /* 62315 */ GIR_RootConstrainSelectedInstOperands,
22766 /* 62316 */ // GIR_Coverage, 1901,
22767 /* 62316 */ GIR_EraseRootFromParent_Done,
22768 /* 62317 */ // Label 1943: @62317
22769 /* 62317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1944*/ GIMT_Encode4(62361), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1902 //
22770 /* 62324 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese),
22771 /* 62329 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22772 /* 62332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22773 /* 62335 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22774 /* 62338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22775 /* 62342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22776 /* 62346 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22777 /* 62350 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3975:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
22778 /* 62350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE),
22779 /* 62353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22780 /* 62355 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22781 /* 62357 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22782 /* 62359 */ GIR_RootConstrainSelectedInstOperands,
22783 /* 62360 */ // GIR_Coverage, 1902,
22784 /* 62360 */ GIR_EraseRootFromParent_Done,
22785 /* 62361 */ // Label 1944: @62361
22786 /* 62361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1945*/ GIMT_Encode4(62405), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1905 //
22787 /* 62368 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1),
22788 /* 62373 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22789 /* 62376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22790 /* 62379 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22791 /* 62382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22792 /* 62386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22793 /* 62390 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22794 /* 62394 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3988:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
22795 /* 62394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1),
22796 /* 62397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22797 /* 62399 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22798 /* 62401 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22799 /* 62403 */ GIR_RootConstrainSelectedInstOperands,
22800 /* 62404 */ // GIR_Coverage, 1905,
22801 /* 62404 */ GIR_EraseRootFromParent_Done,
22802 /* 62405 */ // Label 1945: @62405
22803 /* 62405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1946*/ GIMT_Encode4(62449), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1906 //
22804 /* 62412 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0),
22805 /* 62417 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22806 /* 62420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22807 /* 62423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22808 /* 62426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22809 /* 62430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22810 /* 62434 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22811 /* 62438 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3991:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
22812 /* 62438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0),
22813 /* 62441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22814 /* 62443 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22815 /* 62445 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22816 /* 62447 */ GIR_RootConstrainSelectedInstOperands,
22817 /* 62448 */ // GIR_Coverage, 1906,
22818 /* 62448 */ GIR_EraseRootFromParent_Done,
22819 /* 62449 */ // Label 1946: @62449
22820 /* 62449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1947*/ GIMT_Encode4(62502), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1915 //
22821 /* 62456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr),
22822 /* 62461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22823 /* 62464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22824 /* 62467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22825 /* 62470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22826 /* 62474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22827 /* 62478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22828 /* 62482 */ // (intrinsic_wo_chain:{ *:[i32] } 3824:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
22829 /* 62482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR),
22830 /* 62485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
22831 /* 62487 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
22832 /* 62489 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22833 /* 62491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22834 /* 62494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22835 /* 62500 */ GIR_RootConstrainSelectedInstOperands,
22836 /* 62501 */ // GIR_Coverage, 1915,
22837 /* 62501 */ GIR_EraseRootFromParent_Done,
22838 /* 62502 */ // Label 1947: @62502
22839 /* 62502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1948*/ GIMT_Encode4(62555), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1916 //
22840 /* 62509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl),
22841 /* 62514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22842 /* 62517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22843 /* 62520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22844 /* 62523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22845 /* 62527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22846 /* 62531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22847 /* 62535 */ // (intrinsic_wo_chain:{ *:[i32] } 3831:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
22848 /* 62535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL),
22849 /* 62538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
22850 /* 62540 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
22851 /* 62542 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22852 /* 62544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22853 /* 62547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22854 /* 62553 */ GIR_RootConstrainSelectedInstOperands,
22855 /* 62554 */ // GIR_Coverage, 1916,
22856 /* 62554 */ GIR_EraseRootFromParent_Done,
22857 /* 62555 */ // Label 1948: @62555
22858 /* 62555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1949*/ GIMT_Encode4(62611), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2041 //
22859 /* 62562 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
22860 /* 62567 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22861 /* 62570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22862 /* 62573 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22863 /* 62576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22864 /* 62580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22865 /* 62584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22866 /* 62588 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
22867 /* 62588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16),
22868 /* 62591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22869 /* 62593 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
22870 /* 62595 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
22871 /* 62597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
22872 /* 62600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22873 /* 62603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22874 /* 62609 */ GIR_RootConstrainSelectedInstOperands,
22875 /* 62610 */ // GIR_Coverage, 2041,
22876 /* 62610 */ GIR_EraseRootFromParent_Done,
22877 /* 62611 */ // Label 1949: @62611
22878 /* 62611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1950*/ GIMT_Encode4(62667), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2048 //
22879 /* 62618 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
22880 /* 62623 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22881 /* 62626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22882 /* 62629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22883 /* 62632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22884 /* 62636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22885 /* 62640 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22886 /* 62644 */ // (intrinsic_wo_chain:{ *:[i32] } 4194:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
22887 /* 62644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16),
22888 /* 62647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22889 /* 62649 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
22890 /* 62651 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
22891 /* 62653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
22892 /* 62656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22893 /* 62659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22894 /* 62665 */ GIR_RootConstrainSelectedInstOperands,
22895 /* 62666 */ // GIR_Coverage, 2048,
22896 /* 62666 */ GIR_EraseRootFromParent_Done,
22897 /* 62667 */ // Label 1950: @62667
22898 /* 62667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1951*/ GIMT_Encode4(62720), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2095 //
22899 /* 62674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
22900 /* 62679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22901 /* 62682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22902 /* 62685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22903 /* 62688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22904 /* 62692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22905 /* 62696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22906 /* 62700 */ // (intrinsic_wo_chain:{ *:[i32] } 4145:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22907 /* 62700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD),
22908 /* 62703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22909 /* 62705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22910 /* 62707 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22911 /* 62709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22912 /* 62712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22913 /* 62718 */ GIR_RootConstrainSelectedInstOperands,
22914 /* 62719 */ // GIR_Coverage, 2095,
22915 /* 62719 */ GIR_EraseRootFromParent_Done,
22916 /* 62720 */ // Label 1951: @62720
22917 /* 62720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1952*/ GIMT_Encode4(62773), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2096 //
22918 /* 62727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
22919 /* 62732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22920 /* 62735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22921 /* 62738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22922 /* 62741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22923 /* 62745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22924 /* 62749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22925 /* 62753 */ // (intrinsic_wo_chain:{ *:[i32] } 4146:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22926 /* 62753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX),
22927 /* 62756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22928 /* 62758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22929 /* 62760 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22930 /* 62762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22931 /* 62765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22932 /* 62771 */ GIR_RootConstrainSelectedInstOperands,
22933 /* 62772 */ // GIR_Coverage, 2096,
22934 /* 62772 */ GIR_EraseRootFromParent_Done,
22935 /* 62773 */ // Label 1952: @62773
22936 /* 62773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1953*/ GIMT_Encode4(62826), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2097 //
22937 /* 62780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
22938 /* 62785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22939 /* 62788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22940 /* 62791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22941 /* 62794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22942 /* 62798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22943 /* 62802 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22944 /* 62806 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22945 /* 62806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD),
22946 /* 62809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22947 /* 62811 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22948 /* 62813 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22949 /* 62815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22950 /* 62818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22951 /* 62824 */ GIR_RootConstrainSelectedInstOperands,
22952 /* 62825 */ // GIR_Coverage, 2097,
22953 /* 62825 */ GIR_EraseRootFromParent_Done,
22954 /* 62826 */ // Label 1953: @62826
22955 /* 62826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1954*/ GIMT_Encode4(62879), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2098 //
22956 /* 62833 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
22957 /* 62838 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22958 /* 62841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22959 /* 62844 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22960 /* 62847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22961 /* 62851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22962 /* 62855 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22963 /* 62859 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22964 /* 62859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX),
22965 /* 62862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22966 /* 62864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22967 /* 62866 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22968 /* 62868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22969 /* 62871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22970 /* 62877 */ GIR_RootConstrainSelectedInstOperands,
22971 /* 62878 */ // GIR_Coverage, 2098,
22972 /* 62878 */ GIR_EraseRootFromParent_Done,
22973 /* 62879 */ // Label 1954: @62879
22974 /* 62879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1955*/ GIMT_Encode4(62932), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2179 //
22975 /* 62886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
22976 /* 62891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22977 /* 62894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22978 /* 62897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22979 /* 62900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22980 /* 62904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22981 /* 62908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22982 /* 62912 */ // (intrinsic_wo_chain:{ *:[i32] } 4147:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22983 /* 62912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
22984 /* 62915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22985 /* 62917 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22986 /* 62919 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22987 /* 62921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22988 /* 62924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22989 /* 62930 */ GIR_RootConstrainSelectedInstOperands,
22990 /* 62931 */ // GIR_Coverage, 2179,
22991 /* 62931 */ GIR_EraseRootFromParent_Done,
22992 /* 62932 */ // Label 1955: @62932
22993 /* 62932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1956*/ GIMT_Encode4(62985), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2180 //
22994 /* 62939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
22995 /* 62944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22996 /* 62947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22997 /* 62950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22998 /* 62953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22999 /* 62957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23000 /* 62961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23001 /* 62965 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23002 /* 62965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
23003 /* 62968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23004 /* 62970 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23005 /* 62972 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23006 /* 62974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23007 /* 62977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23008 /* 62983 */ GIR_RootConstrainSelectedInstOperands,
23009 /* 62984 */ // GIR_Coverage, 2180,
23010 /* 62984 */ GIR_EraseRootFromParent_Done,
23011 /* 62985 */ // Label 1956: @62985
23012 /* 62985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1957*/ GIMT_Encode4(63038), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2181 //
23013 /* 62992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23014 /* 62997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23015 /* 63000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23016 /* 63003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23017 /* 63006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23018 /* 63010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23019 /* 63014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23020 /* 63018 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23021 /* 63018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
23022 /* 63021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23023 /* 63023 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23024 /* 63025 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23025 /* 63027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23026 /* 63030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23027 /* 63036 */ GIR_RootConstrainSelectedInstOperands,
23028 /* 63037 */ // GIR_Coverage, 2181,
23029 /* 63037 */ GIR_EraseRootFromParent_Done,
23030 /* 63038 */ // Label 1957: @63038
23031 /* 63038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1958*/ GIMT_Encode4(63091), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2182 //
23032 /* 63045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23033 /* 63050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23034 /* 63053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23035 /* 63056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23036 /* 63059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23037 /* 63063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23038 /* 63067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23039 /* 63071 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23040 /* 63071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
23041 /* 63074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23042 /* 63076 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23043 /* 63078 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23044 /* 63080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23045 /* 63083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23046 /* 63089 */ GIR_RootConstrainSelectedInstOperands,
23047 /* 63090 */ // GIR_Coverage, 2182,
23048 /* 63090 */ GIR_EraseRootFromParent_Done,
23049 /* 63091 */ // Label 1958: @63091
23050 /* 63091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1959*/ GIMT_Encode4(63144), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2183 //
23051 /* 63098 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23052 /* 63103 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23053 /* 63106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23054 /* 63109 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23055 /* 63112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23056 /* 63116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23057 /* 63120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23058 /* 63124 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23059 /* 63124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB),
23060 /* 63127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23061 /* 63129 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23062 /* 63131 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23063 /* 63133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23064 /* 63136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23065 /* 63142 */ GIR_RootConstrainSelectedInstOperands,
23066 /* 63143 */ // GIR_Coverage, 2183,
23067 /* 63143 */ GIR_EraseRootFromParent_Done,
23068 /* 63144 */ // Label 1959: @63144
23069 /* 63144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1960*/ GIMT_Encode4(63197), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2184 //
23070 /* 63151 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23071 /* 63156 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23072 /* 63159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23073 /* 63162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23074 /* 63165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23075 /* 63169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23076 /* 63173 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23077 /* 63177 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23078 /* 63177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT),
23079 /* 63180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23080 /* 63182 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23081 /* 63184 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23082 /* 63186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23083 /* 63189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23084 /* 63195 */ GIR_RootConstrainSelectedInstOperands,
23085 /* 63196 */ // GIR_Coverage, 2184,
23086 /* 63196 */ GIR_EraseRootFromParent_Done,
23087 /* 63197 */ // Label 1960: @63197
23088 /* 63197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1961*/ GIMT_Encode4(63253), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2296 //
23089 /* 63204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23090 /* 63209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23091 /* 63212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23092 /* 63215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23093 /* 63218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23094 /* 63222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23095 /* 63226 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23096 /* 63230 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
23097 /* 63230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16),
23098 /* 63233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23099 /* 63235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23100 /* 63237 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23101 /* 63239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23102 /* 63242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23103 /* 63245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23104 /* 63251 */ GIR_RootConstrainSelectedInstOperands,
23105 /* 63252 */ // GIR_Coverage, 2296,
23106 /* 63252 */ GIR_EraseRootFromParent_Done,
23107 /* 63253 */ // Label 1961: @63253
23108 /* 63253 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1962*/ GIMT_Encode4(63306), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2326 //
23109 /* 63260 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
23110 /* 63265 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23111 /* 63268 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23112 /* 63271 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23113 /* 63274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23114 /* 63278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23115 /* 63282 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23116 /* 63286 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23117 /* 63286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
23118 /* 63289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23119 /* 63291 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
23120 /* 63293 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
23121 /* 63295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23122 /* 63298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23123 /* 63304 */ GIR_RootConstrainSelectedInstOperands,
23124 /* 63305 */ // GIR_Coverage, 2326,
23125 /* 63305 */ GIR_EraseRootFromParent_Done,
23126 /* 63306 */ // Label 1962: @63306
23127 /* 63306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1963*/ GIMT_Encode4(63359), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2327 //
23128 /* 63313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
23129 /* 63318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23130 /* 63321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23131 /* 63324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23132 /* 63327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23133 /* 63331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23134 /* 63335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23135 /* 63339 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23136 /* 63339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
23137 /* 63342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23138 /* 63344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
23139 /* 63346 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
23140 /* 63348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23141 /* 63351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23142 /* 63357 */ GIR_RootConstrainSelectedInstOperands,
23143 /* 63358 */ // GIR_Coverage, 2327,
23144 /* 63358 */ GIR_EraseRootFromParent_Done,
23145 /* 63359 */ // Label 1963: @63359
23146 /* 63359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1964*/ GIMT_Encode4(63412), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2367 //
23147 /* 63366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
23148 /* 63371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23149 /* 63374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23150 /* 63377 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23151 /* 63380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23152 /* 63384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23153 /* 63388 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23154 /* 63392 */ // (intrinsic_wo_chain:{ *:[i32] } 4147:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23155 /* 63392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
23156 /* 63395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23157 /* 63397 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23158 /* 63399 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23159 /* 63401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23160 /* 63404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23161 /* 63410 */ GIR_RootConstrainSelectedInstOperands,
23162 /* 63411 */ // GIR_Coverage, 2367,
23163 /* 63411 */ GIR_EraseRootFromParent_Done,
23164 /* 63412 */ // Label 1964: @63412
23165 /* 63412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1965*/ GIMT_Encode4(63465), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2368 //
23166 /* 63419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
23167 /* 63424 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23168 /* 63427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23169 /* 63430 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23170 /* 63433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23171 /* 63437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23172 /* 63441 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23173 /* 63445 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23174 /* 63445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
23175 /* 63448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23176 /* 63450 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23177 /* 63452 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23178 /* 63454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23179 /* 63457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23180 /* 63463 */ GIR_RootConstrainSelectedInstOperands,
23181 /* 63464 */ // GIR_Coverage, 2368,
23182 /* 63464 */ GIR_EraseRootFromParent_Done,
23183 /* 63465 */ // Label 1965: @63465
23184 /* 63465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1966*/ GIMT_Encode4(63518), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2369 //
23185 /* 63472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23186 /* 63477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23187 /* 63480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23188 /* 63483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23189 /* 63486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23190 /* 63490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23191 /* 63494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23192 /* 63498 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23193 /* 63498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
23194 /* 63501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23195 /* 63503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23196 /* 63505 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23197 /* 63507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23198 /* 63510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23199 /* 63516 */ GIR_RootConstrainSelectedInstOperands,
23200 /* 63517 */ // GIR_Coverage, 2369,
23201 /* 63517 */ GIR_EraseRootFromParent_Done,
23202 /* 63518 */ // Label 1966: @63518
23203 /* 63518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1967*/ GIMT_Encode4(63571), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2370 //
23204 /* 63525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23205 /* 63530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23206 /* 63533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23207 /* 63536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23208 /* 63539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23209 /* 63543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23210 /* 63547 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23211 /* 63551 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23212 /* 63551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
23213 /* 63554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23214 /* 63556 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23215 /* 63558 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23216 /* 63560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23217 /* 63563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23218 /* 63569 */ GIR_RootConstrainSelectedInstOperands,
23219 /* 63570 */ // GIR_Coverage, 2370,
23220 /* 63570 */ GIR_EraseRootFromParent_Done,
23221 /* 63571 */ // Label 1967: @63571
23222 /* 63571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1968*/ GIMT_Encode4(63624), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2371 //
23223 /* 63578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23224 /* 63583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23225 /* 63586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23226 /* 63589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23227 /* 63592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23228 /* 63596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23229 /* 63600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23230 /* 63604 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23231 /* 63604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB),
23232 /* 63607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23233 /* 63609 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23234 /* 63611 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23235 /* 63613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23236 /* 63616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23237 /* 63622 */ GIR_RootConstrainSelectedInstOperands,
23238 /* 63623 */ // GIR_Coverage, 2371,
23239 /* 63623 */ GIR_EraseRootFromParent_Done,
23240 /* 63624 */ // Label 1968: @63624
23241 /* 63624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1969*/ GIMT_Encode4(63677), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2372 //
23242 /* 63631 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23243 /* 63636 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23244 /* 63639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23245 /* 63642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23246 /* 63645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23247 /* 63649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23248 /* 63653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23249 /* 63657 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23250 /* 63657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT),
23251 /* 63660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23252 /* 63662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23253 /* 63664 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23254 /* 63666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23255 /* 63669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23256 /* 63675 */ GIR_RootConstrainSelectedInstOperands,
23257 /* 63676 */ // GIR_Coverage, 2372,
23258 /* 63676 */ GIR_EraseRootFromParent_Done,
23259 /* 63677 */ // Label 1969: @63677
23260 /* 63677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1970*/ GIMT_Encode4(63724), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2902 //
23261 /* 63684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23262 /* 63689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23263 /* 63692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23264 /* 63695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23265 /* 63698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23266 /* 63702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23267 /* 63706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23268 /* 63710 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4005:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
23269 /* 63710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
23270 /* 63713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23271 /* 63715 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23272 /* 63717 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23273 /* 63719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23274 /* 63722 */ GIR_RootConstrainSelectedInstOperands,
23275 /* 63723 */ // GIR_Coverage, 2902,
23276 /* 63723 */ GIR_EraseRootFromParent_Done,
23277 /* 63724 */ // Label 1970: @63724
23278 /* 63724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1971*/ GIMT_Encode4(63771), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2903 //
23279 /* 63731 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23280 /* 63736 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23281 /* 63739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23282 /* 63742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23283 /* 63745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23284 /* 63749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23285 /* 63753 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23286 /* 63757 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4004:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
23287 /* 63757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
23288 /* 63760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23289 /* 63762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23290 /* 63764 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23291 /* 63766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23292 /* 63769 */ GIR_RootConstrainSelectedInstOperands,
23293 /* 63770 */ // GIR_Coverage, 2903,
23294 /* 63770 */ GIR_EraseRootFromParent_Done,
23295 /* 63771 */ // Label 1971: @63771
23296 /* 63771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1972*/ GIMT_Encode4(63818), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2904 //
23297 /* 63778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23298 /* 63783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23299 /* 63786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23300 /* 63789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23301 /* 63792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23302 /* 63796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23303 /* 63800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23304 /* 63804 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4005:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
23305 /* 63804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
23306 /* 63807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23307 /* 63809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23308 /* 63811 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23309 /* 63813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23310 /* 63816 */ GIR_RootConstrainSelectedInstOperands,
23311 /* 63817 */ // GIR_Coverage, 2904,
23312 /* 63817 */ GIR_EraseRootFromParent_Done,
23313 /* 63818 */ // Label 1972: @63818
23314 /* 63818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1973*/ GIMT_Encode4(63865), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2905 //
23315 /* 63825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23316 /* 63830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23317 /* 63833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23318 /* 63836 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23319 /* 63839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23320 /* 63843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23321 /* 63847 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23322 /* 63851 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4004:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
23323 /* 63851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
23324 /* 63854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23325 /* 63856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23326 /* 63858 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23327 /* 63860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23328 /* 63863 */ GIR_RootConstrainSelectedInstOperands,
23329 /* 63864 */ // GIR_Coverage, 2905,
23330 /* 63864 */ GIR_EraseRootFromParent_Done,
23331 /* 63865 */ // Label 1973: @63865
23332 /* 63865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1974*/ GIMT_Encode4(63912), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2906 //
23333 /* 63872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23334 /* 63877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23335 /* 63880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23336 /* 63883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23337 /* 63886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23338 /* 63890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23339 /* 63894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23340 /* 63898 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4005:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
23341 /* 63898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
23342 /* 63901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23343 /* 63903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23344 /* 63905 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23345 /* 63907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23346 /* 63910 */ GIR_RootConstrainSelectedInstOperands,
23347 /* 63911 */ // GIR_Coverage, 2906,
23348 /* 63911 */ GIR_EraseRootFromParent_Done,
23349 /* 63912 */ // Label 1974: @63912
23350 /* 63912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1975*/ GIMT_Encode4(63959), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2907 //
23351 /* 63919 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23352 /* 63924 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23353 /* 63927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23354 /* 63930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23355 /* 63933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23356 /* 63937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23357 /* 63941 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23358 /* 63945 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4004:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
23359 /* 63945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
23360 /* 63948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23361 /* 63950 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23362 /* 63952 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23363 /* 63954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23364 /* 63957 */ GIR_RootConstrainSelectedInstOperands,
23365 /* 63958 */ // GIR_Coverage, 2907,
23366 /* 63958 */ GIR_EraseRootFromParent_Done,
23367 /* 63959 */ // Label 1975: @63959
23368 /* 63959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1976*/ GIMT_Encode4(64006), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2908 //
23369 /* 63966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23370 /* 63971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23371 /* 63974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23372 /* 63977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23373 /* 63980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23374 /* 63984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23375 /* 63988 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23376 /* 63992 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4005:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
23377 /* 63992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
23378 /* 63995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23379 /* 63997 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23380 /* 63999 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23381 /* 64001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23382 /* 64004 */ GIR_RootConstrainSelectedInstOperands,
23383 /* 64005 */ // GIR_Coverage, 2908,
23384 /* 64005 */ GIR_EraseRootFromParent_Done,
23385 /* 64006 */ // Label 1976: @64006
23386 /* 64006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1977*/ GIMT_Encode4(64053), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2909 //
23387 /* 64013 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23388 /* 64018 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23389 /* 64021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23390 /* 64024 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23391 /* 64027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23392 /* 64031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23393 /* 64035 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23394 /* 64039 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4004:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
23395 /* 64039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
23396 /* 64042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23397 /* 64044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23398 /* 64046 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23399 /* 64048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23400 /* 64051 */ GIR_RootConstrainSelectedInstOperands,
23401 /* 64052 */ // GIR_Coverage, 2909,
23402 /* 64052 */ GIR_EraseRootFromParent_Done,
23403 /* 64053 */ // Label 1977: @64053
23404 /* 64053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1978*/ GIMT_Encode4(64127), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3420 //
23405 /* 64060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
23406 /* 64065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23407 /* 64068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23408 /* 64071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23409 /* 64074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23410 /* 64078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23411 /* 64082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23412 /* 64086 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
23413 /* 64086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23414 /* 64089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23415 /* 64093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23416 /* 64098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
23417 /* 64101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23418 /* 64103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23419 /* 64105 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23420 /* 64107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23421 /* 64110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23422 /* 64116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23423 /* 64122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23424 /* 64125 */ GIR_RootConstrainSelectedInstOperands,
23425 /* 64126 */ // GIR_Coverage, 3420,
23426 /* 64126 */ GIR_EraseRootFromParent_Done,
23427 /* 64127 */ // Label 1978: @64127
23428 /* 64127 */ GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(64351),
23429 /* 64132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
23430 /* 64137 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1982*/ GIMT_Encode4(64350),
23431 /* 64148 */ /*GILLT_s16*//*Label 1980*/ GIMT_Encode4(64156),
23432 /* 64152 */ /*GILLT_s32*//*Label 1981*/ GIMT_Encode4(64253),
23433 /* 64156 */ // Label 1980: @64156
23434 /* 64156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1983*/ GIMT_Encode4(64252), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3498 //
23435 /* 64163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23436 /* 64166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23437 /* 64169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23438 /* 64173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23439 /* 64177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23440 /* 64181 */ // (intrinsic_wo_chain:{ *:[f16] } 3800:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23441 /* 64181 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23442 /* 64184 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23443 /* 64188 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23444 /* 64193 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23445 /* 64197 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23446 /* 64202 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23447 /* 64205 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16),
23448 /* 64209 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23449 /* 64214 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23450 /* 64217 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23451 /* 64221 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23452 /* 64224 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23453 /* 64230 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23454 /* 64236 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23455 /* 64238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23456 /* 64241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23457 /* 64243 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23458 /* 64246 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23459 /* 64251 */ // GIR_Coverage, 3498,
23460 /* 64251 */ GIR_EraseRootFromParent_Done,
23461 /* 64252 */ // Label 1983: @64252
23462 /* 64252 */ GIM_Reject,
23463 /* 64253 */ // Label 1981: @64253
23464 /* 64253 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1984*/ GIMT_Encode4(64349), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3496 //
23465 /* 64260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23466 /* 64263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23467 /* 64266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23468 /* 64270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23469 /* 64274 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23470 /* 64278 */ // (intrinsic_wo_chain:{ *:[f32] } 3800:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23471 /* 64278 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23472 /* 64281 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23473 /* 64285 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23474 /* 64290 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23475 /* 64294 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23476 /* 64299 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23477 /* 64302 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32),
23478 /* 64306 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23479 /* 64311 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23480 /* 64314 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23481 /* 64318 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23482 /* 64321 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23483 /* 64327 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23484 /* 64333 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23485 /* 64335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23486 /* 64338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23487 /* 64340 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23488 /* 64343 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23489 /* 64348 */ // GIR_Coverage, 3496,
23490 /* 64348 */ GIR_EraseRootFromParent_Done,
23491 /* 64349 */ // Label 1984: @64349
23492 /* 64349 */ GIM_Reject,
23493 /* 64350 */ // Label 1982: @64350
23494 /* 64350 */ GIM_Reject,
23495 /* 64351 */ // Label 1979: @64351
23496 /* 64351 */ GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(64575),
23497 /* 64356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
23498 /* 64361 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1988*/ GIMT_Encode4(64574),
23499 /* 64372 */ /*GILLT_s16*//*Label 1986*/ GIMT_Encode4(64380),
23500 /* 64376 */ /*GILLT_s32*//*Label 1987*/ GIMT_Encode4(64477),
23501 /* 64380 */ // Label 1986: @64380
23502 /* 64380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1989*/ GIMT_Encode4(64476), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3502 //
23503 /* 64387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23504 /* 64390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23505 /* 64393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23506 /* 64397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23507 /* 64401 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23508 /* 64405 */ // (intrinsic_wo_chain:{ *:[f16] } 3791:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23509 /* 64405 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23510 /* 64408 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23511 /* 64412 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23512 /* 64417 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23513 /* 64421 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23514 /* 64426 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23515 /* 64429 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16),
23516 /* 64433 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23517 /* 64438 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23518 /* 64441 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23519 /* 64445 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23520 /* 64448 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23521 /* 64454 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23522 /* 64460 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23523 /* 64462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23524 /* 64465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23525 /* 64467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23526 /* 64470 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23527 /* 64475 */ // GIR_Coverage, 3502,
23528 /* 64475 */ GIR_EraseRootFromParent_Done,
23529 /* 64476 */ // Label 1989: @64476
23530 /* 64476 */ GIM_Reject,
23531 /* 64477 */ // Label 1987: @64477
23532 /* 64477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1990*/ GIMT_Encode4(64573), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3500 //
23533 /* 64484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23534 /* 64487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23535 /* 64490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23536 /* 64494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23537 /* 64498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23538 /* 64502 */ // (intrinsic_wo_chain:{ *:[f32] } 3791:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23539 /* 64502 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23540 /* 64505 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23541 /* 64509 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23542 /* 64514 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23543 /* 64518 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23544 /* 64523 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23545 /* 64526 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32),
23546 /* 64530 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23547 /* 64535 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23548 /* 64538 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23549 /* 64542 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23550 /* 64545 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23551 /* 64551 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23552 /* 64557 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23553 /* 64559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23554 /* 64562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23555 /* 64564 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23556 /* 64567 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23557 /* 64572 */ // GIR_Coverage, 3500,
23558 /* 64572 */ GIR_EraseRootFromParent_Done,
23559 /* 64573 */ // Label 1990: @64573
23560 /* 64573 */ GIM_Reject,
23561 /* 64574 */ // Label 1988: @64574
23562 /* 64574 */ GIM_Reject,
23563 /* 64575 */ // Label 1985: @64575
23564 /* 64575 */ GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(64799),
23565 /* 64580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
23566 /* 64585 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1994*/ GIMT_Encode4(64798),
23567 /* 64596 */ /*GILLT_s16*//*Label 1992*/ GIMT_Encode4(64604),
23568 /* 64600 */ /*GILLT_s32*//*Label 1993*/ GIMT_Encode4(64701),
23569 /* 64604 */ // Label 1992: @64604
23570 /* 64604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1995*/ GIMT_Encode4(64700), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3506 //
23571 /* 64611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23572 /* 64614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23573 /* 64617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23574 /* 64621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23575 /* 64625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23576 /* 64629 */ // (intrinsic_wo_chain:{ *:[f16] } 3798:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23577 /* 64629 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23578 /* 64632 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23579 /* 64636 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23580 /* 64641 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23581 /* 64645 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23582 /* 64650 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23583 /* 64653 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16),
23584 /* 64657 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23585 /* 64662 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23586 /* 64665 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23587 /* 64669 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23588 /* 64672 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23589 /* 64678 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23590 /* 64684 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23591 /* 64686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23592 /* 64689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23593 /* 64691 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23594 /* 64694 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23595 /* 64699 */ // GIR_Coverage, 3506,
23596 /* 64699 */ GIR_EraseRootFromParent_Done,
23597 /* 64700 */ // Label 1995: @64700
23598 /* 64700 */ GIM_Reject,
23599 /* 64701 */ // Label 1993: @64701
23600 /* 64701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1996*/ GIMT_Encode4(64797), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3504 //
23601 /* 64708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23602 /* 64711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23603 /* 64714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23604 /* 64718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23605 /* 64722 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23606 /* 64726 */ // (intrinsic_wo_chain:{ *:[f32] } 3798:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23607 /* 64726 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23608 /* 64729 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23609 /* 64733 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23610 /* 64738 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23611 /* 64742 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23612 /* 64747 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23613 /* 64750 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32),
23614 /* 64754 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23615 /* 64759 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23616 /* 64762 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23617 /* 64766 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23618 /* 64769 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23619 /* 64775 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23620 /* 64781 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23621 /* 64783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23622 /* 64786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23623 /* 64788 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23624 /* 64791 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23625 /* 64796 */ // GIR_Coverage, 3504,
23626 /* 64796 */ GIR_EraseRootFromParent_Done,
23627 /* 64797 */ // Label 1996: @64797
23628 /* 64797 */ GIM_Reject,
23629 /* 64798 */ // Label 1994: @64798
23630 /* 64798 */ GIM_Reject,
23631 /* 64799 */ // Label 1991: @64799
23632 /* 64799 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(65023),
23633 /* 64804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
23634 /* 64809 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 2000*/ GIMT_Encode4(65022),
23635 /* 64820 */ /*GILLT_s16*//*Label 1998*/ GIMT_Encode4(64828),
23636 /* 64824 */ /*GILLT_s32*//*Label 1999*/ GIMT_Encode4(64925),
23637 /* 64828 */ // Label 1998: @64828
23638 /* 64828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2001*/ GIMT_Encode4(64924), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3510 //
23639 /* 64835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23640 /* 64838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23641 /* 64841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23642 /* 64845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23643 /* 64849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23644 /* 64853 */ // (intrinsic_wo_chain:{ *:[f16] } 3789:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23645 /* 64853 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23646 /* 64856 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23647 /* 64860 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23648 /* 64865 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23649 /* 64869 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23650 /* 64874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23651 /* 64877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16),
23652 /* 64881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23653 /* 64886 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23654 /* 64889 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23655 /* 64893 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23656 /* 64896 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23657 /* 64902 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23658 /* 64908 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23659 /* 64910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23660 /* 64913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23661 /* 64915 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23662 /* 64918 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23663 /* 64923 */ // GIR_Coverage, 3510,
23664 /* 64923 */ GIR_EraseRootFromParent_Done,
23665 /* 64924 */ // Label 2001: @64924
23666 /* 64924 */ GIM_Reject,
23667 /* 64925 */ // Label 1999: @64925
23668 /* 64925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2002*/ GIMT_Encode4(65021), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3508 //
23669 /* 64932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23670 /* 64935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23671 /* 64938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23672 /* 64942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23673 /* 64946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23674 /* 64950 */ // (intrinsic_wo_chain:{ *:[f32] } 3789:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23675 /* 64950 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23676 /* 64953 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23677 /* 64957 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23678 /* 64962 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23679 /* 64966 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23680 /* 64971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23681 /* 64974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32),
23682 /* 64978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23683 /* 64983 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23684 /* 64986 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23685 /* 64990 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23686 /* 64993 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23687 /* 64999 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23688 /* 65005 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23689 /* 65007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23690 /* 65010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23691 /* 65012 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23692 /* 65015 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23693 /* 65020 */ // GIR_Coverage, 3508,
23694 /* 65020 */ GIR_EraseRootFromParent_Done,
23695 /* 65021 */ // Label 2002: @65021
23696 /* 65021 */ GIM_Reject,
23697 /* 65022 */ // Label 2000: @65022
23698 /* 65022 */ GIM_Reject,
23699 /* 65023 */ // Label 1997: @65023
23700 /* 65023 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(65209),
23701 /* 65028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
23702 /* 65033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23703 /* 65036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23704 /* 65039 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2007*/ GIMT_Encode4(65208),
23705 /* 65050 */ /*GILLT_v16s8*//*Label 2004*/ GIMT_Encode4(65070), GIMT_Encode4(0),
23706 /* 65058 */ /*GILLT_v8s16*//*Label 2005*/ GIMT_Encode4(65116), GIMT_Encode4(0),
23707 /* 65066 */ /*GILLT_v4s32*//*Label 2006*/ GIMT_Encode4(65162),
23708 /* 65070 */ // Label 2004: @65070
23709 /* 65070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2008*/ GIMT_Encode4(65115), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3560 //
23710 /* 65077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23711 /* 65081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23712 /* 65085 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23713 /* 65089 */ // (intrinsic_wo_chain:{ *:[i32] } 3796:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
23714 /* 65089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8),
23715 /* 65092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23716 /* 65094 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23717 /* 65096 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23718 /* 65098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23719 /* 65101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23720 /* 65107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23721 /* 65113 */ GIR_RootConstrainSelectedInstOperands,
23722 /* 65114 */ // GIR_Coverage, 3560,
23723 /* 65114 */ GIR_EraseRootFromParent_Done,
23724 /* 65115 */ // Label 2008: @65115
23725 /* 65115 */ GIM_Reject,
23726 /* 65116 */ // Label 2005: @65116
23727 /* 65116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2009*/ GIMT_Encode4(65161), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3562 //
23728 /* 65123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23729 /* 65127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23730 /* 65131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23731 /* 65135 */ // (intrinsic_wo_chain:{ *:[i32] } 3796:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
23732 /* 65135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16),
23733 /* 65138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23734 /* 65140 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23735 /* 65142 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23736 /* 65144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23737 /* 65147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23738 /* 65153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23739 /* 65159 */ GIR_RootConstrainSelectedInstOperands,
23740 /* 65160 */ // GIR_Coverage, 3562,
23741 /* 65160 */ GIR_EraseRootFromParent_Done,
23742 /* 65161 */ // Label 2009: @65161
23743 /* 65161 */ GIM_Reject,
23744 /* 65162 */ // Label 2006: @65162
23745 /* 65162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2010*/ GIMT_Encode4(65207), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3564 //
23746 /* 65169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23747 /* 65173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23748 /* 65177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23749 /* 65181 */ // (intrinsic_wo_chain:{ *:[i32] } 3796:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
23750 /* 65181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32),
23751 /* 65184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23752 /* 65186 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23753 /* 65188 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23754 /* 65190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23755 /* 65193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23756 /* 65199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23757 /* 65205 */ GIR_RootConstrainSelectedInstOperands,
23758 /* 65206 */ // GIR_Coverage, 3564,
23759 /* 65206 */ GIR_EraseRootFromParent_Done,
23760 /* 65207 */ // Label 2010: @65207
23761 /* 65207 */ GIM_Reject,
23762 /* 65208 */ // Label 2007: @65208
23763 /* 65208 */ GIM_Reject,
23764 /* 65209 */ // Label 2003: @65209
23765 /* 65209 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(65395),
23766 /* 65214 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
23767 /* 65219 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23768 /* 65222 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23769 /* 65225 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2015*/ GIMT_Encode4(65394),
23770 /* 65236 */ /*GILLT_v16s8*//*Label 2012*/ GIMT_Encode4(65256), GIMT_Encode4(0),
23771 /* 65244 */ /*GILLT_v8s16*//*Label 2013*/ GIMT_Encode4(65302), GIMT_Encode4(0),
23772 /* 65252 */ /*GILLT_v4s32*//*Label 2014*/ GIMT_Encode4(65348),
23773 /* 65256 */ // Label 2012: @65256
23774 /* 65256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2016*/ GIMT_Encode4(65301), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3566 //
23775 /* 65263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23776 /* 65267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23777 /* 65271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23778 /* 65275 */ // (intrinsic_wo_chain:{ *:[i32] } 3787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
23779 /* 65275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8),
23780 /* 65278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23781 /* 65280 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23782 /* 65282 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23783 /* 65284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23784 /* 65287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23785 /* 65293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23786 /* 65299 */ GIR_RootConstrainSelectedInstOperands,
23787 /* 65300 */ // GIR_Coverage, 3566,
23788 /* 65300 */ GIR_EraseRootFromParent_Done,
23789 /* 65301 */ // Label 2016: @65301
23790 /* 65301 */ GIM_Reject,
23791 /* 65302 */ // Label 2013: @65302
23792 /* 65302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2017*/ GIMT_Encode4(65347), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3568 //
23793 /* 65309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23794 /* 65313 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23795 /* 65317 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23796 /* 65321 */ // (intrinsic_wo_chain:{ *:[i32] } 3787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
23797 /* 65321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16),
23798 /* 65324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23799 /* 65326 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23800 /* 65328 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23801 /* 65330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23802 /* 65333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23803 /* 65339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23804 /* 65345 */ GIR_RootConstrainSelectedInstOperands,
23805 /* 65346 */ // GIR_Coverage, 3568,
23806 /* 65346 */ GIR_EraseRootFromParent_Done,
23807 /* 65347 */ // Label 2017: @65347
23808 /* 65347 */ GIM_Reject,
23809 /* 65348 */ // Label 2014: @65348
23810 /* 65348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2018*/ GIMT_Encode4(65393), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3570 //
23811 /* 65355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23812 /* 65359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23813 /* 65363 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23814 /* 65367 */ // (intrinsic_wo_chain:{ *:[i32] } 3787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
23815 /* 65367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32),
23816 /* 65370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23817 /* 65372 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23818 /* 65374 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23819 /* 65376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23820 /* 65379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23821 /* 65385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23822 /* 65391 */ GIR_RootConstrainSelectedInstOperands,
23823 /* 65392 */ // GIR_Coverage, 3570,
23824 /* 65392 */ GIR_EraseRootFromParent_Done,
23825 /* 65393 */ // Label 2018: @65393
23826 /* 65393 */ GIM_Reject,
23827 /* 65394 */ // Label 2015: @65394
23828 /* 65394 */ GIM_Reject,
23829 /* 65395 */ // Label 2011: @65395
23830 /* 65395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2019*/ GIMT_Encode4(65469), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3677 //
23831 /* 65402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
23832 /* 65407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23833 /* 65410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23834 /* 65413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23835 /* 65416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23836 /* 65420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23837 /* 65424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23838 /* 65428 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
23839 /* 65428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23840 /* 65431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23841 /* 65435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23842 /* 65440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
23843 /* 65443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23844 /* 65445 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23845 /* 65447 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23846 /* 65449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23847 /* 65452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23848 /* 65458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23849 /* 65464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23850 /* 65467 */ GIR_RootConstrainSelectedInstOperands,
23851 /* 65468 */ // GIR_Coverage, 3677,
23852 /* 65468 */ GIR_EraseRootFromParent_Done,
23853 /* 65469 */ // Label 2019: @65469
23854 /* 65469 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(65637),
23855 /* 65474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
23856 /* 65479 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2023*/ GIMT_Encode4(65636),
23857 /* 65490 */ /*GILLT_v8s16*//*Label 2021*/ GIMT_Encode4(65502), GIMT_Encode4(0),
23858 /* 65498 */ /*GILLT_v4s32*//*Label 2022*/ GIMT_Encode4(65569),
23859 /* 65502 */ // Label 2021: @65502
23860 /* 65502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2024*/ GIMT_Encode4(65568), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3687 //
23861 /* 65509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23862 /* 65512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23863 /* 65515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23864 /* 65519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23865 /* 65523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23866 /* 65527 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3895:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
23867 /* 65527 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23868 /* 65530 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23869 /* 65534 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23870 /* 65539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
23871 /* 65542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23872 /* 65544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23873 /* 65546 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23874 /* 65548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23875 /* 65551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23876 /* 65557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23877 /* 65563 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23878 /* 65566 */ GIR_RootConstrainSelectedInstOperands,
23879 /* 65567 */ // GIR_Coverage, 3687,
23880 /* 65567 */ GIR_EraseRootFromParent_Done,
23881 /* 65568 */ // Label 2024: @65568
23882 /* 65568 */ GIM_Reject,
23883 /* 65569 */ // Label 2022: @65569
23884 /* 65569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2025*/ GIMT_Encode4(65635), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3682 //
23885 /* 65576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23886 /* 65579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23887 /* 65582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23888 /* 65586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23889 /* 65590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23890 /* 65594 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3895:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
23891 /* 65594 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23892 /* 65597 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23893 /* 65601 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23894 /* 65606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
23895 /* 65609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23896 /* 65611 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23897 /* 65613 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23898 /* 65615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23899 /* 65618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23900 /* 65624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23901 /* 65630 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23902 /* 65633 */ GIR_RootConstrainSelectedInstOperands,
23903 /* 65634 */ // GIR_Coverage, 3682,
23904 /* 65634 */ GIR_EraseRootFromParent_Done,
23905 /* 65635 */ // Label 2025: @65635
23906 /* 65635 */ GIM_Reject,
23907 /* 65636 */ // Label 2023: @65636
23908 /* 65636 */ GIM_Reject,
23909 /* 65637 */ // Label 2020: @65637
23910 /* 65637 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(65880),
23911 /* 65642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
23912 /* 65647 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2030*/ GIMT_Encode4(65879),
23913 /* 65658 */ /*GILLT_v16s8*//*Label 2027*/ GIMT_Encode4(65678), GIMT_Encode4(0),
23914 /* 65666 */ /*GILLT_v8s16*//*Label 2028*/ GIMT_Encode4(65745), GIMT_Encode4(0),
23915 /* 65674 */ /*GILLT_v4s32*//*Label 2029*/ GIMT_Encode4(65812),
23916 /* 65678 */ // Label 2027: @65678
23917 /* 65678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2031*/ GIMT_Encode4(65744), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3867 //
23918 /* 65685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23919 /* 65688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23920 /* 65691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23921 /* 65695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23922 /* 65699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23923 /* 65703 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
23924 /* 65703 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23925 /* 65706 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23926 /* 65710 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23927 /* 65715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8),
23928 /* 65718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23929 /* 65720 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23930 /* 65722 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23931 /* 65724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23932 /* 65727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23933 /* 65733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23934 /* 65739 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23935 /* 65742 */ GIR_RootConstrainSelectedInstOperands,
23936 /* 65743 */ // GIR_Coverage, 3867,
23937 /* 65743 */ GIR_EraseRootFromParent_Done,
23938 /* 65744 */ // Label 2031: @65744
23939 /* 65744 */ GIM_Reject,
23940 /* 65745 */ // Label 2028: @65745
23941 /* 65745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2032*/ GIMT_Encode4(65811), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3874 //
23942 /* 65752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23943 /* 65755 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23944 /* 65758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23945 /* 65762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23946 /* 65766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23947 /* 65770 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
23948 /* 65770 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23949 /* 65773 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23950 /* 65777 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23951 /* 65782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16),
23952 /* 65785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23953 /* 65787 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23954 /* 65789 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23955 /* 65791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23956 /* 65794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23957 /* 65800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23958 /* 65806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23959 /* 65809 */ GIR_RootConstrainSelectedInstOperands,
23960 /* 65810 */ // GIR_Coverage, 3874,
23961 /* 65810 */ GIR_EraseRootFromParent_Done,
23962 /* 65811 */ // Label 2032: @65811
23963 /* 65811 */ GIM_Reject,
23964 /* 65812 */ // Label 2029: @65812
23965 /* 65812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2033*/ GIMT_Encode4(65878), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3878 //
23966 /* 65819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23967 /* 65822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23968 /* 65825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23969 /* 65829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23970 /* 65833 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23971 /* 65837 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
23972 /* 65837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23973 /* 65840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23974 /* 65844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23975 /* 65849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32),
23976 /* 65852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23977 /* 65854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23978 /* 65856 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23979 /* 65858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23980 /* 65861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23981 /* 65867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23982 /* 65873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23983 /* 65876 */ GIR_RootConstrainSelectedInstOperands,
23984 /* 65877 */ // GIR_Coverage, 3878,
23985 /* 65877 */ GIR_EraseRootFromParent_Done,
23986 /* 65878 */ // Label 2033: @65878
23987 /* 65878 */ GIM_Reject,
23988 /* 65879 */ // Label 2030: @65879
23989 /* 65879 */ GIM_Reject,
23990 /* 65880 */ // Label 2026: @65880
23991 /* 65880 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(66123),
23992 /* 65885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
23993 /* 65890 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2038*/ GIMT_Encode4(66122),
23994 /* 65901 */ /*GILLT_v16s8*//*Label 2035*/ GIMT_Encode4(65921), GIMT_Encode4(0),
23995 /* 65909 */ /*GILLT_v8s16*//*Label 2036*/ GIMT_Encode4(65988), GIMT_Encode4(0),
23996 /* 65917 */ /*GILLT_v4s32*//*Label 2037*/ GIMT_Encode4(66055),
23997 /* 65921 */ // Label 2035: @65921
23998 /* 65921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2039*/ GIMT_Encode4(65987), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3880 //
23999 /* 65928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24000 /* 65931 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24001 /* 65934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24002 /* 65938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24003 /* 65942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24004 /* 65946 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24005 /* 65946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24006 /* 65949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24007 /* 65953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24008 /* 65958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8),
24009 /* 65961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24010 /* 65963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24011 /* 65965 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24012 /* 65967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24013 /* 65970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24014 /* 65976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24015 /* 65982 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24016 /* 65985 */ GIR_RootConstrainSelectedInstOperands,
24017 /* 65986 */ // GIR_Coverage, 3880,
24018 /* 65986 */ GIR_EraseRootFromParent_Done,
24019 /* 65987 */ // Label 2039: @65987
24020 /* 65987 */ GIM_Reject,
24021 /* 65988 */ // Label 2036: @65988
24022 /* 65988 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2040*/ GIMT_Encode4(66054), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3882 //
24023 /* 65995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24024 /* 65998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24025 /* 66001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24026 /* 66005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24027 /* 66009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24028 /* 66013 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24029 /* 66013 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24030 /* 66016 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24031 /* 66020 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24032 /* 66025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16),
24033 /* 66028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24034 /* 66030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24035 /* 66032 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24036 /* 66034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24037 /* 66037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24038 /* 66043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24039 /* 66049 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24040 /* 66052 */ GIR_RootConstrainSelectedInstOperands,
24041 /* 66053 */ // GIR_Coverage, 3882,
24042 /* 66053 */ GIR_EraseRootFromParent_Done,
24043 /* 66054 */ // Label 2040: @66054
24044 /* 66054 */ GIM_Reject,
24045 /* 66055 */ // Label 2037: @66055
24046 /* 66055 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2041*/ GIMT_Encode4(66121), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3884 //
24047 /* 66062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24048 /* 66065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24049 /* 66068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24050 /* 66072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24051 /* 66076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24052 /* 66080 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3924:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24053 /* 66080 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24054 /* 66083 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24055 /* 66087 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24056 /* 66092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32),
24057 /* 66095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24058 /* 66097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24059 /* 66099 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24060 /* 66101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24061 /* 66104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24062 /* 66110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24063 /* 66116 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24064 /* 66119 */ GIR_RootConstrainSelectedInstOperands,
24065 /* 66120 */ // GIR_Coverage, 3884,
24066 /* 66120 */ GIR_EraseRootFromParent_Done,
24067 /* 66121 */ // Label 2041: @66121
24068 /* 66121 */ GIM_Reject,
24069 /* 66122 */ // Label 2038: @66122
24070 /* 66122 */ GIM_Reject,
24071 /* 66123 */ // Label 2034: @66123
24072 /* 66123 */ GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(66291),
24073 /* 66128 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul),
24074 /* 66133 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2045*/ GIMT_Encode4(66290),
24075 /* 66144 */ /*GILLT_v8s16*//*Label 2043*/ GIMT_Encode4(66156), GIMT_Encode4(0),
24076 /* 66152 */ /*GILLT_v4s32*//*Label 2044*/ GIMT_Encode4(66223),
24077 /* 66156 */ // Label 2043: @66156
24078 /* 66156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2046*/ GIMT_Encode4(66222), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4423 //
24079 /* 66163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24080 /* 66166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24081 /* 66169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24082 /* 66173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24083 /* 66177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24084 /* 66181 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3905:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24085 /* 66181 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24086 /* 66184 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24087 /* 66188 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24088 /* 66193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
24089 /* 66196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24090 /* 66198 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24091 /* 66200 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24092 /* 66202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24093 /* 66205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24094 /* 66211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24095 /* 66217 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24096 /* 66220 */ GIR_RootConstrainSelectedInstOperands,
24097 /* 66221 */ // GIR_Coverage, 4423,
24098 /* 66221 */ GIR_EraseRootFromParent_Done,
24099 /* 66222 */ // Label 2046: @66222
24100 /* 66222 */ GIM_Reject,
24101 /* 66223 */ // Label 2044: @66223
24102 /* 66223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2047*/ GIMT_Encode4(66289), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4416 //
24103 /* 66230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24104 /* 66233 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24105 /* 66236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24106 /* 66240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24107 /* 66244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24108 /* 66248 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3905:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24109 /* 66248 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24110 /* 66251 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24111 /* 66255 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24112 /* 66260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
24113 /* 66263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24114 /* 66265 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24115 /* 66267 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24116 /* 66269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24117 /* 66272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24118 /* 66278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24119 /* 66284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24120 /* 66287 */ GIR_RootConstrainSelectedInstOperands,
24121 /* 66288 */ // GIR_Coverage, 4416,
24122 /* 66288 */ GIR_EraseRootFromParent_Done,
24123 /* 66289 */ // Label 2047: @66289
24124 /* 66289 */ GIM_Reject,
24125 /* 66290 */ // Label 2045: @66290
24126 /* 66290 */ GIM_Reject,
24127 /* 66291 */ // Label 2042: @66291
24128 /* 66291 */ GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(66459),
24129 /* 66296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd),
24130 /* 66301 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2051*/ GIMT_Encode4(66458),
24131 /* 66312 */ /*GILLT_v8s16*//*Label 2049*/ GIMT_Encode4(66324), GIMT_Encode4(0),
24132 /* 66320 */ /*GILLT_v4s32*//*Label 2050*/ GIMT_Encode4(66391),
24133 /* 66324 */ // Label 2049: @66324
24134 /* 66324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2052*/ GIMT_Encode4(66390), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4463 //
24135 /* 66331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24136 /* 66334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24137 /* 66337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24138 /* 66341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24139 /* 66345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24140 /* 66349 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3842:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24141 /* 66349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24142 /* 66352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24143 /* 66356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24144 /* 66361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
24145 /* 66364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24146 /* 66366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24147 /* 66368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24148 /* 66370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24149 /* 66373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24150 /* 66379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24151 /* 66385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24152 /* 66388 */ GIR_RootConstrainSelectedInstOperands,
24153 /* 66389 */ // GIR_Coverage, 4463,
24154 /* 66389 */ GIR_EraseRootFromParent_Done,
24155 /* 66390 */ // Label 2052: @66390
24156 /* 66390 */ GIM_Reject,
24157 /* 66391 */ // Label 2050: @66391
24158 /* 66391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2053*/ GIMT_Encode4(66457), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4456 //
24159 /* 66398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24160 /* 66401 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24161 /* 66404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24162 /* 66408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24163 /* 66412 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24164 /* 66416 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3842:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24165 /* 66416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24166 /* 66419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24167 /* 66423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24168 /* 66428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
24169 /* 66431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24170 /* 66433 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24171 /* 66435 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24172 /* 66437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24173 /* 66440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24174 /* 66446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24175 /* 66452 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24176 /* 66455 */ GIR_RootConstrainSelectedInstOperands,
24177 /* 66456 */ // GIR_Coverage, 4456,
24178 /* 66456 */ GIR_EraseRootFromParent_Done,
24179 /* 66457 */ // Label 2053: @66457
24180 /* 66457 */ GIM_Reject,
24181 /* 66458 */ // Label 2051: @66458
24182 /* 66458 */ GIM_Reject,
24183 /* 66459 */ // Label 2048: @66459
24184 /* 66459 */ GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(66627),
24185 /* 66464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub),
24186 /* 66469 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2057*/ GIMT_Encode4(66626),
24187 /* 66480 */ /*GILLT_v8s16*//*Label 2055*/ GIMT_Encode4(66492), GIMT_Encode4(0),
24188 /* 66488 */ /*GILLT_v4s32*//*Label 2056*/ GIMT_Encode4(66559),
24189 /* 66492 */ // Label 2055: @66492
24190 /* 66492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2058*/ GIMT_Encode4(66558), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4477 //
24191 /* 66499 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24192 /* 66502 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24193 /* 66505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24194 /* 66509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24195 /* 66513 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24196 /* 66517 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3973:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24197 /* 66517 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24198 /* 66520 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24199 /* 66524 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24200 /* 66529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
24201 /* 66532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24202 /* 66534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24203 /* 66536 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24204 /* 66538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24205 /* 66541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24206 /* 66547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24207 /* 66553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24208 /* 66556 */ GIR_RootConstrainSelectedInstOperands,
24209 /* 66557 */ // GIR_Coverage, 4477,
24210 /* 66557 */ GIR_EraseRootFromParent_Done,
24211 /* 66558 */ // Label 2058: @66558
24212 /* 66558 */ GIM_Reject,
24213 /* 66559 */ // Label 2056: @66559
24214 /* 66559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2059*/ GIMT_Encode4(66625), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4470 //
24215 /* 66566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24216 /* 66569 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24217 /* 66572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24218 /* 66576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24219 /* 66580 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24220 /* 66584 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3973:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24221 /* 66584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24222 /* 66587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24223 /* 66591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24224 /* 66596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
24225 /* 66599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24226 /* 66601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24227 /* 66603 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24228 /* 66605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24229 /* 66608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24230 /* 66614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24231 /* 66620 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24232 /* 66623 */ GIR_RootConstrainSelectedInstOperands,
24233 /* 66624 */ // GIR_Coverage, 4470,
24234 /* 66624 */ GIR_EraseRootFromParent_Done,
24235 /* 66625 */ // Label 2059: @66625
24236 /* 66625 */ GIM_Reject,
24237 /* 66626 */ // Label 2057: @66626
24238 /* 66626 */ GIM_Reject,
24239 /* 66627 */ // Label 2054: @66627
24240 /* 66627 */ GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(66767),
24241 /* 66632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq),
24242 /* 66637 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2063*/ GIMT_Encode4(66766),
24243 /* 66648 */ /*GILLT_v4s1*//*Label 2061*/ GIMT_Encode4(66656),
24244 /* 66652 */ /*GILLT_v8s1*//*Label 2062*/ GIMT_Encode4(66711),
24245 /* 66656 */ // Label 2061: @66656
24246 /* 66656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2064*/ GIMT_Encode4(66710), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4603 //
24247 /* 66663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24248 /* 66666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24249 /* 66669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24250 /* 66673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24251 /* 66677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24252 /* 66681 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3774:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 0:{ *:[i32] })
24253 /* 66681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24254 /* 66684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24255 /* 66686 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24256 /* 66688 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24257 /* 66690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24258 /* 66693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24259 /* 66696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24260 /* 66702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24261 /* 66708 */ GIR_RootConstrainSelectedInstOperands,
24262 /* 66709 */ // GIR_Coverage, 4603,
24263 /* 66709 */ GIR_EraseRootFromParent_Done,
24264 /* 66710 */ // Label 2064: @66710
24265 /* 66710 */ GIM_Reject,
24266 /* 66711 */ // Label 2062: @66711
24267 /* 66711 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2065*/ GIMT_Encode4(66765), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4601 //
24268 /* 66718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24269 /* 66721 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24270 /* 66724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24271 /* 66728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24272 /* 66732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24273 /* 66736 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3774:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 0:{ *:[i32] })
24274 /* 66736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24275 /* 66739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24276 /* 66741 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24277 /* 66743 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24278 /* 66745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24279 /* 66748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24280 /* 66751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24281 /* 66757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24282 /* 66763 */ GIR_RootConstrainSelectedInstOperands,
24283 /* 66764 */ // GIR_Coverage, 4601,
24284 /* 66764 */ GIR_EraseRootFromParent_Done,
24285 /* 66765 */ // Label 2065: @66765
24286 /* 66765 */ GIM_Reject,
24287 /* 66766 */ // Label 2063: @66766
24288 /* 66766 */ GIM_Reject,
24289 /* 66767 */ // Label 2060: @66767
24290 /* 66767 */ GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(66907),
24291 /* 66772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne),
24292 /* 66777 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2069*/ GIMT_Encode4(66906),
24293 /* 66788 */ /*GILLT_v4s1*//*Label 2067*/ GIMT_Encode4(66796),
24294 /* 66792 */ /*GILLT_v8s1*//*Label 2068*/ GIMT_Encode4(66851),
24295 /* 66796 */ // Label 2067: @66796
24296 /* 66796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2070*/ GIMT_Encode4(66850), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4692 //
24297 /* 66803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24298 /* 66806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24299 /* 66809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24300 /* 66813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24301 /* 66817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24302 /* 66821 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3779:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 1:{ *:[i32] })
24303 /* 66821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24304 /* 66824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24305 /* 66826 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24306 /* 66828 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24307 /* 66830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24308 /* 66833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24309 /* 66836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24310 /* 66842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24311 /* 66848 */ GIR_RootConstrainSelectedInstOperands,
24312 /* 66849 */ // GIR_Coverage, 4692,
24313 /* 66849 */ GIR_EraseRootFromParent_Done,
24314 /* 66850 */ // Label 2070: @66850
24315 /* 66850 */ GIM_Reject,
24316 /* 66851 */ // Label 2068: @66851
24317 /* 66851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2071*/ GIMT_Encode4(66905), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4690 //
24318 /* 66858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24319 /* 66861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24320 /* 66864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24321 /* 66868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24322 /* 66872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24323 /* 66876 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3779:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 1:{ *:[i32] })
24324 /* 66876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24325 /* 66879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24326 /* 66881 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24327 /* 66883 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24328 /* 66885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24329 /* 66888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24330 /* 66891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24331 /* 66897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24332 /* 66903 */ GIR_RootConstrainSelectedInstOperands,
24333 /* 66904 */ // GIR_Coverage, 4690,
24334 /* 66904 */ GIR_EraseRootFromParent_Done,
24335 /* 66905 */ // Label 2071: @66905
24336 /* 66905 */ GIM_Reject,
24337 /* 66906 */ // Label 2069: @66906
24338 /* 66906 */ GIM_Reject,
24339 /* 66907 */ // Label 2066: @66907
24340 /* 66907 */ GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(67047),
24341 /* 66912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge),
24342 /* 66917 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2075*/ GIMT_Encode4(67046),
24343 /* 66928 */ /*GILLT_v4s1*//*Label 2073*/ GIMT_Encode4(66936),
24344 /* 66932 */ /*GILLT_v8s1*//*Label 2074*/ GIMT_Encode4(66991),
24345 /* 66936 */ // Label 2073: @66936
24346 /* 66936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2076*/ GIMT_Encode4(66990), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4708 //
24347 /* 66943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24348 /* 66946 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24349 /* 66949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24350 /* 66953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24351 /* 66957 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24352 /* 66961 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3775:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 10:{ *:[i32] })
24353 /* 66961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24354 /* 66964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24355 /* 66966 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24356 /* 66968 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24357 /* 66970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
24358 /* 66973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24359 /* 66976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24360 /* 66982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24361 /* 66988 */ GIR_RootConstrainSelectedInstOperands,
24362 /* 66989 */ // GIR_Coverage, 4708,
24363 /* 66989 */ GIR_EraseRootFromParent_Done,
24364 /* 66990 */ // Label 2076: @66990
24365 /* 66990 */ GIM_Reject,
24366 /* 66991 */ // Label 2074: @66991
24367 /* 66991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2077*/ GIMT_Encode4(67045), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4706 //
24368 /* 66998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24369 /* 67001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24370 /* 67004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24371 /* 67008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24372 /* 67012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24373 /* 67016 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3775:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 10:{ *:[i32] })
24374 /* 67016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24375 /* 67019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24376 /* 67021 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24377 /* 67023 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24378 /* 67025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
24379 /* 67028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24380 /* 67031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24381 /* 67037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24382 /* 67043 */ GIR_RootConstrainSelectedInstOperands,
24383 /* 67044 */ // GIR_Coverage, 4706,
24384 /* 67044 */ GIR_EraseRootFromParent_Done,
24385 /* 67045 */ // Label 2077: @67045
24386 /* 67045 */ GIM_Reject,
24387 /* 67046 */ // Label 2075: @67046
24388 /* 67046 */ GIM_Reject,
24389 /* 67047 */ // Label 2072: @67047
24390 /* 67047 */ GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(67187),
24391 /* 67052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt),
24392 /* 67057 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2081*/ GIMT_Encode4(67186),
24393 /* 67068 */ /*GILLT_v4s1*//*Label 2079*/ GIMT_Encode4(67076),
24394 /* 67072 */ /*GILLT_v8s1*//*Label 2080*/ GIMT_Encode4(67131),
24395 /* 67076 */ // Label 2079: @67076
24396 /* 67076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2082*/ GIMT_Encode4(67130), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4724 //
24397 /* 67083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24398 /* 67086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24399 /* 67089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24400 /* 67093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24401 /* 67097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24402 /* 67101 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3778:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 11:{ *:[i32] })
24403 /* 67101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24404 /* 67104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24405 /* 67106 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24406 /* 67108 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24407 /* 67110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
24408 /* 67113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24409 /* 67116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24410 /* 67122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24411 /* 67128 */ GIR_RootConstrainSelectedInstOperands,
24412 /* 67129 */ // GIR_Coverage, 4724,
24413 /* 67129 */ GIR_EraseRootFromParent_Done,
24414 /* 67130 */ // Label 2082: @67130
24415 /* 67130 */ GIM_Reject,
24416 /* 67131 */ // Label 2080: @67131
24417 /* 67131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2083*/ GIMT_Encode4(67185), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4722 //
24418 /* 67138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24419 /* 67141 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24420 /* 67144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24421 /* 67148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24422 /* 67152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24423 /* 67156 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3778:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 11:{ *:[i32] })
24424 /* 67156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24425 /* 67159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24426 /* 67161 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24427 /* 67163 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24428 /* 67165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
24429 /* 67168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24430 /* 67171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24431 /* 67177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24432 /* 67183 */ GIR_RootConstrainSelectedInstOperands,
24433 /* 67184 */ // GIR_Coverage, 4722,
24434 /* 67184 */ GIR_EraseRootFromParent_Done,
24435 /* 67185 */ // Label 2083: @67185
24436 /* 67185 */ GIM_Reject,
24437 /* 67186 */ // Label 2081: @67186
24438 /* 67186 */ GIM_Reject,
24439 /* 67187 */ // Label 2078: @67187
24440 /* 67187 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(67327),
24441 /* 67192 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt),
24442 /* 67197 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2087*/ GIMT_Encode4(67326),
24443 /* 67208 */ /*GILLT_v4s1*//*Label 2085*/ GIMT_Encode4(67216),
24444 /* 67212 */ /*GILLT_v8s1*//*Label 2086*/ GIMT_Encode4(67271),
24445 /* 67216 */ // Label 2085: @67216
24446 /* 67216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2088*/ GIMT_Encode4(67270), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4740 //
24447 /* 67223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24448 /* 67226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24449 /* 67229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24450 /* 67233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24451 /* 67237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24452 /* 67241 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3776:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 12:{ *:[i32] })
24453 /* 67241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24454 /* 67244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24455 /* 67246 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24456 /* 67248 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24457 /* 67250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
24458 /* 67253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24459 /* 67256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24460 /* 67262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24461 /* 67268 */ GIR_RootConstrainSelectedInstOperands,
24462 /* 67269 */ // GIR_Coverage, 4740,
24463 /* 67269 */ GIR_EraseRootFromParent_Done,
24464 /* 67270 */ // Label 2088: @67270
24465 /* 67270 */ GIM_Reject,
24466 /* 67271 */ // Label 2086: @67271
24467 /* 67271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2089*/ GIMT_Encode4(67325), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4738 //
24468 /* 67278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24469 /* 67281 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24470 /* 67284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24471 /* 67288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24472 /* 67292 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24473 /* 67296 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3776:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 12:{ *:[i32] })
24474 /* 67296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24475 /* 67299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24476 /* 67301 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24477 /* 67303 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24478 /* 67305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
24479 /* 67308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24480 /* 67311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24481 /* 67317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24482 /* 67323 */ GIR_RootConstrainSelectedInstOperands,
24483 /* 67324 */ // GIR_Coverage, 4738,
24484 /* 67324 */ GIR_EraseRootFromParent_Done,
24485 /* 67325 */ // Label 2089: @67325
24486 /* 67325 */ GIM_Reject,
24487 /* 67326 */ // Label 2087: @67326
24488 /* 67326 */ GIM_Reject,
24489 /* 67327 */ // Label 2084: @67327
24490 /* 67327 */ GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(67467),
24491 /* 67332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le),
24492 /* 67337 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2093*/ GIMT_Encode4(67466),
24493 /* 67348 */ /*GILLT_v4s1*//*Label 2091*/ GIMT_Encode4(67356),
24494 /* 67352 */ /*GILLT_v8s1*//*Label 2092*/ GIMT_Encode4(67411),
24495 /* 67356 */ // Label 2091: @67356
24496 /* 67356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2094*/ GIMT_Encode4(67410), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4756 //
24497 /* 67363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24498 /* 67366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24499 /* 67369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24500 /* 67373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24501 /* 67377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24502 /* 67381 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3777:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 13:{ *:[i32] })
24503 /* 67381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24504 /* 67384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24505 /* 67386 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24506 /* 67388 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24507 /* 67390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
24508 /* 67393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24509 /* 67396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24510 /* 67402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24511 /* 67408 */ GIR_RootConstrainSelectedInstOperands,
24512 /* 67409 */ // GIR_Coverage, 4756,
24513 /* 67409 */ GIR_EraseRootFromParent_Done,
24514 /* 67410 */ // Label 2094: @67410
24515 /* 67410 */ GIM_Reject,
24516 /* 67411 */ // Label 2092: @67411
24517 /* 67411 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2095*/ GIMT_Encode4(67465), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4754 //
24518 /* 67418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24519 /* 67421 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24520 /* 67424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24521 /* 67428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24522 /* 67432 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24523 /* 67436 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3777:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 13:{ *:[i32] })
24524 /* 67436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24525 /* 67439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24526 /* 67441 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24527 /* 67443 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24528 /* 67445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
24529 /* 67448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24530 /* 67451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24531 /* 67457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24532 /* 67463 */ GIR_RootConstrainSelectedInstOperands,
24533 /* 67464 */ // GIR_Coverage, 4754,
24534 /* 67464 */ GIR_EraseRootFromParent_Done,
24535 /* 67465 */ // Label 2095: @67465
24536 /* 67465 */ GIM_Reject,
24537 /* 67466 */ // Label 2093: @67466
24538 /* 67466 */ GIM_Reject,
24539 /* 67467 */ // Label 2090: @67467
24540 /* 67467 */ GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(67818),
24541 /* 67472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
24542 /* 67477 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2100*/ GIMT_Encode4(67817),
24543 /* 67488 */ /*GILLT_v16s8*//*Label 2097*/ GIMT_Encode4(67508), GIMT_Encode4(0),
24544 /* 67496 */ /*GILLT_v8s16*//*Label 2098*/ GIMT_Encode4(67575), GIMT_Encode4(0),
24545 /* 67504 */ /*GILLT_v4s32*//*Label 2099*/ GIMT_Encode4(67696),
24546 /* 67508 */ // Label 2097: @67508
24547 /* 67508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2101*/ GIMT_Encode4(67574), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5278 //
24548 /* 67515 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24549 /* 67518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24550 /* 67521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24551 /* 67525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24552 /* 67529 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24553 /* 67533 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3843:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24554 /* 67533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24555 /* 67536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24556 /* 67540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24557 /* 67545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
24558 /* 67548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24559 /* 67550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24560 /* 67552 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24561 /* 67554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24562 /* 67557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24563 /* 67563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24564 /* 67569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24565 /* 67572 */ GIR_RootConstrainSelectedInstOperands,
24566 /* 67573 */ // GIR_Coverage, 5278,
24567 /* 67573 */ GIR_EraseRootFromParent_Done,
24568 /* 67574 */ // Label 2101: @67574
24569 /* 67574 */ GIM_Reject,
24570 /* 67575 */ // Label 2098: @67575
24571 /* 67575 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(67695),
24572 /* 67580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24573 /* 67583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24574 /* 67586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24575 /* 67590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24576 /* 67594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24577 /* 67598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2103*/ GIMT_Encode4(67646), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5283 //
24578 /* 67605 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3843:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24579 /* 67605 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24580 /* 67608 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24581 /* 67612 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24582 /* 67617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
24583 /* 67620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24584 /* 67622 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24585 /* 67624 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24586 /* 67626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24587 /* 67629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24588 /* 67635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24589 /* 67641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24590 /* 67644 */ GIR_RootConstrainSelectedInstOperands,
24591 /* 67645 */ // GIR_Coverage, 5283,
24592 /* 67645 */ GIR_EraseRootFromParent_Done,
24593 /* 67646 */ // Label 2103: @67646
24594 /* 67646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2104*/ GIMT_Encode4(67694), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5287 //
24595 /* 67653 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3843:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24596 /* 67653 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24597 /* 67656 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24598 /* 67660 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24599 /* 67665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
24600 /* 67668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24601 /* 67670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24602 /* 67672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24603 /* 67674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24604 /* 67677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24605 /* 67683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24606 /* 67689 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24607 /* 67692 */ GIR_RootConstrainSelectedInstOperands,
24608 /* 67693 */ // GIR_Coverage, 5287,
24609 /* 67693 */ GIR_EraseRootFromParent_Done,
24610 /* 67694 */ // Label 2104: @67694
24611 /* 67694 */ GIM_Reject,
24612 /* 67695 */ // Label 2102: @67695
24613 /* 67695 */ GIM_Reject,
24614 /* 67696 */ // Label 2099: @67696
24615 /* 67696 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(67816),
24616 /* 67701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24617 /* 67704 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24618 /* 67707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24619 /* 67711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24620 /* 67715 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24621 /* 67719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2106*/ GIMT_Encode4(67767), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5285 //
24622 /* 67726 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3843:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24623 /* 67726 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24624 /* 67729 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24625 /* 67733 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24626 /* 67738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
24627 /* 67741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24628 /* 67743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24629 /* 67745 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24630 /* 67747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24631 /* 67750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24632 /* 67756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24633 /* 67762 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24634 /* 67765 */ GIR_RootConstrainSelectedInstOperands,
24635 /* 67766 */ // GIR_Coverage, 5285,
24636 /* 67766 */ GIR_EraseRootFromParent_Done,
24637 /* 67767 */ // Label 2106: @67767
24638 /* 67767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2107*/ GIMT_Encode4(67815), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5289 //
24639 /* 67774 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3843:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24640 /* 67774 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24641 /* 67777 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24642 /* 67781 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24643 /* 67786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
24644 /* 67789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24645 /* 67791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24646 /* 67793 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24647 /* 67795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24648 /* 67798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24649 /* 67804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24650 /* 67810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24651 /* 67813 */ GIR_RootConstrainSelectedInstOperands,
24652 /* 67814 */ // GIR_Coverage, 5289,
24653 /* 67814 */ GIR_EraseRootFromParent_Done,
24654 /* 67815 */ // Label 2107: @67815
24655 /* 67815 */ GIM_Reject,
24656 /* 67816 */ // Label 2105: @67816
24657 /* 67816 */ GIM_Reject,
24658 /* 67817 */ // Label 2100: @67817
24659 /* 67817 */ GIM_Reject,
24660 /* 67818 */ // Label 2096: @67818
24661 /* 67818 */ GIM_Reject,
24662 /* 67819 */ // Label 1364: @67819
24663 /* 67819 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(78232),
24664 /* 67824 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
24665 /* 67827 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(68331),
24666 /* 67832 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24667 /* 67837 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2113*/ GIMT_Encode4(68330),
24668 /* 67848 */ /*GILLT_v16s8*//*Label 2110*/ GIMT_Encode4(67868), GIMT_Encode4(0),
24669 /* 67856 */ /*GILLT_v8s16*//*Label 2111*/ GIMT_Encode4(68022), GIMT_Encode4(0),
24670 /* 67864 */ /*GILLT_v4s32*//*Label 2112*/ GIMT_Encode4(68176),
24671 /* 67868 */ // Label 2110: @67868
24672 /* 67868 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(68021),
24673 /* 67873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24674 /* 67876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24675 /* 67879 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24676 /* 67882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24677 /* 67886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24678 /* 67890 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(67955), // Rule ID 4319 //
24679 /* 67895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24680 /* 67899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24681 /* 67903 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
24682 /* 67907 */ // MIs[1] Operand 1
24683 /* 67907 */ // No operand predicates
24684 /* 67907 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24685 /* 67911 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24686 /* 67913 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3925:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24687 /* 67913 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24688 /* 67916 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24689 /* 67920 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24690 /* 67925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8),
24691 /* 67928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24692 /* 67930 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24693 /* 67932 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24694 /* 67935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24695 /* 67938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24696 /* 67944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24697 /* 67950 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24698 /* 67953 */ GIR_RootConstrainSelectedInstOperands,
24699 /* 67954 */ // GIR_Coverage, 4319,
24700 /* 67954 */ GIR_EraseRootFromParent_Done,
24701 /* 67955 */ // Label 2115: @67955
24702 /* 67955 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(68020), // Rule ID 4321 //
24703 /* 67960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24704 /* 67964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24705 /* 67968 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
24706 /* 67972 */ // MIs[1] Operand 1
24707 /* 67972 */ // No operand predicates
24708 /* 67972 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24709 /* 67976 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24710 /* 67978 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3925:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24711 /* 67978 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24712 /* 67981 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24713 /* 67985 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24714 /* 67990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8),
24715 /* 67993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24716 /* 67995 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24717 /* 67997 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24718 /* 68000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24719 /* 68003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24720 /* 68009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24721 /* 68015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24722 /* 68018 */ GIR_RootConstrainSelectedInstOperands,
24723 /* 68019 */ // GIR_Coverage, 4321,
24724 /* 68019 */ GIR_EraseRootFromParent_Done,
24725 /* 68020 */ // Label 2116: @68020
24726 /* 68020 */ GIM_Reject,
24727 /* 68021 */ // Label 2114: @68021
24728 /* 68021 */ GIM_Reject,
24729 /* 68022 */ // Label 2111: @68022
24730 /* 68022 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(68175),
24731 /* 68027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24732 /* 68030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24733 /* 68033 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24734 /* 68036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24735 /* 68040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24736 /* 68044 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(68109), // Rule ID 4323 //
24737 /* 68049 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24738 /* 68053 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24739 /* 68057 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
24740 /* 68061 */ // MIs[1] Operand 1
24741 /* 68061 */ // No operand predicates
24742 /* 68061 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24743 /* 68065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24744 /* 68067 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24745 /* 68067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24746 /* 68070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24747 /* 68074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24748 /* 68079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16),
24749 /* 68082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24750 /* 68084 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24751 /* 68086 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24752 /* 68089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24753 /* 68092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24754 /* 68098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24755 /* 68104 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24756 /* 68107 */ GIR_RootConstrainSelectedInstOperands,
24757 /* 68108 */ // GIR_Coverage, 4323,
24758 /* 68108 */ GIR_EraseRootFromParent_Done,
24759 /* 68109 */ // Label 2118: @68109
24760 /* 68109 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(68174), // Rule ID 4325 //
24761 /* 68114 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24762 /* 68118 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24763 /* 68122 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
24764 /* 68126 */ // MIs[1] Operand 1
24765 /* 68126 */ // No operand predicates
24766 /* 68126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24767 /* 68130 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24768 /* 68132 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24769 /* 68132 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24770 /* 68135 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24771 /* 68139 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24772 /* 68144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16),
24773 /* 68147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24774 /* 68149 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24775 /* 68151 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24776 /* 68154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24777 /* 68157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24778 /* 68163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24779 /* 68169 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24780 /* 68172 */ GIR_RootConstrainSelectedInstOperands,
24781 /* 68173 */ // GIR_Coverage, 4325,
24782 /* 68173 */ GIR_EraseRootFromParent_Done,
24783 /* 68174 */ // Label 2119: @68174
24784 /* 68174 */ GIM_Reject,
24785 /* 68175 */ // Label 2117: @68175
24786 /* 68175 */ GIM_Reject,
24787 /* 68176 */ // Label 2112: @68176
24788 /* 68176 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(68329),
24789 /* 68181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24790 /* 68184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24791 /* 68187 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24792 /* 68190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24793 /* 68194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24794 /* 68198 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(68263), // Rule ID 4327 //
24795 /* 68203 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24796 /* 68207 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24797 /* 68211 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
24798 /* 68215 */ // MIs[1] Operand 1
24799 /* 68215 */ // No operand predicates
24800 /* 68215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24801 /* 68219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24802 /* 68221 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24803 /* 68221 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24804 /* 68224 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24805 /* 68228 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24806 /* 68233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32),
24807 /* 68236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24808 /* 68238 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24809 /* 68240 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24810 /* 68243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24811 /* 68246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24812 /* 68252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24813 /* 68258 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24814 /* 68261 */ GIR_RootConstrainSelectedInstOperands,
24815 /* 68262 */ // GIR_Coverage, 4327,
24816 /* 68262 */ GIR_EraseRootFromParent_Done,
24817 /* 68263 */ // Label 2121: @68263
24818 /* 68263 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(68328), // Rule ID 4329 //
24819 /* 68268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24820 /* 68272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24821 /* 68276 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
24822 /* 68280 */ // MIs[1] Operand 1
24823 /* 68280 */ // No operand predicates
24824 /* 68280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24825 /* 68284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24826 /* 68286 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24827 /* 68286 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24828 /* 68289 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24829 /* 68293 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24830 /* 68298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32),
24831 /* 68301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24832 /* 68303 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24833 /* 68305 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24834 /* 68308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24835 /* 68311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24836 /* 68317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24837 /* 68323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24838 /* 68326 */ GIR_RootConstrainSelectedInstOperands,
24839 /* 68327 */ // GIR_Coverage, 4329,
24840 /* 68327 */ GIR_EraseRootFromParent_Done,
24841 /* 68328 */ // Label 2122: @68328
24842 /* 68328 */ GIM_Reject,
24843 /* 68329 */ // Label 2120: @68329
24844 /* 68329 */ GIM_Reject,
24845 /* 68330 */ // Label 2113: @68330
24846 /* 68330 */ GIM_Reject,
24847 /* 68331 */ // Label 2109: @68331
24848 /* 68331 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(68835),
24849 /* 68336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24850 /* 68341 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2127*/ GIMT_Encode4(68834),
24851 /* 68352 */ /*GILLT_v16s8*//*Label 2124*/ GIMT_Encode4(68372), GIMT_Encode4(0),
24852 /* 68360 */ /*GILLT_v8s16*//*Label 2125*/ GIMT_Encode4(68526), GIMT_Encode4(0),
24853 /* 68368 */ /*GILLT_v4s32*//*Label 2126*/ GIMT_Encode4(68680),
24854 /* 68372 */ // Label 2124: @68372
24855 /* 68372 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(68525),
24856 /* 68377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24857 /* 68380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24858 /* 68383 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24859 /* 68386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24860 /* 68390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24861 /* 68394 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(68459), // Rule ID 4337 //
24862 /* 68399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24863 /* 68403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24864 /* 68407 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
24865 /* 68411 */ // MIs[1] Operand 1
24866 /* 68411 */ // No operand predicates
24867 /* 68411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24868 /* 68415 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24869 /* 68417 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3947:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24870 /* 68417 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24871 /* 68420 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24872 /* 68424 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24873 /* 68429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8),
24874 /* 68432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24875 /* 68434 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24876 /* 68436 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24877 /* 68439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24878 /* 68442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24879 /* 68448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24880 /* 68454 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24881 /* 68457 */ GIR_RootConstrainSelectedInstOperands,
24882 /* 68458 */ // GIR_Coverage, 4337,
24883 /* 68458 */ GIR_EraseRootFromParent_Done,
24884 /* 68459 */ // Label 2129: @68459
24885 /* 68459 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(68524), // Rule ID 4339 //
24886 /* 68464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24887 /* 68468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24888 /* 68472 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
24889 /* 68476 */ // MIs[1] Operand 1
24890 /* 68476 */ // No operand predicates
24891 /* 68476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24892 /* 68480 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24893 /* 68482 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3947:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24894 /* 68482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24895 /* 68485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24896 /* 68489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24897 /* 68494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8),
24898 /* 68497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24899 /* 68499 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24900 /* 68501 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24901 /* 68504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24902 /* 68507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24903 /* 68513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24904 /* 68519 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24905 /* 68522 */ GIR_RootConstrainSelectedInstOperands,
24906 /* 68523 */ // GIR_Coverage, 4339,
24907 /* 68523 */ GIR_EraseRootFromParent_Done,
24908 /* 68524 */ // Label 2130: @68524
24909 /* 68524 */ GIM_Reject,
24910 /* 68525 */ // Label 2128: @68525
24911 /* 68525 */ GIM_Reject,
24912 /* 68526 */ // Label 2125: @68526
24913 /* 68526 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(68679),
24914 /* 68531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24915 /* 68534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24916 /* 68537 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24917 /* 68540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24918 /* 68544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24919 /* 68548 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(68613), // Rule ID 4341 //
24920 /* 68553 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24921 /* 68557 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24922 /* 68561 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
24923 /* 68565 */ // MIs[1] Operand 1
24924 /* 68565 */ // No operand predicates
24925 /* 68565 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24926 /* 68569 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24927 /* 68571 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3947:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24928 /* 68571 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24929 /* 68574 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24930 /* 68578 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24931 /* 68583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16),
24932 /* 68586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24933 /* 68588 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24934 /* 68590 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24935 /* 68593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24936 /* 68596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24937 /* 68602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24938 /* 68608 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24939 /* 68611 */ GIR_RootConstrainSelectedInstOperands,
24940 /* 68612 */ // GIR_Coverage, 4341,
24941 /* 68612 */ GIR_EraseRootFromParent_Done,
24942 /* 68613 */ // Label 2132: @68613
24943 /* 68613 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(68678), // Rule ID 4343 //
24944 /* 68618 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24945 /* 68622 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24946 /* 68626 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
24947 /* 68630 */ // MIs[1] Operand 1
24948 /* 68630 */ // No operand predicates
24949 /* 68630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24950 /* 68634 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24951 /* 68636 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3947:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24952 /* 68636 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24953 /* 68639 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24954 /* 68643 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24955 /* 68648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16),
24956 /* 68651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24957 /* 68653 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24958 /* 68655 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24959 /* 68658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24960 /* 68661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24961 /* 68667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24962 /* 68673 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24963 /* 68676 */ GIR_RootConstrainSelectedInstOperands,
24964 /* 68677 */ // GIR_Coverage, 4343,
24965 /* 68677 */ GIR_EraseRootFromParent_Done,
24966 /* 68678 */ // Label 2133: @68678
24967 /* 68678 */ GIM_Reject,
24968 /* 68679 */ // Label 2131: @68679
24969 /* 68679 */ GIM_Reject,
24970 /* 68680 */ // Label 2126: @68680
24971 /* 68680 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(68833),
24972 /* 68685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24973 /* 68688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24974 /* 68691 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24975 /* 68694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24976 /* 68698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24977 /* 68702 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(68767), // Rule ID 4345 //
24978 /* 68707 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24979 /* 68711 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24980 /* 68715 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
24981 /* 68719 */ // MIs[1] Operand 1
24982 /* 68719 */ // No operand predicates
24983 /* 68719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24984 /* 68723 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24985 /* 68725 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3947:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24986 /* 68725 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24987 /* 68728 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24988 /* 68732 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24989 /* 68737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32),
24990 /* 68740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24991 /* 68742 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24992 /* 68744 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24993 /* 68747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24994 /* 68750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24995 /* 68756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24996 /* 68762 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24997 /* 68765 */ GIR_RootConstrainSelectedInstOperands,
24998 /* 68766 */ // GIR_Coverage, 4345,
24999 /* 68766 */ GIR_EraseRootFromParent_Done,
25000 /* 68767 */ // Label 2135: @68767
25001 /* 68767 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(68832), // Rule ID 4347 //
25002 /* 68772 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25003 /* 68776 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25004 /* 68780 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
25005 /* 68784 */ // MIs[1] Operand 1
25006 /* 68784 */ // No operand predicates
25007 /* 68784 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25008 /* 68788 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25009 /* 68790 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3947:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
25010 /* 68790 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25011 /* 68793 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25012 /* 68797 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25013 /* 68802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32),
25014 /* 68805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25015 /* 68807 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25016 /* 68809 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25017 /* 68812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25018 /* 68815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25019 /* 68821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25020 /* 68827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25021 /* 68830 */ GIR_RootConstrainSelectedInstOperands,
25022 /* 68831 */ // GIR_Coverage, 4347,
25023 /* 68831 */ GIR_EraseRootFromParent_Done,
25024 /* 68832 */ // Label 2136: @68832
25025 /* 68832 */ GIM_Reject,
25026 /* 68833 */ // Label 2134: @68833
25027 /* 68833 */ GIM_Reject,
25028 /* 68834 */ // Label 2127: @68834
25029 /* 68834 */ GIM_Reject,
25030 /* 68835 */ // Label 2123: @68835
25031 /* 68835 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(69437),
25032 /* 68840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25033 /* 68845 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2140*/ GIMT_Encode4(69436),
25034 /* 68856 */ /*GILLT_v8s16*//*Label 2138*/ GIMT_Encode4(68868), GIMT_Encode4(0),
25035 /* 68864 */ /*GILLT_v4s32*//*Label 2139*/ GIMT_Encode4(69152),
25036 /* 68868 */ // Label 2138: @68868
25037 /* 68868 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(69151),
25038 /* 68873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25039 /* 68876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25040 /* 68879 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25041 /* 68882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25042 /* 68886 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(69018),
25043 /* 68891 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25044 /* 68895 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25045 /* 68899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2143*/ GIMT_Encode4(68958), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4493 //
25046 /* 68906 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25047 /* 68910 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25048 /* 68914 */ // MIs[1] Operand 1
25049 /* 68914 */ // No operand predicates
25050 /* 68914 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25051 /* 68916 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3856:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25052 /* 68916 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25053 /* 68919 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25054 /* 68923 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25055 /* 68928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix),
25056 /* 68931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25057 /* 68933 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25058 /* 68935 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25059 /* 68938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25060 /* 68941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25061 /* 68947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25062 /* 68953 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25063 /* 68956 */ GIR_RootConstrainSelectedInstOperands,
25064 /* 68957 */ // GIR_Coverage, 4493,
25065 /* 68957 */ GIR_EraseRootFromParent_Done,
25066 /* 68958 */ // Label 2143: @68958
25067 /* 68958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2144*/ GIMT_Encode4(69017), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4495 //
25068 /* 68965 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25069 /* 68969 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25070 /* 68973 */ // MIs[1] Operand 1
25071 /* 68973 */ // No operand predicates
25072 /* 68973 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25073 /* 68975 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3856:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25074 /* 68975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25075 /* 68978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25076 /* 68982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25077 /* 68987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix),
25078 /* 68990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25079 /* 68992 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25080 /* 68994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25081 /* 68997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25082 /* 69000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25083 /* 69006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25084 /* 69012 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25085 /* 69015 */ GIR_RootConstrainSelectedInstOperands,
25086 /* 69016 */ // GIR_Coverage, 4495,
25087 /* 69016 */ GIR_EraseRootFromParent_Done,
25088 /* 69017 */ // Label 2144: @69017
25089 /* 69017 */ GIM_Reject,
25090 /* 69018 */ // Label 2142: @69018
25091 /* 69018 */ GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(69150),
25092 /* 69023 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25093 /* 69027 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25094 /* 69031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2146*/ GIMT_Encode4(69090), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4497 //
25095 /* 69038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25096 /* 69042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25097 /* 69046 */ // MIs[1] Operand 1
25098 /* 69046 */ // No operand predicates
25099 /* 69046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25100 /* 69048 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3856:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25101 /* 69048 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25102 /* 69051 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25103 /* 69055 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25104 /* 69060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix),
25105 /* 69063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25106 /* 69065 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25107 /* 69067 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25108 /* 69070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25109 /* 69073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25110 /* 69079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25111 /* 69085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25112 /* 69088 */ GIR_RootConstrainSelectedInstOperands,
25113 /* 69089 */ // GIR_Coverage, 4497,
25114 /* 69089 */ GIR_EraseRootFromParent_Done,
25115 /* 69090 */ // Label 2146: @69090
25116 /* 69090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2147*/ GIMT_Encode4(69149), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4499 //
25117 /* 69097 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25118 /* 69101 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25119 /* 69105 */ // MIs[1] Operand 1
25120 /* 69105 */ // No operand predicates
25121 /* 69105 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25122 /* 69107 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3856:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25123 /* 69107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25124 /* 69110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25125 /* 69114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25126 /* 69119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix),
25127 /* 69122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25128 /* 69124 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25129 /* 69126 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25130 /* 69129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25131 /* 69132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25132 /* 69138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25133 /* 69144 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25134 /* 69147 */ GIR_RootConstrainSelectedInstOperands,
25135 /* 69148 */ // GIR_Coverage, 4499,
25136 /* 69148 */ GIR_EraseRootFromParent_Done,
25137 /* 69149 */ // Label 2147: @69149
25138 /* 69149 */ GIM_Reject,
25139 /* 69150 */ // Label 2145: @69150
25140 /* 69150 */ GIM_Reject,
25141 /* 69151 */ // Label 2141: @69151
25142 /* 69151 */ GIM_Reject,
25143 /* 69152 */ // Label 2139: @69152
25144 /* 69152 */ GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(69435),
25145 /* 69157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25146 /* 69160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25147 /* 69163 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25148 /* 69166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25149 /* 69170 */ GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(69302),
25150 /* 69175 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25151 /* 69179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25152 /* 69183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2150*/ GIMT_Encode4(69242), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4501 //
25153 /* 69190 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25154 /* 69194 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25155 /* 69198 */ // MIs[1] Operand 1
25156 /* 69198 */ // No operand predicates
25157 /* 69198 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25158 /* 69200 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3856:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25159 /* 69200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25160 /* 69203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25161 /* 69207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25162 /* 69212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix),
25163 /* 69215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25164 /* 69217 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25165 /* 69219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25166 /* 69222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25167 /* 69225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25168 /* 69231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25169 /* 69237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25170 /* 69240 */ GIR_RootConstrainSelectedInstOperands,
25171 /* 69241 */ // GIR_Coverage, 4501,
25172 /* 69241 */ GIR_EraseRootFromParent_Done,
25173 /* 69242 */ // Label 2150: @69242
25174 /* 69242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2151*/ GIMT_Encode4(69301), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4503 //
25175 /* 69249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25176 /* 69253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25177 /* 69257 */ // MIs[1] Operand 1
25178 /* 69257 */ // No operand predicates
25179 /* 69257 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25180 /* 69259 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3856:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25181 /* 69259 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25182 /* 69262 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25183 /* 69266 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25184 /* 69271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix),
25185 /* 69274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25186 /* 69276 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25187 /* 69278 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25188 /* 69281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25189 /* 69284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25190 /* 69290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25191 /* 69296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25192 /* 69299 */ GIR_RootConstrainSelectedInstOperands,
25193 /* 69300 */ // GIR_Coverage, 4503,
25194 /* 69300 */ GIR_EraseRootFromParent_Done,
25195 /* 69301 */ // Label 2151: @69301
25196 /* 69301 */ GIM_Reject,
25197 /* 69302 */ // Label 2149: @69302
25198 /* 69302 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(69434),
25199 /* 69307 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25200 /* 69311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25201 /* 69315 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2153*/ GIMT_Encode4(69374), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4505 //
25202 /* 69322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25203 /* 69326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25204 /* 69330 */ // MIs[1] Operand 1
25205 /* 69330 */ // No operand predicates
25206 /* 69330 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25207 /* 69332 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3856:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25208 /* 69332 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25209 /* 69335 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25210 /* 69339 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25211 /* 69344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix),
25212 /* 69347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25213 /* 69349 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25214 /* 69351 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25215 /* 69354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25216 /* 69357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25217 /* 69363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25218 /* 69369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25219 /* 69372 */ GIR_RootConstrainSelectedInstOperands,
25220 /* 69373 */ // GIR_Coverage, 4505,
25221 /* 69373 */ GIR_EraseRootFromParent_Done,
25222 /* 69374 */ // Label 2153: @69374
25223 /* 69374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2154*/ GIMT_Encode4(69433), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4507 //
25224 /* 69381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25225 /* 69385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25226 /* 69389 */ // MIs[1] Operand 1
25227 /* 69389 */ // No operand predicates
25228 /* 69389 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25229 /* 69391 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3856:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25230 /* 69391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25231 /* 69394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25232 /* 69398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25233 /* 69403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix),
25234 /* 69406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25235 /* 69408 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25236 /* 69410 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25237 /* 69413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25238 /* 69416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25239 /* 69422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25240 /* 69428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25241 /* 69431 */ GIR_RootConstrainSelectedInstOperands,
25242 /* 69432 */ // GIR_Coverage, 4507,
25243 /* 69432 */ GIR_EraseRootFromParent_Done,
25244 /* 69433 */ // Label 2154: @69433
25245 /* 69433 */ GIM_Reject,
25246 /* 69434 */ // Label 2152: @69434
25247 /* 69434 */ GIM_Reject,
25248 /* 69435 */ // Label 2148: @69435
25249 /* 69435 */ GIM_Reject,
25250 /* 69436 */ // Label 2140: @69436
25251 /* 69436 */ GIM_Reject,
25252 /* 69437 */ // Label 2137: @69437
25253 /* 69437 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(69773),
25254 /* 69442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25255 /* 69447 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25256 /* 69450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25257 /* 69453 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2159*/ GIMT_Encode4(69772),
25258 /* 69464 */ /*GILLT_v16s8*//*Label 2156*/ GIMT_Encode4(69484), GIMT_Encode4(0),
25259 /* 69472 */ /*GILLT_v8s16*//*Label 2157*/ GIMT_Encode4(69580), GIMT_Encode4(0),
25260 /* 69480 */ /*GILLT_v4s32*//*Label 2158*/ GIMT_Encode4(69676),
25261 /* 69484 */ // Label 2156: @69484
25262 /* 69484 */ GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(69579),
25263 /* 69489 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25264 /* 69492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25265 /* 69496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25266 /* 69500 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25267 /* 69504 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2161*/ GIMT_Encode4(69541), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3512 //
25268 /* 69511 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25269 /* 69515 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25270 /* 69515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
25271 /* 69518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25272 /* 69520 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25273 /* 69522 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25274 /* 69524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25275 /* 69527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25276 /* 69533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25277 /* 69539 */ GIR_RootConstrainSelectedInstOperands,
25278 /* 69540 */ // GIR_Coverage, 3512,
25279 /* 69540 */ GIR_EraseRootFromParent_Done,
25280 /* 69541 */ // Label 2161: @69541
25281 /* 69541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2162*/ GIMT_Encode4(69578), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3518 //
25282 /* 69548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25283 /* 69552 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25284 /* 69552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
25285 /* 69555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25286 /* 69557 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25287 /* 69559 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25288 /* 69561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25289 /* 69564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25290 /* 69570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25291 /* 69576 */ GIR_RootConstrainSelectedInstOperands,
25292 /* 69577 */ // GIR_Coverage, 3518,
25293 /* 69577 */ GIR_EraseRootFromParent_Done,
25294 /* 69578 */ // Label 2162: @69578
25295 /* 69578 */ GIM_Reject,
25296 /* 69579 */ // Label 2160: @69579
25297 /* 69579 */ GIM_Reject,
25298 /* 69580 */ // Label 2157: @69580
25299 /* 69580 */ GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(69675),
25300 /* 69585 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25301 /* 69588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25302 /* 69592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25303 /* 69596 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25304 /* 69600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2164*/ GIMT_Encode4(69637), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3514 //
25305 /* 69607 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25306 /* 69611 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25307 /* 69611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
25308 /* 69614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25309 /* 69616 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25310 /* 69618 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25311 /* 69620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25312 /* 69623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25313 /* 69629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25314 /* 69635 */ GIR_RootConstrainSelectedInstOperands,
25315 /* 69636 */ // GIR_Coverage, 3514,
25316 /* 69636 */ GIR_EraseRootFromParent_Done,
25317 /* 69637 */ // Label 2164: @69637
25318 /* 69637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2165*/ GIMT_Encode4(69674), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3520 //
25319 /* 69644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25320 /* 69648 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25321 /* 69648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
25322 /* 69651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25323 /* 69653 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25324 /* 69655 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25325 /* 69657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25326 /* 69660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25327 /* 69666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25328 /* 69672 */ GIR_RootConstrainSelectedInstOperands,
25329 /* 69673 */ // GIR_Coverage, 3520,
25330 /* 69673 */ GIR_EraseRootFromParent_Done,
25331 /* 69674 */ // Label 2165: @69674
25332 /* 69674 */ GIM_Reject,
25333 /* 69675 */ // Label 2163: @69675
25334 /* 69675 */ GIM_Reject,
25335 /* 69676 */ // Label 2158: @69676
25336 /* 69676 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(69771),
25337 /* 69681 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25338 /* 69684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25339 /* 69688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25340 /* 69692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25341 /* 69696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2167*/ GIMT_Encode4(69733), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3516 //
25342 /* 69703 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25343 /* 69707 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25344 /* 69707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
25345 /* 69710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25346 /* 69712 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25347 /* 69714 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25348 /* 69716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25349 /* 69719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25350 /* 69725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25351 /* 69731 */ GIR_RootConstrainSelectedInstOperands,
25352 /* 69732 */ // GIR_Coverage, 3516,
25353 /* 69732 */ GIR_EraseRootFromParent_Done,
25354 /* 69733 */ // Label 2167: @69733
25355 /* 69733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2168*/ GIMT_Encode4(69770), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3522 //
25356 /* 69740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25357 /* 69744 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25358 /* 69744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
25359 /* 69747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25360 /* 69749 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25361 /* 69751 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25362 /* 69753 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25363 /* 69756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25364 /* 69762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25365 /* 69768 */ GIR_RootConstrainSelectedInstOperands,
25366 /* 69769 */ // GIR_Coverage, 3522,
25367 /* 69769 */ GIR_EraseRootFromParent_Done,
25368 /* 69770 */ // Label 2168: @69770
25369 /* 69770 */ GIM_Reject,
25370 /* 69771 */ // Label 2166: @69771
25371 /* 69771 */ GIM_Reject,
25372 /* 69772 */ // Label 2159: @69772
25373 /* 69772 */ GIM_Reject,
25374 /* 69773 */ // Label 2155: @69773
25375 /* 69773 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(70109),
25376 /* 69778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25377 /* 69783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25378 /* 69786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25379 /* 69789 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2173*/ GIMT_Encode4(70108),
25380 /* 69800 */ /*GILLT_v16s8*//*Label 2170*/ GIMT_Encode4(69820), GIMT_Encode4(0),
25381 /* 69808 */ /*GILLT_v8s16*//*Label 2171*/ GIMT_Encode4(69916), GIMT_Encode4(0),
25382 /* 69816 */ /*GILLT_v4s32*//*Label 2172*/ GIMT_Encode4(70012),
25383 /* 69820 */ // Label 2170: @69820
25384 /* 69820 */ GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(69915),
25385 /* 69825 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25386 /* 69828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25387 /* 69832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25388 /* 69836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25389 /* 69840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2175*/ GIMT_Encode4(69877), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3524 //
25390 /* 69847 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25391 /* 69851 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25392 /* 69851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
25393 /* 69854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25394 /* 69856 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25395 /* 69858 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25396 /* 69860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25397 /* 69863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25398 /* 69869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25399 /* 69875 */ GIR_RootConstrainSelectedInstOperands,
25400 /* 69876 */ // GIR_Coverage, 3524,
25401 /* 69876 */ GIR_EraseRootFromParent_Done,
25402 /* 69877 */ // Label 2175: @69877
25403 /* 69877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2176*/ GIMT_Encode4(69914), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3530 //
25404 /* 69884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25405 /* 69888 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25406 /* 69888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
25407 /* 69891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25408 /* 69893 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25409 /* 69895 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25410 /* 69897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25411 /* 69900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25412 /* 69906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25413 /* 69912 */ GIR_RootConstrainSelectedInstOperands,
25414 /* 69913 */ // GIR_Coverage, 3530,
25415 /* 69913 */ GIR_EraseRootFromParent_Done,
25416 /* 69914 */ // Label 2176: @69914
25417 /* 69914 */ GIM_Reject,
25418 /* 69915 */ // Label 2174: @69915
25419 /* 69915 */ GIM_Reject,
25420 /* 69916 */ // Label 2171: @69916
25421 /* 69916 */ GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(70011),
25422 /* 69921 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25423 /* 69924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25424 /* 69928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25425 /* 69932 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25426 /* 69936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2178*/ GIMT_Encode4(69973), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3526 //
25427 /* 69943 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25428 /* 69947 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25429 /* 69947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
25430 /* 69950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25431 /* 69952 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25432 /* 69954 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25433 /* 69956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25434 /* 69959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25435 /* 69965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25436 /* 69971 */ GIR_RootConstrainSelectedInstOperands,
25437 /* 69972 */ // GIR_Coverage, 3526,
25438 /* 69972 */ GIR_EraseRootFromParent_Done,
25439 /* 69973 */ // Label 2178: @69973
25440 /* 69973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2179*/ GIMT_Encode4(70010), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3532 //
25441 /* 69980 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25442 /* 69984 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25443 /* 69984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
25444 /* 69987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25445 /* 69989 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25446 /* 69991 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25447 /* 69993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25448 /* 69996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25449 /* 70002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25450 /* 70008 */ GIR_RootConstrainSelectedInstOperands,
25451 /* 70009 */ // GIR_Coverage, 3532,
25452 /* 70009 */ GIR_EraseRootFromParent_Done,
25453 /* 70010 */ // Label 2179: @70010
25454 /* 70010 */ GIM_Reject,
25455 /* 70011 */ // Label 2177: @70011
25456 /* 70011 */ GIM_Reject,
25457 /* 70012 */ // Label 2172: @70012
25458 /* 70012 */ GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(70107),
25459 /* 70017 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25460 /* 70020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25461 /* 70024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25462 /* 70028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25463 /* 70032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2181*/ GIMT_Encode4(70069), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3528 //
25464 /* 70039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25465 /* 70043 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25466 /* 70043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
25467 /* 70046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25468 /* 70048 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25469 /* 70050 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25470 /* 70052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25471 /* 70055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25472 /* 70061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25473 /* 70067 */ GIR_RootConstrainSelectedInstOperands,
25474 /* 70068 */ // GIR_Coverage, 3528,
25475 /* 70068 */ GIR_EraseRootFromParent_Done,
25476 /* 70069 */ // Label 2181: @70069
25477 /* 70069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2182*/ GIMT_Encode4(70106), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3534 //
25478 /* 70076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25479 /* 70080 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25480 /* 70080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
25481 /* 70083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25482 /* 70085 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25483 /* 70087 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25484 /* 70089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25485 /* 70092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25486 /* 70098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25487 /* 70104 */ GIR_RootConstrainSelectedInstOperands,
25488 /* 70105 */ // GIR_Coverage, 3534,
25489 /* 70105 */ GIR_EraseRootFromParent_Done,
25490 /* 70106 */ // Label 2182: @70106
25491 /* 70106 */ GIM_Reject,
25492 /* 70107 */ // Label 2180: @70107
25493 /* 70107 */ GIM_Reject,
25494 /* 70108 */ // Label 2173: @70108
25495 /* 70108 */ GIM_Reject,
25496 /* 70109 */ // Label 2169: @70109
25497 /* 70109 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(70547),
25498 /* 70114 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25499 /* 70119 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2187*/ GIMT_Encode4(70546),
25500 /* 70130 */ /*GILLT_v16s8*//*Label 2184*/ GIMT_Encode4(70150), GIMT_Encode4(0),
25501 /* 70138 */ /*GILLT_v8s16*//*Label 2185*/ GIMT_Encode4(70282), GIMT_Encode4(0),
25502 /* 70146 */ /*GILLT_v4s32*//*Label 2186*/ GIMT_Encode4(70414),
25503 /* 70150 */ // Label 2184: @70150
25504 /* 70150 */ GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(70281),
25505 /* 70155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25506 /* 70158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25507 /* 70161 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25508 /* 70164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25509 /* 70168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25510 /* 70172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25511 /* 70176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2189*/ GIMT_Encode4(70228), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3945 //
25512 /* 70183 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25513 /* 70187 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3839:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25514 /* 70187 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25515 /* 70190 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25516 /* 70194 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25517 /* 70199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
25518 /* 70202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25519 /* 70204 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25520 /* 70206 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25521 /* 70208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25522 /* 70211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25523 /* 70217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25524 /* 70223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25525 /* 70226 */ GIR_RootConstrainSelectedInstOperands,
25526 /* 70227 */ // GIR_Coverage, 3945,
25527 /* 70227 */ GIR_EraseRootFromParent_Done,
25528 /* 70228 */ // Label 2189: @70228
25529 /* 70228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2190*/ GIMT_Encode4(70280), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3960 //
25530 /* 70235 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25531 /* 70239 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3839:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25532 /* 70239 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25533 /* 70242 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25534 /* 70246 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25535 /* 70251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
25536 /* 70254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25537 /* 70256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25538 /* 70258 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25539 /* 70260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25540 /* 70263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25541 /* 70269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25542 /* 70275 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25543 /* 70278 */ GIR_RootConstrainSelectedInstOperands,
25544 /* 70279 */ // GIR_Coverage, 3960,
25545 /* 70279 */ GIR_EraseRootFromParent_Done,
25546 /* 70280 */ // Label 2190: @70280
25547 /* 70280 */ GIM_Reject,
25548 /* 70281 */ // Label 2188: @70281
25549 /* 70281 */ GIM_Reject,
25550 /* 70282 */ // Label 2185: @70282
25551 /* 70282 */ GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(70413),
25552 /* 70287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25553 /* 70290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25554 /* 70293 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25555 /* 70296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25556 /* 70300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25557 /* 70304 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25558 /* 70308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2192*/ GIMT_Encode4(70360), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3952 //
25559 /* 70315 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25560 /* 70319 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3839:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25561 /* 70319 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25562 /* 70322 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25563 /* 70326 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25564 /* 70331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
25565 /* 70334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25566 /* 70336 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25567 /* 70338 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25568 /* 70340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25569 /* 70343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25570 /* 70349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25571 /* 70355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25572 /* 70358 */ GIR_RootConstrainSelectedInstOperands,
25573 /* 70359 */ // GIR_Coverage, 3952,
25574 /* 70359 */ GIR_EraseRootFromParent_Done,
25575 /* 70360 */ // Label 2192: @70360
25576 /* 70360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2193*/ GIMT_Encode4(70412), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3964 //
25577 /* 70367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25578 /* 70371 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3839:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25579 /* 70371 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25580 /* 70374 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25581 /* 70378 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25582 /* 70383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
25583 /* 70386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25584 /* 70388 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25585 /* 70390 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25586 /* 70392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25587 /* 70395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25588 /* 70401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25589 /* 70407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25590 /* 70410 */ GIR_RootConstrainSelectedInstOperands,
25591 /* 70411 */ // GIR_Coverage, 3964,
25592 /* 70411 */ GIR_EraseRootFromParent_Done,
25593 /* 70412 */ // Label 2193: @70412
25594 /* 70412 */ GIM_Reject,
25595 /* 70413 */ // Label 2191: @70413
25596 /* 70413 */ GIM_Reject,
25597 /* 70414 */ // Label 2186: @70414
25598 /* 70414 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(70545),
25599 /* 70419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25600 /* 70422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25601 /* 70425 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25602 /* 70428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25603 /* 70432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25604 /* 70436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25605 /* 70440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2195*/ GIMT_Encode4(70492), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3956 //
25606 /* 70447 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25607 /* 70451 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3839:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25608 /* 70451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25609 /* 70454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25610 /* 70458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25611 /* 70463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
25612 /* 70466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25613 /* 70468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25614 /* 70470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25615 /* 70472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25616 /* 70475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25617 /* 70481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25618 /* 70487 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25619 /* 70490 */ GIR_RootConstrainSelectedInstOperands,
25620 /* 70491 */ // GIR_Coverage, 3956,
25621 /* 70491 */ GIR_EraseRootFromParent_Done,
25622 /* 70492 */ // Label 2195: @70492
25623 /* 70492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2196*/ GIMT_Encode4(70544), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3968 //
25624 /* 70499 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25625 /* 70503 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3839:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25626 /* 70503 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25627 /* 70506 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25628 /* 70510 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25629 /* 70515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
25630 /* 70518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25631 /* 70520 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25632 /* 70522 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25633 /* 70524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25634 /* 70527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25635 /* 70533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25636 /* 70539 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25637 /* 70542 */ GIR_RootConstrainSelectedInstOperands,
25638 /* 70543 */ // GIR_Coverage, 3968,
25639 /* 70543 */ GIR_EraseRootFromParent_Done,
25640 /* 70544 */ // Label 2196: @70544
25641 /* 70544 */ GIM_Reject,
25642 /* 70545 */ // Label 2194: @70545
25643 /* 70545 */ GIM_Reject,
25644 /* 70546 */ // Label 2187: @70546
25645 /* 70546 */ GIM_Reject,
25646 /* 70547 */ // Label 2183: @70547
25647 /* 70547 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(70985),
25648 /* 70552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25649 /* 70557 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2201*/ GIMT_Encode4(70984),
25650 /* 70568 */ /*GILLT_v16s8*//*Label 2198*/ GIMT_Encode4(70588), GIMT_Encode4(0),
25651 /* 70576 */ /*GILLT_v8s16*//*Label 2199*/ GIMT_Encode4(70720), GIMT_Encode4(0),
25652 /* 70584 */ /*GILLT_v4s32*//*Label 2200*/ GIMT_Encode4(70852),
25653 /* 70588 */ // Label 2198: @70588
25654 /* 70588 */ GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(70719),
25655 /* 70593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25656 /* 70596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25657 /* 70599 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25658 /* 70602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25659 /* 70606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25660 /* 70610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25661 /* 70614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2203*/ GIMT_Encode4(70666), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3969 //
25662 /* 70621 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25663 /* 70625 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25664 /* 70625 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25665 /* 70628 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25666 /* 70632 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25667 /* 70637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
25668 /* 70640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25669 /* 70642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25670 /* 70644 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25671 /* 70646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25672 /* 70649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25673 /* 70655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25674 /* 70661 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25675 /* 70664 */ GIR_RootConstrainSelectedInstOperands,
25676 /* 70665 */ // GIR_Coverage, 3969,
25677 /* 70665 */ GIR_EraseRootFromParent_Done,
25678 /* 70666 */ // Label 2203: @70666
25679 /* 70666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2204*/ GIMT_Encode4(70718), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3984 //
25680 /* 70673 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25681 /* 70677 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25682 /* 70677 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25683 /* 70680 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25684 /* 70684 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25685 /* 70689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
25686 /* 70692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25687 /* 70694 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25688 /* 70696 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25689 /* 70698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25690 /* 70701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25691 /* 70707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25692 /* 70713 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25693 /* 70716 */ GIR_RootConstrainSelectedInstOperands,
25694 /* 70717 */ // GIR_Coverage, 3984,
25695 /* 70717 */ GIR_EraseRootFromParent_Done,
25696 /* 70718 */ // Label 2204: @70718
25697 /* 70718 */ GIM_Reject,
25698 /* 70719 */ // Label 2202: @70719
25699 /* 70719 */ GIM_Reject,
25700 /* 70720 */ // Label 2199: @70720
25701 /* 70720 */ GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(70851),
25702 /* 70725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25703 /* 70728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25704 /* 70731 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25705 /* 70734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25706 /* 70738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25707 /* 70742 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25708 /* 70746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2206*/ GIMT_Encode4(70798), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3976 //
25709 /* 70753 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25710 /* 70757 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25711 /* 70757 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25712 /* 70760 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25713 /* 70764 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25714 /* 70769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
25715 /* 70772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25716 /* 70774 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25717 /* 70776 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25718 /* 70778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25719 /* 70781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25720 /* 70787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25721 /* 70793 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25722 /* 70796 */ GIR_RootConstrainSelectedInstOperands,
25723 /* 70797 */ // GIR_Coverage, 3976,
25724 /* 70797 */ GIR_EraseRootFromParent_Done,
25725 /* 70798 */ // Label 2206: @70798
25726 /* 70798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2207*/ GIMT_Encode4(70850), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3988 //
25727 /* 70805 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25728 /* 70809 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25729 /* 70809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25730 /* 70812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25731 /* 70816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25732 /* 70821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
25733 /* 70824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25734 /* 70826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25735 /* 70828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25736 /* 70830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25737 /* 70833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25738 /* 70839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25739 /* 70845 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25740 /* 70848 */ GIR_RootConstrainSelectedInstOperands,
25741 /* 70849 */ // GIR_Coverage, 3988,
25742 /* 70849 */ GIR_EraseRootFromParent_Done,
25743 /* 70850 */ // Label 2207: @70850
25744 /* 70850 */ GIM_Reject,
25745 /* 70851 */ // Label 2205: @70851
25746 /* 70851 */ GIM_Reject,
25747 /* 70852 */ // Label 2200: @70852
25748 /* 70852 */ GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(70983),
25749 /* 70857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25750 /* 70860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25751 /* 70863 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25752 /* 70866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25753 /* 70870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25754 /* 70874 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25755 /* 70878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2209*/ GIMT_Encode4(70930), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3980 //
25756 /* 70885 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25757 /* 70889 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25758 /* 70889 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25759 /* 70892 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25760 /* 70896 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25761 /* 70901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
25762 /* 70904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25763 /* 70906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25764 /* 70908 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25765 /* 70910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25766 /* 70913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25767 /* 70919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25768 /* 70925 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25769 /* 70928 */ GIR_RootConstrainSelectedInstOperands,
25770 /* 70929 */ // GIR_Coverage, 3980,
25771 /* 70929 */ GIR_EraseRootFromParent_Done,
25772 /* 70930 */ // Label 2209: @70930
25773 /* 70930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2210*/ GIMT_Encode4(70982), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3992 //
25774 /* 70937 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25775 /* 70941 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25776 /* 70941 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25777 /* 70944 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25778 /* 70948 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25779 /* 70953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
25780 /* 70956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25781 /* 70958 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25782 /* 70960 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25783 /* 70962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25784 /* 70965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25785 /* 70971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25786 /* 70977 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25787 /* 70980 */ GIR_RootConstrainSelectedInstOperands,
25788 /* 70981 */ // GIR_Coverage, 3992,
25789 /* 70981 */ GIR_EraseRootFromParent_Done,
25790 /* 70982 */ // Label 2210: @70982
25791 /* 70982 */ GIM_Reject,
25792 /* 70983 */ // Label 2208: @70983
25793 /* 70983 */ GIM_Reject,
25794 /* 70984 */ // Label 2201: @70984
25795 /* 70984 */ GIM_Reject,
25796 /* 70985 */ // Label 2197: @70985
25797 /* 70985 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(71423),
25798 /* 70990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25799 /* 70995 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2215*/ GIMT_Encode4(71422),
25800 /* 71006 */ /*GILLT_v16s8*//*Label 2212*/ GIMT_Encode4(71026), GIMT_Encode4(0),
25801 /* 71014 */ /*GILLT_v8s16*//*Label 2213*/ GIMT_Encode4(71158), GIMT_Encode4(0),
25802 /* 71022 */ /*GILLT_v4s32*//*Label 2214*/ GIMT_Encode4(71290),
25803 /* 71026 */ // Label 2212: @71026
25804 /* 71026 */ GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(71157),
25805 /* 71031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25806 /* 71034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25807 /* 71037 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25808 /* 71040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25809 /* 71044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25810 /* 71048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25811 /* 71052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2217*/ GIMT_Encode4(71104), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3993 //
25812 /* 71059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25813 /* 71063 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3877:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25814 /* 71063 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25815 /* 71066 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25816 /* 71070 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25817 /* 71075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
25818 /* 71078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25819 /* 71080 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25820 /* 71082 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25821 /* 71084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25822 /* 71087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25823 /* 71093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25824 /* 71099 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25825 /* 71102 */ GIR_RootConstrainSelectedInstOperands,
25826 /* 71103 */ // GIR_Coverage, 3993,
25827 /* 71103 */ GIR_EraseRootFromParent_Done,
25828 /* 71104 */ // Label 2217: @71104
25829 /* 71104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2218*/ GIMT_Encode4(71156), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4008 //
25830 /* 71111 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25831 /* 71115 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3877:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25832 /* 71115 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25833 /* 71118 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25834 /* 71122 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25835 /* 71127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
25836 /* 71130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25837 /* 71132 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25838 /* 71134 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25839 /* 71136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25840 /* 71139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25841 /* 71145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25842 /* 71151 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25843 /* 71154 */ GIR_RootConstrainSelectedInstOperands,
25844 /* 71155 */ // GIR_Coverage, 4008,
25845 /* 71155 */ GIR_EraseRootFromParent_Done,
25846 /* 71156 */ // Label 2218: @71156
25847 /* 71156 */ GIM_Reject,
25848 /* 71157 */ // Label 2216: @71157
25849 /* 71157 */ GIM_Reject,
25850 /* 71158 */ // Label 2213: @71158
25851 /* 71158 */ GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(71289),
25852 /* 71163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25853 /* 71166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25854 /* 71169 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25855 /* 71172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25856 /* 71176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25857 /* 71180 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25858 /* 71184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2220*/ GIMT_Encode4(71236), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4000 //
25859 /* 71191 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25860 /* 71195 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3877:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25861 /* 71195 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25862 /* 71198 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25863 /* 71202 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25864 /* 71207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
25865 /* 71210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25866 /* 71212 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25867 /* 71214 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25868 /* 71216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25869 /* 71219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25870 /* 71225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25871 /* 71231 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25872 /* 71234 */ GIR_RootConstrainSelectedInstOperands,
25873 /* 71235 */ // GIR_Coverage, 4000,
25874 /* 71235 */ GIR_EraseRootFromParent_Done,
25875 /* 71236 */ // Label 2220: @71236
25876 /* 71236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2221*/ GIMT_Encode4(71288), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4012 //
25877 /* 71243 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25878 /* 71247 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3877:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25879 /* 71247 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25880 /* 71250 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25881 /* 71254 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25882 /* 71259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
25883 /* 71262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25884 /* 71264 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25885 /* 71266 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25886 /* 71268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25887 /* 71271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25888 /* 71277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25889 /* 71283 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25890 /* 71286 */ GIR_RootConstrainSelectedInstOperands,
25891 /* 71287 */ // GIR_Coverage, 4012,
25892 /* 71287 */ GIR_EraseRootFromParent_Done,
25893 /* 71288 */ // Label 2221: @71288
25894 /* 71288 */ GIM_Reject,
25895 /* 71289 */ // Label 2219: @71289
25896 /* 71289 */ GIM_Reject,
25897 /* 71290 */ // Label 2214: @71290
25898 /* 71290 */ GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(71421),
25899 /* 71295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25900 /* 71298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25901 /* 71301 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25902 /* 71304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25903 /* 71308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25904 /* 71312 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25905 /* 71316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2223*/ GIMT_Encode4(71368), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4004 //
25906 /* 71323 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25907 /* 71327 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3877:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25908 /* 71327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25909 /* 71330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25910 /* 71334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25911 /* 71339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
25912 /* 71342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25913 /* 71344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25914 /* 71346 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25915 /* 71348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25916 /* 71351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25917 /* 71357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25918 /* 71363 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25919 /* 71366 */ GIR_RootConstrainSelectedInstOperands,
25920 /* 71367 */ // GIR_Coverage, 4004,
25921 /* 71367 */ GIR_EraseRootFromParent_Done,
25922 /* 71368 */ // Label 2223: @71368
25923 /* 71368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2224*/ GIMT_Encode4(71420), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4016 //
25924 /* 71375 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25925 /* 71379 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3877:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25926 /* 71379 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25927 /* 71382 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25928 /* 71386 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25929 /* 71391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
25930 /* 71394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25931 /* 71396 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25932 /* 71398 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25933 /* 71400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25934 /* 71403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25935 /* 71409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25936 /* 71415 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25937 /* 71418 */ GIR_RootConstrainSelectedInstOperands,
25938 /* 71419 */ // GIR_Coverage, 4016,
25939 /* 71419 */ GIR_EraseRootFromParent_Done,
25940 /* 71420 */ // Label 2224: @71420
25941 /* 71420 */ GIM_Reject,
25942 /* 71421 */ // Label 2222: @71421
25943 /* 71421 */ GIM_Reject,
25944 /* 71422 */ // Label 2215: @71422
25945 /* 71422 */ GIM_Reject,
25946 /* 71423 */ // Label 2211: @71423
25947 /* 71423 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(71861),
25948 /* 71428 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
25949 /* 71433 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2229*/ GIMT_Encode4(71860),
25950 /* 71444 */ /*GILLT_v16s8*//*Label 2226*/ GIMT_Encode4(71464), GIMT_Encode4(0),
25951 /* 71452 */ /*GILLT_v8s16*//*Label 2227*/ GIMT_Encode4(71596), GIMT_Encode4(0),
25952 /* 71460 */ /*GILLT_v4s32*//*Label 2228*/ GIMT_Encode4(71728),
25953 /* 71464 */ // Label 2226: @71464
25954 /* 71464 */ GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(71595),
25955 /* 71469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25956 /* 71472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25957 /* 71475 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25958 /* 71478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25959 /* 71482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25960 /* 71486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25961 /* 71490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2231*/ GIMT_Encode4(71542), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4017 //
25962 /* 71497 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25963 /* 71501 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3878:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25964 /* 71501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25965 /* 71504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25966 /* 71508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25967 /* 71513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8),
25968 /* 71516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25969 /* 71518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25970 /* 71520 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25971 /* 71522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25972 /* 71525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25973 /* 71531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25974 /* 71537 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25975 /* 71540 */ GIR_RootConstrainSelectedInstOperands,
25976 /* 71541 */ // GIR_Coverage, 4017,
25977 /* 71541 */ GIR_EraseRootFromParent_Done,
25978 /* 71542 */ // Label 2231: @71542
25979 /* 71542 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2232*/ GIMT_Encode4(71594), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4026 //
25980 /* 71549 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25981 /* 71553 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3878:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25982 /* 71553 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25983 /* 71556 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25984 /* 71560 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25985 /* 71565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8),
25986 /* 71568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25987 /* 71570 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25988 /* 71572 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25989 /* 71574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25990 /* 71577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25991 /* 71583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25992 /* 71589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25993 /* 71592 */ GIR_RootConstrainSelectedInstOperands,
25994 /* 71593 */ // GIR_Coverage, 4026,
25995 /* 71593 */ GIR_EraseRootFromParent_Done,
25996 /* 71594 */ // Label 2232: @71594
25997 /* 71594 */ GIM_Reject,
25998 /* 71595 */ // Label 2230: @71595
25999 /* 71595 */ GIM_Reject,
26000 /* 71596 */ // Label 2227: @71596
26001 /* 71596 */ GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(71727),
26002 /* 71601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26003 /* 71604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26004 /* 71607 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26005 /* 71610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26006 /* 71614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26007 /* 71618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26008 /* 71622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2234*/ GIMT_Encode4(71674), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4020 //
26009 /* 71629 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26010 /* 71633 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3878:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26011 /* 71633 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26012 /* 71636 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26013 /* 71640 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26014 /* 71645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16),
26015 /* 71648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26016 /* 71650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26017 /* 71652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26018 /* 71654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26019 /* 71657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26020 /* 71663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26021 /* 71669 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26022 /* 71672 */ GIR_RootConstrainSelectedInstOperands,
26023 /* 71673 */ // GIR_Coverage, 4020,
26024 /* 71673 */ GIR_EraseRootFromParent_Done,
26025 /* 71674 */ // Label 2234: @71674
26026 /* 71674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2235*/ GIMT_Encode4(71726), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4029 //
26027 /* 71681 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26028 /* 71685 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3878:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26029 /* 71685 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26030 /* 71688 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26031 /* 71692 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26032 /* 71697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16),
26033 /* 71700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26034 /* 71702 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26035 /* 71704 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26036 /* 71706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26037 /* 71709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26038 /* 71715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26039 /* 71721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26040 /* 71724 */ GIR_RootConstrainSelectedInstOperands,
26041 /* 71725 */ // GIR_Coverage, 4029,
26042 /* 71725 */ GIR_EraseRootFromParent_Done,
26043 /* 71726 */ // Label 2235: @71726
26044 /* 71726 */ GIM_Reject,
26045 /* 71727 */ // Label 2233: @71727
26046 /* 71727 */ GIM_Reject,
26047 /* 71728 */ // Label 2228: @71728
26048 /* 71728 */ GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(71859),
26049 /* 71733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26050 /* 71736 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26051 /* 71739 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26052 /* 71742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26053 /* 71746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26054 /* 71750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26055 /* 71754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2237*/ GIMT_Encode4(71806), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4023 //
26056 /* 71761 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26057 /* 71765 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3878:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26058 /* 71765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26059 /* 71768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26060 /* 71772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26061 /* 71777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32),
26062 /* 71780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26063 /* 71782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26064 /* 71784 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26065 /* 71786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26066 /* 71789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26067 /* 71795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26068 /* 71801 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26069 /* 71804 */ GIR_RootConstrainSelectedInstOperands,
26070 /* 71805 */ // GIR_Coverage, 4023,
26071 /* 71805 */ GIR_EraseRootFromParent_Done,
26072 /* 71806 */ // Label 2237: @71806
26073 /* 71806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2238*/ GIMT_Encode4(71858), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4032 //
26074 /* 71813 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26075 /* 71817 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3878:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26076 /* 71817 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26077 /* 71820 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26078 /* 71824 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26079 /* 71829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32),
26080 /* 71832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26081 /* 71834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26082 /* 71836 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26083 /* 71838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26084 /* 71841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26085 /* 71847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26086 /* 71853 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26087 /* 71856 */ GIR_RootConstrainSelectedInstOperands,
26088 /* 71857 */ // GIR_Coverage, 4032,
26089 /* 71857 */ GIR_EraseRootFromParent_Done,
26090 /* 71858 */ // Label 2238: @71858
26091 /* 71858 */ GIM_Reject,
26092 /* 71859 */ // Label 2236: @71859
26093 /* 71859 */ GIM_Reject,
26094 /* 71860 */ // Label 2229: @71860
26095 /* 71860 */ GIM_Reject,
26096 /* 71861 */ // Label 2225: @71861
26097 /* 71861 */ GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(72043),
26098 /* 71866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26099 /* 71871 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2242*/ GIMT_Encode4(72042),
26100 /* 71882 */ /*GILLT_v8s16*//*Label 2240*/ GIMT_Encode4(71894), GIMT_Encode4(0),
26101 /* 71890 */ /*GILLT_v4s32*//*Label 2241*/ GIMT_Encode4(71968),
26102 /* 71894 */ // Label 2240: @71894
26103 /* 71894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2243*/ GIMT_Encode4(71967), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4489 //
26104 /* 71901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26105 /* 71904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26106 /* 71907 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26107 /* 71910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26108 /* 71914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26109 /* 71918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26110 /* 71922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26111 /* 71926 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3839:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
26112 /* 71926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26113 /* 71929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26114 /* 71933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26115 /* 71938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
26116 /* 71941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26117 /* 71943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26118 /* 71945 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26119 /* 71947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26120 /* 71950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26121 /* 71956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26122 /* 71962 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26123 /* 71965 */ GIR_RootConstrainSelectedInstOperands,
26124 /* 71966 */ // GIR_Coverage, 4489,
26125 /* 71966 */ GIR_EraseRootFromParent_Done,
26126 /* 71967 */ // Label 2243: @71967
26127 /* 71967 */ GIM_Reject,
26128 /* 71968 */ // Label 2241: @71968
26129 /* 71968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2244*/ GIMT_Encode4(72041), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4487 //
26130 /* 71975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26131 /* 71978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26132 /* 71981 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26133 /* 71984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26134 /* 71988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26135 /* 71992 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26136 /* 71996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26137 /* 72000 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3839:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
26138 /* 72000 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26139 /* 72003 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26140 /* 72007 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26141 /* 72012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
26142 /* 72015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26143 /* 72017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26144 /* 72019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26145 /* 72021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26146 /* 72024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26147 /* 72030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26148 /* 72036 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26149 /* 72039 */ GIR_RootConstrainSelectedInstOperands,
26150 /* 72040 */ // GIR_Coverage, 4487,
26151 /* 72040 */ GIR_EraseRootFromParent_Done,
26152 /* 72041 */ // Label 2244: @72041
26153 /* 72041 */ GIM_Reject,
26154 /* 72042 */ // Label 2242: @72042
26155 /* 72042 */ GIM_Reject,
26156 /* 72043 */ // Label 2239: @72043
26157 /* 72043 */ GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(72341),
26158 /* 72048 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26159 /* 72053 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2248*/ GIMT_Encode4(72340),
26160 /* 72064 */ /*GILLT_v8s16*//*Label 2246*/ GIMT_Encode4(72076), GIMT_Encode4(0),
26161 /* 72072 */ /*GILLT_v4s32*//*Label 2247*/ GIMT_Encode4(72208),
26162 /* 72076 */ // Label 2246: @72076
26163 /* 72076 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(72207),
26164 /* 72081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26165 /* 72084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26166 /* 72087 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26167 /* 72090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26168 /* 72094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26169 /* 72098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26170 /* 72102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2250*/ GIMT_Encode4(72154), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4922 //
26171 /* 72109 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26172 /* 72113 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3908:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26173 /* 72113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26174 /* 72116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26175 /* 72120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26176 /* 72125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8),
26177 /* 72128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26178 /* 72130 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26179 /* 72132 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26180 /* 72134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26181 /* 72137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26182 /* 72143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26183 /* 72149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26184 /* 72152 */ GIR_RootConstrainSelectedInstOperands,
26185 /* 72153 */ // GIR_Coverage, 4922,
26186 /* 72153 */ GIR_EraseRootFromParent_Done,
26187 /* 72154 */ // Label 2250: @72154
26188 /* 72154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2251*/ GIMT_Encode4(72206), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4924 //
26189 /* 72161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26190 /* 72165 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3908:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26191 /* 72165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26192 /* 72168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26193 /* 72172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26194 /* 72177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8),
26195 /* 72180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26196 /* 72182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26197 /* 72184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26198 /* 72186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26199 /* 72189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26200 /* 72195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26201 /* 72201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26202 /* 72204 */ GIR_RootConstrainSelectedInstOperands,
26203 /* 72205 */ // GIR_Coverage, 4924,
26204 /* 72205 */ GIR_EraseRootFromParent_Done,
26205 /* 72206 */ // Label 2251: @72206
26206 /* 72206 */ GIM_Reject,
26207 /* 72207 */ // Label 2249: @72207
26208 /* 72207 */ GIM_Reject,
26209 /* 72208 */ // Label 2247: @72208
26210 /* 72208 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(72339),
26211 /* 72213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26212 /* 72216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26213 /* 72219 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26214 /* 72222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26215 /* 72226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26216 /* 72230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26217 /* 72234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2253*/ GIMT_Encode4(72286), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4926 //
26218 /* 72241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26219 /* 72245 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3908:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26220 /* 72245 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26221 /* 72248 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26222 /* 72252 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26223 /* 72257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16),
26224 /* 72260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26225 /* 72262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26226 /* 72264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26227 /* 72266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26228 /* 72269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26229 /* 72275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26230 /* 72281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26231 /* 72284 */ GIR_RootConstrainSelectedInstOperands,
26232 /* 72285 */ // GIR_Coverage, 4926,
26233 /* 72285 */ GIR_EraseRootFromParent_Done,
26234 /* 72286 */ // Label 2253: @72286
26235 /* 72286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2254*/ GIMT_Encode4(72338), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4928 //
26236 /* 72293 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26237 /* 72297 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3908:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26238 /* 72297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26239 /* 72300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26240 /* 72304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26241 /* 72309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16),
26242 /* 72312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26243 /* 72314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26244 /* 72316 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26245 /* 72318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26246 /* 72321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26247 /* 72327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26248 /* 72333 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26249 /* 72336 */ GIR_RootConstrainSelectedInstOperands,
26250 /* 72337 */ // GIR_Coverage, 4928,
26251 /* 72337 */ GIR_EraseRootFromParent_Done,
26252 /* 72338 */ // Label 2254: @72338
26253 /* 72338 */ GIM_Reject,
26254 /* 72339 */ // Label 2252: @72339
26255 /* 72339 */ GIM_Reject,
26256 /* 72340 */ // Label 2248: @72340
26257 /* 72340 */ GIM_Reject,
26258 /* 72341 */ // Label 2245: @72341
26259 /* 72341 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(72779),
26260 /* 72346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26261 /* 72351 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2259*/ GIMT_Encode4(72778),
26262 /* 72362 */ /*GILLT_v16s8*//*Label 2256*/ GIMT_Encode4(72382), GIMT_Encode4(0),
26263 /* 72370 */ /*GILLT_v8s16*//*Label 2257*/ GIMT_Encode4(72514), GIMT_Encode4(0),
26264 /* 72378 */ /*GILLT_v4s32*//*Label 2258*/ GIMT_Encode4(72646),
26265 /* 72382 */ // Label 2256: @72382
26266 /* 72382 */ GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(72513),
26267 /* 72387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26268 /* 72390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26269 /* 72393 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26270 /* 72396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26271 /* 72400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26272 /* 72404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26273 /* 72408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2261*/ GIMT_Encode4(72460), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4955 //
26274 /* 72415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26275 /* 72419 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3906:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26276 /* 72419 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26277 /* 72422 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26278 /* 72426 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26279 /* 72431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
26280 /* 72434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26281 /* 72436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26282 /* 72438 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26283 /* 72440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26284 /* 72443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26285 /* 72449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26286 /* 72455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26287 /* 72458 */ GIR_RootConstrainSelectedInstOperands,
26288 /* 72459 */ // GIR_Coverage, 4955,
26289 /* 72459 */ GIR_EraseRootFromParent_Done,
26290 /* 72460 */ // Label 2261: @72460
26291 /* 72460 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2262*/ GIMT_Encode4(72512), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4970 //
26292 /* 72467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26293 /* 72471 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3906:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26294 /* 72471 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26295 /* 72474 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26296 /* 72478 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26297 /* 72483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
26298 /* 72486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26299 /* 72488 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26300 /* 72490 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26301 /* 72492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26302 /* 72495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26303 /* 72501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26304 /* 72507 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26305 /* 72510 */ GIR_RootConstrainSelectedInstOperands,
26306 /* 72511 */ // GIR_Coverage, 4970,
26307 /* 72511 */ GIR_EraseRootFromParent_Done,
26308 /* 72512 */ // Label 2262: @72512
26309 /* 72512 */ GIM_Reject,
26310 /* 72513 */ // Label 2260: @72513
26311 /* 72513 */ GIM_Reject,
26312 /* 72514 */ // Label 2257: @72514
26313 /* 72514 */ GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(72645),
26314 /* 72519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26315 /* 72522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26316 /* 72525 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26317 /* 72528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26318 /* 72532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26319 /* 72536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26320 /* 72540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2264*/ GIMT_Encode4(72592), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4962 //
26321 /* 72547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26322 /* 72551 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3906:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26323 /* 72551 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26324 /* 72554 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26325 /* 72558 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26326 /* 72563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
26327 /* 72566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26328 /* 72568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26329 /* 72570 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26330 /* 72572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26331 /* 72575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26332 /* 72581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26333 /* 72587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26334 /* 72590 */ GIR_RootConstrainSelectedInstOperands,
26335 /* 72591 */ // GIR_Coverage, 4962,
26336 /* 72591 */ GIR_EraseRootFromParent_Done,
26337 /* 72592 */ // Label 2264: @72592
26338 /* 72592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2265*/ GIMT_Encode4(72644), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4974 //
26339 /* 72599 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26340 /* 72603 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3906:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26341 /* 72603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26342 /* 72606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26343 /* 72610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26344 /* 72615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
26345 /* 72618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26346 /* 72620 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26347 /* 72622 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26348 /* 72624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26349 /* 72627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26350 /* 72633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26351 /* 72639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26352 /* 72642 */ GIR_RootConstrainSelectedInstOperands,
26353 /* 72643 */ // GIR_Coverage, 4974,
26354 /* 72643 */ GIR_EraseRootFromParent_Done,
26355 /* 72644 */ // Label 2265: @72644
26356 /* 72644 */ GIM_Reject,
26357 /* 72645 */ // Label 2263: @72645
26358 /* 72645 */ GIM_Reject,
26359 /* 72646 */ // Label 2258: @72646
26360 /* 72646 */ GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(72777),
26361 /* 72651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26362 /* 72654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26363 /* 72657 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26364 /* 72660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26365 /* 72664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26366 /* 72668 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26367 /* 72672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2267*/ GIMT_Encode4(72724), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4966 //
26368 /* 72679 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26369 /* 72683 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3906:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26370 /* 72683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26371 /* 72686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26372 /* 72690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26373 /* 72695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
26374 /* 72698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26375 /* 72700 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26376 /* 72702 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26377 /* 72704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26378 /* 72707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26379 /* 72713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26380 /* 72719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26381 /* 72722 */ GIR_RootConstrainSelectedInstOperands,
26382 /* 72723 */ // GIR_Coverage, 4966,
26383 /* 72723 */ GIR_EraseRootFromParent_Done,
26384 /* 72724 */ // Label 2267: @72724
26385 /* 72724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2268*/ GIMT_Encode4(72776), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4978 //
26386 /* 72731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26387 /* 72735 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3906:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26388 /* 72735 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26389 /* 72738 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26390 /* 72742 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26391 /* 72747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
26392 /* 72750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26393 /* 72752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26394 /* 72754 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26395 /* 72756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26396 /* 72759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26397 /* 72765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26398 /* 72771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26399 /* 72774 */ GIR_RootConstrainSelectedInstOperands,
26400 /* 72775 */ // GIR_Coverage, 4978,
26401 /* 72775 */ GIR_EraseRootFromParent_Done,
26402 /* 72776 */ // Label 2268: @72776
26403 /* 72776 */ GIM_Reject,
26404 /* 72777 */ // Label 2266: @72777
26405 /* 72777 */ GIM_Reject,
26406 /* 72778 */ // Label 2259: @72778
26407 /* 72778 */ GIM_Reject,
26408 /* 72779 */ // Label 2255: @72779
26409 /* 72779 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(73217),
26410 /* 72784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26411 /* 72789 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2273*/ GIMT_Encode4(73216),
26412 /* 72800 */ /*GILLT_v16s8*//*Label 2270*/ GIMT_Encode4(72820), GIMT_Encode4(0),
26413 /* 72808 */ /*GILLT_v8s16*//*Label 2271*/ GIMT_Encode4(72952), GIMT_Encode4(0),
26414 /* 72816 */ /*GILLT_v4s32*//*Label 2272*/ GIMT_Encode4(73084),
26415 /* 72820 */ // Label 2270: @72820
26416 /* 72820 */ GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(72951),
26417 /* 72825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26418 /* 72828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26419 /* 72831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26420 /* 72834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26421 /* 72838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26422 /* 72842 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26423 /* 72846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2275*/ GIMT_Encode4(72898), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4979 //
26424 /* 72853 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26425 /* 72857 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3946:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26426 /* 72857 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26427 /* 72860 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26428 /* 72864 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26429 /* 72869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8),
26430 /* 72872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26431 /* 72874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26432 /* 72876 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26433 /* 72878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26434 /* 72881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26435 /* 72887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26436 /* 72893 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26437 /* 72896 */ GIR_RootConstrainSelectedInstOperands,
26438 /* 72897 */ // GIR_Coverage, 4979,
26439 /* 72897 */ GIR_EraseRootFromParent_Done,
26440 /* 72898 */ // Label 2275: @72898
26441 /* 72898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2276*/ GIMT_Encode4(72950), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4985 //
26442 /* 72905 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26443 /* 72909 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3946:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26444 /* 72909 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26445 /* 72912 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26446 /* 72916 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26447 /* 72921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8),
26448 /* 72924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26449 /* 72926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26450 /* 72928 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26451 /* 72930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26452 /* 72933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26453 /* 72939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26454 /* 72945 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26455 /* 72948 */ GIR_RootConstrainSelectedInstOperands,
26456 /* 72949 */ // GIR_Coverage, 4985,
26457 /* 72949 */ GIR_EraseRootFromParent_Done,
26458 /* 72950 */ // Label 2276: @72950
26459 /* 72950 */ GIM_Reject,
26460 /* 72951 */ // Label 2274: @72951
26461 /* 72951 */ GIM_Reject,
26462 /* 72952 */ // Label 2271: @72952
26463 /* 72952 */ GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(73083),
26464 /* 72957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26465 /* 72960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26466 /* 72963 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26467 /* 72966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26468 /* 72970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26469 /* 72974 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26470 /* 72978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2278*/ GIMT_Encode4(73030), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4981 //
26471 /* 72985 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26472 /* 72989 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3946:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26473 /* 72989 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26474 /* 72992 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26475 /* 72996 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26476 /* 73001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16),
26477 /* 73004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26478 /* 73006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26479 /* 73008 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26480 /* 73010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26481 /* 73013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26482 /* 73019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26483 /* 73025 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26484 /* 73028 */ GIR_RootConstrainSelectedInstOperands,
26485 /* 73029 */ // GIR_Coverage, 4981,
26486 /* 73029 */ GIR_EraseRootFromParent_Done,
26487 /* 73030 */ // Label 2278: @73030
26488 /* 73030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2279*/ GIMT_Encode4(73082), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4987 //
26489 /* 73037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26490 /* 73041 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3946:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26491 /* 73041 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26492 /* 73044 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26493 /* 73048 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26494 /* 73053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16),
26495 /* 73056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26496 /* 73058 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26497 /* 73060 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26498 /* 73062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26499 /* 73065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26500 /* 73071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26501 /* 73077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26502 /* 73080 */ GIR_RootConstrainSelectedInstOperands,
26503 /* 73081 */ // GIR_Coverage, 4987,
26504 /* 73081 */ GIR_EraseRootFromParent_Done,
26505 /* 73082 */ // Label 2279: @73082
26506 /* 73082 */ GIM_Reject,
26507 /* 73083 */ // Label 2277: @73083
26508 /* 73083 */ GIM_Reject,
26509 /* 73084 */ // Label 2272: @73084
26510 /* 73084 */ GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(73215),
26511 /* 73089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26512 /* 73092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26513 /* 73095 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26514 /* 73098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26515 /* 73102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26516 /* 73106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26517 /* 73110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2281*/ GIMT_Encode4(73162), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4983 //
26518 /* 73117 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26519 /* 73121 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3946:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26520 /* 73121 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26521 /* 73124 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26522 /* 73128 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26523 /* 73133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32),
26524 /* 73136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26525 /* 73138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26526 /* 73140 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26527 /* 73142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26528 /* 73145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26529 /* 73151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26530 /* 73157 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26531 /* 73160 */ GIR_RootConstrainSelectedInstOperands,
26532 /* 73161 */ // GIR_Coverage, 4983,
26533 /* 73161 */ GIR_EraseRootFromParent_Done,
26534 /* 73162 */ // Label 2281: @73162
26535 /* 73162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2282*/ GIMT_Encode4(73214), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4989 //
26536 /* 73169 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26537 /* 73173 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3946:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26538 /* 73173 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26539 /* 73176 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26540 /* 73180 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26541 /* 73185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32),
26542 /* 73188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26543 /* 73190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26544 /* 73192 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26545 /* 73194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26546 /* 73197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26547 /* 73203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26548 /* 73209 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26549 /* 73212 */ GIR_RootConstrainSelectedInstOperands,
26550 /* 73213 */ // GIR_Coverage, 4989,
26551 /* 73213 */ GIR_EraseRootFromParent_Done,
26552 /* 73214 */ // Label 2282: @73214
26553 /* 73214 */ GIM_Reject,
26554 /* 73215 */ // Label 2280: @73215
26555 /* 73215 */ GIM_Reject,
26556 /* 73216 */ // Label 2273: @73216
26557 /* 73216 */ GIM_Reject,
26558 /* 73217 */ // Label 2269: @73217
26559 /* 73217 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(73326),
26560 /* 73222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
26561 /* 73227 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26562 /* 73230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26563 /* 73233 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26564 /* 73236 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26565 /* 73239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26566 /* 73243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26567 /* 73247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26568 /* 73251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2284*/ GIMT_Encode4(73288), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5040 //
26569 /* 73258 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26570 /* 73262 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3861:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26571 /* 73262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh),
26572 /* 73265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26573 /* 73267 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
26574 /* 73269 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
26575 /* 73271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26576 /* 73274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26577 /* 73280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26578 /* 73286 */ GIR_RootConstrainSelectedInstOperands,
26579 /* 73287 */ // GIR_Coverage, 5040,
26580 /* 73287 */ GIR_EraseRootFromParent_Done,
26581 /* 73288 */ // Label 2284: @73288
26582 /* 73288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2285*/ GIMT_Encode4(73325), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5046 //
26583 /* 73295 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26584 /* 73299 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3861:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26585 /* 73299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th),
26586 /* 73302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26587 /* 73304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
26588 /* 73306 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
26589 /* 73308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26590 /* 73311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26591 /* 73317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26592 /* 73323 */ GIR_RootConstrainSelectedInstOperands,
26593 /* 73324 */ // GIR_Coverage, 5046,
26594 /* 73324 */ GIR_EraseRootFromParent_Done,
26595 /* 73325 */ // Label 2285: @73325
26596 /* 73325 */ GIM_Reject,
26597 /* 73326 */ // Label 2283: @73326
26598 /* 73326 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(73620),
26599 /* 73331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
26600 /* 73336 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2289*/ GIMT_Encode4(73619),
26601 /* 73347 */ /*GILLT_v4s32*//*Label 2287*/ GIMT_Encode4(73355),
26602 /* 73351 */ /*GILLT_v2s64*//*Label 2288*/ GIMT_Encode4(73487),
26603 /* 73355 */ // Label 2287: @73355
26604 /* 73355 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(73486),
26605 /* 73360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26606 /* 73363 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26607 /* 73366 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26608 /* 73369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26609 /* 73373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26610 /* 73377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26611 /* 73381 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2291*/ GIMT_Encode4(73433), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5064 //
26612 /* 73388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26613 /* 73392 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3916:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26614 /* 73392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26615 /* 73395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26616 /* 73399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26617 /* 73404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh),
26618 /* 73407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26619 /* 73409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26620 /* 73411 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26621 /* 73413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26622 /* 73416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26623 /* 73422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26624 /* 73428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26625 /* 73431 */ GIR_RootConstrainSelectedInstOperands,
26626 /* 73432 */ // GIR_Coverage, 5064,
26627 /* 73432 */ GIR_EraseRootFromParent_Done,
26628 /* 73433 */ // Label 2291: @73433
26629 /* 73433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2292*/ GIMT_Encode4(73485), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5066 //
26630 /* 73440 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26631 /* 73444 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3916:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26632 /* 73444 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26633 /* 73447 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26634 /* 73451 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26635 /* 73456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th),
26636 /* 73459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26637 /* 73461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26638 /* 73463 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26639 /* 73465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26640 /* 73468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26641 /* 73474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26642 /* 73480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26643 /* 73483 */ GIR_RootConstrainSelectedInstOperands,
26644 /* 73484 */ // GIR_Coverage, 5066,
26645 /* 73484 */ GIR_EraseRootFromParent_Done,
26646 /* 73485 */ // Label 2292: @73485
26647 /* 73485 */ GIM_Reject,
26648 /* 73486 */ // Label 2290: @73486
26649 /* 73486 */ GIM_Reject,
26650 /* 73487 */ // Label 2288: @73487
26651 /* 73487 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(73618),
26652 /* 73492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26653 /* 73495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26654 /* 73498 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26655 /* 73501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26656 /* 73505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26657 /* 73509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26658 /* 73513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2294*/ GIMT_Encode4(73565), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5068 //
26659 /* 73520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26660 /* 73524 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3916:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26661 /* 73524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26662 /* 73527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26663 /* 73531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26664 /* 73536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh),
26665 /* 73539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26666 /* 73541 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26667 /* 73543 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26668 /* 73545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26669 /* 73548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26670 /* 73554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26671 /* 73560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26672 /* 73563 */ GIR_RootConstrainSelectedInstOperands,
26673 /* 73564 */ // GIR_Coverage, 5068,
26674 /* 73564 */ GIR_EraseRootFromParent_Done,
26675 /* 73565 */ // Label 2294: @73565
26676 /* 73565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2295*/ GIMT_Encode4(73617), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5070 //
26677 /* 73572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26678 /* 73576 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3916:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26679 /* 73576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26680 /* 73579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26681 /* 73583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26682 /* 73588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th),
26683 /* 73591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26684 /* 73593 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26685 /* 73595 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26686 /* 73597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26687 /* 73600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26688 /* 73606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26689 /* 73612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26690 /* 73615 */ GIR_RootConstrainSelectedInstOperands,
26691 /* 73616 */ // GIR_Coverage, 5070,
26692 /* 73616 */ GIR_EraseRootFromParent_Done,
26693 /* 73617 */ // Label 2295: @73617
26694 /* 73617 */ GIM_Reject,
26695 /* 73618 */ // Label 2293: @73618
26696 /* 73618 */ GIM_Reject,
26697 /* 73619 */ // Label 2289: @73619
26698 /* 73619 */ GIM_Reject,
26699 /* 73620 */ // Label 2286: @73620
26700 /* 73620 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(73810),
26701 /* 73625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
26702 /* 73630 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2299*/ GIMT_Encode4(73809),
26703 /* 73641 */ /*GILLT_v8s16*//*Label 2297*/ GIMT_Encode4(73653), GIMT_Encode4(0),
26704 /* 73649 */ /*GILLT_v4s32*//*Label 2298*/ GIMT_Encode4(73731),
26705 /* 73653 */ // Label 2297: @73653
26706 /* 73653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2300*/ GIMT_Encode4(73730), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4450 //
26707 /* 73660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26708 /* 73663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26709 /* 73666 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
26710 /* 73669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26711 /* 73673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26712 /* 73677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26713 /* 73681 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
26714 /* 73685 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26715 /* 73690 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26716 /* 73694 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26717 /* 73698 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26718 /* 73700 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3781:{ *:[iPTR] }, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
26719 /* 73700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
26720 /* 73703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26721 /* 73705 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26722 /* 73707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
26723 /* 73711 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
26724 /* 73713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26725 /* 73716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26726 /* 73722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26727 /* 73728 */ GIR_RootConstrainSelectedInstOperands,
26728 /* 73729 */ // GIR_Coverage, 4450,
26729 /* 73729 */ GIR_EraseRootFromParent_Done,
26730 /* 73730 */ // Label 2300: @73730
26731 /* 73730 */ GIM_Reject,
26732 /* 73731 */ // Label 2298: @73731
26733 /* 73731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2301*/ GIMT_Encode4(73808), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4436 //
26734 /* 73738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26735 /* 73741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26736 /* 73744 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26737 /* 73747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26738 /* 73751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26739 /* 73755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26740 /* 73759 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
26741 /* 73763 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26742 /* 73768 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26743 /* 73772 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26744 /* 73776 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26745 /* 73778 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3781:{ *:[iPTR] }, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
26746 /* 73778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
26747 /* 73781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26748 /* 73783 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26749 /* 73785 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
26750 /* 73789 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
26751 /* 73791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26752 /* 73794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26753 /* 73800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26754 /* 73806 */ GIR_RootConstrainSelectedInstOperands,
26755 /* 73807 */ // GIR_Coverage, 4436,
26756 /* 73807 */ GIR_EraseRootFromParent_Done,
26757 /* 73808 */ // Label 2301: @73808
26758 /* 73808 */ GIM_Reject,
26759 /* 73809 */ // Label 2299: @73809
26760 /* 73809 */ GIM_Reject,
26761 /* 73810 */ // Label 2296: @73810
26762 /* 73810 */ GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(74010),
26763 /* 73815 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
26764 /* 73820 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2305*/ GIMT_Encode4(74009),
26765 /* 73831 */ /*GILLT_v8s16*//*Label 2303*/ GIMT_Encode4(73843), GIMT_Encode4(0),
26766 /* 73839 */ /*GILLT_v4s32*//*Label 2304*/ GIMT_Encode4(73926),
26767 /* 73843 */ // Label 2303: @73843
26768 /* 73843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2306*/ GIMT_Encode4(73925), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4894 //
26769 /* 73850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26770 /* 73853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26771 /* 73856 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
26772 /* 73859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26773 /* 73863 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26774 /* 73867 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26775 /* 73871 */ // MIs[1] Operand 1
26776 /* 73871 */ // No operand predicates
26777 /* 73871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26778 /* 73875 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26779 /* 73879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26780 /* 73881 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
26781 /* 73881 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26782 /* 73884 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26783 /* 73888 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26784 /* 73893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16),
26785 /* 73896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26786 /* 73898 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26787 /* 73900 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
26788 /* 73902 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26789 /* 73905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26790 /* 73908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26791 /* 73914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26792 /* 73920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26793 /* 73923 */ GIR_RootConstrainSelectedInstOperands,
26794 /* 73924 */ // GIR_Coverage, 4894,
26795 /* 73924 */ GIR_EraseRootFromParent_Done,
26796 /* 73925 */ // Label 2306: @73925
26797 /* 73925 */ GIM_Reject,
26798 /* 73926 */ // Label 2304: @73926
26799 /* 73926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2307*/ GIMT_Encode4(74008), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4896 //
26800 /* 73933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26801 /* 73936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26802 /* 73939 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26803 /* 73942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26804 /* 73946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26805 /* 73950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26806 /* 73954 */ // MIs[1] Operand 1
26807 /* 73954 */ // No operand predicates
26808 /* 73954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26809 /* 73958 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26810 /* 73962 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26811 /* 73964 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
26812 /* 73964 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26813 /* 73967 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26814 /* 73971 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26815 /* 73976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32),
26816 /* 73979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26817 /* 73981 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26818 /* 73983 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
26819 /* 73985 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26820 /* 73988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26821 /* 73991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26822 /* 73997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26823 /* 74003 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26824 /* 74006 */ GIR_RootConstrainSelectedInstOperands,
26825 /* 74007 */ // GIR_Coverage, 4896,
26826 /* 74007 */ GIR_EraseRootFromParent_Done,
26827 /* 74008 */ // Label 2307: @74008
26828 /* 74008 */ GIM_Reject,
26829 /* 74009 */ // Label 2305: @74009
26830 /* 74009 */ GIM_Reject,
26831 /* 74010 */ // Label 2302: @74010
26832 /* 74010 */ GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(74200),
26833 /* 74015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
26834 /* 74020 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2311*/ GIMT_Encode4(74199),
26835 /* 74031 */ /*GILLT_v8s16*//*Label 2309*/ GIMT_Encode4(74043), GIMT_Encode4(0),
26836 /* 74039 */ /*GILLT_v4s32*//*Label 2310*/ GIMT_Encode4(74121),
26837 /* 74043 */ // Label 2309: @74043
26838 /* 74043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2312*/ GIMT_Encode4(74120), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4451 //
26839 /* 74050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26840 /* 74053 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26841 /* 74056 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
26842 /* 74059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26843 /* 74063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26844 /* 74067 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
26845 /* 74071 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26846 /* 74075 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
26847 /* 74079 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26848 /* 74084 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26849 /* 74088 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26850 /* 74090 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3781:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
26851 /* 74090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
26852 /* 74093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26853 /* 74095 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26854 /* 74097 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
26855 /* 74099 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
26856 /* 74103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26857 /* 74106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26858 /* 74112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26859 /* 74118 */ GIR_RootConstrainSelectedInstOperands,
26860 /* 74119 */ // GIR_Coverage, 4451,
26861 /* 74119 */ GIR_EraseRootFromParent_Done,
26862 /* 74120 */ // Label 2312: @74120
26863 /* 74120 */ GIM_Reject,
26864 /* 74121 */ // Label 2310: @74121
26865 /* 74121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2313*/ GIMT_Encode4(74198), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4437 //
26866 /* 74128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26867 /* 74131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26868 /* 74134 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26869 /* 74137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26870 /* 74141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26871 /* 74145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
26872 /* 74149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26873 /* 74153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
26874 /* 74157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26875 /* 74162 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26876 /* 74166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26877 /* 74168 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3781:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
26878 /* 74168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
26879 /* 74171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26880 /* 74173 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26881 /* 74175 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
26882 /* 74177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
26883 /* 74181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26884 /* 74184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26885 /* 74190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26886 /* 74196 */ GIR_RootConstrainSelectedInstOperands,
26887 /* 74197 */ // GIR_Coverage, 4437,
26888 /* 74197 */ GIR_EraseRootFromParent_Done,
26889 /* 74198 */ // Label 2313: @74198
26890 /* 74198 */ GIM_Reject,
26891 /* 74199 */ // Label 2311: @74199
26892 /* 74199 */ GIM_Reject,
26893 /* 74200 */ // Label 2308: @74200
26894 /* 74200 */ GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(74313),
26895 /* 74205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
26896 /* 74210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26897 /* 74213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26898 /* 74216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26899 /* 74219 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26900 /* 74222 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2315*/ GIMT_Encode4(74267), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 145 //
26901 /* 74229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26902 /* 74233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26903 /* 74237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26904 /* 74241 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26905 /* 74245 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
26906 /* 74245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8),
26907 /* 74248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26908 /* 74250 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26909 /* 74252 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26910 /* 74254 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26911 /* 74256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26912 /* 74259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26913 /* 74265 */ GIR_RootConstrainSelectedInstOperands,
26914 /* 74266 */ // GIR_Coverage, 145,
26915 /* 74266 */ GIR_EraseRootFromParent_Done,
26916 /* 74267 */ // Label 2315: @74267
26917 /* 74267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2316*/ GIMT_Encode4(74312), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 468 //
26918 /* 74274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26919 /* 74278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26920 /* 74282 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26921 /* 74286 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26922 /* 74290 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26923 /* 74290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8),
26924 /* 74293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26925 /* 74295 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26926 /* 74297 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26927 /* 74299 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26928 /* 74301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26929 /* 74304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26930 /* 74310 */ GIR_RootConstrainSelectedInstOperands,
26931 /* 74311 */ // GIR_Coverage, 468,
26932 /* 74311 */ GIR_EraseRootFromParent_Done,
26933 /* 74312 */ // Label 2316: @74312
26934 /* 74312 */ GIM_Reject,
26935 /* 74313 */ // Label 2314: @74313
26936 /* 74313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2317*/ GIMT_Encode4(74375), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 527 //
26937 /* 74320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
26938 /* 74325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26939 /* 74328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26940 /* 74331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26941 /* 74334 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26942 /* 74337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26943 /* 74341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26944 /* 74345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26945 /* 74349 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26946 /* 74353 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26947 /* 74353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD),
26948 /* 74356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26949 /* 74358 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26950 /* 74360 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26951 /* 74362 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26952 /* 74364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26953 /* 74367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26954 /* 74373 */ GIR_RootConstrainSelectedInstOperands,
26955 /* 74374 */ // GIR_Coverage, 527,
26956 /* 74374 */ GIR_EraseRootFromParent_Done,
26957 /* 74375 */ // Label 2317: @74375
26958 /* 74375 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2318*/ GIMT_Encode4(74437), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 528 //
26959 /* 74382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
26960 /* 74387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26961 /* 74390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26962 /* 74393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26963 /* 74396 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26964 /* 74399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26965 /* 74403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26966 /* 74407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26967 /* 74411 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26968 /* 74415 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26969 /* 74415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX),
26970 /* 74418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26971 /* 74420 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26972 /* 74422 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26973 /* 74424 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26974 /* 74426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26975 /* 74429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26976 /* 74435 */ GIR_RootConstrainSelectedInstOperands,
26977 /* 74436 */ // GIR_Coverage, 528,
26978 /* 74436 */ GIR_EraseRootFromParent_Done,
26979 /* 74437 */ // Label 2318: @74437
26980 /* 74437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2319*/ GIMT_Encode4(74499), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 529 //
26981 /* 74444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
26982 /* 74449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26983 /* 74452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26984 /* 74455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26985 /* 74458 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26986 /* 74461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26987 /* 74465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26988 /* 74469 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26989 /* 74473 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26990 /* 74477 */ // (intrinsic_wo_chain:{ *:[i32] } 4141:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26991 /* 74477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD),
26992 /* 74480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26993 /* 74482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26994 /* 74484 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26995 /* 74486 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26996 /* 74488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26997 /* 74491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26998 /* 74497 */ GIR_RootConstrainSelectedInstOperands,
26999 /* 74498 */ // GIR_Coverage, 529,
27000 /* 74498 */ GIR_EraseRootFromParent_Done,
27001 /* 74499 */ // Label 2319: @74499
27002 /* 74499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2320*/ GIMT_Encode4(74561), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 530 //
27003 /* 74506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
27004 /* 74511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27005 /* 74514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27006 /* 74517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27007 /* 74520 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27008 /* 74523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27009 /* 74527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27010 /* 74531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27011 /* 74535 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27012 /* 74539 */ // (intrinsic_wo_chain:{ *:[i32] } 4142:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27013 /* 74539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX),
27014 /* 74542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27015 /* 74544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27016 /* 74546 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27017 /* 74548 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27018 /* 74550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27019 /* 74553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27020 /* 74559 */ GIR_RootConstrainSelectedInstOperands,
27021 /* 74560 */ // GIR_Coverage, 530,
27022 /* 74560 */ GIR_EraseRootFromParent_Done,
27023 /* 74561 */ // Label 2320: @74561
27024 /* 74561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2321*/ GIMT_Encode4(74614), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1113 //
27025 /* 74568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
27026 /* 74573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
27027 /* 74576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27028 /* 74579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27029 /* 74582 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27030 /* 74585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27031 /* 74589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27032 /* 74593 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27033 /* 74597 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27034 /* 74601 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3994:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27035 /* 74601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD),
27036 /* 74604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27037 /* 74606 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27038 /* 74608 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27039 /* 74610 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27040 /* 74612 */ GIR_RootConstrainSelectedInstOperands,
27041 /* 74613 */ // GIR_Coverage, 1113,
27042 /* 74613 */ GIR_EraseRootFromParent_Done,
27043 /* 74614 */ // Label 2321: @74614
27044 /* 74614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2322*/ GIMT_Encode4(74667), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1114 //
27045 /* 74621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
27046 /* 74626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
27047 /* 74629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27048 /* 74632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27049 /* 74635 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27050 /* 74638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27051 /* 74642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27052 /* 74646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27053 /* 74650 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27054 /* 74654 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3982:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27055 /* 74654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD),
27056 /* 74657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27057 /* 74659 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27058 /* 74661 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27059 /* 74663 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27060 /* 74665 */ GIR_RootConstrainSelectedInstOperands,
27061 /* 74666 */ // GIR_Coverage, 1114,
27062 /* 74666 */ GIR_EraseRootFromParent_Done,
27063 /* 74667 */ // Label 2322: @74667
27064 /* 74667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2323*/ GIMT_Encode4(74720), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1115 //
27065 /* 74674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
27066 /* 74679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27067 /* 74682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27068 /* 74685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27069 /* 74688 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27070 /* 74691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27071 /* 74695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27072 /* 74699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27073 /* 74703 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27074 /* 74707 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3994:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27075 /* 74707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ),
27076 /* 74710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27077 /* 74712 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27078 /* 74714 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27079 /* 74716 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27080 /* 74718 */ GIR_RootConstrainSelectedInstOperands,
27081 /* 74719 */ // GIR_Coverage, 1115,
27082 /* 74719 */ GIR_EraseRootFromParent_Done,
27083 /* 74720 */ // Label 2323: @74720
27084 /* 74720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2324*/ GIMT_Encode4(74773), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1116 //
27085 /* 74727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
27086 /* 74732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27087 /* 74735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27088 /* 74738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27089 /* 74741 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27090 /* 74744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27091 /* 74748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27092 /* 74752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27093 /* 74756 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27094 /* 74760 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3982:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27095 /* 74760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ),
27096 /* 74763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27097 /* 74765 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27098 /* 74767 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27099 /* 74769 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27100 /* 74771 */ GIR_RootConstrainSelectedInstOperands,
27101 /* 74772 */ // GIR_Coverage, 1116,
27102 /* 74772 */ GIR_EraseRootFromParent_Done,
27103 /* 74773 */ // Label 2324: @74773
27104 /* 74773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2325*/ GIMT_Encode4(74826), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1117 //
27105 /* 74780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla),
27106 /* 74785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27107 /* 74788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27108 /* 74791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27109 /* 74794 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27110 /* 74797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27111 /* 74801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27112 /* 74805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27113 /* 74809 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27114 /* 74813 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27115 /* 74813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA),
27116 /* 74816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27117 /* 74818 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27118 /* 74820 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27119 /* 74822 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27120 /* 74824 */ GIR_RootConstrainSelectedInstOperands,
27121 /* 74825 */ // GIR_Coverage, 1117,
27122 /* 74825 */ GIR_EraseRootFromParent_Done,
27123 /* 74826 */ // Label 2325: @74826
27124 /* 74826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2326*/ GIMT_Encode4(74879), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1118 //
27125 /* 74833 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla),
27126 /* 74838 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27127 /* 74841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27128 /* 74844 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27129 /* 74847 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27130 /* 74850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27131 /* 74854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27132 /* 74858 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27133 /* 74862 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27134 /* 74866 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3995:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27135 /* 74866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA),
27136 /* 74869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27137 /* 74871 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27138 /* 74873 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27139 /* 74875 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27140 /* 74877 */ GIR_RootConstrainSelectedInstOperands,
27141 /* 74878 */ // GIR_Coverage, 1118,
27142 /* 74878 */ GIR_EraseRootFromParent_Done,
27143 /* 74879 */ // Label 2326: @74879
27144 /* 74879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2327*/ GIMT_Encode4(74932), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1119 //
27145 /* 74886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla),
27146 /* 74891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27147 /* 74894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27148 /* 74897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27149 /* 74900 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27150 /* 74903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27151 /* 74907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27152 /* 74911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27153 /* 74915 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27154 /* 74919 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3997:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27155 /* 74919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA),
27156 /* 74922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27157 /* 74924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27158 /* 74926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27159 /* 74928 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27160 /* 74930 */ GIR_RootConstrainSelectedInstOperands,
27161 /* 74931 */ // GIR_Coverage, 1119,
27162 /* 74931 */ GIR_EraseRootFromParent_Done,
27163 /* 74932 */ // Label 2327: @74932
27164 /* 74932 */ GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(75054),
27165 /* 74937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
27166 /* 74942 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 2331*/ GIMT_Encode4(75053),
27167 /* 74953 */ /*GILLT_v2s32*//*Label 2329*/ GIMT_Encode4(74961),
27168 /* 74957 */ /*GILLT_v4s32*//*Label 2330*/ GIMT_Encode4(75007),
27169 /* 74961 */ // Label 2329: @74961
27170 /* 74961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2332*/ GIMT_Encode4(75006), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1120 //
27171 /* 74968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27172 /* 74971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27173 /* 74974 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27174 /* 74977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27175 /* 74981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27176 /* 74985 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27177 /* 74989 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27178 /* 74993 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3996:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27179 /* 74993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD),
27180 /* 74996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27181 /* 74998 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27182 /* 75000 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27183 /* 75002 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27184 /* 75004 */ GIR_RootConstrainSelectedInstOperands,
27185 /* 75005 */ // GIR_Coverage, 1120,
27186 /* 75005 */ GIR_EraseRootFromParent_Done,
27187 /* 75006 */ // Label 2332: @75006
27188 /* 75006 */ GIM_Reject,
27189 /* 75007 */ // Label 2330: @75007
27190 /* 75007 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2333*/ GIMT_Encode4(75052), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1121 //
27191 /* 75014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27192 /* 75017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27193 /* 75020 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27194 /* 75023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27195 /* 75027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27196 /* 75031 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27197 /* 75035 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27198 /* 75039 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3996:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27199 /* 75039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ),
27200 /* 75042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27201 /* 75044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27202 /* 75046 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27203 /* 75048 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27204 /* 75050 */ GIR_RootConstrainSelectedInstOperands,
27205 /* 75051 */ // GIR_Coverage, 1121,
27206 /* 75051 */ GIR_EraseRootFromParent_Done,
27207 /* 75052 */ // Label 2333: @75052
27208 /* 75052 */ GIM_Reject,
27209 /* 75053 */ // Label 2331: @75053
27210 /* 75053 */ GIM_Reject,
27211 /* 75054 */ // Label 2328: @75054
27212 /* 75054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2334*/ GIMT_Encode4(75116), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1852 //
27213 /* 75061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1),
27214 /* 75066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
27215 /* 75069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
27216 /* 75072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27217 /* 75075 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27218 /* 75078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27219 /* 75082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27220 /* 75086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27221 /* 75090 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27222 /* 75094 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4108:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27223 /* 75094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1),
27224 /* 75097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27225 /* 75099 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
27226 /* 75101 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27227 /* 75103 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27228 /* 75105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27229 /* 75108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27230 /* 75114 */ GIR_RootConstrainSelectedInstOperands,
27231 /* 75115 */ // GIR_Coverage, 1852,
27232 /* 75115 */ GIR_EraseRootFromParent_Done,
27233 /* 75116 */ // Label 2334: @75116
27234 /* 75116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2335*/ GIMT_Encode4(75169), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1907 //
27235 /* 75123 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0),
27236 /* 75128 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27237 /* 75131 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27238 /* 75134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27239 /* 75137 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27240 /* 75140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27241 /* 75144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27242 /* 75148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27243 /* 75152 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27244 /* 75156 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27245 /* 75156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0),
27246 /* 75159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27247 /* 75161 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27248 /* 75163 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27249 /* 75165 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27250 /* 75167 */ GIR_RootConstrainSelectedInstOperands,
27251 /* 75168 */ // GIR_Coverage, 1907,
27252 /* 75168 */ GIR_EraseRootFromParent_Done,
27253 /* 75169 */ // Label 2335: @75169
27254 /* 75169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2336*/ GIMT_Encode4(75222), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1908 //
27255 /* 75176 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h),
27256 /* 75181 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27257 /* 75184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27258 /* 75187 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27259 /* 75190 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27260 /* 75193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27261 /* 75197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27262 /* 75201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27263 /* 75205 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27264 /* 75209 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27265 /* 75209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H),
27266 /* 75212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27267 /* 75214 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27268 /* 75216 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27269 /* 75218 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27270 /* 75220 */ GIR_RootConstrainSelectedInstOperands,
27271 /* 75221 */ // GIR_Coverage, 1908,
27272 /* 75221 */ GIR_EraseRootFromParent_Done,
27273 /* 75222 */ // Label 2336: @75222
27274 /* 75222 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2337*/ GIMT_Encode4(75275), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1909 //
27275 /* 75229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2),
27276 /* 75234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27277 /* 75237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27278 /* 75240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27279 /* 75243 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27280 /* 75246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27281 /* 75250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27282 /* 75254 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27283 /* 75258 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27284 /* 75262 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3990:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27285 /* 75262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2),
27286 /* 75265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27287 /* 75267 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27288 /* 75269 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27289 /* 75271 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27290 /* 75273 */ GIR_RootConstrainSelectedInstOperands,
27291 /* 75274 */ // GIR_Coverage, 1909,
27292 /* 75274 */ GIR_EraseRootFromParent_Done,
27293 /* 75275 */ // Label 2337: @75275
27294 /* 75275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2338*/ GIMT_Encode4(75328), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1910 //
27295 /* 75282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1),
27296 /* 75287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27297 /* 75290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27298 /* 75293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27299 /* 75296 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27300 /* 75299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27301 /* 75303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27302 /* 75307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27303 /* 75311 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27304 /* 75315 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3992:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27305 /* 75315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1),
27306 /* 75318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27307 /* 75320 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27308 /* 75322 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27309 /* 75324 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27310 /* 75326 */ GIR_RootConstrainSelectedInstOperands,
27311 /* 75327 */ // GIR_Coverage, 1910,
27312 /* 75327 */ GIR_EraseRootFromParent_Done,
27313 /* 75328 */ // Label 2338: @75328
27314 /* 75328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2339*/ GIMT_Encode4(75390), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2087 //
27315 /* 75335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
27316 /* 75340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27317 /* 75343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27318 /* 75346 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27319 /* 75349 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27320 /* 75352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27321 /* 75356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27322 /* 75360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27323 /* 75364 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27324 /* 75368 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27325 /* 75368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD),
27326 /* 75371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27327 /* 75373 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27328 /* 75375 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27329 /* 75377 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27330 /* 75379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27331 /* 75382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27332 /* 75388 */ GIR_RootConstrainSelectedInstOperands,
27333 /* 75389 */ // GIR_Coverage, 2087,
27334 /* 75389 */ GIR_EraseRootFromParent_Done,
27335 /* 75390 */ // Label 2339: @75390
27336 /* 75390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2340*/ GIMT_Encode4(75452), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2088 //
27337 /* 75397 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
27338 /* 75402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27339 /* 75405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27340 /* 75408 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27341 /* 75411 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27342 /* 75414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27343 /* 75418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27344 /* 75422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27345 /* 75426 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27346 /* 75430 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27347 /* 75430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX),
27348 /* 75433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27349 /* 75435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27350 /* 75437 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27351 /* 75439 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27352 /* 75441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27353 /* 75444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27354 /* 75450 */ GIR_RootConstrainSelectedInstOperands,
27355 /* 75451 */ // GIR_Coverage, 2088,
27356 /* 75451 */ GIR_EraseRootFromParent_Done,
27357 /* 75452 */ // Label 2340: @75452
27358 /* 75452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2341*/ GIMT_Encode4(75514), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2089 //
27359 /* 75459 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
27360 /* 75464 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27361 /* 75467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27362 /* 75470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27363 /* 75473 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27364 /* 75476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27365 /* 75480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27366 /* 75484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27367 /* 75488 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27368 /* 75492 */ // (intrinsic_wo_chain:{ *:[i32] } 4141:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27369 /* 75492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD),
27370 /* 75495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27371 /* 75497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27372 /* 75499 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27373 /* 75501 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27374 /* 75503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27375 /* 75506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27376 /* 75512 */ GIR_RootConstrainSelectedInstOperands,
27377 /* 75513 */ // GIR_Coverage, 2089,
27378 /* 75513 */ GIR_EraseRootFromParent_Done,
27379 /* 75514 */ // Label 2341: @75514
27380 /* 75514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2342*/ GIMT_Encode4(75576), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2090 //
27381 /* 75521 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
27382 /* 75526 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27383 /* 75529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27384 /* 75532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27385 /* 75535 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27386 /* 75538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27387 /* 75542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27388 /* 75546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27389 /* 75550 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27390 /* 75554 */ // (intrinsic_wo_chain:{ *:[i32] } 4142:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27391 /* 75554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX),
27392 /* 75557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27393 /* 75559 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27394 /* 75561 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27395 /* 75563 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27396 /* 75565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27397 /* 75568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27398 /* 75574 */ GIR_RootConstrainSelectedInstOperands,
27399 /* 75575 */ // GIR_Coverage, 2090,
27400 /* 75575 */ GIR_EraseRootFromParent_Done,
27401 /* 75576 */ // Label 2342: @75576
27402 /* 75576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2343*/ GIMT_Encode4(75638), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2185 //
27403 /* 75583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
27404 /* 75588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27405 /* 75591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27406 /* 75594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27407 /* 75597 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27408 /* 75600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27409 /* 75604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27410 /* 75608 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27411 /* 75612 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27412 /* 75616 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27413 /* 75616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
27414 /* 75619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27415 /* 75621 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27416 /* 75623 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27417 /* 75625 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27418 /* 75627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27419 /* 75630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27420 /* 75636 */ GIR_RootConstrainSelectedInstOperands,
27421 /* 75637 */ // GIR_Coverage, 2185,
27422 /* 75637 */ GIR_EraseRootFromParent_Done,
27423 /* 75638 */ // Label 2343: @75638
27424 /* 75638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2344*/ GIMT_Encode4(75700), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2186 //
27425 /* 75645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
27426 /* 75650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27427 /* 75653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27428 /* 75656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27429 /* 75659 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27430 /* 75662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27431 /* 75666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27432 /* 75670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27433 /* 75674 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27434 /* 75678 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27435 /* 75678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
27436 /* 75681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27437 /* 75683 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27438 /* 75685 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27439 /* 75687 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27440 /* 75689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27441 /* 75692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27442 /* 75698 */ GIR_RootConstrainSelectedInstOperands,
27443 /* 75699 */ // GIR_Coverage, 2186,
27444 /* 75699 */ GIR_EraseRootFromParent_Done,
27445 /* 75700 */ // Label 2344: @75700
27446 /* 75700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2345*/ GIMT_Encode4(75762), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2187 //
27447 /* 75707 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
27448 /* 75712 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27449 /* 75715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27450 /* 75718 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27451 /* 75721 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27452 /* 75724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27453 /* 75728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27454 /* 75732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27455 /* 75736 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27456 /* 75740 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27457 /* 75740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
27458 /* 75743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27459 /* 75745 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27460 /* 75747 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27461 /* 75749 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27462 /* 75751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27463 /* 75754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27464 /* 75760 */ GIR_RootConstrainSelectedInstOperands,
27465 /* 75761 */ // GIR_Coverage, 2187,
27466 /* 75761 */ GIR_EraseRootFromParent_Done,
27467 /* 75762 */ // Label 2345: @75762
27468 /* 75762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2346*/ GIMT_Encode4(75824), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2188 //
27469 /* 75769 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
27470 /* 75774 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27471 /* 75777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27472 /* 75780 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27473 /* 75783 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27474 /* 75786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27475 /* 75790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27476 /* 75794 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27477 /* 75798 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27478 /* 75802 */ // (intrinsic_wo_chain:{ *:[i32] } 4138:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27479 /* 75802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
27480 /* 75805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27481 /* 75807 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27482 /* 75809 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27483 /* 75811 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27484 /* 75813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27485 /* 75816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27486 /* 75822 */ GIR_RootConstrainSelectedInstOperands,
27487 /* 75823 */ // GIR_Coverage, 2188,
27488 /* 75823 */ GIR_EraseRootFromParent_Done,
27489 /* 75824 */ // Label 2346: @75824
27490 /* 75824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2347*/ GIMT_Encode4(75886), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2189 //
27491 /* 75831 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
27492 /* 75836 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27493 /* 75839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27494 /* 75842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27495 /* 75845 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27496 /* 75848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27497 /* 75852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27498 /* 75856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27499 /* 75860 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27500 /* 75864 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27501 /* 75864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB),
27502 /* 75867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27503 /* 75869 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27504 /* 75871 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27505 /* 75873 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27506 /* 75875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27507 /* 75878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27508 /* 75884 */ GIR_RootConstrainSelectedInstOperands,
27509 /* 75885 */ // GIR_Coverage, 2189,
27510 /* 75885 */ GIR_EraseRootFromParent_Done,
27511 /* 75886 */ // Label 2347: @75886
27512 /* 75886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2348*/ GIMT_Encode4(75948), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2190 //
27513 /* 75893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
27514 /* 75898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27515 /* 75901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27516 /* 75904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27517 /* 75907 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27518 /* 75910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27519 /* 75914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27520 /* 75918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27521 /* 75922 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27522 /* 75926 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27523 /* 75926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT),
27524 /* 75929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27525 /* 75931 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27526 /* 75933 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27527 /* 75935 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27528 /* 75937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27529 /* 75940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27530 /* 75946 */ GIR_RootConstrainSelectedInstOperands,
27531 /* 75947 */ // GIR_Coverage, 2190,
27532 /* 75947 */ GIR_EraseRootFromParent_Done,
27533 /* 75948 */ // Label 2348: @75948
27534 /* 75948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2349*/ GIMT_Encode4(76010), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2377 //
27535 /* 75955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
27536 /* 75960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27537 /* 75963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27538 /* 75966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27539 /* 75969 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27540 /* 75972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27541 /* 75976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27542 /* 75980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27543 /* 75984 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27544 /* 75988 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27545 /* 75988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
27546 /* 75991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27547 /* 75993 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27548 /* 75995 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27549 /* 75997 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27550 /* 75999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27551 /* 76002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27552 /* 76008 */ GIR_RootConstrainSelectedInstOperands,
27553 /* 76009 */ // GIR_Coverage, 2377,
27554 /* 76009 */ GIR_EraseRootFromParent_Done,
27555 /* 76010 */ // Label 2349: @76010
27556 /* 76010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2350*/ GIMT_Encode4(76072), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2378 //
27557 /* 76017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
27558 /* 76022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27559 /* 76025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27560 /* 76028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27561 /* 76031 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27562 /* 76034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27563 /* 76038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27564 /* 76042 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27565 /* 76046 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27566 /* 76050 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27567 /* 76050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
27568 /* 76053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27569 /* 76055 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27570 /* 76057 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27571 /* 76059 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27572 /* 76061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27573 /* 76064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27574 /* 76070 */ GIR_RootConstrainSelectedInstOperands,
27575 /* 76071 */ // GIR_Coverage, 2378,
27576 /* 76071 */ GIR_EraseRootFromParent_Done,
27577 /* 76072 */ // Label 2350: @76072
27578 /* 76072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2351*/ GIMT_Encode4(76134), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2379 //
27579 /* 76079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
27580 /* 76084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27581 /* 76087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27582 /* 76090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27583 /* 76093 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27584 /* 76096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27585 /* 76100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27586 /* 76104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27587 /* 76108 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27588 /* 76112 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27589 /* 76112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
27590 /* 76115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27591 /* 76117 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27592 /* 76119 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27593 /* 76121 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27594 /* 76123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27595 /* 76126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27596 /* 76132 */ GIR_RootConstrainSelectedInstOperands,
27597 /* 76133 */ // GIR_Coverage, 2379,
27598 /* 76133 */ GIR_EraseRootFromParent_Done,
27599 /* 76134 */ // Label 2351: @76134
27600 /* 76134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2352*/ GIMT_Encode4(76196), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2380 //
27601 /* 76141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
27602 /* 76146 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27603 /* 76149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27604 /* 76152 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27605 /* 76155 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27606 /* 76158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27607 /* 76162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27608 /* 76166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27609 /* 76170 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27610 /* 76174 */ // (intrinsic_wo_chain:{ *:[i32] } 4138:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27611 /* 76174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
27612 /* 76177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27613 /* 76179 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27614 /* 76181 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27615 /* 76183 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27616 /* 76185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27617 /* 76188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27618 /* 76194 */ GIR_RootConstrainSelectedInstOperands,
27619 /* 76195 */ // GIR_Coverage, 2380,
27620 /* 76195 */ GIR_EraseRootFromParent_Done,
27621 /* 76196 */ // Label 2352: @76196
27622 /* 76196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2353*/ GIMT_Encode4(76258), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2381 //
27623 /* 76203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
27624 /* 76208 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27625 /* 76211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27626 /* 76214 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27627 /* 76217 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27628 /* 76220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27629 /* 76224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27630 /* 76228 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27631 /* 76232 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27632 /* 76236 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27633 /* 76236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB),
27634 /* 76239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27635 /* 76241 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27636 /* 76243 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27637 /* 76245 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27638 /* 76247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27639 /* 76250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27640 /* 76256 */ GIR_RootConstrainSelectedInstOperands,
27641 /* 76257 */ // GIR_Coverage, 2381,
27642 /* 76257 */ GIR_EraseRootFromParent_Done,
27643 /* 76258 */ // Label 2353: @76258
27644 /* 76258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2354*/ GIMT_Encode4(76320), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2382 //
27645 /* 76265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
27646 /* 76270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27647 /* 76273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27648 /* 76276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27649 /* 76279 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27650 /* 76282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27651 /* 76286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27652 /* 76290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27653 /* 76294 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27654 /* 76298 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27655 /* 76298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT),
27656 /* 76301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27657 /* 76303 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27658 /* 76305 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27659 /* 76307 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27660 /* 76309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27661 /* 76312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27662 /* 76318 */ GIR_RootConstrainSelectedInstOperands,
27663 /* 76319 */ // GIR_Coverage, 2382,
27664 /* 76319 */ GIR_EraseRootFromParent_Done,
27665 /* 76320 */ // Label 2354: @76320
27666 /* 76320 */ GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(76578),
27667 /* 76325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
27668 /* 76330 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2360*/ GIMT_Encode4(76577),
27669 /* 76341 */ /*GILLT_v4s16*//*Label 2356*/ GIMT_Encode4(76357),
27670 /* 76345 */ /*GILLT_v8s16*//*Label 2357*/ GIMT_Encode4(76412),
27671 /* 76349 */ /*GILLT_v2s32*//*Label 2358*/ GIMT_Encode4(76467),
27672 /* 76353 */ /*GILLT_v4s32*//*Label 2359*/ GIMT_Encode4(76522),
27673 /* 76357 */ // Label 2356: @76357
27674 /* 76357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2361*/ GIMT_Encode4(76411), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2856 //
27675 /* 76364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
27676 /* 76367 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
27677 /* 76370 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
27678 /* 76373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27679 /* 76377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27680 /* 76381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27681 /* 76385 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27682 /* 76389 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4066:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
27683 /* 76389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16),
27684 /* 76392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27685 /* 76394 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27686 /* 76396 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27687 /* 76398 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27688 /* 76400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27689 /* 76403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27690 /* 76409 */ GIR_RootConstrainSelectedInstOperands,
27691 /* 76410 */ // GIR_Coverage, 2856,
27692 /* 76410 */ GIR_EraseRootFromParent_Done,
27693 /* 76411 */ // Label 2361: @76411
27694 /* 76411 */ GIM_Reject,
27695 /* 76412 */ // Label 2357: @76412
27696 /* 76412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2362*/ GIMT_Encode4(76466), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2858 //
27697 /* 76419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27698 /* 76422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27699 /* 76425 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27700 /* 76428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27701 /* 76432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27702 /* 76436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27703 /* 76440 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27704 /* 76444 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4066:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
27705 /* 76444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16),
27706 /* 76447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27707 /* 76449 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27708 /* 76451 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27709 /* 76453 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27710 /* 76455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27711 /* 76458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27712 /* 76464 */ GIR_RootConstrainSelectedInstOperands,
27713 /* 76465 */ // GIR_Coverage, 2858,
27714 /* 76465 */ GIR_EraseRootFromParent_Done,
27715 /* 76466 */ // Label 2362: @76466
27716 /* 76466 */ GIM_Reject,
27717 /* 76467 */ // Label 2358: @76467
27718 /* 76467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2363*/ GIMT_Encode4(76521), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2857 //
27719 /* 76474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27720 /* 76477 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
27721 /* 76480 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
27722 /* 76483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27723 /* 76487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27724 /* 76491 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27725 /* 76495 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27726 /* 76499 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4066:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
27727 /* 76499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32),
27728 /* 76502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27729 /* 76504 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27730 /* 76506 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27731 /* 76508 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27732 /* 76510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27733 /* 76513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27734 /* 76519 */ GIR_RootConstrainSelectedInstOperands,
27735 /* 76520 */ // GIR_Coverage, 2857,
27736 /* 76520 */ GIR_EraseRootFromParent_Done,
27737 /* 76521 */ // Label 2363: @76521
27738 /* 76521 */ GIM_Reject,
27739 /* 76522 */ // Label 2359: @76522
27740 /* 76522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2364*/ GIMT_Encode4(76576), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2859 //
27741 /* 76529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27742 /* 76532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27743 /* 76535 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27744 /* 76538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27745 /* 76542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27746 /* 76546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27747 /* 76550 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27748 /* 76554 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4066:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27749 /* 76554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32),
27750 /* 76557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27751 /* 76559 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27752 /* 76561 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27753 /* 76563 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27754 /* 76565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27755 /* 76568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27756 /* 76574 */ GIR_RootConstrainSelectedInstOperands,
27757 /* 76575 */ // GIR_Coverage, 2859,
27758 /* 76575 */ GIR_EraseRootFromParent_Done,
27759 /* 76576 */ // Label 2364: @76576
27760 /* 76576 */ GIM_Reject,
27761 /* 76577 */ // Label 2360: @76577
27762 /* 76577 */ GIM_Reject,
27763 /* 76578 */ // Label 2355: @76578
27764 /* 76578 */ GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(76836),
27765 /* 76583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
27766 /* 76588 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2370*/ GIMT_Encode4(76835),
27767 /* 76599 */ /*GILLT_v4s16*//*Label 2366*/ GIMT_Encode4(76615),
27768 /* 76603 */ /*GILLT_v8s16*//*Label 2367*/ GIMT_Encode4(76670),
27769 /* 76607 */ /*GILLT_v2s32*//*Label 2368*/ GIMT_Encode4(76725),
27770 /* 76611 */ /*GILLT_v4s32*//*Label 2369*/ GIMT_Encode4(76780),
27771 /* 76615 */ // Label 2366: @76615
27772 /* 76615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2371*/ GIMT_Encode4(76669), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2864 //
27773 /* 76622 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
27774 /* 76625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
27775 /* 76628 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
27776 /* 76631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27777 /* 76635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27778 /* 76639 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27779 /* 76643 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27780 /* 76647 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
27781 /* 76647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16),
27782 /* 76650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27783 /* 76652 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27784 /* 76654 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27785 /* 76656 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27786 /* 76658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27787 /* 76661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27788 /* 76667 */ GIR_RootConstrainSelectedInstOperands,
27789 /* 76668 */ // GIR_Coverage, 2864,
27790 /* 76668 */ GIR_EraseRootFromParent_Done,
27791 /* 76669 */ // Label 2371: @76669
27792 /* 76669 */ GIM_Reject,
27793 /* 76670 */ // Label 2367: @76670
27794 /* 76670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2372*/ GIMT_Encode4(76724), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2866 //
27795 /* 76677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27796 /* 76680 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27797 /* 76683 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27798 /* 76686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27799 /* 76690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27800 /* 76694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27801 /* 76698 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27802 /* 76702 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4067:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
27803 /* 76702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16),
27804 /* 76705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27805 /* 76707 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27806 /* 76709 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27807 /* 76711 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27808 /* 76713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27809 /* 76716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27810 /* 76722 */ GIR_RootConstrainSelectedInstOperands,
27811 /* 76723 */ // GIR_Coverage, 2866,
27812 /* 76723 */ GIR_EraseRootFromParent_Done,
27813 /* 76724 */ // Label 2372: @76724
27814 /* 76724 */ GIM_Reject,
27815 /* 76725 */ // Label 2368: @76725
27816 /* 76725 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2373*/ GIMT_Encode4(76779), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2865 //
27817 /* 76732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27818 /* 76735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
27819 /* 76738 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
27820 /* 76741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27821 /* 76745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27822 /* 76749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27823 /* 76753 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27824 /* 76757 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
27825 /* 76757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32),
27826 /* 76760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27827 /* 76762 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27828 /* 76764 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27829 /* 76766 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27830 /* 76768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27831 /* 76771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27832 /* 76777 */ GIR_RootConstrainSelectedInstOperands,
27833 /* 76778 */ // GIR_Coverage, 2865,
27834 /* 76778 */ GIR_EraseRootFromParent_Done,
27835 /* 76779 */ // Label 2373: @76779
27836 /* 76779 */ GIM_Reject,
27837 /* 76780 */ // Label 2369: @76780
27838 /* 76780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2374*/ GIMT_Encode4(76834), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2867 //
27839 /* 76787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27840 /* 76790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27841 /* 76793 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27842 /* 76796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27843 /* 76800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27844 /* 76804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27845 /* 76808 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27846 /* 76812 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27847 /* 76812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32),
27848 /* 76815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27849 /* 76817 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27850 /* 76819 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27851 /* 76821 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27852 /* 76823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27853 /* 76826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27854 /* 76832 */ GIR_RootConstrainSelectedInstOperands,
27855 /* 76833 */ // GIR_Coverage, 2867,
27856 /* 76833 */ GIR_EraseRootFromParent_Done,
27857 /* 76834 */ // Label 2374: @76834
27858 /* 76834 */ GIM_Reject,
27859 /* 76835 */ // Label 2370: @76835
27860 /* 76835 */ GIM_Reject,
27861 /* 76836 */ // Label 2365: @76836
27862 /* 76836 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(76992),
27863 /* 76841 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27864 /* 76846 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2378*/ GIMT_Encode4(76991),
27865 /* 76857 */ /*GILLT_v8s16*//*Label 2376*/ GIMT_Encode4(76869), GIMT_Encode4(0),
27866 /* 76865 */ /*GILLT_v4s32*//*Label 2377*/ GIMT_Encode4(76930),
27867 /* 76869 */ // Label 2376: @76869
27868 /* 76869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2379*/ GIMT_Encode4(76929), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4446 //
27869 /* 76876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27870 /* 76879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27871 /* 76882 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27872 /* 76885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27873 /* 76889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27874 /* 76893 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27875 /* 76897 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27876 /* 76901 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3781:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
27877 /* 76901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
27878 /* 76904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27879 /* 76906 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27880 /* 76908 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27881 /* 76910 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27882 /* 76912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27883 /* 76915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27884 /* 76921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27885 /* 76927 */ GIR_RootConstrainSelectedInstOperands,
27886 /* 76928 */ // GIR_Coverage, 4446,
27887 /* 76928 */ GIR_EraseRootFromParent_Done,
27888 /* 76929 */ // Label 2379: @76929
27889 /* 76929 */ GIM_Reject,
27890 /* 76930 */ // Label 2377: @76930
27891 /* 76930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2380*/ GIMT_Encode4(76990), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4442 //
27892 /* 76937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27893 /* 76940 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27894 /* 76943 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27895 /* 76946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27896 /* 76950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27897 /* 76954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27898 /* 76958 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27899 /* 76962 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3781:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
27900 /* 76962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
27901 /* 76965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27902 /* 76967 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27903 /* 76969 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27904 /* 76971 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27905 /* 76973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27906 /* 76976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27907 /* 76982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27908 /* 76988 */ GIR_RootConstrainSelectedInstOperands,
27909 /* 76989 */ // GIR_Coverage, 4442,
27910 /* 76989 */ GIR_EraseRootFromParent_Done,
27911 /* 76990 */ // Label 2380: @76990
27912 /* 76990 */ GIM_Reject,
27913 /* 76991 */ // Label 2378: @76991
27914 /* 76991 */ GIM_Reject,
27915 /* 76992 */ // Label 2375: @76992
27916 /* 76992 */ GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(77217),
27917 /* 76997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
27918 /* 77002 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2385*/ GIMT_Encode4(77216),
27919 /* 77013 */ /*GILLT_v16s8*//*Label 2382*/ GIMT_Encode4(77033), GIMT_Encode4(0),
27920 /* 77021 */ /*GILLT_v8s16*//*Label 2383*/ GIMT_Encode4(77094), GIMT_Encode4(0),
27921 /* 77029 */ /*GILLT_v4s32*//*Label 2384*/ GIMT_Encode4(77155),
27922 /* 77033 */ // Label 2382: @77033
27923 /* 77033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2386*/ GIMT_Encode4(77093), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5375 //
27924 /* 77040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27925 /* 77043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27926 /* 77046 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27927 /* 77049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27928 /* 77053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27929 /* 77057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27930 /* 77061 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27931 /* 77065 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
27932 /* 77065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8),
27933 /* 77068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27934 /* 77070 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27935 /* 77072 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27936 /* 77074 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27937 /* 77076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27938 /* 77079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27939 /* 77085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27940 /* 77091 */ GIR_RootConstrainSelectedInstOperands,
27941 /* 77092 */ // GIR_Coverage, 5375,
27942 /* 77092 */ GIR_EraseRootFromParent_Done,
27943 /* 77093 */ // Label 2386: @77093
27944 /* 77093 */ GIM_Reject,
27945 /* 77094 */ // Label 2383: @77094
27946 /* 77094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2387*/ GIMT_Encode4(77154), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5377 //
27947 /* 77101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27948 /* 77104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27949 /* 77107 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27950 /* 77110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27951 /* 77114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27952 /* 77118 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27953 /* 77122 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27954 /* 77126 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
27955 /* 77126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16),
27956 /* 77129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27957 /* 77131 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27958 /* 77133 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27959 /* 77135 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27960 /* 77137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27961 /* 77140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27962 /* 77146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27963 /* 77152 */ GIR_RootConstrainSelectedInstOperands,
27964 /* 77153 */ // GIR_Coverage, 5377,
27965 /* 77153 */ GIR_EraseRootFromParent_Done,
27966 /* 77154 */ // Label 2387: @77154
27967 /* 77154 */ GIM_Reject,
27968 /* 77155 */ // Label 2384: @77155
27969 /* 77155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2388*/ GIMT_Encode4(77215), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5379 //
27970 /* 77162 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27971 /* 77165 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27972 /* 77168 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27973 /* 77171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27974 /* 77175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27975 /* 77179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27976 /* 77183 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27977 /* 77187 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
27978 /* 77187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32),
27979 /* 77190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27980 /* 77192 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27981 /* 77194 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27982 /* 77196 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27983 /* 77198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27984 /* 77201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27985 /* 77207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27986 /* 77213 */ GIR_RootConstrainSelectedInstOperands,
27987 /* 77214 */ // GIR_Coverage, 5379,
27988 /* 77214 */ GIR_EraseRootFromParent_Done,
27989 /* 77215 */ // Label 2388: @77215
27990 /* 77215 */ GIM_Reject,
27991 /* 77216 */ // Label 2385: @77216
27992 /* 77216 */ GIM_Reject,
27993 /* 77217 */ // Label 2381: @77217
27994 /* 77217 */ GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(77442),
27995 /* 77222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
27996 /* 77227 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2393*/ GIMT_Encode4(77441),
27997 /* 77238 */ /*GILLT_v16s8*//*Label 2390*/ GIMT_Encode4(77258), GIMT_Encode4(0),
27998 /* 77246 */ /*GILLT_v8s16*//*Label 2391*/ GIMT_Encode4(77319), GIMT_Encode4(0),
27999 /* 77254 */ /*GILLT_v4s32*//*Label 2392*/ GIMT_Encode4(77380),
28000 /* 77258 */ // Label 2390: @77258
28001 /* 77258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2394*/ GIMT_Encode4(77318), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5381 //
28002 /* 77265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28003 /* 77268 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28004 /* 77271 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28005 /* 77274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28006 /* 77278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28007 /* 77282 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28008 /* 77286 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28009 /* 77290 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3920:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28010 /* 77290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8),
28011 /* 77293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28012 /* 77295 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28013 /* 77297 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28014 /* 77299 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28015 /* 77301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28016 /* 77304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28017 /* 77310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28018 /* 77316 */ GIR_RootConstrainSelectedInstOperands,
28019 /* 77317 */ // GIR_Coverage, 5381,
28020 /* 77317 */ GIR_EraseRootFromParent_Done,
28021 /* 77318 */ // Label 2394: @77318
28022 /* 77318 */ GIM_Reject,
28023 /* 77319 */ // Label 2391: @77319
28024 /* 77319 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2395*/ GIMT_Encode4(77379), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5383 //
28025 /* 77326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28026 /* 77329 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28027 /* 77332 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28028 /* 77335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28029 /* 77339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28030 /* 77343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28031 /* 77347 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28032 /* 77351 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28033 /* 77351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16),
28034 /* 77354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28035 /* 77356 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28036 /* 77358 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28037 /* 77360 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28038 /* 77362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28039 /* 77365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28040 /* 77371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28041 /* 77377 */ GIR_RootConstrainSelectedInstOperands,
28042 /* 77378 */ // GIR_Coverage, 5383,
28043 /* 77378 */ GIR_EraseRootFromParent_Done,
28044 /* 77379 */ // Label 2395: @77379
28045 /* 77379 */ GIM_Reject,
28046 /* 77380 */ // Label 2392: @77380
28047 /* 77380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2396*/ GIMT_Encode4(77440), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5385 //
28048 /* 77387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28049 /* 77390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28050 /* 77393 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28051 /* 77396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28052 /* 77400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28053 /* 77404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28054 /* 77408 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28055 /* 77412 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3920:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28056 /* 77412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32),
28057 /* 77415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28058 /* 77417 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28059 /* 77419 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28060 /* 77421 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28061 /* 77423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28062 /* 77426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28063 /* 77432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28064 /* 77438 */ GIR_RootConstrainSelectedInstOperands,
28065 /* 77439 */ // GIR_Coverage, 5385,
28066 /* 77439 */ GIR_EraseRootFromParent_Done,
28067 /* 77440 */ // Label 2396: @77440
28068 /* 77440 */ GIM_Reject,
28069 /* 77441 */ // Label 2393: @77441
28070 /* 77441 */ GIM_Reject,
28071 /* 77442 */ // Label 2389: @77442
28072 /* 77442 */ GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(77667),
28073 /* 77447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28074 /* 77452 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2401*/ GIMT_Encode4(77666),
28075 /* 77463 */ /*GILLT_v16s8*//*Label 2398*/ GIMT_Encode4(77483), GIMT_Encode4(0),
28076 /* 77471 */ /*GILLT_v8s16*//*Label 2399*/ GIMT_Encode4(77544), GIMT_Encode4(0),
28077 /* 77479 */ /*GILLT_v4s32*//*Label 2400*/ GIMT_Encode4(77605),
28078 /* 77483 */ // Label 2398: @77483
28079 /* 77483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2402*/ GIMT_Encode4(77543), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5387 //
28080 /* 77490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28081 /* 77493 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28082 /* 77496 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28083 /* 77499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28084 /* 77503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28085 /* 77507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28086 /* 77511 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28087 /* 77515 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28088 /* 77515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8),
28089 /* 77518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28090 /* 77520 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28091 /* 77522 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28092 /* 77524 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28093 /* 77526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28094 /* 77529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28095 /* 77535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28096 /* 77541 */ GIR_RootConstrainSelectedInstOperands,
28097 /* 77542 */ // GIR_Coverage, 5387,
28098 /* 77542 */ GIR_EraseRootFromParent_Done,
28099 /* 77543 */ // Label 2402: @77543
28100 /* 77543 */ GIM_Reject,
28101 /* 77544 */ // Label 2399: @77544
28102 /* 77544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2403*/ GIMT_Encode4(77604), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5389 //
28103 /* 77551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28104 /* 77554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28105 /* 77557 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28106 /* 77560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28107 /* 77564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28108 /* 77568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28109 /* 77572 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28110 /* 77576 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28111 /* 77576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16),
28112 /* 77579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28113 /* 77581 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28114 /* 77583 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28115 /* 77585 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28116 /* 77587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28117 /* 77590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28118 /* 77596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28119 /* 77602 */ GIR_RootConstrainSelectedInstOperands,
28120 /* 77603 */ // GIR_Coverage, 5389,
28121 /* 77603 */ GIR_EraseRootFromParent_Done,
28122 /* 77604 */ // Label 2403: @77604
28123 /* 77604 */ GIM_Reject,
28124 /* 77605 */ // Label 2400: @77605
28125 /* 77605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2404*/ GIMT_Encode4(77665), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5391 //
28126 /* 77612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28127 /* 77615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28128 /* 77618 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28129 /* 77621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28130 /* 77625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28131 /* 77629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28132 /* 77633 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28133 /* 77637 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28134 /* 77637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32),
28135 /* 77640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28136 /* 77642 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28137 /* 77644 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28138 /* 77646 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28139 /* 77648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28140 /* 77651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28141 /* 77657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28142 /* 77663 */ GIR_RootConstrainSelectedInstOperands,
28143 /* 77664 */ // GIR_Coverage, 5391,
28144 /* 77664 */ GIR_EraseRootFromParent_Done,
28145 /* 77665 */ // Label 2404: @77665
28146 /* 77665 */ GIM_Reject,
28147 /* 77666 */ // Label 2401: @77666
28148 /* 77666 */ GIM_Reject,
28149 /* 77667 */ // Label 2397: @77667
28150 /* 77667 */ GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(77892),
28151 /* 77672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28152 /* 77677 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2409*/ GIMT_Encode4(77891),
28153 /* 77688 */ /*GILLT_v16s8*//*Label 2406*/ GIMT_Encode4(77708), GIMT_Encode4(0),
28154 /* 77696 */ /*GILLT_v8s16*//*Label 2407*/ GIMT_Encode4(77769), GIMT_Encode4(0),
28155 /* 77704 */ /*GILLT_v4s32*//*Label 2408*/ GIMT_Encode4(77830),
28156 /* 77708 */ // Label 2406: @77708
28157 /* 77708 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2410*/ GIMT_Encode4(77768), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5393 //
28158 /* 77715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28159 /* 77718 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28160 /* 77721 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28161 /* 77724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28162 /* 77728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28163 /* 77732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28164 /* 77736 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28165 /* 77740 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3922:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28166 /* 77740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8),
28167 /* 77743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28168 /* 77745 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28169 /* 77747 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28170 /* 77749 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28171 /* 77751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28172 /* 77754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28173 /* 77760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28174 /* 77766 */ GIR_RootConstrainSelectedInstOperands,
28175 /* 77767 */ // GIR_Coverage, 5393,
28176 /* 77767 */ GIR_EraseRootFromParent_Done,
28177 /* 77768 */ // Label 2410: @77768
28178 /* 77768 */ GIM_Reject,
28179 /* 77769 */ // Label 2407: @77769
28180 /* 77769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2411*/ GIMT_Encode4(77829), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5395 //
28181 /* 77776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28182 /* 77779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28183 /* 77782 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28184 /* 77785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28185 /* 77789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28186 /* 77793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28187 /* 77797 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28188 /* 77801 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3922:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28189 /* 77801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16),
28190 /* 77804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28191 /* 77806 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28192 /* 77808 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28193 /* 77810 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28194 /* 77812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28195 /* 77815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28196 /* 77821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28197 /* 77827 */ GIR_RootConstrainSelectedInstOperands,
28198 /* 77828 */ // GIR_Coverage, 5395,
28199 /* 77828 */ GIR_EraseRootFromParent_Done,
28200 /* 77829 */ // Label 2411: @77829
28201 /* 77829 */ GIM_Reject,
28202 /* 77830 */ // Label 2408: @77830
28203 /* 77830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2412*/ GIMT_Encode4(77890), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5397 //
28204 /* 77837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28205 /* 77840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28206 /* 77843 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28207 /* 77846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28208 /* 77850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28209 /* 77854 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28210 /* 77858 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28211 /* 77862 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3922:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28212 /* 77862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32),
28213 /* 77865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28214 /* 77867 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28215 /* 77869 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28216 /* 77871 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28217 /* 77873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28218 /* 77876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28219 /* 77882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28220 /* 77888 */ GIR_RootConstrainSelectedInstOperands,
28221 /* 77889 */ // GIR_Coverage, 5397,
28222 /* 77889 */ GIR_EraseRootFromParent_Done,
28223 /* 77890 */ // Label 2412: @77890
28224 /* 77890 */ GIM_Reject,
28225 /* 77891 */ // Label 2409: @77891
28226 /* 77891 */ GIM_Reject,
28227 /* 77892 */ // Label 2405: @77892
28228 /* 77892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2413*/ GIMT_Encode4(78005), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3083 //
28229 /* 77899 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c),
28230 /* 77904 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28231 /* 77907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28232 /* 77910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28233 /* 77913 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28234 /* 77916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28235 /* 77920 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3983:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28236 /* 77920 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
28237 /* 77923 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28238 /* 77927 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28239 /* 77932 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28240 /* 77936 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
28241 /* 77941 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
28242 /* 77944 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28243 /* 77948 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28244 /* 77953 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28245 /* 77955 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28246 /* 77958 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
28247 /* 77962 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28248 /* 77967 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28249 /* 77970 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
28250 /* 77973 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28251 /* 77976 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28252 /* 77981 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28253 /* 77986 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28254 /* 77991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C),
28255 /* 77994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28256 /* 77996 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
28257 /* 77998 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28258 /* 78001 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
28259 /* 78003 */ GIR_RootConstrainSelectedInstOperands,
28260 /* 78004 */ // GIR_Coverage, 3083,
28261 /* 78004 */ GIR_EraseRootFromParent_Done,
28262 /* 78005 */ // Label 2413: @78005
28263 /* 78005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2414*/ GIMT_Encode4(78118), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3084 //
28264 /* 78012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m),
28265 /* 78017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28266 /* 78020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28267 /* 78023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28268 /* 78026 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28269 /* 78029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28270 /* 78033 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3985:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28271 /* 78033 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
28272 /* 78036 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28273 /* 78040 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28274 /* 78045 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28275 /* 78049 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
28276 /* 78054 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
28277 /* 78057 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28278 /* 78061 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28279 /* 78066 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28280 /* 78068 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28281 /* 78071 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
28282 /* 78075 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28283 /* 78080 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28284 /* 78083 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
28285 /* 78086 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28286 /* 78089 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28287 /* 78094 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28288 /* 78099 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28289 /* 78104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M),
28290 /* 78107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28291 /* 78109 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
28292 /* 78111 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28293 /* 78114 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
28294 /* 78116 */ GIR_RootConstrainSelectedInstOperands,
28295 /* 78117 */ // GIR_Coverage, 3084,
28296 /* 78117 */ GIR_EraseRootFromParent_Done,
28297 /* 78118 */ // Label 2414: @78118
28298 /* 78118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2415*/ GIMT_Encode4(78231), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3085 //
28299 /* 78125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p),
28300 /* 78130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28301 /* 78133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28302 /* 78136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28303 /* 78139 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28304 /* 78142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28305 /* 78146 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3986:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28306 /* 78146 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
28307 /* 78149 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28308 /* 78153 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28309 /* 78158 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28310 /* 78162 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
28311 /* 78167 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
28312 /* 78170 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28313 /* 78174 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28314 /* 78179 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28315 /* 78181 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28316 /* 78184 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
28317 /* 78188 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28318 /* 78193 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28319 /* 78196 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
28320 /* 78199 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28321 /* 78202 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28322 /* 78207 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28323 /* 78212 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28324 /* 78217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P),
28325 /* 78220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28326 /* 78222 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
28327 /* 78224 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28328 /* 78227 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
28329 /* 78229 */ GIR_RootConstrainSelectedInstOperands,
28330 /* 78230 */ // GIR_Coverage, 3085,
28331 /* 78230 */ GIR_EraseRootFromParent_Done,
28332 /* 78231 */ // Label 2415: @78231
28333 /* 78231 */ GIM_Reject,
28334 /* 78232 */ // Label 2108: @78232
28335 /* 78232 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(81071),
28336 /* 78237 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
28337 /* 78240 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(78760),
28338 /* 78245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28339 /* 78250 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2420*/ GIMT_Encode4(78759),
28340 /* 78261 */ /*GILLT_v8s16*//*Label 2418*/ GIMT_Encode4(78273), GIMT_Encode4(0),
28341 /* 78269 */ /*GILLT_v4s32*//*Label 2419*/ GIMT_Encode4(78516),
28342 /* 78273 */ // Label 2418: @78273
28343 /* 78273 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(78515),
28344 /* 78278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28345 /* 78281 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28346 /* 78284 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28347 /* 78287 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28348 /* 78290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28349 /* 78294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28350 /* 78298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
28351 /* 78302 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(78408),
28352 /* 78307 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28353 /* 78311 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(78359), // Rule ID 4130 //
28354 /* 78316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28355 /* 78320 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28356 /* 78320 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28357 /* 78323 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28358 /* 78327 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28359 /* 78332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh),
28360 /* 78335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28361 /* 78337 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28362 /* 78339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28363 /* 78342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28364 /* 78348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28365 /* 78354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28366 /* 78357 */ GIR_RootConstrainSelectedInstOperands,
28367 /* 78358 */ // GIR_Coverage, 4130,
28368 /* 78358 */ GIR_EraseRootFromParent_Done,
28369 /* 78359 */ // Label 2423: @78359
28370 /* 78359 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(78407), // Rule ID 4134 //
28371 /* 78364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28372 /* 78368 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28373 /* 78368 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28374 /* 78371 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28375 /* 78375 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28376 /* 78380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th),
28377 /* 78383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28378 /* 78385 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28379 /* 78387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28380 /* 78390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28381 /* 78396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28382 /* 78402 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28383 /* 78405 */ GIR_RootConstrainSelectedInstOperands,
28384 /* 78406 */ // GIR_Coverage, 4134,
28385 /* 78406 */ GIR_EraseRootFromParent_Done,
28386 /* 78407 */ // Label 2424: @78407
28387 /* 78407 */ GIM_Reject,
28388 /* 78408 */ // Label 2422: @78408
28389 /* 78408 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(78514),
28390 /* 78413 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28391 /* 78417 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(78465), // Rule ID 4146 //
28392 /* 78422 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28393 /* 78426 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28394 /* 78426 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28395 /* 78429 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28396 /* 78433 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28397 /* 78438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh),
28398 /* 78441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28399 /* 78443 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28400 /* 78445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28401 /* 78448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28402 /* 78454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28403 /* 78460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28404 /* 78463 */ GIR_RootConstrainSelectedInstOperands,
28405 /* 78464 */ // GIR_Coverage, 4146,
28406 /* 78464 */ GIR_EraseRootFromParent_Done,
28407 /* 78465 */ // Label 2426: @78465
28408 /* 78465 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(78513), // Rule ID 4150 //
28409 /* 78470 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28410 /* 78474 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28411 /* 78474 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28412 /* 78477 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28413 /* 78481 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28414 /* 78486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th),
28415 /* 78489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28416 /* 78491 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28417 /* 78493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28418 /* 78496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28419 /* 78502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28420 /* 78508 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28421 /* 78511 */ GIR_RootConstrainSelectedInstOperands,
28422 /* 78512 */ // GIR_Coverage, 4150,
28423 /* 78512 */ GIR_EraseRootFromParent_Done,
28424 /* 78513 */ // Label 2427: @78513
28425 /* 78513 */ GIM_Reject,
28426 /* 78514 */ // Label 2425: @78514
28427 /* 78514 */ GIM_Reject,
28428 /* 78515 */ // Label 2421: @78515
28429 /* 78515 */ GIM_Reject,
28430 /* 78516 */ // Label 2419: @78516
28431 /* 78516 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(78758),
28432 /* 78521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28433 /* 78524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28434 /* 78527 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28435 /* 78530 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28436 /* 78533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28437 /* 78537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28438 /* 78541 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
28439 /* 78545 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(78651),
28440 /* 78550 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28441 /* 78554 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(78602), // Rule ID 4138 //
28442 /* 78559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28443 /* 78563 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28444 /* 78563 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28445 /* 78566 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28446 /* 78570 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28447 /* 78575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh),
28448 /* 78578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28449 /* 78580 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28450 /* 78582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28451 /* 78585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28452 /* 78591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28453 /* 78597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28454 /* 78600 */ GIR_RootConstrainSelectedInstOperands,
28455 /* 78601 */ // GIR_Coverage, 4138,
28456 /* 78601 */ GIR_EraseRootFromParent_Done,
28457 /* 78602 */ // Label 2430: @78602
28458 /* 78602 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(78650), // Rule ID 4142 //
28459 /* 78607 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28460 /* 78611 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28461 /* 78611 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28462 /* 78614 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28463 /* 78618 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28464 /* 78623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th),
28465 /* 78626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28466 /* 78628 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28467 /* 78630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28468 /* 78633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28469 /* 78639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28470 /* 78645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28471 /* 78648 */ GIR_RootConstrainSelectedInstOperands,
28472 /* 78649 */ // GIR_Coverage, 4142,
28473 /* 78649 */ GIR_EraseRootFromParent_Done,
28474 /* 78650 */ // Label 2431: @78650
28475 /* 78650 */ GIM_Reject,
28476 /* 78651 */ // Label 2429: @78651
28477 /* 78651 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(78757),
28478 /* 78656 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28479 /* 78660 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(78708), // Rule ID 4154 //
28480 /* 78665 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28481 /* 78669 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28482 /* 78669 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28483 /* 78672 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28484 /* 78676 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28485 /* 78681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh),
28486 /* 78684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28487 /* 78686 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28488 /* 78688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28489 /* 78691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28490 /* 78697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28491 /* 78703 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28492 /* 78706 */ GIR_RootConstrainSelectedInstOperands,
28493 /* 78707 */ // GIR_Coverage, 4154,
28494 /* 78707 */ GIR_EraseRootFromParent_Done,
28495 /* 78708 */ // Label 2433: @78708
28496 /* 78708 */ GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(78756), // Rule ID 4158 //
28497 /* 78713 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28498 /* 78717 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28499 /* 78717 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28500 /* 78720 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28501 /* 78724 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28502 /* 78729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th),
28503 /* 78732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28504 /* 78734 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28505 /* 78736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28506 /* 78739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28507 /* 78745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28508 /* 78751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28509 /* 78754 */ GIR_RootConstrainSelectedInstOperands,
28510 /* 78755 */ // GIR_Coverage, 4158,
28511 /* 78755 */ GIR_EraseRootFromParent_Done,
28512 /* 78756 */ // Label 2434: @78756
28513 /* 78756 */ GIM_Reject,
28514 /* 78757 */ // Label 2432: @78757
28515 /* 78757 */ GIM_Reject,
28516 /* 78758 */ // Label 2428: @78758
28517 /* 78758 */ GIM_Reject,
28518 /* 78759 */ // Label 2420: @78759
28519 /* 78759 */ GIM_Reject,
28520 /* 78760 */ // Label 2417: @78760
28521 /* 78760 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(79575),
28522 /* 78765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
28523 /* 78770 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2439*/ GIMT_Encode4(79574),
28524 /* 78781 */ /*GILLT_v8s16*//*Label 2436*/ GIMT_Encode4(78797), GIMT_Encode4(0),
28525 /* 78789 */ /*GILLT_v4s32*//*Label 2437*/ GIMT_Encode4(79056),
28526 /* 78793 */ /*GILLT_v2s64*//*Label 2438*/ GIMT_Encode4(79315),
28527 /* 78797 */ // Label 2436: @78797
28528 /* 78797 */ GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(79055),
28529 /* 78802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28530 /* 78805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28531 /* 78808 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28532 /* 78811 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28533 /* 78814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28534 /* 78818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28535 /* 78822 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28536 /* 78826 */ GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(78940),
28537 /* 78831 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28538 /* 78835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2442*/ GIMT_Encode4(78887), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4898 //
28539 /* 78842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28540 /* 78846 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28541 /* 78846 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28542 /* 78849 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28543 /* 78853 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28544 /* 78858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
28545 /* 78861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28546 /* 78863 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28547 /* 78865 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28548 /* 78867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28549 /* 78870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28550 /* 78876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28551 /* 78882 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28552 /* 78885 */ GIR_RootConstrainSelectedInstOperands,
28553 /* 78886 */ // GIR_Coverage, 4898,
28554 /* 78886 */ GIR_EraseRootFromParent_Done,
28555 /* 78887 */ // Label 2442: @78887
28556 /* 78887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2443*/ GIMT_Encode4(78939), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4900 //
28557 /* 78894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28558 /* 78898 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28559 /* 78898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28560 /* 78901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28561 /* 78905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28562 /* 78910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8),
28563 /* 78913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28564 /* 78915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28565 /* 78917 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28566 /* 78919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28567 /* 78922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28568 /* 78928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28569 /* 78934 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28570 /* 78937 */ GIR_RootConstrainSelectedInstOperands,
28571 /* 78938 */ // GIR_Coverage, 4900,
28572 /* 78938 */ GIR_EraseRootFromParent_Done,
28573 /* 78939 */ // Label 2443: @78939
28574 /* 78939 */ GIM_Reject,
28575 /* 78940 */ // Label 2441: @78940
28576 /* 78940 */ GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(79054),
28577 /* 78945 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28578 /* 78949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2445*/ GIMT_Encode4(79001), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4910 //
28579 /* 78956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28580 /* 78960 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28581 /* 78960 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28582 /* 78963 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28583 /* 78967 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28584 /* 78972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8),
28585 /* 78975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28586 /* 78977 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28587 /* 78979 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28588 /* 78981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28589 /* 78984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28590 /* 78990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28591 /* 78996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28592 /* 78999 */ GIR_RootConstrainSelectedInstOperands,
28593 /* 79000 */ // GIR_Coverage, 4910,
28594 /* 79000 */ GIR_EraseRootFromParent_Done,
28595 /* 79001 */ // Label 2445: @79001
28596 /* 79001 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2446*/ GIMT_Encode4(79053), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4912 //
28597 /* 79008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28598 /* 79012 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28599 /* 79012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28600 /* 79015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28601 /* 79019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28602 /* 79024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8),
28603 /* 79027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28604 /* 79029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28605 /* 79031 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28606 /* 79033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28607 /* 79036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28608 /* 79042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28609 /* 79048 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28610 /* 79051 */ GIR_RootConstrainSelectedInstOperands,
28611 /* 79052 */ // GIR_Coverage, 4912,
28612 /* 79052 */ GIR_EraseRootFromParent_Done,
28613 /* 79053 */ // Label 2446: @79053
28614 /* 79053 */ GIM_Reject,
28615 /* 79054 */ // Label 2444: @79054
28616 /* 79054 */ GIM_Reject,
28617 /* 79055 */ // Label 2440: @79055
28618 /* 79055 */ GIM_Reject,
28619 /* 79056 */ // Label 2437: @79056
28620 /* 79056 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(79314),
28621 /* 79061 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28622 /* 79064 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28623 /* 79067 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28624 /* 79070 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28625 /* 79073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28626 /* 79077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28627 /* 79081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28628 /* 79085 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(79199),
28629 /* 79090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28630 /* 79094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2449*/ GIMT_Encode4(79146), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4902 //
28631 /* 79101 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28632 /* 79105 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28633 /* 79105 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28634 /* 79108 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28635 /* 79112 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28636 /* 79117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
28637 /* 79120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28638 /* 79122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28639 /* 79124 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28640 /* 79126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28641 /* 79129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28642 /* 79135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28643 /* 79141 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28644 /* 79144 */ GIR_RootConstrainSelectedInstOperands,
28645 /* 79145 */ // GIR_Coverage, 4902,
28646 /* 79145 */ GIR_EraseRootFromParent_Done,
28647 /* 79146 */ // Label 2449: @79146
28648 /* 79146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2450*/ GIMT_Encode4(79198), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4904 //
28649 /* 79153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28650 /* 79157 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28651 /* 79157 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28652 /* 79160 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28653 /* 79164 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28654 /* 79169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16),
28655 /* 79172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28656 /* 79174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28657 /* 79176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28658 /* 79178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28659 /* 79181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28660 /* 79187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28661 /* 79193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28662 /* 79196 */ GIR_RootConstrainSelectedInstOperands,
28663 /* 79197 */ // GIR_Coverage, 4904,
28664 /* 79197 */ GIR_EraseRootFromParent_Done,
28665 /* 79198 */ // Label 2450: @79198
28666 /* 79198 */ GIM_Reject,
28667 /* 79199 */ // Label 2448: @79199
28668 /* 79199 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(79313),
28669 /* 79204 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28670 /* 79208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2452*/ GIMT_Encode4(79260), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4914 //
28671 /* 79215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28672 /* 79219 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28673 /* 79219 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28674 /* 79222 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28675 /* 79226 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28676 /* 79231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16),
28677 /* 79234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28678 /* 79236 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28679 /* 79238 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28680 /* 79240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28681 /* 79243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28682 /* 79249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28683 /* 79255 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28684 /* 79258 */ GIR_RootConstrainSelectedInstOperands,
28685 /* 79259 */ // GIR_Coverage, 4914,
28686 /* 79259 */ GIR_EraseRootFromParent_Done,
28687 /* 79260 */ // Label 2452: @79260
28688 /* 79260 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2453*/ GIMT_Encode4(79312), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4916 //
28689 /* 79267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28690 /* 79271 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28691 /* 79271 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28692 /* 79274 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28693 /* 79278 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28694 /* 79283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16),
28695 /* 79286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28696 /* 79288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28697 /* 79290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28698 /* 79292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28699 /* 79295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28700 /* 79301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28701 /* 79307 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28702 /* 79310 */ GIR_RootConstrainSelectedInstOperands,
28703 /* 79311 */ // GIR_Coverage, 4916,
28704 /* 79311 */ GIR_EraseRootFromParent_Done,
28705 /* 79312 */ // Label 2453: @79312
28706 /* 79312 */ GIM_Reject,
28707 /* 79313 */ // Label 2451: @79313
28708 /* 79313 */ GIM_Reject,
28709 /* 79314 */ // Label 2447: @79314
28710 /* 79314 */ GIM_Reject,
28711 /* 79315 */ // Label 2438: @79315
28712 /* 79315 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(79573),
28713 /* 79320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28714 /* 79323 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28715 /* 79326 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28716 /* 79329 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28717 /* 79332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28718 /* 79336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28719 /* 79340 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28720 /* 79344 */ GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(79458),
28721 /* 79349 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28722 /* 79353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2456*/ GIMT_Encode4(79405), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4906 //
28723 /* 79360 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28724 /* 79364 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28725 /* 79364 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28726 /* 79367 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28727 /* 79371 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28728 /* 79376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32),
28729 /* 79379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28730 /* 79381 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28731 /* 79383 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28732 /* 79385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28733 /* 79388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28734 /* 79394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28735 /* 79400 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28736 /* 79403 */ GIR_RootConstrainSelectedInstOperands,
28737 /* 79404 */ // GIR_Coverage, 4906,
28738 /* 79404 */ GIR_EraseRootFromParent_Done,
28739 /* 79405 */ // Label 2456: @79405
28740 /* 79405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2457*/ GIMT_Encode4(79457), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4908 //
28741 /* 79412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28742 /* 79416 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28743 /* 79416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28744 /* 79419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28745 /* 79423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28746 /* 79428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32),
28747 /* 79431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28748 /* 79433 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28749 /* 79435 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28750 /* 79437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28751 /* 79440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28752 /* 79446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28753 /* 79452 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28754 /* 79455 */ GIR_RootConstrainSelectedInstOperands,
28755 /* 79456 */ // GIR_Coverage, 4908,
28756 /* 79456 */ GIR_EraseRootFromParent_Done,
28757 /* 79457 */ // Label 2457: @79457
28758 /* 79457 */ GIM_Reject,
28759 /* 79458 */ // Label 2455: @79458
28760 /* 79458 */ GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(79572),
28761 /* 79463 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28762 /* 79467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2459*/ GIMT_Encode4(79519), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4918 //
28763 /* 79474 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28764 /* 79478 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28765 /* 79478 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28766 /* 79481 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28767 /* 79485 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28768 /* 79490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32),
28769 /* 79493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28770 /* 79495 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28771 /* 79497 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28772 /* 79499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28773 /* 79502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28774 /* 79508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28775 /* 79514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28776 /* 79517 */ GIR_RootConstrainSelectedInstOperands,
28777 /* 79518 */ // GIR_Coverage, 4918,
28778 /* 79518 */ GIR_EraseRootFromParent_Done,
28779 /* 79519 */ // Label 2459: @79519
28780 /* 79519 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2460*/ GIMT_Encode4(79571), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4920 //
28781 /* 79526 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28782 /* 79530 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28783 /* 79530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28784 /* 79533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28785 /* 79537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28786 /* 79542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32),
28787 /* 79545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28788 /* 79547 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28789 /* 79549 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28790 /* 79551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28791 /* 79554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28792 /* 79560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28793 /* 79566 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28794 /* 79569 */ GIR_RootConstrainSelectedInstOperands,
28795 /* 79570 */ // GIR_Coverage, 4920,
28796 /* 79570 */ GIR_EraseRootFromParent_Done,
28797 /* 79571 */ // Label 2460: @79571
28798 /* 79571 */ GIM_Reject,
28799 /* 79572 */ // Label 2458: @79572
28800 /* 79572 */ GIM_Reject,
28801 /* 79573 */ // Label 2454: @79573
28802 /* 79573 */ GIM_Reject,
28803 /* 79574 */ // Label 2439: @79574
28804 /* 79574 */ GIM_Reject,
28805 /* 79575 */ // Label 2435: @79575
28806 /* 79575 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(80258),
28807 /* 79580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
28808 /* 79585 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2465*/ GIMT_Encode4(80257),
28809 /* 79596 */ /*GILLT_v16s8*//*Label 2462*/ GIMT_Encode4(79616), GIMT_Encode4(0),
28810 /* 79604 */ /*GILLT_v8s16*//*Label 2463*/ GIMT_Encode4(79785), GIMT_Encode4(0),
28811 /* 79612 */ /*GILLT_v4s32*//*Label 2464*/ GIMT_Encode4(80021),
28812 /* 79616 */ // Label 2462: @79616
28813 /* 79616 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(79784),
28814 /* 79621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28815 /* 79624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28816 /* 79627 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28817 /* 79630 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
28818 /* 79633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28819 /* 79637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2467*/ GIMT_Encode4(79710), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5052 //
28820 /* 79644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
28821 /* 79648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28822 /* 79652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28823 /* 79656 */ // MIs[1] Operand 1
28824 /* 79656 */ // No operand predicates
28825 /* 79656 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28826 /* 79660 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28827 /* 79664 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28828 /* 79666 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3845:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
28829 /* 79666 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28830 /* 79669 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28831 /* 79673 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28832 /* 79678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8),
28833 /* 79681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28834 /* 79683 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28835 /* 79685 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28836 /* 79687 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28837 /* 79690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28838 /* 79693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28839 /* 79699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28840 /* 79705 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28841 /* 79708 */ GIR_RootConstrainSelectedInstOperands,
28842 /* 79709 */ // GIR_Coverage, 5052,
28843 /* 79709 */ GIR_EraseRootFromParent_Done,
28844 /* 79710 */ // Label 2467: @79710
28845 /* 79710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2468*/ GIMT_Encode4(79783), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5058 //
28846 /* 79717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
28847 /* 79721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28848 /* 79725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28849 /* 79729 */ // MIs[1] Operand 1
28850 /* 79729 */ // No operand predicates
28851 /* 79729 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28852 /* 79733 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28853 /* 79737 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28854 /* 79739 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3845:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
28855 /* 79739 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28856 /* 79742 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28857 /* 79746 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28858 /* 79751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8),
28859 /* 79754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28860 /* 79756 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28861 /* 79758 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28862 /* 79760 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28863 /* 79763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28864 /* 79766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28865 /* 79772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28866 /* 79778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28867 /* 79781 */ GIR_RootConstrainSelectedInstOperands,
28868 /* 79782 */ // GIR_Coverage, 5058,
28869 /* 79782 */ GIR_EraseRootFromParent_Done,
28870 /* 79783 */ // Label 2468: @79783
28871 /* 79783 */ GIM_Reject,
28872 /* 79784 */ // Label 2466: @79784
28873 /* 79784 */ GIM_Reject,
28874 /* 79785 */ // Label 2463: @79785
28875 /* 79785 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(80020),
28876 /* 79790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28877 /* 79793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28878 /* 79796 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
28879 /* 79799 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
28880 /* 79802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28881 /* 79806 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(79946),
28882 /* 79811 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
28883 /* 79815 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28884 /* 79819 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28885 /* 79823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2471*/ GIMT_Encode4(79884), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4483 //
28886 /* 79830 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28887 /* 79834 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28888 /* 79838 */ // MIs[1] Operand 1
28889 /* 79838 */ // No operand predicates
28890 /* 79838 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28891 /* 79840 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3845:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
28892 /* 79840 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28893 /* 79843 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28894 /* 79847 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28895 /* 79852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16),
28896 /* 79855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28897 /* 79857 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28898 /* 79859 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28899 /* 79861 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28900 /* 79864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28901 /* 79867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28902 /* 79873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28903 /* 79879 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28904 /* 79882 */ GIR_RootConstrainSelectedInstOperands,
28905 /* 79883 */ // GIR_Coverage, 4483,
28906 /* 79883 */ GIR_EraseRootFromParent_Done,
28907 /* 79884 */ // Label 2471: @79884
28908 /* 79884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2472*/ GIMT_Encode4(79945), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5054 //
28909 /* 79891 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28910 /* 79895 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28911 /* 79899 */ // MIs[1] Operand 1
28912 /* 79899 */ // No operand predicates
28913 /* 79899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28914 /* 79901 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
28915 /* 79901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28916 /* 79904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28917 /* 79908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28918 /* 79913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16),
28919 /* 79916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28920 /* 79918 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28921 /* 79920 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28922 /* 79922 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28923 /* 79925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28924 /* 79928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28925 /* 79934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28926 /* 79940 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28927 /* 79943 */ GIR_RootConstrainSelectedInstOperands,
28928 /* 79944 */ // GIR_Coverage, 5054,
28929 /* 79944 */ GIR_EraseRootFromParent_Done,
28930 /* 79945 */ // Label 2472: @79945
28931 /* 79945 */ GIM_Reject,
28932 /* 79946 */ // Label 2470: @79946
28933 /* 79946 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2473*/ GIMT_Encode4(80019), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5060 //
28934 /* 79953 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
28935 /* 79957 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28936 /* 79961 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28937 /* 79965 */ // MIs[1] Operand 1
28938 /* 79965 */ // No operand predicates
28939 /* 79965 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28940 /* 79969 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28941 /* 79973 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28942 /* 79975 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
28943 /* 79975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28944 /* 79978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28945 /* 79982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28946 /* 79987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16),
28947 /* 79990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28948 /* 79992 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28949 /* 79994 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28950 /* 79996 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28951 /* 79999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28952 /* 80002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28953 /* 80008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28954 /* 80014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28955 /* 80017 */ GIR_RootConstrainSelectedInstOperands,
28956 /* 80018 */ // GIR_Coverage, 5060,
28957 /* 80018 */ GIR_EraseRootFromParent_Done,
28958 /* 80019 */ // Label 2473: @80019
28959 /* 80019 */ GIM_Reject,
28960 /* 80020 */ // Label 2469: @80020
28961 /* 80020 */ GIM_Reject,
28962 /* 80021 */ // Label 2464: @80021
28963 /* 80021 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(80256),
28964 /* 80026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28965 /* 80029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28966 /* 80032 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28967 /* 80035 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
28968 /* 80038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28969 /* 80042 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(80182),
28970 /* 80047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
28971 /* 80051 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28972 /* 80055 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28973 /* 80059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2476*/ GIMT_Encode4(80120), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4485 //
28974 /* 80066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28975 /* 80070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28976 /* 80074 */ // MIs[1] Operand 1
28977 /* 80074 */ // No operand predicates
28978 /* 80074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28979 /* 80076 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3845:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
28980 /* 80076 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28981 /* 80079 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28982 /* 80083 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28983 /* 80088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32),
28984 /* 80091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28985 /* 80093 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28986 /* 80095 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28987 /* 80097 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28988 /* 80100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28989 /* 80103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28990 /* 80109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28991 /* 80115 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28992 /* 80118 */ GIR_RootConstrainSelectedInstOperands,
28993 /* 80119 */ // GIR_Coverage, 4485,
28994 /* 80119 */ GIR_EraseRootFromParent_Done,
28995 /* 80120 */ // Label 2476: @80120
28996 /* 80120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2477*/ GIMT_Encode4(80181), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5056 //
28997 /* 80127 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28998 /* 80131 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28999 /* 80135 */ // MIs[1] Operand 1
29000 /* 80135 */ // No operand predicates
29001 /* 80135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29002 /* 80137 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29003 /* 80137 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29004 /* 80140 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29005 /* 80144 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29006 /* 80149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32),
29007 /* 80152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29008 /* 80154 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29009 /* 80156 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29010 /* 80158 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29011 /* 80161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29012 /* 80164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29013 /* 80170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29014 /* 80176 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29015 /* 80179 */ GIR_RootConstrainSelectedInstOperands,
29016 /* 80180 */ // GIR_Coverage, 5056,
29017 /* 80180 */ GIR_EraseRootFromParent_Done,
29018 /* 80181 */ // Label 2477: @80181
29019 /* 80181 */ GIM_Reject,
29020 /* 80182 */ // Label 2475: @80182
29021 /* 80182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2478*/ GIMT_Encode4(80255), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5062 //
29022 /* 80189 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29023 /* 80193 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29024 /* 80197 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29025 /* 80201 */ // MIs[1] Operand 1
29026 /* 80201 */ // No operand predicates
29027 /* 80201 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29028 /* 80205 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29029 /* 80209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29030 /* 80211 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29031 /* 80211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29032 /* 80214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29033 /* 80218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29034 /* 80223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32),
29035 /* 80226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29036 /* 80228 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29037 /* 80230 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29038 /* 80232 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29039 /* 80235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29040 /* 80238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29041 /* 80244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29042 /* 80250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29043 /* 80253 */ GIR_RootConstrainSelectedInstOperands,
29044 /* 80254 */ // GIR_Coverage, 5062,
29045 /* 80254 */ GIR_EraseRootFromParent_Done,
29046 /* 80255 */ // Label 2478: @80255
29047 /* 80255 */ GIM_Reject,
29048 /* 80256 */ // Label 2474: @80256
29049 /* 80256 */ GIM_Reject,
29050 /* 80257 */ // Label 2465: @80257
29051 /* 80257 */ GIM_Reject,
29052 /* 80258 */ // Label 2461: @80258
29053 /* 80258 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(80657),
29054 /* 80263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29055 /* 80268 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
29056 /* 80271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29057 /* 80274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29058 /* 80277 */ GIM_SwitchType, /*MI*/0, /*Op*/4, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2483*/ GIMT_Encode4(80656),
29059 /* 80288 */ /*GILLT_v16s8*//*Label 2480*/ GIMT_Encode4(80308), GIMT_Encode4(0),
29060 /* 80296 */ /*GILLT_v8s16*//*Label 2481*/ GIMT_Encode4(80424), GIMT_Encode4(0),
29061 /* 80304 */ /*GILLT_v4s32*//*Label 2482*/ GIMT_Encode4(80540),
29062 /* 80308 */ // Label 2480: @80308
29063 /* 80308 */ GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(80423),
29064 /* 80313 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
29065 /* 80316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29066 /* 80320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2485*/ GIMT_Encode4(80371), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3428 //
29067 /* 80327 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29068 /* 80331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29069 /* 80335 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29070 /* 80339 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29071 /* 80343 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29072 /* 80343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8),
29073 /* 80346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29074 /* 80348 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29075 /* 80350 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29076 /* 80352 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29077 /* 80354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29078 /* 80357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29079 /* 80363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29080 /* 80369 */ GIR_RootConstrainSelectedInstOperands,
29081 /* 80370 */ // GIR_Coverage, 3428,
29082 /* 80370 */ GIR_EraseRootFromParent_Done,
29083 /* 80371 */ // Label 2485: @80371
29084 /* 80371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2486*/ GIMT_Encode4(80422), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3434 //
29085 /* 80378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29086 /* 80382 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29087 /* 80386 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29088 /* 80390 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29089 /* 80394 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29090 /* 80394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8),
29091 /* 80397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29092 /* 80399 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29093 /* 80401 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29094 /* 80403 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29095 /* 80405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29096 /* 80408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29097 /* 80414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29098 /* 80420 */ GIR_RootConstrainSelectedInstOperands,
29099 /* 80421 */ // GIR_Coverage, 3434,
29100 /* 80421 */ GIR_EraseRootFromParent_Done,
29101 /* 80422 */ // Label 2486: @80422
29102 /* 80422 */ GIM_Reject,
29103 /* 80423 */ // Label 2484: @80423
29104 /* 80423 */ GIM_Reject,
29105 /* 80424 */ // Label 2481: @80424
29106 /* 80424 */ GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(80539),
29107 /* 80429 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29108 /* 80432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29109 /* 80436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2488*/ GIMT_Encode4(80487), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3430 //
29110 /* 80443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29111 /* 80447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29112 /* 80451 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29113 /* 80455 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29114 /* 80459 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29115 /* 80459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16),
29116 /* 80462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29117 /* 80464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29118 /* 80466 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29119 /* 80468 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29120 /* 80470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29121 /* 80473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29122 /* 80479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29123 /* 80485 */ GIR_RootConstrainSelectedInstOperands,
29124 /* 80486 */ // GIR_Coverage, 3430,
29125 /* 80486 */ GIR_EraseRootFromParent_Done,
29126 /* 80487 */ // Label 2488: @80487
29127 /* 80487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2489*/ GIMT_Encode4(80538), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3436 //
29128 /* 80494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29129 /* 80498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29130 /* 80502 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29131 /* 80506 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29132 /* 80510 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29133 /* 80510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16),
29134 /* 80513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29135 /* 80515 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29136 /* 80517 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29137 /* 80519 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29138 /* 80521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29139 /* 80524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29140 /* 80530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29141 /* 80536 */ GIR_RootConstrainSelectedInstOperands,
29142 /* 80537 */ // GIR_Coverage, 3436,
29143 /* 80537 */ GIR_EraseRootFromParent_Done,
29144 /* 80538 */ // Label 2489: @80538
29145 /* 80538 */ GIM_Reject,
29146 /* 80539 */ // Label 2487: @80539
29147 /* 80539 */ GIM_Reject,
29148 /* 80540 */ // Label 2482: @80540
29149 /* 80540 */ GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(80655),
29150 /* 80545 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
29151 /* 80548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29152 /* 80552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2491*/ GIMT_Encode4(80603), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3432 //
29153 /* 80559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29154 /* 80563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29155 /* 80567 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29156 /* 80571 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29157 /* 80575 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29158 /* 80575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32),
29159 /* 80578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29160 /* 80580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29161 /* 80582 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29162 /* 80584 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29163 /* 80586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29164 /* 80589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29165 /* 80595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29166 /* 80601 */ GIR_RootConstrainSelectedInstOperands,
29167 /* 80602 */ // GIR_Coverage, 3432,
29168 /* 80602 */ GIR_EraseRootFromParent_Done,
29169 /* 80603 */ // Label 2491: @80603
29170 /* 80603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2492*/ GIMT_Encode4(80654), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3438 //
29171 /* 80610 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29172 /* 80614 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29173 /* 80618 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29174 /* 80622 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29175 /* 80626 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29176 /* 80626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32),
29177 /* 80629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29178 /* 80631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29179 /* 80633 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29180 /* 80635 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29181 /* 80637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29182 /* 80640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29183 /* 80646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29184 /* 80652 */ GIR_RootConstrainSelectedInstOperands,
29185 /* 80653 */ // GIR_Coverage, 3438,
29186 /* 80653 */ GIR_EraseRootFromParent_Done,
29187 /* 80654 */ // Label 2492: @80654
29188 /* 80654 */ GIM_Reject,
29189 /* 80655 */ // Label 2490: @80655
29190 /* 80655 */ GIM_Reject,
29191 /* 80656 */ // Label 2483: @80656
29192 /* 80656 */ GIM_Reject,
29193 /* 80657 */ // Label 2479: @80657
29194 /* 80657 */ GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(80845),
29195 /* 80662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
29196 /* 80667 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2496*/ GIMT_Encode4(80844),
29197 /* 80678 */ /*GILLT_v8s16*//*Label 2494*/ GIMT_Encode4(80690), GIMT_Encode4(0),
29198 /* 80686 */ /*GILLT_v4s32*//*Label 2495*/ GIMT_Encode4(80767),
29199 /* 80690 */ // Label 2494: @80690
29200 /* 80690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2497*/ GIMT_Encode4(80766), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4429 //
29201 /* 80697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29202 /* 80700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29203 /* 80703 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29204 /* 80706 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29205 /* 80709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29206 /* 80713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29207 /* 80717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29208 /* 80721 */ // MIs[1] Operand 1
29209 /* 80721 */ // No operand predicates
29210 /* 80721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29211 /* 80725 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29212 /* 80729 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29213 /* 80733 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29214 /* 80735 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3848:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29215 /* 80735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16),
29216 /* 80738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29217 /* 80740 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
29218 /* 80742 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29219 /* 80744 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29220 /* 80746 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29221 /* 80749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29222 /* 80752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29223 /* 80758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29224 /* 80764 */ GIR_RootConstrainSelectedInstOperands,
29225 /* 80765 */ // GIR_Coverage, 4429,
29226 /* 80765 */ GIR_EraseRootFromParent_Done,
29227 /* 80766 */ // Label 2497: @80766
29228 /* 80766 */ GIM_Reject,
29229 /* 80767 */ // Label 2495: @80767
29230 /* 80767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2498*/ GIMT_Encode4(80843), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4432 //
29231 /* 80774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29232 /* 80777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29233 /* 80780 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29234 /* 80783 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
29235 /* 80786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29236 /* 80790 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29237 /* 80794 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29238 /* 80798 */ // MIs[1] Operand 1
29239 /* 80798 */ // No operand predicates
29240 /* 80798 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29241 /* 80802 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29242 /* 80806 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29243 /* 80810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29244 /* 80812 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3848:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
29245 /* 80812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32),
29246 /* 80815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29247 /* 80817 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
29248 /* 80819 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29249 /* 80821 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29250 /* 80823 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29251 /* 80826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29252 /* 80829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29253 /* 80835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29254 /* 80841 */ GIR_RootConstrainSelectedInstOperands,
29255 /* 80842 */ // GIR_Coverage, 4432,
29256 /* 80842 */ GIR_EraseRootFromParent_Done,
29257 /* 80843 */ // Label 2498: @80843
29258 /* 80843 */ GIM_Reject,
29259 /* 80844 */ // Label 2496: @80844
29260 /* 80844 */ GIM_Reject,
29261 /* 80845 */ // Label 2493: @80845
29262 /* 80845 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2499*/ GIMT_Encode4(80940), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3077 //
29263 /* 80852 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2),
29264 /* 80857 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
29265 /* 80860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
29266 /* 80863 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
29267 /* 80866 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
29268 /* 80869 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
29269 /* 80872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
29270 /* 80876 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4109:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29271 /* 80876 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29272 /* 80879 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
29273 /* 80883 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29274 /* 80888 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
29275 /* 80892 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
29276 /* 80895 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
29277 /* 80899 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
29278 /* 80902 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
29279 /* 80907 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
29280 /* 80912 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
29281 /* 80917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2),
29282 /* 80920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29283 /* 80922 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
29284 /* 80924 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29285 /* 80927 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
29286 /* 80929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
29287 /* 80932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29288 /* 80938 */ GIR_RootConstrainSelectedInstOperands,
29289 /* 80939 */ // GIR_Coverage, 3077,
29290 /* 80939 */ GIR_EraseRootFromParent_Done,
29291 /* 80940 */ // Label 2499: @80940
29292 /* 80940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2500*/ GIMT_Encode4(81070), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3078 //
29293 /* 80947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3),
29294 /* 80952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
29295 /* 80955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
29296 /* 80958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
29297 /* 80961 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
29298 /* 80964 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
29299 /* 80967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
29300 /* 80971 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4106:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29301 /* 80971 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
29302 /* 80974 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29303 /* 80978 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29304 /* 80983 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
29305 /* 80985 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
29306 /* 80988 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
29307 /* 80992 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29308 /* 80997 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
29309 /* 81001 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
29310 /* 81004 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
29311 /* 81008 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
29312 /* 81011 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
29313 /* 81015 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
29314 /* 81018 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29315 /* 81021 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
29316 /* 81024 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
29317 /* 81029 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
29318 /* 81034 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
29319 /* 81039 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
29320 /* 81044 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
29321 /* 81049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo),
29322 /* 81052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29323 /* 81054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29324 /* 81057 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
29325 /* 81059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
29326 /* 81062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29327 /* 81068 */ GIR_RootConstrainSelectedInstOperands,
29328 /* 81069 */ // GIR_Coverage, 3078,
29329 /* 81069 */ GIR_EraseRootFromParent_Done,
29330 /* 81070 */ // Label 2500: @81070
29331 /* 81070 */ GIM_Reject,
29332 /* 81071 */ // Label 2416: @81071
29333 /* 81071 */ GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(84627),
29334 /* 81076 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
29335 /* 81079 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(82597),
29336 /* 81084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
29337 /* 81089 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2506*/ GIMT_Encode4(82596),
29338 /* 81100 */ /*GILLT_v16s8*//*Label 2503*/ GIMT_Encode4(81120), GIMT_Encode4(0),
29339 /* 81108 */ /*GILLT_v8s16*//*Label 2504*/ GIMT_Encode4(81612), GIMT_Encode4(0),
29340 /* 81116 */ /*GILLT_v4s32*//*Label 2505*/ GIMT_Encode4(82104),
29341 /* 81120 */ // Label 2503: @81120
29342 /* 81120 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(81611),
29343 /* 81125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29344 /* 81128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29345 /* 81131 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29346 /* 81134 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29347 /* 81137 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29348 /* 81140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29349 /* 81144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29350 /* 81148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29351 /* 81152 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(81266),
29352 /* 81157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29353 /* 81161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29354 /* 81165 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(81215), // Rule ID 4241 //
29355 /* 81170 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29356 /* 81174 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29357 /* 81174 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29358 /* 81177 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29359 /* 81181 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29360 /* 81186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8),
29361 /* 81189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29362 /* 81191 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29363 /* 81193 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29364 /* 81195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29365 /* 81198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29366 /* 81204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29367 /* 81210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29368 /* 81213 */ GIR_RootConstrainSelectedInstOperands,
29369 /* 81214 */ // GIR_Coverage, 4241,
29370 /* 81214 */ GIR_EraseRootFromParent_Done,
29371 /* 81215 */ // Label 2509: @81215
29372 /* 81215 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(81265), // Rule ID 4247 //
29373 /* 81220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29374 /* 81224 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29375 /* 81224 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29376 /* 81227 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29377 /* 81231 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29378 /* 81236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8),
29379 /* 81239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29380 /* 81241 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29381 /* 81243 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29382 /* 81245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29383 /* 81248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29384 /* 81254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29385 /* 81260 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29386 /* 81263 */ GIR_RootConstrainSelectedInstOperands,
29387 /* 81264 */ // GIR_Coverage, 4247,
29388 /* 81264 */ GIR_EraseRootFromParent_Done,
29389 /* 81265 */ // Label 2510: @81265
29390 /* 81265 */ GIM_Reject,
29391 /* 81266 */ // Label 2508: @81266
29392 /* 81266 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(81496),
29393 /* 81271 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29394 /* 81275 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(81385),
29395 /* 81280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29396 /* 81284 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(81334), // Rule ID 4253 //
29397 /* 81289 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29398 /* 81293 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29399 /* 81293 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29400 /* 81296 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29401 /* 81300 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29402 /* 81305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8),
29403 /* 81308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29404 /* 81310 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29405 /* 81312 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29406 /* 81314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29407 /* 81317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29408 /* 81323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29409 /* 81329 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29410 /* 81332 */ GIR_RootConstrainSelectedInstOperands,
29411 /* 81333 */ // GIR_Coverage, 4253,
29412 /* 81333 */ GIR_EraseRootFromParent_Done,
29413 /* 81334 */ // Label 2513: @81334
29414 /* 81334 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(81384), // Rule ID 4259 //
29415 /* 81339 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29416 /* 81343 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29417 /* 81343 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29418 /* 81346 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29419 /* 81350 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29420 /* 81355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8),
29421 /* 81358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29422 /* 81360 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29423 /* 81362 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29424 /* 81364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29425 /* 81367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29426 /* 81373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29427 /* 81379 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29428 /* 81382 */ GIR_RootConstrainSelectedInstOperands,
29429 /* 81383 */ // GIR_Coverage, 4259,
29430 /* 81383 */ GIR_EraseRootFromParent_Done,
29431 /* 81384 */ // Label 2514: @81384
29432 /* 81384 */ GIM_Reject,
29433 /* 81385 */ // Label 2512: @81385
29434 /* 81385 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(81495),
29435 /* 81390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29436 /* 81394 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(81444), // Rule ID 4265 //
29437 /* 81399 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29438 /* 81403 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29439 /* 81403 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29440 /* 81406 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29441 /* 81410 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29442 /* 81415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8),
29443 /* 81418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29444 /* 81420 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29445 /* 81422 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29446 /* 81424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29447 /* 81427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29448 /* 81433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29449 /* 81439 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29450 /* 81442 */ GIR_RootConstrainSelectedInstOperands,
29451 /* 81443 */ // GIR_Coverage, 4265,
29452 /* 81443 */ GIR_EraseRootFromParent_Done,
29453 /* 81444 */ // Label 2516: @81444
29454 /* 81444 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(81494), // Rule ID 4271 //
29455 /* 81449 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29456 /* 81453 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29457 /* 81453 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29458 /* 81456 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29459 /* 81460 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29460 /* 81465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8),
29461 /* 81468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29462 /* 81470 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29463 /* 81472 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29464 /* 81474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29465 /* 81477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29466 /* 81483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29467 /* 81489 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29468 /* 81492 */ GIR_RootConstrainSelectedInstOperands,
29469 /* 81493 */ // GIR_Coverage, 4271,
29470 /* 81493 */ GIR_EraseRootFromParent_Done,
29471 /* 81494 */ // Label 2517: @81494
29472 /* 81494 */ GIM_Reject,
29473 /* 81495 */ // Label 2515: @81495
29474 /* 81495 */ GIM_Reject,
29475 /* 81496 */ // Label 2511: @81496
29476 /* 81496 */ GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(81610),
29477 /* 81501 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29478 /* 81505 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29479 /* 81509 */ GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(81559), // Rule ID 4277 //
29480 /* 81514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29481 /* 81518 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29482 /* 81518 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29483 /* 81521 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29484 /* 81525 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29485 /* 81530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8),
29486 /* 81533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29487 /* 81535 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29488 /* 81537 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29489 /* 81539 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29490 /* 81542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29491 /* 81548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29492 /* 81554 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29493 /* 81557 */ GIR_RootConstrainSelectedInstOperands,
29494 /* 81558 */ // GIR_Coverage, 4277,
29495 /* 81558 */ GIR_EraseRootFromParent_Done,
29496 /* 81559 */ // Label 2519: @81559
29497 /* 81559 */ GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(81609), // Rule ID 4283 //
29498 /* 81564 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29499 /* 81568 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29500 /* 81568 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29501 /* 81571 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29502 /* 81575 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29503 /* 81580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8),
29504 /* 81583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29505 /* 81585 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29506 /* 81587 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29507 /* 81589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29508 /* 81592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29509 /* 81598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29510 /* 81604 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29511 /* 81607 */ GIR_RootConstrainSelectedInstOperands,
29512 /* 81608 */ // GIR_Coverage, 4283,
29513 /* 81608 */ GIR_EraseRootFromParent_Done,
29514 /* 81609 */ // Label 2520: @81609
29515 /* 81609 */ GIM_Reject,
29516 /* 81610 */ // Label 2518: @81610
29517 /* 81610 */ GIM_Reject,
29518 /* 81611 */ // Label 2507: @81611
29519 /* 81611 */ GIM_Reject,
29520 /* 81612 */ // Label 2504: @81612
29521 /* 81612 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(82103),
29522 /* 81617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29523 /* 81620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29524 /* 81623 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29525 /* 81626 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29526 /* 81629 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29527 /* 81632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29528 /* 81636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29529 /* 81640 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29530 /* 81644 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(81758),
29531 /* 81649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29532 /* 81653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29533 /* 81657 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(81707), // Rule ID 4243 //
29534 /* 81662 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29535 /* 81666 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29536 /* 81666 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29537 /* 81669 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29538 /* 81673 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29539 /* 81678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16),
29540 /* 81681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29541 /* 81683 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29542 /* 81685 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29543 /* 81687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29544 /* 81690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29545 /* 81696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29546 /* 81702 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29547 /* 81705 */ GIR_RootConstrainSelectedInstOperands,
29548 /* 81706 */ // GIR_Coverage, 4243,
29549 /* 81706 */ GIR_EraseRootFromParent_Done,
29550 /* 81707 */ // Label 2523: @81707
29551 /* 81707 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(81757), // Rule ID 4249 //
29552 /* 81712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29553 /* 81716 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29554 /* 81716 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29555 /* 81719 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29556 /* 81723 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29557 /* 81728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16),
29558 /* 81731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29559 /* 81733 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29560 /* 81735 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29561 /* 81737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29562 /* 81740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29563 /* 81746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29564 /* 81752 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29565 /* 81755 */ GIR_RootConstrainSelectedInstOperands,
29566 /* 81756 */ // GIR_Coverage, 4249,
29567 /* 81756 */ GIR_EraseRootFromParent_Done,
29568 /* 81757 */ // Label 2524: @81757
29569 /* 81757 */ GIM_Reject,
29570 /* 81758 */ // Label 2522: @81758
29571 /* 81758 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(81988),
29572 /* 81763 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29573 /* 81767 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(81877),
29574 /* 81772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29575 /* 81776 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(81826), // Rule ID 4255 //
29576 /* 81781 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29577 /* 81785 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29578 /* 81785 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29579 /* 81788 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29580 /* 81792 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29581 /* 81797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16),
29582 /* 81800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29583 /* 81802 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29584 /* 81804 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29585 /* 81806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29586 /* 81809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29587 /* 81815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29588 /* 81821 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29589 /* 81824 */ GIR_RootConstrainSelectedInstOperands,
29590 /* 81825 */ // GIR_Coverage, 4255,
29591 /* 81825 */ GIR_EraseRootFromParent_Done,
29592 /* 81826 */ // Label 2527: @81826
29593 /* 81826 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(81876), // Rule ID 4261 //
29594 /* 81831 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29595 /* 81835 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29596 /* 81835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29597 /* 81838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29598 /* 81842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29599 /* 81847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16),
29600 /* 81850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29601 /* 81852 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29602 /* 81854 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29603 /* 81856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29604 /* 81859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29605 /* 81865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29606 /* 81871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29607 /* 81874 */ GIR_RootConstrainSelectedInstOperands,
29608 /* 81875 */ // GIR_Coverage, 4261,
29609 /* 81875 */ GIR_EraseRootFromParent_Done,
29610 /* 81876 */ // Label 2528: @81876
29611 /* 81876 */ GIM_Reject,
29612 /* 81877 */ // Label 2526: @81877
29613 /* 81877 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(81987),
29614 /* 81882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29615 /* 81886 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(81936), // Rule ID 4267 //
29616 /* 81891 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29617 /* 81895 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29618 /* 81895 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29619 /* 81898 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29620 /* 81902 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29621 /* 81907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16),
29622 /* 81910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29623 /* 81912 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29624 /* 81914 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29625 /* 81916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29626 /* 81919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29627 /* 81925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29628 /* 81931 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29629 /* 81934 */ GIR_RootConstrainSelectedInstOperands,
29630 /* 81935 */ // GIR_Coverage, 4267,
29631 /* 81935 */ GIR_EraseRootFromParent_Done,
29632 /* 81936 */ // Label 2530: @81936
29633 /* 81936 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(81986), // Rule ID 4273 //
29634 /* 81941 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29635 /* 81945 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29636 /* 81945 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29637 /* 81948 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29638 /* 81952 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29639 /* 81957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16),
29640 /* 81960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29641 /* 81962 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29642 /* 81964 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29643 /* 81966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29644 /* 81969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29645 /* 81975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29646 /* 81981 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29647 /* 81984 */ GIR_RootConstrainSelectedInstOperands,
29648 /* 81985 */ // GIR_Coverage, 4273,
29649 /* 81985 */ GIR_EraseRootFromParent_Done,
29650 /* 81986 */ // Label 2531: @81986
29651 /* 81986 */ GIM_Reject,
29652 /* 81987 */ // Label 2529: @81987
29653 /* 81987 */ GIM_Reject,
29654 /* 81988 */ // Label 2525: @81988
29655 /* 81988 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(82102),
29656 /* 81993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29657 /* 81997 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29658 /* 82001 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(82051), // Rule ID 4279 //
29659 /* 82006 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29660 /* 82010 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29661 /* 82010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29662 /* 82013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29663 /* 82017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29664 /* 82022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16),
29665 /* 82025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29666 /* 82027 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29667 /* 82029 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29668 /* 82031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29669 /* 82034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29670 /* 82040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29671 /* 82046 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29672 /* 82049 */ GIR_RootConstrainSelectedInstOperands,
29673 /* 82050 */ // GIR_Coverage, 4279,
29674 /* 82050 */ GIR_EraseRootFromParent_Done,
29675 /* 82051 */ // Label 2533: @82051
29676 /* 82051 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(82101), // Rule ID 4285 //
29677 /* 82056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29678 /* 82060 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29679 /* 82060 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29680 /* 82063 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29681 /* 82067 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29682 /* 82072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16),
29683 /* 82075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29684 /* 82077 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29685 /* 82079 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29686 /* 82081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29687 /* 82084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29688 /* 82090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29689 /* 82096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29690 /* 82099 */ GIR_RootConstrainSelectedInstOperands,
29691 /* 82100 */ // GIR_Coverage, 4285,
29692 /* 82100 */ GIR_EraseRootFromParent_Done,
29693 /* 82101 */ // Label 2534: @82101
29694 /* 82101 */ GIM_Reject,
29695 /* 82102 */ // Label 2532: @82102
29696 /* 82102 */ GIM_Reject,
29697 /* 82103 */ // Label 2521: @82103
29698 /* 82103 */ GIM_Reject,
29699 /* 82104 */ // Label 2505: @82104
29700 /* 82104 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(82595),
29701 /* 82109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29702 /* 82112 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29703 /* 82115 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29704 /* 82118 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29705 /* 82121 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29706 /* 82124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29707 /* 82128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29708 /* 82132 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29709 /* 82136 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(82250),
29710 /* 82141 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29711 /* 82145 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29712 /* 82149 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(82199), // Rule ID 4245 //
29713 /* 82154 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29714 /* 82158 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29715 /* 82158 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29716 /* 82161 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29717 /* 82165 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29718 /* 82170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32),
29719 /* 82173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29720 /* 82175 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29721 /* 82177 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29722 /* 82179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29723 /* 82182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29724 /* 82188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29725 /* 82194 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29726 /* 82197 */ GIR_RootConstrainSelectedInstOperands,
29727 /* 82198 */ // GIR_Coverage, 4245,
29728 /* 82198 */ GIR_EraseRootFromParent_Done,
29729 /* 82199 */ // Label 2537: @82199
29730 /* 82199 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(82249), // Rule ID 4251 //
29731 /* 82204 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29732 /* 82208 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29733 /* 82208 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29734 /* 82211 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29735 /* 82215 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29736 /* 82220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32),
29737 /* 82223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29738 /* 82225 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29739 /* 82227 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29740 /* 82229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29741 /* 82232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29742 /* 82238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29743 /* 82244 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29744 /* 82247 */ GIR_RootConstrainSelectedInstOperands,
29745 /* 82248 */ // GIR_Coverage, 4251,
29746 /* 82248 */ GIR_EraseRootFromParent_Done,
29747 /* 82249 */ // Label 2538: @82249
29748 /* 82249 */ GIM_Reject,
29749 /* 82250 */ // Label 2536: @82250
29750 /* 82250 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(82480),
29751 /* 82255 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29752 /* 82259 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(82369),
29753 /* 82264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29754 /* 82268 */ GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(82318), // Rule ID 4257 //
29755 /* 82273 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29756 /* 82277 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29757 /* 82277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29758 /* 82280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29759 /* 82284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29760 /* 82289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32),
29761 /* 82292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29762 /* 82294 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29763 /* 82296 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29764 /* 82298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29765 /* 82301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29766 /* 82307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29767 /* 82313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29768 /* 82316 */ GIR_RootConstrainSelectedInstOperands,
29769 /* 82317 */ // GIR_Coverage, 4257,
29770 /* 82317 */ GIR_EraseRootFromParent_Done,
29771 /* 82318 */ // Label 2541: @82318
29772 /* 82318 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(82368), // Rule ID 4263 //
29773 /* 82323 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29774 /* 82327 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29775 /* 82327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29776 /* 82330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29777 /* 82334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29778 /* 82339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32),
29779 /* 82342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29780 /* 82344 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29781 /* 82346 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29782 /* 82348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29783 /* 82351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29784 /* 82357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29785 /* 82363 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29786 /* 82366 */ GIR_RootConstrainSelectedInstOperands,
29787 /* 82367 */ // GIR_Coverage, 4263,
29788 /* 82367 */ GIR_EraseRootFromParent_Done,
29789 /* 82368 */ // Label 2542: @82368
29790 /* 82368 */ GIM_Reject,
29791 /* 82369 */ // Label 2540: @82369
29792 /* 82369 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(82479),
29793 /* 82374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29794 /* 82378 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(82428), // Rule ID 4269 //
29795 /* 82383 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29796 /* 82387 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29797 /* 82387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29798 /* 82390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29799 /* 82394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29800 /* 82399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32),
29801 /* 82402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29802 /* 82404 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29803 /* 82406 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29804 /* 82408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29805 /* 82411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29806 /* 82417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29807 /* 82423 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29808 /* 82426 */ GIR_RootConstrainSelectedInstOperands,
29809 /* 82427 */ // GIR_Coverage, 4269,
29810 /* 82427 */ GIR_EraseRootFromParent_Done,
29811 /* 82428 */ // Label 2544: @82428
29812 /* 82428 */ GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(82478), // Rule ID 4275 //
29813 /* 82433 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29814 /* 82437 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29815 /* 82437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29816 /* 82440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29817 /* 82444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29818 /* 82449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32),
29819 /* 82452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29820 /* 82454 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29821 /* 82456 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29822 /* 82458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29823 /* 82461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29824 /* 82467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29825 /* 82473 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29826 /* 82476 */ GIR_RootConstrainSelectedInstOperands,
29827 /* 82477 */ // GIR_Coverage, 4275,
29828 /* 82477 */ GIR_EraseRootFromParent_Done,
29829 /* 82478 */ // Label 2545: @82478
29830 /* 82478 */ GIM_Reject,
29831 /* 82479 */ // Label 2543: @82479
29832 /* 82479 */ GIM_Reject,
29833 /* 82480 */ // Label 2539: @82480
29834 /* 82480 */ GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(82594),
29835 /* 82485 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29836 /* 82489 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29837 /* 82493 */ GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(82543), // Rule ID 4281 //
29838 /* 82498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29839 /* 82502 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29840 /* 82502 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29841 /* 82505 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29842 /* 82509 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29843 /* 82514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32),
29844 /* 82517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29845 /* 82519 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29846 /* 82521 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29847 /* 82523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29848 /* 82526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29849 /* 82532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29850 /* 82538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29851 /* 82541 */ GIR_RootConstrainSelectedInstOperands,
29852 /* 82542 */ // GIR_Coverage, 4281,
29853 /* 82542 */ GIR_EraseRootFromParent_Done,
29854 /* 82543 */ // Label 2547: @82543
29855 /* 82543 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(82593), // Rule ID 4287 //
29856 /* 82548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29857 /* 82552 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29858 /* 82552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29859 /* 82555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29860 /* 82559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29861 /* 82564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32),
29862 /* 82567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29863 /* 82569 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29864 /* 82571 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29865 /* 82573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29866 /* 82576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29867 /* 82582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29868 /* 82588 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29869 /* 82591 */ GIR_RootConstrainSelectedInstOperands,
29870 /* 82592 */ // GIR_Coverage, 4287,
29871 /* 82592 */ GIR_EraseRootFromParent_Done,
29872 /* 82593 */ // Label 2548: @82593
29873 /* 82593 */ GIM_Reject,
29874 /* 82594 */ // Label 2546: @82594
29875 /* 82594 */ GIM_Reject,
29876 /* 82595 */ // Label 2535: @82595
29877 /* 82595 */ GIM_Reject,
29878 /* 82596 */ // Label 2506: @82596
29879 /* 82596 */ GIM_Reject,
29880 /* 82597 */ // Label 2502: @82597
29881 /* 82597 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(83207),
29882 /* 82602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
29883 /* 82607 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2552*/ GIMT_Encode4(83206),
29884 /* 82618 */ /*GILLT_v16s8*//*Label 2550*/ GIMT_Encode4(82630), GIMT_Encode4(0),
29885 /* 82626 */ /*GILLT_v8s16*//*Label 2551*/ GIMT_Encode4(82918),
29886 /* 82630 */ // Label 2550: @82630
29887 /* 82630 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(82917),
29888 /* 82635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29889 /* 82638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29890 /* 82641 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29891 /* 82644 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29892 /* 82647 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29893 /* 82650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29894 /* 82654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29895 /* 82658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29896 /* 82662 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(82746),
29897 /* 82667 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29898 /* 82671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29899 /* 82675 */ GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(82710), // Rule ID 5004 //
29900 /* 82680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29901 /* 82684 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29902 /* 82684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh),
29903 /* 82687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29904 /* 82689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29905 /* 82691 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29906 /* 82693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29907 /* 82696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29908 /* 82702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29909 /* 82708 */ GIR_RootConstrainSelectedInstOperands,
29910 /* 82709 */ // GIR_Coverage, 5004,
29911 /* 82709 */ GIR_EraseRootFromParent_Done,
29912 /* 82710 */ // Label 2555: @82710
29913 /* 82710 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(82745), // Rule ID 5006 //
29914 /* 82715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29915 /* 82719 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29916 /* 82719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th),
29917 /* 82722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29918 /* 82724 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29919 /* 82726 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29920 /* 82728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29921 /* 82731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29922 /* 82737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29923 /* 82743 */ GIR_RootConstrainSelectedInstOperands,
29924 /* 82744 */ // GIR_Coverage, 5006,
29925 /* 82744 */ GIR_EraseRootFromParent_Done,
29926 /* 82745 */ // Label 2556: @82745
29927 /* 82745 */ GIM_Reject,
29928 /* 82746 */ // Label 2554: @82746
29929 /* 82746 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(82916),
29930 /* 82751 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29931 /* 82755 */ GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(82835),
29932 /* 82760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29933 /* 82764 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(82799), // Rule ID 5012 //
29934 /* 82769 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29935 /* 82773 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29936 /* 82773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh),
29937 /* 82776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29938 /* 82778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29939 /* 82780 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29940 /* 82782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29941 /* 82785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29942 /* 82791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29943 /* 82797 */ GIR_RootConstrainSelectedInstOperands,
29944 /* 82798 */ // GIR_Coverage, 5012,
29945 /* 82798 */ GIR_EraseRootFromParent_Done,
29946 /* 82799 */ // Label 2559: @82799
29947 /* 82799 */ GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(82834), // Rule ID 5014 //
29948 /* 82804 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29949 /* 82808 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29950 /* 82808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th),
29951 /* 82811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29952 /* 82813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29953 /* 82815 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29954 /* 82817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29955 /* 82820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29956 /* 82826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29957 /* 82832 */ GIR_RootConstrainSelectedInstOperands,
29958 /* 82833 */ // GIR_Coverage, 5014,
29959 /* 82833 */ GIR_EraseRootFromParent_Done,
29960 /* 82834 */ // Label 2560: @82834
29961 /* 82834 */ GIM_Reject,
29962 /* 82835 */ // Label 2558: @82835
29963 /* 82835 */ GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(82915),
29964 /* 82840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29965 /* 82844 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(82879), // Rule ID 5020 //
29966 /* 82849 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29967 /* 82853 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29968 /* 82853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh),
29969 /* 82856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29970 /* 82858 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29971 /* 82860 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29972 /* 82862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29973 /* 82865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29974 /* 82871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29975 /* 82877 */ GIR_RootConstrainSelectedInstOperands,
29976 /* 82878 */ // GIR_Coverage, 5020,
29977 /* 82878 */ GIR_EraseRootFromParent_Done,
29978 /* 82879 */ // Label 2562: @82879
29979 /* 82879 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(82914), // Rule ID 5022 //
29980 /* 82884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29981 /* 82888 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29982 /* 82888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th),
29983 /* 82891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29984 /* 82893 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29985 /* 82895 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29986 /* 82897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29987 /* 82900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29988 /* 82906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29989 /* 82912 */ GIR_RootConstrainSelectedInstOperands,
29990 /* 82913 */ // GIR_Coverage, 5022,
29991 /* 82913 */ GIR_EraseRootFromParent_Done,
29992 /* 82914 */ // Label 2563: @82914
29993 /* 82914 */ GIM_Reject,
29994 /* 82915 */ // Label 2561: @82915
29995 /* 82915 */ GIM_Reject,
29996 /* 82916 */ // Label 2557: @82916
29997 /* 82916 */ GIM_Reject,
29998 /* 82917 */ // Label 2553: @82917
29999 /* 82917 */ GIM_Reject,
30000 /* 82918 */ // Label 2551: @82918
30001 /* 82918 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(83205),
30002 /* 82923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30003 /* 82926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30004 /* 82929 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30005 /* 82932 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30006 /* 82935 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30007 /* 82938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30008 /* 82942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30009 /* 82946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30010 /* 82950 */ GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(83034),
30011 /* 82955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30012 /* 82959 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30013 /* 82963 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(82998), // Rule ID 5000 //
30014 /* 82968 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30015 /* 82972 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30016 /* 82972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh),
30017 /* 82975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30018 /* 82977 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30019 /* 82979 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30020 /* 82981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30021 /* 82984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30022 /* 82990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30023 /* 82996 */ GIR_RootConstrainSelectedInstOperands,
30024 /* 82997 */ // GIR_Coverage, 5000,
30025 /* 82997 */ GIR_EraseRootFromParent_Done,
30026 /* 82998 */ // Label 2566: @82998
30027 /* 82998 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(83033), // Rule ID 5002 //
30028 /* 83003 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30029 /* 83007 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30030 /* 83007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th),
30031 /* 83010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30032 /* 83012 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30033 /* 83014 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30034 /* 83016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30035 /* 83019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30036 /* 83025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30037 /* 83031 */ GIR_RootConstrainSelectedInstOperands,
30038 /* 83032 */ // GIR_Coverage, 5002,
30039 /* 83032 */ GIR_EraseRootFromParent_Done,
30040 /* 83033 */ // Label 2567: @83033
30041 /* 83033 */ GIM_Reject,
30042 /* 83034 */ // Label 2565: @83034
30043 /* 83034 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(83204),
30044 /* 83039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30045 /* 83043 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(83123),
30046 /* 83048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30047 /* 83052 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(83087), // Rule ID 5008 //
30048 /* 83057 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30049 /* 83061 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30050 /* 83061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh),
30051 /* 83064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30052 /* 83066 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30053 /* 83068 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30054 /* 83070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30055 /* 83073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30056 /* 83079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30057 /* 83085 */ GIR_RootConstrainSelectedInstOperands,
30058 /* 83086 */ // GIR_Coverage, 5008,
30059 /* 83086 */ GIR_EraseRootFromParent_Done,
30060 /* 83087 */ // Label 2570: @83087
30061 /* 83087 */ GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(83122), // Rule ID 5010 //
30062 /* 83092 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30063 /* 83096 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30064 /* 83096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th),
30065 /* 83099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30066 /* 83101 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30067 /* 83103 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30068 /* 83105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30069 /* 83108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30070 /* 83114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30071 /* 83120 */ GIR_RootConstrainSelectedInstOperands,
30072 /* 83121 */ // GIR_Coverage, 5010,
30073 /* 83121 */ GIR_EraseRootFromParent_Done,
30074 /* 83122 */ // Label 2571: @83122
30075 /* 83122 */ GIM_Reject,
30076 /* 83123 */ // Label 2569: @83123
30077 /* 83123 */ GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(83203),
30078 /* 83128 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30079 /* 83132 */ GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(83167), // Rule ID 5016 //
30080 /* 83137 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30081 /* 83141 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30082 /* 83141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh),
30083 /* 83144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30084 /* 83146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30085 /* 83148 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30086 /* 83150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30087 /* 83153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30088 /* 83159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30089 /* 83165 */ GIR_RootConstrainSelectedInstOperands,
30090 /* 83166 */ // GIR_Coverage, 5016,
30091 /* 83166 */ GIR_EraseRootFromParent_Done,
30092 /* 83167 */ // Label 2573: @83167
30093 /* 83167 */ GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(83202), // Rule ID 5018 //
30094 /* 83172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30095 /* 83176 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30096 /* 83176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th),
30097 /* 83179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30098 /* 83181 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30099 /* 83183 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30100 /* 83185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30101 /* 83188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30102 /* 83194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30103 /* 83200 */ GIR_RootConstrainSelectedInstOperands,
30104 /* 83201 */ // GIR_Coverage, 5018,
30105 /* 83201 */ GIR_EraseRootFromParent_Done,
30106 /* 83202 */ // Label 2574: @83202
30107 /* 83202 */ GIM_Reject,
30108 /* 83203 */ // Label 2572: @83203
30109 /* 83203 */ GIM_Reject,
30110 /* 83204 */ // Label 2568: @83204
30111 /* 83204 */ GIM_Reject,
30112 /* 83205 */ // Label 2564: @83205
30113 /* 83205 */ GIM_Reject,
30114 /* 83206 */ // Label 2552: @83206
30115 /* 83206 */ GIM_Reject,
30116 /* 83207 */ // Label 2549: @83207
30117 /* 83207 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(84371),
30118 /* 83212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
30119 /* 83217 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2579*/ GIMT_Encode4(84370),
30120 /* 83228 */ /*GILLT_v16s8*//*Label 2576*/ GIMT_Encode4(83248), GIMT_Encode4(0),
30121 /* 83236 */ /*GILLT_v8s16*//*Label 2577*/ GIMT_Encode4(83622), GIMT_Encode4(0),
30122 /* 83244 */ /*GILLT_v4s32*//*Label 2578*/ GIMT_Encode4(83996),
30123 /* 83248 */ // Label 2576: @83248
30124 /* 83248 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(83621),
30125 /* 83253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30126 /* 83256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30127 /* 83259 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30128 /* 83262 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30129 /* 83265 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30130 /* 83268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30131 /* 83272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30132 /* 83276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30133 /* 83280 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(83450),
30134 /* 83285 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30135 /* 83289 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(83369),
30136 /* 83294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30137 /* 83298 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(83333), // Rule ID 5224 //
30138 /* 83303 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30139 /* 83307 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30140 /* 83307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8),
30141 /* 83310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30142 /* 83312 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30143 /* 83314 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30144 /* 83316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30145 /* 83319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30146 /* 83325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30147 /* 83331 */ GIR_RootConstrainSelectedInstOperands,
30148 /* 83332 */ // GIR_Coverage, 5224,
30149 /* 83332 */ GIR_EraseRootFromParent_Done,
30150 /* 83333 */ // Label 2583: @83333
30151 /* 83333 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(83368), // Rule ID 5230 //
30152 /* 83338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30153 /* 83342 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30154 /* 83342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8),
30155 /* 83345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30156 /* 83347 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30157 /* 83349 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30158 /* 83351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30159 /* 83354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30160 /* 83360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30161 /* 83366 */ GIR_RootConstrainSelectedInstOperands,
30162 /* 83367 */ // GIR_Coverage, 5230,
30163 /* 83367 */ GIR_EraseRootFromParent_Done,
30164 /* 83368 */ // Label 2584: @83368
30165 /* 83368 */ GIM_Reject,
30166 /* 83369 */ // Label 2582: @83369
30167 /* 83369 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(83449),
30168 /* 83374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30169 /* 83378 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(83413), // Rule ID 5236 //
30170 /* 83383 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30171 /* 83387 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30172 /* 83387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8),
30173 /* 83390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30174 /* 83392 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30175 /* 83394 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30176 /* 83396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30177 /* 83399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30178 /* 83405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30179 /* 83411 */ GIR_RootConstrainSelectedInstOperands,
30180 /* 83412 */ // GIR_Coverage, 5236,
30181 /* 83412 */ GIR_EraseRootFromParent_Done,
30182 /* 83413 */ // Label 2586: @83413
30183 /* 83413 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(83448), // Rule ID 5242 //
30184 /* 83418 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30185 /* 83422 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30186 /* 83422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8),
30187 /* 83425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30188 /* 83427 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30189 /* 83429 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30190 /* 83431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30191 /* 83434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30192 /* 83440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30193 /* 83446 */ GIR_RootConstrainSelectedInstOperands,
30194 /* 83447 */ // GIR_Coverage, 5242,
30195 /* 83447 */ GIR_EraseRootFromParent_Done,
30196 /* 83448 */ // Label 2587: @83448
30197 /* 83448 */ GIM_Reject,
30198 /* 83449 */ // Label 2585: @83449
30199 /* 83449 */ GIM_Reject,
30200 /* 83450 */ // Label 2581: @83450
30201 /* 83450 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(83620),
30202 /* 83455 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30203 /* 83459 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(83539),
30204 /* 83464 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30205 /* 83468 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(83503), // Rule ID 5248 //
30206 /* 83473 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30207 /* 83477 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30208 /* 83477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8),
30209 /* 83480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30210 /* 83482 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30211 /* 83484 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30212 /* 83486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30213 /* 83489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30214 /* 83495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30215 /* 83501 */ GIR_RootConstrainSelectedInstOperands,
30216 /* 83502 */ // GIR_Coverage, 5248,
30217 /* 83502 */ GIR_EraseRootFromParent_Done,
30218 /* 83503 */ // Label 2590: @83503
30219 /* 83503 */ GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(83538), // Rule ID 5254 //
30220 /* 83508 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30221 /* 83512 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30222 /* 83512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8),
30223 /* 83515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30224 /* 83517 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30225 /* 83519 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30226 /* 83521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30227 /* 83524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30228 /* 83530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30229 /* 83536 */ GIR_RootConstrainSelectedInstOperands,
30230 /* 83537 */ // GIR_Coverage, 5254,
30231 /* 83537 */ GIR_EraseRootFromParent_Done,
30232 /* 83538 */ // Label 2591: @83538
30233 /* 83538 */ GIM_Reject,
30234 /* 83539 */ // Label 2589: @83539
30235 /* 83539 */ GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(83619),
30236 /* 83544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30237 /* 83548 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(83583), // Rule ID 5260 //
30238 /* 83553 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30239 /* 83557 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30240 /* 83557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8),
30241 /* 83560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30242 /* 83562 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30243 /* 83564 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30244 /* 83566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30245 /* 83569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30246 /* 83575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30247 /* 83581 */ GIR_RootConstrainSelectedInstOperands,
30248 /* 83582 */ // GIR_Coverage, 5260,
30249 /* 83582 */ GIR_EraseRootFromParent_Done,
30250 /* 83583 */ // Label 2593: @83583
30251 /* 83583 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(83618), // Rule ID 5266 //
30252 /* 83588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30253 /* 83592 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30254 /* 83592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8),
30255 /* 83595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30256 /* 83597 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30257 /* 83599 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30258 /* 83601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30259 /* 83604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30260 /* 83610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30261 /* 83616 */ GIR_RootConstrainSelectedInstOperands,
30262 /* 83617 */ // GIR_Coverage, 5266,
30263 /* 83617 */ GIR_EraseRootFromParent_Done,
30264 /* 83618 */ // Label 2594: @83618
30265 /* 83618 */ GIM_Reject,
30266 /* 83619 */ // Label 2592: @83619
30267 /* 83619 */ GIM_Reject,
30268 /* 83620 */ // Label 2588: @83620
30269 /* 83620 */ GIM_Reject,
30270 /* 83621 */ // Label 2580: @83621
30271 /* 83621 */ GIM_Reject,
30272 /* 83622 */ // Label 2577: @83622
30273 /* 83622 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(83995),
30274 /* 83627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30275 /* 83630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30276 /* 83633 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30277 /* 83636 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30278 /* 83639 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30279 /* 83642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30280 /* 83646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30281 /* 83650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30282 /* 83654 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(83824),
30283 /* 83659 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30284 /* 83663 */ GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(83743),
30285 /* 83668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30286 /* 83672 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(83707), // Rule ID 5226 //
30287 /* 83677 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30288 /* 83681 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30289 /* 83681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16),
30290 /* 83684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30291 /* 83686 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30292 /* 83688 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30293 /* 83690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30294 /* 83693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30295 /* 83699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30296 /* 83705 */ GIR_RootConstrainSelectedInstOperands,
30297 /* 83706 */ // GIR_Coverage, 5226,
30298 /* 83706 */ GIR_EraseRootFromParent_Done,
30299 /* 83707 */ // Label 2598: @83707
30300 /* 83707 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(83742), // Rule ID 5232 //
30301 /* 83712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30302 /* 83716 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30303 /* 83716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16),
30304 /* 83719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30305 /* 83721 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30306 /* 83723 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30307 /* 83725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30308 /* 83728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30309 /* 83734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30310 /* 83740 */ GIR_RootConstrainSelectedInstOperands,
30311 /* 83741 */ // GIR_Coverage, 5232,
30312 /* 83741 */ GIR_EraseRootFromParent_Done,
30313 /* 83742 */ // Label 2599: @83742
30314 /* 83742 */ GIM_Reject,
30315 /* 83743 */ // Label 2597: @83743
30316 /* 83743 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(83823),
30317 /* 83748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30318 /* 83752 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(83787), // Rule ID 5238 //
30319 /* 83757 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30320 /* 83761 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30321 /* 83761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16),
30322 /* 83764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30323 /* 83766 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30324 /* 83768 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30325 /* 83770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30326 /* 83773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30327 /* 83779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30328 /* 83785 */ GIR_RootConstrainSelectedInstOperands,
30329 /* 83786 */ // GIR_Coverage, 5238,
30330 /* 83786 */ GIR_EraseRootFromParent_Done,
30331 /* 83787 */ // Label 2601: @83787
30332 /* 83787 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(83822), // Rule ID 5244 //
30333 /* 83792 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30334 /* 83796 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30335 /* 83796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16),
30336 /* 83799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30337 /* 83801 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30338 /* 83803 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30339 /* 83805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30340 /* 83808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30341 /* 83814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30342 /* 83820 */ GIR_RootConstrainSelectedInstOperands,
30343 /* 83821 */ // GIR_Coverage, 5244,
30344 /* 83821 */ GIR_EraseRootFromParent_Done,
30345 /* 83822 */ // Label 2602: @83822
30346 /* 83822 */ GIM_Reject,
30347 /* 83823 */ // Label 2600: @83823
30348 /* 83823 */ GIM_Reject,
30349 /* 83824 */ // Label 2596: @83824
30350 /* 83824 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(83994),
30351 /* 83829 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30352 /* 83833 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(83913),
30353 /* 83838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30354 /* 83842 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(83877), // Rule ID 5250 //
30355 /* 83847 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30356 /* 83851 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30357 /* 83851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16),
30358 /* 83854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30359 /* 83856 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30360 /* 83858 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30361 /* 83860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30362 /* 83863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30363 /* 83869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30364 /* 83875 */ GIR_RootConstrainSelectedInstOperands,
30365 /* 83876 */ // GIR_Coverage, 5250,
30366 /* 83876 */ GIR_EraseRootFromParent_Done,
30367 /* 83877 */ // Label 2605: @83877
30368 /* 83877 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(83912), // Rule ID 5256 //
30369 /* 83882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30370 /* 83886 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30371 /* 83886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16),
30372 /* 83889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30373 /* 83891 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30374 /* 83893 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30375 /* 83895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30376 /* 83898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30377 /* 83904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30378 /* 83910 */ GIR_RootConstrainSelectedInstOperands,
30379 /* 83911 */ // GIR_Coverage, 5256,
30380 /* 83911 */ GIR_EraseRootFromParent_Done,
30381 /* 83912 */ // Label 2606: @83912
30382 /* 83912 */ GIM_Reject,
30383 /* 83913 */ // Label 2604: @83913
30384 /* 83913 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(83993),
30385 /* 83918 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30386 /* 83922 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(83957), // Rule ID 5262 //
30387 /* 83927 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30388 /* 83931 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30389 /* 83931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16),
30390 /* 83934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30391 /* 83936 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30392 /* 83938 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30393 /* 83940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30394 /* 83943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30395 /* 83949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30396 /* 83955 */ GIR_RootConstrainSelectedInstOperands,
30397 /* 83956 */ // GIR_Coverage, 5262,
30398 /* 83956 */ GIR_EraseRootFromParent_Done,
30399 /* 83957 */ // Label 2608: @83957
30400 /* 83957 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(83992), // Rule ID 5268 //
30401 /* 83962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30402 /* 83966 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30403 /* 83966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16),
30404 /* 83969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30405 /* 83971 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30406 /* 83973 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30407 /* 83975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30408 /* 83978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30409 /* 83984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30410 /* 83990 */ GIR_RootConstrainSelectedInstOperands,
30411 /* 83991 */ // GIR_Coverage, 5268,
30412 /* 83991 */ GIR_EraseRootFromParent_Done,
30413 /* 83992 */ // Label 2609: @83992
30414 /* 83992 */ GIM_Reject,
30415 /* 83993 */ // Label 2607: @83993
30416 /* 83993 */ GIM_Reject,
30417 /* 83994 */ // Label 2603: @83994
30418 /* 83994 */ GIM_Reject,
30419 /* 83995 */ // Label 2595: @83995
30420 /* 83995 */ GIM_Reject,
30421 /* 83996 */ // Label 2578: @83996
30422 /* 83996 */ GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(84369),
30423 /* 84001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30424 /* 84004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30425 /* 84007 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30426 /* 84010 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30427 /* 84013 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30428 /* 84016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30429 /* 84020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30430 /* 84024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30431 /* 84028 */ GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(84198),
30432 /* 84033 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30433 /* 84037 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(84117),
30434 /* 84042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30435 /* 84046 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(84081), // Rule ID 5228 //
30436 /* 84051 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30437 /* 84055 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30438 /* 84055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32),
30439 /* 84058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30440 /* 84060 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30441 /* 84062 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30442 /* 84064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30443 /* 84067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30444 /* 84073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30445 /* 84079 */ GIR_RootConstrainSelectedInstOperands,
30446 /* 84080 */ // GIR_Coverage, 5228,
30447 /* 84080 */ GIR_EraseRootFromParent_Done,
30448 /* 84081 */ // Label 2613: @84081
30449 /* 84081 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(84116), // Rule ID 5234 //
30450 /* 84086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30451 /* 84090 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30452 /* 84090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32),
30453 /* 84093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30454 /* 84095 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30455 /* 84097 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30456 /* 84099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30457 /* 84102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30458 /* 84108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30459 /* 84114 */ GIR_RootConstrainSelectedInstOperands,
30460 /* 84115 */ // GIR_Coverage, 5234,
30461 /* 84115 */ GIR_EraseRootFromParent_Done,
30462 /* 84116 */ // Label 2614: @84116
30463 /* 84116 */ GIM_Reject,
30464 /* 84117 */ // Label 2612: @84117
30465 /* 84117 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(84197),
30466 /* 84122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30467 /* 84126 */ GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(84161), // Rule ID 5240 //
30468 /* 84131 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30469 /* 84135 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30470 /* 84135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32),
30471 /* 84138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30472 /* 84140 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30473 /* 84142 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30474 /* 84144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30475 /* 84147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30476 /* 84153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30477 /* 84159 */ GIR_RootConstrainSelectedInstOperands,
30478 /* 84160 */ // GIR_Coverage, 5240,
30479 /* 84160 */ GIR_EraseRootFromParent_Done,
30480 /* 84161 */ // Label 2616: @84161
30481 /* 84161 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(84196), // Rule ID 5246 //
30482 /* 84166 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30483 /* 84170 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30484 /* 84170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32),
30485 /* 84173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30486 /* 84175 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30487 /* 84177 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30488 /* 84179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30489 /* 84182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30490 /* 84188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30491 /* 84194 */ GIR_RootConstrainSelectedInstOperands,
30492 /* 84195 */ // GIR_Coverage, 5246,
30493 /* 84195 */ GIR_EraseRootFromParent_Done,
30494 /* 84196 */ // Label 2617: @84196
30495 /* 84196 */ GIM_Reject,
30496 /* 84197 */ // Label 2615: @84197
30497 /* 84197 */ GIM_Reject,
30498 /* 84198 */ // Label 2611: @84198
30499 /* 84198 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(84368),
30500 /* 84203 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30501 /* 84207 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(84287),
30502 /* 84212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30503 /* 84216 */ GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(84251), // Rule ID 5252 //
30504 /* 84221 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30505 /* 84225 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30506 /* 84225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32),
30507 /* 84228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30508 /* 84230 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30509 /* 84232 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30510 /* 84234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30511 /* 84237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30512 /* 84243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30513 /* 84249 */ GIR_RootConstrainSelectedInstOperands,
30514 /* 84250 */ // GIR_Coverage, 5252,
30515 /* 84250 */ GIR_EraseRootFromParent_Done,
30516 /* 84251 */ // Label 2620: @84251
30517 /* 84251 */ GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(84286), // Rule ID 5258 //
30518 /* 84256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30519 /* 84260 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30520 /* 84260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32),
30521 /* 84263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30522 /* 84265 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30523 /* 84267 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30524 /* 84269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30525 /* 84272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30526 /* 84278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30527 /* 84284 */ GIR_RootConstrainSelectedInstOperands,
30528 /* 84285 */ // GIR_Coverage, 5258,
30529 /* 84285 */ GIR_EraseRootFromParent_Done,
30530 /* 84286 */ // Label 2621: @84286
30531 /* 84286 */ GIM_Reject,
30532 /* 84287 */ // Label 2619: @84287
30533 /* 84287 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(84367),
30534 /* 84292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30535 /* 84296 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(84331), // Rule ID 5264 //
30536 /* 84301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30537 /* 84305 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30538 /* 84305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32),
30539 /* 84308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30540 /* 84310 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30541 /* 84312 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30542 /* 84314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30543 /* 84317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30544 /* 84323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30545 /* 84329 */ GIR_RootConstrainSelectedInstOperands,
30546 /* 84330 */ // GIR_Coverage, 5264,
30547 /* 84330 */ GIR_EraseRootFromParent_Done,
30548 /* 84331 */ // Label 2623: @84331
30549 /* 84331 */ GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(84366), // Rule ID 5270 //
30550 /* 84336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30551 /* 84340 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30552 /* 84340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32),
30553 /* 84343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30554 /* 84345 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30555 /* 84347 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30556 /* 84349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30557 /* 84352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30558 /* 84358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30559 /* 84364 */ GIR_RootConstrainSelectedInstOperands,
30560 /* 84365 */ // GIR_Coverage, 5270,
30561 /* 84365 */ GIR_EraseRootFromParent_Done,
30562 /* 84366 */ // Label 2624: @84366
30563 /* 84366 */ GIM_Reject,
30564 /* 84367 */ // Label 2622: @84367
30565 /* 84367 */ GIM_Reject,
30566 /* 84368 */ // Label 2618: @84368
30567 /* 84368 */ GIM_Reject,
30568 /* 84369 */ // Label 2610: @84369
30569 /* 84369 */ GIM_Reject,
30570 /* 84370 */ // Label 2579: @84370
30571 /* 84370 */ GIM_Reject,
30572 /* 84371 */ // Label 2575: @84371
30573 /* 84371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2625*/ GIMT_Encode4(84506), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3079 //
30574 /* 84378 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3),
30575 /* 84383 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30576 /* 84386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30577 /* 84389 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30578 /* 84392 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30579 /* 84395 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30580 /* 84398 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
30581 /* 84401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30582 /* 84405 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4110:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30583 /* 84405 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
30584 /* 84408 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30585 /* 84412 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30586 /* 84417 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
30587 /* 84419 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30588 /* 84422 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30589 /* 84426 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30590 /* 84431 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
30591 /* 84435 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30592 /* 84438 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
30593 /* 84442 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30594 /* 84445 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
30595 /* 84449 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
30596 /* 84452 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
30597 /* 84455 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
30598 /* 84458 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
30599 /* 84463 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30600 /* 84468 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30601 /* 84473 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
30602 /* 84478 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
30603 /* 84483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo),
30604 /* 84486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
30605 /* 84488 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
30606 /* 84490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30607 /* 84493 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
30608 /* 84495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30609 /* 84498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30610 /* 84504 */ GIR_RootConstrainSelectedInstOperands,
30611 /* 84505 */ // GIR_Coverage, 3079,
30612 /* 84505 */ GIR_EraseRootFromParent_Done,
30613 /* 84506 */ // Label 2625: @84506
30614 /* 84506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2626*/ GIMT_Encode4(84626), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3080 //
30615 /* 84513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4),
30616 /* 84518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30617 /* 84521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30618 /* 84524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30619 /* 84527 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30620 /* 84530 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30621 /* 84533 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
30622 /* 84536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30623 /* 84540 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4107:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30624 /* 84540 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30625 /* 84543 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30626 /* 84547 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30627 /* 84552 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
30628 /* 84556 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30629 /* 84559 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
30630 /* 84563 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30631 /* 84566 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
30632 /* 84570 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
30633 /* 84573 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
30634 /* 84577 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
30635 /* 84580 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
30636 /* 84585 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30637 /* 84590 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30638 /* 84595 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
30639 /* 84600 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
30640 /* 84605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo),
30641 /* 84608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
30642 /* 84610 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30643 /* 84613 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
30644 /* 84615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30645 /* 84618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30646 /* 84624 */ GIR_RootConstrainSelectedInstOperands,
30647 /* 84625 */ // GIR_Coverage, 3080,
30648 /* 84625 */ GIR_EraseRootFromParent_Done,
30649 /* 84626 */ // Label 2626: @84626
30650 /* 84626 */ GIM_Reject,
30651 /* 84627 */ // Label 2501: @84627
30652 /* 84627 */ GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(87821),
30653 /* 84632 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
30654 /* 84635 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(86450),
30655 /* 84640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
30656 /* 84645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30657 /* 84648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30658 /* 84651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30659 /* 84654 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30660 /* 84657 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30661 /* 84660 */ GIM_SwitchType, /*MI*/0, /*Op*/6, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2632*/ GIMT_Encode4(86449),
30662 /* 84671 */ /*GILLT_v16s8*//*Label 2629*/ GIMT_Encode4(84691), GIMT_Encode4(0),
30663 /* 84679 */ /*GILLT_v8s16*//*Label 2630*/ GIMT_Encode4(85277), GIMT_Encode4(0),
30664 /* 84687 */ /*GILLT_v4s32*//*Label 2631*/ GIMT_Encode4(85863),
30665 /* 84691 */ // Label 2629: @84691
30666 /* 84691 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(85276),
30667 /* 84696 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
30668 /* 84699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30669 /* 84703 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(84815),
30670 /* 84708 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30671 /* 84712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30672 /* 84716 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2635*/ GIMT_Encode4(84765), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3572 //
30673 /* 84723 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30674 /* 84727 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30675 /* 84731 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30676 /* 84735 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30677 /* 84739 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30678 /* 84739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8),
30679 /* 84742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30680 /* 84744 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30681 /* 84746 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30682 /* 84748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30683 /* 84751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30684 /* 84757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30685 /* 84763 */ GIR_RootConstrainSelectedInstOperands,
30686 /* 84764 */ // GIR_Coverage, 3572,
30687 /* 84764 */ GIR_EraseRootFromParent_Done,
30688 /* 84765 */ // Label 2635: @84765
30689 /* 84765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2636*/ GIMT_Encode4(84814), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3576 //
30690 /* 84772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30691 /* 84776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30692 /* 84780 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30693 /* 84784 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30694 /* 84788 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30695 /* 84788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8),
30696 /* 84791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30697 /* 84793 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30698 /* 84795 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30699 /* 84797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30700 /* 84800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30701 /* 84806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30702 /* 84812 */ GIR_RootConstrainSelectedInstOperands,
30703 /* 84813 */ // GIR_Coverage, 3576,
30704 /* 84813 */ GIR_EraseRootFromParent_Done,
30705 /* 84814 */ // Label 2636: @84814
30706 /* 84814 */ GIM_Reject,
30707 /* 84815 */ // Label 2634: @84815
30708 /* 84815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2637*/ GIMT_Encode4(84872), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3580 //
30709 /* 84822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30710 /* 84826 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30711 /* 84830 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30712 /* 84834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30713 /* 84838 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30714 /* 84842 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30715 /* 84846 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30716 /* 84846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
30717 /* 84849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30718 /* 84851 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30719 /* 84853 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30720 /* 84855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30721 /* 84858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30722 /* 84864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30723 /* 84870 */ GIR_RootConstrainSelectedInstOperands,
30724 /* 84871 */ // GIR_Coverage, 3580,
30725 /* 84871 */ GIR_EraseRootFromParent_Done,
30726 /* 84872 */ // Label 2637: @84872
30727 /* 84872 */ GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(84984),
30728 /* 84877 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30729 /* 84881 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
30730 /* 84885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2639*/ GIMT_Encode4(84934), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3608 //
30731 /* 84892 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30732 /* 84896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30733 /* 84900 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30734 /* 84904 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30735 /* 84908 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30736 /* 84908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8),
30737 /* 84911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30738 /* 84913 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30739 /* 84915 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30740 /* 84917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30741 /* 84920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30742 /* 84926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30743 /* 84932 */ GIR_RootConstrainSelectedInstOperands,
30744 /* 84933 */ // GIR_Coverage, 3608,
30745 /* 84933 */ GIR_EraseRootFromParent_Done,
30746 /* 84934 */ // Label 2639: @84934
30747 /* 84934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2640*/ GIMT_Encode4(84983), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3612 //
30748 /* 84941 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30749 /* 84945 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30750 /* 84949 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30751 /* 84953 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30752 /* 84957 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30753 /* 84957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8),
30754 /* 84960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30755 /* 84962 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30756 /* 84964 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30757 /* 84966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30758 /* 84969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30759 /* 84975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30760 /* 84981 */ GIR_RootConstrainSelectedInstOperands,
30761 /* 84982 */ // GIR_Coverage, 3612,
30762 /* 84982 */ GIR_EraseRootFromParent_Done,
30763 /* 84983 */ // Label 2640: @84983
30764 /* 84983 */ GIM_Reject,
30765 /* 84984 */ // Label 2638: @84984
30766 /* 84984 */ GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(85100),
30767 /* 84989 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30768 /* 84993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30769 /* 84997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2642*/ GIMT_Encode4(85048), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3574 //
30770 /* 85004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30771 /* 85008 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30772 /* 85012 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30773 /* 85016 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30774 /* 85020 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30775 /* 85020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8),
30776 /* 85023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30777 /* 85025 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30778 /* 85027 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30779 /* 85029 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30780 /* 85031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30781 /* 85034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30782 /* 85040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30783 /* 85046 */ GIR_RootConstrainSelectedInstOperands,
30784 /* 85047 */ // GIR_Coverage, 3574,
30785 /* 85047 */ GIR_EraseRootFromParent_Done,
30786 /* 85048 */ // Label 2642: @85048
30787 /* 85048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2643*/ GIMT_Encode4(85099), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3578 //
30788 /* 85055 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30789 /* 85059 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30790 /* 85063 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30791 /* 85067 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30792 /* 85071 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30793 /* 85071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8),
30794 /* 85074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30795 /* 85076 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30796 /* 85078 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30797 /* 85080 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30798 /* 85082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30799 /* 85085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30800 /* 85091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30801 /* 85097 */ GIR_RootConstrainSelectedInstOperands,
30802 /* 85098 */ // GIR_Coverage, 3578,
30803 /* 85098 */ GIR_EraseRootFromParent_Done,
30804 /* 85099 */ // Label 2643: @85099
30805 /* 85099 */ GIM_Reject,
30806 /* 85100 */ // Label 2641: @85100
30807 /* 85100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2644*/ GIMT_Encode4(85159), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3582 //
30808 /* 85107 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30809 /* 85111 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30810 /* 85115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30811 /* 85119 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30812 /* 85123 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30813 /* 85127 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30814 /* 85131 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30815 /* 85131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
30816 /* 85134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30817 /* 85136 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30818 /* 85138 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30819 /* 85140 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30820 /* 85142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30821 /* 85145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30822 /* 85151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30823 /* 85157 */ GIR_RootConstrainSelectedInstOperands,
30824 /* 85158 */ // GIR_Coverage, 3582,
30825 /* 85158 */ GIR_EraseRootFromParent_Done,
30826 /* 85159 */ // Label 2644: @85159
30827 /* 85159 */ GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(85275),
30828 /* 85164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30829 /* 85168 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
30830 /* 85172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2646*/ GIMT_Encode4(85223), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3610 //
30831 /* 85179 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30832 /* 85183 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30833 /* 85187 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30834 /* 85191 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30835 /* 85195 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30836 /* 85195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8),
30837 /* 85198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30838 /* 85200 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30839 /* 85202 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30840 /* 85204 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30841 /* 85206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30842 /* 85209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30843 /* 85215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30844 /* 85221 */ GIR_RootConstrainSelectedInstOperands,
30845 /* 85222 */ // GIR_Coverage, 3610,
30846 /* 85222 */ GIR_EraseRootFromParent_Done,
30847 /* 85223 */ // Label 2646: @85223
30848 /* 85223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2647*/ GIMT_Encode4(85274), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3614 //
30849 /* 85230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30850 /* 85234 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30851 /* 85238 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30852 /* 85242 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30853 /* 85246 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30854 /* 85246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8),
30855 /* 85249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30856 /* 85251 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30857 /* 85253 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30858 /* 85255 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30859 /* 85257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30860 /* 85260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30861 /* 85266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30862 /* 85272 */ GIR_RootConstrainSelectedInstOperands,
30863 /* 85273 */ // GIR_Coverage, 3614,
30864 /* 85273 */ GIR_EraseRootFromParent_Done,
30865 /* 85274 */ // Label 2647: @85274
30866 /* 85274 */ GIM_Reject,
30867 /* 85275 */ // Label 2645: @85275
30868 /* 85275 */ GIM_Reject,
30869 /* 85276 */ // Label 2633: @85276
30870 /* 85276 */ GIM_Reject,
30871 /* 85277 */ // Label 2630: @85277
30872 /* 85277 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(85862),
30873 /* 85282 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
30874 /* 85285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30875 /* 85289 */ GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(85401),
30876 /* 85294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30877 /* 85298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30878 /* 85302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2650*/ GIMT_Encode4(85351), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3584 //
30879 /* 85309 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30880 /* 85313 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30881 /* 85317 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30882 /* 85321 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30883 /* 85325 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30884 /* 85325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16),
30885 /* 85328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30886 /* 85330 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30887 /* 85332 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30888 /* 85334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30889 /* 85337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30890 /* 85343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30891 /* 85349 */ GIR_RootConstrainSelectedInstOperands,
30892 /* 85350 */ // GIR_Coverage, 3584,
30893 /* 85350 */ GIR_EraseRootFromParent_Done,
30894 /* 85351 */ // Label 2650: @85351
30895 /* 85351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2651*/ GIMT_Encode4(85400), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3588 //
30896 /* 85358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30897 /* 85362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30898 /* 85366 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30899 /* 85370 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30900 /* 85374 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30901 /* 85374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16),
30902 /* 85377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30903 /* 85379 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30904 /* 85381 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30905 /* 85383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30906 /* 85386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30907 /* 85392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30908 /* 85398 */ GIR_RootConstrainSelectedInstOperands,
30909 /* 85399 */ // GIR_Coverage, 3588,
30910 /* 85399 */ GIR_EraseRootFromParent_Done,
30911 /* 85400 */ // Label 2651: @85400
30912 /* 85400 */ GIM_Reject,
30913 /* 85401 */ // Label 2649: @85401
30914 /* 85401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2652*/ GIMT_Encode4(85458), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3592 //
30915 /* 85408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30916 /* 85412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30917 /* 85416 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30918 /* 85420 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30919 /* 85424 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30920 /* 85428 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30921 /* 85432 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30922 /* 85432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
30923 /* 85435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30924 /* 85437 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30925 /* 85439 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30926 /* 85441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30927 /* 85444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30928 /* 85450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30929 /* 85456 */ GIR_RootConstrainSelectedInstOperands,
30930 /* 85457 */ // GIR_Coverage, 3592,
30931 /* 85457 */ GIR_EraseRootFromParent_Done,
30932 /* 85458 */ // Label 2652: @85458
30933 /* 85458 */ GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(85570),
30934 /* 85463 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30935 /* 85467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
30936 /* 85471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2654*/ GIMT_Encode4(85520), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3616 //
30937 /* 85478 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30938 /* 85482 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30939 /* 85486 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30940 /* 85490 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30941 /* 85494 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30942 /* 85494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16),
30943 /* 85497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30944 /* 85499 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30945 /* 85501 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30946 /* 85503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30947 /* 85506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30948 /* 85512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30949 /* 85518 */ GIR_RootConstrainSelectedInstOperands,
30950 /* 85519 */ // GIR_Coverage, 3616,
30951 /* 85519 */ GIR_EraseRootFromParent_Done,
30952 /* 85520 */ // Label 2654: @85520
30953 /* 85520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2655*/ GIMT_Encode4(85569), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3620 //
30954 /* 85527 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30955 /* 85531 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30956 /* 85535 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30957 /* 85539 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30958 /* 85543 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30959 /* 85543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16),
30960 /* 85546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30961 /* 85548 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30962 /* 85550 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30963 /* 85552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30964 /* 85555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30965 /* 85561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30966 /* 85567 */ GIR_RootConstrainSelectedInstOperands,
30967 /* 85568 */ // GIR_Coverage, 3620,
30968 /* 85568 */ GIR_EraseRootFromParent_Done,
30969 /* 85569 */ // Label 2655: @85569
30970 /* 85569 */ GIM_Reject,
30971 /* 85570 */ // Label 2653: @85570
30972 /* 85570 */ GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(85686),
30973 /* 85575 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30974 /* 85579 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30975 /* 85583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2657*/ GIMT_Encode4(85634), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3586 //
30976 /* 85590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30977 /* 85594 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30978 /* 85598 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30979 /* 85602 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30980 /* 85606 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30981 /* 85606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16),
30982 /* 85609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30983 /* 85611 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30984 /* 85613 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30985 /* 85615 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30986 /* 85617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30987 /* 85620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30988 /* 85626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30989 /* 85632 */ GIR_RootConstrainSelectedInstOperands,
30990 /* 85633 */ // GIR_Coverage, 3586,
30991 /* 85633 */ GIR_EraseRootFromParent_Done,
30992 /* 85634 */ // Label 2657: @85634
30993 /* 85634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2658*/ GIMT_Encode4(85685), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3590 //
30994 /* 85641 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30995 /* 85645 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30996 /* 85649 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30997 /* 85653 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30998 /* 85657 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30999 /* 85657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16),
31000 /* 85660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31001 /* 85662 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31002 /* 85664 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31003 /* 85666 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31004 /* 85668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31005 /* 85671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31006 /* 85677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31007 /* 85683 */ GIR_RootConstrainSelectedInstOperands,
31008 /* 85684 */ // GIR_Coverage, 3590,
31009 /* 85684 */ GIR_EraseRootFromParent_Done,
31010 /* 85685 */ // Label 2658: @85685
31011 /* 85685 */ GIM_Reject,
31012 /* 85686 */ // Label 2656: @85686
31013 /* 85686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2659*/ GIMT_Encode4(85745), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3594 //
31014 /* 85693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31015 /* 85697 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31016 /* 85701 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31017 /* 85705 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31018 /* 85709 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31019 /* 85713 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31020 /* 85717 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31021 /* 85717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
31022 /* 85720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31023 /* 85722 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31024 /* 85724 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31025 /* 85726 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31026 /* 85728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31027 /* 85731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31028 /* 85737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31029 /* 85743 */ GIR_RootConstrainSelectedInstOperands,
31030 /* 85744 */ // GIR_Coverage, 3594,
31031 /* 85744 */ GIR_EraseRootFromParent_Done,
31032 /* 85745 */ // Label 2659: @85745
31033 /* 85745 */ GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(85861),
31034 /* 85750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31035 /* 85754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
31036 /* 85758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2661*/ GIMT_Encode4(85809), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3618 //
31037 /* 85765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31038 /* 85769 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31039 /* 85773 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31040 /* 85777 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31041 /* 85781 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31042 /* 85781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16),
31043 /* 85784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31044 /* 85786 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31045 /* 85788 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31046 /* 85790 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31047 /* 85792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31048 /* 85795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31049 /* 85801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31050 /* 85807 */ GIR_RootConstrainSelectedInstOperands,
31051 /* 85808 */ // GIR_Coverage, 3618,
31052 /* 85808 */ GIR_EraseRootFromParent_Done,
31053 /* 85809 */ // Label 2661: @85809
31054 /* 85809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2662*/ GIMT_Encode4(85860), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3622 //
31055 /* 85816 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31056 /* 85820 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31057 /* 85824 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31058 /* 85828 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31059 /* 85832 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31060 /* 85832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16),
31061 /* 85835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31062 /* 85837 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31063 /* 85839 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31064 /* 85841 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31065 /* 85843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31066 /* 85846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31067 /* 85852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31068 /* 85858 */ GIR_RootConstrainSelectedInstOperands,
31069 /* 85859 */ // GIR_Coverage, 3622,
31070 /* 85859 */ GIR_EraseRootFromParent_Done,
31071 /* 85860 */ // Label 2662: @85860
31072 /* 85860 */ GIM_Reject,
31073 /* 85861 */ // Label 2660: @85861
31074 /* 85861 */ GIM_Reject,
31075 /* 85862 */ // Label 2648: @85862
31076 /* 85862 */ GIM_Reject,
31077 /* 85863 */ // Label 2631: @85863
31078 /* 85863 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(86448),
31079 /* 85868 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
31080 /* 85871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31081 /* 85875 */ GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(85987),
31082 /* 85880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31083 /* 85884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31084 /* 85888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2665*/ GIMT_Encode4(85937), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3596 //
31085 /* 85895 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31086 /* 85899 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31087 /* 85903 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31088 /* 85907 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31089 /* 85911 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31090 /* 85911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32),
31091 /* 85914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31092 /* 85916 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31093 /* 85918 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31094 /* 85920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31095 /* 85923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31096 /* 85929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31097 /* 85935 */ GIR_RootConstrainSelectedInstOperands,
31098 /* 85936 */ // GIR_Coverage, 3596,
31099 /* 85936 */ GIR_EraseRootFromParent_Done,
31100 /* 85937 */ // Label 2665: @85937
31101 /* 85937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2666*/ GIMT_Encode4(85986), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3600 //
31102 /* 85944 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31103 /* 85948 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31104 /* 85952 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31105 /* 85956 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31106 /* 85960 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31107 /* 85960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32),
31108 /* 85963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31109 /* 85965 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31110 /* 85967 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31111 /* 85969 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31112 /* 85972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31113 /* 85978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31114 /* 85984 */ GIR_RootConstrainSelectedInstOperands,
31115 /* 85985 */ // GIR_Coverage, 3600,
31116 /* 85985 */ GIR_EraseRootFromParent_Done,
31117 /* 85986 */ // Label 2666: @85986
31118 /* 85986 */ GIM_Reject,
31119 /* 85987 */ // Label 2664: @85987
31120 /* 85987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2667*/ GIMT_Encode4(86044), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3604 //
31121 /* 85994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31122 /* 85998 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31123 /* 86002 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31124 /* 86006 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31125 /* 86010 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31126 /* 86014 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31127 /* 86018 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31128 /* 86018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
31129 /* 86021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31130 /* 86023 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31131 /* 86025 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31132 /* 86027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31133 /* 86030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31134 /* 86036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31135 /* 86042 */ GIR_RootConstrainSelectedInstOperands,
31136 /* 86043 */ // GIR_Coverage, 3604,
31137 /* 86043 */ GIR_EraseRootFromParent_Done,
31138 /* 86044 */ // Label 2667: @86044
31139 /* 86044 */ GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(86156),
31140 /* 86049 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31141 /* 86053 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
31142 /* 86057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2669*/ GIMT_Encode4(86106), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3624 //
31143 /* 86064 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31144 /* 86068 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31145 /* 86072 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31146 /* 86076 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31147 /* 86080 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31148 /* 86080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32),
31149 /* 86083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31150 /* 86085 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31151 /* 86087 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31152 /* 86089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31153 /* 86092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31154 /* 86098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31155 /* 86104 */ GIR_RootConstrainSelectedInstOperands,
31156 /* 86105 */ // GIR_Coverage, 3624,
31157 /* 86105 */ GIR_EraseRootFromParent_Done,
31158 /* 86106 */ // Label 2669: @86106
31159 /* 86106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2670*/ GIMT_Encode4(86155), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3628 //
31160 /* 86113 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31161 /* 86117 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31162 /* 86121 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31163 /* 86125 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31164 /* 86129 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31165 /* 86129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32),
31166 /* 86132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31167 /* 86134 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31168 /* 86136 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31169 /* 86138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31170 /* 86141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31171 /* 86147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31172 /* 86153 */ GIR_RootConstrainSelectedInstOperands,
31173 /* 86154 */ // GIR_Coverage, 3628,
31174 /* 86154 */ GIR_EraseRootFromParent_Done,
31175 /* 86155 */ // Label 2670: @86155
31176 /* 86155 */ GIM_Reject,
31177 /* 86156 */ // Label 2668: @86156
31178 /* 86156 */ GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(86272),
31179 /* 86161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31180 /* 86165 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31181 /* 86169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2672*/ GIMT_Encode4(86220), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3598 //
31182 /* 86176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31183 /* 86180 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31184 /* 86184 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31185 /* 86188 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31186 /* 86192 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31187 /* 86192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32),
31188 /* 86195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31189 /* 86197 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31190 /* 86199 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31191 /* 86201 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31192 /* 86203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31193 /* 86206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31194 /* 86212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31195 /* 86218 */ GIR_RootConstrainSelectedInstOperands,
31196 /* 86219 */ // GIR_Coverage, 3598,
31197 /* 86219 */ GIR_EraseRootFromParent_Done,
31198 /* 86220 */ // Label 2672: @86220
31199 /* 86220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2673*/ GIMT_Encode4(86271), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3602 //
31200 /* 86227 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31201 /* 86231 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31202 /* 86235 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31203 /* 86239 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31204 /* 86243 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31205 /* 86243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32),
31206 /* 86246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31207 /* 86248 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31208 /* 86250 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31209 /* 86252 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31210 /* 86254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31211 /* 86257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31212 /* 86263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31213 /* 86269 */ GIR_RootConstrainSelectedInstOperands,
31214 /* 86270 */ // GIR_Coverage, 3602,
31215 /* 86270 */ GIR_EraseRootFromParent_Done,
31216 /* 86271 */ // Label 2673: @86271
31217 /* 86271 */ GIM_Reject,
31218 /* 86272 */ // Label 2671: @86272
31219 /* 86272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2674*/ GIMT_Encode4(86331), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3606 //
31220 /* 86279 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31221 /* 86283 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31222 /* 86287 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31223 /* 86291 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31224 /* 86295 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31225 /* 86299 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31226 /* 86303 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31227 /* 86303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
31228 /* 86306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31229 /* 86308 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31230 /* 86310 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31231 /* 86312 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31232 /* 86314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31233 /* 86317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31234 /* 86323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31235 /* 86329 */ GIR_RootConstrainSelectedInstOperands,
31236 /* 86330 */ // GIR_Coverage, 3606,
31237 /* 86330 */ GIR_EraseRootFromParent_Done,
31238 /* 86331 */ // Label 2674: @86331
31239 /* 86331 */ GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(86447),
31240 /* 86336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31241 /* 86340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
31242 /* 86344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2676*/ GIMT_Encode4(86395), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3626 //
31243 /* 86351 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31244 /* 86355 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31245 /* 86359 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31246 /* 86363 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31247 /* 86367 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31248 /* 86367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32),
31249 /* 86370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31250 /* 86372 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31251 /* 86374 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31252 /* 86376 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31253 /* 86378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31254 /* 86381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31255 /* 86387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31256 /* 86393 */ GIR_RootConstrainSelectedInstOperands,
31257 /* 86394 */ // GIR_Coverage, 3626,
31258 /* 86394 */ GIR_EraseRootFromParent_Done,
31259 /* 86395 */ // Label 2676: @86395
31260 /* 86395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2677*/ GIMT_Encode4(86446), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3630 //
31261 /* 86402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31262 /* 86406 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31263 /* 86410 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31264 /* 86414 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31265 /* 86418 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31266 /* 86418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32),
31267 /* 86421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31268 /* 86423 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31269 /* 86425 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31270 /* 86427 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31271 /* 86429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31272 /* 86432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31273 /* 86438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31274 /* 86444 */ GIR_RootConstrainSelectedInstOperands,
31275 /* 86445 */ // GIR_Coverage, 3630,
31276 /* 86445 */ GIR_EraseRootFromParent_Done,
31277 /* 86446 */ // Label 2677: @86446
31278 /* 86446 */ GIM_Reject,
31279 /* 86447 */ // Label 2675: @86447
31280 /* 86447 */ GIM_Reject,
31281 /* 86448 */ // Label 2663: @86448
31282 /* 86448 */ GIM_Reject,
31283 /* 86449 */ // Label 2632: @86449
31284 /* 86449 */ GIM_Reject,
31285 /* 86450 */ // Label 2628: @86450
31286 /* 86450 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(87695),
31287 /* 86455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
31288 /* 86460 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2682*/ GIMT_Encode4(87694),
31289 /* 86471 */ /*GILLT_v16s8*//*Label 2679*/ GIMT_Encode4(86491), GIMT_Encode4(0),
31290 /* 86479 */ /*GILLT_v8s16*//*Label 2680*/ GIMT_Encode4(86892), GIMT_Encode4(0),
31291 /* 86487 */ /*GILLT_v4s32*//*Label 2681*/ GIMT_Encode4(87293),
31292 /* 86491 */ // Label 2679: @86491
31293 /* 86491 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(86891),
31294 /* 86496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31295 /* 86499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
31296 /* 86502 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
31297 /* 86505 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31298 /* 86508 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31299 /* 86511 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31300 /* 86514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31301 /* 86518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31302 /* 86522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31303 /* 86526 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31304 /* 86530 */ GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(86575), // Rule ID 4846 //
31305 /* 86535 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31306 /* 86539 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31307 /* 86543 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31308 /* 86547 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31309 /* 86547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8),
31310 /* 86550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31311 /* 86552 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31312 /* 86554 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31313 /* 86556 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31314 /* 86558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31315 /* 86561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31316 /* 86567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31317 /* 86573 */ GIR_RootConstrainSelectedInstOperands,
31318 /* 86574 */ // GIR_Coverage, 4846,
31319 /* 86574 */ GIR_EraseRootFromParent_Done,
31320 /* 86575 */ // Label 2684: @86575
31321 /* 86575 */ GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(86620), // Rule ID 4852 //
31322 /* 86580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31323 /* 86584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31324 /* 86588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31325 /* 86592 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31326 /* 86592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8),
31327 /* 86595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31328 /* 86597 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31329 /* 86599 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31330 /* 86601 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31331 /* 86603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31332 /* 86606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31333 /* 86612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31334 /* 86618 */ GIR_RootConstrainSelectedInstOperands,
31335 /* 86619 */ // GIR_Coverage, 4852,
31336 /* 86619 */ GIR_EraseRootFromParent_Done,
31337 /* 86620 */ // Label 2685: @86620
31338 /* 86620 */ GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(86665), // Rule ID 4858 //
31339 /* 86625 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31340 /* 86629 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31341 /* 86633 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31342 /* 86637 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31343 /* 86637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8),
31344 /* 86640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31345 /* 86642 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31346 /* 86644 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31347 /* 86646 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31348 /* 86648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31349 /* 86651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31350 /* 86657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31351 /* 86663 */ GIR_RootConstrainSelectedInstOperands,
31352 /* 86664 */ // GIR_Coverage, 4858,
31353 /* 86664 */ GIR_EraseRootFromParent_Done,
31354 /* 86665 */ // Label 2686: @86665
31355 /* 86665 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(86710), // Rule ID 4864 //
31356 /* 86670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31357 /* 86674 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31358 /* 86678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31359 /* 86682 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31360 /* 86682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8),
31361 /* 86685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31362 /* 86687 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31363 /* 86689 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31364 /* 86691 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31365 /* 86693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31366 /* 86696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31367 /* 86702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31368 /* 86708 */ GIR_RootConstrainSelectedInstOperands,
31369 /* 86709 */ // GIR_Coverage, 4864,
31370 /* 86709 */ GIR_EraseRootFromParent_Done,
31371 /* 86710 */ // Label 2687: @86710
31372 /* 86710 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(86755), // Rule ID 4870 //
31373 /* 86715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31374 /* 86719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31375 /* 86723 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31376 /* 86727 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31377 /* 86727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8),
31378 /* 86730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31379 /* 86732 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31380 /* 86734 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31381 /* 86736 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31382 /* 86738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31383 /* 86741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31384 /* 86747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31385 /* 86753 */ GIR_RootConstrainSelectedInstOperands,
31386 /* 86754 */ // GIR_Coverage, 4870,
31387 /* 86754 */ GIR_EraseRootFromParent_Done,
31388 /* 86755 */ // Label 2688: @86755
31389 /* 86755 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(86800), // Rule ID 4876 //
31390 /* 86760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31391 /* 86764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31392 /* 86768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31393 /* 86772 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31394 /* 86772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8),
31395 /* 86775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31396 /* 86777 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31397 /* 86779 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31398 /* 86781 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31399 /* 86783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31400 /* 86786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31401 /* 86792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31402 /* 86798 */ GIR_RootConstrainSelectedInstOperands,
31403 /* 86799 */ // GIR_Coverage, 4876,
31404 /* 86799 */ GIR_EraseRootFromParent_Done,
31405 /* 86800 */ // Label 2689: @86800
31406 /* 86800 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(86845), // Rule ID 4882 //
31407 /* 86805 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31408 /* 86809 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31409 /* 86813 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31410 /* 86817 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31411 /* 86817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8),
31412 /* 86820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31413 /* 86822 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31414 /* 86824 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31415 /* 86826 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31416 /* 86828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31417 /* 86831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31418 /* 86837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31419 /* 86843 */ GIR_RootConstrainSelectedInstOperands,
31420 /* 86844 */ // GIR_Coverage, 4882,
31421 /* 86844 */ GIR_EraseRootFromParent_Done,
31422 /* 86845 */ // Label 2690: @86845
31423 /* 86845 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(86890), // Rule ID 4888 //
31424 /* 86850 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31425 /* 86854 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31426 /* 86858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31427 /* 86862 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31428 /* 86862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8),
31429 /* 86865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31430 /* 86867 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31431 /* 86869 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31432 /* 86871 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31433 /* 86873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31434 /* 86876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31435 /* 86882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31436 /* 86888 */ GIR_RootConstrainSelectedInstOperands,
31437 /* 86889 */ // GIR_Coverage, 4888,
31438 /* 86889 */ GIR_EraseRootFromParent_Done,
31439 /* 86890 */ // Label 2691: @86890
31440 /* 86890 */ GIM_Reject,
31441 /* 86891 */ // Label 2683: @86891
31442 /* 86891 */ GIM_Reject,
31443 /* 86892 */ // Label 2680: @86892
31444 /* 86892 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(87292),
31445 /* 86897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31446 /* 86900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31447 /* 86903 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
31448 /* 86906 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31449 /* 86909 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31450 /* 86912 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31451 /* 86915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31452 /* 86919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31453 /* 86923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31454 /* 86927 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31455 /* 86931 */ GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(86976), // Rule ID 4848 //
31456 /* 86936 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31457 /* 86940 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31458 /* 86944 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31459 /* 86948 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31460 /* 86948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16),
31461 /* 86951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31462 /* 86953 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31463 /* 86955 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31464 /* 86957 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31465 /* 86959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31466 /* 86962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31467 /* 86968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31468 /* 86974 */ GIR_RootConstrainSelectedInstOperands,
31469 /* 86975 */ // GIR_Coverage, 4848,
31470 /* 86975 */ GIR_EraseRootFromParent_Done,
31471 /* 86976 */ // Label 2693: @86976
31472 /* 86976 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(87021), // Rule ID 4854 //
31473 /* 86981 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31474 /* 86985 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31475 /* 86989 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31476 /* 86993 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31477 /* 86993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16),
31478 /* 86996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31479 /* 86998 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31480 /* 87000 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31481 /* 87002 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31482 /* 87004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31483 /* 87007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31484 /* 87013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31485 /* 87019 */ GIR_RootConstrainSelectedInstOperands,
31486 /* 87020 */ // GIR_Coverage, 4854,
31487 /* 87020 */ GIR_EraseRootFromParent_Done,
31488 /* 87021 */ // Label 2694: @87021
31489 /* 87021 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(87066), // Rule ID 4860 //
31490 /* 87026 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31491 /* 87030 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31492 /* 87034 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31493 /* 87038 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31494 /* 87038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16),
31495 /* 87041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31496 /* 87043 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31497 /* 87045 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31498 /* 87047 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31499 /* 87049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31500 /* 87052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31501 /* 87058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31502 /* 87064 */ GIR_RootConstrainSelectedInstOperands,
31503 /* 87065 */ // GIR_Coverage, 4860,
31504 /* 87065 */ GIR_EraseRootFromParent_Done,
31505 /* 87066 */ // Label 2695: @87066
31506 /* 87066 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(87111), // Rule ID 4866 //
31507 /* 87071 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31508 /* 87075 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31509 /* 87079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31510 /* 87083 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31511 /* 87083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16),
31512 /* 87086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31513 /* 87088 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31514 /* 87090 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31515 /* 87092 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31516 /* 87094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31517 /* 87097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31518 /* 87103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31519 /* 87109 */ GIR_RootConstrainSelectedInstOperands,
31520 /* 87110 */ // GIR_Coverage, 4866,
31521 /* 87110 */ GIR_EraseRootFromParent_Done,
31522 /* 87111 */ // Label 2696: @87111
31523 /* 87111 */ GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(87156), // Rule ID 4872 //
31524 /* 87116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31525 /* 87120 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31526 /* 87124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31527 /* 87128 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31528 /* 87128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16),
31529 /* 87131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31530 /* 87133 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31531 /* 87135 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31532 /* 87137 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31533 /* 87139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31534 /* 87142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31535 /* 87148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31536 /* 87154 */ GIR_RootConstrainSelectedInstOperands,
31537 /* 87155 */ // GIR_Coverage, 4872,
31538 /* 87155 */ GIR_EraseRootFromParent_Done,
31539 /* 87156 */ // Label 2697: @87156
31540 /* 87156 */ GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(87201), // Rule ID 4878 //
31541 /* 87161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31542 /* 87165 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31543 /* 87169 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31544 /* 87173 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31545 /* 87173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16),
31546 /* 87176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31547 /* 87178 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31548 /* 87180 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31549 /* 87182 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31550 /* 87184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31551 /* 87187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31552 /* 87193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31553 /* 87199 */ GIR_RootConstrainSelectedInstOperands,
31554 /* 87200 */ // GIR_Coverage, 4878,
31555 /* 87200 */ GIR_EraseRootFromParent_Done,
31556 /* 87201 */ // Label 2698: @87201
31557 /* 87201 */ GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(87246), // Rule ID 4884 //
31558 /* 87206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31559 /* 87210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31560 /* 87214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31561 /* 87218 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31562 /* 87218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16),
31563 /* 87221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31564 /* 87223 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31565 /* 87225 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31566 /* 87227 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31567 /* 87229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31568 /* 87232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31569 /* 87238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31570 /* 87244 */ GIR_RootConstrainSelectedInstOperands,
31571 /* 87245 */ // GIR_Coverage, 4884,
31572 /* 87245 */ GIR_EraseRootFromParent_Done,
31573 /* 87246 */ // Label 2699: @87246
31574 /* 87246 */ GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(87291), // Rule ID 4890 //
31575 /* 87251 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31576 /* 87255 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31577 /* 87259 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31578 /* 87263 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31579 /* 87263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16),
31580 /* 87266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31581 /* 87268 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31582 /* 87270 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31583 /* 87272 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31584 /* 87274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31585 /* 87277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31586 /* 87283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31587 /* 87289 */ GIR_RootConstrainSelectedInstOperands,
31588 /* 87290 */ // GIR_Coverage, 4890,
31589 /* 87290 */ GIR_EraseRootFromParent_Done,
31590 /* 87291 */ // Label 2700: @87291
31591 /* 87291 */ GIM_Reject,
31592 /* 87292 */ // Label 2692: @87292
31593 /* 87292 */ GIM_Reject,
31594 /* 87293 */ // Label 2681: @87293
31595 /* 87293 */ GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(87693),
31596 /* 87298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31597 /* 87301 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31598 /* 87304 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
31599 /* 87307 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31600 /* 87310 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31601 /* 87313 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31602 /* 87316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31603 /* 87320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31604 /* 87324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31605 /* 87328 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31606 /* 87332 */ GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(87377), // Rule ID 4850 //
31607 /* 87337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31608 /* 87341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31609 /* 87345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31610 /* 87349 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31611 /* 87349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32),
31612 /* 87352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31613 /* 87354 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31614 /* 87356 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31615 /* 87358 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31616 /* 87360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31617 /* 87363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31618 /* 87369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31619 /* 87375 */ GIR_RootConstrainSelectedInstOperands,
31620 /* 87376 */ // GIR_Coverage, 4850,
31621 /* 87376 */ GIR_EraseRootFromParent_Done,
31622 /* 87377 */ // Label 2702: @87377
31623 /* 87377 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(87422), // Rule ID 4856 //
31624 /* 87382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31625 /* 87386 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31626 /* 87390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31627 /* 87394 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31628 /* 87394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32),
31629 /* 87397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31630 /* 87399 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31631 /* 87401 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31632 /* 87403 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31633 /* 87405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31634 /* 87408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31635 /* 87414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31636 /* 87420 */ GIR_RootConstrainSelectedInstOperands,
31637 /* 87421 */ // GIR_Coverage, 4856,
31638 /* 87421 */ GIR_EraseRootFromParent_Done,
31639 /* 87422 */ // Label 2703: @87422
31640 /* 87422 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(87467), // Rule ID 4862 //
31641 /* 87427 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31642 /* 87431 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31643 /* 87435 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31644 /* 87439 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31645 /* 87439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32),
31646 /* 87442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31647 /* 87444 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31648 /* 87446 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31649 /* 87448 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31650 /* 87450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31651 /* 87453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31652 /* 87459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31653 /* 87465 */ GIR_RootConstrainSelectedInstOperands,
31654 /* 87466 */ // GIR_Coverage, 4862,
31655 /* 87466 */ GIR_EraseRootFromParent_Done,
31656 /* 87467 */ // Label 2704: @87467
31657 /* 87467 */ GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(87512), // Rule ID 4868 //
31658 /* 87472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31659 /* 87476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31660 /* 87480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31661 /* 87484 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31662 /* 87484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32),
31663 /* 87487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31664 /* 87489 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31665 /* 87491 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31666 /* 87493 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31667 /* 87495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31668 /* 87498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31669 /* 87504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31670 /* 87510 */ GIR_RootConstrainSelectedInstOperands,
31671 /* 87511 */ // GIR_Coverage, 4868,
31672 /* 87511 */ GIR_EraseRootFromParent_Done,
31673 /* 87512 */ // Label 2705: @87512
31674 /* 87512 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(87557), // Rule ID 4874 //
31675 /* 87517 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31676 /* 87521 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31677 /* 87525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31678 /* 87529 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31679 /* 87529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32),
31680 /* 87532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31681 /* 87534 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31682 /* 87536 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31683 /* 87538 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31684 /* 87540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31685 /* 87543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31686 /* 87549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31687 /* 87555 */ GIR_RootConstrainSelectedInstOperands,
31688 /* 87556 */ // GIR_Coverage, 4874,
31689 /* 87556 */ GIR_EraseRootFromParent_Done,
31690 /* 87557 */ // Label 2706: @87557
31691 /* 87557 */ GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(87602), // Rule ID 4880 //
31692 /* 87562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31693 /* 87566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31694 /* 87570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31695 /* 87574 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31696 /* 87574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32),
31697 /* 87577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31698 /* 87579 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31699 /* 87581 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31700 /* 87583 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31701 /* 87585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31702 /* 87588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31703 /* 87594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31704 /* 87600 */ GIR_RootConstrainSelectedInstOperands,
31705 /* 87601 */ // GIR_Coverage, 4880,
31706 /* 87601 */ GIR_EraseRootFromParent_Done,
31707 /* 87602 */ // Label 2707: @87602
31708 /* 87602 */ GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(87647), // Rule ID 4886 //
31709 /* 87607 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31710 /* 87611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31711 /* 87615 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31712 /* 87619 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31713 /* 87619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32),
31714 /* 87622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31715 /* 87624 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31716 /* 87626 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31717 /* 87628 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31718 /* 87630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31719 /* 87633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31720 /* 87639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31721 /* 87645 */ GIR_RootConstrainSelectedInstOperands,
31722 /* 87646 */ // GIR_Coverage, 4886,
31723 /* 87646 */ GIR_EraseRootFromParent_Done,
31724 /* 87647 */ // Label 2708: @87647
31725 /* 87647 */ GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(87692), // Rule ID 4892 //
31726 /* 87652 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31727 /* 87656 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31728 /* 87660 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31729 /* 87664 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31730 /* 87664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32),
31731 /* 87667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31732 /* 87669 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31733 /* 87671 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31734 /* 87673 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31735 /* 87675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31736 /* 87678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31737 /* 87684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31738 /* 87690 */ GIR_RootConstrainSelectedInstOperands,
31739 /* 87691 */ // GIR_Coverage, 4892,
31740 /* 87691 */ GIR_EraseRootFromParent_Done,
31741 /* 87692 */ // Label 2709: @87692
31742 /* 87692 */ GIM_Reject,
31743 /* 87693 */ // Label 2701: @87693
31744 /* 87693 */ GIM_Reject,
31745 /* 87694 */ // Label 2682: @87694
31746 /* 87694 */ GIM_Reject,
31747 /* 87695 */ // Label 2678: @87695
31748 /* 87695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2710*/ GIMT_Encode4(87820), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3081 //
31749 /* 87702 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4),
31750 /* 87707 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
31751 /* 87710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
31752 /* 87713 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
31753 /* 87716 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
31754 /* 87719 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
31755 /* 87722 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
31756 /* 87725 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8,
31757 /* 87728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
31758 /* 87732 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4111:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31759 /* 87732 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31760 /* 87735 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
31761 /* 87739 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31762 /* 87744 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
31763 /* 87748 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
31764 /* 87751 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
31765 /* 87755 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
31766 /* 87758 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
31767 /* 87762 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
31768 /* 87765 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
31769 /* 87769 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
31770 /* 87772 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
31771 /* 87777 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
31772 /* 87782 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
31773 /* 87787 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
31774 /* 87792 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
31775 /* 87797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo),
31776 /* 87800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31777 /* 87802 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
31778 /* 87804 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31779 /* 87807 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm
31780 /* 87809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
31781 /* 87812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31782 /* 87818 */ GIR_RootConstrainSelectedInstOperands,
31783 /* 87819 */ // GIR_Coverage, 3081,
31784 /* 87819 */ GIR_EraseRootFromParent_Done,
31785 /* 87820 */ // Label 2710: @87820
31786 /* 87820 */ GIM_Reject,
31787 /* 87821 */ // Label 2627: @87821
31788 /* 87821 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(90440),
31789 /* 87826 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
31790 /* 87829 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn),
31791 /* 87834 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2714*/ GIMT_Encode4(90439),
31792 /* 87845 */ /*GILLT_v16s8*//*Label 2712*/ GIMT_Encode4(87857), GIMT_Encode4(0),
31793 /* 87853 */ /*GILLT_v8s16*//*Label 2713*/ GIMT_Encode4(89148),
31794 /* 87857 */ // Label 2712: @87857
31795 /* 87857 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(89147),
31796 /* 87862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31797 /* 87865 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31798 /* 87868 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31799 /* 87871 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31800 /* 87874 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31801 /* 87877 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31802 /* 87880 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
31803 /* 87883 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
31804 /* 87886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31805 /* 87890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31806 /* 87894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31807 /* 87898 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(88400),
31808 /* 87903 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31809 /* 87907 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(88153),
31810 /* 87912 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31811 /* 87916 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(88034),
31812 /* 87921 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31813 /* 87925 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
31814 /* 87929 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(87981), // Rule ID 4161 //
31815 /* 87934 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31816 /* 87938 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31817 /* 87942 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31818 /* 87946 */ // MIs[1] Operand 1
31819 /* 87946 */ // No operand predicates
31820 /* 87946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31821 /* 87950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31822 /* 87952 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31823 /* 87952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
31824 /* 87955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31825 /* 87957 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31826 /* 87959 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31827 /* 87961 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31828 /* 87964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31829 /* 87967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31830 /* 87973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31831 /* 87979 */ GIR_RootConstrainSelectedInstOperands,
31832 /* 87980 */ // GIR_Coverage, 4161,
31833 /* 87980 */ GIR_EraseRootFromParent_Done,
31834 /* 87981 */ // Label 2719: @87981
31835 /* 87981 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(88033), // Rule ID 4163 //
31836 /* 87986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31837 /* 87990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31838 /* 87994 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31839 /* 87998 */ // MIs[1] Operand 1
31840 /* 87998 */ // No operand predicates
31841 /* 87998 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31842 /* 88002 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31843 /* 88004 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31844 /* 88004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
31845 /* 88007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31846 /* 88009 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31847 /* 88011 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31848 /* 88013 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31849 /* 88016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31850 /* 88019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31851 /* 88025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31852 /* 88031 */ GIR_RootConstrainSelectedInstOperands,
31853 /* 88032 */ // GIR_Coverage, 4163,
31854 /* 88032 */ GIR_EraseRootFromParent_Done,
31855 /* 88033 */ // Label 2720: @88033
31856 /* 88033 */ GIM_Reject,
31857 /* 88034 */ // Label 2718: @88034
31858 /* 88034 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(88152),
31859 /* 88039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31860 /* 88043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
31861 /* 88047 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(88099), // Rule ID 4169 //
31862 /* 88052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31863 /* 88056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31864 /* 88060 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31865 /* 88064 */ // MIs[1] Operand 1
31866 /* 88064 */ // No operand predicates
31867 /* 88064 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31868 /* 88068 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31869 /* 88070 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31870 /* 88070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
31871 /* 88073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31872 /* 88075 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31873 /* 88077 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31874 /* 88079 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31875 /* 88082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31876 /* 88085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31877 /* 88091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31878 /* 88097 */ GIR_RootConstrainSelectedInstOperands,
31879 /* 88098 */ // GIR_Coverage, 4169,
31880 /* 88098 */ GIR_EraseRootFromParent_Done,
31881 /* 88099 */ // Label 2722: @88099
31882 /* 88099 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(88151), // Rule ID 4171 //
31883 /* 88104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31884 /* 88108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31885 /* 88112 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31886 /* 88116 */ // MIs[1] Operand 1
31887 /* 88116 */ // No operand predicates
31888 /* 88116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31889 /* 88120 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31890 /* 88122 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31891 /* 88122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
31892 /* 88125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31893 /* 88127 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31894 /* 88129 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31895 /* 88131 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31896 /* 88134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31897 /* 88137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31898 /* 88143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31899 /* 88149 */ GIR_RootConstrainSelectedInstOperands,
31900 /* 88150 */ // GIR_Coverage, 4171,
31901 /* 88150 */ GIR_EraseRootFromParent_Done,
31902 /* 88151 */ // Label 2723: @88151
31903 /* 88151 */ GIM_Reject,
31904 /* 88152 */ // Label 2721: @88152
31905 /* 88152 */ GIM_Reject,
31906 /* 88153 */ // Label 2717: @88153
31907 /* 88153 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(88399),
31908 /* 88158 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31909 /* 88162 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(88280),
31910 /* 88167 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31911 /* 88171 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
31912 /* 88175 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(88227), // Rule ID 4177 //
31913 /* 88180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31914 /* 88184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31915 /* 88188 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31916 /* 88192 */ // MIs[1] Operand 1
31917 /* 88192 */ // No operand predicates
31918 /* 88192 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31919 /* 88196 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31920 /* 88198 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31921 /* 88198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
31922 /* 88201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31923 /* 88203 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31924 /* 88205 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31925 /* 88207 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31926 /* 88210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31927 /* 88213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31928 /* 88219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31929 /* 88225 */ GIR_RootConstrainSelectedInstOperands,
31930 /* 88226 */ // GIR_Coverage, 4177,
31931 /* 88226 */ GIR_EraseRootFromParent_Done,
31932 /* 88227 */ // Label 2726: @88227
31933 /* 88227 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(88279), // Rule ID 4179 //
31934 /* 88232 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31935 /* 88236 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31936 /* 88240 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31937 /* 88244 */ // MIs[1] Operand 1
31938 /* 88244 */ // No operand predicates
31939 /* 88244 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31940 /* 88248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31941 /* 88250 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31942 /* 88250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
31943 /* 88253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31944 /* 88255 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31945 /* 88257 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31946 /* 88259 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31947 /* 88262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31948 /* 88265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31949 /* 88271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31950 /* 88277 */ GIR_RootConstrainSelectedInstOperands,
31951 /* 88278 */ // GIR_Coverage, 4179,
31952 /* 88278 */ GIR_EraseRootFromParent_Done,
31953 /* 88279 */ // Label 2727: @88279
31954 /* 88279 */ GIM_Reject,
31955 /* 88280 */ // Label 2725: @88280
31956 /* 88280 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(88398),
31957 /* 88285 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31958 /* 88289 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
31959 /* 88293 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(88345), // Rule ID 4185 //
31960 /* 88298 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31961 /* 88302 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31962 /* 88306 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31963 /* 88310 */ // MIs[1] Operand 1
31964 /* 88310 */ // No operand predicates
31965 /* 88310 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31966 /* 88314 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31967 /* 88316 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31968 /* 88316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
31969 /* 88319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31970 /* 88321 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31971 /* 88323 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31972 /* 88325 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31973 /* 88328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31974 /* 88331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31975 /* 88337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31976 /* 88343 */ GIR_RootConstrainSelectedInstOperands,
31977 /* 88344 */ // GIR_Coverage, 4185,
31978 /* 88344 */ GIR_EraseRootFromParent_Done,
31979 /* 88345 */ // Label 2729: @88345
31980 /* 88345 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(88397), // Rule ID 4187 //
31981 /* 88350 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31982 /* 88354 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31983 /* 88358 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31984 /* 88362 */ // MIs[1] Operand 1
31985 /* 88362 */ // No operand predicates
31986 /* 88362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31987 /* 88366 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31988 /* 88368 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31989 /* 88368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
31990 /* 88371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31991 /* 88373 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31992 /* 88375 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31993 /* 88377 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31994 /* 88380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31995 /* 88383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31996 /* 88389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31997 /* 88395 */ GIR_RootConstrainSelectedInstOperands,
31998 /* 88396 */ // GIR_Coverage, 4187,
31999 /* 88396 */ GIR_EraseRootFromParent_Done,
32000 /* 88397 */ // Label 2730: @88397
32001 /* 88397 */ GIM_Reject,
32002 /* 88398 */ // Label 2728: @88398
32003 /* 88398 */ GIM_Reject,
32004 /* 88399 */ // Label 2724: @88399
32005 /* 88399 */ GIM_Reject,
32006 /* 88400 */ // Label 2716: @88400
32007 /* 88400 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(89146),
32008 /* 88405 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32009 /* 88409 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(88655),
32010 /* 88414 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32011 /* 88418 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(88536),
32012 /* 88423 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32013 /* 88427 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32014 /* 88431 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(88483), // Rule ID 4193 //
32015 /* 88436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32016 /* 88440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32017 /* 88444 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32018 /* 88448 */ // MIs[1] Operand 1
32019 /* 88448 */ // No operand predicates
32020 /* 88448 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32021 /* 88452 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32022 /* 88454 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32023 /* 88454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16),
32024 /* 88457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32025 /* 88459 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32026 /* 88461 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32027 /* 88463 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32028 /* 88466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32029 /* 88469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32030 /* 88475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32031 /* 88481 */ GIR_RootConstrainSelectedInstOperands,
32032 /* 88482 */ // GIR_Coverage, 4193,
32033 /* 88482 */ GIR_EraseRootFromParent_Done,
32034 /* 88483 */ // Label 2734: @88483
32035 /* 88483 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(88535), // Rule ID 4195 //
32036 /* 88488 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32037 /* 88492 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32038 /* 88496 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32039 /* 88500 */ // MIs[1] Operand 1
32040 /* 88500 */ // No operand predicates
32041 /* 88500 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32042 /* 88504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32043 /* 88506 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32044 /* 88506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16),
32045 /* 88509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32046 /* 88511 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32047 /* 88513 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32048 /* 88515 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32049 /* 88518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32050 /* 88521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32051 /* 88527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32052 /* 88533 */ GIR_RootConstrainSelectedInstOperands,
32053 /* 88534 */ // GIR_Coverage, 4195,
32054 /* 88534 */ GIR_EraseRootFromParent_Done,
32055 /* 88535 */ // Label 2735: @88535
32056 /* 88535 */ GIM_Reject,
32057 /* 88536 */ // Label 2733: @88536
32058 /* 88536 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(88654),
32059 /* 88541 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32060 /* 88545 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32061 /* 88549 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(88601), // Rule ID 4201 //
32062 /* 88554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32063 /* 88558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32064 /* 88562 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32065 /* 88566 */ // MIs[1] Operand 1
32066 /* 88566 */ // No operand predicates
32067 /* 88566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32068 /* 88570 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32069 /* 88572 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32070 /* 88572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16),
32071 /* 88575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32072 /* 88577 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32073 /* 88579 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32074 /* 88581 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32075 /* 88584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32076 /* 88587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32077 /* 88593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32078 /* 88599 */ GIR_RootConstrainSelectedInstOperands,
32079 /* 88600 */ // GIR_Coverage, 4201,
32080 /* 88600 */ GIR_EraseRootFromParent_Done,
32081 /* 88601 */ // Label 2737: @88601
32082 /* 88601 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(88653), // Rule ID 4203 //
32083 /* 88606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32084 /* 88610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32085 /* 88614 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32086 /* 88618 */ // MIs[1] Operand 1
32087 /* 88618 */ // No operand predicates
32088 /* 88618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32089 /* 88622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32090 /* 88624 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32091 /* 88624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16),
32092 /* 88627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32093 /* 88629 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32094 /* 88631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32095 /* 88633 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32096 /* 88636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32097 /* 88639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32098 /* 88645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32099 /* 88651 */ GIR_RootConstrainSelectedInstOperands,
32100 /* 88652 */ // GIR_Coverage, 4203,
32101 /* 88652 */ GIR_EraseRootFromParent_Done,
32102 /* 88653 */ // Label 2738: @88653
32103 /* 88653 */ GIM_Reject,
32104 /* 88654 */ // Label 2736: @88654
32105 /* 88654 */ GIM_Reject,
32106 /* 88655 */ // Label 2732: @88655
32107 /* 88655 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(88901),
32108 /* 88660 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32109 /* 88664 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(88782),
32110 /* 88669 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32111 /* 88673 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32112 /* 88677 */ GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(88729), // Rule ID 4209 //
32113 /* 88682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32114 /* 88686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32115 /* 88690 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32116 /* 88694 */ // MIs[1] Operand 1
32117 /* 88694 */ // No operand predicates
32118 /* 88694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32119 /* 88698 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32120 /* 88700 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32121 /* 88700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16),
32122 /* 88703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32123 /* 88705 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32124 /* 88707 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32125 /* 88709 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32126 /* 88712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32127 /* 88715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32128 /* 88721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32129 /* 88727 */ GIR_RootConstrainSelectedInstOperands,
32130 /* 88728 */ // GIR_Coverage, 4209,
32131 /* 88728 */ GIR_EraseRootFromParent_Done,
32132 /* 88729 */ // Label 2741: @88729
32133 /* 88729 */ GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(88781), // Rule ID 4211 //
32134 /* 88734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32135 /* 88738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32136 /* 88742 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32137 /* 88746 */ // MIs[1] Operand 1
32138 /* 88746 */ // No operand predicates
32139 /* 88746 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32140 /* 88750 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32141 /* 88752 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32142 /* 88752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16),
32143 /* 88755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32144 /* 88757 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32145 /* 88759 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32146 /* 88761 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32147 /* 88764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32148 /* 88767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32149 /* 88773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32150 /* 88779 */ GIR_RootConstrainSelectedInstOperands,
32151 /* 88780 */ // GIR_Coverage, 4211,
32152 /* 88780 */ GIR_EraseRootFromParent_Done,
32153 /* 88781 */ // Label 2742: @88781
32154 /* 88781 */ GIM_Reject,
32155 /* 88782 */ // Label 2740: @88782
32156 /* 88782 */ GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(88900),
32157 /* 88787 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32158 /* 88791 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32159 /* 88795 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(88847), // Rule ID 4217 //
32160 /* 88800 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32161 /* 88804 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32162 /* 88808 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32163 /* 88812 */ // MIs[1] Operand 1
32164 /* 88812 */ // No operand predicates
32165 /* 88812 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32166 /* 88816 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32167 /* 88818 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32168 /* 88818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16),
32169 /* 88821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32170 /* 88823 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32171 /* 88825 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32172 /* 88827 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32173 /* 88830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32174 /* 88833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32175 /* 88839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32176 /* 88845 */ GIR_RootConstrainSelectedInstOperands,
32177 /* 88846 */ // GIR_Coverage, 4217,
32178 /* 88846 */ GIR_EraseRootFromParent_Done,
32179 /* 88847 */ // Label 2744: @88847
32180 /* 88847 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(88899), // Rule ID 4219 //
32181 /* 88852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32182 /* 88856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32183 /* 88860 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32184 /* 88864 */ // MIs[1] Operand 1
32185 /* 88864 */ // No operand predicates
32186 /* 88864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32187 /* 88868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32188 /* 88870 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32189 /* 88870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16),
32190 /* 88873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32191 /* 88875 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32192 /* 88877 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32193 /* 88879 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32194 /* 88882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32195 /* 88885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32196 /* 88891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32197 /* 88897 */ GIR_RootConstrainSelectedInstOperands,
32198 /* 88898 */ // GIR_Coverage, 4219,
32199 /* 88898 */ GIR_EraseRootFromParent_Done,
32200 /* 88899 */ // Label 2745: @88899
32201 /* 88899 */ GIM_Reject,
32202 /* 88900 */ // Label 2743: @88900
32203 /* 88900 */ GIM_Reject,
32204 /* 88901 */ // Label 2739: @88901
32205 /* 88901 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(89023),
32206 /* 88906 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32207 /* 88910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32208 /* 88914 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32209 /* 88918 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(88970), // Rule ID 4225 //
32210 /* 88923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32211 /* 88927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32212 /* 88931 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32213 /* 88935 */ // MIs[1] Operand 1
32214 /* 88935 */ // No operand predicates
32215 /* 88935 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32216 /* 88939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32217 /* 88941 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32218 /* 88941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh),
32219 /* 88944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32220 /* 88946 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32221 /* 88948 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32222 /* 88950 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32223 /* 88953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32224 /* 88956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32225 /* 88962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32226 /* 88968 */ GIR_RootConstrainSelectedInstOperands,
32227 /* 88969 */ // GIR_Coverage, 4225,
32228 /* 88969 */ GIR_EraseRootFromParent_Done,
32229 /* 88970 */ // Label 2747: @88970
32230 /* 88970 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(89022), // Rule ID 4227 //
32231 /* 88975 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32232 /* 88979 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32233 /* 88983 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32234 /* 88987 */ // MIs[1] Operand 1
32235 /* 88987 */ // No operand predicates
32236 /* 88987 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32237 /* 88991 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32238 /* 88993 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32239 /* 88993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th),
32240 /* 88996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32241 /* 88998 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32242 /* 89000 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32243 /* 89002 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32244 /* 89005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32245 /* 89008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32246 /* 89014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32247 /* 89020 */ GIR_RootConstrainSelectedInstOperands,
32248 /* 89021 */ // GIR_Coverage, 4227,
32249 /* 89021 */ GIR_EraseRootFromParent_Done,
32250 /* 89022 */ // Label 2748: @89022
32251 /* 89022 */ GIM_Reject,
32252 /* 89023 */ // Label 2746: @89023
32253 /* 89023 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(89145),
32254 /* 89028 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32255 /* 89032 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32256 /* 89036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32257 /* 89040 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(89092), // Rule ID 4233 //
32258 /* 89045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32259 /* 89049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32260 /* 89053 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32261 /* 89057 */ // MIs[1] Operand 1
32262 /* 89057 */ // No operand predicates
32263 /* 89057 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32264 /* 89061 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32265 /* 89063 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32266 /* 89063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh),
32267 /* 89066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32268 /* 89068 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32269 /* 89070 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32270 /* 89072 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32271 /* 89075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32272 /* 89078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32273 /* 89084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32274 /* 89090 */ GIR_RootConstrainSelectedInstOperands,
32275 /* 89091 */ // GIR_Coverage, 4233,
32276 /* 89091 */ GIR_EraseRootFromParent_Done,
32277 /* 89092 */ // Label 2750: @89092
32278 /* 89092 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(89144), // Rule ID 4235 //
32279 /* 89097 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32280 /* 89101 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32281 /* 89105 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32282 /* 89109 */ // MIs[1] Operand 1
32283 /* 89109 */ // No operand predicates
32284 /* 89109 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32285 /* 89113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32286 /* 89115 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32287 /* 89115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th),
32288 /* 89118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32289 /* 89120 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32290 /* 89122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32291 /* 89124 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32292 /* 89127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32293 /* 89130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32294 /* 89136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32295 /* 89142 */ GIR_RootConstrainSelectedInstOperands,
32296 /* 89143 */ // GIR_Coverage, 4235,
32297 /* 89143 */ GIR_EraseRootFromParent_Done,
32298 /* 89144 */ // Label 2751: @89144
32299 /* 89144 */ GIM_Reject,
32300 /* 89145 */ // Label 2749: @89145
32301 /* 89145 */ GIM_Reject,
32302 /* 89146 */ // Label 2731: @89146
32303 /* 89146 */ GIM_Reject,
32304 /* 89147 */ // Label 2715: @89147
32305 /* 89147 */ GIM_Reject,
32306 /* 89148 */ // Label 2713: @89148
32307 /* 89148 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(90438),
32308 /* 89153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32309 /* 89156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32310 /* 89159 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32311 /* 89162 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32312 /* 89165 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32313 /* 89168 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
32314 /* 89171 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
32315 /* 89174 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
32316 /* 89177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32317 /* 89181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32318 /* 89185 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32319 /* 89189 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(89691),
32320 /* 89194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32321 /* 89198 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(89444),
32322 /* 89203 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32323 /* 89207 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(89325),
32324 /* 89212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32325 /* 89216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32326 /* 89220 */ GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(89272), // Rule ID 4165 //
32327 /* 89225 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32328 /* 89229 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32329 /* 89233 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32330 /* 89237 */ // MIs[1] Operand 1
32331 /* 89237 */ // No operand predicates
32332 /* 89237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32333 /* 89241 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32334 /* 89243 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32335 /* 89243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
32336 /* 89246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32337 /* 89248 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32338 /* 89250 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32339 /* 89252 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32340 /* 89255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32341 /* 89258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32342 /* 89264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32343 /* 89270 */ GIR_RootConstrainSelectedInstOperands,
32344 /* 89271 */ // GIR_Coverage, 4165,
32345 /* 89271 */ GIR_EraseRootFromParent_Done,
32346 /* 89272 */ // Label 2756: @89272
32347 /* 89272 */ GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(89324), // Rule ID 4167 //
32348 /* 89277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32349 /* 89281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32350 /* 89285 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32351 /* 89289 */ // MIs[1] Operand 1
32352 /* 89289 */ // No operand predicates
32353 /* 89289 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32354 /* 89293 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32355 /* 89295 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32356 /* 89295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
32357 /* 89298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32358 /* 89300 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32359 /* 89302 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32360 /* 89304 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32361 /* 89307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32362 /* 89310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32363 /* 89316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32364 /* 89322 */ GIR_RootConstrainSelectedInstOperands,
32365 /* 89323 */ // GIR_Coverage, 4167,
32366 /* 89323 */ GIR_EraseRootFromParent_Done,
32367 /* 89324 */ // Label 2757: @89324
32368 /* 89324 */ GIM_Reject,
32369 /* 89325 */ // Label 2755: @89325
32370 /* 89325 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(89443),
32371 /* 89330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32372 /* 89334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32373 /* 89338 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(89390), // Rule ID 4173 //
32374 /* 89343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32375 /* 89347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32376 /* 89351 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32377 /* 89355 */ // MIs[1] Operand 1
32378 /* 89355 */ // No operand predicates
32379 /* 89355 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32380 /* 89359 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32381 /* 89361 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32382 /* 89361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
32383 /* 89364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32384 /* 89366 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32385 /* 89368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32386 /* 89370 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32387 /* 89373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32388 /* 89376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32389 /* 89382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32390 /* 89388 */ GIR_RootConstrainSelectedInstOperands,
32391 /* 89389 */ // GIR_Coverage, 4173,
32392 /* 89389 */ GIR_EraseRootFromParent_Done,
32393 /* 89390 */ // Label 2759: @89390
32394 /* 89390 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(89442), // Rule ID 4175 //
32395 /* 89395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32396 /* 89399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32397 /* 89403 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32398 /* 89407 */ // MIs[1] Operand 1
32399 /* 89407 */ // No operand predicates
32400 /* 89407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32401 /* 89411 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32402 /* 89413 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32403 /* 89413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
32404 /* 89416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32405 /* 89418 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32406 /* 89420 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32407 /* 89422 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32408 /* 89425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32409 /* 89428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32410 /* 89434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32411 /* 89440 */ GIR_RootConstrainSelectedInstOperands,
32412 /* 89441 */ // GIR_Coverage, 4175,
32413 /* 89441 */ GIR_EraseRootFromParent_Done,
32414 /* 89442 */ // Label 2760: @89442
32415 /* 89442 */ GIM_Reject,
32416 /* 89443 */ // Label 2758: @89443
32417 /* 89443 */ GIM_Reject,
32418 /* 89444 */ // Label 2754: @89444
32419 /* 89444 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(89690),
32420 /* 89449 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32421 /* 89453 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(89571),
32422 /* 89458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32423 /* 89462 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32424 /* 89466 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(89518), // Rule ID 4181 //
32425 /* 89471 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32426 /* 89475 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32427 /* 89479 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32428 /* 89483 */ // MIs[1] Operand 1
32429 /* 89483 */ // No operand predicates
32430 /* 89483 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32431 /* 89487 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32432 /* 89489 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32433 /* 89489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
32434 /* 89492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32435 /* 89494 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32436 /* 89496 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32437 /* 89498 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32438 /* 89501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32439 /* 89504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32440 /* 89510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32441 /* 89516 */ GIR_RootConstrainSelectedInstOperands,
32442 /* 89517 */ // GIR_Coverage, 4181,
32443 /* 89517 */ GIR_EraseRootFromParent_Done,
32444 /* 89518 */ // Label 2763: @89518
32445 /* 89518 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(89570), // Rule ID 4183 //
32446 /* 89523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32447 /* 89527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32448 /* 89531 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32449 /* 89535 */ // MIs[1] Operand 1
32450 /* 89535 */ // No operand predicates
32451 /* 89535 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32452 /* 89539 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32453 /* 89541 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32454 /* 89541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
32455 /* 89544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32456 /* 89546 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32457 /* 89548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32458 /* 89550 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32459 /* 89553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32460 /* 89556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32461 /* 89562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32462 /* 89568 */ GIR_RootConstrainSelectedInstOperands,
32463 /* 89569 */ // GIR_Coverage, 4183,
32464 /* 89569 */ GIR_EraseRootFromParent_Done,
32465 /* 89570 */ // Label 2764: @89570
32466 /* 89570 */ GIM_Reject,
32467 /* 89571 */ // Label 2762: @89571
32468 /* 89571 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(89689),
32469 /* 89576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32470 /* 89580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32471 /* 89584 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(89636), // Rule ID 4189 //
32472 /* 89589 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32473 /* 89593 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32474 /* 89597 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32475 /* 89601 */ // MIs[1] Operand 1
32476 /* 89601 */ // No operand predicates
32477 /* 89601 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32478 /* 89605 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32479 /* 89607 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32480 /* 89607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
32481 /* 89610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32482 /* 89612 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32483 /* 89614 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32484 /* 89616 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32485 /* 89619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32486 /* 89622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32487 /* 89628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32488 /* 89634 */ GIR_RootConstrainSelectedInstOperands,
32489 /* 89635 */ // GIR_Coverage, 4189,
32490 /* 89635 */ GIR_EraseRootFromParent_Done,
32491 /* 89636 */ // Label 2766: @89636
32492 /* 89636 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(89688), // Rule ID 4191 //
32493 /* 89641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32494 /* 89645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32495 /* 89649 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32496 /* 89653 */ // MIs[1] Operand 1
32497 /* 89653 */ // No operand predicates
32498 /* 89653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32499 /* 89657 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32500 /* 89659 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32501 /* 89659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
32502 /* 89662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32503 /* 89664 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32504 /* 89666 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32505 /* 89668 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32506 /* 89671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32507 /* 89674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32508 /* 89680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32509 /* 89686 */ GIR_RootConstrainSelectedInstOperands,
32510 /* 89687 */ // GIR_Coverage, 4191,
32511 /* 89687 */ GIR_EraseRootFromParent_Done,
32512 /* 89688 */ // Label 2767: @89688
32513 /* 89688 */ GIM_Reject,
32514 /* 89689 */ // Label 2765: @89689
32515 /* 89689 */ GIM_Reject,
32516 /* 89690 */ // Label 2761: @89690
32517 /* 89690 */ GIM_Reject,
32518 /* 89691 */ // Label 2753: @89691
32519 /* 89691 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(90437),
32520 /* 89696 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32521 /* 89700 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(89946),
32522 /* 89705 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32523 /* 89709 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(89827),
32524 /* 89714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32525 /* 89718 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32526 /* 89722 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(89774), // Rule ID 4197 //
32527 /* 89727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32528 /* 89731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32529 /* 89735 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32530 /* 89739 */ // MIs[1] Operand 1
32531 /* 89739 */ // No operand predicates
32532 /* 89739 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32533 /* 89743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32534 /* 89745 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32535 /* 89745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32),
32536 /* 89748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32537 /* 89750 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32538 /* 89752 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32539 /* 89754 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32540 /* 89757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32541 /* 89760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32542 /* 89766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32543 /* 89772 */ GIR_RootConstrainSelectedInstOperands,
32544 /* 89773 */ // GIR_Coverage, 4197,
32545 /* 89773 */ GIR_EraseRootFromParent_Done,
32546 /* 89774 */ // Label 2771: @89774
32547 /* 89774 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(89826), // Rule ID 4199 //
32548 /* 89779 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32549 /* 89783 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32550 /* 89787 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32551 /* 89791 */ // MIs[1] Operand 1
32552 /* 89791 */ // No operand predicates
32553 /* 89791 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32554 /* 89795 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32555 /* 89797 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32556 /* 89797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32),
32557 /* 89800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32558 /* 89802 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32559 /* 89804 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32560 /* 89806 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32561 /* 89809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32562 /* 89812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32563 /* 89818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32564 /* 89824 */ GIR_RootConstrainSelectedInstOperands,
32565 /* 89825 */ // GIR_Coverage, 4199,
32566 /* 89825 */ GIR_EraseRootFromParent_Done,
32567 /* 89826 */ // Label 2772: @89826
32568 /* 89826 */ GIM_Reject,
32569 /* 89827 */ // Label 2770: @89827
32570 /* 89827 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(89945),
32571 /* 89832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32572 /* 89836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32573 /* 89840 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(89892), // Rule ID 4205 //
32574 /* 89845 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32575 /* 89849 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32576 /* 89853 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32577 /* 89857 */ // MIs[1] Operand 1
32578 /* 89857 */ // No operand predicates
32579 /* 89857 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32580 /* 89861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32581 /* 89863 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32582 /* 89863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32),
32583 /* 89866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32584 /* 89868 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32585 /* 89870 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32586 /* 89872 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32587 /* 89875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32588 /* 89878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32589 /* 89884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32590 /* 89890 */ GIR_RootConstrainSelectedInstOperands,
32591 /* 89891 */ // GIR_Coverage, 4205,
32592 /* 89891 */ GIR_EraseRootFromParent_Done,
32593 /* 89892 */ // Label 2774: @89892
32594 /* 89892 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(89944), // Rule ID 4207 //
32595 /* 89897 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32596 /* 89901 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32597 /* 89905 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32598 /* 89909 */ // MIs[1] Operand 1
32599 /* 89909 */ // No operand predicates
32600 /* 89909 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32601 /* 89913 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32602 /* 89915 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32603 /* 89915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32),
32604 /* 89918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32605 /* 89920 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32606 /* 89922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32607 /* 89924 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32608 /* 89927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32609 /* 89930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32610 /* 89936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32611 /* 89942 */ GIR_RootConstrainSelectedInstOperands,
32612 /* 89943 */ // GIR_Coverage, 4207,
32613 /* 89943 */ GIR_EraseRootFromParent_Done,
32614 /* 89944 */ // Label 2775: @89944
32615 /* 89944 */ GIM_Reject,
32616 /* 89945 */ // Label 2773: @89945
32617 /* 89945 */ GIM_Reject,
32618 /* 89946 */ // Label 2769: @89946
32619 /* 89946 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(90192),
32620 /* 89951 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32621 /* 89955 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(90073),
32622 /* 89960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32623 /* 89964 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32624 /* 89968 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(90020), // Rule ID 4213 //
32625 /* 89973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32626 /* 89977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32627 /* 89981 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32628 /* 89985 */ // MIs[1] Operand 1
32629 /* 89985 */ // No operand predicates
32630 /* 89985 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32631 /* 89989 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32632 /* 89991 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32633 /* 89991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32),
32634 /* 89994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32635 /* 89996 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32636 /* 89998 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32637 /* 90000 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32638 /* 90003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32639 /* 90006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32640 /* 90012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32641 /* 90018 */ GIR_RootConstrainSelectedInstOperands,
32642 /* 90019 */ // GIR_Coverage, 4213,
32643 /* 90019 */ GIR_EraseRootFromParent_Done,
32644 /* 90020 */ // Label 2778: @90020
32645 /* 90020 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(90072), // Rule ID 4215 //
32646 /* 90025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32647 /* 90029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32648 /* 90033 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32649 /* 90037 */ // MIs[1] Operand 1
32650 /* 90037 */ // No operand predicates
32651 /* 90037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32652 /* 90041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32653 /* 90043 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32654 /* 90043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32),
32655 /* 90046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32656 /* 90048 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32657 /* 90050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32658 /* 90052 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32659 /* 90055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32660 /* 90058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32661 /* 90064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32662 /* 90070 */ GIR_RootConstrainSelectedInstOperands,
32663 /* 90071 */ // GIR_Coverage, 4215,
32664 /* 90071 */ GIR_EraseRootFromParent_Done,
32665 /* 90072 */ // Label 2779: @90072
32666 /* 90072 */ GIM_Reject,
32667 /* 90073 */ // Label 2777: @90073
32668 /* 90073 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(90191),
32669 /* 90078 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32670 /* 90082 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32671 /* 90086 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(90138), // Rule ID 4221 //
32672 /* 90091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32673 /* 90095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32674 /* 90099 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32675 /* 90103 */ // MIs[1] Operand 1
32676 /* 90103 */ // No operand predicates
32677 /* 90103 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32678 /* 90107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32679 /* 90109 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32680 /* 90109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32),
32681 /* 90112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32682 /* 90114 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32683 /* 90116 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32684 /* 90118 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32685 /* 90121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32686 /* 90124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32687 /* 90130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32688 /* 90136 */ GIR_RootConstrainSelectedInstOperands,
32689 /* 90137 */ // GIR_Coverage, 4221,
32690 /* 90137 */ GIR_EraseRootFromParent_Done,
32691 /* 90138 */ // Label 2781: @90138
32692 /* 90138 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(90190), // Rule ID 4223 //
32693 /* 90143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32694 /* 90147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32695 /* 90151 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32696 /* 90155 */ // MIs[1] Operand 1
32697 /* 90155 */ // No operand predicates
32698 /* 90155 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32699 /* 90159 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32700 /* 90161 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32701 /* 90161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32),
32702 /* 90164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32703 /* 90166 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32704 /* 90168 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32705 /* 90170 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32706 /* 90173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32707 /* 90176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32708 /* 90182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32709 /* 90188 */ GIR_RootConstrainSelectedInstOperands,
32710 /* 90189 */ // GIR_Coverage, 4223,
32711 /* 90189 */ GIR_EraseRootFromParent_Done,
32712 /* 90190 */ // Label 2782: @90190
32713 /* 90190 */ GIM_Reject,
32714 /* 90191 */ // Label 2780: @90191
32715 /* 90191 */ GIM_Reject,
32716 /* 90192 */ // Label 2776: @90192
32717 /* 90192 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(90314),
32718 /* 90197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32719 /* 90201 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32720 /* 90205 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32721 /* 90209 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(90261), // Rule ID 4229 //
32722 /* 90214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32723 /* 90218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32724 /* 90222 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32725 /* 90226 */ // MIs[1] Operand 1
32726 /* 90226 */ // No operand predicates
32727 /* 90226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32728 /* 90230 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32729 /* 90232 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32730 /* 90232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh),
32731 /* 90235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32732 /* 90237 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32733 /* 90239 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32734 /* 90241 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32735 /* 90244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32736 /* 90247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32737 /* 90253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32738 /* 90259 */ GIR_RootConstrainSelectedInstOperands,
32739 /* 90260 */ // GIR_Coverage, 4229,
32740 /* 90260 */ GIR_EraseRootFromParent_Done,
32741 /* 90261 */ // Label 2784: @90261
32742 /* 90261 */ GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(90313), // Rule ID 4231 //
32743 /* 90266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32744 /* 90270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32745 /* 90274 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32746 /* 90278 */ // MIs[1] Operand 1
32747 /* 90278 */ // No operand predicates
32748 /* 90278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32749 /* 90282 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32750 /* 90284 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32751 /* 90284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th),
32752 /* 90287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32753 /* 90289 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32754 /* 90291 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32755 /* 90293 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32756 /* 90296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32757 /* 90299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32758 /* 90305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32759 /* 90311 */ GIR_RootConstrainSelectedInstOperands,
32760 /* 90312 */ // GIR_Coverage, 4231,
32761 /* 90312 */ GIR_EraseRootFromParent_Done,
32762 /* 90313 */ // Label 2785: @90313
32763 /* 90313 */ GIM_Reject,
32764 /* 90314 */ // Label 2783: @90314
32765 /* 90314 */ GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(90436),
32766 /* 90319 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32767 /* 90323 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32768 /* 90327 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32769 /* 90331 */ GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(90383), // Rule ID 4237 //
32770 /* 90336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32771 /* 90340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32772 /* 90344 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32773 /* 90348 */ // MIs[1] Operand 1
32774 /* 90348 */ // No operand predicates
32775 /* 90348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32776 /* 90352 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32777 /* 90354 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32778 /* 90354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh),
32779 /* 90357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32780 /* 90359 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32781 /* 90361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32782 /* 90363 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32783 /* 90366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32784 /* 90369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32785 /* 90375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32786 /* 90381 */ GIR_RootConstrainSelectedInstOperands,
32787 /* 90382 */ // GIR_Coverage, 4237,
32788 /* 90382 */ GIR_EraseRootFromParent_Done,
32789 /* 90383 */ // Label 2787: @90383
32790 /* 90383 */ GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(90435), // Rule ID 4239 //
32791 /* 90388 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32792 /* 90392 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32793 /* 90396 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32794 /* 90400 */ // MIs[1] Operand 1
32795 /* 90400 */ // No operand predicates
32796 /* 90400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32797 /* 90404 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32798 /* 90406 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32799 /* 90406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th),
32800 /* 90409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32801 /* 90411 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32802 /* 90413 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32803 /* 90415 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32804 /* 90418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32805 /* 90421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32806 /* 90427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32807 /* 90433 */ GIR_RootConstrainSelectedInstOperands,
32808 /* 90434 */ // GIR_Coverage, 4239,
32809 /* 90434 */ GIR_EraseRootFromParent_Done,
32810 /* 90435 */ // Label 2788: @90435
32811 /* 90435 */ GIM_Reject,
32812 /* 90436 */ // Label 2786: @90436
32813 /* 90436 */ GIM_Reject,
32814 /* 90437 */ // Label 2768: @90437
32815 /* 90437 */ GIM_Reject,
32816 /* 90438 */ // Label 2752: @90438
32817 /* 90438 */ GIM_Reject,
32818 /* 90439 */ // Label 2714: @90439
32819 /* 90439 */ GIM_Reject,
32820 /* 90440 */ // Label 2711: @90440
32821 /* 90440 */ GIM_Reject,
32822 /* 90441 */ // Label 23: @90441
32823 /* 90441 */ GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(90496),
32824 /* 90446 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
32825 /* 90449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex),
32826 /* 90454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2790*/ GIMT_Encode4(90470), GIMT_Encode2(GIFBS_HasV6K_IsARM), // Rule ID 244 //
32827 /* 90461 */ // (intrinsic_void 3726:{ *:[iPTR] }) => (CLREX)
32828 /* 90461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX),
32829 /* 90464 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32830 /* 90468 */ GIR_RootConstrainSelectedInstOperands,
32831 /* 90469 */ // GIR_Coverage, 244,
32832 /* 90469 */ GIR_EraseRootFromParent_Done,
32833 /* 90470 */ // Label 2790: @90470
32834 /* 90470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2791*/ GIMT_Encode4(90495), GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb), // Rule ID 573 //
32835 /* 90477 */ // (intrinsic_void 3726:{ *:[iPTR] }) => (t2CLREX)
32836 /* 90477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX),
32837 /* 90480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32838 /* 90483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32839 /* 90489 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32840 /* 90493 */ GIR_RootConstrainSelectedInstOperands,
32841 /* 90494 */ // GIR_Coverage, 573,
32842 /* 90494 */ GIR_EraseRootFromParent_Done,
32843 /* 90495 */ // Label 2791: @90495
32844 /* 90495 */ GIM_Reject,
32845 /* 90496 */ // Label 2789: @90496
32846 /* 90496 */ GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(91279),
32847 /* 90501 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
32848 /* 90504 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2793*/ GIMT_Encode4(90539), GIMT_Encode2(GIFBS_IsThumb_IsWindows), // Rule ID 343 //
32849 /* 90511 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
32850 /* 90516 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32851 /* 90519 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249),
32852 /* 90530 */ // (intrinsic_void 4180:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0)
32853 /* 90530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0),
32854 /* 90533 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32855 /* 90537 */ GIR_RootConstrainSelectedInstOperands,
32856 /* 90538 */ // GIR_Coverage, 343,
32857 /* 90538 */ GIR_EraseRootFromParent_Done,
32858 /* 90539 */ // Label 2793: @90539
32859 /* 90539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2794*/ GIMT_Encode4(90590), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2 //
32860 /* 90546 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
32861 /* 90551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32862 /* 90554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32863 /* 90558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32864 /* 90562 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
32865 /* 90566 */ // MIs[1] Operand 1
32866 /* 90566 */ // No operand predicates
32867 /* 90566 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32868 /* 90568 */ // (intrinsic_void 3744:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm)
32869 /* 90568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT),
32870 /* 90571 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32871 /* 90574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32872 /* 90577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32873 /* 90583 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32874 /* 90588 */ GIR_RootConstrainSelectedInstOperands,
32875 /* 90589 */ // GIR_Coverage, 2,
32876 /* 90589 */ GIR_EraseRootFromParent_Done,
32877 /* 90590 */ // Label 2794: @90590
32878 /* 90590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2795*/ GIMT_Encode4(90641), GIMT_Encode2(GIFBS_HasV7_IsARM), // Rule ID 10 //
32879 /* 90597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
32880 /* 90602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32881 /* 90605 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32882 /* 90609 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32883 /* 90613 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32884 /* 90617 */ // MIs[1] Operand 1
32885 /* 90617 */ // No operand predicates
32886 /* 90617 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32887 /* 90619 */ // (intrinsic_void 3739:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt)
32888 /* 90619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG),
32889 /* 90622 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32890 /* 90625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32891 /* 90628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32892 /* 90634 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32893 /* 90639 */ GIR_RootConstrainSelectedInstOperands,
32894 /* 90640 */ // GIR_Coverage, 10,
32895 /* 90640 */ GIR_EraseRootFromParent_Done,
32896 /* 90641 */ // Label 2795: @90641
32897 /* 90641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2796*/ GIMT_Encode4(90683), GIMT_Encode2(GIFBS_IsARM), // Rule ID 11 //
32898 /* 90648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
32899 /* 90653 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32900 /* 90656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32901 /* 90660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32902 /* 90664 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
32903 /* 90668 */ // MIs[1] Operand 1
32904 /* 90668 */ // No operand predicates
32905 /* 90668 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32906 /* 90670 */ // (intrinsic_void 4180:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16)
32907 /* 90670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
32908 /* 90673 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
32909 /* 90676 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32910 /* 90681 */ GIR_RootConstrainSelectedInstOperands,
32911 /* 90682 */ // GIR_Coverage, 11,
32912 /* 90682 */ GIR_EraseRootFromParent_Done,
32913 /* 90683 */ // Label 2796: @90683
32914 /* 90683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2797*/ GIMT_Encode4(90725), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 227 //
32915 /* 90690 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
32916 /* 90695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32917 /* 90698 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32918 /* 90702 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32919 /* 90706 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32920 /* 90710 */ // MIs[1] Operand 1
32921 /* 90710 */ // No operand predicates
32922 /* 90710 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32923 /* 90712 */ // (intrinsic_void 3740:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt)
32924 /* 90712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB),
32925 /* 90715 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32926 /* 90718 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32927 /* 90723 */ GIR_RootConstrainSelectedInstOperands,
32928 /* 90724 */ // GIR_Coverage, 227,
32929 /* 90724 */ GIR_EraseRootFromParent_Done,
32930 /* 90725 */ // Label 2797: @90725
32931 /* 90725 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2798*/ GIMT_Encode4(90767), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 228 //
32932 /* 90732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
32933 /* 90737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32934 /* 90740 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32935 /* 90744 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32936 /* 90748 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32937 /* 90752 */ // MIs[1] Operand 1
32938 /* 90752 */ // No operand predicates
32939 /* 90752 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32940 /* 90754 */ // (intrinsic_void 3741:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt)
32941 /* 90754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB),
32942 /* 90757 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32943 /* 90760 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32944 /* 90765 */ GIR_RootConstrainSelectedInstOperands,
32945 /* 90766 */ // GIR_Coverage, 228,
32946 /* 90766 */ GIR_EraseRootFromParent_Done,
32947 /* 90767 */ // Label 2798: @90767
32948 /* 90767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2799*/ GIMT_Encode4(90809), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 229 //
32949 /* 90774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
32950 /* 90779 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32951 /* 90782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32952 /* 90786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32953 /* 90790 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32954 /* 90794 */ // MIs[1] Operand 1
32955 /* 90794 */ // No operand predicates
32956 /* 90794 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32957 /* 90796 */ // (intrinsic_void 3745:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt)
32958 /* 90796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB),
32959 /* 90799 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32960 /* 90802 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32961 /* 90807 */ GIR_RootConstrainSelectedInstOperands,
32962 /* 90808 */ // GIR_Coverage, 229,
32963 /* 90808 */ GIR_EraseRootFromParent_Done,
32964 /* 90809 */ // Label 2799: @90809
32965 /* 90809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2800*/ GIMT_Encode4(90860), GIMT_Encode2(GIFBS_HasV6M_IsThumb), // Rule ID 275 //
32966 /* 90816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
32967 /* 90821 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32968 /* 90824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32969 /* 90828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32970 /* 90832 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32971 /* 90836 */ // MIs[1] Operand 1
32972 /* 90836 */ // No operand predicates
32973 /* 90836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32974 /* 90838 */ // (intrinsic_void 3744:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm)
32975 /* 90838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT),
32976 /* 90841 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32977 /* 90844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32978 /* 90847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32979 /* 90853 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32980 /* 90858 */ GIR_RootConstrainSelectedInstOperands,
32981 /* 90859 */ // GIR_Coverage, 275,
32982 /* 90859 */ GIR_EraseRootFromParent_Done,
32983 /* 90860 */ // Label 2800: @90860
32984 /* 90860 */ GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(90942),
32985 /* 90865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
32986 /* 90870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32987 /* 90873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2802*/ GIMT_Encode4(90907), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 342 //
32988 /* 90880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32989 /* 90884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32990 /* 90888 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
32991 /* 90892 */ // MIs[1] Operand 1
32992 /* 90892 */ // No operand predicates
32993 /* 90892 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32994 /* 90894 */ // (intrinsic_void 4180:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8)
32995 /* 90894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
32996 /* 90897 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
32997 /* 90900 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32998 /* 90905 */ GIR_RootConstrainSelectedInstOperands,
32999 /* 90906 */ // GIR_Coverage, 342,
33000 /* 90906 */ GIR_EraseRootFromParent_Done,
33001 /* 90907 */ // Label 2802: @90907
33002 /* 90907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2803*/ GIMT_Encode4(90941), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 493 //
33003 /* 90914 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33004 /* 90918 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33005 /* 90922 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
33006 /* 90926 */ // MIs[1] Operand 1
33007 /* 90926 */ // No operand predicates
33008 /* 90926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33009 /* 90928 */ // (intrinsic_void 4180:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16)
33010 /* 90928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF),
33011 /* 90931 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
33012 /* 90934 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33013 /* 90939 */ GIR_RootConstrainSelectedInstOperands,
33014 /* 90940 */ // GIR_Coverage, 493,
33015 /* 90940 */ GIR_EraseRootFromParent_Done,
33016 /* 90941 */ // Label 2803: @90941
33017 /* 90941 */ GIM_Reject,
33018 /* 90942 */ // Label 2801: @90942
33019 /* 90942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2804*/ GIMT_Encode4(90993), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 558 //
33020 /* 90949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
33021 /* 90954 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33022 /* 90957 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33023 /* 90961 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33024 /* 90965 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
33025 /* 90969 */ // MIs[1] Operand 1
33026 /* 90969 */ // No operand predicates
33027 /* 90969 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33028 /* 90971 */ // (intrinsic_void 3740:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt)
33029 /* 90971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB),
33030 /* 90974 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33031 /* 90977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33032 /* 90980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33033 /* 90986 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33034 /* 90991 */ GIR_RootConstrainSelectedInstOperands,
33035 /* 90992 */ // GIR_Coverage, 558,
33036 /* 90992 */ GIR_EraseRootFromParent_Done,
33037 /* 90993 */ // Label 2804: @90993
33038 /* 90993 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2805*/ GIMT_Encode4(91044), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 559 //
33039 /* 91000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
33040 /* 91005 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33041 /* 91008 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33042 /* 91012 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33043 /* 91016 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
33044 /* 91020 */ // MIs[1] Operand 1
33045 /* 91020 */ // No operand predicates
33046 /* 91020 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33047 /* 91022 */ // (intrinsic_void 3741:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt)
33048 /* 91022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB),
33049 /* 91025 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33050 /* 91028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33051 /* 91031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33052 /* 91037 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33053 /* 91042 */ GIR_RootConstrainSelectedInstOperands,
33054 /* 91043 */ // GIR_Coverage, 559,
33055 /* 91043 */ GIR_EraseRootFromParent_Done,
33056 /* 91044 */ // Label 2805: @91044
33057 /* 91044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2806*/ GIMT_Encode4(91095), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 560 //
33058 /* 91051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
33059 /* 91056 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33060 /* 91059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33061 /* 91063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33062 /* 91067 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
33063 /* 91071 */ // MIs[1] Operand 1
33064 /* 91071 */ // No operand predicates
33065 /* 91071 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33066 /* 91073 */ // (intrinsic_void 3745:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt)
33067 /* 91073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB),
33068 /* 91076 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33069 /* 91079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33070 /* 91082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33071 /* 91088 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33072 /* 91093 */ GIR_RootConstrainSelectedInstOperands,
33073 /* 91094 */ // GIR_Coverage, 560,
33074 /* 91094 */ GIR_EraseRootFromParent_Done,
33075 /* 91095 */ // Label 2806: @91095
33076 /* 91095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2807*/ GIMT_Encode4(91146), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 578 //
33077 /* 91102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
33078 /* 91107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33079 /* 91110 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33080 /* 91114 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33081 /* 91118 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
33082 /* 91122 */ // MIs[1] Operand 1
33083 /* 91122 */ // No operand predicates
33084 /* 91122 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33085 /* 91124 */ // (intrinsic_void 3744:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm)
33086 /* 91124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT),
33087 /* 91127 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33088 /* 91130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33089 /* 91133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33090 /* 91139 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33091 /* 91144 */ GIR_RootConstrainSelectedInstOperands,
33092 /* 91145 */ // GIR_Coverage, 578,
33093 /* 91145 */ GIR_EraseRootFromParent_Done,
33094 /* 91146 */ // Label 2807: @91146
33095 /* 91146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2808*/ GIMT_Encode4(91197), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 579 //
33096 /* 91153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
33097 /* 91158 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33098 /* 91161 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33099 /* 91165 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33100 /* 91169 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
33101 /* 91173 */ // MIs[1] Operand 1
33102 /* 91173 */ // No operand predicates
33103 /* 91173 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33104 /* 91175 */ // (intrinsic_void 3739:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt)
33105 /* 91175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG),
33106 /* 91178 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33107 /* 91181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33108 /* 91184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33109 /* 91190 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33110 /* 91195 */ GIR_RootConstrainSelectedInstOperands,
33111 /* 91196 */ // GIR_Coverage, 579,
33112 /* 91196 */ GIR_EraseRootFromParent_Done,
33113 /* 91197 */ // Label 2808: @91197
33114 /* 91197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2809*/ GIMT_Encode4(91236), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 845 //
33115 /* 91204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr),
33116 /* 91209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33117 /* 91212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33118 /* 91216 */ // (intrinsic_w_chain:{ *:[i32] } 3742:{ *:[iPTR] }) => (VMRS:{ *:[i32] })
33119 /* 91216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
33120 /* 91219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
33121 /* 91221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33122 /* 91224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33123 /* 91230 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33124 /* 91234 */ GIR_RootConstrainSelectedInstOperands,
33125 /* 91235 */ // GIR_Coverage, 845,
33126 /* 91235 */ GIR_EraseRootFromParent_Done,
33127 /* 91236 */ // Label 2809: @91236
33128 /* 91236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2810*/ GIMT_Encode4(91278), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 846 //
33129 /* 91243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr),
33130 /* 91248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33131 /* 91251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33132 /* 91255 */ // (intrinsic_void 4124:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
33133 /* 91255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
33134 /* 91258 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
33135 /* 91260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33136 /* 91263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33137 /* 91269 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
33138 /* 91272 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33139 /* 91276 */ GIR_RootConstrainSelectedInstOperands,
33140 /* 91277 */ // GIR_Coverage, 846,
33141 /* 91277 */ GIR_EraseRootFromParent_Done,
33142 /* 91278 */ // Label 2810: @91278
33143 /* 91278 */ GIM_Reject,
33144 /* 91279 */ // Label 2792: @91279
33145 /* 91279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2811*/ GIMT_Encode4(91321), GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2), // Rule ID 603 //
33146 /* 91286 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
33147 /* 91289 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations),
33148 /* 91294 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33149 /* 91297 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33150 /* 91300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID),
33151 /* 91304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33152 /* 91308 */ // (intrinsic_w_chain:{ *:[i32] } 373:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc)
33153 /* 91308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart),
33154 /* 91311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X]
33155 /* 91313 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc
33156 /* 91315 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33157 /* 91319 */ GIR_RootConstrainSelectedInstOperands,
33158 /* 91320 */ // GIR_Coverage, 603,
33159 /* 91320 */ GIR_EraseRootFromParent_Done,
33160 /* 91321 */ // Label 2811: @91321
33161 /* 91321 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(93254),
33162 /* 91326 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
33163 /* 91329 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(91529),
33164 /* 91334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
33165 /* 91339 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2816*/ GIMT_Encode4(91528),
33166 /* 91350 */ /*GILLT_v4s32*//*Label 2814*/ GIMT_Encode4(91358),
33167 /* 91354 */ /*GILLT_v2s64*//*Label 2815*/ GIMT_Encode4(91443),
33168 /* 91358 */ // Label 2814: @91358
33169 /* 91358 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(91442),
33170 /* 91363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33171 /* 91366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33172 /* 91369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33173 /* 91373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33174 /* 91377 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(91409), // Rule ID 5586 //
33175 /* 91382 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33176 /* 91386 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33177 /* 91390 */ // MIs[1] Operand 1
33178 /* 91390 */ // No operand predicates
33179 /* 91390 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33180 /* 91392 */ // (intrinsic_w_chain:{ *:[v4i32] } 3885:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33181 /* 91392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
33182 /* 91395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33183 /* 91397 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33184 /* 91399 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33185 /* 91402 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33186 /* 91407 */ GIR_RootConstrainSelectedInstOperands,
33187 /* 91408 */ // GIR_Coverage, 5586,
33188 /* 91408 */ GIR_EraseRootFromParent_Done,
33189 /* 91409 */ // Label 2818: @91409
33190 /* 91409 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(91441), // Rule ID 5592 //
33191 /* 91414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33192 /* 91418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33193 /* 91422 */ // MIs[1] Operand 1
33194 /* 91422 */ // No operand predicates
33195 /* 91422 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33196 /* 91424 */ // (intrinsic_w_chain:{ *:[v4f32] } 3885:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33197 /* 91424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
33198 /* 91427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33199 /* 91429 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33200 /* 91431 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33201 /* 91434 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33202 /* 91439 */ GIR_RootConstrainSelectedInstOperands,
33203 /* 91440 */ // GIR_Coverage, 5592,
33204 /* 91440 */ GIR_EraseRootFromParent_Done,
33205 /* 91441 */ // Label 2819: @91441
33206 /* 91441 */ GIM_Reject,
33207 /* 91442 */ // Label 2817: @91442
33208 /* 91442 */ GIM_Reject,
33209 /* 91443 */ // Label 2815: @91443
33210 /* 91443 */ GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(91527),
33211 /* 91448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
33212 /* 91451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33213 /* 91454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33214 /* 91458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33215 /* 91462 */ GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(91494), // Rule ID 5594 //
33216 /* 91467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33217 /* 91471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33218 /* 91475 */ // MIs[1] Operand 1
33219 /* 91475 */ // No operand predicates
33220 /* 91475 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33221 /* 91477 */ // (intrinsic_w_chain:{ *:[v2i64] } 3885:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33222 /* 91477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
33223 /* 91480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33224 /* 91482 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33225 /* 91484 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33226 /* 91487 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33227 /* 91492 */ GIR_RootConstrainSelectedInstOperands,
33228 /* 91493 */ // GIR_Coverage, 5594,
33229 /* 91493 */ GIR_EraseRootFromParent_Done,
33230 /* 91494 */ // Label 2821: @91494
33231 /* 91494 */ GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(91526), // Rule ID 5596 //
33232 /* 91499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33233 /* 91503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33234 /* 91507 */ // MIs[1] Operand 1
33235 /* 91507 */ // No operand predicates
33236 /* 91507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33237 /* 91509 */ // (intrinsic_w_chain:{ *:[v2f64] } 3885:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33238 /* 91509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
33239 /* 91512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33240 /* 91514 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33241 /* 91516 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33242 /* 91519 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33243 /* 91524 */ GIR_RootConstrainSelectedInstOperands,
33244 /* 91525 */ // GIR_Coverage, 5596,
33245 /* 91525 */ GIR_EraseRootFromParent_Done,
33246 /* 91526 */ // Label 2822: @91526
33247 /* 91526 */ GIM_Reject,
33248 /* 91527 */ // Label 2820: @91527
33249 /* 91527 */ GIM_Reject,
33250 /* 91528 */ // Label 2816: @91528
33251 /* 91528 */ GIM_Reject,
33252 /* 91529 */ // Label 2813: @91529
33253 /* 91529 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(91571), // Rule ID 1927 //
33254 /* 91534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space),
33255 /* 91539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33256 /* 91542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33257 /* 91545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33258 /* 91549 */ // MIs[0] size
33259 /* 91549 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
33260 /* 91552 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33261 /* 91556 */ // (intrinsic_w_chain:{ *:[i32] } 4155:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
33262 /* 91556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE),
33263 /* 91559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33264 /* 91561 */ GIR_RootToRootCopy, /*OpIdx*/2, // size
33265 /* 91563 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
33266 /* 91565 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33267 /* 91569 */ GIR_RootConstrainSelectedInstOperands,
33268 /* 91570 */ // GIR_Coverage, 1927,
33269 /* 91570 */ GIR_EraseRootFromParent_Done,
33270 /* 91571 */ // Label 2823: @91571
33271 /* 91571 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(91771),
33272 /* 91576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
33273 /* 91581 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2827*/ GIMT_Encode4(91770),
33274 /* 91592 */ /*GILLT_v4s32*//*Label 2825*/ GIMT_Encode4(91600),
33275 /* 91596 */ /*GILLT_v2s64*//*Label 2826*/ GIMT_Encode4(91685),
33276 /* 91600 */ // Label 2825: @91600
33277 /* 91600 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(91684),
33278 /* 91605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33279 /* 91608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33280 /* 91611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33281 /* 91615 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33282 /* 91619 */ GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(91651), // Rule ID 5588 //
33283 /* 91624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33284 /* 91628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33285 /* 91632 */ // MIs[1] Operand 1
33286 /* 91632 */ // No operand predicates
33287 /* 91632 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33288 /* 91634 */ // (intrinsic_void 3967:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33289 /* 91634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
33290 /* 91637 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33291 /* 91639 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33292 /* 91641 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33293 /* 91644 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33294 /* 91649 */ GIR_RootConstrainSelectedInstOperands,
33295 /* 91650 */ // GIR_Coverage, 5588,
33296 /* 91650 */ GIR_EraseRootFromParent_Done,
33297 /* 91651 */ // Label 2829: @91651
33298 /* 91651 */ GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(91683), // Rule ID 5598 //
33299 /* 91656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33300 /* 91660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33301 /* 91664 */ // MIs[1] Operand 1
33302 /* 91664 */ // No operand predicates
33303 /* 91664 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33304 /* 91666 */ // (intrinsic_void 3967:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33305 /* 91666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
33306 /* 91669 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33307 /* 91671 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33308 /* 91673 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33309 /* 91676 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33310 /* 91681 */ GIR_RootConstrainSelectedInstOperands,
33311 /* 91682 */ // GIR_Coverage, 5598,
33312 /* 91682 */ GIR_EraseRootFromParent_Done,
33313 /* 91683 */ // Label 2830: @91683
33314 /* 91683 */ GIM_Reject,
33315 /* 91684 */ // Label 2828: @91684
33316 /* 91684 */ GIM_Reject,
33317 /* 91685 */ // Label 2826: @91685
33318 /* 91685 */ GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(91769),
33319 /* 91690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33320 /* 91693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
33321 /* 91696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33322 /* 91700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33323 /* 91704 */ GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(91736), // Rule ID 5602 //
33324 /* 91709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33325 /* 91713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33326 /* 91717 */ // MIs[1] Operand 1
33327 /* 91717 */ // No operand predicates
33328 /* 91717 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33329 /* 91719 */ // (intrinsic_void 3967:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33330 /* 91719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
33331 /* 91722 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33332 /* 91724 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33333 /* 91726 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33334 /* 91729 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33335 /* 91734 */ GIR_RootConstrainSelectedInstOperands,
33336 /* 91735 */ // GIR_Coverage, 5602,
33337 /* 91735 */ GIR_EraseRootFromParent_Done,
33338 /* 91736 */ // Label 2832: @91736
33339 /* 91736 */ GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(91768), // Rule ID 5606 //
33340 /* 91741 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33341 /* 91745 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33342 /* 91749 */ // MIs[1] Operand 1
33343 /* 91749 */ // No operand predicates
33344 /* 91749 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33345 /* 91751 */ // (intrinsic_void 3967:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33346 /* 91751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
33347 /* 91754 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33348 /* 91756 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33349 /* 91758 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33350 /* 91761 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33351 /* 91766 */ GIR_RootConstrainSelectedInstOperands,
33352 /* 91767 */ // GIR_Coverage, 5606,
33353 /* 91767 */ GIR_EraseRootFromParent_Done,
33354 /* 91768 */ // Label 2833: @91768
33355 /* 91768 */ GIM_Reject,
33356 /* 91769 */ // Label 2831: @91769
33357 /* 91769 */ GIM_Reject,
33358 /* 91770 */ // Label 2827: @91770
33359 /* 91770 */ GIM_Reject,
33360 /* 91771 */ // Label 2824: @91771
33361 /* 91771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2834*/ GIMT_Encode4(91828), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 3 //
33362 /* 91778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
33363 /* 91783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33364 /* 91786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33365 /* 91789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33366 /* 91792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33367 /* 91796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33368 /* 91800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33369 /* 91804 */ // (intrinsic_w_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
33370 /* 91804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL),
33371 /* 91807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33372 /* 91809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33373 /* 91811 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33374 /* 91813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33375 /* 91816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33376 /* 91822 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33377 /* 91826 */ GIR_RootConstrainSelectedInstOperands,
33378 /* 91827 */ // GIR_Coverage, 3,
33379 /* 91827 */ GIR_EraseRootFromParent_Done,
33380 /* 91828 */ // Label 2834: @91828
33381 /* 91828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2835*/ GIMT_Encode4(91885), GIMT_Encode2(GIFBS_IsARM), // Rule ID 120 //
33382 /* 91835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
33383 /* 91840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33384 /* 91843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33385 /* 91846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33386 /* 91849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33387 /* 91853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33388 /* 91857 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33389 /* 91861 */ // (intrinsic_w_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33390 /* 91861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX),
33391 /* 91864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33392 /* 91866 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33393 /* 91868 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33394 /* 91870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33395 /* 91873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33396 /* 91879 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33397 /* 91883 */ GIR_RootConstrainSelectedInstOperands,
33398 /* 91884 */ // GIR_Coverage, 120,
33399 /* 91884 */ GIR_EraseRootFromParent_Done,
33400 /* 91885 */ // Label 2835: @91885
33401 /* 91885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2836*/ GIMT_Encode4(91942), GIMT_Encode2(GIFBS_IsARM), // Rule ID 121 //
33402 /* 91892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
33403 /* 91897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33404 /* 91900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33405 /* 91903 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33406 /* 91906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33407 /* 91910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33408 /* 91914 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33409 /* 91918 */ // (intrinsic_w_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33410 /* 91918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16),
33411 /* 91921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33412 /* 91923 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33413 /* 91925 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33414 /* 91927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33415 /* 91930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33416 /* 91936 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33417 /* 91940 */ GIR_RootConstrainSelectedInstOperands,
33418 /* 91941 */ // GIR_Coverage, 121,
33419 /* 91941 */ GIR_EraseRootFromParent_Done,
33420 /* 91942 */ // Label 2836: @91942
33421 /* 91942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2837*/ GIMT_Encode4(91999), GIMT_Encode2(GIFBS_IsARM), // Rule ID 122 //
33422 /* 91949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
33423 /* 91954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33424 /* 91957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33425 /* 91960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33426 /* 91963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33427 /* 91967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33428 /* 91971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33429 /* 91975 */ // (intrinsic_w_chain:{ *:[i32] } 4121:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33430 /* 91975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8),
33431 /* 91978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33432 /* 91980 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33433 /* 91982 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33434 /* 91984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33435 /* 91987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33436 /* 91993 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33437 /* 91997 */ GIR_RootConstrainSelectedInstOperands,
33438 /* 91998 */ // GIR_Coverage, 122,
33439 /* 91998 */ GIR_EraseRootFromParent_Done,
33440 /* 91999 */ // Label 2837: @91999
33441 /* 91999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2838*/ GIMT_Encode4(92056), GIMT_Encode2(GIFBS_IsARM), // Rule ID 123 //
33442 /* 92006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
33443 /* 92011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33444 /* 92014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33445 /* 92017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33446 /* 92020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33447 /* 92024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33448 /* 92028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33449 /* 92032 */ // (intrinsic_w_chain:{ *:[i32] } 4158:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33450 /* 92032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX),
33451 /* 92035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33452 /* 92037 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33453 /* 92039 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33454 /* 92041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33455 /* 92044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33456 /* 92050 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33457 /* 92054 */ GIR_RootConstrainSelectedInstOperands,
33458 /* 92055 */ // GIR_Coverage, 123,
33459 /* 92055 */ GIR_EraseRootFromParent_Done,
33460 /* 92056 */ // Label 2838: @92056
33461 /* 92056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2839*/ GIMT_Encode4(92113), GIMT_Encode2(GIFBS_IsARM), // Rule ID 124 //
33462 /* 92063 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
33463 /* 92068 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33464 /* 92071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33465 /* 92074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33466 /* 92077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33467 /* 92081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33468 /* 92085 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33469 /* 92089 */ // (intrinsic_w_chain:{ *:[i32] } 4159:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33470 /* 92089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16),
33471 /* 92092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33472 /* 92094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33473 /* 92096 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33474 /* 92098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33475 /* 92101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33476 /* 92107 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33477 /* 92111 */ GIR_RootConstrainSelectedInstOperands,
33478 /* 92112 */ // GIR_Coverage, 124,
33479 /* 92112 */ GIR_EraseRootFromParent_Done,
33480 /* 92113 */ // Label 2839: @92113
33481 /* 92113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2840*/ GIMT_Encode4(92170), GIMT_Encode2(GIFBS_IsARM), // Rule ID 125 //
33482 /* 92120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
33483 /* 92125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33484 /* 92128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33485 /* 92131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33486 /* 92134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33487 /* 92138 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33488 /* 92142 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33489 /* 92146 */ // (intrinsic_w_chain:{ *:[i32] } 4160:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33490 /* 92146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8),
33491 /* 92149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33492 /* 92151 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33493 /* 92153 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33494 /* 92155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33495 /* 92158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33496 /* 92164 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33497 /* 92168 */ GIR_RootConstrainSelectedInstOperands,
33498 /* 92169 */ // GIR_Coverage, 125,
33499 /* 92169 */ GIR_EraseRootFromParent_Done,
33500 /* 92170 */ // Label 2840: @92170
33501 /* 92170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2841*/ GIMT_Encode4(92227), GIMT_Encode2(GIFBS_IsARM), // Rule ID 126 //
33502 /* 92177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
33503 /* 92182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33504 /* 92185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33505 /* 92188 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33506 /* 92191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33507 /* 92195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33508 /* 92199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33509 /* 92203 */ // (intrinsic_w_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33510 /* 92203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX),
33511 /* 92206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33512 /* 92208 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33513 /* 92210 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33514 /* 92212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33515 /* 92215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33516 /* 92221 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33517 /* 92225 */ GIR_RootConstrainSelectedInstOperands,
33518 /* 92226 */ // GIR_Coverage, 126,
33519 /* 92226 */ GIR_EraseRootFromParent_Done,
33520 /* 92227 */ // Label 2841: @92227
33521 /* 92227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2842*/ GIMT_Encode4(92284), GIMT_Encode2(GIFBS_IsARM), // Rule ID 127 //
33522 /* 92234 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
33523 /* 92239 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33524 /* 92242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33525 /* 92245 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33526 /* 92248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33527 /* 92252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33528 /* 92256 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33529 /* 92260 */ // (intrinsic_w_chain:{ *:[i32] } 4171:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33530 /* 92260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16),
33531 /* 92263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33532 /* 92265 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33533 /* 92267 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33534 /* 92269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33535 /* 92272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33536 /* 92278 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33537 /* 92282 */ GIR_RootConstrainSelectedInstOperands,
33538 /* 92283 */ // GIR_Coverage, 127,
33539 /* 92283 */ GIR_EraseRootFromParent_Done,
33540 /* 92284 */ // Label 2842: @92284
33541 /* 92284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2843*/ GIMT_Encode4(92341), GIMT_Encode2(GIFBS_IsARM), // Rule ID 128 //
33542 /* 92291 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
33543 /* 92296 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33544 /* 92299 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33545 /* 92302 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33546 /* 92305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33547 /* 92309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33548 /* 92313 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33549 /* 92317 */ // (intrinsic_w_chain:{ *:[i32] } 4172:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33550 /* 92317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8),
33551 /* 92320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33552 /* 92322 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33553 /* 92324 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33554 /* 92326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33555 /* 92329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33556 /* 92335 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33557 /* 92339 */ GIR_RootConstrainSelectedInstOperands,
33558 /* 92340 */ // GIR_Coverage, 128,
33559 /* 92340 */ GIR_EraseRootFromParent_Done,
33560 /* 92341 */ // Label 2843: @92341
33561 /* 92341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2844*/ GIMT_Encode4(92398), GIMT_Encode2(GIFBS_IsARM), // Rule ID 129 //
33562 /* 92348 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
33563 /* 92353 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33564 /* 92356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33565 /* 92359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33566 /* 92362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33567 /* 92366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33568 /* 92370 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33569 /* 92374 */ // (intrinsic_w_chain:{ *:[i32] } 4191:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33570 /* 92374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX),
33571 /* 92377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33572 /* 92379 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33573 /* 92381 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33574 /* 92383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33575 /* 92386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33576 /* 92392 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33577 /* 92396 */ GIR_RootConstrainSelectedInstOperands,
33578 /* 92397 */ // GIR_Coverage, 129,
33579 /* 92397 */ GIR_EraseRootFromParent_Done,
33580 /* 92398 */ // Label 2844: @92398
33581 /* 92398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2845*/ GIMT_Encode4(92455), GIMT_Encode2(GIFBS_IsARM), // Rule ID 130 //
33582 /* 92405 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
33583 /* 92410 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33584 /* 92413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33585 /* 92416 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33586 /* 92419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33587 /* 92423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33588 /* 92427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33589 /* 92431 */ // (intrinsic_w_chain:{ *:[i32] } 4192:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33590 /* 92431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16),
33591 /* 92434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33592 /* 92436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33593 /* 92438 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33594 /* 92440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33595 /* 92443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33596 /* 92449 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33597 /* 92453 */ GIR_RootConstrainSelectedInstOperands,
33598 /* 92454 */ // GIR_Coverage, 130,
33599 /* 92454 */ GIR_EraseRootFromParent_Done,
33600 /* 92455 */ // Label 2845: @92455
33601 /* 92455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2846*/ GIMT_Encode4(92512), GIMT_Encode2(GIFBS_IsARM), // Rule ID 131 //
33602 /* 92462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
33603 /* 92467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33604 /* 92470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33605 /* 92473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33606 /* 92476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33607 /* 92480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33608 /* 92484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33609 /* 92488 */ // (intrinsic_w_chain:{ *:[i32] } 4193:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33610 /* 92488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8),
33611 /* 92491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33612 /* 92493 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33613 /* 92495 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33614 /* 92497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33615 /* 92500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33616 /* 92506 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33617 /* 92510 */ GIR_RootConstrainSelectedInstOperands,
33618 /* 92511 */ // GIR_Coverage, 131,
33619 /* 92511 */ GIR_EraseRootFromParent_Done,
33620 /* 92512 */ // Label 2846: @92512
33621 /* 92512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2847*/ GIMT_Encode4(92569), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 430 //
33622 /* 92519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
33623 /* 92524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33624 /* 92527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33625 /* 92530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33626 /* 92533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33627 /* 92537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33628 /* 92541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33629 /* 92545 */ // (intrinsic_w_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
33630 /* 92545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL),
33631 /* 92548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33632 /* 92550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33633 /* 92552 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33634 /* 92554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33635 /* 92557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33636 /* 92563 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33637 /* 92567 */ GIR_RootConstrainSelectedInstOperands,
33638 /* 92568 */ // GIR_Coverage, 430,
33639 /* 92568 */ GIR_EraseRootFromParent_Done,
33640 /* 92569 */ // Label 2847: @92569
33641 /* 92569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2848*/ GIMT_Encode4(92626), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 443 //
33642 /* 92576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
33643 /* 92581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33644 /* 92584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33645 /* 92587 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33646 /* 92590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33647 /* 92594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33648 /* 92598 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33649 /* 92602 */ // (intrinsic_w_chain:{ *:[i32] } 4122:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33650 /* 92602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX),
33651 /* 92605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33652 /* 92607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33653 /* 92609 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33654 /* 92611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33655 /* 92614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33656 /* 92620 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33657 /* 92624 */ GIR_RootConstrainSelectedInstOperands,
33658 /* 92625 */ // GIR_Coverage, 443,
33659 /* 92625 */ GIR_EraseRootFromParent_Done,
33660 /* 92626 */ // Label 2848: @92626
33661 /* 92626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2849*/ GIMT_Encode4(92683), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 444 //
33662 /* 92633 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
33663 /* 92638 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33664 /* 92641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33665 /* 92644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33666 /* 92647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33667 /* 92651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33668 /* 92655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33669 /* 92659 */ // (intrinsic_w_chain:{ *:[i32] } 4120:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33670 /* 92659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16),
33671 /* 92662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33672 /* 92664 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33673 /* 92666 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33674 /* 92668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33675 /* 92671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33676 /* 92677 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33677 /* 92681 */ GIR_RootConstrainSelectedInstOperands,
33678 /* 92682 */ // GIR_Coverage, 444,
33679 /* 92682 */ GIR_EraseRootFromParent_Done,
33680 /* 92683 */ // Label 2849: @92683
33681 /* 92683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2850*/ GIMT_Encode4(92740), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 445 //
33682 /* 92690 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
33683 /* 92695 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33684 /* 92698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33685 /* 92701 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33686 /* 92704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33687 /* 92708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33688 /* 92712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33689 /* 92716 */ // (intrinsic_w_chain:{ *:[i32] } 4121:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33690 /* 92716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8),
33691 /* 92719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33692 /* 92721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33693 /* 92723 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33694 /* 92725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33695 /* 92728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33696 /* 92734 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33697 /* 92738 */ GIR_RootConstrainSelectedInstOperands,
33698 /* 92739 */ // GIR_Coverage, 445,
33699 /* 92739 */ GIR_EraseRootFromParent_Done,
33700 /* 92740 */ // Label 2850: @92740
33701 /* 92740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2851*/ GIMT_Encode4(92797), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 446 //
33702 /* 92747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
33703 /* 92752 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33704 /* 92755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33705 /* 92758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33706 /* 92761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33707 /* 92765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33708 /* 92769 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33709 /* 92773 */ // (intrinsic_w_chain:{ *:[i32] } 4158:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33710 /* 92773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX),
33711 /* 92776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33712 /* 92778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33713 /* 92780 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33714 /* 92782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33715 /* 92785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33716 /* 92791 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33717 /* 92795 */ GIR_RootConstrainSelectedInstOperands,
33718 /* 92796 */ // GIR_Coverage, 446,
33719 /* 92796 */ GIR_EraseRootFromParent_Done,
33720 /* 92797 */ // Label 2851: @92797
33721 /* 92797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2852*/ GIMT_Encode4(92854), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 447 //
33722 /* 92804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
33723 /* 92809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33724 /* 92812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33725 /* 92815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33726 /* 92818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33727 /* 92822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33728 /* 92826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33729 /* 92830 */ // (intrinsic_w_chain:{ *:[i32] } 4159:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33730 /* 92830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16),
33731 /* 92833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33732 /* 92835 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33733 /* 92837 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33734 /* 92839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33735 /* 92842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33736 /* 92848 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33737 /* 92852 */ GIR_RootConstrainSelectedInstOperands,
33738 /* 92853 */ // GIR_Coverage, 447,
33739 /* 92853 */ GIR_EraseRootFromParent_Done,
33740 /* 92854 */ // Label 2852: @92854
33741 /* 92854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2853*/ GIMT_Encode4(92911), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 448 //
33742 /* 92861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
33743 /* 92866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33744 /* 92869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33745 /* 92872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33746 /* 92875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33747 /* 92879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33748 /* 92883 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33749 /* 92887 */ // (intrinsic_w_chain:{ *:[i32] } 4160:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33750 /* 92887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8),
33751 /* 92890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33752 /* 92892 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33753 /* 92894 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33754 /* 92896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33755 /* 92899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33756 /* 92905 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33757 /* 92909 */ GIR_RootConstrainSelectedInstOperands,
33758 /* 92910 */ // GIR_Coverage, 448,
33759 /* 92910 */ GIR_EraseRootFromParent_Done,
33760 /* 92911 */ // Label 2853: @92911
33761 /* 92911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2854*/ GIMT_Encode4(92968), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 449 //
33762 /* 92918 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
33763 /* 92923 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33764 /* 92926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33765 /* 92929 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33766 /* 92932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33767 /* 92936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33768 /* 92940 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33769 /* 92944 */ // (intrinsic_w_chain:{ *:[i32] } 4173:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33770 /* 92944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX),
33771 /* 92947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33772 /* 92949 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33773 /* 92951 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33774 /* 92953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33775 /* 92956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33776 /* 92962 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33777 /* 92966 */ GIR_RootConstrainSelectedInstOperands,
33778 /* 92967 */ // GIR_Coverage, 449,
33779 /* 92967 */ GIR_EraseRootFromParent_Done,
33780 /* 92968 */ // Label 2854: @92968
33781 /* 92968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2855*/ GIMT_Encode4(93025), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 450 //
33782 /* 92975 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
33783 /* 92980 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33784 /* 92983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33785 /* 92986 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33786 /* 92989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33787 /* 92993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33788 /* 92997 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33789 /* 93001 */ // (intrinsic_w_chain:{ *:[i32] } 4171:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33790 /* 93001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16),
33791 /* 93004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33792 /* 93006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33793 /* 93008 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33794 /* 93010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33795 /* 93013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33796 /* 93019 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33797 /* 93023 */ GIR_RootConstrainSelectedInstOperands,
33798 /* 93024 */ // GIR_Coverage, 450,
33799 /* 93024 */ GIR_EraseRootFromParent_Done,
33800 /* 93025 */ // Label 2855: @93025
33801 /* 93025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2856*/ GIMT_Encode4(93082), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 451 //
33802 /* 93032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
33803 /* 93037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33804 /* 93040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33805 /* 93043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33806 /* 93046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33807 /* 93050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33808 /* 93054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33809 /* 93058 */ // (intrinsic_w_chain:{ *:[i32] } 4172:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33810 /* 93058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8),
33811 /* 93061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33812 /* 93063 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33813 /* 93065 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33814 /* 93067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33815 /* 93070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33816 /* 93076 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33817 /* 93080 */ GIR_RootConstrainSelectedInstOperands,
33818 /* 93081 */ // GIR_Coverage, 451,
33819 /* 93081 */ GIR_EraseRootFromParent_Done,
33820 /* 93082 */ // Label 2856: @93082
33821 /* 93082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2857*/ GIMT_Encode4(93139), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 452 //
33822 /* 93089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
33823 /* 93094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33824 /* 93097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33825 /* 93100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33826 /* 93103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33827 /* 93107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33828 /* 93111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33829 /* 93115 */ // (intrinsic_w_chain:{ *:[i32] } 4191:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33830 /* 93115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX),
33831 /* 93118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33832 /* 93120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33833 /* 93122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33834 /* 93124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33835 /* 93127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33836 /* 93133 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33837 /* 93137 */ GIR_RootConstrainSelectedInstOperands,
33838 /* 93138 */ // GIR_Coverage, 452,
33839 /* 93138 */ GIR_EraseRootFromParent_Done,
33840 /* 93139 */ // Label 2857: @93139
33841 /* 93139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2858*/ GIMT_Encode4(93196), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 453 //
33842 /* 93146 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
33843 /* 93151 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33844 /* 93154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33845 /* 93157 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33846 /* 93160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33847 /* 93164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33848 /* 93168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33849 /* 93172 */ // (intrinsic_w_chain:{ *:[i32] } 4192:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33850 /* 93172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16),
33851 /* 93175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33852 /* 93177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33853 /* 93179 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33854 /* 93181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33855 /* 93184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33856 /* 93190 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33857 /* 93194 */ GIR_RootConstrainSelectedInstOperands,
33858 /* 93195 */ // GIR_Coverage, 453,
33859 /* 93195 */ GIR_EraseRootFromParent_Done,
33860 /* 93196 */ // Label 2858: @93196
33861 /* 93196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2859*/ GIMT_Encode4(93253), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 454 //
33862 /* 93203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
33863 /* 93208 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33864 /* 93211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33865 /* 93214 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33866 /* 93217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33867 /* 93221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33868 /* 93225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33869 /* 93229 */ // (intrinsic_w_chain:{ *:[i32] } 4193:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33870 /* 93229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8),
33871 /* 93232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33872 /* 93234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33873 /* 93236 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33874 /* 93238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33875 /* 93241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33876 /* 93247 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33877 /* 93251 */ GIR_RootConstrainSelectedInstOperands,
33878 /* 93252 */ // GIR_Coverage, 454,
33879 /* 93252 */ GIR_EraseRootFromParent_Done,
33880 /* 93253 */ // Label 2859: @93253
33881 /* 93253 */ GIM_Reject,
33882 /* 93254 */ // Label 2812: @93254
33883 /* 93254 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(93479),
33884 /* 93259 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
33885 /* 93262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb),
33886 /* 93267 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2863*/ GIMT_Encode4(93478),
33887 /* 93278 */ /*GILLT_v4s32*//*Label 2861*/ GIMT_Encode4(93286),
33888 /* 93282 */ /*GILLT_v2s64*//*Label 2862*/ GIMT_Encode4(93382),
33889 /* 93286 */ // Label 2861: @93286
33890 /* 93286 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(93381),
33891 /* 93291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33892 /* 93294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33893 /* 93297 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33894 /* 93300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33895 /* 93304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33896 /* 93308 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33897 /* 93312 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(93346), // Rule ID 5590 //
33898 /* 93317 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33899 /* 93321 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33900 /* 93325 */ // MIs[1] Operand 1
33901 /* 93325 */ // No operand predicates
33902 /* 93325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33903 /* 93327 */ // (intrinsic_w_chain:{ *:[v4i32] } 3969:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33904 /* 93327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
33905 /* 93330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33906 /* 93332 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33907 /* 93334 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33908 /* 93336 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33909 /* 93339 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33910 /* 93344 */ GIR_RootConstrainSelectedInstOperands,
33911 /* 93345 */ // GIR_Coverage, 5590,
33912 /* 93345 */ GIR_EraseRootFromParent_Done,
33913 /* 93346 */ // Label 2865: @93346
33914 /* 93346 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(93380), // Rule ID 5600 //
33915 /* 93351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33916 /* 93355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33917 /* 93359 */ // MIs[1] Operand 1
33918 /* 93359 */ // No operand predicates
33919 /* 93359 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33920 /* 93361 */ // (intrinsic_w_chain:{ *:[v4i32] } 3969:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33921 /* 93361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
33922 /* 93364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33923 /* 93366 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33924 /* 93368 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33925 /* 93370 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33926 /* 93373 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33927 /* 93378 */ GIR_RootConstrainSelectedInstOperands,
33928 /* 93379 */ // GIR_Coverage, 5600,
33929 /* 93379 */ GIR_EraseRootFromParent_Done,
33930 /* 93380 */ // Label 2866: @93380
33931 /* 93380 */ GIM_Reject,
33932 /* 93381 */ // Label 2864: @93381
33933 /* 93381 */ GIM_Reject,
33934 /* 93382 */ // Label 2862: @93382
33935 /* 93382 */ GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(93477),
33936 /* 93387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
33937 /* 93390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33938 /* 93393 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
33939 /* 93396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33940 /* 93400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33941 /* 93404 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33942 /* 93408 */ GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(93442), // Rule ID 5604 //
33943 /* 93413 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33944 /* 93417 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33945 /* 93421 */ // MIs[1] Operand 1
33946 /* 93421 */ // No operand predicates
33947 /* 93421 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33948 /* 93423 */ // (intrinsic_w_chain:{ *:[v2i64] } 3969:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33949 /* 93423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
33950 /* 93426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33951 /* 93428 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33952 /* 93430 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33953 /* 93432 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33954 /* 93435 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33955 /* 93440 */ GIR_RootConstrainSelectedInstOperands,
33956 /* 93441 */ // GIR_Coverage, 5604,
33957 /* 93441 */ GIR_EraseRootFromParent_Done,
33958 /* 93442 */ // Label 2868: @93442
33959 /* 93442 */ GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(93476), // Rule ID 5608 //
33960 /* 93447 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33961 /* 93451 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33962 /* 93455 */ // MIs[1] Operand 1
33963 /* 93455 */ // No operand predicates
33964 /* 93455 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33965 /* 93457 */ // (intrinsic_w_chain:{ *:[v2i64] } 3969:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33966 /* 93457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
33967 /* 93460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33968 /* 93462 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33969 /* 93464 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33970 /* 93466 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33971 /* 93469 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33972 /* 93474 */ GIR_RootConstrainSelectedInstOperands,
33973 /* 93475 */ // GIR_Coverage, 5608,
33974 /* 93475 */ GIR_EraseRootFromParent_Done,
33975 /* 93476 */ // Label 2869: @93476
33976 /* 93476 */ GIM_Reject,
33977 /* 93477 */ // Label 2867: @93477
33978 /* 93477 */ GIM_Reject,
33979 /* 93478 */ // Label 2863: @93478
33980 /* 93478 */ GIM_Reject,
33981 /* 93479 */ // Label 2860: @93479
33982 /* 93479 */ GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(94315),
33983 /* 93484 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
33984 /* 93487 */ GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(94071),
33985 /* 93492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
33986 /* 93497 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2876*/ GIMT_Encode4(94070),
33987 /* 93508 */ /*GILLT_v16s8*//*Label 2872*/ GIMT_Encode4(93532), GIMT_Encode4(0),
33988 /* 93516 */ /*GILLT_v8s16*//*Label 2873*/ GIMT_Encode4(93586), GIMT_Encode4(0),
33989 /* 93524 */ /*GILLT_v4s32*//*Label 2874*/ GIMT_Encode4(93762),
33990 /* 93528 */ /*GILLT_v2s64*//*Label 2875*/ GIMT_Encode4(93986),
33991 /* 93532 */ // Label 2872: @93532
33992 /* 93532 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(93585), // Rule ID 5482 //
33993 /* 93537 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33994 /* 93540 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33995 /* 93543 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33996 /* 93546 */ // MIs[0] base
33997 /* 93546 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
33998 /* 93550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33999 /* 93554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34000 /* 93558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34001 /* 93562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34002 /* 93566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34003 /* 93570 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
34004 /* 93570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq),
34005 /* 93573 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34006 /* 93575 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34007 /* 93577 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34008 /* 93579 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34009 /* 93583 */ GIR_RootConstrainSelectedInstOperands,
34010 /* 93584 */ // GIR_Coverage, 5482,
34011 /* 93584 */ GIR_EraseRootFromParent_Done,
34012 /* 93585 */ // Label 2877: @93585
34013 /* 93585 */ GIM_Reject,
34014 /* 93586 */ // Label 2873: @93586
34015 /* 93586 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(93761),
34016 /* 93591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34017 /* 93594 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34018 /* 93597 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34019 /* 93600 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
34020 /* 93604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34021 /* 93608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34022 /* 93612 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34023 /* 93616 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(93674),
34024 /* 93621 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34025 /* 93625 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(93649), // Rule ID 5478 //
34026 /* 93630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34027 /* 93634 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34028 /* 93634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
34029 /* 93637 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34030 /* 93639 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34031 /* 93641 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34032 /* 93643 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34033 /* 93647 */ GIR_RootConstrainSelectedInstOperands,
34034 /* 93648 */ // GIR_Coverage, 5478,
34035 /* 93648 */ GIR_EraseRootFromParent_Done,
34036 /* 93649 */ // Label 2880: @93649
34037 /* 93649 */ GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(93673), // Rule ID 5479 //
34038 /* 93654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34039 /* 93658 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34040 /* 93658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
34041 /* 93661 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34042 /* 93663 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34043 /* 93665 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34044 /* 93667 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34045 /* 93671 */ GIR_RootConstrainSelectedInstOperands,
34046 /* 93672 */ // GIR_Coverage, 5479,
34047 /* 93672 */ GIR_EraseRootFromParent_Done,
34048 /* 93673 */ // Label 2881: @93673
34049 /* 93673 */ GIM_Reject,
34050 /* 93674 */ // Label 2879: @93674
34051 /* 93674 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(93702), // Rule ID 5562 //
34052 /* 93679 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34053 /* 93683 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34054 /* 93687 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34055 /* 93687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq),
34056 /* 93690 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34057 /* 93692 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34058 /* 93694 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34059 /* 93696 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34060 /* 93700 */ GIR_RootConstrainSelectedInstOperands,
34061 /* 93701 */ // GIR_Coverage, 5562,
34062 /* 93701 */ GIR_EraseRootFromParent_Done,
34063 /* 93702 */ // Label 2882: @93702
34064 /* 93702 */ GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(93760),
34065 /* 93707 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34066 /* 93711 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(93735), // Rule ID 5566 //
34067 /* 93716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34068 /* 93720 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34069 /* 93720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
34070 /* 93723 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34071 /* 93725 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34072 /* 93727 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34073 /* 93729 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34074 /* 93733 */ GIR_RootConstrainSelectedInstOperands,
34075 /* 93734 */ // GIR_Coverage, 5566,
34076 /* 93734 */ GIR_EraseRootFromParent_Done,
34077 /* 93735 */ // Label 2884: @93735
34078 /* 93735 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(93759), // Rule ID 5567 //
34079 /* 93740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34080 /* 93744 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34081 /* 93744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
34082 /* 93747 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34083 /* 93749 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34084 /* 93751 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34085 /* 93753 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34086 /* 93757 */ GIR_RootConstrainSelectedInstOperands,
34087 /* 93758 */ // GIR_Coverage, 5567,
34088 /* 93758 */ GIR_EraseRootFromParent_Done,
34089 /* 93759 */ // Label 2885: @93759
34090 /* 93759 */ GIM_Reject,
34091 /* 93760 */ // Label 2883: @93760
34092 /* 93760 */ GIM_Reject,
34093 /* 93761 */ // Label 2878: @93761
34094 /* 93761 */ GIM_Reject,
34095 /* 93762 */ // Label 2874: @93762
34096 /* 93762 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(93985),
34097 /* 93767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34098 /* 93770 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34099 /* 93773 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34100 /* 93776 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
34101 /* 93780 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34102 /* 93784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34103 /* 93788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34104 /* 93792 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(93820), // Rule ID 5564 //
34105 /* 93797 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34106 /* 93801 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34107 /* 93805 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34108 /* 93805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq),
34109 /* 93808 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34110 /* 93810 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34111 /* 93812 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34112 /* 93814 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34113 /* 93818 */ GIR_RootConstrainSelectedInstOperands,
34114 /* 93819 */ // GIR_Coverage, 5564,
34115 /* 93819 */ GIR_EraseRootFromParent_Done,
34116 /* 93820 */ // Label 2887: @93820
34117 /* 93820 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(93878),
34118 /* 93825 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34119 /* 93829 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(93853), // Rule ID 5570 //
34120 /* 93834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34121 /* 93838 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34122 /* 93838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u),
34123 /* 93841 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34124 /* 93843 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34125 /* 93845 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34126 /* 93847 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34127 /* 93851 */ GIR_RootConstrainSelectedInstOperands,
34128 /* 93852 */ // GIR_Coverage, 5570,
34129 /* 93852 */ GIR_EraseRootFromParent_Done,
34130 /* 93853 */ // Label 2889: @93853
34131 /* 93853 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(93877), // Rule ID 5571 //
34132 /* 93858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34133 /* 93862 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34134 /* 93862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq),
34135 /* 93865 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34136 /* 93867 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34137 /* 93869 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34138 /* 93871 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34139 /* 93875 */ GIR_RootConstrainSelectedInstOperands,
34140 /* 93876 */ // GIR_Coverage, 5571,
34141 /* 93876 */ GIR_EraseRootFromParent_Done,
34142 /* 93877 */ // Label 2890: @93877
34143 /* 93877 */ GIM_Reject,
34144 /* 93878 */ // Label 2888: @93878
34145 /* 93878 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(93984),
34146 /* 93883 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
34147 /* 93887 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(93911), // Rule ID 5574 //
34148 /* 93892 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34149 /* 93896 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34150 /* 93896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
34151 /* 93899 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34152 /* 93901 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34153 /* 93903 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34154 /* 93905 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34155 /* 93909 */ GIR_RootConstrainSelectedInstOperands,
34156 /* 93910 */ // GIR_Coverage, 5574,
34157 /* 93910 */ GIR_EraseRootFromParent_Done,
34158 /* 93911 */ // Label 2892: @93911
34159 /* 93911 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(93935), // Rule ID 5575 //
34160 /* 93916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34161 /* 93920 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34162 /* 93920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
34163 /* 93923 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34164 /* 93925 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34165 /* 93927 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34166 /* 93929 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34167 /* 93933 */ GIR_RootConstrainSelectedInstOperands,
34168 /* 93934 */ // GIR_Coverage, 5575,
34169 /* 93934 */ GIR_EraseRootFromParent_Done,
34170 /* 93935 */ // Label 2893: @93935
34171 /* 93935 */ GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(93959), // Rule ID 5578 //
34172 /* 93940 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34173 /* 93944 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34174 /* 93944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
34175 /* 93947 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34176 /* 93949 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34177 /* 93951 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34178 /* 93953 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34179 /* 93957 */ GIR_RootConstrainSelectedInstOperands,
34180 /* 93958 */ // GIR_Coverage, 5578,
34181 /* 93958 */ GIR_EraseRootFromParent_Done,
34182 /* 93959 */ // Label 2894: @93959
34183 /* 93959 */ GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(93983), // Rule ID 5579 //
34184 /* 93964 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34185 /* 93968 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34186 /* 93968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
34187 /* 93971 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34188 /* 93973 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34189 /* 93975 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34190 /* 93977 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34191 /* 93981 */ GIR_RootConstrainSelectedInstOperands,
34192 /* 93982 */ // GIR_Coverage, 5579,
34193 /* 93982 */ GIR_EraseRootFromParent_Done,
34194 /* 93983 */ // Label 2895: @93983
34195 /* 93983 */ GIM_Reject,
34196 /* 93984 */ // Label 2891: @93984
34197 /* 93984 */ GIM_Reject,
34198 /* 93985 */ // Label 2886: @93985
34199 /* 93985 */ GIM_Reject,
34200 /* 93986 */ // Label 2875: @93986
34201 /* 93986 */ GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(94069),
34202 /* 93991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
34203 /* 93994 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34204 /* 93997 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34205 /* 94000 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
34206 /* 94004 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34207 /* 94008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34208 /* 94012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34209 /* 94016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
34210 /* 94020 */ GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(94044), // Rule ID 5582 //
34211 /* 94025 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34212 /* 94029 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34213 /* 94029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u),
34214 /* 94032 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34215 /* 94034 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34216 /* 94036 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34217 /* 94038 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34218 /* 94042 */ GIR_RootConstrainSelectedInstOperands,
34219 /* 94043 */ // GIR_Coverage, 5582,
34220 /* 94043 */ GIR_EraseRootFromParent_Done,
34221 /* 94044 */ // Label 2897: @94044
34222 /* 94044 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(94068), // Rule ID 5583 //
34223 /* 94049 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
34224 /* 94053 */ // (intrinsic_void 3971:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34225 /* 94053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq),
34226 /* 94056 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34227 /* 94058 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34228 /* 94060 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34229 /* 94062 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34230 /* 94066 */ GIR_RootConstrainSelectedInstOperands,
34231 /* 94067 */ // GIR_Coverage, 5583,
34232 /* 94067 */ GIR_EraseRootFromParent_Done,
34233 /* 94068 */ // Label 2898: @94068
34234 /* 94068 */ GIM_Reject,
34235 /* 94069 */ // Label 2896: @94069
34236 /* 94069 */ GIM_Reject,
34237 /* 94070 */ // Label 2876: @94070
34238 /* 94070 */ GIM_Reject,
34239 /* 94071 */ // Label 2871: @94071
34240 /* 94071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2899*/ GIMT_Encode4(94134), GIMT_Encode2(GIFBS_IsARM), // Rule ID 257 //
34241 /* 94078 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
34242 /* 94083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34243 /* 94086 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34244 /* 94089 */ // MIs[0] cop
34245 /* 94089 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34246 /* 94092 */ // MIs[0] opc1
34247 /* 94092 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34248 /* 94095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34249 /* 94099 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34250 /* 94103 */ // MIs[0] CRm
34251 /* 94103 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34252 /* 94106 */ // (intrinsic_void 3756:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34253 /* 94106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR),
34254 /* 94109 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34255 /* 94111 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34256 /* 94113 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34257 /* 94115 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34258 /* 94117 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34259 /* 94119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34260 /* 94122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34261 /* 94128 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34262 /* 94132 */ GIR_RootConstrainSelectedInstOperands,
34263 /* 94133 */ // GIR_Coverage, 257,
34264 /* 94133 */ GIR_EraseRootFromParent_Done,
34265 /* 94134 */ // Label 2899: @94134
34266 /* 94134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2900*/ GIMT_Encode4(94188), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 258 //
34267 /* 94141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
34268 /* 94146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34269 /* 94149 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34270 /* 94152 */ // MIs[0] cop
34271 /* 94152 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34272 /* 94155 */ // MIs[0] opc1
34273 /* 94155 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34274 /* 94158 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34275 /* 94162 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34276 /* 94166 */ // MIs[0] CRm
34277 /* 94166 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34278 /* 94169 */ // (intrinsic_void 3757:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34279 /* 94169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2),
34280 /* 94172 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34281 /* 94174 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34282 /* 94176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34283 /* 94178 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34284 /* 94180 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34285 /* 94182 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34286 /* 94186 */ GIR_RootConstrainSelectedInstOperands,
34287 /* 94187 */ // GIR_Coverage, 258,
34288 /* 94187 */ GIR_EraseRootFromParent_Done,
34289 /* 94188 */ // Label 2900: @94188
34290 /* 94188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2901*/ GIMT_Encode4(94251), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 595 //
34291 /* 94195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
34292 /* 94200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34293 /* 94203 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34294 /* 94206 */ // MIs[0] cop
34295 /* 94206 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34296 /* 94209 */ // MIs[0] opc1
34297 /* 94209 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34298 /* 94212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34299 /* 94216 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34300 /* 94220 */ // MIs[0] CRm
34301 /* 94220 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34302 /* 94223 */ // (intrinsic_void 3756:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34303 /* 94223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR),
34304 /* 94226 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34305 /* 94228 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34306 /* 94230 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34307 /* 94232 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34308 /* 94234 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34309 /* 94236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34310 /* 94239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34311 /* 94245 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34312 /* 94249 */ GIR_RootConstrainSelectedInstOperands,
34313 /* 94250 */ // GIR_Coverage, 595,
34314 /* 94250 */ GIR_EraseRootFromParent_Done,
34315 /* 94251 */ // Label 2901: @94251
34316 /* 94251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2902*/ GIMT_Encode4(94314), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 596 //
34317 /* 94258 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
34318 /* 94263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34319 /* 94266 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34320 /* 94269 */ // MIs[0] cop
34321 /* 94269 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34322 /* 94272 */ // MIs[0] opc1
34323 /* 94272 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34324 /* 94275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34325 /* 94279 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34326 /* 94283 */ // MIs[0] CRm
34327 /* 94283 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34328 /* 94286 */ // (intrinsic_void 3757:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34329 /* 94286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2),
34330 /* 94289 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34331 /* 94291 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34332 /* 94293 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34333 /* 94295 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34334 /* 94297 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34335 /* 94299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34336 /* 94302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34337 /* 94308 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34338 /* 94312 */ GIR_RootConstrainSelectedInstOperands,
34339 /* 94313 */ // GIR_Coverage, 596,
34340 /* 94313 */ GIR_EraseRootFromParent_Done,
34341 /* 94314 */ // Label 2902: @94314
34342 /* 94314 */ GIM_Reject,
34343 /* 94315 */ // Label 2870: @94315
34344 /* 94315 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(96220),
34345 /* 94320 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
34346 /* 94323 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2904*/ GIMT_Encode4(94383), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 245 //
34347 /* 94330 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
34348 /* 94335 */ // MIs[0] cop
34349 /* 94335 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34350 /* 94338 */ // MIs[0] opc1
34351 /* 94338 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34352 /* 94341 */ // MIs[0] CRd
34353 /* 94341 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34354 /* 94344 */ // MIs[0] CRn
34355 /* 94344 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34356 /* 94347 */ // MIs[0] CRm
34357 /* 94347 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34358 /* 94350 */ // MIs[0] opc2
34359 /* 94350 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34360 /* 94353 */ // (intrinsic_void 3724:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34361 /* 94353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP),
34362 /* 94356 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34363 /* 94358 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34364 /* 94360 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34365 /* 94362 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34366 /* 94364 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34367 /* 94366 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34368 /* 94368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34369 /* 94371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34370 /* 94377 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34371 /* 94381 */ GIR_RootConstrainSelectedInstOperands,
34372 /* 94382 */ // GIR_Coverage, 245,
34373 /* 94382 */ GIR_EraseRootFromParent_Done,
34374 /* 94383 */ // Label 2904: @94383
34375 /* 94383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2905*/ GIMT_Encode4(94434), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 246 //
34376 /* 94390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
34377 /* 94395 */ // MIs[0] cop
34378 /* 94395 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34379 /* 94398 */ // MIs[0] opc1
34380 /* 94398 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34381 /* 94401 */ // MIs[0] CRd
34382 /* 94401 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34383 /* 94404 */ // MIs[0] CRn
34384 /* 94404 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34385 /* 94407 */ // MIs[0] CRm
34386 /* 94407 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34387 /* 94410 */ // MIs[0] opc2
34388 /* 94410 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34389 /* 94413 */ // (intrinsic_void 3725:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34390 /* 94413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2),
34391 /* 94416 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34392 /* 94418 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34393 /* 94420 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34394 /* 94422 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34395 /* 94424 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34396 /* 94426 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34397 /* 94428 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34398 /* 94432 */ GIR_RootConstrainSelectedInstOperands,
34399 /* 94433 */ // GIR_Coverage, 246,
34400 /* 94433 */ GIR_EraseRootFromParent_Done,
34401 /* 94434 */ // Label 2905: @94434
34402 /* 94434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2906*/ GIMT_Encode4(94494), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 597 //
34403 /* 94441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
34404 /* 94446 */ // MIs[0] cop
34405 /* 94446 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34406 /* 94449 */ // MIs[0] opc1
34407 /* 94449 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34408 /* 94452 */ // MIs[0] CRd
34409 /* 94452 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34410 /* 94455 */ // MIs[0] CRn
34411 /* 94455 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34412 /* 94458 */ // MIs[0] CRm
34413 /* 94458 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34414 /* 94461 */ // MIs[0] opc2
34415 /* 94461 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34416 /* 94464 */ // (intrinsic_void 3724:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34417 /* 94464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP),
34418 /* 94467 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34419 /* 94469 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34420 /* 94471 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34421 /* 94473 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34422 /* 94475 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34423 /* 94477 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34424 /* 94479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34425 /* 94482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34426 /* 94488 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34427 /* 94492 */ GIR_RootConstrainSelectedInstOperands,
34428 /* 94493 */ // GIR_Coverage, 597,
34429 /* 94493 */ GIR_EraseRootFromParent_Done,
34430 /* 94494 */ // Label 2906: @94494
34431 /* 94494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2907*/ GIMT_Encode4(94554), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 598 //
34432 /* 94501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
34433 /* 94506 */ // MIs[0] cop
34434 /* 94506 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34435 /* 94509 */ // MIs[0] opc1
34436 /* 94509 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34437 /* 94512 */ // MIs[0] CRd
34438 /* 94512 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34439 /* 94515 */ // MIs[0] CRn
34440 /* 94515 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34441 /* 94518 */ // MIs[0] CRm
34442 /* 94518 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34443 /* 94521 */ // MIs[0] opc2
34444 /* 94521 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34445 /* 94524 */ // (intrinsic_void 3725:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34446 /* 94524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2),
34447 /* 94527 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34448 /* 94529 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34449 /* 94531 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34450 /* 94533 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34451 /* 94535 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34452 /* 94537 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34453 /* 94539 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34454 /* 94542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34455 /* 94548 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34456 /* 94552 */ GIR_RootConstrainSelectedInstOperands,
34457 /* 94553 */ // GIR_Coverage, 598,
34458 /* 94553 */ GIR_EraseRootFromParent_Done,
34459 /* 94554 */ // Label 2907: @94554
34460 /* 94554 */ GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(95972),
34461 /* 94559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
34462 /* 94564 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2913*/ GIMT_Encode4(95971),
34463 /* 94575 */ /*GILLT_v16s8*//*Label 2909*/ GIMT_Encode4(94599), GIMT_Encode4(0),
34464 /* 94583 */ /*GILLT_v8s16*//*Label 2910*/ GIMT_Encode4(94690), GIMT_Encode4(0),
34465 /* 94591 */ /*GILLT_v4s32*//*Label 2911*/ GIMT_Encode4(95143),
34466 /* 94595 */ /*GILLT_v2s64*//*Label 2912*/ GIMT_Encode4(95708),
34467 /* 94599 */ // Label 2909: @94599
34468 /* 94599 */ GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(94689),
34469 /* 94604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
34470 /* 94607 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34471 /* 94610 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34472 /* 94613 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34473 /* 94616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34474 /* 94620 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34475 /* 94624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34476 /* 94628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34477 /* 94632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34478 /* 94636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34479 /* 94640 */ GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(94664), // Rule ID 5476 //
34480 /* 94645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34481 /* 94649 */ // (intrinsic_w_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
34482 /* 94649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
34483 /* 94652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34484 /* 94654 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34485 /* 94656 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34486 /* 94658 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34487 /* 94662 */ GIR_RootConstrainSelectedInstOperands,
34488 /* 94663 */ // GIR_Coverage, 5476,
34489 /* 94663 */ GIR_EraseRootFromParent_Done,
34490 /* 94664 */ // Label 2915: @94664
34491 /* 94664 */ GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(94688), // Rule ID 5484 //
34492 /* 94669 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34493 /* 94673 */ // (intrinsic_w_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
34494 /* 94673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
34495 /* 94676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34496 /* 94678 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34497 /* 94680 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34498 /* 94682 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34499 /* 94686 */ GIR_RootConstrainSelectedInstOperands,
34500 /* 94687 */ // GIR_Coverage, 5484,
34501 /* 94687 */ GIR_EraseRootFromParent_Done,
34502 /* 94688 */ // Label 2916: @94688
34503 /* 94688 */ GIM_Reject,
34504 /* 94689 */ // Label 2914: @94689
34505 /* 94689 */ GIM_Reject,
34506 /* 94690 */ // Label 2910: @94690
34507 /* 94690 */ GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(95142),
34508 /* 94695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34509 /* 94698 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34510 /* 94701 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34511 /* 94704 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34512 /* 94707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34513 /* 94711 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34514 /* 94715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34515 /* 94719 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34516 /* 94723 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(94789),
34517 /* 94728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34518 /* 94732 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(94760), // Rule ID 5472 //
34519 /* 94737 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34520 /* 94741 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34521 /* 94745 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34522 /* 94745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34523 /* 94748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34524 /* 94750 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34525 /* 94752 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34526 /* 94754 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34527 /* 94758 */ GIR_RootConstrainSelectedInstOperands,
34528 /* 94759 */ // GIR_Coverage, 5472,
34529 /* 94759 */ GIR_EraseRootFromParent_Done,
34530 /* 94760 */ // Label 2919: @94760
34531 /* 94760 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(94788), // Rule ID 5473 //
34532 /* 94765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34533 /* 94769 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34534 /* 94773 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34535 /* 94773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34536 /* 94776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34537 /* 94778 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34538 /* 94780 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34539 /* 94782 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34540 /* 94786 */ GIR_RootConstrainSelectedInstOperands,
34541 /* 94787 */ // GIR_Coverage, 5473,
34542 /* 94787 */ GIR_EraseRootFromParent_Done,
34543 /* 94788 */ // Label 2920: @94788
34544 /* 94788 */ GIM_Reject,
34545 /* 94789 */ // Label 2918: @94789
34546 /* 94789 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(94851),
34547 /* 94794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34548 /* 94798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34549 /* 94802 */ GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(94826), // Rule ID 5486 //
34550 /* 94807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34551 /* 94811 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34552 /* 94811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq),
34553 /* 94814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34554 /* 94816 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34555 /* 94818 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34556 /* 94820 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34557 /* 94824 */ GIR_RootConstrainSelectedInstOperands,
34558 /* 94825 */ // GIR_Coverage, 5486,
34559 /* 94825 */ GIR_EraseRootFromParent_Done,
34560 /* 94826 */ // Label 2922: @94826
34561 /* 94826 */ GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(94850), // Rule ID 5488 //
34562 /* 94831 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34563 /* 94835 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34564 /* 94835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq),
34565 /* 94838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34566 /* 94840 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34567 /* 94842 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34568 /* 94844 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34569 /* 94848 */ GIR_RootConstrainSelectedInstOperands,
34570 /* 94849 */ // GIR_Coverage, 5488,
34571 /* 94849 */ GIR_EraseRootFromParent_Done,
34572 /* 94850 */ // Label 2923: @94850
34573 /* 94850 */ GIM_Reject,
34574 /* 94851 */ // Label 2921: @94851
34575 /* 94851 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(95141),
34576 /* 94856 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34577 /* 94860 */ GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(94888), // Rule ID 5494 //
34578 /* 94865 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34579 /* 94869 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34580 /* 94873 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34581 /* 94873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34582 /* 94876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34583 /* 94878 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34584 /* 94880 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34585 /* 94882 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34586 /* 94886 */ GIR_RootConstrainSelectedInstOperands,
34587 /* 94887 */ // GIR_Coverage, 5494,
34588 /* 94887 */ GIR_EraseRootFromParent_Done,
34589 /* 94888 */ // Label 2925: @94888
34590 /* 94888 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(94916), // Rule ID 5495 //
34591 /* 94893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34592 /* 94897 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34593 /* 94901 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34594 /* 94901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34595 /* 94904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34596 /* 94906 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34597 /* 94908 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34598 /* 94910 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34599 /* 94914 */ GIR_RootConstrainSelectedInstOperands,
34600 /* 94915 */ // GIR_Coverage, 5495,
34601 /* 94915 */ GIR_EraseRootFromParent_Done,
34602 /* 94916 */ // Label 2926: @94916
34603 /* 94916 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(94944), // Rule ID 5498 //
34604 /* 94921 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34605 /* 94925 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34606 /* 94929 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34607 /* 94929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34608 /* 94932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34609 /* 94934 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34610 /* 94936 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34611 /* 94938 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34612 /* 94942 */ GIR_RootConstrainSelectedInstOperands,
34613 /* 94943 */ // GIR_Coverage, 5498,
34614 /* 94943 */ GIR_EraseRootFromParent_Done,
34615 /* 94944 */ // Label 2927: @94944
34616 /* 94944 */ GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(94972), // Rule ID 5499 //
34617 /* 94949 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34618 /* 94953 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34619 /* 94957 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34620 /* 94957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34621 /* 94960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34622 /* 94962 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34623 /* 94964 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34624 /* 94966 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34625 /* 94970 */ GIR_RootConstrainSelectedInstOperands,
34626 /* 94971 */ // GIR_Coverage, 5499,
34627 /* 94971 */ GIR_EraseRootFromParent_Done,
34628 /* 94972 */ // Label 2928: @94972
34629 /* 94972 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(95000), // Rule ID 5502 //
34630 /* 94977 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34631 /* 94981 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34632 /* 94985 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34633 /* 94985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34634 /* 94988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34635 /* 94990 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34636 /* 94992 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34637 /* 94994 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34638 /* 94998 */ GIR_RootConstrainSelectedInstOperands,
34639 /* 94999 */ // GIR_Coverage, 5502,
34640 /* 94999 */ GIR_EraseRootFromParent_Done,
34641 /* 95000 */ // Label 2929: @95000
34642 /* 95000 */ GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(95028), // Rule ID 5503 //
34643 /* 95005 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34644 /* 95009 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34645 /* 95013 */ // (intrinsic_w_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34646 /* 95013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34647 /* 95016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34648 /* 95018 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34649 /* 95020 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34650 /* 95022 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34651 /* 95026 */ GIR_RootConstrainSelectedInstOperands,
34652 /* 95027 */ // GIR_Coverage, 5503,
34653 /* 95027 */ GIR_EraseRootFromParent_Done,
34654 /* 95028 */ // Label 2930: @95028
34655 /* 95028 */ GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(95056), // Rule ID 5506 //
34656 /* 95033 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34657 /* 95037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34658 /* 95041 */ // (intrinsic_w_chain:{ *:[v8f16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34659 /* 95041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34660 /* 95044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34661 /* 95046 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34662 /* 95048 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34663 /* 95050 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34664 /* 95054 */ GIR_RootConstrainSelectedInstOperands,
34665 /* 95055 */ // GIR_Coverage, 5506,
34666 /* 95055 */ GIR_EraseRootFromParent_Done,
34667 /* 95056 */ // Label 2931: @95056
34668 /* 95056 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(95084), // Rule ID 5507 //
34669 /* 95061 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34670 /* 95065 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34671 /* 95069 */ // (intrinsic_w_chain:{ *:[v8f16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34672 /* 95069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34673 /* 95072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34674 /* 95074 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34675 /* 95076 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34676 /* 95078 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34677 /* 95082 */ GIR_RootConstrainSelectedInstOperands,
34678 /* 95083 */ // GIR_Coverage, 5507,
34679 /* 95083 */ GIR_EraseRootFromParent_Done,
34680 /* 95084 */ // Label 2932: @95084
34681 /* 95084 */ GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(95112), // Rule ID 5510 //
34682 /* 95089 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34683 /* 95093 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34684 /* 95097 */ // (intrinsic_w_chain:{ *:[v8f16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34685 /* 95097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34686 /* 95100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34687 /* 95102 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34688 /* 95104 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34689 /* 95106 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34690 /* 95110 */ GIR_RootConstrainSelectedInstOperands,
34691 /* 95111 */ // GIR_Coverage, 5510,
34692 /* 95111 */ GIR_EraseRootFromParent_Done,
34693 /* 95112 */ // Label 2933: @95112
34694 /* 95112 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(95140), // Rule ID 5511 //
34695 /* 95117 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34696 /* 95121 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34697 /* 95125 */ // (intrinsic_w_chain:{ *:[v8f16] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34698 /* 95125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34699 /* 95128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34700 /* 95130 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34701 /* 95132 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34702 /* 95134 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34703 /* 95138 */ GIR_RootConstrainSelectedInstOperands,
34704 /* 95139 */ // GIR_Coverage, 5511,
34705 /* 95139 */ GIR_EraseRootFromParent_Done,
34706 /* 95140 */ // Label 2934: @95140
34707 /* 95140 */ GIM_Reject,
34708 /* 95141 */ // Label 2924: @95141
34709 /* 95141 */ GIM_Reject,
34710 /* 95142 */ // Label 2917: @95142
34711 /* 95142 */ GIM_Reject,
34712 /* 95143 */ // Label 2911: @95143
34713 /* 95143 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(95707),
34714 /* 95148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34715 /* 95151 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34716 /* 95154 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34717 /* 95157 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34718 /* 95160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34719 /* 95164 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34720 /* 95168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34721 /* 95172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34722 /* 95176 */ GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(95238),
34723 /* 95181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34724 /* 95185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34725 /* 95189 */ GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(95213), // Rule ID 5490 //
34726 /* 95194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34727 /* 95198 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34728 /* 95198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq),
34729 /* 95201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34730 /* 95203 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34731 /* 95205 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34732 /* 95207 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34733 /* 95211 */ GIR_RootConstrainSelectedInstOperands,
34734 /* 95212 */ // GIR_Coverage, 5490,
34735 /* 95212 */ GIR_EraseRootFromParent_Done,
34736 /* 95213 */ // Label 2937: @95213
34737 /* 95213 */ GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(95237), // Rule ID 5492 //
34738 /* 95218 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34739 /* 95222 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34740 /* 95222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq),
34741 /* 95225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34742 /* 95227 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34743 /* 95229 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34744 /* 95231 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34745 /* 95235 */ GIR_RootConstrainSelectedInstOperands,
34746 /* 95236 */ // GIR_Coverage, 5492,
34747 /* 95236 */ GIR_EraseRootFromParent_Done,
34748 /* 95237 */ // Label 2938: @95237
34749 /* 95237 */ GIM_Reject,
34750 /* 95238 */ // Label 2936: @95238
34751 /* 95238 */ GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(95360),
34752 /* 95243 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34753 /* 95247 */ GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(95275), // Rule ID 5514 //
34754 /* 95252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34755 /* 95256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34756 /* 95260 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34757 /* 95260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u),
34758 /* 95263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34759 /* 95265 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34760 /* 95267 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34761 /* 95269 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34762 /* 95273 */ GIR_RootConstrainSelectedInstOperands,
34763 /* 95274 */ // GIR_Coverage, 5514,
34764 /* 95274 */ GIR_EraseRootFromParent_Done,
34765 /* 95275 */ // Label 2940: @95275
34766 /* 95275 */ GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(95303), // Rule ID 5515 //
34767 /* 95280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34768 /* 95284 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34769 /* 95288 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34770 /* 95288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq),
34771 /* 95291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34772 /* 95293 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34773 /* 95295 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34774 /* 95297 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34775 /* 95301 */ GIR_RootConstrainSelectedInstOperands,
34776 /* 95302 */ // GIR_Coverage, 5515,
34777 /* 95302 */ GIR_EraseRootFromParent_Done,
34778 /* 95303 */ // Label 2941: @95303
34779 /* 95303 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(95331), // Rule ID 5518 //
34780 /* 95308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34781 /* 95312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34782 /* 95316 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34783 /* 95316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u),
34784 /* 95319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34785 /* 95321 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34786 /* 95323 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34787 /* 95325 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34788 /* 95329 */ GIR_RootConstrainSelectedInstOperands,
34789 /* 95330 */ // GIR_Coverage, 5518,
34790 /* 95330 */ GIR_EraseRootFromParent_Done,
34791 /* 95331 */ // Label 2942: @95331
34792 /* 95331 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(95359), // Rule ID 5519 //
34793 /* 95336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34794 /* 95340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34795 /* 95344 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34796 /* 95344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq),
34797 /* 95347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34798 /* 95349 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34799 /* 95351 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34800 /* 95353 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34801 /* 95357 */ GIR_RootConstrainSelectedInstOperands,
34802 /* 95358 */ // GIR_Coverage, 5519,
34803 /* 95358 */ GIR_EraseRootFromParent_Done,
34804 /* 95359 */ // Label 2943: @95359
34805 /* 95359 */ GIM_Reject,
34806 /* 95360 */ // Label 2939: @95360
34807 /* 95360 */ GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(95706),
34808 /* 95365 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
34809 /* 95369 */ GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(95397), // Rule ID 5522 //
34810 /* 95374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34811 /* 95378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34812 /* 95382 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34813 /* 95382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34814 /* 95385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34815 /* 95387 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34816 /* 95389 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34817 /* 95391 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34818 /* 95395 */ GIR_RootConstrainSelectedInstOperands,
34819 /* 95396 */ // GIR_Coverage, 5522,
34820 /* 95396 */ GIR_EraseRootFromParent_Done,
34821 /* 95397 */ // Label 2945: @95397
34822 /* 95397 */ GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(95425), // Rule ID 5523 //
34823 /* 95402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34824 /* 95406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34825 /* 95410 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34826 /* 95410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34827 /* 95413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34828 /* 95415 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34829 /* 95417 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34830 /* 95419 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34831 /* 95423 */ GIR_RootConstrainSelectedInstOperands,
34832 /* 95424 */ // GIR_Coverage, 5523,
34833 /* 95424 */ GIR_EraseRootFromParent_Done,
34834 /* 95425 */ // Label 2946: @95425
34835 /* 95425 */ GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(95453), // Rule ID 5526 //
34836 /* 95430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34837 /* 95434 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34838 /* 95438 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34839 /* 95438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34840 /* 95441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34841 /* 95443 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34842 /* 95445 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34843 /* 95447 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34844 /* 95451 */ GIR_RootConstrainSelectedInstOperands,
34845 /* 95452 */ // GIR_Coverage, 5526,
34846 /* 95452 */ GIR_EraseRootFromParent_Done,
34847 /* 95453 */ // Label 2947: @95453
34848 /* 95453 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(95481), // Rule ID 5527 //
34849 /* 95458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34850 /* 95462 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34851 /* 95466 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34852 /* 95466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34853 /* 95469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34854 /* 95471 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34855 /* 95473 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34856 /* 95475 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34857 /* 95479 */ GIR_RootConstrainSelectedInstOperands,
34858 /* 95480 */ // GIR_Coverage, 5527,
34859 /* 95480 */ GIR_EraseRootFromParent_Done,
34860 /* 95481 */ // Label 2948: @95481
34861 /* 95481 */ GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(95509), // Rule ID 5530 //
34862 /* 95486 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34863 /* 95490 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34864 /* 95494 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34865 /* 95494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34866 /* 95497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34867 /* 95499 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34868 /* 95501 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34869 /* 95503 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34870 /* 95507 */ GIR_RootConstrainSelectedInstOperands,
34871 /* 95508 */ // GIR_Coverage, 5530,
34872 /* 95508 */ GIR_EraseRootFromParent_Done,
34873 /* 95509 */ // Label 2949: @95509
34874 /* 95509 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(95537), // Rule ID 5531 //
34875 /* 95514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34876 /* 95518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34877 /* 95522 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34878 /* 95522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34879 /* 95525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34880 /* 95527 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34881 /* 95529 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34882 /* 95531 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34883 /* 95535 */ GIR_RootConstrainSelectedInstOperands,
34884 /* 95536 */ // GIR_Coverage, 5531,
34885 /* 95536 */ GIR_EraseRootFromParent_Done,
34886 /* 95537 */ // Label 2950: @95537
34887 /* 95537 */ GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(95565), // Rule ID 5534 //
34888 /* 95542 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34889 /* 95546 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34890 /* 95550 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34891 /* 95550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34892 /* 95553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34893 /* 95555 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34894 /* 95557 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34895 /* 95559 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34896 /* 95563 */ GIR_RootConstrainSelectedInstOperands,
34897 /* 95564 */ // GIR_Coverage, 5534,
34898 /* 95564 */ GIR_EraseRootFromParent_Done,
34899 /* 95565 */ // Label 2951: @95565
34900 /* 95565 */ GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(95593), // Rule ID 5535 //
34901 /* 95570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34902 /* 95574 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34903 /* 95578 */ // (intrinsic_w_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34904 /* 95578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34905 /* 95581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34906 /* 95583 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34907 /* 95585 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34908 /* 95587 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34909 /* 95591 */ GIR_RootConstrainSelectedInstOperands,
34910 /* 95592 */ // GIR_Coverage, 5535,
34911 /* 95592 */ GIR_EraseRootFromParent_Done,
34912 /* 95593 */ // Label 2952: @95593
34913 /* 95593 */ GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(95621), // Rule ID 5538 //
34914 /* 95598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34915 /* 95602 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34916 /* 95606 */ // (intrinsic_w_chain:{ *:[v4f32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34917 /* 95606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34918 /* 95609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34919 /* 95611 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34920 /* 95613 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34921 /* 95615 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34922 /* 95619 */ GIR_RootConstrainSelectedInstOperands,
34923 /* 95620 */ // GIR_Coverage, 5538,
34924 /* 95620 */ GIR_EraseRootFromParent_Done,
34925 /* 95621 */ // Label 2953: @95621
34926 /* 95621 */ GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(95649), // Rule ID 5539 //
34927 /* 95626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34928 /* 95630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34929 /* 95634 */ // (intrinsic_w_chain:{ *:[v4f32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34930 /* 95634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34931 /* 95637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34932 /* 95639 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34933 /* 95641 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34934 /* 95643 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34935 /* 95647 */ GIR_RootConstrainSelectedInstOperands,
34936 /* 95648 */ // GIR_Coverage, 5539,
34937 /* 95648 */ GIR_EraseRootFromParent_Done,
34938 /* 95649 */ // Label 2954: @95649
34939 /* 95649 */ GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(95677), // Rule ID 5542 //
34940 /* 95654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34941 /* 95658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34942 /* 95662 */ // (intrinsic_w_chain:{ *:[v4f32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34943 /* 95662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34944 /* 95665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34945 /* 95667 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34946 /* 95669 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34947 /* 95671 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34948 /* 95675 */ GIR_RootConstrainSelectedInstOperands,
34949 /* 95676 */ // GIR_Coverage, 5542,
34950 /* 95676 */ GIR_EraseRootFromParent_Done,
34951 /* 95677 */ // Label 2955: @95677
34952 /* 95677 */ GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(95705), // Rule ID 5543 //
34953 /* 95682 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34954 /* 95686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34955 /* 95690 */ // (intrinsic_w_chain:{ *:[v4f32] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34956 /* 95690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34957 /* 95693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34958 /* 95695 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34959 /* 95697 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34960 /* 95699 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34961 /* 95703 */ GIR_RootConstrainSelectedInstOperands,
34962 /* 95704 */ // GIR_Coverage, 5543,
34963 /* 95704 */ GIR_EraseRootFromParent_Done,
34964 /* 95705 */ // Label 2956: @95705
34965 /* 95705 */ GIM_Reject,
34966 /* 95706 */ // Label 2944: @95706
34967 /* 95706 */ GIM_Reject,
34968 /* 95707 */ // Label 2935: @95707
34969 /* 95707 */ GIM_Reject,
34970 /* 95708 */ // Label 2912: @95708
34971 /* 95708 */ GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(95970),
34972 /* 95713 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
34973 /* 95716 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34974 /* 95719 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34975 /* 95722 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34976 /* 95725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34977 /* 95729 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34978 /* 95733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34979 /* 95737 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34980 /* 95741 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
34981 /* 95745 */ GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(95773), // Rule ID 5546 //
34982 /* 95750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34983 /* 95754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34984 /* 95758 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34985 /* 95758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
34986 /* 95761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34987 /* 95763 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34988 /* 95765 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34989 /* 95767 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34990 /* 95771 */ GIR_RootConstrainSelectedInstOperands,
34991 /* 95772 */ // GIR_Coverage, 5546,
34992 /* 95772 */ GIR_EraseRootFromParent_Done,
34993 /* 95773 */ // Label 2958: @95773
34994 /* 95773 */ GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(95801), // Rule ID 5547 //
34995 /* 95778 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
34996 /* 95782 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34997 /* 95786 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34998 /* 95786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
34999 /* 95789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35000 /* 95791 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35001 /* 95793 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35002 /* 95795 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35003 /* 95799 */ GIR_RootConstrainSelectedInstOperands,
35004 /* 95800 */ // GIR_Coverage, 5547,
35005 /* 95800 */ GIR_EraseRootFromParent_Done,
35006 /* 95801 */ // Label 2959: @95801
35007 /* 95801 */ GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(95829), // Rule ID 5550 //
35008 /* 95806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
35009 /* 95810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35010 /* 95814 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35011 /* 95814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
35012 /* 95817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35013 /* 95819 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35014 /* 95821 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35015 /* 95823 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35016 /* 95827 */ GIR_RootConstrainSelectedInstOperands,
35017 /* 95828 */ // GIR_Coverage, 5550,
35018 /* 95828 */ GIR_EraseRootFromParent_Done,
35019 /* 95829 */ // Label 2960: @95829
35020 /* 95829 */ GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(95857), // Rule ID 5551 //
35021 /* 95834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
35022 /* 95838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35023 /* 95842 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35024 /* 95842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
35025 /* 95845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35026 /* 95847 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35027 /* 95849 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35028 /* 95851 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35029 /* 95855 */ GIR_RootConstrainSelectedInstOperands,
35030 /* 95856 */ // GIR_Coverage, 5551,
35031 /* 95856 */ GIR_EraseRootFromParent_Done,
35032 /* 95857 */ // Label 2961: @95857
35033 /* 95857 */ GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(95885), // Rule ID 5554 //
35034 /* 95862 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
35035 /* 95866 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
35036 /* 95870 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35037 /* 95870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
35038 /* 95873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35039 /* 95875 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35040 /* 95877 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35041 /* 95879 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35042 /* 95883 */ GIR_RootConstrainSelectedInstOperands,
35043 /* 95884 */ // GIR_Coverage, 5554,
35044 /* 95884 */ GIR_EraseRootFromParent_Done,
35045 /* 95885 */ // Label 2962: @95885
35046 /* 95885 */ GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(95913), // Rule ID 5555 //
35047 /* 95890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
35048 /* 95894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
35049 /* 95898 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35050 /* 95898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
35051 /* 95901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35052 /* 95903 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35053 /* 95905 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35054 /* 95907 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35055 /* 95911 */ GIR_RootConstrainSelectedInstOperands,
35056 /* 95912 */ // GIR_Coverage, 5555,
35057 /* 95912 */ GIR_EraseRootFromParent_Done,
35058 /* 95913 */ // Label 2963: @95913
35059 /* 95913 */ GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(95941), // Rule ID 5558 //
35060 /* 95918 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
35061 /* 95922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35062 /* 95926 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35063 /* 95926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
35064 /* 95929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35065 /* 95931 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35066 /* 95933 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35067 /* 95935 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35068 /* 95939 */ GIR_RootConstrainSelectedInstOperands,
35069 /* 95940 */ // GIR_Coverage, 5558,
35070 /* 95940 */ GIR_EraseRootFromParent_Done,
35071 /* 95941 */ // Label 2964: @95941
35072 /* 95941 */ GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(95969), // Rule ID 5559 //
35073 /* 95946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
35074 /* 95950 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35075 /* 95954 */ // (intrinsic_w_chain:{ *:[v2i64] } 3889:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35076 /* 95954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
35077 /* 95957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35078 /* 95959 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35079 /* 95961 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35080 /* 95963 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35081 /* 95967 */ GIR_RootConstrainSelectedInstOperands,
35082 /* 95968 */ // GIR_Coverage, 5559,
35083 /* 95968 */ GIR_EraseRootFromParent_Done,
35084 /* 95969 */ // Label 2965: @95969
35085 /* 95969 */ GIM_Reject,
35086 /* 95970 */ // Label 2957: @95970
35087 /* 95970 */ GIM_Reject,
35088 /* 95971 */ // Label 2913: @95971
35089 /* 95971 */ GIM_Reject,
35090 /* 95972 */ // Label 2908: @95972
35091 /* 95972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2966*/ GIMT_Encode4(96036), GIMT_Encode2(GIFBS_IsARM), // Rule ID 255 //
35092 /* 95979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
35093 /* 95984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35094 /* 95987 */ // MIs[0] cop
35095 /* 95987 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35096 /* 95990 */ // MIs[0] opc1
35097 /* 95990 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35098 /* 95993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35099 /* 95997 */ // MIs[0] CRn
35100 /* 95997 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35101 /* 96000 */ // MIs[0] CRm
35102 /* 96000 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35103 /* 96003 */ // MIs[0] opc2
35104 /* 96003 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35105 /* 96006 */ // (intrinsic_void 3754:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35106 /* 96006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR),
35107 /* 96009 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35108 /* 96011 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35109 /* 96013 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35110 /* 96015 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35111 /* 96017 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35112 /* 96019 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35113 /* 96021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35114 /* 96024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35115 /* 96030 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35116 /* 96034 */ GIR_RootConstrainSelectedInstOperands,
35117 /* 96035 */ // GIR_Coverage, 255,
35118 /* 96035 */ GIR_EraseRootFromParent_Done,
35119 /* 96036 */ // Label 2966: @96036
35120 /* 96036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2967*/ GIMT_Encode4(96091), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 256 //
35121 /* 96043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
35122 /* 96048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35123 /* 96051 */ // MIs[0] cop
35124 /* 96051 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35125 /* 96054 */ // MIs[0] opc1
35126 /* 96054 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35127 /* 96057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35128 /* 96061 */ // MIs[0] CRn
35129 /* 96061 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35130 /* 96064 */ // MIs[0] CRm
35131 /* 96064 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35132 /* 96067 */ // MIs[0] opc2
35133 /* 96067 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35134 /* 96070 */ // (intrinsic_void 3755:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35135 /* 96070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2),
35136 /* 96073 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35137 /* 96075 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35138 /* 96077 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35139 /* 96079 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35140 /* 96081 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35141 /* 96083 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35142 /* 96085 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35143 /* 96089 */ GIR_RootConstrainSelectedInstOperands,
35144 /* 96090 */ // GIR_Coverage, 256,
35145 /* 96090 */ GIR_EraseRootFromParent_Done,
35146 /* 96091 */ // Label 2967: @96091
35147 /* 96091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2968*/ GIMT_Encode4(96155), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 593 //
35148 /* 96098 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
35149 /* 96103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35150 /* 96106 */ // MIs[0] cop
35151 /* 96106 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35152 /* 96109 */ // MIs[0] opc1
35153 /* 96109 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35154 /* 96112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35155 /* 96116 */ // MIs[0] CRn
35156 /* 96116 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35157 /* 96119 */ // MIs[0] CRm
35158 /* 96119 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35159 /* 96122 */ // MIs[0] opc2
35160 /* 96122 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35161 /* 96125 */ // (intrinsic_void 3754:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35162 /* 96125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR),
35163 /* 96128 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35164 /* 96130 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35165 /* 96132 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35166 /* 96134 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35167 /* 96136 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35168 /* 96138 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35169 /* 96140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35170 /* 96143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35171 /* 96149 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35172 /* 96153 */ GIR_RootConstrainSelectedInstOperands,
35173 /* 96154 */ // GIR_Coverage, 593,
35174 /* 96154 */ GIR_EraseRootFromParent_Done,
35175 /* 96155 */ // Label 2968: @96155
35176 /* 96155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2969*/ GIMT_Encode4(96219), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 594 //
35177 /* 96162 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
35178 /* 96167 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35179 /* 96170 */ // MIs[0] cop
35180 /* 96170 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35181 /* 96173 */ // MIs[0] opc1
35182 /* 96173 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35183 /* 96176 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35184 /* 96180 */ // MIs[0] CRn
35185 /* 96180 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35186 /* 96183 */ // MIs[0] CRm
35187 /* 96183 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35188 /* 96186 */ // MIs[0] opc2
35189 /* 96186 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35190 /* 96189 */ // (intrinsic_void 3755:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35191 /* 96189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2),
35192 /* 96192 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35193 /* 96194 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35194 /* 96196 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35195 /* 96198 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35196 /* 96200 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35197 /* 96202 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35198 /* 96204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35199 /* 96207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35200 /* 96213 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35201 /* 96217 */ GIR_RootConstrainSelectedInstOperands,
35202 /* 96218 */ // GIR_Coverage, 594,
35203 /* 96218 */ GIR_EraseRootFromParent_Done,
35204 /* 96219 */ // Label 2969: @96219
35205 /* 96219 */ GIM_Reject,
35206 /* 96220 */ // Label 2903: @96220
35207 /* 96220 */ GIM_Reject,
35208 /* 96221 */ // Label 24: @96221
35209 /* 96221 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2973*/ GIMT_Encode4(96359),
35210 /* 96232 */ /*GILLT_v8s16*//*Label 2970*/ GIMT_Encode4(96248), GIMT_Encode4(0),
35211 /* 96240 */ /*GILLT_v4s32*//*Label 2971*/ GIMT_Encode4(96285),
35212 /* 96244 */ /*GILLT_v2s64*//*Label 2972*/ GIMT_Encode4(96322),
35213 /* 96248 */ // Label 2970: @96248
35214 /* 96248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2974*/ GIMT_Encode4(96284), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3055 //
35215 /* 96255 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
35216 /* 96258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35217 /* 96262 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35218 /* 96266 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
35219 /* 96266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
35220 /* 96269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35221 /* 96271 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35222 /* 96273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35223 /* 96276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35224 /* 96282 */ GIR_RootConstrainSelectedInstOperands,
35225 /* 96283 */ // GIR_Coverage, 3055,
35226 /* 96283 */ GIR_EraseRootFromParent_Done,
35227 /* 96284 */ // Label 2974: @96284
35228 /* 96284 */ GIM_Reject,
35229 /* 96285 */ // Label 2971: @96285
35230 /* 96285 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2975*/ GIMT_Encode4(96321), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3056 //
35231 /* 96292 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
35232 /* 96295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35233 /* 96299 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35234 /* 96303 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
35235 /* 96303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
35236 /* 96306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35237 /* 96308 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35238 /* 96310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35239 /* 96313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35240 /* 96319 */ GIR_RootConstrainSelectedInstOperands,
35241 /* 96320 */ // GIR_Coverage, 3056,
35242 /* 96320 */ GIR_EraseRootFromParent_Done,
35243 /* 96321 */ // Label 2975: @96321
35244 /* 96321 */ GIM_Reject,
35245 /* 96322 */ // Label 2972: @96322
35246 /* 96322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2976*/ GIMT_Encode4(96358), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3057 //
35247 /* 96329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
35248 /* 96332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35249 /* 96336 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35250 /* 96340 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
35251 /* 96340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
35252 /* 96343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35253 /* 96345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35254 /* 96347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35255 /* 96350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35256 /* 96356 */ GIR_RootConstrainSelectedInstOperands,
35257 /* 96357 */ // GIR_Coverage, 3057,
35258 /* 96357 */ GIR_EraseRootFromParent_Done,
35259 /* 96358 */ // Label 2976: @96358
35260 /* 96358 */ GIM_Reject,
35261 /* 96359 */ // Label 2973: @96359
35262 /* 96359 */ GIM_Reject,
35263 /* 96360 */ // Label 25: @96360
35264 /* 96360 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 2980*/ GIMT_Encode4(96502),
35265 /* 96371 */ /*GILLT_v8s8*//*Label 2977*/ GIMT_Encode4(96391), GIMT_Encode4(0),
35266 /* 96379 */ /*GILLT_v4s16*//*Label 2978*/ GIMT_Encode4(96428), GIMT_Encode4(0),
35267 /* 96387 */ /*GILLT_v2s32*//*Label 2979*/ GIMT_Encode4(96465),
35268 /* 96391 */ // Label 2977: @96391
35269 /* 96391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2981*/ GIMT_Encode4(96427), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1748 //
35270 /* 96398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
35271 /* 96401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35272 /* 96405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35273 /* 96409 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
35274 /* 96409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8),
35275 /* 96412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35276 /* 96414 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35277 /* 96416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35278 /* 96419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35279 /* 96425 */ GIR_RootConstrainSelectedInstOperands,
35280 /* 96426 */ // GIR_Coverage, 1748,
35281 /* 96426 */ GIR_EraseRootFromParent_Done,
35282 /* 96427 */ // Label 2981: @96427
35283 /* 96427 */ GIM_Reject,
35284 /* 96428 */ // Label 2978: @96428
35285 /* 96428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2982*/ GIMT_Encode4(96464), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1749 //
35286 /* 96435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35287 /* 96438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35288 /* 96442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35289 /* 96446 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
35290 /* 96446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16),
35291 /* 96449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35292 /* 96451 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35293 /* 96453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35294 /* 96456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35295 /* 96462 */ GIR_RootConstrainSelectedInstOperands,
35296 /* 96463 */ // GIR_Coverage, 1749,
35297 /* 96463 */ GIR_EraseRootFromParent_Done,
35298 /* 96464 */ // Label 2982: @96464
35299 /* 96464 */ GIM_Reject,
35300 /* 96465 */ // Label 2979: @96465
35301 /* 96465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2983*/ GIMT_Encode4(96501), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1750 //
35302 /* 96472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
35303 /* 96475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35304 /* 96479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35305 /* 96483 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
35306 /* 96483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32),
35307 /* 96486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35308 /* 96488 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35309 /* 96490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35310 /* 96493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35311 /* 96499 */ GIR_RootConstrainSelectedInstOperands,
35312 /* 96500 */ // GIR_Coverage, 1750,
35313 /* 96500 */ GIR_EraseRootFromParent_Done,
35314 /* 96501 */ // Label 2983: @96501
35315 /* 96501 */ GIM_Reject,
35316 /* 96502 */ // Label 2980: @96502
35317 /* 96502 */ GIM_Reject,
35318 /* 96503 */ // Label 26: @96503
35319 /* 96503 */ GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(96814),
35320 /* 96508 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35321 /* 96511 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2985*/ GIMT_Encode4(96551), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 403 //
35322 /* 96518 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
35323 /* 96522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35324 /* 96526 */ // MIs[0] Operand 1
35325 /* 96526 */ // No operand predicates
35326 /* 96526 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35327 /* 96526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
35328 /* 96529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35329 /* 96531 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35330 /* 96534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35331 /* 96537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35332 /* 96543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35333 /* 96549 */ GIR_RootConstrainSelectedInstOperands,
35334 /* 96550 */ // GIR_Coverage, 403,
35335 /* 96550 */ GIR_EraseRootFromParent_Done,
35336 /* 96551 */ // Label 2985: @96551
35337 /* 96551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2986*/ GIMT_Encode4(96591), GIMT_Encode2(GIFBS_IsARM), // Rule ID 56 //
35338 /* 96558 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
35339 /* 96562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35340 /* 96566 */ // MIs[0] Operand 1
35341 /* 96566 */ // No operand predicates
35342 /* 96566 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35343 /* 96566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi),
35344 /* 96569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35345 /* 96571 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35346 /* 96574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35347 /* 96577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35348 /* 96583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35349 /* 96589 */ GIR_RootConstrainSelectedInstOperands,
35350 /* 96590 */ // GIR_Coverage, 56,
35351 /* 96590 */ GIR_EraseRootFromParent_Done,
35352 /* 96591 */ // Label 2986: @96591
35353 /* 96591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2987*/ GIMT_Encode4(96625), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 57 //
35354 /* 96598 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35355 /* 96602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35356 /* 96606 */ // MIs[0] Operand 1
35357 /* 96606 */ // No operand predicates
35358 /* 96606 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35359 /* 96606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16),
35360 /* 96609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35361 /* 96611 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35362 /* 96614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35363 /* 96617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35364 /* 96623 */ GIR_RootConstrainSelectedInstOperands,
35365 /* 96624 */ // GIR_Coverage, 57,
35366 /* 96624 */ GIR_EraseRootFromParent_Done,
35367 /* 96625 */ // Label 2987: @96625
35368 /* 96625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2988*/ GIMT_Encode4(96667), GIMT_Encode2(GIFBS_IsARM), // Rule ID 167 //
35369 /* 96632 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
35370 /* 96636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35371 /* 96640 */ // MIs[0] Operand 1
35372 /* 96640 */ // No operand predicates
35373 /* 96640 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
35374 /* 96640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi),
35375 /* 96643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35376 /* 96645 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
35377 /* 96650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35378 /* 96653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35379 /* 96659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35380 /* 96665 */ GIR_RootConstrainSelectedInstOperands,
35381 /* 96666 */ // GIR_Coverage, 167,
35382 /* 96666 */ GIR_EraseRootFromParent_Done,
35383 /* 96667 */ // Label 2988: @96667
35384 /* 96667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2989*/ GIMT_Encode4(96692), GIMT_Encode2(GIFBS_IsARM), // Rule ID 267 //
35385 /* 96674 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm),
35386 /* 96678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35387 /* 96682 */ // MIs[0] Operand 1
35388 /* 96682 */ // No operand predicates
35389 /* 96682 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
35390 /* 96682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm),
35391 /* 96685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35392 /* 96687 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
35393 /* 96690 */ GIR_RootConstrainSelectedInstOperands,
35394 /* 96691 */ // GIR_Coverage, 267,
35395 /* 96691 */ GIR_EraseRootFromParent_Done,
35396 /* 96692 */ // Label 2989: @96692
35397 /* 96692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2990*/ GIMT_Encode4(96732), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 321 //
35398 /* 96699 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
35399 /* 96703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35400 /* 96707 */ // MIs[0] Operand 1
35401 /* 96707 */ // No operand predicates
35402 /* 96707 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8)
35403 /* 96707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
35404 /* 96710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35405 /* 96712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
35406 /* 96718 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8
35407 /* 96721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35408 /* 96724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35409 /* 96730 */ GIR_RootConstrainSelectedInstOperands,
35410 /* 96731 */ // GIR_Coverage, 321,
35411 /* 96731 */ GIR_EraseRootFromParent_Done,
35412 /* 96732 */ // Label 2990: @96732
35413 /* 96732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2991*/ GIMT_Encode4(96766), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 404 //
35414 /* 96739 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35415 /* 96743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35416 /* 96747 */ // MIs[0] Operand 1
35417 /* 96747 */ // No operand predicates
35418 /* 96747 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35419 /* 96747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
35420 /* 96750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35421 /* 96752 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35422 /* 96755 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35423 /* 96758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35424 /* 96764 */ GIR_RootConstrainSelectedInstOperands,
35425 /* 96765 */ // GIR_Coverage, 404,
35426 /* 96765 */ GIR_EraseRootFromParent_Done,
35427 /* 96766 */ // Label 2991: @96766
35428 /* 96766 */ GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(96813),
35429 /* 96771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35430 /* 96775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2993*/ GIMT_Encode4(96795), GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only), // Rule ID 352 //
35431 /* 96782 */ // MIs[0] Operand 1
35432 /* 96782 */ // No operand predicates
35433 /* 96782 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src)
35434 /* 96782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm),
35435 /* 96785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35436 /* 96787 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
35437 /* 96790 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0,
35438 /* 96793 */ GIR_RootConstrainSelectedInstOperands,
35439 /* 96794 */ // GIR_Coverage, 352,
35440 /* 96794 */ GIR_EraseRootFromParent_Done,
35441 /* 96795 */ // Label 2993: @96795
35442 /* 96795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2994*/ GIMT_Encode4(96812), GIMT_Encode2(GIFBS_IsThumb_UseMovt), // Rule ID 581 //
35443 /* 96802 */ // MIs[0] Operand 1
35444 /* 96802 */ // No operand predicates
35445 /* 96802 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
35446 /* 96802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
35447 /* 96805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35448 /* 96807 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
35449 /* 96810 */ GIR_RootConstrainSelectedInstOperands,
35450 /* 96811 */ // GIR_Coverage, 581,
35451 /* 96811 */ GIR_EraseRootFromParent_Done,
35452 /* 96812 */ // Label 2994: @96812
35453 /* 96812 */ GIM_Reject,
35454 /* 96813 */ // Label 2992: @96813
35455 /* 96813 */ GIM_Reject,
35456 /* 96814 */ // Label 2984: @96814
35457 /* 96814 */ GIM_Reject,
35458 /* 96815 */ // Label 27: @96815
35459 /* 96815 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2997*/ GIMT_Encode4(96908),
35460 /* 96826 */ /*GILLT_s32*//*Label 2995*/ GIMT_Encode4(96834),
35461 /* 96830 */ /*GILLT_s64*//*Label 2996*/ GIMT_Encode4(96871),
35462 /* 96834 */ // Label 2995: @96834
35463 /* 96834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2998*/ GIMT_Encode4(96870), GIMT_Encode2(GIFBS_HasVFP3), // Rule ID 848 //
35464 /* 96841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
35465 /* 96845 */ // MIs[0] Operand 1
35466 /* 96845 */ // No operand predicates
35467 /* 96845 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm),
35468 /* 96849 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
35469 /* 96849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS),
35470 /* 96852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
35471 /* 96854 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm
35472 /* 96859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35473 /* 96862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35474 /* 96868 */ GIR_RootConstrainSelectedInstOperands,
35475 /* 96869 */ // GIR_Coverage, 848,
35476 /* 96869 */ GIR_EraseRootFromParent_Done,
35477 /* 96870 */ // Label 2998: @96870
35478 /* 96870 */ GIM_Reject,
35479 /* 96871 */ // Label 2996: @96871
35480 /* 96871 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2999*/ GIMT_Encode4(96907), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3), // Rule ID 847 //
35481 /* 96878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35482 /* 96882 */ // MIs[0] Operand 1
35483 /* 96882 */ // No operand predicates
35484 /* 96882 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm),
35485 /* 96886 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
35486 /* 96886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD),
35487 /* 96889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
35488 /* 96891 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm
35489 /* 96896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35490 /* 96899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35491 /* 96905 */ GIR_RootConstrainSelectedInstOperands,
35492 /* 96906 */ // GIR_Coverage, 847,
35493 /* 96906 */ GIR_EraseRootFromParent_Done,
35494 /* 96907 */ // Label 2999: @96907
35495 /* 96907 */ GIM_Reject,
35496 /* 96908 */ // Label 2997: @96908
35497 /* 96908 */ GIM_Reject,
35498 /* 96909 */ // Label 28: @96909
35499 /* 96909 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 3003*/ GIMT_Encode4(97047),
35500 /* 96920 */ /*GILLT_v8s16*//*Label 3000*/ GIMT_Encode4(96936), GIMT_Encode4(0),
35501 /* 96928 */ /*GILLT_v4s32*//*Label 3001*/ GIMT_Encode4(96973),
35502 /* 96932 */ /*GILLT_v2s64*//*Label 3002*/ GIMT_Encode4(97010),
35503 /* 96936 */ // Label 3000: @96936
35504 /* 96936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3004*/ GIMT_Encode4(96972), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1760 //
35505 /* 96943 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
35506 /* 96946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35507 /* 96950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35508 /* 96954 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
35509 /* 96954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16),
35510 /* 96957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35511 /* 96959 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35512 /* 96961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35513 /* 96964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35514 /* 96970 */ GIR_RootConstrainSelectedInstOperands,
35515 /* 96971 */ // GIR_Coverage, 1760,
35516 /* 96971 */ GIR_EraseRootFromParent_Done,
35517 /* 96972 */ // Label 3004: @96972
35518 /* 96972 */ GIM_Reject,
35519 /* 96973 */ // Label 3001: @96973
35520 /* 96973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3005*/ GIMT_Encode4(97009), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1761 //
35521 /* 96980 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
35522 /* 96983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35523 /* 96987 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35524 /* 96991 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
35525 /* 96991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32),
35526 /* 96994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35527 /* 96996 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35528 /* 96998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35529 /* 97001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35530 /* 97007 */ GIR_RootConstrainSelectedInstOperands,
35531 /* 97008 */ // GIR_Coverage, 1761,
35532 /* 97008 */ GIR_EraseRootFromParent_Done,
35533 /* 97009 */ // Label 3005: @97009
35534 /* 97009 */ GIM_Reject,
35535 /* 97010 */ // Label 3002: @97010
35536 /* 97010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3006*/ GIMT_Encode4(97046), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1762 //
35537 /* 97017 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
35538 /* 97020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35539 /* 97024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35540 /* 97028 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
35541 /* 97028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64),
35542 /* 97031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35543 /* 97033 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35544 /* 97035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35545 /* 97038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35546 /* 97044 */ GIR_RootConstrainSelectedInstOperands,
35547 /* 97045 */ // GIR_Coverage, 1762,
35548 /* 97045 */ GIR_EraseRootFromParent_Done,
35549 /* 97046 */ // Label 3006: @97046
35550 /* 97046 */ GIM_Reject,
35551 /* 97047 */ // Label 3003: @97047
35552 /* 97047 */ GIM_Reject,
35553 /* 97048 */ // Label 29: @97048
35554 /* 97048 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3010*/ GIMT_Encode4(97637),
35555 /* 97059 */ /*GILLT_s32*//*Label 3007*/ GIMT_Encode4(97107), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
35556 /* 97095 */ /*GILLT_v8s16*//*Label 3008*/ GIMT_Encode4(97387), GIMT_Encode4(0),
35557 /* 97103 */ /*GILLT_v4s32*//*Label 3009*/ GIMT_Encode4(97456),
35558 /* 97107 */ // Label 3007: @97107
35559 /* 97107 */ GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(97386),
35560 /* 97112 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35561 /* 97115 */ GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(97201),
35562 /* 97120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35563 /* 97124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35564 /* 97128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3013*/ GIMT_Encode4(97164), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 339 //
35565 /* 97135 */ // MIs[0] Operand 2
35566 /* 97135 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35567 /* 97146 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
35568 /* 97146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB),
35569 /* 97149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35570 /* 97151 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
35571 /* 97153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35572 /* 97156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35573 /* 97162 */ GIR_RootConstrainSelectedInstOperands,
35574 /* 97163 */ // GIR_Coverage, 339,
35575 /* 97163 */ GIR_EraseRootFromParent_Done,
35576 /* 97164 */ // Label 3013: @97164
35577 /* 97164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3014*/ GIMT_Encode4(97200), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 340 //
35578 /* 97171 */ // MIs[0] Operand 2
35579 /* 97171 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35580 /* 97182 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
35581 /* 97182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH),
35582 /* 97185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35583 /* 97187 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
35584 /* 97189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35585 /* 97192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35586 /* 97198 */ GIR_RootConstrainSelectedInstOperands,
35587 /* 97199 */ // GIR_Coverage, 340,
35588 /* 97199 */ GIR_EraseRootFromParent_Done,
35589 /* 97200 */ // Label 3014: @97200
35590 /* 97200 */ GIM_Reject,
35591 /* 97201 */ // Label 3012: @97201
35592 /* 97201 */ GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(97293),
35593 /* 97206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35594 /* 97210 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35595 /* 97214 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3016*/ GIMT_Encode4(97253), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2197 //
35596 /* 97221 */ // MIs[0] Operand 2
35597 /* 97221 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35598 /* 97232 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35599 /* 97232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB),
35600 /* 97235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35601 /* 97237 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35602 /* 97239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35603 /* 97242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35604 /* 97245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35605 /* 97251 */ GIR_RootConstrainSelectedInstOperands,
35606 /* 97252 */ // GIR_Coverage, 2197,
35607 /* 97252 */ GIR_EraseRootFromParent_Done,
35608 /* 97253 */ // Label 3016: @97253
35609 /* 97253 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3017*/ GIMT_Encode4(97292), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2198 //
35610 /* 97260 */ // MIs[0] Operand 2
35611 /* 97260 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35612 /* 97271 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35613 /* 97271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH),
35614 /* 97274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35615 /* 97276 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35616 /* 97278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35617 /* 97281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35618 /* 97284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35619 /* 97290 */ GIR_RootConstrainSelectedInstOperands,
35620 /* 97291 */ // GIR_Coverage, 2198,
35621 /* 97291 */ GIR_EraseRootFromParent_Done,
35622 /* 97292 */ // Label 3017: @97292
35623 /* 97292 */ GIM_Reject,
35624 /* 97293 */ // Label 3015: @97293
35625 /* 97293 */ GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(97385),
35626 /* 97298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35627 /* 97302 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35628 /* 97306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3019*/ GIMT_Encode4(97345), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2441 //
35629 /* 97313 */ // MIs[0] Operand 2
35630 /* 97313 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35631 /* 97324 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35632 /* 97324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB),
35633 /* 97327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35634 /* 97329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35635 /* 97331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35636 /* 97334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35637 /* 97337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35638 /* 97343 */ GIR_RootConstrainSelectedInstOperands,
35639 /* 97344 */ // GIR_Coverage, 2441,
35640 /* 97344 */ GIR_EraseRootFromParent_Done,
35641 /* 97345 */ // Label 3019: @97345
35642 /* 97345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3020*/ GIMT_Encode4(97384), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2442 //
35643 /* 97352 */ // MIs[0] Operand 2
35644 /* 97352 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35645 /* 97363 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35646 /* 97363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH),
35647 /* 97366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35648 /* 97368 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35649 /* 97370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35650 /* 97373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35651 /* 97376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35652 /* 97382 */ GIR_RootConstrainSelectedInstOperands,
35653 /* 97383 */ // GIR_Coverage, 2442,
35654 /* 97383 */ GIR_EraseRootFromParent_Done,
35655 /* 97384 */ // Label 3020: @97384
35656 /* 97384 */ GIM_Reject,
35657 /* 97385 */ // Label 3018: @97385
35658 /* 97385 */ GIM_Reject,
35659 /* 97386 */ // Label 3011: @97386
35660 /* 97386 */ GIM_Reject,
35661 /* 97387 */ // Label 3008: @97387
35662 /* 97387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3021*/ GIMT_Encode4(97455), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4117 //
35663 /* 97394 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
35664 /* 97397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35665 /* 97401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35666 /* 97405 */ // MIs[0] Operand 2
35667 /* 97405 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35668 /* 97416 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
35669 /* 97416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35670 /* 97419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35671 /* 97423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35672 /* 97428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
35673 /* 97431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35674 /* 97433 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
35675 /* 97435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35676 /* 97438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35677 /* 97444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35678 /* 97450 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35679 /* 97453 */ GIR_RootConstrainSelectedInstOperands,
35680 /* 97454 */ // GIR_Coverage, 4117,
35681 /* 97454 */ GIR_EraseRootFromParent_Done,
35682 /* 97455 */ // Label 3021: @97455
35683 /* 97455 */ GIM_Reject,
35684 /* 97456 */ // Label 3009: @97456
35685 /* 97456 */ GIM_Try, /*On fail goto*//*Label 3022*/ GIMT_Encode4(97636),
35686 /* 97461 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35687 /* 97464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35688 /* 97468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35689 /* 97472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3023*/ GIMT_Encode4(97529), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4116 //
35690 /* 97479 */ // MIs[0] Operand 2
35691 /* 97479 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35692 /* 97490 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
35693 /* 97490 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35694 /* 97493 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35695 /* 97497 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35696 /* 97502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
35697 /* 97505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35698 /* 97507 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
35699 /* 97509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35700 /* 97512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35701 /* 97518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35702 /* 97524 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35703 /* 97527 */ GIR_RootConstrainSelectedInstOperands,
35704 /* 97528 */ // GIR_Coverage, 4116,
35705 /* 97528 */ GIR_EraseRootFromParent_Done,
35706 /* 97529 */ // Label 3023: @97529
35707 /* 97529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3024*/ GIMT_Encode4(97635), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4118 //
35708 /* 97536 */ // MIs[0] Operand 2
35709 /* 97536 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35710 /* 97547 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src))
35711 /* 97547 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
35712 /* 97550 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35713 /* 97554 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35714 /* 97559 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
35715 /* 97562 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35716 /* 97566 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35717 /* 97571 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
35718 /* 97574 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
35719 /* 97578 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35720 /* 97583 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
35721 /* 97587 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
35722 /* 97590 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35723 /* 97596 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35724 /* 97602 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
35725 /* 97605 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35726 /* 97607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
35727 /* 97610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35728 /* 97612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35729 /* 97615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35730 /* 97618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35731 /* 97624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35732 /* 97630 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35733 /* 97633 */ GIR_RootConstrainSelectedInstOperands,
35734 /* 97634 */ // GIR_Coverage, 4118,
35735 /* 97634 */ GIR_EraseRootFromParent_Done,
35736 /* 97635 */ // Label 3024: @97635
35737 /* 97635 */ GIM_Reject,
35738 /* 97636 */ // Label 3022: @97636
35739 /* 97636 */ GIM_Reject,
35740 /* 97637 */ // Label 3010: @97637
35741 /* 97637 */ GIM_Reject,
35742 /* 97638 */ // Label 30: @97638
35743 /* 97638 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 3028*/ GIMT_Encode4(98325),
35744 /* 97649 */ /*GILLT_v8s16*//*Label 3025*/ GIMT_Encode4(97665), GIMT_Encode4(0),
35745 /* 97657 */ /*GILLT_v4s32*//*Label 3026*/ GIMT_Encode4(97885),
35746 /* 97661 */ /*GILLT_v2s64*//*Label 3027*/ GIMT_Encode4(98105),
35747 /* 97665 */ // Label 3025: @97665
35748 /* 97665 */ GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(97884),
35749 /* 97670 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
35750 /* 97673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35751 /* 97677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3030*/ GIMT_Encode4(97736), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1335 //
35752 /* 97684 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35753 /* 97688 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
35754 /* 97692 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
35755 /* 97696 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
35756 /* 97700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35757 /* 97705 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35758 /* 97710 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35759 /* 97712 */ // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
35760 /* 97712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16),
35761 /* 97715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35762 /* 97717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35763 /* 97721 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35764 /* 97725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35765 /* 97728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35766 /* 97734 */ GIR_RootConstrainSelectedInstOperands,
35767 /* 97735 */ // GIR_Coverage, 1335,
35768 /* 97735 */ GIR_EraseRootFromParent_Done,
35769 /* 97736 */ // Label 3030: @97736
35770 /* 97736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3031*/ GIMT_Encode4(97795), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1338 //
35771 /* 97743 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35772 /* 97747 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35773 /* 97751 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
35774 /* 97755 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
35775 /* 97759 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35776 /* 97764 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35777 /* 97769 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35778 /* 97771 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
35779 /* 97771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
35780 /* 97774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35781 /* 97776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35782 /* 97780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35783 /* 97784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35784 /* 97787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35785 /* 97793 */ GIR_RootConstrainSelectedInstOperands,
35786 /* 97794 */ // GIR_Coverage, 1338,
35787 /* 97794 */ GIR_EraseRootFromParent_Done,
35788 /* 97795 */ // Label 3031: @97795
35789 /* 97795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3032*/ GIMT_Encode4(97854), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2967 //
35790 /* 97802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35791 /* 97806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35792 /* 97810 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
35793 /* 97814 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
35794 /* 97818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35795 /* 97823 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35796 /* 97828 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35797 /* 97830 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)
35798 /* 97830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
35799 /* 97833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35800 /* 97835 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
35801 /* 97839 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
35802 /* 97843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35803 /* 97846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35804 /* 97852 */ GIR_RootConstrainSelectedInstOperands,
35805 /* 97853 */ // GIR_Coverage, 2967,
35806 /* 97853 */ GIR_EraseRootFromParent_Done,
35807 /* 97854 */ // Label 3032: @97854
35808 /* 97854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3033*/ GIMT_Encode4(97883), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1763 //
35809 /* 97861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35810 /* 97865 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
35811 /* 97865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
35812 /* 97868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35813 /* 97870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35814 /* 97872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35815 /* 97875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35816 /* 97881 */ GIR_RootConstrainSelectedInstOperands,
35817 /* 97882 */ // GIR_Coverage, 1763,
35818 /* 97882 */ GIR_EraseRootFromParent_Done,
35819 /* 97883 */ // Label 3033: @97883
35820 /* 97883 */ GIM_Reject,
35821 /* 97884 */ // Label 3029: @97884
35822 /* 97884 */ GIM_Reject,
35823 /* 97885 */ // Label 3026: @97885
35824 /* 97885 */ GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(98104),
35825 /* 97890 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
35826 /* 97893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35827 /* 97897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3035*/ GIMT_Encode4(97956), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1336 //
35828 /* 97904 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35829 /* 97908 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
35830 /* 97912 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
35831 /* 97916 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
35832 /* 97920 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35833 /* 97925 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35834 /* 97930 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35835 /* 97932 */ // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
35836 /* 97932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32),
35837 /* 97935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35838 /* 97937 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35839 /* 97941 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35840 /* 97945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35841 /* 97948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35842 /* 97954 */ GIR_RootConstrainSelectedInstOperands,
35843 /* 97955 */ // GIR_Coverage, 1336,
35844 /* 97955 */ GIR_EraseRootFromParent_Done,
35845 /* 97956 */ // Label 3035: @97956
35846 /* 97956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3036*/ GIMT_Encode4(98015), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1339 //
35847 /* 97963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35848 /* 97967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35849 /* 97971 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
35850 /* 97975 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
35851 /* 97979 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35852 /* 97984 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35853 /* 97989 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35854 /* 97991 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
35855 /* 97991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
35856 /* 97994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35857 /* 97996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35858 /* 98000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35859 /* 98004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35860 /* 98007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35861 /* 98013 */ GIR_RootConstrainSelectedInstOperands,
35862 /* 98014 */ // GIR_Coverage, 1339,
35863 /* 98014 */ GIR_EraseRootFromParent_Done,
35864 /* 98015 */ // Label 3036: @98015
35865 /* 98015 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3037*/ GIMT_Encode4(98074), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2968 //
35866 /* 98022 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35867 /* 98026 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35868 /* 98030 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
35869 /* 98034 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
35870 /* 98038 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35871 /* 98043 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35872 /* 98048 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35873 /* 98050 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)
35874 /* 98050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
35875 /* 98053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35876 /* 98055 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
35877 /* 98059 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
35878 /* 98063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35879 /* 98066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35880 /* 98072 */ GIR_RootConstrainSelectedInstOperands,
35881 /* 98073 */ // GIR_Coverage, 2968,
35882 /* 98073 */ GIR_EraseRootFromParent_Done,
35883 /* 98074 */ // Label 3037: @98074
35884 /* 98074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3038*/ GIMT_Encode4(98103), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1764 //
35885 /* 98081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35886 /* 98085 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
35887 /* 98085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
35888 /* 98088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35889 /* 98090 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35890 /* 98092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35891 /* 98095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35892 /* 98101 */ GIR_RootConstrainSelectedInstOperands,
35893 /* 98102 */ // GIR_Coverage, 1764,
35894 /* 98102 */ GIR_EraseRootFromParent_Done,
35895 /* 98103 */ // Label 3038: @98103
35896 /* 98103 */ GIM_Reject,
35897 /* 98104 */ // Label 3034: @98104
35898 /* 98104 */ GIM_Reject,
35899 /* 98105 */ // Label 3027: @98105
35900 /* 98105 */ GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(98324),
35901 /* 98110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
35902 /* 98113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35903 /* 98117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3040*/ GIMT_Encode4(98176), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1337 //
35904 /* 98124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35905 /* 98128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
35906 /* 98132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
35907 /* 98136 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
35908 /* 98140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35909 /* 98145 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35910 /* 98150 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35911 /* 98152 */ // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
35912 /* 98152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64),
35913 /* 98155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35914 /* 98157 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35915 /* 98161 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35916 /* 98165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35917 /* 98168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35918 /* 98174 */ GIR_RootConstrainSelectedInstOperands,
35919 /* 98175 */ // GIR_Coverage, 1337,
35920 /* 98175 */ GIR_EraseRootFromParent_Done,
35921 /* 98176 */ // Label 3040: @98176
35922 /* 98176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3041*/ GIMT_Encode4(98235), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1340 //
35923 /* 98183 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35924 /* 98187 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35925 /* 98191 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
35926 /* 98195 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
35927 /* 98199 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35928 /* 98204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35929 /* 98209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35930 /* 98211 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
35931 /* 98211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
35932 /* 98214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35933 /* 98216 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35934 /* 98220 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35935 /* 98224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35936 /* 98227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35937 /* 98233 */ GIR_RootConstrainSelectedInstOperands,
35938 /* 98234 */ // GIR_Coverage, 1340,
35939 /* 98234 */ GIR_EraseRootFromParent_Done,
35940 /* 98235 */ // Label 3041: @98235
35941 /* 98235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3042*/ GIMT_Encode4(98294), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2969 //
35942 /* 98242 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35943 /* 98246 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35944 /* 98250 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
35945 /* 98254 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
35946 /* 98258 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35947 /* 98263 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35948 /* 98268 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35949 /* 98270 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)
35950 /* 98270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
35951 /* 98273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35952 /* 98275 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
35953 /* 98279 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
35954 /* 98283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35955 /* 98286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35956 /* 98292 */ GIR_RootConstrainSelectedInstOperands,
35957 /* 98293 */ // GIR_Coverage, 2969,
35958 /* 98293 */ GIR_EraseRootFromParent_Done,
35959 /* 98294 */ // Label 3042: @98294
35960 /* 98294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3043*/ GIMT_Encode4(98323), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1765 //
35961 /* 98301 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35962 /* 98305 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
35963 /* 98305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
35964 /* 98308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35965 /* 98310 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35966 /* 98312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35967 /* 98315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35968 /* 98321 */ GIR_RootConstrainSelectedInstOperands,
35969 /* 98322 */ // GIR_Coverage, 1765,
35970 /* 98322 */ GIR_EraseRootFromParent_Done,
35971 /* 98323 */ // Label 3043: @98323
35972 /* 98323 */ GIM_Reject,
35973 /* 98324 */ // Label 3039: @98324
35974 /* 98324 */ GIM_Reject,
35975 /* 98325 */ // Label 3028: @98325
35976 /* 98325 */ GIM_Reject,
35977 /* 98326 */ // Label 31: @98326
35978 /* 98326 */ GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(98537),
35979 /* 98331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35980 /* 98334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35981 /* 98337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35982 /* 98340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3045*/ GIMT_Encode4(98396), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 469 //
35983 /* 98347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35984 /* 98351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35985 /* 98355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35986 /* 98359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35987 /* 98363 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
35988 /* 98367 */ // MIs[1] Operand 1
35989 /* 98367 */ // No operand predicates
35990 /* 98367 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35991 /* 98369 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
35992 /* 98369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri),
35993 /* 98372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35994 /* 98374 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
35995 /* 98376 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35996 /* 98379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35997 /* 98382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35998 /* 98388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35999 /* 98394 */ GIR_RootConstrainSelectedInstOperands,
36000 /* 98395 */ // GIR_Coverage, 469,
36001 /* 98395 */ GIR_EraseRootFromParent_Done,
36002 /* 98396 */ // Label 3045: @98396
36003 /* 98396 */ GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(98491),
36004 /* 98401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36005 /* 98405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36006 /* 98409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3047*/ GIMT_Encode4(98453), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 317 //
36007 /* 98416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
36008 /* 98420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36009 /* 98424 */ // MIs[1] Operand 1
36010 /* 98424 */ // No operand predicates
36011 /* 98424 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36012 /* 98426 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5)
36013 /* 98426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri),
36014 /* 98429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36015 /* 98431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36016 /* 98437 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36017 /* 98439 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5
36018 /* 98442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36019 /* 98445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36020 /* 98451 */ GIR_RootConstrainSelectedInstOperands,
36021 /* 98452 */ // GIR_Coverage, 317,
36022 /* 98452 */ GIR_EraseRootFromParent_Done,
36023 /* 98453 */ // Label 3047: @98453
36024 /* 98453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3048*/ GIMT_Encode4(98490), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 318 //
36025 /* 98460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36026 /* 98464 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
36027 /* 98464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr),
36028 /* 98467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
36029 /* 98469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36030 /* 98475 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36031 /* 98477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36032 /* 98479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36033 /* 98482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36034 /* 98488 */ GIR_RootConstrainSelectedInstOperands,
36035 /* 98489 */ // GIR_Coverage, 318,
36036 /* 98489 */ GIR_EraseRootFromParent_Done,
36037 /* 98490 */ // Label 3048: @98490
36038 /* 98490 */ GIM_Reject,
36039 /* 98491 */ // Label 3046: @98491
36040 /* 98491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3049*/ GIMT_Encode4(98536), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 470 //
36041 /* 98498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36042 /* 98502 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36043 /* 98506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36044 /* 98510 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36045 /* 98510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr),
36046 /* 98513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36047 /* 98515 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36048 /* 98517 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36049 /* 98519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36050 /* 98522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36051 /* 98528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36052 /* 98534 */ GIR_RootConstrainSelectedInstOperands,
36053 /* 98535 */ // GIR_Coverage, 470,
36054 /* 98535 */ GIR_EraseRootFromParent_Done,
36055 /* 98536 */ // Label 3049: @98536
36056 /* 98536 */ GIM_Reject,
36057 /* 98537 */ // Label 3044: @98537
36058 /* 98537 */ GIM_Reject,
36059 /* 98538 */ // Label 32: @98538
36060 /* 98538 */ GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(98643),
36061 /* 98543 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36062 /* 98546 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36063 /* 98549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36064 /* 98552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3051*/ GIMT_Encode4(98597), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 320 //
36065 /* 98559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36066 /* 98563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36067 /* 98567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36068 /* 98571 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
36069 /* 98571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr),
36070 /* 98574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
36071 /* 98576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36072 /* 98582 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36073 /* 98584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36074 /* 98586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36075 /* 98589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36076 /* 98595 */ GIR_RootConstrainSelectedInstOperands,
36077 /* 98596 */ // GIR_Coverage, 320,
36078 /* 98596 */ GIR_EraseRootFromParent_Done,
36079 /* 98597 */ // Label 3051: @98597
36080 /* 98597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3052*/ GIMT_Encode4(98642), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 472 //
36081 /* 98604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36082 /* 98608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36083 /* 98612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36084 /* 98616 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36085 /* 98616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr),
36086 /* 98619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36087 /* 98621 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36088 /* 98623 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36089 /* 98625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36090 /* 98628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36091 /* 98634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36092 /* 98640 */ GIR_RootConstrainSelectedInstOperands,
36093 /* 98641 */ // GIR_Coverage, 472,
36094 /* 98641 */ GIR_EraseRootFromParent_Done,
36095 /* 98642 */ // Label 3052: @98642
36096 /* 98642 */ GIM_Reject,
36097 /* 98643 */ // Label 3050: @98643
36098 /* 98643 */ GIM_Reject,
36099 /* 98644 */ // Label 33: @98644
36100 /* 98644 */ GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(98911),
36101 /* 98649 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36102 /* 98652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36103 /* 98655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36104 /* 98658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3054*/ GIMT_Encode4(98712), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 200 //
36105 /* 98665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36106 /* 98669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36107 /* 98673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36108 /* 98677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36109 /* 98681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36110 /* 98686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36111 /* 98690 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36112 /* 98692 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
36113 /* 98692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
36114 /* 98695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36115 /* 98697 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36116 /* 98701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36117 /* 98704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36118 /* 98710 */ GIR_RootConstrainSelectedInstOperands,
36119 /* 98711 */ // GIR_Coverage, 200,
36120 /* 98711 */ GIR_EraseRootFromParent_Done,
36121 /* 98712 */ // Label 3054: @98712
36122 /* 98712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3055*/ GIMT_Encode4(98766), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 327 //
36123 /* 98719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36124 /* 98723 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36125 /* 98727 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36126 /* 98731 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36127 /* 98735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36128 /* 98740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36129 /* 98744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36130 /* 98746 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
36131 /* 98746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH),
36132 /* 98749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36133 /* 98751 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36134 /* 98755 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36135 /* 98758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36136 /* 98764 */ GIR_RootConstrainSelectedInstOperands,
36137 /* 98765 */ // GIR_Coverage, 327,
36138 /* 98765 */ GIR_EraseRootFromParent_Done,
36139 /* 98766 */ // Label 3055: @98766
36140 /* 98766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3056*/ GIMT_Encode4(98820), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 537 //
36141 /* 98773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36142 /* 98777 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36143 /* 98781 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36144 /* 98785 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36145 /* 98789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36146 /* 98794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36147 /* 98798 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36148 /* 98800 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
36149 /* 98800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
36150 /* 98803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36151 /* 98805 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36152 /* 98809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36153 /* 98812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36154 /* 98818 */ GIR_RootConstrainSelectedInstOperands,
36155 /* 98819 */ // GIR_Coverage, 537,
36156 /* 98819 */ GIR_EraseRootFromParent_Done,
36157 /* 98820 */ // Label 3056: @98820
36158 /* 98820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3057*/ GIMT_Encode4(98865), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 311 //
36159 /* 98827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36160 /* 98831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36161 /* 98835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36162 /* 98839 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
36163 /* 98839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr),
36164 /* 98842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
36165 /* 98844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36166 /* 98850 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36167 /* 98852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36168 /* 98854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36169 /* 98857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36170 /* 98863 */ GIR_RootConstrainSelectedInstOperands,
36171 /* 98864 */ // GIR_Coverage, 311,
36172 /* 98864 */ GIR_EraseRootFromParent_Done,
36173 /* 98865 */ // Label 3057: @98865
36174 /* 98865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3058*/ GIMT_Encode4(98910), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 474 //
36175 /* 98872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36176 /* 98876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36177 /* 98880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36178 /* 98884 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36179 /* 98884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr),
36180 /* 98887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36181 /* 98889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36182 /* 98891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36183 /* 98893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36184 /* 98896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36185 /* 98902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36186 /* 98908 */ GIR_RootConstrainSelectedInstOperands,
36187 /* 98909 */ // GIR_Coverage, 474,
36188 /* 98909 */ GIR_EraseRootFromParent_Done,
36189 /* 98910 */ // Label 3058: @98910
36190 /* 98910 */ GIM_Reject,
36191 /* 98911 */ // Label 3053: @98911
36192 /* 98911 */ GIM_Reject,
36193 /* 98912 */ // Label 34: @98912
36194 /* 98912 */ GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(99237),
36195 /* 98917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36196 /* 98920 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36197 /* 98923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36198 /* 98926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3060*/ GIMT_Encode4(98980), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 199 //
36199 /* 98933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36200 /* 98937 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36201 /* 98941 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36202 /* 98945 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36203 /* 98949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36204 /* 98954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36205 /* 98958 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36206 /* 98960 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
36207 /* 98960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16),
36208 /* 98963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36209 /* 98965 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36210 /* 98969 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36211 /* 98972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36212 /* 98978 */ GIR_RootConstrainSelectedInstOperands,
36213 /* 98979 */ // GIR_Coverage, 199,
36214 /* 98979 */ GIR_EraseRootFromParent_Done,
36215 /* 98980 */ // Label 3060: @98980
36216 /* 98980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3061*/ GIMT_Encode4(99034), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 326 //
36217 /* 98987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36218 /* 98991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36219 /* 98995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36220 /* 98999 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36221 /* 99003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36222 /* 99008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36223 /* 99012 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36224 /* 99014 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
36225 /* 99014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16),
36226 /* 99017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36227 /* 99019 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36228 /* 99023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36229 /* 99026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36230 /* 99032 */ GIR_RootConstrainSelectedInstOperands,
36231 /* 99033 */ // GIR_Coverage, 326,
36232 /* 99033 */ GIR_EraseRootFromParent_Done,
36233 /* 99034 */ // Label 3061: @99034
36234 /* 99034 */ GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(99146),
36235 /* 99039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36236 /* 99043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3063*/ GIMT_Encode4(99093), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 536 //
36237 /* 99050 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36238 /* 99054 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36239 /* 99058 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36240 /* 99062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36241 /* 99067 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36242 /* 99071 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36243 /* 99073 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
36244 /* 99073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16),
36245 /* 99076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36246 /* 99078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36247 /* 99082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36248 /* 99085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36249 /* 99091 */ GIR_RootConstrainSelectedInstOperands,
36250 /* 99092 */ // GIR_Coverage, 536,
36251 /* 99092 */ GIR_EraseRootFromParent_Done,
36252 /* 99093 */ // Label 3063: @99093
36253 /* 99093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3064*/ GIMT_Encode4(99145), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 475 //
36254 /* 99100 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36255 /* 99104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
36256 /* 99108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36257 /* 99112 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
36258 /* 99116 */ // MIs[1] Operand 1
36259 /* 99116 */ // No operand predicates
36260 /* 99116 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36261 /* 99118 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
36262 /* 99118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri),
36263 /* 99121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36264 /* 99123 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36265 /* 99125 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
36266 /* 99128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36267 /* 99131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36268 /* 99137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36269 /* 99143 */ GIR_RootConstrainSelectedInstOperands,
36270 /* 99144 */ // GIR_Coverage, 475,
36271 /* 99144 */ GIR_EraseRootFromParent_Done,
36272 /* 99145 */ // Label 3064: @99145
36273 /* 99145 */ GIM_Reject,
36274 /* 99146 */ // Label 3062: @99146
36275 /* 99146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3065*/ GIMT_Encode4(99191), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 328 //
36276 /* 99153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36277 /* 99157 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36278 /* 99161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36279 /* 99165 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
36280 /* 99165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR),
36281 /* 99168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
36282 /* 99170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36283 /* 99176 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36284 /* 99178 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36285 /* 99180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36286 /* 99183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36287 /* 99189 */ GIR_RootConstrainSelectedInstOperands,
36288 /* 99190 */ // GIR_Coverage, 328,
36289 /* 99190 */ GIR_EraseRootFromParent_Done,
36290 /* 99191 */ // Label 3065: @99191
36291 /* 99191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3066*/ GIMT_Encode4(99236), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 476 //
36292 /* 99198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36293 /* 99202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36294 /* 99206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36295 /* 99210 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36296 /* 99210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr),
36297 /* 99213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36298 /* 99215 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36299 /* 99217 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36300 /* 99219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36301 /* 99222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36302 /* 99228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36303 /* 99234 */ GIR_RootConstrainSelectedInstOperands,
36304 /* 99235 */ // GIR_Coverage, 476,
36305 /* 99235 */ GIR_EraseRootFromParent_Done,
36306 /* 99236 */ // Label 3066: @99236
36307 /* 99236 */ GIM_Reject,
36308 /* 99237 */ // Label 3059: @99237
36309 /* 99237 */ GIM_Reject,
36310 /* 99238 */ // Label 35: @99238
36311 /* 99238 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 3070*/ GIMT_Encode4(99470),
36312 /* 99249 */ /*GILLT_v16s8*//*Label 3067*/ GIMT_Encode4(99269), GIMT_Encode4(0),
36313 /* 99257 */ /*GILLT_v8s16*//*Label 3068*/ GIMT_Encode4(99336), GIMT_Encode4(0),
36314 /* 99265 */ /*GILLT_v4s32*//*Label 3069*/ GIMT_Encode4(99403),
36315 /* 99269 */ // Label 3067: @99269
36316 /* 99269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3071*/ GIMT_Encode4(99335), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4967 //
36317 /* 99276 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36318 /* 99279 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36319 /* 99282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36320 /* 99286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36321 /* 99290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36322 /* 99294 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36323 /* 99294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36324 /* 99297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36325 /* 99301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36326 /* 99306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
36327 /* 99309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36328 /* 99311 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36329 /* 99313 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36330 /* 99315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36331 /* 99318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36332 /* 99324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36333 /* 99330 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36334 /* 99333 */ GIR_RootConstrainSelectedInstOperands,
36335 /* 99334 */ // GIR_Coverage, 4967,
36336 /* 99334 */ GIR_EraseRootFromParent_Done,
36337 /* 99335 */ // Label 3071: @99335
36338 /* 99335 */ GIM_Reject,
36339 /* 99336 */ // Label 3068: @99336
36340 /* 99336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3072*/ GIMT_Encode4(99402), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4971 //
36341 /* 99343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36342 /* 99346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36343 /* 99349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36344 /* 99353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36345 /* 99357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36346 /* 99361 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36347 /* 99361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36348 /* 99364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36349 /* 99368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36350 /* 99373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
36351 /* 99376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36352 /* 99378 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36353 /* 99380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36354 /* 99382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36355 /* 99385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36356 /* 99391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36357 /* 99397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36358 /* 99400 */ GIR_RootConstrainSelectedInstOperands,
36359 /* 99401 */ // GIR_Coverage, 4971,
36360 /* 99401 */ GIR_EraseRootFromParent_Done,
36361 /* 99402 */ // Label 3072: @99402
36362 /* 99402 */ GIM_Reject,
36363 /* 99403 */ // Label 3069: @99403
36364 /* 99403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3073*/ GIMT_Encode4(99469), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4975 //
36365 /* 99410 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
36366 /* 99413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36367 /* 99416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36368 /* 99420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36369 /* 99424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36370 /* 99428 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
36371 /* 99428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36372 /* 99431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36373 /* 99435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36374 /* 99440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
36375 /* 99443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36376 /* 99445 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36377 /* 99447 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36378 /* 99449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36379 /* 99452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36380 /* 99458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36381 /* 99464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36382 /* 99467 */ GIR_RootConstrainSelectedInstOperands,
36383 /* 99468 */ // GIR_Coverage, 4975,
36384 /* 99468 */ GIR_EraseRootFromParent_Done,
36385 /* 99469 */ // Label 3073: @99469
36386 /* 99469 */ GIM_Reject,
36387 /* 99470 */ // Label 3070: @99470
36388 /* 99470 */ GIM_Reject,
36389 /* 99471 */ // Label 36: @99471
36390 /* 99471 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3078*/ GIMT_Encode4(99822),
36391 /* 99482 */ /*GILLT_s32*//*Label 3074*/ GIMT_Encode4(99530), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
36392 /* 99510 */ /*GILLT_v16s8*//*Label 3075*/ GIMT_Encode4(99621), GIMT_Encode4(0),
36393 /* 99518 */ /*GILLT_v8s16*//*Label 3076*/ GIMT_Encode4(99688), GIMT_Encode4(0),
36394 /* 99526 */ /*GILLT_v4s32*//*Label 3077*/ GIMT_Encode4(99755),
36395 /* 99530 */ // Label 3074: @99530
36396 /* 99530 */ GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(99620),
36397 /* 99535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36398 /* 99538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36399 /* 99541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3080*/ GIMT_Encode4(99580), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 177 //
36400 /* 99548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36401 /* 99552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36402 /* 99556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36403 /* 99560 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
36404 /* 99560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL),
36405 /* 99563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36406 /* 99565 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36407 /* 99567 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36408 /* 99569 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36409 /* 99572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36410 /* 99578 */ GIR_RootConstrainSelectedInstOperands,
36411 /* 99579 */ // GIR_Coverage, 177,
36412 /* 99579 */ GIR_EraseRootFromParent_Done,
36413 /* 99580 */ // Label 3080: @99580
36414 /* 99580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3081*/ GIMT_Encode4(99619), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 506 //
36415 /* 99587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36416 /* 99591 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36417 /* 99595 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36418 /* 99599 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36419 /* 99599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL),
36420 /* 99602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36421 /* 99604 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36422 /* 99606 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36423 /* 99608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36424 /* 99611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36425 /* 99617 */ GIR_RootConstrainSelectedInstOperands,
36426 /* 99618 */ // GIR_Coverage, 506,
36427 /* 99618 */ GIR_EraseRootFromParent_Done,
36428 /* 99619 */ // Label 3081: @99619
36429 /* 99619 */ GIM_Reject,
36430 /* 99620 */ // Label 3079: @99620
36431 /* 99620 */ GIM_Reject,
36432 /* 99621 */ // Label 3075: @99621
36433 /* 99621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3082*/ GIMT_Encode4(99687), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4956 //
36434 /* 99628 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36435 /* 99631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36436 /* 99634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36437 /* 99638 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36438 /* 99642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36439 /* 99646 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36440 /* 99646 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36441 /* 99649 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36442 /* 99653 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36443 /* 99658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
36444 /* 99661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36445 /* 99663 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36446 /* 99665 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36447 /* 99667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36448 /* 99670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36449 /* 99676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36450 /* 99682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36451 /* 99685 */ GIR_RootConstrainSelectedInstOperands,
36452 /* 99686 */ // GIR_Coverage, 4956,
36453 /* 99686 */ GIR_EraseRootFromParent_Done,
36454 /* 99687 */ // Label 3082: @99687
36455 /* 99687 */ GIM_Reject,
36456 /* 99688 */ // Label 3076: @99688
36457 /* 99688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3083*/ GIMT_Encode4(99754), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4959 //
36458 /* 99695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36459 /* 99698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36460 /* 99701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36461 /* 99705 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36462 /* 99709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36463 /* 99713 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36464 /* 99713 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36465 /* 99716 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36466 /* 99720 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36467 /* 99725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
36468 /* 99728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36469 /* 99730 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36470 /* 99732 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36471 /* 99734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36472 /* 99737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36473 /* 99743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36474 /* 99749 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36475 /* 99752 */ GIR_RootConstrainSelectedInstOperands,
36476 /* 99753 */ // GIR_Coverage, 4959,
36477 /* 99753 */ GIR_EraseRootFromParent_Done,
36478 /* 99754 */ // Label 3083: @99754
36479 /* 99754 */ GIM_Reject,
36480 /* 99755 */ // Label 3077: @99755
36481 /* 99755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3084*/ GIMT_Encode4(99821), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4963 //
36482 /* 99762 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
36483 /* 99765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36484 /* 99768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36485 /* 99772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36486 /* 99776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36487 /* 99780 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
36488 /* 99780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36489 /* 99783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36490 /* 99787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36491 /* 99792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
36492 /* 99795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36493 /* 99797 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36494 /* 99799 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36495 /* 99801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36496 /* 99804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36497 /* 99810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36498 /* 99816 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36499 /* 99819 */ GIR_RootConstrainSelectedInstOperands,
36500 /* 99820 */ // GIR_Coverage, 4963,
36501 /* 99820 */ GIR_EraseRootFromParent_Done,
36502 /* 99821 */ // Label 3084: @99821
36503 /* 99821 */ GIM_Reject,
36504 /* 99822 */ // Label 3078: @99822
36505 /* 99822 */ GIM_Reject,
36506 /* 99823 */ // Label 37: @99823
36507 /* 99823 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3093*/ GIMT_Encode4(100448),
36508 /* 99834 */ /*GILLT_s64*//*Label 3085*/ GIMT_Encode4(99882), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
36509 /* 99854 */ /*GILLT_v8s8*//*Label 3086*/ GIMT_Encode4(99928),
36510 /* 99858 */ /*GILLT_v16s8*//*Label 3087*/ GIMT_Encode4(99974),
36511 /* 99862 */ /*GILLT_v4s16*//*Label 3088*/ GIMT_Encode4(100086),
36512 /* 99866 */ /*GILLT_v8s16*//*Label 3089*/ GIMT_Encode4(100132),
36513 /* 99870 */ /*GILLT_v2s32*//*Label 3090*/ GIMT_Encode4(100244),
36514 /* 99874 */ /*GILLT_v4s32*//*Label 3091*/ GIMT_Encode4(100290),
36515 /* 99878 */ /*GILLT_v2s64*//*Label 3092*/ GIMT_Encode4(100402),
36516 /* 99882 */ // Label 3085: @99882
36517 /* 99882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3094*/ GIMT_Encode4(99927), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 950 //
36518 /* 99889 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
36519 /* 99892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
36520 /* 99895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36521 /* 99899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36522 /* 99903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36523 /* 99907 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
36524 /* 99907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64),
36525 /* 99910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36526 /* 99912 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36527 /* 99914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36528 /* 99916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36529 /* 99919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36530 /* 99925 */ GIR_RootConstrainSelectedInstOperands,
36531 /* 99926 */ // GIR_Coverage, 950,
36532 /* 99926 */ GIR_EraseRootFromParent_Done,
36533 /* 99927 */ // Label 3094: @99927
36534 /* 99927 */ GIM_Reject,
36535 /* 99928 */ // Label 3086: @99928
36536 /* 99928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3095*/ GIMT_Encode4(99973), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 948 //
36537 /* 99935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
36538 /* 99938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
36539 /* 99941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36540 /* 99945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36541 /* 99949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36542 /* 99953 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
36543 /* 99953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8),
36544 /* 99956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36545 /* 99958 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36546 /* 99960 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36547 /* 99962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36548 /* 99965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36549 /* 99971 */ GIR_RootConstrainSelectedInstOperands,
36550 /* 99972 */ // GIR_Coverage, 948,
36551 /* 99972 */ GIR_EraseRootFromParent_Done,
36552 /* 99973 */ // Label 3095: @99973
36553 /* 99973 */ GIM_Reject,
36554 /* 99974 */ // Label 3087: @99974
36555 /* 99974 */ GIM_Try, /*On fail goto*//*Label 3096*/ GIMT_Encode4(100085),
36556 /* 99979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36557 /* 99982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36558 /* 99985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3097*/ GIMT_Encode4(100024), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 949 //
36559 /* 99992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36560 /* 99996 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36561 /* 100000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36562 /* 100004 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
36563 /* 100004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8),
36564 /* 100007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36565 /* 100009 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36566 /* 100011 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36567 /* 100013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36568 /* 100016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36569 /* 100022 */ GIR_RootConstrainSelectedInstOperands,
36570 /* 100023 */ // GIR_Coverage, 949,
36571 /* 100023 */ GIR_EraseRootFromParent_Done,
36572 /* 100024 */ // Label 3097: @100024
36573 /* 100024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3098*/ GIMT_Encode4(100084), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3918 //
36574 /* 100031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36575 /* 100035 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36576 /* 100039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36577 /* 100043 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36578 /* 100043 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36579 /* 100046 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36580 /* 100050 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36581 /* 100055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8),
36582 /* 100058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36583 /* 100060 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36584 /* 100062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36585 /* 100064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36586 /* 100067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36587 /* 100073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36588 /* 100079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36589 /* 100082 */ GIR_RootConstrainSelectedInstOperands,
36590 /* 100083 */ // GIR_Coverage, 3918,
36591 /* 100083 */ GIR_EraseRootFromParent_Done,
36592 /* 100084 */ // Label 3098: @100084
36593 /* 100084 */ GIM_Reject,
36594 /* 100085 */ // Label 3096: @100085
36595 /* 100085 */ GIM_Reject,
36596 /* 100086 */ // Label 3088: @100086
36597 /* 100086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3099*/ GIMT_Encode4(100131), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 944 //
36598 /* 100093 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
36599 /* 100096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
36600 /* 100099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36601 /* 100103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36602 /* 100107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36603 /* 100111 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
36604 /* 100111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16),
36605 /* 100114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36606 /* 100116 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36607 /* 100118 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36608 /* 100120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36609 /* 100123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36610 /* 100129 */ GIR_RootConstrainSelectedInstOperands,
36611 /* 100130 */ // GIR_Coverage, 944,
36612 /* 100130 */ GIR_EraseRootFromParent_Done,
36613 /* 100131 */ // Label 3099: @100131
36614 /* 100131 */ GIM_Reject,
36615 /* 100132 */ // Label 3089: @100132
36616 /* 100132 */ GIM_Try, /*On fail goto*//*Label 3100*/ GIMT_Encode4(100243),
36617 /* 100137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36618 /* 100140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36619 /* 100143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3101*/ GIMT_Encode4(100182), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 946 //
36620 /* 100150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36621 /* 100154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36622 /* 100158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36623 /* 100162 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
36624 /* 100162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16),
36625 /* 100165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36626 /* 100167 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36627 /* 100169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36628 /* 100171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36629 /* 100174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36630 /* 100180 */ GIR_RootConstrainSelectedInstOperands,
36631 /* 100181 */ // GIR_Coverage, 946,
36632 /* 100181 */ GIR_EraseRootFromParent_Done,
36633 /* 100182 */ // Label 3101: @100182
36634 /* 100182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3102*/ GIMT_Encode4(100242), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3921 //
36635 /* 100189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36636 /* 100193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36637 /* 100197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36638 /* 100201 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36639 /* 100201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36640 /* 100204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36641 /* 100208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36642 /* 100213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16),
36643 /* 100216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36644 /* 100218 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36645 /* 100220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36646 /* 100222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36647 /* 100225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36648 /* 100231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36649 /* 100237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36650 /* 100240 */ GIR_RootConstrainSelectedInstOperands,
36651 /* 100241 */ // GIR_Coverage, 3921,
36652 /* 100241 */ GIR_EraseRootFromParent_Done,
36653 /* 100242 */ // Label 3102: @100242
36654 /* 100242 */ GIM_Reject,
36655 /* 100243 */ // Label 3100: @100243
36656 /* 100243 */ GIM_Reject,
36657 /* 100244 */ // Label 3090: @100244
36658 /* 100244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3103*/ GIMT_Encode4(100289), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 945 //
36659 /* 100251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
36660 /* 100254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
36661 /* 100257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36662 /* 100261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36663 /* 100265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36664 /* 100269 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
36665 /* 100269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32),
36666 /* 100272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36667 /* 100274 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36668 /* 100276 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36669 /* 100278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36670 /* 100281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36671 /* 100287 */ GIR_RootConstrainSelectedInstOperands,
36672 /* 100288 */ // GIR_Coverage, 945,
36673 /* 100288 */ GIR_EraseRootFromParent_Done,
36674 /* 100289 */ // Label 3103: @100289
36675 /* 100289 */ GIM_Reject,
36676 /* 100290 */ // Label 3091: @100290
36677 /* 100290 */ GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(100401),
36678 /* 100295 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
36679 /* 100298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36680 /* 100301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3105*/ GIMT_Encode4(100340), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 947 //
36681 /* 100308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36682 /* 100312 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36683 /* 100316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36684 /* 100320 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
36685 /* 100320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32),
36686 /* 100323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36687 /* 100325 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36688 /* 100327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36689 /* 100329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36690 /* 100332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36691 /* 100338 */ GIR_RootConstrainSelectedInstOperands,
36692 /* 100339 */ // GIR_Coverage, 947,
36693 /* 100339 */ GIR_EraseRootFromParent_Done,
36694 /* 100340 */ // Label 3105: @100340
36695 /* 100340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3106*/ GIMT_Encode4(100400), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3924 //
36696 /* 100347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36697 /* 100351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36698 /* 100355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36699 /* 100359 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
36700 /* 100359 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36701 /* 100362 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36702 /* 100366 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36703 /* 100371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32),
36704 /* 100374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36705 /* 100376 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36706 /* 100378 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36707 /* 100380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36708 /* 100383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36709 /* 100389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36710 /* 100395 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36711 /* 100398 */ GIR_RootConstrainSelectedInstOperands,
36712 /* 100399 */ // GIR_Coverage, 3924,
36713 /* 100399 */ GIR_EraseRootFromParent_Done,
36714 /* 100400 */ // Label 3106: @100400
36715 /* 100400 */ GIM_Reject,
36716 /* 100401 */ // Label 3104: @100401
36717 /* 100401 */ GIM_Reject,
36718 /* 100402 */ // Label 3092: @100402
36719 /* 100402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3107*/ GIMT_Encode4(100447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 951 //
36720 /* 100409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
36721 /* 100412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36722 /* 100415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36723 /* 100419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36724 /* 100423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36725 /* 100427 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
36726 /* 100427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64),
36727 /* 100430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36728 /* 100432 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36729 /* 100434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36730 /* 100436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36731 /* 100439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36732 /* 100445 */ GIR_RootConstrainSelectedInstOperands,
36733 /* 100446 */ // GIR_Coverage, 951,
36734 /* 100446 */ GIR_EraseRootFromParent_Done,
36735 /* 100447 */ // Label 3107: @100447
36736 /* 100447 */ GIM_Reject,
36737 /* 100448 */ // Label 3093: @100448
36738 /* 100448 */ GIM_Reject,
36739 /* 100449 */ // Label 38: @100449
36740 /* 100449 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3117*/ GIMT_Encode4(101721),
36741 /* 100460 */ /*GILLT_s32*//*Label 3108*/ GIMT_Encode4(100512),
36742 /* 100464 */ /*GILLT_s64*//*Label 3109*/ GIMT_Encode4(100847), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
36743 /* 100484 */ /*GILLT_v8s8*//*Label 3110*/ GIMT_Encode4(100893),
36744 /* 100488 */ /*GILLT_v16s8*//*Label 3111*/ GIMT_Encode4(100939),
36745 /* 100492 */ /*GILLT_v4s16*//*Label 3112*/ GIMT_Encode4(101051),
36746 /* 100496 */ /*GILLT_v8s16*//*Label 3113*/ GIMT_Encode4(101097),
36747 /* 100500 */ /*GILLT_v2s32*//*Label 3114*/ GIMT_Encode4(101209),
36748 /* 100504 */ /*GILLT_v4s32*//*Label 3115*/ GIMT_Encode4(101255),
36749 /* 100508 */ /*GILLT_v2s64*//*Label 3116*/ GIMT_Encode4(101521),
36750 /* 100512 */ // Label 3108: @100512
36751 /* 100512 */ GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(100846),
36752 /* 100517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36753 /* 100520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36754 /* 100523 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3119*/ GIMT_Encode4(100584), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 6254 //
36755 /* 100530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36756 /* 100534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36757 /* 100538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36758 /* 100542 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36759 /* 100546 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36760 /* 100551 */ // MIs[1] Rn
36761 /* 100551 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36762 /* 100556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36763 /* 100560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36764 /* 100562 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36765 /* 100562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
36766 /* 100565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36767 /* 100567 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36768 /* 100569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36769 /* 100573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36770 /* 100576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36771 /* 100582 */ GIR_RootConstrainSelectedInstOperands,
36772 /* 100583 */ // GIR_Coverage, 6254,
36773 /* 100583 */ GIR_EraseRootFromParent_Done,
36774 /* 100584 */ // Label 3119: @100584
36775 /* 100584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3120*/ GIMT_Encode4(100645), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6294 //
36776 /* 100591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36777 /* 100595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36778 /* 100599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36779 /* 100603 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36780 /* 100607 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36781 /* 100612 */ // MIs[1] Rn
36782 /* 100612 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36783 /* 100617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36784 /* 100621 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36785 /* 100623 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36786 /* 100623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
36787 /* 100626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36788 /* 100628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36789 /* 100630 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36790 /* 100634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36791 /* 100637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36792 /* 100643 */ GIR_RootConstrainSelectedInstOperands,
36793 /* 100644 */ // GIR_Coverage, 6294,
36794 /* 100644 */ GIR_EraseRootFromParent_Done,
36795 /* 100645 */ // Label 3120: @100645
36796 /* 100645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3121*/ GIMT_Encode4(100706), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2058 //
36797 /* 100652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36798 /* 100656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36799 /* 100660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
36800 /* 100664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36801 /* 100668 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36802 /* 100672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36803 /* 100677 */ // MIs[1] Rn
36804 /* 100677 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36805 /* 100682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36806 /* 100684 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36807 /* 100684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
36808 /* 100687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36809 /* 100689 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36810 /* 100691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36811 /* 100695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36812 /* 100698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36813 /* 100704 */ GIR_RootConstrainSelectedInstOperands,
36814 /* 100705 */ // GIR_Coverage, 2058,
36815 /* 100705 */ GIR_EraseRootFromParent_Done,
36816 /* 100706 */ // Label 3121: @100706
36817 /* 100706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3122*/ GIMT_Encode4(100767), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2332 //
36818 /* 100713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36819 /* 100717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36820 /* 100721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
36821 /* 100725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36822 /* 100729 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36823 /* 100733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36824 /* 100738 */ // MIs[1] Rn
36825 /* 100738 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36826 /* 100743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36827 /* 100745 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36828 /* 100745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
36829 /* 100748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36830 /* 100750 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36831 /* 100752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36832 /* 100756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36833 /* 100759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36834 /* 100765 */ GIR_RootConstrainSelectedInstOperands,
36835 /* 100766 */ // GIR_Coverage, 2332,
36836 /* 100766 */ GIR_EraseRootFromParent_Done,
36837 /* 100767 */ // Label 3122: @100767
36838 /* 100767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3123*/ GIMT_Encode4(100806), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2056 //
36839 /* 100774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36840 /* 100778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36841 /* 100782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36842 /* 100786 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
36843 /* 100786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
36844 /* 100789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36845 /* 100791 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
36846 /* 100793 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
36847 /* 100795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36848 /* 100798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36849 /* 100804 */ GIR_RootConstrainSelectedInstOperands,
36850 /* 100805 */ // GIR_Coverage, 2056,
36851 /* 100805 */ GIR_EraseRootFromParent_Done,
36852 /* 100806 */ // Label 3123: @100806
36853 /* 100806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3124*/ GIMT_Encode4(100845), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2330 //
36854 /* 100813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36855 /* 100817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36856 /* 100821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36857 /* 100825 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36858 /* 100825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
36859 /* 100828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36860 /* 100830 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36861 /* 100832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36862 /* 100834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36863 /* 100837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36864 /* 100843 */ GIR_RootConstrainSelectedInstOperands,
36865 /* 100844 */ // GIR_Coverage, 2330,
36866 /* 100844 */ GIR_EraseRootFromParent_Done,
36867 /* 100845 */ // Label 3124: @100845
36868 /* 100845 */ GIM_Reject,
36869 /* 100846 */ // Label 3118: @100846
36870 /* 100846 */ GIM_Reject,
36871 /* 100847 */ // Label 3109: @100847
36872 /* 100847 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3125*/ GIMT_Encode4(100892), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 942 //
36873 /* 100854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
36874 /* 100857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
36875 /* 100860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36876 /* 100864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36877 /* 100868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36878 /* 100872 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
36879 /* 100872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64),
36880 /* 100875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36881 /* 100877 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36882 /* 100879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36883 /* 100881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36884 /* 100884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36885 /* 100890 */ GIR_RootConstrainSelectedInstOperands,
36886 /* 100891 */ // GIR_Coverage, 942,
36887 /* 100891 */ GIR_EraseRootFromParent_Done,
36888 /* 100892 */ // Label 3125: @100892
36889 /* 100892 */ GIM_Reject,
36890 /* 100893 */ // Label 3110: @100893
36891 /* 100893 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3126*/ GIMT_Encode4(100938), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 940 //
36892 /* 100900 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
36893 /* 100903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
36894 /* 100906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36895 /* 100910 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36896 /* 100914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36897 /* 100918 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
36898 /* 100918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8),
36899 /* 100921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36900 /* 100923 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36901 /* 100925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36902 /* 100927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36903 /* 100930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36904 /* 100936 */ GIR_RootConstrainSelectedInstOperands,
36905 /* 100937 */ // GIR_Coverage, 940,
36906 /* 100937 */ GIR_EraseRootFromParent_Done,
36907 /* 100938 */ // Label 3126: @100938
36908 /* 100938 */ GIM_Reject,
36909 /* 100939 */ // Label 3111: @100939
36910 /* 100939 */ GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(101050),
36911 /* 100944 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36912 /* 100947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36913 /* 100950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3128*/ GIMT_Encode4(100989), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 941 //
36914 /* 100957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36915 /* 100961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36916 /* 100965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36917 /* 100969 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
36918 /* 100969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8),
36919 /* 100972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36920 /* 100974 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36921 /* 100976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36922 /* 100978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36923 /* 100981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36924 /* 100987 */ GIR_RootConstrainSelectedInstOperands,
36925 /* 100988 */ // GIR_Coverage, 941,
36926 /* 100988 */ GIR_EraseRootFromParent_Done,
36927 /* 100989 */ // Label 3128: @100989
36928 /* 100989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3129*/ GIMT_Encode4(101049), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3909 //
36929 /* 100996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36930 /* 101000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36931 /* 101004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36932 /* 101008 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36933 /* 101008 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36934 /* 101011 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36935 /* 101015 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36936 /* 101020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8),
36937 /* 101023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36938 /* 101025 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36939 /* 101027 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36940 /* 101029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36941 /* 101032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36942 /* 101038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36943 /* 101044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36944 /* 101047 */ GIR_RootConstrainSelectedInstOperands,
36945 /* 101048 */ // GIR_Coverage, 3909,
36946 /* 101048 */ GIR_EraseRootFromParent_Done,
36947 /* 101049 */ // Label 3129: @101049
36948 /* 101049 */ GIM_Reject,
36949 /* 101050 */ // Label 3127: @101050
36950 /* 101050 */ GIM_Reject,
36951 /* 101051 */ // Label 3112: @101051
36952 /* 101051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3130*/ GIMT_Encode4(101096), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 936 //
36953 /* 101058 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
36954 /* 101061 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
36955 /* 101064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36956 /* 101068 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36957 /* 101072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36958 /* 101076 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
36959 /* 101076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16),
36960 /* 101079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36961 /* 101081 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36962 /* 101083 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36963 /* 101085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36964 /* 101088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36965 /* 101094 */ GIR_RootConstrainSelectedInstOperands,
36966 /* 101095 */ // GIR_Coverage, 936,
36967 /* 101095 */ GIR_EraseRootFromParent_Done,
36968 /* 101096 */ // Label 3130: @101096
36969 /* 101096 */ GIM_Reject,
36970 /* 101097 */ // Label 3113: @101097
36971 /* 101097 */ GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(101208),
36972 /* 101102 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36973 /* 101105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36974 /* 101108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3132*/ GIMT_Encode4(101147), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 938 //
36975 /* 101115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36976 /* 101119 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36977 /* 101123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36978 /* 101127 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
36979 /* 101127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16),
36980 /* 101130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36981 /* 101132 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36982 /* 101134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36983 /* 101136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36984 /* 101139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36985 /* 101145 */ GIR_RootConstrainSelectedInstOperands,
36986 /* 101146 */ // GIR_Coverage, 938,
36987 /* 101146 */ GIR_EraseRootFromParent_Done,
36988 /* 101147 */ // Label 3132: @101147
36989 /* 101147 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3133*/ GIMT_Encode4(101207), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3912 //
36990 /* 101154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36991 /* 101158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36992 /* 101162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36993 /* 101166 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36994 /* 101166 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36995 /* 101169 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36996 /* 101173 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36997 /* 101178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16),
36998 /* 101181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36999 /* 101183 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37000 /* 101185 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37001 /* 101187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37002 /* 101190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37003 /* 101196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37004 /* 101202 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37005 /* 101205 */ GIR_RootConstrainSelectedInstOperands,
37006 /* 101206 */ // GIR_Coverage, 3912,
37007 /* 101206 */ GIR_EraseRootFromParent_Done,
37008 /* 101207 */ // Label 3133: @101207
37009 /* 101207 */ GIM_Reject,
37010 /* 101208 */ // Label 3131: @101208
37011 /* 101208 */ GIM_Reject,
37012 /* 101209 */ // Label 3114: @101209
37013 /* 101209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3134*/ GIMT_Encode4(101254), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 937 //
37014 /* 101216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
37015 /* 101219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
37016 /* 101222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37017 /* 101226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37018 /* 101230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37019 /* 101234 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37020 /* 101234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32),
37021 /* 101237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37022 /* 101239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37023 /* 101241 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37024 /* 101243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37025 /* 101246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37026 /* 101252 */ GIR_RootConstrainSelectedInstOperands,
37027 /* 101253 */ // GIR_Coverage, 937,
37028 /* 101253 */ GIR_EraseRootFromParent_Done,
37029 /* 101254 */ // Label 3134: @101254
37030 /* 101254 */ GIM_Reject,
37031 /* 101255 */ // Label 3115: @101255
37032 /* 101255 */ GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(101520),
37033 /* 101260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
37034 /* 101263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
37035 /* 101266 */ GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(101459),
37036 /* 101271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37037 /* 101275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3137*/ GIMT_Encode4(101348), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6377 //
37038 /* 101282 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37039 /* 101286 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37040 /* 101290 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37041 /* 101293 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37042 /* 101298 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
37043 /* 101302 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
37044 /* 101306 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37045 /* 101311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37046 /* 101316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37047 /* 101320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37048 /* 101322 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37049 /* 101322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
37050 /* 101325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37051 /* 101327 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
37052 /* 101329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37053 /* 101333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37054 /* 101337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37055 /* 101340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37056 /* 101346 */ GIR_RootConstrainSelectedInstOperands,
37057 /* 101347 */ // GIR_Coverage, 6377,
37058 /* 101347 */ GIR_EraseRootFromParent_Done,
37059 /* 101348 */ // Label 3137: @101348
37060 /* 101348 */ GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(101458),
37061 /* 101353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37062 /* 101357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3139*/ GIMT_Encode4(101426), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2872 //
37063 /* 101364 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37064 /* 101368 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37065 /* 101372 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37066 /* 101375 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37067 /* 101380 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
37068 /* 101384 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
37069 /* 101388 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37070 /* 101393 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37071 /* 101398 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37072 /* 101400 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37073 /* 101400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
37074 /* 101403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37075 /* 101405 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37076 /* 101407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37077 /* 101411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37078 /* 101415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37079 /* 101418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37080 /* 101424 */ GIR_RootConstrainSelectedInstOperands,
37081 /* 101425 */ // GIR_Coverage, 2872,
37082 /* 101425 */ GIR_EraseRootFromParent_Done,
37083 /* 101426 */ // Label 3139: @101426
37084 /* 101426 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3140*/ GIMT_Encode4(101457), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 939 //
37085 /* 101433 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37086 /* 101437 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37087 /* 101437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32),
37088 /* 101440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37089 /* 101442 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37090 /* 101444 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37091 /* 101446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37092 /* 101449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37093 /* 101455 */ GIR_RootConstrainSelectedInstOperands,
37094 /* 101456 */ // GIR_Coverage, 939,
37095 /* 101456 */ GIR_EraseRootFromParent_Done,
37096 /* 101457 */ // Label 3140: @101457
37097 /* 101457 */ GIM_Reject,
37098 /* 101458 */ // Label 3138: @101458
37099 /* 101458 */ GIM_Reject,
37100 /* 101459 */ // Label 3136: @101459
37101 /* 101459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3141*/ GIMT_Encode4(101519), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3915 //
37102 /* 101466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37103 /* 101470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37104 /* 101474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37105 /* 101478 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37106 /* 101478 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37107 /* 101481 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37108 /* 101485 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37109 /* 101490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32),
37110 /* 101493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37111 /* 101495 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37112 /* 101497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37113 /* 101499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37114 /* 101502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37115 /* 101508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37116 /* 101514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37117 /* 101517 */ GIR_RootConstrainSelectedInstOperands,
37118 /* 101518 */ // GIR_Coverage, 3915,
37119 /* 101518 */ GIR_EraseRootFromParent_Done,
37120 /* 101519 */ // Label 3141: @101519
37121 /* 101519 */ GIM_Reject,
37122 /* 101520 */ // Label 3135: @101520
37123 /* 101520 */ GIM_Reject,
37124 /* 101521 */ // Label 3116: @101521
37125 /* 101521 */ GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(101720),
37126 /* 101526 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
37127 /* 101529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
37128 /* 101532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37129 /* 101536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3143*/ GIMT_Encode4(101609), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6378 //
37130 /* 101543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37131 /* 101547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37132 /* 101551 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37133 /* 101554 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37134 /* 101559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37135 /* 101563 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37136 /* 101567 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37137 /* 101572 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37138 /* 101577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37139 /* 101581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37140 /* 101583 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37141 /* 101583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
37142 /* 101586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37143 /* 101588 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
37144 /* 101590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37145 /* 101594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37146 /* 101598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37147 /* 101601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37148 /* 101607 */ GIR_RootConstrainSelectedInstOperands,
37149 /* 101608 */ // GIR_Coverage, 6378,
37150 /* 101608 */ GIR_EraseRootFromParent_Done,
37151 /* 101609 */ // Label 3143: @101609
37152 /* 101609 */ GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(101719),
37153 /* 101614 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37154 /* 101618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3145*/ GIMT_Encode4(101687), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2873 //
37155 /* 101625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37156 /* 101629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37157 /* 101633 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37158 /* 101636 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37159 /* 101641 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37160 /* 101645 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37161 /* 101649 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37162 /* 101654 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37163 /* 101659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37164 /* 101661 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37165 /* 101661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
37166 /* 101664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37167 /* 101666 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37168 /* 101668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37169 /* 101672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37170 /* 101676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37171 /* 101679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37172 /* 101685 */ GIR_RootConstrainSelectedInstOperands,
37173 /* 101686 */ // GIR_Coverage, 2873,
37174 /* 101686 */ GIR_EraseRootFromParent_Done,
37175 /* 101687 */ // Label 3145: @101687
37176 /* 101687 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3146*/ GIMT_Encode4(101718), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 943 //
37177 /* 101694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37178 /* 101698 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
37179 /* 101698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64),
37180 /* 101701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37181 /* 101703 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37182 /* 101705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37183 /* 101707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37184 /* 101710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37185 /* 101716 */ GIR_RootConstrainSelectedInstOperands,
37186 /* 101717 */ // GIR_Coverage, 943,
37187 /* 101717 */ GIR_EraseRootFromParent_Done,
37188 /* 101718 */ // Label 3146: @101718
37189 /* 101718 */ GIM_Reject,
37190 /* 101719 */ // Label 3144: @101719
37191 /* 101719 */ GIM_Reject,
37192 /* 101720 */ // Label 3142: @101720
37193 /* 101720 */ GIM_Reject,
37194 /* 101721 */ // Label 3117: @101721
37195 /* 101721 */ GIM_Reject,
37196 /* 101722 */ // Label 39: @101722
37197 /* 101722 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3155*/ GIMT_Encode4(102347),
37198 /* 101733 */ /*GILLT_s64*//*Label 3147*/ GIMT_Encode4(101781), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
37199 /* 101753 */ /*GILLT_v8s8*//*Label 3148*/ GIMT_Encode4(101827),
37200 /* 101757 */ /*GILLT_v16s8*//*Label 3149*/ GIMT_Encode4(101873),
37201 /* 101761 */ /*GILLT_v4s16*//*Label 3150*/ GIMT_Encode4(101985),
37202 /* 101765 */ /*GILLT_v8s16*//*Label 3151*/ GIMT_Encode4(102031),
37203 /* 101769 */ /*GILLT_v2s32*//*Label 3152*/ GIMT_Encode4(102143),
37204 /* 101773 */ /*GILLT_v4s32*//*Label 3153*/ GIMT_Encode4(102189),
37205 /* 101777 */ /*GILLT_v2s64*//*Label 3154*/ GIMT_Encode4(102301),
37206 /* 101781 */ // Label 3147: @101781
37207 /* 101781 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3156*/ GIMT_Encode4(101826), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1184 //
37208 /* 101788 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
37209 /* 101791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
37210 /* 101794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37211 /* 101798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37212 /* 101802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37213 /* 101806 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
37214 /* 101806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64),
37215 /* 101809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37216 /* 101811 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37217 /* 101813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37218 /* 101815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37219 /* 101818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37220 /* 101824 */ GIR_RootConstrainSelectedInstOperands,
37221 /* 101825 */ // GIR_Coverage, 1184,
37222 /* 101825 */ GIR_EraseRootFromParent_Done,
37223 /* 101826 */ // Label 3156: @101826
37224 /* 101826 */ GIM_Reject,
37225 /* 101827 */ // Label 3148: @101827
37226 /* 101827 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3157*/ GIMT_Encode4(101872), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1182 //
37227 /* 101834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
37228 /* 101837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
37229 /* 101840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37230 /* 101844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37231 /* 101848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37232 /* 101852 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37233 /* 101852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8),
37234 /* 101855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37235 /* 101857 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37236 /* 101859 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37237 /* 101861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37238 /* 101864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37239 /* 101870 */ GIR_RootConstrainSelectedInstOperands,
37240 /* 101871 */ // GIR_Coverage, 1182,
37241 /* 101871 */ GIR_EraseRootFromParent_Done,
37242 /* 101872 */ // Label 3157: @101872
37243 /* 101872 */ GIM_Reject,
37244 /* 101873 */ // Label 3149: @101873
37245 /* 101873 */ GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(101984),
37246 /* 101878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
37247 /* 101881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
37248 /* 101884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3159*/ GIMT_Encode4(101923), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1183 //
37249 /* 101891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37250 /* 101895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37251 /* 101899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37252 /* 101903 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37253 /* 101903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8),
37254 /* 101906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37255 /* 101908 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37256 /* 101910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37257 /* 101912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37258 /* 101915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37259 /* 101921 */ GIR_RootConstrainSelectedInstOperands,
37260 /* 101922 */ // GIR_Coverage, 1183,
37261 /* 101922 */ GIR_EraseRootFromParent_Done,
37262 /* 101923 */ // Label 3159: @101923
37263 /* 101923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3160*/ GIMT_Encode4(101983), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3936 //
37264 /* 101930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37265 /* 101934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37266 /* 101938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37267 /* 101942 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37268 /* 101942 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37269 /* 101945 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37270 /* 101949 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37271 /* 101954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8),
37272 /* 101957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37273 /* 101959 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37274 /* 101961 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37275 /* 101963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37276 /* 101966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37277 /* 101972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37278 /* 101978 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37279 /* 101981 */ GIR_RootConstrainSelectedInstOperands,
37280 /* 101982 */ // GIR_Coverage, 3936,
37281 /* 101982 */ GIR_EraseRootFromParent_Done,
37282 /* 101983 */ // Label 3160: @101983
37283 /* 101983 */ GIM_Reject,
37284 /* 101984 */ // Label 3158: @101984
37285 /* 101984 */ GIM_Reject,
37286 /* 101985 */ // Label 3150: @101985
37287 /* 101985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3161*/ GIMT_Encode4(102030), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1178 //
37288 /* 101992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
37289 /* 101995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
37290 /* 101998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37291 /* 102002 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37292 /* 102006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37293 /* 102010 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37294 /* 102010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16),
37295 /* 102013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37296 /* 102015 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37297 /* 102017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37298 /* 102019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37299 /* 102022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37300 /* 102028 */ GIR_RootConstrainSelectedInstOperands,
37301 /* 102029 */ // GIR_Coverage, 1178,
37302 /* 102029 */ GIR_EraseRootFromParent_Done,
37303 /* 102030 */ // Label 3161: @102030
37304 /* 102030 */ GIM_Reject,
37305 /* 102031 */ // Label 3151: @102031
37306 /* 102031 */ GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(102142),
37307 /* 102036 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
37308 /* 102039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
37309 /* 102042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3163*/ GIMT_Encode4(102081), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1180 //
37310 /* 102049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37311 /* 102053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37312 /* 102057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37313 /* 102061 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37314 /* 102061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16),
37315 /* 102064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37316 /* 102066 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37317 /* 102068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37318 /* 102070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37319 /* 102073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37320 /* 102079 */ GIR_RootConstrainSelectedInstOperands,
37321 /* 102080 */ // GIR_Coverage, 1180,
37322 /* 102080 */ GIR_EraseRootFromParent_Done,
37323 /* 102081 */ // Label 3163: @102081
37324 /* 102081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3164*/ GIMT_Encode4(102141), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3939 //
37325 /* 102088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37326 /* 102092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37327 /* 102096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37328 /* 102100 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37329 /* 102100 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37330 /* 102103 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37331 /* 102107 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37332 /* 102112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16),
37333 /* 102115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37334 /* 102117 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37335 /* 102119 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37336 /* 102121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37337 /* 102124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37338 /* 102130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37339 /* 102136 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37340 /* 102139 */ GIR_RootConstrainSelectedInstOperands,
37341 /* 102140 */ // GIR_Coverage, 3939,
37342 /* 102140 */ GIR_EraseRootFromParent_Done,
37343 /* 102141 */ // Label 3164: @102141
37344 /* 102141 */ GIM_Reject,
37345 /* 102142 */ // Label 3162: @102142
37346 /* 102142 */ GIM_Reject,
37347 /* 102143 */ // Label 3152: @102143
37348 /* 102143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3165*/ GIMT_Encode4(102188), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1179 //
37349 /* 102150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
37350 /* 102153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
37351 /* 102156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37352 /* 102160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37353 /* 102164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37354 /* 102168 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37355 /* 102168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32),
37356 /* 102171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37357 /* 102173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37358 /* 102175 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37359 /* 102177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37360 /* 102180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37361 /* 102186 */ GIR_RootConstrainSelectedInstOperands,
37362 /* 102187 */ // GIR_Coverage, 1179,
37363 /* 102187 */ GIR_EraseRootFromParent_Done,
37364 /* 102188 */ // Label 3165: @102188
37365 /* 102188 */ GIM_Reject,
37366 /* 102189 */ // Label 3153: @102189
37367 /* 102189 */ GIM_Try, /*On fail goto*//*Label 3166*/ GIMT_Encode4(102300),
37368 /* 102194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
37369 /* 102197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
37370 /* 102200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3167*/ GIMT_Encode4(102239), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1181 //
37371 /* 102207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37372 /* 102211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37373 /* 102215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37374 /* 102219 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37375 /* 102219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32),
37376 /* 102222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37377 /* 102224 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37378 /* 102226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37379 /* 102228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37380 /* 102231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37381 /* 102237 */ GIR_RootConstrainSelectedInstOperands,
37382 /* 102238 */ // GIR_Coverage, 1181,
37383 /* 102238 */ GIR_EraseRootFromParent_Done,
37384 /* 102239 */ // Label 3167: @102239
37385 /* 102239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3168*/ GIMT_Encode4(102299), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3942 //
37386 /* 102246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37387 /* 102250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37388 /* 102254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37389 /* 102258 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37390 /* 102258 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37391 /* 102261 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37392 /* 102265 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37393 /* 102270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32),
37394 /* 102273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37395 /* 102275 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37396 /* 102277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37397 /* 102279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37398 /* 102282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37399 /* 102288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37400 /* 102294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37401 /* 102297 */ GIR_RootConstrainSelectedInstOperands,
37402 /* 102298 */ // GIR_Coverage, 3942,
37403 /* 102298 */ GIR_EraseRootFromParent_Done,
37404 /* 102299 */ // Label 3168: @102299
37405 /* 102299 */ GIM_Reject,
37406 /* 102300 */ // Label 3166: @102300
37407 /* 102300 */ GIM_Reject,
37408 /* 102301 */ // Label 3154: @102301
37409 /* 102301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3169*/ GIMT_Encode4(102346), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1185 //
37410 /* 102308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
37411 /* 102311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
37412 /* 102314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37413 /* 102318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37414 /* 102322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37415 /* 102326 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
37416 /* 102326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64),
37417 /* 102329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37418 /* 102331 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37419 /* 102333 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37420 /* 102335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37421 /* 102338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37422 /* 102344 */ GIR_RootConstrainSelectedInstOperands,
37423 /* 102345 */ // GIR_Coverage, 1185,
37424 /* 102345 */ GIR_EraseRootFromParent_Done,
37425 /* 102346 */ // Label 3169: @102346
37426 /* 102346 */ GIM_Reject,
37427 /* 102347 */ // Label 3155: @102347
37428 /* 102347 */ GIM_Reject,
37429 /* 102348 */ // Label 40: @102348
37430 /* 102348 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3179*/ GIMT_Encode4(103340),
37431 /* 102359 */ /*GILLT_s32*//*Label 3170*/ GIMT_Encode4(102411),
37432 /* 102363 */ /*GILLT_s64*//*Label 3171*/ GIMT_Encode4(102624), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
37433 /* 102383 */ /*GILLT_v8s8*//*Label 3172*/ GIMT_Encode4(102670),
37434 /* 102387 */ /*GILLT_v16s8*//*Label 3173*/ GIMT_Encode4(102716),
37435 /* 102391 */ /*GILLT_v4s16*//*Label 3174*/ GIMT_Encode4(102828),
37436 /* 102395 */ /*GILLT_v8s16*//*Label 3175*/ GIMT_Encode4(102874),
37437 /* 102399 */ /*GILLT_v2s32*//*Label 3176*/ GIMT_Encode4(102986),
37438 /* 102403 */ /*GILLT_v4s32*//*Label 3177*/ GIMT_Encode4(103032),
37439 /* 102407 */ /*GILLT_v2s64*//*Label 3178*/ GIMT_Encode4(103219),
37440 /* 102411 */ // Label 3170: @102411
37441 /* 102411 */ GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(102623),
37442 /* 102416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
37443 /* 102419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
37444 /* 102422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3181*/ GIMT_Encode4(102483), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2059 //
37445 /* 102429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
37446 /* 102433 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37447 /* 102437 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37448 /* 102441 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
37449 /* 102445 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37450 /* 102449 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37451 /* 102454 */ // MIs[1] Rn
37452 /* 102454 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37453 /* 102459 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37454 /* 102461 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37455 /* 102461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
37456 /* 102464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37457 /* 102466 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
37458 /* 102468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37459 /* 102472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37460 /* 102475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37461 /* 102481 */ GIR_RootConstrainSelectedInstOperands,
37462 /* 102482 */ // GIR_Coverage, 2059,
37463 /* 102482 */ GIR_EraseRootFromParent_Done,
37464 /* 102483 */ // Label 3181: @102483
37465 /* 102483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3182*/ GIMT_Encode4(102544), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2333 //
37466 /* 102490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37467 /* 102494 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37468 /* 102498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37469 /* 102502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
37470 /* 102506 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37471 /* 102510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37472 /* 102515 */ // MIs[1] Rn
37473 /* 102515 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37474 /* 102520 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37475 /* 102522 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37476 /* 102522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
37477 /* 102525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37478 /* 102527 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
37479 /* 102529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37480 /* 102533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37481 /* 102536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37482 /* 102542 */ GIR_RootConstrainSelectedInstOperands,
37483 /* 102543 */ // GIR_Coverage, 2333,
37484 /* 102543 */ GIR_EraseRootFromParent_Done,
37485 /* 102544 */ // Label 3182: @102544
37486 /* 102544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3183*/ GIMT_Encode4(102583), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2057 //
37487 /* 102551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
37488 /* 102555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37489 /* 102559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37490 /* 102563 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
37491 /* 102563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
37492 /* 102566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37493 /* 102568 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
37494 /* 102570 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
37495 /* 102572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37496 /* 102575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37497 /* 102581 */ GIR_RootConstrainSelectedInstOperands,
37498 /* 102582 */ // GIR_Coverage, 2057,
37499 /* 102582 */ GIR_EraseRootFromParent_Done,
37500 /* 102583 */ // Label 3183: @102583
37501 /* 102583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3184*/ GIMT_Encode4(102622), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2331 //
37502 /* 102590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37503 /* 102594 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37504 /* 102598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37505 /* 102602 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37506 /* 102602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
37507 /* 102605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37508 /* 102607 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
37509 /* 102609 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
37510 /* 102611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37511 /* 102614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37512 /* 102620 */ GIR_RootConstrainSelectedInstOperands,
37513 /* 102621 */ // GIR_Coverage, 2331,
37514 /* 102621 */ GIR_EraseRootFromParent_Done,
37515 /* 102622 */ // Label 3184: @102622
37516 /* 102622 */ GIM_Reject,
37517 /* 102623 */ // Label 3180: @102623
37518 /* 102623 */ GIM_Reject,
37519 /* 102624 */ // Label 3171: @102624
37520 /* 102624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3185*/ GIMT_Encode4(102669), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1176 //
37521 /* 102631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
37522 /* 102634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
37523 /* 102637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37524 /* 102641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37525 /* 102645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37526 /* 102649 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
37527 /* 102649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64),
37528 /* 102652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37529 /* 102654 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37530 /* 102656 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37531 /* 102658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37532 /* 102661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37533 /* 102667 */ GIR_RootConstrainSelectedInstOperands,
37534 /* 102668 */ // GIR_Coverage, 1176,
37535 /* 102668 */ GIR_EraseRootFromParent_Done,
37536 /* 102669 */ // Label 3185: @102669
37537 /* 102669 */ GIM_Reject,
37538 /* 102670 */ // Label 3172: @102670
37539 /* 102670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3186*/ GIMT_Encode4(102715), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1174 //
37540 /* 102677 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
37541 /* 102680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
37542 /* 102683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37543 /* 102687 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37544 /* 102691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37545 /* 102695 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37546 /* 102695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8),
37547 /* 102698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37548 /* 102700 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37549 /* 102702 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37550 /* 102704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37551 /* 102707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37552 /* 102713 */ GIR_RootConstrainSelectedInstOperands,
37553 /* 102714 */ // GIR_Coverage, 1174,
37554 /* 102714 */ GIR_EraseRootFromParent_Done,
37555 /* 102715 */ // Label 3186: @102715
37556 /* 102715 */ GIM_Reject,
37557 /* 102716 */ // Label 3173: @102716
37558 /* 102716 */ GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(102827),
37559 /* 102721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
37560 /* 102724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
37561 /* 102727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3188*/ GIMT_Encode4(102766), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1175 //
37562 /* 102734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37563 /* 102738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37564 /* 102742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37565 /* 102746 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37566 /* 102746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8),
37567 /* 102749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37568 /* 102751 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37569 /* 102753 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37570 /* 102755 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37571 /* 102758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37572 /* 102764 */ GIR_RootConstrainSelectedInstOperands,
37573 /* 102765 */ // GIR_Coverage, 1175,
37574 /* 102765 */ GIR_EraseRootFromParent_Done,
37575 /* 102766 */ // Label 3188: @102766
37576 /* 102766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3189*/ GIMT_Encode4(102826), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3927 //
37577 /* 102773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37578 /* 102777 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37579 /* 102781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37580 /* 102785 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37581 /* 102785 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37582 /* 102788 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37583 /* 102792 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37584 /* 102797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8),
37585 /* 102800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37586 /* 102802 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37587 /* 102804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37588 /* 102806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37589 /* 102809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37590 /* 102815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37591 /* 102821 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37592 /* 102824 */ GIR_RootConstrainSelectedInstOperands,
37593 /* 102825 */ // GIR_Coverage, 3927,
37594 /* 102825 */ GIR_EraseRootFromParent_Done,
37595 /* 102826 */ // Label 3189: @102826
37596 /* 102826 */ GIM_Reject,
37597 /* 102827 */ // Label 3187: @102827
37598 /* 102827 */ GIM_Reject,
37599 /* 102828 */ // Label 3174: @102828
37600 /* 102828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3190*/ GIMT_Encode4(102873), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1170 //
37601 /* 102835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
37602 /* 102838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
37603 /* 102841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37604 /* 102845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37605 /* 102849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37606 /* 102853 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37607 /* 102853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16),
37608 /* 102856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37609 /* 102858 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37610 /* 102860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37611 /* 102862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37612 /* 102865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37613 /* 102871 */ GIR_RootConstrainSelectedInstOperands,
37614 /* 102872 */ // GIR_Coverage, 1170,
37615 /* 102872 */ GIR_EraseRootFromParent_Done,
37616 /* 102873 */ // Label 3190: @102873
37617 /* 102873 */ GIM_Reject,
37618 /* 102874 */ // Label 3175: @102874
37619 /* 102874 */ GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(102985),
37620 /* 102879 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
37621 /* 102882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
37622 /* 102885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3192*/ GIMT_Encode4(102924), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1172 //
37623 /* 102892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37624 /* 102896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37625 /* 102900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37626 /* 102904 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37627 /* 102904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16),
37628 /* 102907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37629 /* 102909 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37630 /* 102911 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37631 /* 102913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37632 /* 102916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37633 /* 102922 */ GIR_RootConstrainSelectedInstOperands,
37634 /* 102923 */ // GIR_Coverage, 1172,
37635 /* 102923 */ GIR_EraseRootFromParent_Done,
37636 /* 102924 */ // Label 3192: @102924
37637 /* 102924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3193*/ GIMT_Encode4(102984), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3930 //
37638 /* 102931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37639 /* 102935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37640 /* 102939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37641 /* 102943 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37642 /* 102943 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37643 /* 102946 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37644 /* 102950 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37645 /* 102955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16),
37646 /* 102958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37647 /* 102960 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37648 /* 102962 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37649 /* 102964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37650 /* 102967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37651 /* 102973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37652 /* 102979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37653 /* 102982 */ GIR_RootConstrainSelectedInstOperands,
37654 /* 102983 */ // GIR_Coverage, 3930,
37655 /* 102983 */ GIR_EraseRootFromParent_Done,
37656 /* 102984 */ // Label 3193: @102984
37657 /* 102984 */ GIM_Reject,
37658 /* 102985 */ // Label 3191: @102985
37659 /* 102985 */ GIM_Reject,
37660 /* 102986 */ // Label 3176: @102986
37661 /* 102986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3194*/ GIMT_Encode4(103031), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1171 //
37662 /* 102993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
37663 /* 102996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
37664 /* 102999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37665 /* 103003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37666 /* 103007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37667 /* 103011 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37668 /* 103011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32),
37669 /* 103014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37670 /* 103016 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37671 /* 103018 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37672 /* 103020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37673 /* 103023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37674 /* 103029 */ GIR_RootConstrainSelectedInstOperands,
37675 /* 103030 */ // GIR_Coverage, 1171,
37676 /* 103030 */ GIR_EraseRootFromParent_Done,
37677 /* 103031 */ // Label 3194: @103031
37678 /* 103031 */ GIM_Reject,
37679 /* 103032 */ // Label 3177: @103032
37680 /* 103032 */ GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(103218),
37681 /* 103037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
37682 /* 103040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
37683 /* 103043 */ GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(103157),
37684 /* 103048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37685 /* 103052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37686 /* 103056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3197*/ GIMT_Encode4(103125), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2882 //
37687 /* 103063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37688 /* 103067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37689 /* 103071 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37690 /* 103074 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37691 /* 103079 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
37692 /* 103083 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
37693 /* 103087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37694 /* 103092 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37695 /* 103097 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37696 /* 103099 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37697 /* 103099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32),
37698 /* 103102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37699 /* 103104 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37700 /* 103106 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37701 /* 103110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37702 /* 103114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37703 /* 103117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37704 /* 103123 */ GIR_RootConstrainSelectedInstOperands,
37705 /* 103124 */ // GIR_Coverage, 2882,
37706 /* 103124 */ GIR_EraseRootFromParent_Done,
37707 /* 103125 */ // Label 3197: @103125
37708 /* 103125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3198*/ GIMT_Encode4(103156), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1173 //
37709 /* 103132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37710 /* 103136 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37711 /* 103136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32),
37712 /* 103139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37713 /* 103141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37714 /* 103143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37715 /* 103145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37716 /* 103148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37717 /* 103154 */ GIR_RootConstrainSelectedInstOperands,
37718 /* 103155 */ // GIR_Coverage, 1173,
37719 /* 103155 */ GIR_EraseRootFromParent_Done,
37720 /* 103156 */ // Label 3198: @103156
37721 /* 103156 */ GIM_Reject,
37722 /* 103157 */ // Label 3196: @103157
37723 /* 103157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3199*/ GIMT_Encode4(103217), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3933 //
37724 /* 103164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37725 /* 103168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37726 /* 103172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37727 /* 103176 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37728 /* 103176 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37729 /* 103179 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37730 /* 103183 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37731 /* 103188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32),
37732 /* 103191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37733 /* 103193 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37734 /* 103195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37735 /* 103197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37736 /* 103200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37737 /* 103206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37738 /* 103212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37739 /* 103215 */ GIR_RootConstrainSelectedInstOperands,
37740 /* 103216 */ // GIR_Coverage, 3933,
37741 /* 103216 */ GIR_EraseRootFromParent_Done,
37742 /* 103217 */ // Label 3199: @103217
37743 /* 103217 */ GIM_Reject,
37744 /* 103218 */ // Label 3195: @103218
37745 /* 103218 */ GIM_Reject,
37746 /* 103219 */ // Label 3178: @103219
37747 /* 103219 */ GIM_Try, /*On fail goto*//*Label 3200*/ GIMT_Encode4(103339),
37748 /* 103224 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
37749 /* 103227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
37750 /* 103230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37751 /* 103234 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37752 /* 103238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3201*/ GIMT_Encode4(103307), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2883 //
37753 /* 103245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37754 /* 103249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37755 /* 103253 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37756 /* 103256 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37757 /* 103261 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37758 /* 103265 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37759 /* 103269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37760 /* 103274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37761 /* 103279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37762 /* 103281 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37763 /* 103281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64),
37764 /* 103284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37765 /* 103286 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37766 /* 103288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37767 /* 103292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37768 /* 103296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37769 /* 103299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37770 /* 103305 */ GIR_RootConstrainSelectedInstOperands,
37771 /* 103306 */ // GIR_Coverage, 2883,
37772 /* 103306 */ GIR_EraseRootFromParent_Done,
37773 /* 103307 */ // Label 3201: @103307
37774 /* 103307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3202*/ GIMT_Encode4(103338), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1177 //
37775 /* 103314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37776 /* 103318 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
37777 /* 103318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64),
37778 /* 103321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37779 /* 103323 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37780 /* 103325 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37781 /* 103327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37782 /* 103330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37783 /* 103336 */ GIR_RootConstrainSelectedInstOperands,
37784 /* 103337 */ // GIR_Coverage, 1177,
37785 /* 103337 */ GIR_EraseRootFromParent_Done,
37786 /* 103338 */ // Label 3202: @103338
37787 /* 103338 */ GIM_Reject,
37788 /* 103339 */ // Label 3200: @103339
37789 /* 103339 */ GIM_Reject,
37790 /* 103340 */ // Label 3179: @103340
37791 /* 103340 */ GIM_Reject,
37792 /* 103341 */ // Label 41: @103341
37793 /* 103341 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3210*/ GIMT_Encode4(106145),
37794 /* 103352 */ /*GILLT_s16*//*Label 3203*/ GIMT_Encode4(103404),
37795 /* 103356 */ /*GILLT_s32*//*Label 3204*/ GIMT_Encode4(103450),
37796 /* 103360 */ /*GILLT_s64*//*Label 3205*/ GIMT_Encode4(105067), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
37797 /* 103388 */ /*GILLT_v4s16*//*Label 3206*/ GIMT_Encode4(105113),
37798 /* 103392 */ /*GILLT_v8s16*//*Label 3207*/ GIMT_Encode4(105317),
37799 /* 103396 */ /*GILLT_v2s32*//*Label 3208*/ GIMT_Encode4(105785),
37800 /* 103400 */ /*GILLT_v4s32*//*Label 3209*/ GIMT_Encode4(105831),
37801 /* 103404 */ // Label 3203: @103404
37802 /* 103404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3211*/ GIMT_Encode4(103449), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 621 //
37803 /* 103411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
37804 /* 103414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
37805 /* 103417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
37806 /* 103421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
37807 /* 103425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
37808 /* 103429 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
37809 /* 103429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
37810 /* 103432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
37811 /* 103434 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
37812 /* 103436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
37813 /* 103438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37814 /* 103441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37815 /* 103447 */ GIR_RootConstrainSelectedInstOperands,
37816 /* 103448 */ // GIR_Coverage, 621,
37817 /* 103448 */ GIR_EraseRootFromParent_Done,
37818 /* 103449 */ // Label 3211: @103449
37819 /* 103449 */ GIM_Reject,
37820 /* 103450 */ // Label 3204: @103450
37821 /* 103450 */ GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(105066),
37822 /* 103455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
37823 /* 103458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
37824 /* 103461 */ GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(104137),
37825 /* 103466 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
37826 /* 103470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37827 /* 103474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3214*/ GIMT_Encode4(103805), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 6558 //
37828 /* 103481 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37829 /* 103485 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
37830 /* 103489 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37831 /* 103493 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37832 /* 103497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37833 /* 103502 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37834 /* 103507 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
37835 /* 103511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37836 /* 103515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37837 /* 103517 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)<<P:Predicate_fmul_contract>>, SPR:{ *:[f32] }:$acc)<<P:Predicate_fadd_contract>> => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
37838 /* 103517 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
37839 /* 103520 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37840 /* 103524 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37841 /* 103529 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
37842 /* 103531 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
37843 /* 103534 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37844 /* 103538 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37845 /* 103543 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
37846 /* 103546 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37847 /* 103551 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
37848 /* 103554 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37849 /* 103558 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37850 /* 103563 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
37851 /* 103566 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
37852 /* 103570 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
37853 /* 103573 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37854 /* 103578 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37855 /* 103583 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37856 /* 103588 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
37857 /* 103591 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37858 /* 103595 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37859 /* 103600 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
37860 /* 103602 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
37861 /* 103605 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37862 /* 103609 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37863 /* 103614 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
37864 /* 103617 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37865 /* 103622 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
37866 /* 103625 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37867 /* 103629 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37868 /* 103634 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
37869 /* 103637 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
37870 /* 103641 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
37871 /* 103644 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37872 /* 103649 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37873 /* 103654 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37874 /* 103659 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
37875 /* 103662 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37876 /* 103666 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37877 /* 103671 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
37878 /* 103673 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
37879 /* 103676 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37880 /* 103680 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37881 /* 103685 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
37882 /* 103688 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37883 /* 103693 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
37884 /* 103696 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37885 /* 103700 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37886 /* 103705 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
37887 /* 103708 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
37888 /* 103712 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
37889 /* 103715 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37890 /* 103720 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37891 /* 103725 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37892 /* 103730 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
37893 /* 103733 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
37894 /* 103737 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37895 /* 103742 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
37896 /* 103745 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
37897 /* 103748 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
37898 /* 103751 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
37899 /* 103754 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37900 /* 103760 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37901 /* 103762 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
37902 /* 103765 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37903 /* 103769 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37904 /* 103774 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
37905 /* 103777 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37906 /* 103782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37907 /* 103785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37908 /* 103787 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
37909 /* 103794 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
37910 /* 103799 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37911 /* 103804 */ // GIR_Coverage, 6558,
37912 /* 103804 */ GIR_EraseRootFromParent_Done,
37913 /* 103805 */ // Label 3214: @103805
37914 /* 103805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3215*/ GIMT_Encode4(104136), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3091 //
37915 /* 103812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37916 /* 103816 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37917 /* 103820 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
37918 /* 103824 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37919 /* 103828 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37920 /* 103832 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37921 /* 103837 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37922 /* 103842 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
37923 /* 103846 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37924 /* 103848 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
37925 /* 103848 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
37926 /* 103851 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37927 /* 103855 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37928 /* 103860 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
37929 /* 103862 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
37930 /* 103865 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37931 /* 103869 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37932 /* 103874 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
37933 /* 103877 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37934 /* 103882 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
37935 /* 103885 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37936 /* 103889 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37937 /* 103894 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
37938 /* 103897 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
37939 /* 103901 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
37940 /* 103904 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37941 /* 103909 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37942 /* 103914 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37943 /* 103919 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
37944 /* 103922 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37945 /* 103926 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37946 /* 103931 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
37947 /* 103933 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
37948 /* 103936 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37949 /* 103940 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37950 /* 103945 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
37951 /* 103948 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37952 /* 103953 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
37953 /* 103956 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37954 /* 103960 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37955 /* 103965 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
37956 /* 103968 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
37957 /* 103972 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
37958 /* 103975 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37959 /* 103980 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37960 /* 103985 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37961 /* 103990 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
37962 /* 103993 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37963 /* 103997 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37964 /* 104002 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
37965 /* 104004 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
37966 /* 104007 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37967 /* 104011 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37968 /* 104016 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
37969 /* 104019 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37970 /* 104024 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
37971 /* 104027 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37972 /* 104031 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37973 /* 104036 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
37974 /* 104039 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
37975 /* 104043 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
37976 /* 104046 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37977 /* 104051 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37978 /* 104056 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37979 /* 104061 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
37980 /* 104064 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
37981 /* 104068 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37982 /* 104073 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
37983 /* 104076 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
37984 /* 104079 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
37985 /* 104082 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
37986 /* 104085 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37987 /* 104091 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37988 /* 104093 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
37989 /* 104096 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37990 /* 104100 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37991 /* 104105 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
37992 /* 104108 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37993 /* 104113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37994 /* 104116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37995 /* 104118 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
37996 /* 104125 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
37997 /* 104130 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37998 /* 104135 */ // GIR_Coverage, 3091,
37999 /* 104135 */ GIR_EraseRootFromParent_Done,
38000 /* 104136 */ // Label 3215: @104136
38001 /* 104136 */ GIM_Reject,
38002 /* 104137 */ // Label 3213: @104137
38003 /* 104137 */ GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(105065),
38004 /* 104142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38005 /* 104146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3217*/ GIMT_Encode4(104473), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 6557 //
38006 /* 104153 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38007 /* 104157 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38008 /* 104161 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38009 /* 104165 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38010 /* 104169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38011 /* 104174 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38012 /* 104179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38013 /* 104183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38014 /* 104185 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38015 /* 104185 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
38016 /* 104188 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38017 /* 104192 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38018 /* 104197 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
38019 /* 104199 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
38020 /* 104202 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38021 /* 104206 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38022 /* 104211 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
38023 /* 104214 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38024 /* 104219 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
38025 /* 104222 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38026 /* 104226 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38027 /* 104231 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
38028 /* 104234 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
38029 /* 104238 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
38030 /* 104241 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38031 /* 104246 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38032 /* 104251 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38033 /* 104256 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38034 /* 104259 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38035 /* 104263 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38036 /* 104268 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38037 /* 104270 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38038 /* 104273 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38039 /* 104277 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38040 /* 104282 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38041 /* 104285 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38042 /* 104290 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38043 /* 104293 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38044 /* 104297 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38045 /* 104302 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38046 /* 104305 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
38047 /* 104309 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38048 /* 104312 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38049 /* 104317 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38050 /* 104322 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38051 /* 104327 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38052 /* 104330 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38053 /* 104334 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38054 /* 104339 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38055 /* 104341 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38056 /* 104344 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38057 /* 104348 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38058 /* 104353 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38059 /* 104356 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38060 /* 104361 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38061 /* 104364 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38062 /* 104368 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38063 /* 104373 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38064 /* 104376 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
38065 /* 104380 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38066 /* 104383 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38067 /* 104388 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38068 /* 104393 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38069 /* 104398 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38070 /* 104401 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
38071 /* 104405 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38072 /* 104410 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38073 /* 104413 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38074 /* 104416 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38075 /* 104419 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38076 /* 104422 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38077 /* 104428 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38078 /* 104430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38079 /* 104433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38080 /* 104437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38081 /* 104442 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38082 /* 104445 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38083 /* 104450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38084 /* 104453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38085 /* 104455 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38086 /* 104462 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38087 /* 104467 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38088 /* 104472 */ // GIR_Coverage, 6557,
38089 /* 104472 */ GIR_EraseRootFromParent_Done,
38090 /* 104473 */ // Label 3217: @104473
38091 /* 104473 */ GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(105064),
38092 /* 104478 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38093 /* 104482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3219*/ GIMT_Encode4(104805), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3089 //
38094 /* 104489 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38095 /* 104493 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38096 /* 104497 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38097 /* 104501 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38098 /* 104505 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38099 /* 104510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38100 /* 104515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38101 /* 104517 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38102 /* 104517 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
38103 /* 104520 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38104 /* 104524 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38105 /* 104529 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
38106 /* 104531 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
38107 /* 104534 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38108 /* 104538 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38109 /* 104543 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
38110 /* 104546 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38111 /* 104551 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
38112 /* 104554 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38113 /* 104558 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38114 /* 104563 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
38115 /* 104566 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
38116 /* 104570 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
38117 /* 104573 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38118 /* 104578 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38119 /* 104583 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38120 /* 104588 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38121 /* 104591 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38122 /* 104595 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38123 /* 104600 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38124 /* 104602 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38125 /* 104605 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38126 /* 104609 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38127 /* 104614 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38128 /* 104617 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38129 /* 104622 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38130 /* 104625 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38131 /* 104629 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38132 /* 104634 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38133 /* 104637 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
38134 /* 104641 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38135 /* 104644 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38136 /* 104649 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38137 /* 104654 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38138 /* 104659 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38139 /* 104662 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38140 /* 104666 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38141 /* 104671 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38142 /* 104673 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38143 /* 104676 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38144 /* 104680 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38145 /* 104685 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38146 /* 104688 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38147 /* 104693 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38148 /* 104696 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38149 /* 104700 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38150 /* 104705 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38151 /* 104708 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
38152 /* 104712 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38153 /* 104715 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38154 /* 104720 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38155 /* 104725 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38156 /* 104730 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38157 /* 104733 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
38158 /* 104737 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38159 /* 104742 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38160 /* 104745 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38161 /* 104748 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38162 /* 104751 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38163 /* 104754 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38164 /* 104760 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38165 /* 104762 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38166 /* 104765 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38167 /* 104769 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38168 /* 104774 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38169 /* 104777 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38170 /* 104782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38171 /* 104785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38172 /* 104787 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38173 /* 104794 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38174 /* 104799 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38175 /* 104804 */ // GIR_Coverage, 3089,
38176 /* 104804 */ GIR_EraseRootFromParent_Done,
38177 /* 104805 */ // Label 3219: @104805
38178 /* 104805 */ GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(105063),
38179 /* 104810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38180 /* 104814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3221*/ GIMT_Encode4(104841), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 619 //
38181 /* 104821 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
38182 /* 104821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
38183 /* 104824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38184 /* 104826 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
38185 /* 104828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
38186 /* 104830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38187 /* 104833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38188 /* 104839 */ GIR_RootConstrainSelectedInstOperands,
38189 /* 104840 */ // GIR_Coverage, 619,
38190 /* 104840 */ GIR_EraseRootFromParent_Done,
38191 /* 104841 */ // Label 3221: @104841
38192 /* 104841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3222*/ GIMT_Encode4(105062), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3086 //
38193 /* 104848 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38194 /* 104848 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38195 /* 104851 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38196 /* 104855 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38197 /* 104860 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38198 /* 104862 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38199 /* 104865 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38200 /* 104869 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38201 /* 104874 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38202 /* 104877 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38203 /* 104882 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38204 /* 104885 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38205 /* 104889 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38206 /* 104894 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38207 /* 104897 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
38208 /* 104901 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38209 /* 104904 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38210 /* 104909 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38211 /* 104914 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38212 /* 104919 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38213 /* 104922 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38214 /* 104926 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38215 /* 104931 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38216 /* 104933 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38217 /* 104936 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38218 /* 104940 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38219 /* 104945 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38220 /* 104948 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38221 /* 104953 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38222 /* 104956 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38223 /* 104960 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38224 /* 104965 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38225 /* 104968 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
38226 /* 104972 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38227 /* 104975 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38228 /* 104980 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38229 /* 104985 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38230 /* 104990 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38231 /* 104993 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
38232 /* 104997 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38233 /* 105002 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38234 /* 105005 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38235 /* 105008 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38236 /* 105011 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38237 /* 105017 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38238 /* 105019 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38239 /* 105022 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38240 /* 105026 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38241 /* 105031 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38242 /* 105034 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38243 /* 105039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38244 /* 105042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38245 /* 105044 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38246 /* 105051 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38247 /* 105056 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38248 /* 105061 */ // GIR_Coverage, 3086,
38249 /* 105061 */ GIR_EraseRootFromParent_Done,
38250 /* 105062 */ // Label 3222: @105062
38251 /* 105062 */ GIM_Reject,
38252 /* 105063 */ // Label 3220: @105063
38253 /* 105063 */ GIM_Reject,
38254 /* 105064 */ // Label 3218: @105064
38255 /* 105064 */ GIM_Reject,
38256 /* 105065 */ // Label 3216: @105065
38257 /* 105065 */ GIM_Reject,
38258 /* 105066 */ // Label 3212: @105066
38259 /* 105066 */ GIM_Reject,
38260 /* 105067 */ // Label 3205: @105067
38261 /* 105067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3223*/ GIMT_Encode4(105112), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 617 //
38262 /* 105074 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
38263 /* 105077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
38264 /* 105080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38265 /* 105084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38266 /* 105088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38267 /* 105092 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
38268 /* 105092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
38269 /* 105095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
38270 /* 105097 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
38271 /* 105099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
38272 /* 105101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38273 /* 105104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38274 /* 105110 */ GIR_RootConstrainSelectedInstOperands,
38275 /* 105111 */ // GIR_Coverage, 617,
38276 /* 105111 */ GIR_EraseRootFromParent_Done,
38277 /* 105112 */ // Label 3223: @105112
38278 /* 105112 */ GIM_Reject,
38279 /* 105113 */ // Label 3206: @105113
38280 /* 105113 */ GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(105316),
38281 /* 105118 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38282 /* 105121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
38283 /* 105124 */ GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(105276),
38284 /* 105129 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
38285 /* 105133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38286 /* 105137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3226*/ GIMT_Encode4(105206), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6184 //
38287 /* 105144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38288 /* 105148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38289 /* 105152 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38290 /* 105156 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38291 /* 105160 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38292 /* 105165 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38293 /* 105170 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
38294 /* 105174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38295 /* 105178 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38296 /* 105180 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)<<P:Predicate_fmul_contract>>, DPR:{ *:[v4f16] }:$src1)<<P:Predicate_fadd_contract>> => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38297 /* 105180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
38298 /* 105183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38299 /* 105185 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
38300 /* 105187 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38301 /* 105191 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38302 /* 105195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38303 /* 105198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38304 /* 105204 */ GIR_RootConstrainSelectedInstOperands,
38305 /* 105205 */ // GIR_Coverage, 6184,
38306 /* 105205 */ GIR_EraseRootFromParent_Done,
38307 /* 105206 */ // Label 3226: @105206
38308 /* 105206 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3227*/ GIMT_Encode4(105275), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1101 //
38309 /* 105213 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38310 /* 105217 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38311 /* 105221 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38312 /* 105225 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38313 /* 105229 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38314 /* 105233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38315 /* 105238 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38316 /* 105243 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
38317 /* 105247 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38318 /* 105249 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38319 /* 105249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
38320 /* 105252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38321 /* 105254 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38322 /* 105256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38323 /* 105260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38324 /* 105264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38325 /* 105267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38326 /* 105273 */ GIR_RootConstrainSelectedInstOperands,
38327 /* 105274 */ // GIR_Coverage, 1101,
38328 /* 105274 */ GIR_EraseRootFromParent_Done,
38329 /* 105275 */ // Label 3227: @105275
38330 /* 105275 */ GIM_Reject,
38331 /* 105276 */ // Label 3225: @105276
38332 /* 105276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3228*/ GIMT_Encode4(105315), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 886 //
38333 /* 105283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38334 /* 105287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38335 /* 105291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38336 /* 105295 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38337 /* 105295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd),
38338 /* 105298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38339 /* 105300 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38340 /* 105302 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38341 /* 105304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38342 /* 105307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38343 /* 105313 */ GIR_RootConstrainSelectedInstOperands,
38344 /* 105314 */ // GIR_Coverage, 886,
38345 /* 105314 */ GIR_EraseRootFromParent_Done,
38346 /* 105315 */ // Label 3228: @105315
38347 /* 105315 */ GIM_Reject,
38348 /* 105316 */ // Label 3224: @105316
38349 /* 105316 */ GIM_Reject,
38350 /* 105317 */ // Label 3207: @105317
38351 /* 105317 */ GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(105784),
38352 /* 105322 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
38353 /* 105325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
38354 /* 105328 */ GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(105684),
38355 /* 105333 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
38356 /* 105337 */ GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(105535),
38357 /* 105342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38358 /* 105346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3232*/ GIMT_Encode4(105440), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6672 //
38359 /* 105353 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38360 /* 105357 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38361 /* 105361 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5,
38362 /* 105364 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
38363 /* 105369 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38364 /* 105373 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
38365 /* 105377 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v8s16,
38366 /* 105381 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
38367 /* 105385 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38368 /* 105389 */ // MIs[2] Operand 1
38369 /* 105389 */ // No operand predicates
38370 /* 105389 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38371 /* 105394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38372 /* 105399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38373 /* 105403 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
38374 /* 105405 */ // (fadd:{ *:[v8f16] } (intrinsic_wo_chain:{ *:[v8f16] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm), MQPR:{ *:[v8f16] }:$Qd_src)<<P:Predicate_fadd_contract>> => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
38375 /* 105405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16),
38376 /* 105408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38377 /* 105410 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
38378 /* 105412 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn
38379 /* 105416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm
38380 /* 105420 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot
38381 /* 105423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38382 /* 105426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38383 /* 105432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38384 /* 105438 */ GIR_RootConstrainSelectedInstOperands,
38385 /* 105439 */ // GIR_Coverage, 6672,
38386 /* 105439 */ GIR_EraseRootFromParent_Done,
38387 /* 105440 */ // Label 3232: @105440
38388 /* 105440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3233*/ GIMT_Encode4(105534), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4430 //
38389 /* 105447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38390 /* 105451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38391 /* 105455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38392 /* 105459 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5,
38393 /* 105462 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
38394 /* 105467 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38395 /* 105471 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
38396 /* 105475 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v8s16,
38397 /* 105479 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
38398 /* 105483 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38399 /* 105487 */ // MIs[2] Operand 1
38400 /* 105487 */ // No operand predicates
38401 /* 105487 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38402 /* 105492 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38403 /* 105497 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
38404 /* 105499 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, (intrinsic_wo_chain:{ *:[v8f16] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm))<<P:Predicate_fadd_contract>> => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
38405 /* 105499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16),
38406 /* 105502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38407 /* 105504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd_src
38408 /* 105506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn
38409 /* 105510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm
38410 /* 105514 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot
38411 /* 105517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38412 /* 105520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38413 /* 105526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38414 /* 105532 */ GIR_RootConstrainSelectedInstOperands,
38415 /* 105533 */ // GIR_Coverage, 4430,
38416 /* 105533 */ GIR_EraseRootFromParent_Done,
38417 /* 105534 */ // Label 3233: @105534
38418 /* 105534 */ GIM_Reject,
38419 /* 105535 */ // Label 3231: @105535
38420 /* 105535 */ GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(105683),
38421 /* 105540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38422 /* 105544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3235*/ GIMT_Encode4(105613), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6185 //
38423 /* 105551 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38424 /* 105555 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38425 /* 105559 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
38426 /* 105563 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38427 /* 105567 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38428 /* 105572 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38429 /* 105577 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
38430 /* 105581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38431 /* 105585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38432 /* 105587 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)<<P:Predicate_fmul_contract>>, QPR:{ *:[v8f16] }:$src1)<<P:Predicate_fadd_contract>> => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38433 /* 105587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
38434 /* 105590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38435 /* 105592 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
38436 /* 105594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38437 /* 105598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38438 /* 105602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38439 /* 105605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38440 /* 105611 */ GIR_RootConstrainSelectedInstOperands,
38441 /* 105612 */ // GIR_Coverage, 6185,
38442 /* 105612 */ GIR_EraseRootFromParent_Done,
38443 /* 105613 */ // Label 3235: @105613
38444 /* 105613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3236*/ GIMT_Encode4(105682), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1102 //
38445 /* 105620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38446 /* 105624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38447 /* 105628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38448 /* 105632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
38449 /* 105636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38450 /* 105640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38451 /* 105645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38452 /* 105650 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
38453 /* 105654 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38454 /* 105656 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38455 /* 105656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
38456 /* 105659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38457 /* 105661 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38458 /* 105663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38459 /* 105667 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38460 /* 105671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38461 /* 105674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38462 /* 105680 */ GIR_RootConstrainSelectedInstOperands,
38463 /* 105681 */ // GIR_Coverage, 1102,
38464 /* 105681 */ GIR_EraseRootFromParent_Done,
38465 /* 105682 */ // Label 3236: @105682
38466 /* 105682 */ GIM_Reject,
38467 /* 105683 */ // Label 3234: @105683
38468 /* 105683 */ GIM_Reject,
38469 /* 105684 */ // Label 3230: @105684
38470 /* 105684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3237*/ GIMT_Encode4(105723), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 887 //
38471 /* 105691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38472 /* 105695 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38473 /* 105699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38474 /* 105703 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38475 /* 105703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq),
38476 /* 105706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38477 /* 105708 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38478 /* 105710 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38479 /* 105712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38480 /* 105715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38481 /* 105721 */ GIR_RootConstrainSelectedInstOperands,
38482 /* 105722 */ // GIR_Coverage, 887,
38483 /* 105722 */ GIR_EraseRootFromParent_Done,
38484 /* 105723 */ // Label 3237: @105723
38485 /* 105723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3238*/ GIMT_Encode4(105783), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4462 //
38486 /* 105730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38487 /* 105734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38488 /* 105738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38489 /* 105742 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
38490 /* 105742 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38491 /* 105745 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38492 /* 105749 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38493 /* 105754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
38494 /* 105757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38495 /* 105759 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
38496 /* 105761 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
38497 /* 105763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38498 /* 105766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38499 /* 105772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38500 /* 105778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38501 /* 105781 */ GIR_RootConstrainSelectedInstOperands,
38502 /* 105782 */ // GIR_Coverage, 4462,
38503 /* 105782 */ GIR_EraseRootFromParent_Done,
38504 /* 105783 */ // Label 3238: @105783
38505 /* 105783 */ GIM_Reject,
38506 /* 105784 */ // Label 3229: @105784
38507 /* 105784 */ GIM_Reject,
38508 /* 105785 */ // Label 3208: @105785
38509 /* 105785 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3239*/ GIMT_Encode4(105830), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 884 //
38510 /* 105792 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38511 /* 105795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
38512 /* 105798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38513 /* 105802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38514 /* 105806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38515 /* 105810 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
38516 /* 105810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
38517 /* 105813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38518 /* 105815 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38519 /* 105817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38520 /* 105819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38521 /* 105822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38522 /* 105828 */ GIR_RootConstrainSelectedInstOperands,
38523 /* 105829 */ // GIR_Coverage, 884,
38524 /* 105829 */ GIR_EraseRootFromParent_Done,
38525 /* 105830 */ // Label 3239: @105830
38526 /* 105830 */ GIM_Reject,
38527 /* 105831 */ // Label 3209: @105831
38528 /* 105831 */ GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(106144),
38529 /* 105836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
38530 /* 105839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
38531 /* 105842 */ GIM_Try, /*On fail goto*//*Label 3241*/ GIMT_Encode4(106044),
38532 /* 105847 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
38533 /* 105851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38534 /* 105855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3242*/ GIMT_Encode4(105949), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6673 //
38535 /* 105862 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38536 /* 105866 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38537 /* 105870 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5,
38538 /* 105873 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
38539 /* 105878 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38540 /* 105882 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
38541 /* 105886 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v4s32,
38542 /* 105890 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
38543 /* 105894 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38544 /* 105898 */ // MIs[2] Operand 1
38545 /* 105898 */ // No operand predicates
38546 /* 105898 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38547 /* 105903 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38548 /* 105908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38549 /* 105912 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
38550 /* 105914 */ // (fadd:{ *:[v4f32] } (intrinsic_wo_chain:{ *:[v4f32] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm), MQPR:{ *:[v4f32] }:$Qd_src)<<P:Predicate_fadd_contract>> => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
38551 /* 105914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32),
38552 /* 105917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38553 /* 105919 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
38554 /* 105921 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn
38555 /* 105925 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm
38556 /* 105929 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot
38557 /* 105932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38558 /* 105935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38559 /* 105941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38560 /* 105947 */ GIR_RootConstrainSelectedInstOperands,
38561 /* 105948 */ // GIR_Coverage, 6673,
38562 /* 105948 */ GIR_EraseRootFromParent_Done,
38563 /* 105949 */ // Label 3242: @105949
38564 /* 105949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3243*/ GIMT_Encode4(106043), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4433 //
38565 /* 105956 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38566 /* 105960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38567 /* 105964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
38568 /* 105968 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5,
38569 /* 105971 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
38570 /* 105976 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38571 /* 105980 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
38572 /* 105984 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v4s32,
38573 /* 105988 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
38574 /* 105992 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38575 /* 105996 */ // MIs[2] Operand 1
38576 /* 105996 */ // No operand predicates
38577 /* 105996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38578 /* 106001 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38579 /* 106006 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
38580 /* 106008 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, (intrinsic_wo_chain:{ *:[v4f32] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm))<<P:Predicate_fadd_contract>> => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
38581 /* 106008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32),
38582 /* 106011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38583 /* 106013 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd_src
38584 /* 106015 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn
38585 /* 106019 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm
38586 /* 106023 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot
38587 /* 106026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38588 /* 106029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38589 /* 106035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38590 /* 106041 */ GIR_RootConstrainSelectedInstOperands,
38591 /* 106042 */ // GIR_Coverage, 4433,
38592 /* 106042 */ GIR_EraseRootFromParent_Done,
38593 /* 106043 */ // Label 3243: @106043
38594 /* 106043 */ GIM_Reject,
38595 /* 106044 */ // Label 3241: @106044
38596 /* 106044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3244*/ GIMT_Encode4(106083), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 885 //
38597 /* 106051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38598 /* 106055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38599 /* 106059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38600 /* 106063 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
38601 /* 106063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq),
38602 /* 106066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38603 /* 106068 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38604 /* 106070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38605 /* 106072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38606 /* 106075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38607 /* 106081 */ GIR_RootConstrainSelectedInstOperands,
38608 /* 106082 */ // GIR_Coverage, 885,
38609 /* 106082 */ GIR_EraseRootFromParent_Done,
38610 /* 106083 */ // Label 3244: @106083
38611 /* 106083 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3245*/ GIMT_Encode4(106143), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4455 //
38612 /* 106090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38613 /* 106094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38614 /* 106098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38615 /* 106102 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
38616 /* 106102 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38617 /* 106105 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38618 /* 106109 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38619 /* 106114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
38620 /* 106117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38621 /* 106119 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
38622 /* 106121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
38623 /* 106123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38624 /* 106126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38625 /* 106132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38626 /* 106138 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38627 /* 106141 */ GIR_RootConstrainSelectedInstOperands,
38628 /* 106142 */ // GIR_Coverage, 4455,
38629 /* 106142 */ GIR_EraseRootFromParent_Done,
38630 /* 106143 */ // Label 3245: @106143
38631 /* 106143 */ GIM_Reject,
38632 /* 106144 */ // Label 3240: @106144
38633 /* 106144 */ GIM_Reject,
38634 /* 106145 */ // Label 3210: @106145
38635 /* 106145 */ GIM_Reject,
38636 /* 106146 */ // Label 42: @106146
38637 /* 106146 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3253*/ GIMT_Encode4(107858),
38638 /* 106157 */ /*GILLT_s16*//*Label 3246*/ GIMT_Encode4(106209),
38639 /* 106161 */ /*GILLT_s32*//*Label 3247*/ GIMT_Encode4(106255),
38640 /* 106165 */ /*GILLT_s64*//*Label 3248*/ GIMT_Encode4(107202), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38641 /* 106193 */ /*GILLT_v4s16*//*Label 3249*/ GIMT_Encode4(107248),
38642 /* 106197 */ /*GILLT_v8s16*//*Label 3250*/ GIMT_Encode4(107444),
38643 /* 106201 */ /*GILLT_v2s32*//*Label 3251*/ GIMT_Encode4(107700),
38644 /* 106205 */ /*GILLT_v4s32*//*Label 3252*/ GIMT_Encode4(107746),
38645 /* 106209 */ // Label 3246: @106209
38646 /* 106209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3254*/ GIMT_Encode4(106254), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 627 //
38647 /* 106216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
38648 /* 106219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
38649 /* 106222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38650 /* 106226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38651 /* 106230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38652 /* 106234 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
38653 /* 106234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
38654 /* 106237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38655 /* 106239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
38656 /* 106241 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
38657 /* 106243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38658 /* 106246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38659 /* 106252 */ GIR_RootConstrainSelectedInstOperands,
38660 /* 106253 */ // GIR_Coverage, 627,
38661 /* 106253 */ GIR_EraseRootFromParent_Done,
38662 /* 106254 */ // Label 3254: @106254
38663 /* 106254 */ GIM_Reject,
38664 /* 106255 */ // Label 3247: @106255
38665 /* 106255 */ GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(107201),
38666 /* 106260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38667 /* 106263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38668 /* 106266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3256*/ GIMT_Encode4(106605), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3092 //
38669 /* 106273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38670 /* 106277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38671 /* 106281 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38672 /* 106285 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38673 /* 106289 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38674 /* 106293 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38675 /* 106297 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38676 /* 106302 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38677 /* 106307 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
38678 /* 106311 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract),
38679 /* 106315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38680 /* 106317 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38681 /* 106317 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
38682 /* 106320 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38683 /* 106324 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38684 /* 106329 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
38685 /* 106331 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
38686 /* 106334 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38687 /* 106338 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38688 /* 106343 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
38689 /* 106346 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38690 /* 106351 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
38691 /* 106354 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38692 /* 106358 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38693 /* 106363 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
38694 /* 106366 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
38695 /* 106370 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
38696 /* 106373 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38697 /* 106378 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38698 /* 106383 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38699 /* 106388 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38700 /* 106391 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38701 /* 106395 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38702 /* 106400 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38703 /* 106402 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38704 /* 106405 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38705 /* 106409 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38706 /* 106414 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38707 /* 106417 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38708 /* 106422 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38709 /* 106425 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38710 /* 106429 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38711 /* 106434 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38712 /* 106437 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
38713 /* 106441 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38714 /* 106444 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38715 /* 106449 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38716 /* 106454 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38717 /* 106459 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38718 /* 106462 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38719 /* 106466 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38720 /* 106471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38721 /* 106473 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38722 /* 106476 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38723 /* 106480 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38724 /* 106485 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38725 /* 106488 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38726 /* 106493 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38727 /* 106496 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38728 /* 106500 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38729 /* 106505 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38730 /* 106508 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
38731 /* 106512 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38732 /* 106515 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38733 /* 106520 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38734 /* 106525 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38735 /* 106530 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38736 /* 106533 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
38737 /* 106537 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38738 /* 106542 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38739 /* 106545 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38740 /* 106548 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38741 /* 106551 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38742 /* 106554 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38743 /* 106560 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38744 /* 106562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38745 /* 106565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38746 /* 106569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38747 /* 106574 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38748 /* 106577 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38749 /* 106582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38750 /* 106585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38751 /* 106587 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38752 /* 106594 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38753 /* 106599 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38754 /* 106604 */ // GIR_Coverage, 3092,
38755 /* 106604 */ GIR_EraseRootFromParent_Done,
38756 /* 106605 */ // Label 3256: @106605
38757 /* 106605 */ GIM_Try, /*On fail goto*//*Label 3257*/ GIMT_Encode4(107200),
38758 /* 106610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38759 /* 106614 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38760 /* 106618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3258*/ GIMT_Encode4(106941), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3090 //
38761 /* 106625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38762 /* 106629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38763 /* 106633 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38764 /* 106637 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38765 /* 106641 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38766 /* 106646 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38767 /* 106651 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38768 /* 106653 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38769 /* 106653 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
38770 /* 106656 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38771 /* 106660 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38772 /* 106665 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
38773 /* 106667 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
38774 /* 106670 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38775 /* 106674 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38776 /* 106679 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
38777 /* 106682 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38778 /* 106687 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
38779 /* 106690 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38780 /* 106694 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38781 /* 106699 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
38782 /* 106702 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
38783 /* 106706 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
38784 /* 106709 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38785 /* 106714 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38786 /* 106719 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38787 /* 106724 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38788 /* 106727 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38789 /* 106731 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38790 /* 106736 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38791 /* 106738 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38792 /* 106741 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38793 /* 106745 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38794 /* 106750 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38795 /* 106753 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38796 /* 106758 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38797 /* 106761 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38798 /* 106765 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38799 /* 106770 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38800 /* 106773 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
38801 /* 106777 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38802 /* 106780 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38803 /* 106785 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38804 /* 106790 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38805 /* 106795 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38806 /* 106798 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38807 /* 106802 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38808 /* 106807 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38809 /* 106809 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38810 /* 106812 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38811 /* 106816 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38812 /* 106821 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38813 /* 106824 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38814 /* 106829 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38815 /* 106832 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38816 /* 106836 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38817 /* 106841 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38818 /* 106844 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
38819 /* 106848 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38820 /* 106851 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38821 /* 106856 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38822 /* 106861 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38823 /* 106866 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38824 /* 106869 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd),
38825 /* 106873 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38826 /* 106878 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38827 /* 106881 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38828 /* 106884 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38829 /* 106887 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38830 /* 106890 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38831 /* 106896 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38832 /* 106898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38833 /* 106901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38834 /* 106905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38835 /* 106910 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38836 /* 106913 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38837 /* 106918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38838 /* 106921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38839 /* 106923 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38840 /* 106930 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38841 /* 106935 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38842 /* 106940 */ // GIR_Coverage, 3090,
38843 /* 106940 */ GIR_EraseRootFromParent_Done,
38844 /* 106941 */ // Label 3258: @106941
38845 /* 106941 */ GIM_Try, /*On fail goto*//*Label 3259*/ GIMT_Encode4(107199),
38846 /* 106946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38847 /* 106950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3260*/ GIMT_Encode4(106977), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 625 //
38848 /* 106957 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
38849 /* 106957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
38850 /* 106960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38851 /* 106962 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
38852 /* 106964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
38853 /* 106966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38854 /* 106969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38855 /* 106975 */ GIR_RootConstrainSelectedInstOperands,
38856 /* 106976 */ // GIR_Coverage, 625,
38857 /* 106976 */ GIR_EraseRootFromParent_Done,
38858 /* 106977 */ // Label 3260: @106977
38859 /* 106977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3261*/ GIMT_Encode4(107198), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3087 //
38860 /* 106984 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38861 /* 106984 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38862 /* 106987 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38863 /* 106991 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38864 /* 106996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38865 /* 106998 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38866 /* 107001 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38867 /* 107005 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38868 /* 107010 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38869 /* 107013 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38870 /* 107018 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38871 /* 107021 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38872 /* 107025 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38873 /* 107030 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38874 /* 107033 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
38875 /* 107037 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38876 /* 107040 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38877 /* 107045 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38878 /* 107050 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38879 /* 107055 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38880 /* 107058 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38881 /* 107062 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38882 /* 107067 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38883 /* 107069 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38884 /* 107072 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38885 /* 107076 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38886 /* 107081 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38887 /* 107084 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38888 /* 107089 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38889 /* 107092 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38890 /* 107096 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38891 /* 107101 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38892 /* 107104 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
38893 /* 107108 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38894 /* 107111 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38895 /* 107116 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38896 /* 107121 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38897 /* 107126 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38898 /* 107129 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
38899 /* 107133 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38900 /* 107138 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38901 /* 107141 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38902 /* 107144 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38903 /* 107147 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38904 /* 107153 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38905 /* 107155 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38906 /* 107158 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38907 /* 107162 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38908 /* 107167 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38909 /* 107170 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38910 /* 107175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38911 /* 107178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38912 /* 107180 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38913 /* 107187 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38914 /* 107192 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38915 /* 107197 */ // GIR_Coverage, 3087,
38916 /* 107197 */ GIR_EraseRootFromParent_Done,
38917 /* 107198 */ // Label 3261: @107198
38918 /* 107198 */ GIM_Reject,
38919 /* 107199 */ // Label 3259: @107199
38920 /* 107199 */ GIM_Reject,
38921 /* 107200 */ // Label 3257: @107200
38922 /* 107200 */ GIM_Reject,
38923 /* 107201 */ // Label 3255: @107201
38924 /* 107201 */ GIM_Reject,
38925 /* 107202 */ // Label 3248: @107202
38926 /* 107202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3262*/ GIMT_Encode4(107247), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 623 //
38927 /* 107209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
38928 /* 107212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
38929 /* 107215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38930 /* 107219 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38931 /* 107223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38932 /* 107227 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
38933 /* 107227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
38934 /* 107230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
38935 /* 107232 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
38936 /* 107234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
38937 /* 107236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38938 /* 107239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38939 /* 107245 */ GIR_RootConstrainSelectedInstOperands,
38940 /* 107246 */ // GIR_Coverage, 623,
38941 /* 107246 */ GIR_EraseRootFromParent_Done,
38942 /* 107247 */ // Label 3262: @107247
38943 /* 107247 */ GIM_Reject,
38944 /* 107248 */ // Label 3249: @107248
38945 /* 107248 */ GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(107443),
38946 /* 107253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38947 /* 107256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
38948 /* 107259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3264*/ GIMT_Encode4(107336), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1111 //
38949 /* 107266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38950 /* 107270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38951 /* 107274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38952 /* 107278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38953 /* 107282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38954 /* 107286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38955 /* 107290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38956 /* 107295 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38957 /* 107300 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
38958 /* 107304 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract),
38959 /* 107308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38960 /* 107310 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38961 /* 107310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd),
38962 /* 107313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38963 /* 107315 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38964 /* 107317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38965 /* 107321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38966 /* 107325 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38967 /* 107328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38968 /* 107334 */ GIR_RootConstrainSelectedInstOperands,
38969 /* 107335 */ // GIR_Coverage, 1111,
38970 /* 107335 */ GIR_EraseRootFromParent_Done,
38971 /* 107336 */ // Label 3264: @107336
38972 /* 107336 */ GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(107442),
38973 /* 107341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38974 /* 107345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38975 /* 107349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3266*/ GIMT_Encode4(107410), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1067 //
38976 /* 107356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38977 /* 107360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38978 /* 107364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38979 /* 107368 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38980 /* 107372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38981 /* 107377 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38982 /* 107382 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38983 /* 107384 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38984 /* 107384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd),
38985 /* 107387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38986 /* 107389 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38987 /* 107391 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38988 /* 107395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38989 /* 107399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38990 /* 107402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38991 /* 107408 */ GIR_RootConstrainSelectedInstOperands,
38992 /* 107409 */ // GIR_Coverage, 1067,
38993 /* 107409 */ GIR_EraseRootFromParent_Done,
38994 /* 107410 */ // Label 3266: @107410
38995 /* 107410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3267*/ GIMT_Encode4(107441), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1132 //
38996 /* 107417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38997 /* 107421 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38998 /* 107421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd),
38999 /* 107424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39000 /* 107426 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39001 /* 107428 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39002 /* 107430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39003 /* 107433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39004 /* 107439 */ GIR_RootConstrainSelectedInstOperands,
39005 /* 107440 */ // GIR_Coverage, 1132,
39006 /* 107440 */ GIR_EraseRootFromParent_Done,
39007 /* 107441 */ // Label 3267: @107441
39008 /* 107441 */ GIM_Reject,
39009 /* 107442 */ // Label 3265: @107442
39010 /* 107442 */ GIM_Reject,
39011 /* 107443 */ // Label 3263: @107443
39012 /* 107443 */ GIM_Reject,
39013 /* 107444 */ // Label 3250: @107444
39014 /* 107444 */ GIM_Try, /*On fail goto*//*Label 3268*/ GIMT_Encode4(107699),
39015 /* 107449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39016 /* 107452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39017 /* 107455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3269*/ GIMT_Encode4(107532), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1112 //
39018 /* 107462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39019 /* 107466 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39020 /* 107470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39021 /* 107474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
39022 /* 107478 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39023 /* 107482 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
39024 /* 107486 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39025 /* 107491 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39026 /* 107496 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
39027 /* 107500 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract),
39028 /* 107504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39029 /* 107506 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39030 /* 107506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq),
39031 /* 107509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39032 /* 107511 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
39033 /* 107513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39034 /* 107517 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39035 /* 107521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39036 /* 107524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39037 /* 107530 */ GIR_RootConstrainSelectedInstOperands,
39038 /* 107531 */ // GIR_Coverage, 1112,
39039 /* 107531 */ GIR_EraseRootFromParent_Done,
39040 /* 107532 */ // Label 3269: @107532
39041 /* 107532 */ GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(107638),
39042 /* 107537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39043 /* 107541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39044 /* 107545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3271*/ GIMT_Encode4(107606), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1068 //
39045 /* 107552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39046 /* 107556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
39047 /* 107560 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39048 /* 107564 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
39049 /* 107568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39050 /* 107573 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39051 /* 107578 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39052 /* 107580 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39053 /* 107580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq),
39054 /* 107583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39055 /* 107585 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
39056 /* 107587 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39057 /* 107591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39058 /* 107595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39059 /* 107598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39060 /* 107604 */ GIR_RootConstrainSelectedInstOperands,
39061 /* 107605 */ // GIR_Coverage, 1068,
39062 /* 107605 */ GIR_EraseRootFromParent_Done,
39063 /* 107606 */ // Label 3271: @107606
39064 /* 107606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3272*/ GIMT_Encode4(107637), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1133 //
39065 /* 107613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39066 /* 107617 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39067 /* 107617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq),
39068 /* 107620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39069 /* 107622 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39070 /* 107624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39071 /* 107626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39072 /* 107629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39073 /* 107635 */ GIR_RootConstrainSelectedInstOperands,
39074 /* 107636 */ // GIR_Coverage, 1133,
39075 /* 107636 */ GIR_EraseRootFromParent_Done,
39076 /* 107637 */ // Label 3272: @107637
39077 /* 107637 */ GIM_Reject,
39078 /* 107638 */ // Label 3270: @107638
39079 /* 107638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3273*/ GIMT_Encode4(107698), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4476 //
39080 /* 107645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39081 /* 107649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39082 /* 107653 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39083 /* 107657 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
39084 /* 107657 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39085 /* 107660 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39086 /* 107664 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39087 /* 107669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
39088 /* 107672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39089 /* 107674 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39090 /* 107676 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39091 /* 107678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39092 /* 107681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39093 /* 107687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39094 /* 107693 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39095 /* 107696 */ GIR_RootConstrainSelectedInstOperands,
39096 /* 107697 */ // GIR_Coverage, 4476,
39097 /* 107697 */ GIR_EraseRootFromParent_Done,
39098 /* 107698 */ // Label 3273: @107698
39099 /* 107698 */ GIM_Reject,
39100 /* 107699 */ // Label 3268: @107699
39101 /* 107699 */ GIM_Reject,
39102 /* 107700 */ // Label 3251: @107700
39103 /* 107700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3274*/ GIMT_Encode4(107745), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1130 //
39104 /* 107707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
39105 /* 107710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
39106 /* 107713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39107 /* 107717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39108 /* 107721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39109 /* 107725 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
39110 /* 107725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
39111 /* 107728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39112 /* 107730 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39113 /* 107732 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39114 /* 107734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39115 /* 107737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39116 /* 107743 */ GIR_RootConstrainSelectedInstOperands,
39117 /* 107744 */ // GIR_Coverage, 1130,
39118 /* 107744 */ GIR_EraseRootFromParent_Done,
39119 /* 107745 */ // Label 3274: @107745
39120 /* 107745 */ GIM_Reject,
39121 /* 107746 */ // Label 3252: @107746
39122 /* 107746 */ GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(107857),
39123 /* 107751 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39124 /* 107754 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39125 /* 107757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3276*/ GIMT_Encode4(107796), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1131 //
39126 /* 107764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39127 /* 107768 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39128 /* 107772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39129 /* 107776 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
39130 /* 107776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq),
39131 /* 107779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39132 /* 107781 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39133 /* 107783 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39134 /* 107785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39135 /* 107788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39136 /* 107794 */ GIR_RootConstrainSelectedInstOperands,
39137 /* 107795 */ // GIR_Coverage, 1131,
39138 /* 107795 */ GIR_EraseRootFromParent_Done,
39139 /* 107796 */ // Label 3276: @107796
39140 /* 107796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3277*/ GIMT_Encode4(107856), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4469 //
39141 /* 107803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39142 /* 107807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39143 /* 107811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39144 /* 107815 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
39145 /* 107815 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39146 /* 107818 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39147 /* 107822 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39148 /* 107827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
39149 /* 107830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39150 /* 107832 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39151 /* 107834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39152 /* 107836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39153 /* 107839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39154 /* 107845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39155 /* 107851 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39156 /* 107854 */ GIR_RootConstrainSelectedInstOperands,
39157 /* 107855 */ // GIR_Coverage, 4469,
39158 /* 107855 */ GIR_EraseRootFromParent_Done,
39159 /* 107856 */ // Label 3277: @107856
39160 /* 107856 */ GIM_Reject,
39161 /* 107857 */ // Label 3275: @107857
39162 /* 107857 */ GIM_Reject,
39163 /* 107858 */ // Label 3253: @107858
39164 /* 107858 */ GIM_Reject,
39165 /* 107859 */ // Label 43: @107859
39166 /* 107859 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3285*/ GIMT_Encode4(108823),
39167 /* 107870 */ /*GILLT_s16*//*Label 3278*/ GIMT_Encode4(107922),
39168 /* 107874 */ /*GILLT_s32*//*Label 3279*/ GIMT_Encode4(107968),
39169 /* 107878 */ /*GILLT_s64*//*Label 3280*/ GIMT_Encode4(108349), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39170 /* 107906 */ /*GILLT_v4s16*//*Label 3281*/ GIMT_Encode4(108507),
39171 /* 107910 */ /*GILLT_v8s16*//*Label 3282*/ GIMT_Encode4(108553),
39172 /* 107914 */ /*GILLT_v2s32*//*Label 3283*/ GIMT_Encode4(108665),
39173 /* 107918 */ /*GILLT_v4s32*//*Label 3284*/ GIMT_Encode4(108711),
39174 /* 107922 */ // Label 3278: @107922
39175 /* 107922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3286*/ GIMT_Encode4(107967), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 639 //
39176 /* 107929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
39177 /* 107932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
39178 /* 107935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39179 /* 107939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39180 /* 107943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39181 /* 107947 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39182 /* 107947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
39183 /* 107950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39184 /* 107952 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39185 /* 107954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39186 /* 107956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39187 /* 107959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39188 /* 107965 */ GIR_RootConstrainSelectedInstOperands,
39189 /* 107966 */ // GIR_Coverage, 639,
39190 /* 107966 */ GIR_EraseRootFromParent_Done,
39191 /* 107967 */ // Label 3286: @107967
39192 /* 107967 */ GIM_Reject,
39193 /* 107968 */ // Label 3279: @107968
39194 /* 107968 */ GIM_Try, /*On fail goto*//*Label 3287*/ GIMT_Encode4(108348),
39195 /* 107973 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39196 /* 107976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39197 /* 107979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39198 /* 107983 */ GIM_Try, /*On fail goto*//*Label 3288*/ GIMT_Encode4(108033), // Rule ID 2502 //
39199 /* 107988 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39200 /* 107992 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39201 /* 107996 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39202 /* 108000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39203 /* 108005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39204 /* 108009 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39205 /* 108011 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
39206 /* 108011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
39207 /* 108014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39208 /* 108016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
39209 /* 108020 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
39210 /* 108022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39211 /* 108025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39212 /* 108031 */ GIR_RootConstrainSelectedInstOperands,
39213 /* 108032 */ // GIR_Coverage, 2502,
39214 /* 108032 */ GIR_EraseRootFromParent_Done,
39215 /* 108033 */ // Label 3288: @108033
39216 /* 108033 */ GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(108347),
39217 /* 108038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39218 /* 108042 */ GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(108088), // Rule ID 6320 //
39219 /* 108047 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39220 /* 108051 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39221 /* 108055 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39222 /* 108059 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39223 /* 108064 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39224 /* 108066 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
39225 /* 108066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
39226 /* 108069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39227 /* 108071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
39228 /* 108075 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
39229 /* 108077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39230 /* 108080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39231 /* 108086 */ GIR_RootConstrainSelectedInstOperands,
39232 /* 108087 */ // GIR_Coverage, 6320,
39233 /* 108087 */ GIR_EraseRootFromParent_Done,
39234 /* 108088 */ // Label 3290: @108088
39235 /* 108088 */ GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(108346),
39236 /* 108093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39237 /* 108097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3292*/ GIMT_Encode4(108124), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 637 //
39238 /* 108104 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39239 /* 108104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
39240 /* 108107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39241 /* 108109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39242 /* 108111 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39243 /* 108113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39244 /* 108116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39245 /* 108122 */ GIR_RootConstrainSelectedInstOperands,
39246 /* 108123 */ // GIR_Coverage, 637,
39247 /* 108123 */ GIR_EraseRootFromParent_Done,
39248 /* 108124 */ // Label 3292: @108124
39249 /* 108124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3293*/ GIMT_Encode4(108345), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3088 //
39250 /* 108131 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
39251 /* 108131 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
39252 /* 108134 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39253 /* 108138 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39254 /* 108143 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
39255 /* 108145 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
39256 /* 108148 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39257 /* 108152 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39258 /* 108157 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
39259 /* 108160 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39260 /* 108165 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
39261 /* 108168 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
39262 /* 108172 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39263 /* 108177 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
39264 /* 108180 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
39265 /* 108184 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
39266 /* 108187 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39267 /* 108192 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39268 /* 108197 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
39269 /* 108202 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
39270 /* 108205 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39271 /* 108209 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39272 /* 108214 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
39273 /* 108216 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
39274 /* 108219 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39275 /* 108223 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39276 /* 108228 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
39277 /* 108231 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39278 /* 108236 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
39279 /* 108239 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
39280 /* 108243 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39281 /* 108248 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
39282 /* 108251 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
39283 /* 108255 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
39284 /* 108258 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39285 /* 108263 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39286 /* 108268 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
39287 /* 108273 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
39288 /* 108276 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
39289 /* 108280 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39290 /* 108285 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
39291 /* 108288 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
39292 /* 108291 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
39293 /* 108294 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39294 /* 108300 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39295 /* 108302 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
39296 /* 108305 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39297 /* 108309 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39298 /* 108314 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
39299 /* 108317 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39300 /* 108322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39301 /* 108325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39302 /* 108327 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
39303 /* 108334 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
39304 /* 108339 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39305 /* 108344 */ // GIR_Coverage, 3088,
39306 /* 108344 */ GIR_EraseRootFromParent_Done,
39307 /* 108345 */ // Label 3293: @108345
39308 /* 108345 */ GIM_Reject,
39309 /* 108346 */ // Label 3291: @108346
39310 /* 108346 */ GIM_Reject,
39311 /* 108347 */ // Label 3289: @108347
39312 /* 108347 */ GIM_Reject,
39313 /* 108348 */ // Label 3287: @108348
39314 /* 108348 */ GIM_Reject,
39315 /* 108349 */ // Label 3280: @108349
39316 /* 108349 */ GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(108506),
39317 /* 108354 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
39318 /* 108357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39319 /* 108360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39320 /* 108364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3295*/ GIMT_Encode4(108416), GIMT_Encode2(GIFBS_HasDPVFP), // Rule ID 2501 //
39321 /* 108371 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39322 /* 108375 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39323 /* 108379 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39324 /* 108383 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39325 /* 108388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39326 /* 108392 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39327 /* 108394 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
39328 /* 108394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
39329 /* 108397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39330 /* 108399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
39331 /* 108403 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
39332 /* 108405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39333 /* 108408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39334 /* 108414 */ GIR_RootConstrainSelectedInstOperands,
39335 /* 108415 */ // GIR_Coverage, 2501,
39336 /* 108415 */ GIR_EraseRootFromParent_Done,
39337 /* 108416 */ // Label 3295: @108416
39338 /* 108416 */ GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(108505),
39339 /* 108421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39340 /* 108425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3297*/ GIMT_Encode4(108473), GIMT_Encode2(GIFBS_HasDPVFP), // Rule ID 6319 //
39341 /* 108432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39342 /* 108436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39343 /* 108440 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39344 /* 108444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39345 /* 108449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39346 /* 108451 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
39347 /* 108451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
39348 /* 108454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39349 /* 108456 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
39350 /* 108460 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
39351 /* 108462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39352 /* 108465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39353 /* 108471 */ GIR_RootConstrainSelectedInstOperands,
39354 /* 108472 */ // GIR_Coverage, 6319,
39355 /* 108472 */ GIR_EraseRootFromParent_Done,
39356 /* 108473 */ // Label 3297: @108473
39357 /* 108473 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3298*/ GIMT_Encode4(108504), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 635 //
39358 /* 108480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39359 /* 108484 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39360 /* 108484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
39361 /* 108487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39362 /* 108489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
39363 /* 108491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39364 /* 108493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39365 /* 108496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39366 /* 108502 */ GIR_RootConstrainSelectedInstOperands,
39367 /* 108503 */ // GIR_Coverage, 635,
39368 /* 108503 */ GIR_EraseRootFromParent_Done,
39369 /* 108504 */ // Label 3298: @108504
39370 /* 108504 */ GIM_Reject,
39371 /* 108505 */ // Label 3296: @108505
39372 /* 108505 */ GIM_Reject,
39373 /* 108506 */ // Label 3294: @108506
39374 /* 108506 */ GIM_Reject,
39375 /* 108507 */ // Label 3281: @108507
39376 /* 108507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3299*/ GIMT_Encode4(108552), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 965 //
39377 /* 108514 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
39378 /* 108517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
39379 /* 108520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39380 /* 108524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39381 /* 108528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39382 /* 108532 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
39383 /* 108532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd),
39384 /* 108535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39385 /* 108537 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39386 /* 108539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39387 /* 108541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39388 /* 108544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39389 /* 108550 */ GIR_RootConstrainSelectedInstOperands,
39390 /* 108551 */ // GIR_Coverage, 965,
39391 /* 108551 */ GIR_EraseRootFromParent_Done,
39392 /* 108552 */ // Label 3299: @108552
39393 /* 108552 */ GIM_Reject,
39394 /* 108553 */ // Label 3282: @108553
39395 /* 108553 */ GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(108664),
39396 /* 108558 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39397 /* 108561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39398 /* 108564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3301*/ GIMT_Encode4(108603), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 966 //
39399 /* 108571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39400 /* 108575 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39401 /* 108579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39402 /* 108583 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39403 /* 108583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq),
39404 /* 108586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39405 /* 108588 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39406 /* 108590 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39407 /* 108592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39408 /* 108595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39409 /* 108601 */ GIR_RootConstrainSelectedInstOperands,
39410 /* 108602 */ // GIR_Coverage, 966,
39411 /* 108602 */ GIR_EraseRootFromParent_Done,
39412 /* 108603 */ // Label 3301: @108603
39413 /* 108603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3302*/ GIMT_Encode4(108663), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4422 //
39414 /* 108610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39415 /* 108614 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39416 /* 108618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39417 /* 108622 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
39418 /* 108622 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39419 /* 108625 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39420 /* 108629 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39421 /* 108634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
39422 /* 108637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39423 /* 108639 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39424 /* 108641 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39425 /* 108643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39426 /* 108646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39427 /* 108652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39428 /* 108658 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39429 /* 108661 */ GIR_RootConstrainSelectedInstOperands,
39430 /* 108662 */ // GIR_Coverage, 4422,
39431 /* 108662 */ GIR_EraseRootFromParent_Done,
39432 /* 108663 */ // Label 3302: @108663
39433 /* 108663 */ GIM_Reject,
39434 /* 108664 */ // Label 3300: @108664
39435 /* 108664 */ GIM_Reject,
39436 /* 108665 */ // Label 3283: @108665
39437 /* 108665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3303*/ GIMT_Encode4(108710), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 963 //
39438 /* 108672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
39439 /* 108675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
39440 /* 108678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39441 /* 108682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39442 /* 108686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39443 /* 108690 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
39444 /* 108690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
39445 /* 108693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39446 /* 108695 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39447 /* 108697 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39448 /* 108699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39449 /* 108702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39450 /* 108708 */ GIR_RootConstrainSelectedInstOperands,
39451 /* 108709 */ // GIR_Coverage, 963,
39452 /* 108709 */ GIR_EraseRootFromParent_Done,
39453 /* 108710 */ // Label 3303: @108710
39454 /* 108710 */ GIM_Reject,
39455 /* 108711 */ // Label 3284: @108711
39456 /* 108711 */ GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(108822),
39457 /* 108716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39458 /* 108719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39459 /* 108722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3305*/ GIMT_Encode4(108761), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 964 //
39460 /* 108729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39461 /* 108733 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39462 /* 108737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39463 /* 108741 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
39464 /* 108741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq),
39465 /* 108744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39466 /* 108746 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39467 /* 108748 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39468 /* 108750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39469 /* 108753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39470 /* 108759 */ GIR_RootConstrainSelectedInstOperands,
39471 /* 108760 */ // GIR_Coverage, 964,
39472 /* 108760 */ GIR_EraseRootFromParent_Done,
39473 /* 108761 */ // Label 3305: @108761
39474 /* 108761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3306*/ GIMT_Encode4(108821), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4415 //
39475 /* 108768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39476 /* 108772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39477 /* 108776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39478 /* 108780 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
39479 /* 108780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39480 /* 108783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39481 /* 108787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39482 /* 108792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
39483 /* 108795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39484 /* 108797 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39485 /* 108799 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39486 /* 108801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39487 /* 108804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39488 /* 108810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39489 /* 108816 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39490 /* 108819 */ GIR_RootConstrainSelectedInstOperands,
39491 /* 108820 */ // GIR_Coverage, 4415,
39492 /* 108820 */ GIR_EraseRootFromParent_Done,
39493 /* 108821 */ // Label 3306: @108821
39494 /* 108821 */ GIM_Reject,
39495 /* 108822 */ // Label 3304: @108822
39496 /* 108822 */ GIM_Reject,
39497 /* 108823 */ // Label 3285: @108823
39498 /* 108823 */ GIM_Reject,
39499 /* 108824 */ // Label 44: @108824
39500 /* 108824 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3314*/ GIMT_Encode4(110886),
39501 /* 108835 */ /*GILLT_s16*//*Label 3307*/ GIMT_Encode4(108887),
39502 /* 108839 */ /*GILLT_s32*//*Label 3308*/ GIMT_Encode4(109268),
39503 /* 108843 */ /*GILLT_s64*//*Label 3309*/ GIMT_Encode4(109649), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39504 /* 108871 */ /*GILLT_v4s16*//*Label 3310*/ GIMT_Encode4(110030),
39505 /* 108875 */ /*GILLT_v8s16*//*Label 3311*/ GIMT_Encode4(110085),
39506 /* 108879 */ /*GILLT_v2s32*//*Label 3312*/ GIMT_Encode4(110335),
39507 /* 108883 */ /*GILLT_v4s32*//*Label 3313*/ GIMT_Encode4(110514),
39508 /* 108887 */ // Label 3307: @108887
39509 /* 108887 */ GIM_Try, /*On fail goto*//*Label 3315*/ GIMT_Encode4(109267),
39510 /* 108892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
39511 /* 108895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
39512 /* 108898 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
39513 /* 108901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39514 /* 108905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3316*/ GIMT_Encode4(108978), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2775 //
39515 /* 108912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39516 /* 108916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39517 /* 108920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39518 /* 108924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39519 /* 108929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39520 /* 108933 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39521 /* 108937 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39522 /* 108941 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
39523 /* 108945 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39524 /* 108950 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39525 /* 108952 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39526 /* 108952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
39527 /* 108955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39528 /* 108957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39529 /* 108961 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39530 /* 108965 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39531 /* 108967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39532 /* 108970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39533 /* 108976 */ GIR_RootConstrainSelectedInstOperands,
39534 /* 108977 */ // GIR_Coverage, 2775,
39535 /* 108977 */ GIR_EraseRootFromParent_Done,
39536 /* 108978 */ // Label 3316: @108978
39537 /* 108978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3317*/ GIMT_Encode4(109051), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6340 //
39538 /* 108985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39539 /* 108989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39540 /* 108993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39541 /* 108997 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39542 /* 109001 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39543 /* 109006 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39544 /* 109010 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39545 /* 109014 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
39546 /* 109018 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39547 /* 109023 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39548 /* 109025 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39549 /* 109025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
39550 /* 109028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39551 /* 109030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39552 /* 109034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39553 /* 109038 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39554 /* 109040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39555 /* 109043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39556 /* 109049 */ GIR_RootConstrainSelectedInstOperands,
39557 /* 109050 */ // GIR_Coverage, 6340,
39558 /* 109050 */ GIR_EraseRootFromParent_Done,
39559 /* 109051 */ // Label 3317: @109051
39560 /* 109051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3318*/ GIMT_Encode4(109109), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2755 //
39561 /* 109058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39562 /* 109062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39563 /* 109066 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39564 /* 109070 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39565 /* 109075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39566 /* 109079 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39567 /* 109083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39568 /* 109085 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39569 /* 109085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
39570 /* 109088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39571 /* 109090 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39572 /* 109092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39573 /* 109096 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39574 /* 109098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39575 /* 109101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39576 /* 109107 */ GIR_RootConstrainSelectedInstOperands,
39577 /* 109108 */ // GIR_Coverage, 2755,
39578 /* 109108 */ GIR_EraseRootFromParent_Done,
39579 /* 109109 */ // Label 3318: @109109
39580 /* 109109 */ GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(109266),
39581 /* 109114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39582 /* 109118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3320*/ GIMT_Encode4(109172), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6334 //
39583 /* 109125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39584 /* 109129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39585 /* 109133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39586 /* 109137 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39587 /* 109142 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39588 /* 109146 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39589 /* 109148 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39590 /* 109148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
39591 /* 109151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39592 /* 109153 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39593 /* 109155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39594 /* 109159 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39595 /* 109161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39596 /* 109164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39597 /* 109170 */ GIR_RootConstrainSelectedInstOperands,
39598 /* 109171 */ // GIR_Coverage, 6334,
39599 /* 109171 */ GIR_EraseRootFromParent_Done,
39600 /* 109172 */ // Label 3320: @109172
39601 /* 109172 */ GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(109265),
39602 /* 109177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39603 /* 109181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3322*/ GIMT_Encode4(109231), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2789 //
39604 /* 109188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
39605 /* 109192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39606 /* 109196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39607 /* 109200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39608 /* 109205 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39609 /* 109207 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39610 /* 109207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
39611 /* 109210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39612 /* 109212 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
39613 /* 109216 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39614 /* 109218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39615 /* 109220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39616 /* 109223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39617 /* 109229 */ GIR_RootConstrainSelectedInstOperands,
39618 /* 109230 */ // GIR_Coverage, 2789,
39619 /* 109230 */ GIR_EraseRootFromParent_Done,
39620 /* 109231 */ // Label 3322: @109231
39621 /* 109231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3323*/ GIMT_Encode4(109264), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2737 //
39622 /* 109238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39623 /* 109242 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39624 /* 109242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
39625 /* 109245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39626 /* 109247 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39627 /* 109249 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39628 /* 109251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39629 /* 109253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39630 /* 109256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39631 /* 109262 */ GIR_RootConstrainSelectedInstOperands,
39632 /* 109263 */ // GIR_Coverage, 2737,
39633 /* 109263 */ GIR_EraseRootFromParent_Done,
39634 /* 109264 */ // Label 3323: @109264
39635 /* 109264 */ GIM_Reject,
39636 /* 109265 */ // Label 3321: @109265
39637 /* 109265 */ GIM_Reject,
39638 /* 109266 */ // Label 3319: @109266
39639 /* 109266 */ GIM_Reject,
39640 /* 109267 */ // Label 3315: @109267
39641 /* 109267 */ GIM_Reject,
39642 /* 109268 */ // Label 3308: @109268
39643 /* 109268 */ GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(109648),
39644 /* 109273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39645 /* 109276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39646 /* 109279 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
39647 /* 109282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39648 /* 109286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3325*/ GIMT_Encode4(109359), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2773 //
39649 /* 109293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39650 /* 109297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39651 /* 109301 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39652 /* 109305 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39653 /* 109310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39654 /* 109314 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39655 /* 109318 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39656 /* 109322 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
39657 /* 109326 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39658 /* 109331 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39659 /* 109333 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39660 /* 109333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
39661 /* 109336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39662 /* 109338 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39663 /* 109342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39664 /* 109346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39665 /* 109348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39666 /* 109351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39667 /* 109357 */ GIR_RootConstrainSelectedInstOperands,
39668 /* 109358 */ // GIR_Coverage, 2773,
39669 /* 109358 */ GIR_EraseRootFromParent_Done,
39670 /* 109359 */ // Label 3325: @109359
39671 /* 109359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3326*/ GIMT_Encode4(109432), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6338 //
39672 /* 109366 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39673 /* 109370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39674 /* 109374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39675 /* 109378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39676 /* 109382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39677 /* 109387 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39678 /* 109391 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39679 /* 109395 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
39680 /* 109399 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39681 /* 109404 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39682 /* 109406 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39683 /* 109406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
39684 /* 109409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39685 /* 109411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39686 /* 109415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39687 /* 109419 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39688 /* 109421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39689 /* 109424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39690 /* 109430 */ GIR_RootConstrainSelectedInstOperands,
39691 /* 109431 */ // GIR_Coverage, 6338,
39692 /* 109431 */ GIR_EraseRootFromParent_Done,
39693 /* 109432 */ // Label 3326: @109432
39694 /* 109432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3327*/ GIMT_Encode4(109490), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2753 //
39695 /* 109439 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39696 /* 109443 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39697 /* 109447 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39698 /* 109451 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39699 /* 109456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39700 /* 109460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39701 /* 109464 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39702 /* 109466 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39703 /* 109466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
39704 /* 109469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39705 /* 109471 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39706 /* 109473 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39707 /* 109477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39708 /* 109479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39709 /* 109482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39710 /* 109488 */ GIR_RootConstrainSelectedInstOperands,
39711 /* 109489 */ // GIR_Coverage, 2753,
39712 /* 109489 */ GIR_EraseRootFromParent_Done,
39713 /* 109490 */ // Label 3327: @109490
39714 /* 109490 */ GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(109647),
39715 /* 109495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39716 /* 109499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3329*/ GIMT_Encode4(109553), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6332 //
39717 /* 109506 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39718 /* 109510 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39719 /* 109514 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39720 /* 109518 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39721 /* 109523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39722 /* 109527 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39723 /* 109529 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39724 /* 109529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
39725 /* 109532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39726 /* 109534 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39727 /* 109536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39728 /* 109540 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39729 /* 109542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39730 /* 109545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39731 /* 109551 */ GIR_RootConstrainSelectedInstOperands,
39732 /* 109552 */ // GIR_Coverage, 6332,
39733 /* 109552 */ GIR_EraseRootFromParent_Done,
39734 /* 109553 */ // Label 3329: @109553
39735 /* 109553 */ GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(109646),
39736 /* 109558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39737 /* 109562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3331*/ GIMT_Encode4(109612), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2787 //
39738 /* 109569 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
39739 /* 109573 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39740 /* 109577 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39741 /* 109581 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39742 /* 109586 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39743 /* 109588 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39744 /* 109588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
39745 /* 109591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39746 /* 109593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
39747 /* 109597 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39748 /* 109599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39749 /* 109601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39750 /* 109604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39751 /* 109610 */ GIR_RootConstrainSelectedInstOperands,
39752 /* 109611 */ // GIR_Coverage, 2787,
39753 /* 109611 */ GIR_EraseRootFromParent_Done,
39754 /* 109612 */ // Label 3331: @109612
39755 /* 109612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3332*/ GIMT_Encode4(109645), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2735 //
39756 /* 109619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39757 /* 109623 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39758 /* 109623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
39759 /* 109626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39760 /* 109628 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39761 /* 109630 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39762 /* 109632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39763 /* 109634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39764 /* 109637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39765 /* 109643 */ GIR_RootConstrainSelectedInstOperands,
39766 /* 109644 */ // GIR_Coverage, 2735,
39767 /* 109644 */ GIR_EraseRootFromParent_Done,
39768 /* 109645 */ // Label 3332: @109645
39769 /* 109645 */ GIM_Reject,
39770 /* 109646 */ // Label 3330: @109646
39771 /* 109646 */ GIM_Reject,
39772 /* 109647 */ // Label 3328: @109647
39773 /* 109647 */ GIM_Reject,
39774 /* 109648 */ // Label 3324: @109648
39775 /* 109648 */ GIM_Reject,
39776 /* 109649 */ // Label 3309: @109649
39777 /* 109649 */ GIM_Try, /*On fail goto*//*Label 3333*/ GIMT_Encode4(110029),
39778 /* 109654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
39779 /* 109657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39780 /* 109660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
39781 /* 109663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39782 /* 109667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3334*/ GIMT_Encode4(109740), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2771 //
39783 /* 109674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39784 /* 109678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39785 /* 109682 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39786 /* 109686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39787 /* 109691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39788 /* 109695 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39789 /* 109699 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39790 /* 109703 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
39791 /* 109707 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39792 /* 109712 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39793 /* 109714 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39794 /* 109714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
39795 /* 109717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39796 /* 109719 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
39797 /* 109723 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39798 /* 109727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39799 /* 109729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39800 /* 109732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39801 /* 109738 */ GIR_RootConstrainSelectedInstOperands,
39802 /* 109739 */ // GIR_Coverage, 2771,
39803 /* 109739 */ GIR_EraseRootFromParent_Done,
39804 /* 109740 */ // Label 3334: @109740
39805 /* 109740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3335*/ GIMT_Encode4(109813), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6336 //
39806 /* 109747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39807 /* 109751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39808 /* 109755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39809 /* 109759 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39810 /* 109763 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39811 /* 109768 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39812 /* 109772 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39813 /* 109776 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
39814 /* 109780 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39815 /* 109785 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39816 /* 109787 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39817 /* 109787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
39818 /* 109790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39819 /* 109792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
39820 /* 109796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39821 /* 109800 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
39822 /* 109802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39823 /* 109805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39824 /* 109811 */ GIR_RootConstrainSelectedInstOperands,
39825 /* 109812 */ // GIR_Coverage, 6336,
39826 /* 109812 */ GIR_EraseRootFromParent_Done,
39827 /* 109813 */ // Label 3335: @109813
39828 /* 109813 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3336*/ GIMT_Encode4(109871), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2751 //
39829 /* 109820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39830 /* 109824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39831 /* 109828 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39832 /* 109832 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39833 /* 109837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39834 /* 109841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39835 /* 109845 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39836 /* 109847 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39837 /* 109847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
39838 /* 109850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39839 /* 109852 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
39840 /* 109854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39841 /* 109858 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39842 /* 109860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39843 /* 109863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39844 /* 109869 */ GIR_RootConstrainSelectedInstOperands,
39845 /* 109870 */ // GIR_Coverage, 2751,
39846 /* 109870 */ GIR_EraseRootFromParent_Done,
39847 /* 109871 */ // Label 3336: @109871
39848 /* 109871 */ GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(110028),
39849 /* 109876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39850 /* 109880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3338*/ GIMT_Encode4(109934), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6330 //
39851 /* 109887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39852 /* 109891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39853 /* 109895 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39854 /* 109899 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39855 /* 109904 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39856 /* 109908 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39857 /* 109910 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39858 /* 109910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
39859 /* 109913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39860 /* 109915 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
39861 /* 109917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39862 /* 109921 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
39863 /* 109923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39864 /* 109926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39865 /* 109932 */ GIR_RootConstrainSelectedInstOperands,
39866 /* 109933 */ // GIR_Coverage, 6330,
39867 /* 109933 */ GIR_EraseRootFromParent_Done,
39868 /* 109934 */ // Label 3338: @109934
39869 /* 109934 */ GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(110027),
39870 /* 109939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39871 /* 109943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3340*/ GIMT_Encode4(109993), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2785 //
39872 /* 109950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
39873 /* 109954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39874 /* 109958 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39875 /* 109962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39876 /* 109967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39877 /* 109969 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39878 /* 109969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
39879 /* 109972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39880 /* 109974 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
39881 /* 109978 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
39882 /* 109980 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39883 /* 109982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39884 /* 109985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39885 /* 109991 */ GIR_RootConstrainSelectedInstOperands,
39886 /* 109992 */ // GIR_Coverage, 2785,
39887 /* 109992 */ GIR_EraseRootFromParent_Done,
39888 /* 109993 */ // Label 3340: @109993
39889 /* 109993 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3341*/ GIMT_Encode4(110026), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2733 //
39890 /* 110000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39891 /* 110004 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39892 /* 110004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
39893 /* 110007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39894 /* 110009 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
39895 /* 110011 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
39896 /* 110013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39897 /* 110015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39898 /* 110018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39899 /* 110024 */ GIR_RootConstrainSelectedInstOperands,
39900 /* 110025 */ // GIR_Coverage, 2733,
39901 /* 110025 */ GIR_EraseRootFromParent_Done,
39902 /* 110026 */ // Label 3341: @110026
39903 /* 110026 */ GIM_Reject,
39904 /* 110027 */ // Label 3339: @110027
39905 /* 110027 */ GIM_Reject,
39906 /* 110028 */ // Label 3337: @110028
39907 /* 110028 */ GIM_Reject,
39908 /* 110029 */ // Label 3333: @110029
39909 /* 110029 */ GIM_Reject,
39910 /* 110030 */ // Label 3310: @110030
39911 /* 110030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3342*/ GIMT_Encode4(110084), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2886 //
39912 /* 110037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
39913 /* 110040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
39914 /* 110043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
39915 /* 110046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39916 /* 110050 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39917 /* 110054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39918 /* 110058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39919 /* 110062 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
39920 /* 110062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
39921 /* 110065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39922 /* 110067 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39923 /* 110069 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39924 /* 110071 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39925 /* 110073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39926 /* 110076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39927 /* 110082 */ GIR_RootConstrainSelectedInstOperands,
39928 /* 110083 */ // GIR_Coverage, 2886,
39929 /* 110083 */ GIR_EraseRootFromParent_Done,
39930 /* 110084 */ // Label 3342: @110084
39931 /* 110084 */ GIM_Reject,
39932 /* 110085 */ // Label 3311: @110085
39933 /* 110085 */ GIM_Try, /*On fail goto*//*Label 3343*/ GIMT_Encode4(110334),
39934 /* 110090 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39935 /* 110093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39936 /* 110096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
39937 /* 110099 */ GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(110237),
39938 /* 110104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39939 /* 110108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3345*/ GIMT_Encode4(110172), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4449 //
39940 /* 110115 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39941 /* 110119 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39942 /* 110123 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39943 /* 110127 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39944 /* 110132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39945 /* 110136 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39946 /* 110140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39947 /* 110142 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
39948 /* 110142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
39949 /* 110145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39950 /* 110147 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39951 /* 110149 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
39952 /* 110153 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
39953 /* 110155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39954 /* 110158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39955 /* 110164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39956 /* 110170 */ GIR_RootConstrainSelectedInstOperands,
39957 /* 110171 */ // GIR_Coverage, 4449,
39958 /* 110171 */ GIR_EraseRootFromParent_Done,
39959 /* 110172 */ // Label 3345: @110172
39960 /* 110172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3346*/ GIMT_Encode4(110236), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6676 //
39961 /* 110179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39962 /* 110183 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39963 /* 110187 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39964 /* 110191 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39965 /* 110195 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39966 /* 110200 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39967 /* 110204 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39968 /* 110206 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
39969 /* 110206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
39970 /* 110209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39971 /* 110211 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39972 /* 110213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
39973 /* 110217 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
39974 /* 110219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39975 /* 110222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39976 /* 110228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39977 /* 110234 */ GIR_RootConstrainSelectedInstOperands,
39978 /* 110235 */ // GIR_Coverage, 6676,
39979 /* 110235 */ GIR_EraseRootFromParent_Done,
39980 /* 110236 */ // Label 3346: @110236
39981 /* 110236 */ GIM_Reject,
39982 /* 110237 */ // Label 3344: @110237
39983 /* 110237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3347*/ GIMT_Encode4(110282), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2887 //
39984 /* 110244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39985 /* 110248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39986 /* 110252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39987 /* 110256 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39988 /* 110260 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39989 /* 110260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
39990 /* 110263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39991 /* 110265 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39992 /* 110267 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39993 /* 110269 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39994 /* 110271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39995 /* 110274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39996 /* 110280 */ GIR_RootConstrainSelectedInstOperands,
39997 /* 110281 */ // GIR_Coverage, 2887,
39998 /* 110281 */ GIR_EraseRootFromParent_Done,
39999 /* 110282 */ // Label 3347: @110282
40000 /* 110282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3348*/ GIMT_Encode4(110333), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4445 //
40001 /* 110289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40002 /* 110293 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40003 /* 110297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40004 /* 110301 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40005 /* 110305 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
40006 /* 110305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
40007 /* 110308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40008 /* 110310 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
40009 /* 110312 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
40010 /* 110314 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
40011 /* 110316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40012 /* 110319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40013 /* 110325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40014 /* 110331 */ GIR_RootConstrainSelectedInstOperands,
40015 /* 110332 */ // GIR_Coverage, 4445,
40016 /* 110332 */ GIR_EraseRootFromParent_Done,
40017 /* 110333 */ // Label 3348: @110333
40018 /* 110333 */ GIM_Reject,
40019 /* 110334 */ // Label 3343: @110334
40020 /* 110334 */ GIM_Reject,
40021 /* 110335 */ // Label 3312: @110335
40022 /* 110335 */ GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(110513),
40023 /* 110340 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40024 /* 110343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
40025 /* 110346 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
40026 /* 110349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40027 /* 110353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3350*/ GIMT_Encode4(110411), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2890 //
40028 /* 110360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40029 /* 110364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
40030 /* 110368 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
40031 /* 110372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40032 /* 110377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40033 /* 110381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40034 /* 110385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40035 /* 110387 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
40036 /* 110387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
40037 /* 110390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40038 /* 110392 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
40039 /* 110394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40040 /* 110398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40041 /* 110400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40042 /* 110403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40043 /* 110409 */ GIR_RootConstrainSelectedInstOperands,
40044 /* 110410 */ // GIR_Coverage, 2890,
40045 /* 110410 */ GIR_EraseRootFromParent_Done,
40046 /* 110411 */ // Label 3350: @110411
40047 /* 110411 */ GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(110512),
40048 /* 110416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40049 /* 110420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3352*/ GIMT_Encode4(110474), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6393 //
40050 /* 110427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40051 /* 110431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
40052 /* 110435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
40053 /* 110439 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40054 /* 110444 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40055 /* 110448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40056 /* 110450 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
40057 /* 110450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
40058 /* 110453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40059 /* 110455 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
40060 /* 110457 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40061 /* 110461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40062 /* 110463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40063 /* 110466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40064 /* 110472 */ GIR_RootConstrainSelectedInstOperands,
40065 /* 110473 */ // GIR_Coverage, 6393,
40066 /* 110473 */ GIR_EraseRootFromParent_Done,
40067 /* 110474 */ // Label 3352: @110474
40068 /* 110474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3353*/ GIMT_Encode4(110511), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2888 //
40069 /* 110481 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40070 /* 110485 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40071 /* 110489 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
40072 /* 110489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
40073 /* 110492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40074 /* 110494 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
40075 /* 110496 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40076 /* 110498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40077 /* 110500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40078 /* 110503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40079 /* 110509 */ GIR_RootConstrainSelectedInstOperands,
40080 /* 110510 */ // GIR_Coverage, 2888,
40081 /* 110510 */ GIR_EraseRootFromParent_Done,
40082 /* 110511 */ // Label 3353: @110511
40083 /* 110511 */ GIM_Reject,
40084 /* 110512 */ // Label 3351: @110512
40085 /* 110512 */ GIM_Reject,
40086 /* 110513 */ // Label 3349: @110513
40087 /* 110513 */ GIM_Reject,
40088 /* 110514 */ // Label 3313: @110514
40089 /* 110514 */ GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(110885),
40090 /* 110519 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40091 /* 110522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
40092 /* 110525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
40093 /* 110528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3355*/ GIMT_Encode4(110590), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2891 //
40094 /* 110535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40095 /* 110539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40096 /* 110543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
40097 /* 110547 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
40098 /* 110551 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40099 /* 110556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40100 /* 110560 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40101 /* 110564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40102 /* 110566 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
40103 /* 110566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
40104 /* 110569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40105 /* 110571 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
40106 /* 110573 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40107 /* 110577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40108 /* 110579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40109 /* 110582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40110 /* 110588 */ GIR_RootConstrainSelectedInstOperands,
40111 /* 110589 */ // GIR_Coverage, 2891,
40112 /* 110589 */ GIR_EraseRootFromParent_Done,
40113 /* 110590 */ // Label 3355: @110590
40114 /* 110590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3356*/ GIMT_Encode4(110658), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4435 //
40115 /* 110597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40116 /* 110601 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40117 /* 110605 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
40118 /* 110609 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
40119 /* 110613 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40120 /* 110618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40121 /* 110622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40122 /* 110626 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40123 /* 110628 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
40124 /* 110628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
40125 /* 110631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40126 /* 110633 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
40127 /* 110635 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
40128 /* 110639 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
40129 /* 110641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40130 /* 110644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40131 /* 110650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40132 /* 110656 */ GIR_RootConstrainSelectedInstOperands,
40133 /* 110657 */ // GIR_Coverage, 4435,
40134 /* 110657 */ GIR_EraseRootFromParent_Done,
40135 /* 110658 */ // Label 3356: @110658
40136 /* 110658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3357*/ GIMT_Encode4(110720), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6394 //
40137 /* 110665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40138 /* 110669 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40139 /* 110673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40140 /* 110677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
40141 /* 110681 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
40142 /* 110685 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40143 /* 110690 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40144 /* 110694 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40145 /* 110696 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
40146 /* 110696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
40147 /* 110699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40148 /* 110701 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
40149 /* 110703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40150 /* 110707 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40151 /* 110709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40152 /* 110712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40153 /* 110718 */ GIR_RootConstrainSelectedInstOperands,
40154 /* 110719 */ // GIR_Coverage, 6394,
40155 /* 110719 */ GIR_EraseRootFromParent_Done,
40156 /* 110720 */ // Label 3357: @110720
40157 /* 110720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3358*/ GIMT_Encode4(110788), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6674 //
40158 /* 110727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40159 /* 110731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40160 /* 110735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40161 /* 110739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
40162 /* 110743 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
40163 /* 110747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40164 /* 110752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40165 /* 110756 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40166 /* 110758 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
40167 /* 110758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
40168 /* 110761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40169 /* 110763 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
40170 /* 110765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
40171 /* 110769 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
40172 /* 110771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40173 /* 110774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40174 /* 110780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40175 /* 110786 */ GIR_RootConstrainSelectedInstOperands,
40176 /* 110787 */ // GIR_Coverage, 6674,
40177 /* 110787 */ GIR_EraseRootFromParent_Done,
40178 /* 110788 */ // Label 3358: @110788
40179 /* 110788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3359*/ GIMT_Encode4(110833), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2889 //
40180 /* 110795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40181 /* 110799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40182 /* 110803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40183 /* 110807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40184 /* 110811 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
40185 /* 110811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq),
40186 /* 110814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40187 /* 110816 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
40188 /* 110818 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40189 /* 110820 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40190 /* 110822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40191 /* 110825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40192 /* 110831 */ GIR_RootConstrainSelectedInstOperands,
40193 /* 110832 */ // GIR_Coverage, 2889,
40194 /* 110832 */ GIR_EraseRootFromParent_Done,
40195 /* 110833 */ // Label 3359: @110833
40196 /* 110833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3360*/ GIMT_Encode4(110884), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4441 //
40197 /* 110840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40198 /* 110844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40199 /* 110848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40200 /* 110852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40201 /* 110856 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
40202 /* 110856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
40203 /* 110859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40204 /* 110861 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
40205 /* 110863 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
40206 /* 110865 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
40207 /* 110867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40208 /* 110870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40209 /* 110876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40210 /* 110882 */ GIR_RootConstrainSelectedInstOperands,
40211 /* 110883 */ // GIR_Coverage, 4441,
40212 /* 110883 */ GIR_EraseRootFromParent_Done,
40213 /* 110884 */ // Label 3360: @110884
40214 /* 110884 */ GIM_Reject,
40215 /* 110885 */ // Label 3354: @110885
40216 /* 110885 */ GIM_Reject,
40217 /* 110886 */ // Label 3314: @110886
40218 /* 110886 */ GIM_Reject,
40219 /* 110887 */ // Label 45: @110887
40220 /* 110887 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3364*/ GIMT_Encode4(111048),
40221 /* 110898 */ /*GILLT_s16*//*Label 3361*/ GIMT_Encode4(110910),
40222 /* 110902 */ /*GILLT_s32*//*Label 3362*/ GIMT_Encode4(110956),
40223 /* 110906 */ /*GILLT_s64*//*Label 3363*/ GIMT_Encode4(111002),
40224 /* 110910 */ // Label 3361: @110910
40225 /* 110910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3365*/ GIMT_Encode4(110955), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 633 //
40226 /* 110917 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
40227 /* 110920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
40228 /* 110923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40229 /* 110927 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40230 /* 110931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40231 /* 110935 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40232 /* 110935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
40233 /* 110938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40234 /* 110940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
40235 /* 110942 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
40236 /* 110944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40237 /* 110947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40238 /* 110953 */ GIR_RootConstrainSelectedInstOperands,
40239 /* 110954 */ // GIR_Coverage, 633,
40240 /* 110954 */ GIR_EraseRootFromParent_Done,
40241 /* 110955 */ // Label 3365: @110955
40242 /* 110955 */ GIM_Reject,
40243 /* 110956 */ // Label 3362: @110956
40244 /* 110956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3366*/ GIMT_Encode4(111001), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 631 //
40245 /* 110963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
40246 /* 110966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
40247 /* 110969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40248 /* 110973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40249 /* 110977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40250 /* 110981 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40251 /* 110981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
40252 /* 110984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40253 /* 110986 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
40254 /* 110988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
40255 /* 110990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40256 /* 110993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40257 /* 110999 */ GIR_RootConstrainSelectedInstOperands,
40258 /* 111000 */ // GIR_Coverage, 631,
40259 /* 111000 */ GIR_EraseRootFromParent_Done,
40260 /* 111001 */ // Label 3366: @111001
40261 /* 111001 */ GIM_Reject,
40262 /* 111002 */ // Label 3363: @111002
40263 /* 111002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3367*/ GIMT_Encode4(111047), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 629 //
40264 /* 111009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40265 /* 111012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40266 /* 111015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40267 /* 111019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40268 /* 111023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40269 /* 111027 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40270 /* 111027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
40271 /* 111030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40272 /* 111032 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
40273 /* 111034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
40274 /* 111036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40275 /* 111039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40276 /* 111045 */ GIR_RootConstrainSelectedInstOperands,
40277 /* 111046 */ // GIR_Coverage, 629,
40278 /* 111046 */ GIR_EraseRootFromParent_Done,
40279 /* 111047 */ // Label 3367: @111047
40280 /* 111047 */ GIM_Reject,
40281 /* 111048 */ // Label 3364: @111048
40282 /* 111048 */ GIM_Reject,
40283 /* 111049 */ // Label 46: @111049
40284 /* 111049 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3375*/ GIMT_Encode4(113456),
40285 /* 111060 */ /*GILLT_s16*//*Label 3368*/ GIMT_Encode4(111112),
40286 /* 111064 */ /*GILLT_s32*//*Label 3369*/ GIMT_Encode4(111753),
40287 /* 111068 */ /*GILLT_s64*//*Label 3370*/ GIMT_Encode4(112547), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40288 /* 111096 */ /*GILLT_v4s16*//*Label 3371*/ GIMT_Encode4(113188),
40289 /* 111100 */ /*GILLT_v8s16*//*Label 3372*/ GIMT_Encode4(113225),
40290 /* 111104 */ /*GILLT_v2s32*//*Label 3373*/ GIMT_Encode4(113322),
40291 /* 111108 */ /*GILLT_v4s32*//*Label 3374*/ GIMT_Encode4(113359),
40292 /* 111112 */ // Label 3368: @111112
40293 /* 111112 */ GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(111752),
40294 /* 111117 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
40295 /* 111120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40296 /* 111124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3377*/ GIMT_Encode4(111208), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2795 //
40297 /* 111131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40298 /* 111135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40299 /* 111139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40300 /* 111143 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40301 /* 111147 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40302 /* 111151 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40303 /* 111155 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40304 /* 111159 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40305 /* 111163 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40306 /* 111168 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40307 /* 111173 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40308 /* 111178 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40309 /* 111180 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40310 /* 111180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40311 /* 111183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40312 /* 111185 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40313 /* 111189 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40314 /* 111193 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40315 /* 111197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40316 /* 111200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40317 /* 111206 */ GIR_RootConstrainSelectedInstOperands,
40318 /* 111207 */ // GIR_Coverage, 2795,
40319 /* 111207 */ GIR_EraseRootFromParent_Done,
40320 /* 111208 */ // Label 3377: @111208
40321 /* 111208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3378*/ GIMT_Encode4(111292), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6346 //
40322 /* 111215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40323 /* 111219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40324 /* 111223 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40325 /* 111227 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40326 /* 111231 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40327 /* 111235 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40328 /* 111240 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40329 /* 111244 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40330 /* 111248 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40331 /* 111252 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40332 /* 111257 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40333 /* 111262 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40334 /* 111264 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40335 /* 111264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40336 /* 111267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40337 /* 111269 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40338 /* 111273 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40339 /* 111277 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40340 /* 111281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40341 /* 111284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40342 /* 111290 */ GIR_RootConstrainSelectedInstOperands,
40343 /* 111291 */ // GIR_Coverage, 6346,
40344 /* 111291 */ GIR_EraseRootFromParent_Done,
40345 /* 111292 */ // Label 3378: @111292
40346 /* 111292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3379*/ GIMT_Encode4(111376), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2794 //
40347 /* 111299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40348 /* 111303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40349 /* 111307 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40350 /* 111311 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40351 /* 111315 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40352 /* 111319 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40353 /* 111323 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40354 /* 111327 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40355 /* 111331 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40356 /* 111336 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40357 /* 111341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40358 /* 111346 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40359 /* 111348 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40360 /* 111348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40361 /* 111351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40362 /* 111353 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40363 /* 111357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40364 /* 111361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40365 /* 111365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40366 /* 111368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40367 /* 111374 */ GIR_RootConstrainSelectedInstOperands,
40368 /* 111375 */ // GIR_Coverage, 2794,
40369 /* 111375 */ GIR_EraseRootFromParent_Done,
40370 /* 111376 */ // Label 3379: @111376
40371 /* 111376 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3380*/ GIMT_Encode4(111460), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6345 //
40372 /* 111383 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40373 /* 111387 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40374 /* 111391 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40375 /* 111395 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40376 /* 111399 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40377 /* 111403 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40378 /* 111408 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40379 /* 111412 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40380 /* 111416 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40381 /* 111420 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40382 /* 111425 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40383 /* 111430 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40384 /* 111432 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40385 /* 111432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40386 /* 111435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40387 /* 111437 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40388 /* 111441 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40389 /* 111445 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40390 /* 111449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40391 /* 111452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40392 /* 111458 */ GIR_RootConstrainSelectedInstOperands,
40393 /* 111459 */ // GIR_Coverage, 6345,
40394 /* 111459 */ GIR_EraseRootFromParent_Done,
40395 /* 111460 */ // Label 3380: @111460
40396 /* 111460 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3381*/ GIMT_Encode4(111532), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2769 //
40397 /* 111467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40398 /* 111471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40399 /* 111475 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40400 /* 111479 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40401 /* 111483 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40402 /* 111487 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40403 /* 111492 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40404 /* 111497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40405 /* 111502 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40406 /* 111504 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40407 /* 111504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
40408 /* 111507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40409 /* 111509 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40410 /* 111513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40411 /* 111517 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40412 /* 111521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40413 /* 111524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40414 /* 111530 */ GIR_RootConstrainSelectedInstOperands,
40415 /* 111531 */ // GIR_Coverage, 2769,
40416 /* 111531 */ GIR_EraseRootFromParent_Done,
40417 /* 111532 */ // Label 3381: @111532
40418 /* 111532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3382*/ GIMT_Encode4(111604), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2768 //
40419 /* 111539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40420 /* 111543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40421 /* 111547 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40422 /* 111551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40423 /* 111555 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40424 /* 111559 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40425 /* 111564 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40426 /* 111569 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40427 /* 111574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40428 /* 111576 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40429 /* 111576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
40430 /* 111579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40431 /* 111581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40432 /* 111585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40433 /* 111589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40434 /* 111593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40435 /* 111596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40436 /* 111602 */ GIR_RootConstrainSelectedInstOperands,
40437 /* 111603 */ // GIR_Coverage, 2768,
40438 /* 111603 */ GIR_EraseRootFromParent_Done,
40439 /* 111604 */ // Label 3382: @111604
40440 /* 111604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3383*/ GIMT_Encode4(111663), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 645 //
40441 /* 111611 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40442 /* 111615 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40443 /* 111619 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40444 /* 111623 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40445 /* 111627 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40446 /* 111632 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40447 /* 111637 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40448 /* 111639 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40449 /* 111639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
40450 /* 111642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40451 /* 111644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40452 /* 111648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40453 /* 111652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40454 /* 111655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40455 /* 111661 */ GIR_RootConstrainSelectedInstOperands,
40456 /* 111662 */ // GIR_Coverage, 645,
40457 /* 111662 */ GIR_EraseRootFromParent_Done,
40458 /* 111663 */ // Label 3383: @111663
40459 /* 111663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3384*/ GIMT_Encode4(111722), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 644 //
40460 /* 111670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40461 /* 111674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
40462 /* 111678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40463 /* 111682 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40464 /* 111686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40465 /* 111691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40466 /* 111696 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40467 /* 111698 */ // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40468 /* 111698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
40469 /* 111701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40470 /* 111703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40471 /* 111707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40472 /* 111711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40473 /* 111714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40474 /* 111720 */ GIR_RootConstrainSelectedInstOperands,
40475 /* 111721 */ // GIR_Coverage, 644,
40476 /* 111721 */ GIR_EraseRootFromParent_Done,
40477 /* 111722 */ // Label 3384: @111722
40478 /* 111722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3385*/ GIMT_Encode4(111751), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 691 //
40479 /* 111729 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40480 /* 111733 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
40481 /* 111733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH),
40482 /* 111736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40483 /* 111738 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
40484 /* 111740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40485 /* 111743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40486 /* 111749 */ GIR_RootConstrainSelectedInstOperands,
40487 /* 111750 */ // GIR_Coverage, 691,
40488 /* 111750 */ GIR_EraseRootFromParent_Done,
40489 /* 111751 */ // Label 3385: @111751
40490 /* 111751 */ GIM_Reject,
40491 /* 111752 */ // Label 3376: @111752
40492 /* 111752 */ GIM_Reject,
40493 /* 111753 */ // Label 3369: @111753
40494 /* 111753 */ GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(112546),
40495 /* 111758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
40496 /* 111761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40497 /* 111765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3387*/ GIMT_Encode4(111849), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2793 //
40498 /* 111772 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40499 /* 111776 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40500 /* 111780 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40501 /* 111784 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40502 /* 111788 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40503 /* 111792 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40504 /* 111796 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40505 /* 111800 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40506 /* 111804 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40507 /* 111809 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40508 /* 111814 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40509 /* 111819 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40510 /* 111821 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40511 /* 111821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40512 /* 111824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40513 /* 111826 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40514 /* 111830 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40515 /* 111834 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40516 /* 111838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40517 /* 111841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40518 /* 111847 */ GIR_RootConstrainSelectedInstOperands,
40519 /* 111848 */ // GIR_Coverage, 2793,
40520 /* 111848 */ GIR_EraseRootFromParent_Done,
40521 /* 111849 */ // Label 3387: @111849
40522 /* 111849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3388*/ GIMT_Encode4(111933), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6344 //
40523 /* 111856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40524 /* 111860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40525 /* 111864 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40526 /* 111868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40527 /* 111872 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40528 /* 111876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40529 /* 111881 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40530 /* 111885 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40531 /* 111889 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40532 /* 111893 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40533 /* 111898 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40534 /* 111903 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40535 /* 111905 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40536 /* 111905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40537 /* 111908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40538 /* 111910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40539 /* 111914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40540 /* 111918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40541 /* 111922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40542 /* 111925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40543 /* 111931 */ GIR_RootConstrainSelectedInstOperands,
40544 /* 111932 */ // GIR_Coverage, 6344,
40545 /* 111932 */ GIR_EraseRootFromParent_Done,
40546 /* 111933 */ // Label 3388: @111933
40547 /* 111933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3389*/ GIMT_Encode4(112017), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2792 //
40548 /* 111940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40549 /* 111944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40550 /* 111948 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40551 /* 111952 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40552 /* 111956 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40553 /* 111960 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40554 /* 111964 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40555 /* 111968 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40556 /* 111972 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40557 /* 111977 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40558 /* 111982 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40559 /* 111987 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40560 /* 111989 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40561 /* 111989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40562 /* 111992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40563 /* 111994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40564 /* 111998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40565 /* 112002 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40566 /* 112006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40567 /* 112009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40568 /* 112015 */ GIR_RootConstrainSelectedInstOperands,
40569 /* 112016 */ // GIR_Coverage, 2792,
40570 /* 112016 */ GIR_EraseRootFromParent_Done,
40571 /* 112017 */ // Label 3389: @112017
40572 /* 112017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3390*/ GIMT_Encode4(112101), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6343 //
40573 /* 112024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40574 /* 112028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40575 /* 112032 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40576 /* 112036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40577 /* 112040 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40578 /* 112044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40579 /* 112049 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40580 /* 112053 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40581 /* 112057 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40582 /* 112061 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40583 /* 112066 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40584 /* 112071 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40585 /* 112073 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40586 /* 112073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40587 /* 112076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40588 /* 112078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40589 /* 112082 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40590 /* 112086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40591 /* 112090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40592 /* 112093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40593 /* 112099 */ GIR_RootConstrainSelectedInstOperands,
40594 /* 112100 */ // GIR_Coverage, 6343,
40595 /* 112100 */ GIR_EraseRootFromParent_Done,
40596 /* 112101 */ // Label 3390: @112101
40597 /* 112101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3391*/ GIMT_Encode4(112173), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2767 //
40598 /* 112108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40599 /* 112112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40600 /* 112116 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40601 /* 112120 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40602 /* 112124 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40603 /* 112128 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40604 /* 112133 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40605 /* 112138 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40606 /* 112143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40607 /* 112145 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40608 /* 112145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
40609 /* 112148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40610 /* 112150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40611 /* 112154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40612 /* 112158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40613 /* 112162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40614 /* 112165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40615 /* 112171 */ GIR_RootConstrainSelectedInstOperands,
40616 /* 112172 */ // GIR_Coverage, 2767,
40617 /* 112172 */ GIR_EraseRootFromParent_Done,
40618 /* 112173 */ // Label 3391: @112173
40619 /* 112173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3392*/ GIMT_Encode4(112245), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2766 //
40620 /* 112180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40621 /* 112184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40622 /* 112188 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40623 /* 112192 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40624 /* 112196 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40625 /* 112200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40626 /* 112205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40627 /* 112210 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40628 /* 112215 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40629 /* 112217 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40630 /* 112217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
40631 /* 112220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40632 /* 112222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40633 /* 112226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40634 /* 112230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40635 /* 112234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40636 /* 112237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40637 /* 112243 */ GIR_RootConstrainSelectedInstOperands,
40638 /* 112244 */ // GIR_Coverage, 2766,
40639 /* 112244 */ GIR_EraseRootFromParent_Done,
40640 /* 112245 */ // Label 3392: @112245
40641 /* 112245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3393*/ GIMT_Encode4(112304), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 643 //
40642 /* 112252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40643 /* 112256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40644 /* 112260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40645 /* 112264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40646 /* 112268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40647 /* 112273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40648 /* 112278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40649 /* 112280 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40650 /* 112280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
40651 /* 112283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40652 /* 112285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40653 /* 112289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40654 /* 112293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40655 /* 112296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40656 /* 112302 */ GIR_RootConstrainSelectedInstOperands,
40657 /* 112303 */ // GIR_Coverage, 643,
40658 /* 112303 */ GIR_EraseRootFromParent_Done,
40659 /* 112304 */ // Label 3393: @112304
40660 /* 112304 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3394*/ GIMT_Encode4(112363), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 642 //
40661 /* 112311 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40662 /* 112315 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
40663 /* 112319 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40664 /* 112323 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40665 /* 112327 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40666 /* 112332 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40667 /* 112337 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40668 /* 112339 */ // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40669 /* 112339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
40670 /* 112342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40671 /* 112344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40672 /* 112348 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40673 /* 112352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40674 /* 112355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40675 /* 112361 */ GIR_RootConstrainSelectedInstOperands,
40676 /* 112362 */ // GIR_Coverage, 642,
40677 /* 112362 */ GIR_EraseRootFromParent_Done,
40678 /* 112363 */ // Label 3394: @112363
40679 /* 112363 */ GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(112545),
40680 /* 112368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40681 /* 112372 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3396*/ GIMT_Encode4(112397), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 690 //
40682 /* 112379 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
40683 /* 112379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS),
40684 /* 112382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40685 /* 112384 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
40686 /* 112386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40687 /* 112389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40688 /* 112395 */ GIR_RootConstrainSelectedInstOperands,
40689 /* 112396 */ // GIR_Coverage, 690,
40690 /* 112396 */ GIR_EraseRootFromParent_Done,
40691 /* 112397 */ // Label 3396: @112397
40692 /* 112397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3397*/ GIMT_Encode4(112544), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3094 //
40693 /* 112404 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40694 /* 112404 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40695 /* 112407 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40696 /* 112411 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40697 /* 112416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40698 /* 112418 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40699 /* 112421 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40700 /* 112425 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40701 /* 112430 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40702 /* 112433 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40703 /* 112438 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40704 /* 112441 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40705 /* 112445 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40706 /* 112450 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40707 /* 112453 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
40708 /* 112457 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40709 /* 112460 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40710 /* 112465 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40711 /* 112470 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40712 /* 112475 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40713 /* 112478 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
40714 /* 112482 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40715 /* 112487 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40716 /* 112490 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40717 /* 112493 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40718 /* 112499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40719 /* 112501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40720 /* 112504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40721 /* 112508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40722 /* 112513 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40723 /* 112516 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40724 /* 112521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40725 /* 112524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40726 /* 112526 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40727 /* 112533 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40728 /* 112538 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40729 /* 112543 */ // GIR_Coverage, 3094,
40730 /* 112543 */ GIR_EraseRootFromParent_Done,
40731 /* 112544 */ // Label 3397: @112544
40732 /* 112544 */ GIM_Reject,
40733 /* 112545 */ // Label 3395: @112545
40734 /* 112545 */ GIM_Reject,
40735 /* 112546 */ // Label 3386: @112546
40736 /* 112546 */ GIM_Reject,
40737 /* 112547 */ // Label 3370: @112547
40738 /* 112547 */ GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(113187),
40739 /* 112552 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40740 /* 112555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40741 /* 112559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3399*/ GIMT_Encode4(112643), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2791 //
40742 /* 112566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40743 /* 112570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40744 /* 112574 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40745 /* 112578 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40746 /* 112582 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40747 /* 112586 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40748 /* 112590 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40749 /* 112594 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40750 /* 112598 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40751 /* 112603 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40752 /* 112608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40753 /* 112613 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40754 /* 112615 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40755 /* 112615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40756 /* 112618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40757 /* 112620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40758 /* 112624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40759 /* 112628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40760 /* 112632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40761 /* 112635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40762 /* 112641 */ GIR_RootConstrainSelectedInstOperands,
40763 /* 112642 */ // GIR_Coverage, 2791,
40764 /* 112642 */ GIR_EraseRootFromParent_Done,
40765 /* 112643 */ // Label 3399: @112643
40766 /* 112643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3400*/ GIMT_Encode4(112727), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6342 //
40767 /* 112650 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40768 /* 112654 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40769 /* 112658 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40770 /* 112662 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40771 /* 112666 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40772 /* 112670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40773 /* 112675 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40774 /* 112679 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40775 /* 112683 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40776 /* 112687 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40777 /* 112692 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40778 /* 112697 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40779 /* 112699 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40780 /* 112699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40781 /* 112702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40782 /* 112704 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40783 /* 112708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40784 /* 112712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
40785 /* 112716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40786 /* 112719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40787 /* 112725 */ GIR_RootConstrainSelectedInstOperands,
40788 /* 112726 */ // GIR_Coverage, 6342,
40789 /* 112726 */ GIR_EraseRootFromParent_Done,
40790 /* 112727 */ // Label 3400: @112727
40791 /* 112727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3401*/ GIMT_Encode4(112811), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2790 //
40792 /* 112734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40793 /* 112738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40794 /* 112742 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40795 /* 112746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40796 /* 112750 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40797 /* 112754 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40798 /* 112758 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40799 /* 112762 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40800 /* 112766 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40801 /* 112771 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40802 /* 112776 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40803 /* 112781 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40804 /* 112783 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40805 /* 112783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40806 /* 112786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40807 /* 112788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40808 /* 112792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40809 /* 112796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40810 /* 112800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40811 /* 112803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40812 /* 112809 */ GIR_RootConstrainSelectedInstOperands,
40813 /* 112810 */ // GIR_Coverage, 2790,
40814 /* 112810 */ GIR_EraseRootFromParent_Done,
40815 /* 112811 */ // Label 3401: @112811
40816 /* 112811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3402*/ GIMT_Encode4(112895), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6341 //
40817 /* 112818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40818 /* 112822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40819 /* 112826 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40820 /* 112830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40821 /* 112834 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40822 /* 112838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40823 /* 112843 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40824 /* 112847 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40825 /* 112851 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40826 /* 112855 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40827 /* 112860 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40828 /* 112865 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40829 /* 112867 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40830 /* 112867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40831 /* 112870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40832 /* 112872 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40833 /* 112876 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40834 /* 112880 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
40835 /* 112884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40836 /* 112887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40837 /* 112893 */ GIR_RootConstrainSelectedInstOperands,
40838 /* 112894 */ // GIR_Coverage, 6341,
40839 /* 112894 */ GIR_EraseRootFromParent_Done,
40840 /* 112895 */ // Label 3402: @112895
40841 /* 112895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3403*/ GIMT_Encode4(112967), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2765 //
40842 /* 112902 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40843 /* 112906 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40844 /* 112910 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40845 /* 112914 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40846 /* 112918 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40847 /* 112922 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40848 /* 112927 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40849 /* 112932 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40850 /* 112937 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40851 /* 112939 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40852 /* 112939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
40853 /* 112942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40854 /* 112944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40855 /* 112948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40856 /* 112952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40857 /* 112956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40858 /* 112959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40859 /* 112965 */ GIR_RootConstrainSelectedInstOperands,
40860 /* 112966 */ // GIR_Coverage, 2765,
40861 /* 112966 */ GIR_EraseRootFromParent_Done,
40862 /* 112967 */ // Label 3403: @112967
40863 /* 112967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3404*/ GIMT_Encode4(113039), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2764 //
40864 /* 112974 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40865 /* 112978 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40866 /* 112982 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40867 /* 112986 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40868 /* 112990 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40869 /* 112994 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40870 /* 112999 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40871 /* 113004 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40872 /* 113009 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40873 /* 113011 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40874 /* 113011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
40875 /* 113014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40876 /* 113016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40877 /* 113020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40878 /* 113024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40879 /* 113028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40880 /* 113031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40881 /* 113037 */ GIR_RootConstrainSelectedInstOperands,
40882 /* 113038 */ // GIR_Coverage, 2764,
40883 /* 113038 */ GIR_EraseRootFromParent_Done,
40884 /* 113039 */ // Label 3404: @113039
40885 /* 113039 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3405*/ GIMT_Encode4(113098), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 641 //
40886 /* 113046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40887 /* 113050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40888 /* 113054 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40889 /* 113058 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40890 /* 113062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40891 /* 113067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40892 /* 113072 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40893 /* 113074 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40894 /* 113074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
40895 /* 113077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40896 /* 113079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40897 /* 113083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40898 /* 113087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40899 /* 113090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40900 /* 113096 */ GIR_RootConstrainSelectedInstOperands,
40901 /* 113097 */ // GIR_Coverage, 641,
40902 /* 113097 */ GIR_EraseRootFromParent_Done,
40903 /* 113098 */ // Label 3405: @113098
40904 /* 113098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3406*/ GIMT_Encode4(113157), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 640 //
40905 /* 113105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40906 /* 113109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
40907 /* 113113 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40908 /* 113117 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40909 /* 113121 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40910 /* 113126 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40911 /* 113131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40912 /* 113133 */ // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40913 /* 113133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
40914 /* 113136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40915 /* 113138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40916 /* 113142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40917 /* 113146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40918 /* 113149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40919 /* 113155 */ GIR_RootConstrainSelectedInstOperands,
40920 /* 113156 */ // GIR_Coverage, 640,
40921 /* 113156 */ GIR_EraseRootFromParent_Done,
40922 /* 113157 */ // Label 3406: @113157
40923 /* 113157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3407*/ GIMT_Encode4(113186), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 689 //
40924 /* 113164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40925 /* 113168 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
40926 /* 113168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD),
40927 /* 113171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40928 /* 113173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
40929 /* 113175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40930 /* 113178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40931 /* 113184 */ GIR_RootConstrainSelectedInstOperands,
40932 /* 113185 */ // GIR_Coverage, 689,
40933 /* 113185 */ GIR_EraseRootFromParent_Done,
40934 /* 113186 */ // Label 3407: @113186
40935 /* 113186 */ GIM_Reject,
40936 /* 113187 */ // Label 3398: @113187
40937 /* 113187 */ GIM_Reject,
40938 /* 113188 */ // Label 3371: @113188
40939 /* 113188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3408*/ GIMT_Encode4(113224), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1694 //
40940 /* 113195 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40941 /* 113198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40942 /* 113202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40943 /* 113206 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
40944 /* 113206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd),
40945 /* 113209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40946 /* 113211 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40947 /* 113213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40948 /* 113216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40949 /* 113222 */ GIR_RootConstrainSelectedInstOperands,
40950 /* 113223 */ // GIR_Coverage, 1694,
40951 /* 113223 */ GIR_EraseRootFromParent_Done,
40952 /* 113224 */ // Label 3408: @113224
40953 /* 113224 */ GIM_Reject,
40954 /* 113225 */ // Label 3372: @113225
40955 /* 113225 */ GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(113321),
40956 /* 113230 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
40957 /* 113233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3410*/ GIMT_Encode4(113266), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1695 //
40958 /* 113240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40959 /* 113244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40960 /* 113248 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
40961 /* 113248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq),
40962 /* 113251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40963 /* 113253 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40964 /* 113255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40965 /* 113258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40966 /* 113264 */ GIR_RootConstrainSelectedInstOperands,
40967 /* 113265 */ // GIR_Coverage, 1695,
40968 /* 113265 */ GIR_EraseRootFromParent_Done,
40969 /* 113266 */ // Label 3410: @113266
40970 /* 113266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3411*/ GIMT_Encode4(113320), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4573 //
40971 /* 113273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40972 /* 113277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40973 /* 113281 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
40974 /* 113281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40975 /* 113284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40976 /* 113288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40977 /* 113293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16),
40978 /* 113296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40979 /* 113298 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
40980 /* 113300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40981 /* 113303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40982 /* 113309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40983 /* 113315 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40984 /* 113318 */ GIR_RootConstrainSelectedInstOperands,
40985 /* 113319 */ // GIR_Coverage, 4573,
40986 /* 113319 */ GIR_EraseRootFromParent_Done,
40987 /* 113320 */ // Label 3411: @113320
40988 /* 113320 */ GIM_Reject,
40989 /* 113321 */ // Label 3409: @113321
40990 /* 113321 */ GIM_Reject,
40991 /* 113322 */ // Label 3373: @113322
40992 /* 113322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3412*/ GIMT_Encode4(113358), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1692 //
40993 /* 113329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40994 /* 113332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40995 /* 113336 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40996 /* 113340 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
40997 /* 113340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
40998 /* 113343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40999 /* 113345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41000 /* 113347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41001 /* 113350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41002 /* 113356 */ GIR_RootConstrainSelectedInstOperands,
41003 /* 113357 */ // GIR_Coverage, 1692,
41004 /* 113357 */ GIR_EraseRootFromParent_Done,
41005 /* 113358 */ // Label 3412: @113358
41006 /* 113358 */ GIM_Reject,
41007 /* 113359 */ // Label 3374: @113359
41008 /* 113359 */ GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(113455),
41009 /* 113364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41010 /* 113367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3414*/ GIMT_Encode4(113400), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1693 //
41011 /* 113374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41012 /* 113378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41013 /* 113382 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
41014 /* 113382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q),
41015 /* 113385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41016 /* 113387 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41017 /* 113389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41018 /* 113392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41019 /* 113398 */ GIR_RootConstrainSelectedInstOperands,
41020 /* 113399 */ // GIR_Coverage, 1693,
41021 /* 113399 */ GIR_EraseRootFromParent_Done,
41022 /* 113400 */ // Label 3414: @113400
41023 /* 113400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3415*/ GIMT_Encode4(113454), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4575 //
41024 /* 113407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41025 /* 113411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41026 /* 113415 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
41027 /* 113415 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41028 /* 113418 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41029 /* 113422 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41030 /* 113427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32),
41031 /* 113430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41032 /* 113432 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
41033 /* 113434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41034 /* 113437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41035 /* 113443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41036 /* 113449 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41037 /* 113452 */ GIR_RootConstrainSelectedInstOperands,
41038 /* 113453 */ // GIR_Coverage, 4575,
41039 /* 113453 */ GIR_EraseRootFromParent_Done,
41040 /* 113454 */ // Label 3415: @113454
41041 /* 113454 */ GIM_Reject,
41042 /* 113455 */ // Label 3413: @113455
41043 /* 113455 */ GIM_Reject,
41044 /* 113456 */ // Label 3375: @113456
41045 /* 113456 */ GIM_Reject,
41046 /* 113457 */ // Label 47: @113457
41047 /* 113457 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3419*/ GIMT_Encode4(113720),
41048 /* 113468 */ /*GILLT_s32*//*Label 3416*/ GIMT_Encode4(113516),
41049 /* 113472 */ /*GILLT_s64*//*Label 3417*/ GIMT_Encode4(113575), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41050 /* 113512 */ /*GILLT_v4s32*//*Label 3418*/ GIMT_Encode4(113685),
41051 /* 113516 */ // Label 3416: @113516
41052 /* 113516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3420*/ GIMT_Encode4(113574), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2504 //
41053 /* 113523 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
41054 /* 113526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41055 /* 113530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41056 /* 113534 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
41057 /* 113534 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41058 /* 113537 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41059 /* 113541 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41060 /* 113546 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41061 /* 113550 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41062 /* 113555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS),
41063 /* 113558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41064 /* 113560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41065 /* 113563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41066 /* 113566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41067 /* 113572 */ GIR_RootConstrainSelectedInstOperands,
41068 /* 113573 */ // GIR_Coverage, 2504,
41069 /* 113573 */ GIR_EraseRootFromParent_Done,
41070 /* 113574 */ // Label 3420: @113574
41071 /* 113574 */ GIM_Reject,
41072 /* 113575 */ // Label 3417: @113575
41073 /* 113575 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 3423*/ GIMT_Encode4(113684),
41074 /* 113586 */ /*GILLT_s16*//*Label 3421*/ GIMT_Encode4(113594),
41075 /* 113590 */ /*GILLT_s32*//*Label 3422*/ GIMT_Encode4(113650),
41076 /* 113594 */ // Label 3421: @113594
41077 /* 113594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3424*/ GIMT_Encode4(113649), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2524 //
41078 /* 113601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41079 /* 113605 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41080 /* 113609 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
41081 /* 113609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41082 /* 113612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41083 /* 113616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41084 /* 113621 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41085 /* 113625 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41086 /* 113630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD),
41087 /* 113633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
41088 /* 113635 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41089 /* 113638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41090 /* 113641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41091 /* 113647 */ GIR_RootConstrainSelectedInstOperands,
41092 /* 113648 */ // GIR_Coverage, 2524,
41093 /* 113648 */ GIR_EraseRootFromParent_Done,
41094 /* 113649 */ // Label 3424: @113649
41095 /* 113649 */ GIM_Reject,
41096 /* 113650 */ // Label 3422: @113650
41097 /* 113650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3425*/ GIMT_Encode4(113683), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 686 //
41098 /* 113657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41099 /* 113661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41100 /* 113665 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
41101 /* 113665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS),
41102 /* 113668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
41103 /* 113670 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
41104 /* 113672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41105 /* 113675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41106 /* 113681 */ GIR_RootConstrainSelectedInstOperands,
41107 /* 113682 */ // GIR_Coverage, 686,
41108 /* 113682 */ GIR_EraseRootFromParent_Done,
41109 /* 113683 */ // Label 3425: @113683
41110 /* 113683 */ GIM_Reject,
41111 /* 113684 */ // Label 3423: @113684
41112 /* 113684 */ GIM_Reject,
41113 /* 113685 */ // Label 3418: @113685
41114 /* 113685 */ GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(113719), // Rule ID 3059 //
41115 /* 113690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41116 /* 113693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41117 /* 113697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41118 /* 113701 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)
41119 /* 113701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
41120 /* 113704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41121 /* 113706 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41122 /* 113708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41123 /* 113711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41124 /* 113717 */ GIR_RootConstrainSelectedInstOperands,
41125 /* 113718 */ // GIR_Coverage, 3059,
41126 /* 113718 */ GIR_EraseRootFromParent_Done,
41127 /* 113719 */ // Label 3426: @113719
41128 /* 113719 */ GIM_Reject,
41129 /* 113720 */ // Label 3419: @113720
41130 /* 113720 */ GIM_Reject,
41131 /* 113721 */ // Label 48: @113721
41132 /* 113721 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(10), /*)*//*default:*//*Label 3430*/ GIMT_Encode4(114012),
41133 /* 113732 */ /*GILLT_s16*//*Label 3427*/ GIMT_Encode4(113772),
41134 /* 113736 */ /*GILLT_s32*//*Label 3428*/ GIMT_Encode4(113940), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41135 /* 113768 */ /*GILLT_v4s16*//*Label 3429*/ GIMT_Encode4(113977),
41136 /* 113772 */ // Label 3427: @113772
41137 /* 113772 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 3433*/ GIMT_Encode4(113939),
41138 /* 113783 */ /*GILLT_s32*//*Label 3431*/ GIMT_Encode4(113791),
41139 /* 113787 */ /*GILLT_s64*//*Label 3432*/ GIMT_Encode4(113865),
41140 /* 113791 */ // Label 3431: @113791
41141 /* 113791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3434*/ GIMT_Encode4(113864), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2508 //
41142 /* 113798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41143 /* 113802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41144 /* 113806 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
41145 /* 113806 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41146 /* 113809 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41147 /* 113813 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41148 /* 113818 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41149 /* 113820 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41150 /* 113823 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH),
41151 /* 113827 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41152 /* 113832 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41153 /* 113835 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41154 /* 113839 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41155 /* 113842 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41156 /* 113848 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41157 /* 113850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41158 /* 113853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41159 /* 113855 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41160 /* 113858 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
41161 /* 113863 */ // GIR_Coverage, 2508,
41162 /* 113863 */ GIR_EraseRootFromParent_Done,
41163 /* 113864 */ // Label 3434: @113864
41164 /* 113864 */ GIM_Reject,
41165 /* 113865 */ // Label 3432: @113865
41166 /* 113865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3435*/ GIMT_Encode4(113938), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2528 //
41167 /* 113872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41168 /* 113876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41169 /* 113880 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
41170 /* 113880 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41171 /* 113883 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41172 /* 113887 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41173 /* 113892 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41174 /* 113894 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41175 /* 113897 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH),
41176 /* 113901 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41177 /* 113906 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41178 /* 113909 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
41179 /* 113913 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41180 /* 113916 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41181 /* 113922 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41182 /* 113924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41183 /* 113927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41184 /* 113929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41185 /* 113932 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
41186 /* 113937 */ // GIR_Coverage, 2528,
41187 /* 113937 */ GIR_EraseRootFromParent_Done,
41188 /* 113938 */ // Label 3435: @113938
41189 /* 113938 */ GIM_Reject,
41190 /* 113939 */ // Label 3433: @113939
41191 /* 113939 */ GIM_Reject,
41192 /* 113940 */ // Label 3428: @113940
41193 /* 113940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3436*/ GIMT_Encode4(113976), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 688 //
41194 /* 113947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
41195 /* 113950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41196 /* 113954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41197 /* 113958 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
41198 /* 113958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD),
41199 /* 113961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41200 /* 113963 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
41201 /* 113965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41202 /* 113968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41203 /* 113974 */ GIR_RootConstrainSelectedInstOperands,
41204 /* 113975 */ // GIR_Coverage, 688,
41205 /* 113975 */ GIR_EraseRootFromParent_Done,
41206 /* 113976 */ // Label 3436: @113976
41207 /* 113976 */ GIM_Reject,
41208 /* 113977 */ // Label 3429: @113977
41209 /* 113977 */ GIM_Try, /*On fail goto*//*Label 3437*/ GIMT_Encode4(114011), // Rule ID 3058 //
41210 /* 113982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41211 /* 113985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41212 /* 113989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41213 /* 113993 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)
41214 /* 113993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
41215 /* 113996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41216 /* 113998 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41217 /* 114000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41218 /* 114003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41219 /* 114009 */ GIR_RootConstrainSelectedInstOperands,
41220 /* 114010 */ // GIR_Coverage, 3058,
41221 /* 114010 */ GIR_EraseRootFromParent_Done,
41222 /* 114011 */ // Label 3437: @114011
41223 /* 114011 */ GIM_Reject,
41224 /* 114012 */ // Label 3430: @114012
41225 /* 114012 */ GIM_Reject,
41226 /* 114013 */ // Label 49: @114013
41227 /* 114013 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3445*/ GIMT_Encode4(115294),
41228 /* 114024 */ /*GILLT_s32*//*Label 3438*/ GIMT_Encode4(114072), GIMT_Encode4(0), GIMT_Encode4(0),
41229 /* 114036 */ /*GILLT_v4s1*//*Label 3439*/ GIMT_Encode4(114922),
41230 /* 114040 */ /*GILLT_v8s1*//*Label 3440*/ GIMT_Encode4(114974), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41231 /* 114056 */ /*GILLT_v4s16*//*Label 3441*/ GIMT_Encode4(115026),
41232 /* 114060 */ /*GILLT_v8s16*//*Label 3442*/ GIMT_Encode4(115063),
41233 /* 114064 */ /*GILLT_v2s32*//*Label 3443*/ GIMT_Encode4(115160),
41234 /* 114068 */ /*GILLT_v4s32*//*Label 3444*/ GIMT_Encode4(115197),
41235 /* 114072 */ // Label 3438: @114072
41236 /* 114072 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3449*/ GIMT_Encode4(114921),
41237 /* 114083 */ /*GILLT_s16*//*Label 3446*/ GIMT_Encode4(114095),
41238 /* 114087 */ /*GILLT_s32*//*Label 3447*/ GIMT_Encode4(114332),
41239 /* 114091 */ /*GILLT_s64*//*Label 3448*/ GIMT_Encode4(114684),
41240 /* 114095 */ // Label 3446: @114095
41241 /* 114095 */ GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(114331),
41242 /* 114100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41243 /* 114104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3451*/ GIMT_Encode4(114162), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2558 //
41244 /* 114111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41245 /* 114115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41246 /* 114119 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41247 /* 114123 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41248 /* 114128 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41249 /* 114130 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41250 /* 114130 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41251 /* 114133 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH),
41252 /* 114137 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41253 /* 114142 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41254 /* 114146 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41255 /* 114148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41256 /* 114151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41257 /* 114153 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41258 /* 114156 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41259 /* 114161 */ // GIR_Coverage, 2558,
41260 /* 114161 */ GIR_EraseRootFromParent_Done,
41261 /* 114162 */ // Label 3451: @114162
41262 /* 114162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3452*/ GIMT_Encode4(114220), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2582 //
41263 /* 114169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41264 /* 114173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41265 /* 114177 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41266 /* 114181 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41267 /* 114186 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41268 /* 114188 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41269 /* 114188 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41270 /* 114191 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH),
41271 /* 114195 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41272 /* 114200 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41273 /* 114204 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41274 /* 114206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41275 /* 114209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41276 /* 114211 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41277 /* 114214 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41278 /* 114219 */ // GIR_Coverage, 2582,
41279 /* 114219 */ GIR_EraseRootFromParent_Done,
41280 /* 114220 */ // Label 3452: @114220
41281 /* 114220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3453*/ GIMT_Encode4(114278), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2534 //
41282 /* 114227 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41283 /* 114231 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41284 /* 114235 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41285 /* 114239 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41286 /* 114244 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41287 /* 114246 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41288 /* 114246 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41289 /* 114249 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH),
41290 /* 114253 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41291 /* 114258 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41292 /* 114262 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41293 /* 114264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41294 /* 114267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41295 /* 114269 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41296 /* 114272 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41297 /* 114277 */ // GIR_Coverage, 2534,
41298 /* 114277 */ GIR_EraseRootFromParent_Done,
41299 /* 114278 */ // Label 3453: @114278
41300 /* 114278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3454*/ GIMT_Encode4(114330), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2643 //
41301 /* 114285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41302 /* 114289 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41303 /* 114289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41304 /* 114292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH),
41305 /* 114296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41306 /* 114301 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41307 /* 114305 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41308 /* 114308 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41309 /* 114314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41310 /* 114316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41311 /* 114319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41312 /* 114321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41313 /* 114324 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41314 /* 114329 */ // GIR_Coverage, 2643,
41315 /* 114329 */ GIR_EraseRootFromParent_Done,
41316 /* 114330 */ // Label 3454: @114330
41317 /* 114330 */ GIM_Reject,
41318 /* 114331 */ // Label 3450: @114331
41319 /* 114331 */ GIM_Reject,
41320 /* 114332 */ // Label 3447: @114332
41321 /* 114332 */ GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(114568),
41322 /* 114337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41323 /* 114341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3456*/ GIMT_Encode4(114399), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2566 //
41324 /* 114348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41325 /* 114352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41326 /* 114356 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41327 /* 114360 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41328 /* 114365 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41329 /* 114367 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41330 /* 114367 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41331 /* 114370 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS),
41332 /* 114374 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41333 /* 114379 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41334 /* 114383 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41335 /* 114385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41336 /* 114388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41337 /* 114390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41338 /* 114393 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41339 /* 114398 */ // GIR_Coverage, 2566,
41340 /* 114398 */ GIR_EraseRootFromParent_Done,
41341 /* 114399 */ // Label 3456: @114399
41342 /* 114399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3457*/ GIMT_Encode4(114457), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2590 //
41343 /* 114406 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41344 /* 114410 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41345 /* 114414 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41346 /* 114418 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41347 /* 114423 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41348 /* 114425 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41349 /* 114425 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41350 /* 114428 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS),
41351 /* 114432 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41352 /* 114437 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41353 /* 114441 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41354 /* 114443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41355 /* 114446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41356 /* 114448 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41357 /* 114451 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41358 /* 114456 */ // GIR_Coverage, 2590,
41359 /* 114456 */ GIR_EraseRootFromParent_Done,
41360 /* 114457 */ // Label 3457: @114457
41361 /* 114457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3458*/ GIMT_Encode4(114515), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2542 //
41362 /* 114464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41363 /* 114468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41364 /* 114472 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41365 /* 114476 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41366 /* 114481 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41367 /* 114483 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41368 /* 114483 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41369 /* 114486 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS),
41370 /* 114490 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41371 /* 114495 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41372 /* 114499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41373 /* 114501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41374 /* 114504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41375 /* 114506 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41376 /* 114509 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41377 /* 114514 */ // GIR_Coverage, 2542,
41378 /* 114514 */ GIR_EraseRootFromParent_Done,
41379 /* 114515 */ // Label 3458: @114515
41380 /* 114515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3459*/ GIMT_Encode4(114567), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2637 //
41381 /* 114522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41382 /* 114526 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41383 /* 114526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41384 /* 114529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS),
41385 /* 114533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41386 /* 114538 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41387 /* 114542 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41388 /* 114545 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41389 /* 114551 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41390 /* 114553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41391 /* 114556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41392 /* 114558 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41393 /* 114561 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41394 /* 114566 */ // GIR_Coverage, 2637,
41395 /* 114566 */ GIR_EraseRootFromParent_Done,
41396 /* 114567 */ // Label 3459: @114567
41397 /* 114567 */ GIM_Reject,
41398 /* 114568 */ // Label 3455: @114568
41399 /* 114568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3460*/ GIMT_Encode4(114683), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3099 //
41400 /* 114575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41401 /* 114579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41402 /* 114583 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
41403 /* 114583 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41404 /* 114586 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41405 /* 114590 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41406 /* 114595 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41407 /* 114597 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
41408 /* 114600 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41409 /* 114604 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41410 /* 114609 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41411 /* 114612 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
41412 /* 114616 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
41413 /* 114619 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41414 /* 114624 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41415 /* 114629 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41416 /* 114634 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41417 /* 114637 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
41418 /* 114641 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41419 /* 114646 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41420 /* 114649 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41421 /* 114652 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41422 /* 114658 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41423 /* 114660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41424 /* 114663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41425 /* 114665 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41426 /* 114672 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41427 /* 114677 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41428 /* 114682 */ // GIR_Coverage, 3099,
41429 /* 114682 */ GIR_EraseRootFromParent_Done,
41430 /* 114683 */ // Label 3460: @114683
41431 /* 114683 */ GIM_Reject,
41432 /* 114684 */ // Label 3448: @114684
41433 /* 114684 */ GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(114920),
41434 /* 114689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41435 /* 114693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3462*/ GIMT_Encode4(114751), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2574 //
41436 /* 114700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41437 /* 114704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41438 /* 114708 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41439 /* 114712 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41440 /* 114717 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41441 /* 114719 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41442 /* 114719 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41443 /* 114722 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD),
41444 /* 114726 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41445 /* 114731 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41446 /* 114735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41447 /* 114737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41448 /* 114740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41449 /* 114742 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41450 /* 114745 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41451 /* 114750 */ // GIR_Coverage, 2574,
41452 /* 114750 */ GIR_EraseRootFromParent_Done,
41453 /* 114751 */ // Label 3462: @114751
41454 /* 114751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3463*/ GIMT_Encode4(114809), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2598 //
41455 /* 114758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41456 /* 114762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41457 /* 114766 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41458 /* 114770 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41459 /* 114775 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41460 /* 114777 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41461 /* 114777 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41462 /* 114780 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD),
41463 /* 114784 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41464 /* 114789 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41465 /* 114793 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41466 /* 114795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41467 /* 114798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41468 /* 114800 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41469 /* 114803 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41470 /* 114808 */ // GIR_Coverage, 2598,
41471 /* 114808 */ GIR_EraseRootFromParent_Done,
41472 /* 114809 */ // Label 3463: @114809
41473 /* 114809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3464*/ GIMT_Encode4(114867), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2550 //
41474 /* 114816 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41475 /* 114820 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41476 /* 114824 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41477 /* 114828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41478 /* 114833 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41479 /* 114835 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41480 /* 114835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41481 /* 114838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD),
41482 /* 114842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41483 /* 114847 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41484 /* 114851 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41485 /* 114853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41486 /* 114856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41487 /* 114858 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41488 /* 114861 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41489 /* 114866 */ // GIR_Coverage, 2550,
41490 /* 114866 */ GIR_EraseRootFromParent_Done,
41491 /* 114867 */ // Label 3464: @114867
41492 /* 114867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3465*/ GIMT_Encode4(114919), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2631 //
41493 /* 114874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41494 /* 114878 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41495 /* 114878 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41496 /* 114881 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD),
41497 /* 114885 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41498 /* 114890 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41499 /* 114894 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41500 /* 114897 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41501 /* 114903 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41502 /* 114905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41503 /* 114908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41504 /* 114910 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41505 /* 114913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41506 /* 114918 */ // GIR_Coverage, 2631,
41507 /* 114918 */ GIR_EraseRootFromParent_Done,
41508 /* 114919 */ // Label 3465: @114919
41509 /* 114919 */ GIM_Reject,
41510 /* 114920 */ // Label 3461: @114920
41511 /* 114920 */ GIM_Reject,
41512 /* 114921 */ // Label 3449: @114921
41513 /* 114921 */ GIM_Reject,
41514 /* 114922 */ // Label 3439: @114922
41515 /* 114922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3466*/ GIMT_Encode4(114973), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5640 //
41516 /* 114929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41517 /* 114932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41518 /* 114936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41519 /* 114940 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41520 /* 114940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
41521 /* 114943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41522 /* 114945 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41523 /* 114947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41524 /* 114953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41525 /* 114956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41526 /* 114959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41527 /* 114965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41528 /* 114971 */ GIR_RootConstrainSelectedInstOperands,
41529 /* 114972 */ // GIR_Coverage, 5640,
41530 /* 114972 */ GIR_EraseRootFromParent_Done,
41531 /* 114973 */ // Label 3466: @114973
41532 /* 114973 */ GIM_Reject,
41533 /* 114974 */ // Label 3440: @114974
41534 /* 114974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3467*/ GIMT_Encode4(115025), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5641 //
41535 /* 114981 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41536 /* 114984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41537 /* 114988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41538 /* 114992 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41539 /* 114992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
41540 /* 114995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41541 /* 114997 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41542 /* 114999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41543 /* 115005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41544 /* 115008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41545 /* 115011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41546 /* 115017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41547 /* 115023 */ GIR_RootConstrainSelectedInstOperands,
41548 /* 115024 */ // GIR_Coverage, 5641,
41549 /* 115024 */ GIR_EraseRootFromParent_Done,
41550 /* 115025 */ // Label 3467: @115025
41551 /* 115025 */ GIM_Reject,
41552 /* 115026 */ // Label 3441: @115026
41553 /* 115026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3468*/ GIMT_Encode4(115062), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1774 //
41554 /* 115033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41555 /* 115036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41556 /* 115040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41557 /* 115044 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
41558 /* 115044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd),
41559 /* 115047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41560 /* 115049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41561 /* 115051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41562 /* 115054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41563 /* 115060 */ GIR_RootConstrainSelectedInstOperands,
41564 /* 115061 */ // GIR_Coverage, 1774,
41565 /* 115061 */ GIR_EraseRootFromParent_Done,
41566 /* 115062 */ // Label 3468: @115062
41567 /* 115062 */ GIM_Reject,
41568 /* 115063 */ // Label 3442: @115063
41569 /* 115063 */ GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(115159),
41570 /* 115068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41571 /* 115071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3470*/ GIMT_Encode4(115104), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1778 //
41572 /* 115078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41573 /* 115082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41574 /* 115086 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
41575 /* 115086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq),
41576 /* 115089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41577 /* 115091 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41578 /* 115093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41579 /* 115096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41580 /* 115102 */ GIR_RootConstrainSelectedInstOperands,
41581 /* 115103 */ // GIR_Coverage, 1778,
41582 /* 115103 */ GIR_EraseRootFromParent_Done,
41583 /* 115104 */ // Label 3470: @115104
41584 /* 115104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3471*/ GIMT_Encode4(115158), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4541 //
41585 /* 115111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41586 /* 115115 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41587 /* 115119 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
41588 /* 115119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41589 /* 115122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41590 /* 115126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41591 /* 115131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
41592 /* 115134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41593 /* 115136 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41594 /* 115138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41595 /* 115141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41596 /* 115147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41597 /* 115153 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41598 /* 115156 */ GIR_RootConstrainSelectedInstOperands,
41599 /* 115157 */ // GIR_Coverage, 4541,
41600 /* 115157 */ GIR_EraseRootFromParent_Done,
41601 /* 115158 */ // Label 3471: @115158
41602 /* 115158 */ GIM_Reject,
41603 /* 115159 */ // Label 3469: @115159
41604 /* 115159 */ GIM_Reject,
41605 /* 115160 */ // Label 3443: @115160
41606 /* 115160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3472*/ GIMT_Encode4(115196), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1766 //
41607 /* 115167 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
41608 /* 115170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41609 /* 115174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41610 /* 115178 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
41611 /* 115178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
41612 /* 115181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41613 /* 115183 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41614 /* 115185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41615 /* 115188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41616 /* 115194 */ GIR_RootConstrainSelectedInstOperands,
41617 /* 115195 */ // GIR_Coverage, 1766,
41618 /* 115195 */ GIR_EraseRootFromParent_Done,
41619 /* 115196 */ // Label 3472: @115196
41620 /* 115196 */ GIM_Reject,
41621 /* 115197 */ // Label 3444: @115197
41622 /* 115197 */ GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(115293),
41623 /* 115202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41624 /* 115205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3474*/ GIMT_Encode4(115238), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1770 //
41625 /* 115212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41626 /* 115216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41627 /* 115220 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
41628 /* 115220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq),
41629 /* 115223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41630 /* 115225 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41631 /* 115227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41632 /* 115230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41633 /* 115236 */ GIR_RootConstrainSelectedInstOperands,
41634 /* 115237 */ // GIR_Coverage, 1770,
41635 /* 115237 */ GIR_EraseRootFromParent_Done,
41636 /* 115238 */ // Label 3474: @115238
41637 /* 115238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3475*/ GIMT_Encode4(115292), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4547 //
41638 /* 115245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41639 /* 115249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41640 /* 115253 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
41641 /* 115253 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41642 /* 115256 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41643 /* 115260 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41644 /* 115265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
41645 /* 115268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41646 /* 115270 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41647 /* 115272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41648 /* 115275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41649 /* 115281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41650 /* 115287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41651 /* 115290 */ GIR_RootConstrainSelectedInstOperands,
41652 /* 115291 */ // GIR_Coverage, 4547,
41653 /* 115291 */ GIR_EraseRootFromParent_Done,
41654 /* 115292 */ // Label 3475: @115292
41655 /* 115292 */ GIM_Reject,
41656 /* 115293 */ // Label 3473: @115293
41657 /* 115293 */ GIM_Reject,
41658 /* 115294 */ // Label 3445: @115294
41659 /* 115294 */ GIM_Reject,
41660 /* 115295 */ // Label 50: @115295
41661 /* 115295 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3483*/ GIMT_Encode4(116576),
41662 /* 115306 */ /*GILLT_s32*//*Label 3476*/ GIMT_Encode4(115354), GIMT_Encode4(0), GIMT_Encode4(0),
41663 /* 115318 */ /*GILLT_v4s1*//*Label 3477*/ GIMT_Encode4(116204),
41664 /* 115322 */ /*GILLT_v8s1*//*Label 3478*/ GIMT_Encode4(116256), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41665 /* 115338 */ /*GILLT_v4s16*//*Label 3479*/ GIMT_Encode4(116308),
41666 /* 115342 */ /*GILLT_v8s16*//*Label 3480*/ GIMT_Encode4(116345),
41667 /* 115346 */ /*GILLT_v2s32*//*Label 3481*/ GIMT_Encode4(116442),
41668 /* 115350 */ /*GILLT_v4s32*//*Label 3482*/ GIMT_Encode4(116479),
41669 /* 115354 */ // Label 3476: @115354
41670 /* 115354 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3487*/ GIMT_Encode4(116203),
41671 /* 115365 */ /*GILLT_s16*//*Label 3484*/ GIMT_Encode4(115377),
41672 /* 115369 */ /*GILLT_s32*//*Label 3485*/ GIMT_Encode4(115614),
41673 /* 115373 */ /*GILLT_s64*//*Label 3486*/ GIMT_Encode4(115966),
41674 /* 115377 */ // Label 3484: @115377
41675 /* 115377 */ GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(115613),
41676 /* 115382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41677 /* 115386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3489*/ GIMT_Encode4(115444), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2562 //
41678 /* 115393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41679 /* 115397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41680 /* 115401 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41681 /* 115405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41682 /* 115410 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41683 /* 115412 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41684 /* 115412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41685 /* 115415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH),
41686 /* 115419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41687 /* 115424 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41688 /* 115428 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41689 /* 115430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41690 /* 115433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41691 /* 115435 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41692 /* 115438 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41693 /* 115443 */ // GIR_Coverage, 2562,
41694 /* 115443 */ GIR_EraseRootFromParent_Done,
41695 /* 115444 */ // Label 3489: @115444
41696 /* 115444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3490*/ GIMT_Encode4(115502), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2586 //
41697 /* 115451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41698 /* 115455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41699 /* 115459 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41700 /* 115463 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41701 /* 115468 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41702 /* 115470 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41703 /* 115470 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41704 /* 115473 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH),
41705 /* 115477 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41706 /* 115482 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41707 /* 115486 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41708 /* 115488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41709 /* 115491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41710 /* 115493 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41711 /* 115496 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41712 /* 115501 */ // GIR_Coverage, 2586,
41713 /* 115501 */ GIR_EraseRootFromParent_Done,
41714 /* 115502 */ // Label 3490: @115502
41715 /* 115502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3491*/ GIMT_Encode4(115560), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2538 //
41716 /* 115509 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41717 /* 115513 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41718 /* 115517 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41719 /* 115521 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41720 /* 115526 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41721 /* 115528 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41722 /* 115528 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41723 /* 115531 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH),
41724 /* 115535 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41725 /* 115540 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41726 /* 115544 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41727 /* 115546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41728 /* 115549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41729 /* 115551 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41730 /* 115554 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41731 /* 115559 */ // GIR_Coverage, 2538,
41732 /* 115559 */ GIR_EraseRootFromParent_Done,
41733 /* 115560 */ // Label 3491: @115560
41734 /* 115560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3492*/ GIMT_Encode4(115612), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2658 //
41735 /* 115567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41736 /* 115571 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41737 /* 115571 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41738 /* 115574 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH),
41739 /* 115578 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41740 /* 115583 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41741 /* 115587 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41742 /* 115590 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41743 /* 115596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41744 /* 115598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41745 /* 115601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41746 /* 115603 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41747 /* 115606 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41748 /* 115611 */ // GIR_Coverage, 2658,
41749 /* 115611 */ GIR_EraseRootFromParent_Done,
41750 /* 115612 */ // Label 3492: @115612
41751 /* 115612 */ GIM_Reject,
41752 /* 115613 */ // Label 3488: @115613
41753 /* 115613 */ GIM_Reject,
41754 /* 115614 */ // Label 3485: @115614
41755 /* 115614 */ GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(115850),
41756 /* 115619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41757 /* 115623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3494*/ GIMT_Encode4(115681), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2570 //
41758 /* 115630 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41759 /* 115634 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41760 /* 115638 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41761 /* 115642 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41762 /* 115647 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41763 /* 115649 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41764 /* 115649 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41765 /* 115652 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS),
41766 /* 115656 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41767 /* 115661 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41768 /* 115665 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41769 /* 115667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41770 /* 115670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41771 /* 115672 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41772 /* 115675 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41773 /* 115680 */ // GIR_Coverage, 2570,
41774 /* 115680 */ GIR_EraseRootFromParent_Done,
41775 /* 115681 */ // Label 3494: @115681
41776 /* 115681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3495*/ GIMT_Encode4(115739), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2594 //
41777 /* 115688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41778 /* 115692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41779 /* 115696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41780 /* 115700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41781 /* 115705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41782 /* 115707 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41783 /* 115707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41784 /* 115710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS),
41785 /* 115714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41786 /* 115719 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41787 /* 115723 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41788 /* 115725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41789 /* 115728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41790 /* 115730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41791 /* 115733 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41792 /* 115738 */ // GIR_Coverage, 2594,
41793 /* 115738 */ GIR_EraseRootFromParent_Done,
41794 /* 115739 */ // Label 3495: @115739
41795 /* 115739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3496*/ GIMT_Encode4(115797), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2546 //
41796 /* 115746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41797 /* 115750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41798 /* 115754 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41799 /* 115758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41800 /* 115763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41801 /* 115765 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41802 /* 115765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41803 /* 115768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS),
41804 /* 115772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41805 /* 115777 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41806 /* 115781 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41807 /* 115783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41808 /* 115786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41809 /* 115788 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41810 /* 115791 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41811 /* 115796 */ // GIR_Coverage, 2546,
41812 /* 115796 */ GIR_EraseRootFromParent_Done,
41813 /* 115797 */ // Label 3496: @115797
41814 /* 115797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3497*/ GIMT_Encode4(115849), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2652 //
41815 /* 115804 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41816 /* 115808 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41817 /* 115808 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41818 /* 115811 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS),
41819 /* 115815 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41820 /* 115820 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41821 /* 115824 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41822 /* 115827 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41823 /* 115833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41824 /* 115835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41825 /* 115838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41826 /* 115840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41827 /* 115843 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41828 /* 115848 */ // GIR_Coverage, 2652,
41829 /* 115848 */ GIR_EraseRootFromParent_Done,
41830 /* 115849 */ // Label 3497: @115849
41831 /* 115849 */ GIM_Reject,
41832 /* 115850 */ // Label 3493: @115850
41833 /* 115850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3498*/ GIMT_Encode4(115965), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3100 //
41834 /* 115857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41835 /* 115861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41836 /* 115865 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
41837 /* 115865 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41838 /* 115868 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41839 /* 115872 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41840 /* 115877 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41841 /* 115879 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
41842 /* 115882 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41843 /* 115886 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41844 /* 115891 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41845 /* 115894 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
41846 /* 115898 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
41847 /* 115901 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41848 /* 115906 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41849 /* 115911 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41850 /* 115916 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41851 /* 115919 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
41852 /* 115923 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41853 /* 115928 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41854 /* 115931 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41855 /* 115934 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41856 /* 115940 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41857 /* 115942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41858 /* 115945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41859 /* 115947 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41860 /* 115954 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41861 /* 115959 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41862 /* 115964 */ // GIR_Coverage, 3100,
41863 /* 115964 */ GIR_EraseRootFromParent_Done,
41864 /* 115965 */ // Label 3498: @115965
41865 /* 115965 */ GIM_Reject,
41866 /* 115966 */ // Label 3486: @115966
41867 /* 115966 */ GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(116202),
41868 /* 115971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41869 /* 115975 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3500*/ GIMT_Encode4(116033), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2578 //
41870 /* 115982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41871 /* 115986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41872 /* 115990 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41873 /* 115994 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41874 /* 115999 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41875 /* 116001 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41876 /* 116001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41877 /* 116004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD),
41878 /* 116008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41879 /* 116013 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41880 /* 116017 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41881 /* 116019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41882 /* 116022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41883 /* 116024 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41884 /* 116027 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41885 /* 116032 */ // GIR_Coverage, 2578,
41886 /* 116032 */ GIR_EraseRootFromParent_Done,
41887 /* 116033 */ // Label 3500: @116033
41888 /* 116033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3501*/ GIMT_Encode4(116091), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2602 //
41889 /* 116040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41890 /* 116044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41891 /* 116048 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41892 /* 116052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41893 /* 116057 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41894 /* 116059 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41895 /* 116059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41896 /* 116062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD),
41897 /* 116066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41898 /* 116071 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41899 /* 116075 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41900 /* 116077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41901 /* 116080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41902 /* 116082 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41903 /* 116085 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41904 /* 116090 */ // GIR_Coverage, 2602,
41905 /* 116090 */ GIR_EraseRootFromParent_Done,
41906 /* 116091 */ // Label 3501: @116091
41907 /* 116091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3502*/ GIMT_Encode4(116149), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2554 //
41908 /* 116098 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41909 /* 116102 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41910 /* 116106 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41911 /* 116110 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41912 /* 116115 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41913 /* 116117 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41914 /* 116117 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41915 /* 116120 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD),
41916 /* 116124 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41917 /* 116129 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41918 /* 116133 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41919 /* 116135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41920 /* 116138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41921 /* 116140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41922 /* 116143 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41923 /* 116148 */ // GIR_Coverage, 2554,
41924 /* 116148 */ GIR_EraseRootFromParent_Done,
41925 /* 116149 */ // Label 3502: @116149
41926 /* 116149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3503*/ GIMT_Encode4(116201), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2646 //
41927 /* 116156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41928 /* 116160 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41929 /* 116160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41930 /* 116163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD),
41931 /* 116167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41932 /* 116172 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41933 /* 116176 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41934 /* 116179 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41935 /* 116185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41936 /* 116187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41937 /* 116190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41938 /* 116192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41939 /* 116195 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41940 /* 116200 */ // GIR_Coverage, 2646,
41941 /* 116200 */ GIR_EraseRootFromParent_Done,
41942 /* 116201 */ // Label 3503: @116201
41943 /* 116201 */ GIM_Reject,
41944 /* 116202 */ // Label 3499: @116202
41945 /* 116202 */ GIM_Reject,
41946 /* 116203 */ // Label 3487: @116203
41947 /* 116203 */ GIM_Reject,
41948 /* 116204 */ // Label 3477: @116204
41949 /* 116204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3504*/ GIMT_Encode4(116255), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5638 //
41950 /* 116211 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41951 /* 116214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41952 /* 116218 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41953 /* 116222 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41954 /* 116222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
41955 /* 116225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41956 /* 116227 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41957 /* 116229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41958 /* 116235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41959 /* 116238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41960 /* 116241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41961 /* 116247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41962 /* 116253 */ GIR_RootConstrainSelectedInstOperands,
41963 /* 116254 */ // GIR_Coverage, 5638,
41964 /* 116254 */ GIR_EraseRootFromParent_Done,
41965 /* 116255 */ // Label 3504: @116255
41966 /* 116255 */ GIM_Reject,
41967 /* 116256 */ // Label 3478: @116256
41968 /* 116256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3505*/ GIMT_Encode4(116307), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5639 //
41969 /* 116263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41970 /* 116266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41971 /* 116270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41972 /* 116274 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41973 /* 116274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
41974 /* 116277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41975 /* 116279 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41976 /* 116281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41977 /* 116287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41978 /* 116290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41979 /* 116293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41980 /* 116299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41981 /* 116305 */ GIR_RootConstrainSelectedInstOperands,
41982 /* 116306 */ // GIR_Coverage, 5639,
41983 /* 116306 */ GIR_EraseRootFromParent_Done,
41984 /* 116307 */ // Label 3505: @116307
41985 /* 116307 */ GIM_Reject,
41986 /* 116308 */ // Label 3479: @116308
41987 /* 116308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3506*/ GIMT_Encode4(116344), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1775 //
41988 /* 116315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41989 /* 116318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41990 /* 116322 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41991 /* 116326 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
41992 /* 116326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud),
41993 /* 116329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41994 /* 116331 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41995 /* 116333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41996 /* 116336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41997 /* 116342 */ GIR_RootConstrainSelectedInstOperands,
41998 /* 116343 */ // GIR_Coverage, 1775,
41999 /* 116343 */ GIR_EraseRootFromParent_Done,
42000 /* 116344 */ // Label 3506: @116344
42001 /* 116344 */ GIM_Reject,
42002 /* 116345 */ // Label 3480: @116345
42003 /* 116345 */ GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(116441),
42004 /* 116350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42005 /* 116353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3508*/ GIMT_Encode4(116386), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1779 //
42006 /* 116360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42007 /* 116364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42008 /* 116368 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
42009 /* 116368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq),
42010 /* 116371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42011 /* 116373 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42012 /* 116375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42013 /* 116378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42014 /* 116384 */ GIR_RootConstrainSelectedInstOperands,
42015 /* 116385 */ // GIR_Coverage, 1779,
42016 /* 116385 */ GIR_EraseRootFromParent_Done,
42017 /* 116386 */ // Label 3508: @116386
42018 /* 116386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3509*/ GIMT_Encode4(116440), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4544 //
42019 /* 116393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42020 /* 116397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42021 /* 116401 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
42022 /* 116401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42023 /* 116404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42024 /* 116408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42025 /* 116413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
42026 /* 116416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42027 /* 116418 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42028 /* 116420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42029 /* 116423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42030 /* 116429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42031 /* 116435 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42032 /* 116438 */ GIR_RootConstrainSelectedInstOperands,
42033 /* 116439 */ // GIR_Coverage, 4544,
42034 /* 116439 */ GIR_EraseRootFromParent_Done,
42035 /* 116440 */ // Label 3509: @116440
42036 /* 116440 */ GIM_Reject,
42037 /* 116441 */ // Label 3507: @116441
42038 /* 116441 */ GIM_Reject,
42039 /* 116442 */ // Label 3481: @116442
42040 /* 116442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3510*/ GIMT_Encode4(116478), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1767 //
42041 /* 116449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42042 /* 116452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42043 /* 116456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42044 /* 116460 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
42045 /* 116460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
42046 /* 116463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42047 /* 116465 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42048 /* 116467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42049 /* 116470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42050 /* 116476 */ GIR_RootConstrainSelectedInstOperands,
42051 /* 116477 */ // GIR_Coverage, 1767,
42052 /* 116477 */ GIR_EraseRootFromParent_Done,
42053 /* 116478 */ // Label 3510: @116478
42054 /* 116478 */ GIM_Reject,
42055 /* 116479 */ // Label 3482: @116479
42056 /* 116479 */ GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(116575),
42057 /* 116484 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42058 /* 116487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3512*/ GIMT_Encode4(116520), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1771 //
42059 /* 116494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42060 /* 116498 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42061 /* 116502 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
42062 /* 116502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq),
42063 /* 116505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42064 /* 116507 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42065 /* 116509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42066 /* 116512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42067 /* 116518 */ GIR_RootConstrainSelectedInstOperands,
42068 /* 116519 */ // GIR_Coverage, 1771,
42069 /* 116519 */ GIR_EraseRootFromParent_Done,
42070 /* 116520 */ // Label 3512: @116520
42071 /* 116520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3513*/ GIMT_Encode4(116574), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4550 //
42072 /* 116527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42073 /* 116531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42074 /* 116535 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
42075 /* 116535 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42076 /* 116538 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42077 /* 116542 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42078 /* 116547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
42079 /* 116550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42080 /* 116552 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42081 /* 116554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42082 /* 116557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42083 /* 116563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42084 /* 116569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42085 /* 116572 */ GIR_RootConstrainSelectedInstOperands,
42086 /* 116573 */ // GIR_Coverage, 4550,
42087 /* 116573 */ GIR_EraseRootFromParent_Done,
42088 /* 116574 */ // Label 3513: @116574
42089 /* 116574 */ GIM_Reject,
42090 /* 116575 */ // Label 3511: @116575
42091 /* 116575 */ GIM_Reject,
42092 /* 116576 */ // Label 3483: @116576
42093 /* 116576 */ GIM_Reject,
42094 /* 116577 */ // Label 51: @116577
42095 /* 116577 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3521*/ GIMT_Encode4(117218),
42096 /* 116588 */ /*GILLT_s16*//*Label 3514*/ GIMT_Encode4(116640),
42097 /* 116592 */ /*GILLT_s32*//*Label 3515*/ GIMT_Encode4(116699),
42098 /* 116596 */ /*GILLT_s64*//*Label 3516*/ GIMT_Encode4(116891), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42099 /* 116624 */ /*GILLT_v4s16*//*Label 3517*/ GIMT_Encode4(116950),
42100 /* 116628 */ /*GILLT_v8s16*//*Label 3518*/ GIMT_Encode4(116987),
42101 /* 116632 */ /*GILLT_v2s32*//*Label 3519*/ GIMT_Encode4(117084),
42102 /* 116636 */ /*GILLT_v4s32*//*Label 3520*/ GIMT_Encode4(117121),
42103 /* 116640 */ // Label 3514: @116640
42104 /* 116640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3522*/ GIMT_Encode4(116698), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2619 //
42105 /* 116647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42106 /* 116650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42107 /* 116654 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42108 /* 116658 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42109 /* 116658 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42110 /* 116661 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42111 /* 116665 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42112 /* 116670 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42113 /* 116674 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42114 /* 116679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH),
42115 /* 116682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42116 /* 116684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42117 /* 116687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42118 /* 116690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42119 /* 116696 */ GIR_RootConstrainSelectedInstOperands,
42120 /* 116697 */ // GIR_Coverage, 2619,
42121 /* 116697 */ GIR_EraseRootFromParent_Done,
42122 /* 116698 */ // Label 3522: @116698
42123 /* 116698 */ GIM_Reject,
42124 /* 116699 */ // Label 3515: @116699
42125 /* 116699 */ GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(116890),
42126 /* 116704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42127 /* 116707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42128 /* 116711 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42129 /* 116715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3524*/ GIMT_Encode4(116762), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2615 //
42130 /* 116722 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42131 /* 116722 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42132 /* 116725 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42133 /* 116729 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42134 /* 116734 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42135 /* 116738 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42136 /* 116743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS),
42137 /* 116746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42138 /* 116748 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42139 /* 116751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42140 /* 116754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42141 /* 116760 */ GIR_RootConstrainSelectedInstOperands,
42142 /* 116761 */ // GIR_Coverage, 2615,
42143 /* 116761 */ GIR_EraseRootFromParent_Done,
42144 /* 116762 */ // Label 3524: @116762
42145 /* 116762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3525*/ GIMT_Encode4(116889), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3101 //
42146 /* 116769 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
42147 /* 116769 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
42148 /* 116772 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42149 /* 116776 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42150 /* 116781 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
42151 /* 116785 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42152 /* 116790 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42153 /* 116793 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42154 /* 116797 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42155 /* 116802 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42156 /* 116804 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
42157 /* 116807 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42158 /* 116811 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42159 /* 116816 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42160 /* 116819 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
42161 /* 116822 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
42162 /* 116825 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42163 /* 116830 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42164 /* 116835 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42165 /* 116840 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42166 /* 116843 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
42167 /* 116847 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42168 /* 116852 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42169 /* 116855 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42170 /* 116858 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42171 /* 116864 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42172 /* 116866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42173 /* 116869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42174 /* 116871 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42175 /* 116878 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42176 /* 116883 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42177 /* 116888 */ // GIR_Coverage, 3101,
42178 /* 116888 */ GIR_EraseRootFromParent_Done,
42179 /* 116889 */ // Label 3525: @116889
42180 /* 116889 */ GIM_Reject,
42181 /* 116890 */ // Label 3523: @116890
42182 /* 116890 */ GIM_Reject,
42183 /* 116891 */ // Label 3516: @116891
42184 /* 116891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3526*/ GIMT_Encode4(116949), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2611 //
42185 /* 116898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42186 /* 116901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42187 /* 116905 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42188 /* 116909 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42189 /* 116909 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42190 /* 116912 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42191 /* 116916 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42192 /* 116921 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42193 /* 116925 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42194 /* 116930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD),
42195 /* 116933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42196 /* 116935 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42197 /* 116938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42198 /* 116941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42199 /* 116947 */ GIR_RootConstrainSelectedInstOperands,
42200 /* 116948 */ // GIR_Coverage, 2611,
42201 /* 116948 */ GIR_EraseRootFromParent_Done,
42202 /* 116949 */ // Label 3526: @116949
42203 /* 116949 */ GIM_Reject,
42204 /* 116950 */ // Label 3517: @116950
42205 /* 116950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3527*/ GIMT_Encode4(116986), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1776 //
42206 /* 116957 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42207 /* 116960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42208 /* 116964 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42209 /* 116968 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
42210 /* 116968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd),
42211 /* 116971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42212 /* 116973 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42213 /* 116975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42214 /* 116978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42215 /* 116984 */ GIR_RootConstrainSelectedInstOperands,
42216 /* 116985 */ // GIR_Coverage, 1776,
42217 /* 116985 */ GIR_EraseRootFromParent_Done,
42218 /* 116986 */ // Label 3527: @116986
42219 /* 116986 */ GIM_Reject,
42220 /* 116987 */ // Label 3518: @116987
42221 /* 116987 */ GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(117083),
42222 /* 116992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42223 /* 116995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3529*/ GIMT_Encode4(117028), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1780 //
42224 /* 117002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42225 /* 117006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42226 /* 117010 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
42227 /* 117010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq),
42228 /* 117013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42229 /* 117015 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42230 /* 117017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42231 /* 117020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42232 /* 117026 */ GIR_RootConstrainSelectedInstOperands,
42233 /* 117027 */ // GIR_Coverage, 1780,
42234 /* 117027 */ GIR_EraseRootFromParent_Done,
42235 /* 117028 */ // Label 3529: @117028
42236 /* 117028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3530*/ GIMT_Encode4(117082), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4553 //
42237 /* 117035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42238 /* 117039 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42239 /* 117043 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
42240 /* 117043 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42241 /* 117046 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42242 /* 117050 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42243 /* 117055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
42244 /* 117058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42245 /* 117060 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42246 /* 117062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42247 /* 117065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42248 /* 117071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42249 /* 117077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42250 /* 117080 */ GIR_RootConstrainSelectedInstOperands,
42251 /* 117081 */ // GIR_Coverage, 4553,
42252 /* 117081 */ GIR_EraseRootFromParent_Done,
42253 /* 117082 */ // Label 3530: @117082
42254 /* 117082 */ GIM_Reject,
42255 /* 117083 */ // Label 3528: @117083
42256 /* 117083 */ GIM_Reject,
42257 /* 117084 */ // Label 3519: @117084
42258 /* 117084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3531*/ GIMT_Encode4(117120), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1768 //
42259 /* 117091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42260 /* 117094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42261 /* 117098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42262 /* 117102 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
42263 /* 117102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
42264 /* 117105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42265 /* 117107 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42266 /* 117109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42267 /* 117112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42268 /* 117118 */ GIR_RootConstrainSelectedInstOperands,
42269 /* 117119 */ // GIR_Coverage, 1768,
42270 /* 117119 */ GIR_EraseRootFromParent_Done,
42271 /* 117120 */ // Label 3531: @117120
42272 /* 117120 */ GIM_Reject,
42273 /* 117121 */ // Label 3520: @117121
42274 /* 117121 */ GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(117217),
42275 /* 117126 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42276 /* 117129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3533*/ GIMT_Encode4(117162), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1772 //
42277 /* 117136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42278 /* 117140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42279 /* 117144 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
42280 /* 117144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq),
42281 /* 117147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42282 /* 117149 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42283 /* 117151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42284 /* 117154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42285 /* 117160 */ GIR_RootConstrainSelectedInstOperands,
42286 /* 117161 */ // GIR_Coverage, 1772,
42287 /* 117161 */ GIR_EraseRootFromParent_Done,
42288 /* 117162 */ // Label 3533: @117162
42289 /* 117162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3534*/ GIMT_Encode4(117216), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4559 //
42290 /* 117169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42291 /* 117173 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42292 /* 117177 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
42293 /* 117177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42294 /* 117180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42295 /* 117184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42296 /* 117189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
42297 /* 117192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42298 /* 117194 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42299 /* 117196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42300 /* 117199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42301 /* 117205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42302 /* 117211 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42303 /* 117214 */ GIR_RootConstrainSelectedInstOperands,
42304 /* 117215 */ // GIR_Coverage, 4559,
42305 /* 117215 */ GIR_EraseRootFromParent_Done,
42306 /* 117216 */ // Label 3534: @117216
42307 /* 117216 */ GIM_Reject,
42308 /* 117217 */ // Label 3532: @117217
42309 /* 117217 */ GIM_Reject,
42310 /* 117218 */ // Label 3521: @117218
42311 /* 117218 */ GIM_Reject,
42312 /* 117219 */ // Label 52: @117219
42313 /* 117219 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3542*/ GIMT_Encode4(117860),
42314 /* 117230 */ /*GILLT_s16*//*Label 3535*/ GIMT_Encode4(117282),
42315 /* 117234 */ /*GILLT_s32*//*Label 3536*/ GIMT_Encode4(117341),
42316 /* 117238 */ /*GILLT_s64*//*Label 3537*/ GIMT_Encode4(117533), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42317 /* 117266 */ /*GILLT_v4s16*//*Label 3538*/ GIMT_Encode4(117592),
42318 /* 117270 */ /*GILLT_v8s16*//*Label 3539*/ GIMT_Encode4(117629),
42319 /* 117274 */ /*GILLT_v2s32*//*Label 3540*/ GIMT_Encode4(117726),
42320 /* 117278 */ /*GILLT_v4s32*//*Label 3541*/ GIMT_Encode4(117763),
42321 /* 117282 */ // Label 3535: @117282
42322 /* 117282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3543*/ GIMT_Encode4(117340), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2629 //
42323 /* 117289 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42324 /* 117292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42325 /* 117296 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42326 /* 117300 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42327 /* 117300 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42328 /* 117303 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42329 /* 117307 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42330 /* 117312 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42331 /* 117316 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42332 /* 117321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH),
42333 /* 117324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42334 /* 117326 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42335 /* 117329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42336 /* 117332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42337 /* 117338 */ GIR_RootConstrainSelectedInstOperands,
42338 /* 117339 */ // GIR_Coverage, 2629,
42339 /* 117339 */ GIR_EraseRootFromParent_Done,
42340 /* 117340 */ // Label 3543: @117340
42341 /* 117340 */ GIM_Reject,
42342 /* 117341 */ // Label 3536: @117341
42343 /* 117341 */ GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(117532),
42344 /* 117346 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42345 /* 117349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42346 /* 117353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42347 /* 117357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3545*/ GIMT_Encode4(117404), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2625 //
42348 /* 117364 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42349 /* 117364 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42350 /* 117367 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42351 /* 117371 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42352 /* 117376 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42353 /* 117380 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42354 /* 117385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS),
42355 /* 117388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42356 /* 117390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42357 /* 117393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42358 /* 117396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42359 /* 117402 */ GIR_RootConstrainSelectedInstOperands,
42360 /* 117403 */ // GIR_Coverage, 2625,
42361 /* 117403 */ GIR_EraseRootFromParent_Done,
42362 /* 117404 */ // Label 3545: @117404
42363 /* 117404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3546*/ GIMT_Encode4(117531), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3102 //
42364 /* 117411 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
42365 /* 117411 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
42366 /* 117414 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42367 /* 117418 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42368 /* 117423 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
42369 /* 117427 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42370 /* 117432 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42371 /* 117435 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42372 /* 117439 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42373 /* 117444 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42374 /* 117446 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
42375 /* 117449 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42376 /* 117453 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42377 /* 117458 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42378 /* 117461 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
42379 /* 117464 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
42380 /* 117467 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42381 /* 117472 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42382 /* 117477 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42383 /* 117482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42384 /* 117485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
42385 /* 117489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42386 /* 117494 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42387 /* 117497 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42388 /* 117500 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42389 /* 117506 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42390 /* 117508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42391 /* 117511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42392 /* 117513 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42393 /* 117520 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42394 /* 117525 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42395 /* 117530 */ // GIR_Coverage, 3102,
42396 /* 117530 */ GIR_EraseRootFromParent_Done,
42397 /* 117531 */ // Label 3546: @117531
42398 /* 117531 */ GIM_Reject,
42399 /* 117532 */ // Label 3544: @117532
42400 /* 117532 */ GIM_Reject,
42401 /* 117533 */ // Label 3537: @117533
42402 /* 117533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3547*/ GIMT_Encode4(117591), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2621 //
42403 /* 117540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42404 /* 117543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42405 /* 117547 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42406 /* 117551 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42407 /* 117551 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42408 /* 117554 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42409 /* 117558 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42410 /* 117563 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42411 /* 117567 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42412 /* 117572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD),
42413 /* 117575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42414 /* 117577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42415 /* 117580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42416 /* 117583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42417 /* 117589 */ GIR_RootConstrainSelectedInstOperands,
42418 /* 117590 */ // GIR_Coverage, 2621,
42419 /* 117590 */ GIR_EraseRootFromParent_Done,
42420 /* 117591 */ // Label 3547: @117591
42421 /* 117591 */ GIM_Reject,
42422 /* 117592 */ // Label 3538: @117592
42423 /* 117592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3548*/ GIMT_Encode4(117628), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1777 //
42424 /* 117599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42425 /* 117602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42426 /* 117606 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42427 /* 117610 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
42428 /* 117610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd),
42429 /* 117613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42430 /* 117615 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42431 /* 117617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42432 /* 117620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42433 /* 117626 */ GIR_RootConstrainSelectedInstOperands,
42434 /* 117627 */ // GIR_Coverage, 1777,
42435 /* 117627 */ GIR_EraseRootFromParent_Done,
42436 /* 117628 */ // Label 3548: @117628
42437 /* 117628 */ GIM_Reject,
42438 /* 117629 */ // Label 3539: @117629
42439 /* 117629 */ GIM_Try, /*On fail goto*//*Label 3549*/ GIMT_Encode4(117725),
42440 /* 117634 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42441 /* 117637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3550*/ GIMT_Encode4(117670), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1781 //
42442 /* 117644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42443 /* 117648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42444 /* 117652 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
42445 /* 117652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq),
42446 /* 117655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42447 /* 117657 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42448 /* 117659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42449 /* 117662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42450 /* 117668 */ GIR_RootConstrainSelectedInstOperands,
42451 /* 117669 */ // GIR_Coverage, 1781,
42452 /* 117669 */ GIR_EraseRootFromParent_Done,
42453 /* 117670 */ // Label 3550: @117670
42454 /* 117670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3551*/ GIMT_Encode4(117724), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4556 //
42455 /* 117677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42456 /* 117681 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42457 /* 117685 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
42458 /* 117685 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42459 /* 117688 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42460 /* 117692 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42461 /* 117697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
42462 /* 117700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42463 /* 117702 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42464 /* 117704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42465 /* 117707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42466 /* 117713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42467 /* 117719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42468 /* 117722 */ GIR_RootConstrainSelectedInstOperands,
42469 /* 117723 */ // GIR_Coverage, 4556,
42470 /* 117723 */ GIR_EraseRootFromParent_Done,
42471 /* 117724 */ // Label 3551: @117724
42472 /* 117724 */ GIM_Reject,
42473 /* 117725 */ // Label 3549: @117725
42474 /* 117725 */ GIM_Reject,
42475 /* 117726 */ // Label 3540: @117726
42476 /* 117726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3552*/ GIMT_Encode4(117762), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1769 //
42477 /* 117733 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42478 /* 117736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42479 /* 117740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42480 /* 117744 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
42481 /* 117744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
42482 /* 117747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42483 /* 117749 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42484 /* 117751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42485 /* 117754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42486 /* 117760 */ GIR_RootConstrainSelectedInstOperands,
42487 /* 117761 */ // GIR_Coverage, 1769,
42488 /* 117761 */ GIR_EraseRootFromParent_Done,
42489 /* 117762 */ // Label 3552: @117762
42490 /* 117762 */ GIM_Reject,
42491 /* 117763 */ // Label 3541: @117763
42492 /* 117763 */ GIM_Try, /*On fail goto*//*Label 3553*/ GIMT_Encode4(117859),
42493 /* 117768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42494 /* 117771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3554*/ GIMT_Encode4(117804), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1773 //
42495 /* 117778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42496 /* 117782 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42497 /* 117786 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
42498 /* 117786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq),
42499 /* 117789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42500 /* 117791 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42501 /* 117793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42502 /* 117796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42503 /* 117802 */ GIR_RootConstrainSelectedInstOperands,
42504 /* 117803 */ // GIR_Coverage, 1773,
42505 /* 117803 */ GIR_EraseRootFromParent_Done,
42506 /* 117804 */ // Label 3554: @117804
42507 /* 117804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3555*/ GIMT_Encode4(117858), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4562 //
42508 /* 117811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42509 /* 117815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42510 /* 117819 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
42511 /* 117819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42512 /* 117822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42513 /* 117826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42514 /* 117831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
42515 /* 117834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42516 /* 117836 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42517 /* 117838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42518 /* 117841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42519 /* 117847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42520 /* 117853 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42521 /* 117856 */ GIR_RootConstrainSelectedInstOperands,
42522 /* 117857 */ // GIR_Coverage, 4562,
42523 /* 117857 */ GIR_EraseRootFromParent_Done,
42524 /* 117858 */ // Label 3555: @117858
42525 /* 117858 */ GIM_Reject,
42526 /* 117859 */ // Label 3553: @117859
42527 /* 117859 */ GIM_Reject,
42528 /* 117860 */ // Label 3542: @117860
42529 /* 117860 */ GIM_Reject,
42530 /* 117861 */ // Label 53: @117861
42531 /* 117861 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3559*/ GIMT_Encode4(118223),
42532 /* 117872 */ /*GILLT_s32*//*Label 3556*/ GIMT_Encode4(117920), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42533 /* 117908 */ /*GILLT_v8s16*//*Label 3557*/ GIMT_Encode4(118115), GIMT_Encode4(0),
42534 /* 117916 */ /*GILLT_v4s32*//*Label 3558*/ GIMT_Encode4(118169),
42535 /* 117920 */ // Label 3556: @117920
42536 /* 117920 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3563*/ GIMT_Encode4(118114),
42537 /* 117931 */ /*GILLT_s16*//*Label 3560*/ GIMT_Encode4(117943),
42538 /* 117935 */ /*GILLT_s32*//*Label 3561*/ GIMT_Encode4(118000),
42539 /* 117939 */ /*GILLT_s64*//*Label 3562*/ GIMT_Encode4(118057),
42540 /* 117943 */ // Label 3560: @117943
42541 /* 117943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3564*/ GIMT_Encode4(117999), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2644 //
42542 /* 117950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42543 /* 117954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42544 /* 117958 */ // (fp_to_sint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42545 /* 117958 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42546 /* 117961 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH),
42547 /* 117965 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42548 /* 117970 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42549 /* 117974 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42550 /* 117977 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42551 /* 117983 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42552 /* 117985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42553 /* 117988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42554 /* 117990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42555 /* 117993 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42556 /* 117998 */ // GIR_Coverage, 2644,
42557 /* 117998 */ GIR_EraseRootFromParent_Done,
42558 /* 117999 */ // Label 3564: @117999
42559 /* 117999 */ GIM_Reject,
42560 /* 118000 */ // Label 3561: @118000
42561 /* 118000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3565*/ GIMT_Encode4(118056), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2638 //
42562 /* 118007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42563 /* 118011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42564 /* 118015 */ // (fp_to_sint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42565 /* 118015 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42566 /* 118018 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS),
42567 /* 118022 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42568 /* 118027 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42569 /* 118031 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42570 /* 118034 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42571 /* 118040 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42572 /* 118042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42573 /* 118045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42574 /* 118047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42575 /* 118050 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42576 /* 118055 */ // GIR_Coverage, 2638,
42577 /* 118055 */ GIR_EraseRootFromParent_Done,
42578 /* 118056 */ // Label 3565: @118056
42579 /* 118056 */ GIM_Reject,
42580 /* 118057 */ // Label 3562: @118057
42581 /* 118057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3566*/ GIMT_Encode4(118113), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2632 //
42582 /* 118064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42583 /* 118068 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42584 /* 118072 */ // (fp_to_sint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42585 /* 118072 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42586 /* 118075 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD),
42587 /* 118079 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42588 /* 118084 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42589 /* 118088 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42590 /* 118091 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42591 /* 118097 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42592 /* 118099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42593 /* 118102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42594 /* 118104 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42595 /* 118107 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42596 /* 118112 */ // GIR_Coverage, 2632,
42597 /* 118112 */ GIR_EraseRootFromParent_Done,
42598 /* 118113 */ // Label 3566: @118113
42599 /* 118113 */ GIM_Reject,
42600 /* 118114 */ // Label 3563: @118114
42601 /* 118114 */ GIM_Reject,
42602 /* 118115 */ // Label 3557: @118115
42603 /* 118115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3567*/ GIMT_Encode4(118168), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4567 //
42604 /* 118122 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42605 /* 118125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42606 /* 118129 */ // (fp_to_sint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)
42607 /* 118129 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42608 /* 118132 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42609 /* 118136 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42610 /* 118141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
42611 /* 118144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42612 /* 118146 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42613 /* 118148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42614 /* 118151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42615 /* 118157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42616 /* 118163 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42617 /* 118166 */ GIR_RootConstrainSelectedInstOperands,
42618 /* 118167 */ // GIR_Coverage, 4567,
42619 /* 118167 */ GIR_EraseRootFromParent_Done,
42620 /* 118168 */ // Label 3567: @118168
42621 /* 118168 */ GIM_Reject,
42622 /* 118169 */ // Label 3558: @118169
42623 /* 118169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3568*/ GIMT_Encode4(118222), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4565 //
42624 /* 118176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42625 /* 118179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42626 /* 118183 */ // (fp_to_sint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)
42627 /* 118183 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42628 /* 118186 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42629 /* 118190 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42630 /* 118195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
42631 /* 118198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42632 /* 118200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42633 /* 118202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42634 /* 118205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42635 /* 118211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42636 /* 118217 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42637 /* 118220 */ GIR_RootConstrainSelectedInstOperands,
42638 /* 118221 */ // GIR_Coverage, 4565,
42639 /* 118221 */ GIR_EraseRootFromParent_Done,
42640 /* 118222 */ // Label 3568: @118222
42641 /* 118222 */ GIM_Reject,
42642 /* 118223 */ // Label 3559: @118223
42643 /* 118223 */ GIM_Reject,
42644 /* 118224 */ // Label 54: @118224
42645 /* 118224 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3572*/ GIMT_Encode4(118586),
42646 /* 118235 */ /*GILLT_s32*//*Label 3569*/ GIMT_Encode4(118283), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42647 /* 118271 */ /*GILLT_v8s16*//*Label 3570*/ GIMT_Encode4(118478), GIMT_Encode4(0),
42648 /* 118279 */ /*GILLT_v4s32*//*Label 3571*/ GIMT_Encode4(118532),
42649 /* 118283 */ // Label 3569: @118283
42650 /* 118283 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3576*/ GIMT_Encode4(118477),
42651 /* 118294 */ /*GILLT_s16*//*Label 3573*/ GIMT_Encode4(118306),
42652 /* 118298 */ /*GILLT_s32*//*Label 3574*/ GIMT_Encode4(118363),
42653 /* 118302 */ /*GILLT_s64*//*Label 3575*/ GIMT_Encode4(118420),
42654 /* 118306 */ // Label 3573: @118306
42655 /* 118306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3577*/ GIMT_Encode4(118362), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2659 //
42656 /* 118313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42657 /* 118317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42658 /* 118321 */ // (fp_to_uint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42659 /* 118321 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42660 /* 118324 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH),
42661 /* 118328 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42662 /* 118333 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42663 /* 118337 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42664 /* 118340 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42665 /* 118346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42666 /* 118348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42667 /* 118351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42668 /* 118353 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42669 /* 118356 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42670 /* 118361 */ // GIR_Coverage, 2659,
42671 /* 118361 */ GIR_EraseRootFromParent_Done,
42672 /* 118362 */ // Label 3577: @118362
42673 /* 118362 */ GIM_Reject,
42674 /* 118363 */ // Label 3574: @118363
42675 /* 118363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3578*/ GIMT_Encode4(118419), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2653 //
42676 /* 118370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42677 /* 118374 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42678 /* 118378 */ // (fp_to_uint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42679 /* 118378 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42680 /* 118381 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS),
42681 /* 118385 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42682 /* 118390 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42683 /* 118394 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42684 /* 118397 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42685 /* 118403 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42686 /* 118405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42687 /* 118408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42688 /* 118410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42689 /* 118413 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42690 /* 118418 */ // GIR_Coverage, 2653,
42691 /* 118418 */ GIR_EraseRootFromParent_Done,
42692 /* 118419 */ // Label 3578: @118419
42693 /* 118419 */ GIM_Reject,
42694 /* 118420 */ // Label 3575: @118420
42695 /* 118420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3579*/ GIMT_Encode4(118476), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2647 //
42696 /* 118427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42697 /* 118431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42698 /* 118435 */ // (fp_to_uint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42699 /* 118435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42700 /* 118438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD),
42701 /* 118442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42702 /* 118447 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42703 /* 118451 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42704 /* 118454 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42705 /* 118460 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42706 /* 118462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42707 /* 118465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42708 /* 118467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42709 /* 118470 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42710 /* 118475 */ // GIR_Coverage, 2647,
42711 /* 118475 */ GIR_EraseRootFromParent_Done,
42712 /* 118476 */ // Label 3579: @118476
42713 /* 118476 */ GIM_Reject,
42714 /* 118477 */ // Label 3576: @118477
42715 /* 118477 */ GIM_Reject,
42716 /* 118478 */ // Label 3570: @118478
42717 /* 118478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3580*/ GIMT_Encode4(118531), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4568 //
42718 /* 118485 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42719 /* 118488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42720 /* 118492 */ // (fp_to_uint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)
42721 /* 118492 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42722 /* 118495 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42723 /* 118499 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42724 /* 118504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
42725 /* 118507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42726 /* 118509 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42727 /* 118511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42728 /* 118514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42729 /* 118520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42730 /* 118526 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42731 /* 118529 */ GIR_RootConstrainSelectedInstOperands,
42732 /* 118530 */ // GIR_Coverage, 4568,
42733 /* 118530 */ GIR_EraseRootFromParent_Done,
42734 /* 118531 */ // Label 3580: @118531
42735 /* 118531 */ GIM_Reject,
42736 /* 118532 */ // Label 3571: @118532
42737 /* 118532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3581*/ GIMT_Encode4(118585), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4566 //
42738 /* 118539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42739 /* 118542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42740 /* 118546 */ // (fp_to_uint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)
42741 /* 118546 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42742 /* 118549 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42743 /* 118553 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42744 /* 118558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
42745 /* 118561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42746 /* 118563 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42747 /* 118565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42748 /* 118568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42749 /* 118574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42750 /* 118580 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42751 /* 118583 */ GIR_RootConstrainSelectedInstOperands,
42752 /* 118584 */ // GIR_Coverage, 4566,
42753 /* 118584 */ GIR_EraseRootFromParent_Done,
42754 /* 118585 */ // Label 3581: @118585
42755 /* 118585 */ GIM_Reject,
42756 /* 118586 */ // Label 3572: @118586
42757 /* 118586 */ GIM_Reject,
42758 /* 118587 */ // Label 55: @118587
42759 /* 118587 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3589*/ GIMT_Encode4(119350),
42760 /* 118598 */ /*GILLT_s16*//*Label 3582*/ GIMT_Encode4(118650),
42761 /* 118602 */ /*GILLT_s32*//*Label 3583*/ GIMT_Encode4(118687),
42762 /* 118606 */ /*GILLT_s64*//*Label 3584*/ GIMT_Encode4(118877), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42763 /* 118634 */ /*GILLT_v4s16*//*Label 3585*/ GIMT_Encode4(118914),
42764 /* 118638 */ /*GILLT_v8s16*//*Label 3586*/ GIMT_Encode4(118951),
42765 /* 118642 */ /*GILLT_v2s32*//*Label 3587*/ GIMT_Encode4(119132),
42766 /* 118646 */ /*GILLT_v4s32*//*Label 3588*/ GIMT_Encode4(119169),
42767 /* 118650 */ // Label 3582: @118650
42768 /* 118650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3590*/ GIMT_Encode4(118686), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 678 //
42769 /* 118657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
42770 /* 118660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42771 /* 118664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42772 /* 118668 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
42773 /* 118668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH),
42774 /* 118671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42775 /* 118673 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42776 /* 118675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42777 /* 118678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42778 /* 118684 */ GIR_RootConstrainSelectedInstOperands,
42779 /* 118685 */ // GIR_Coverage, 678,
42780 /* 118685 */ GIR_EraseRootFromParent_Done,
42781 /* 118686 */ // Label 3590: @118686
42782 /* 118686 */ GIM_Reject,
42783 /* 118687 */ // Label 3583: @118687
42784 /* 118687 */ GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(118876),
42785 /* 118692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42786 /* 118695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42787 /* 118699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42788 /* 118703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3592*/ GIMT_Encode4(118728), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 677 //
42789 /* 118710 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
42790 /* 118710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS),
42791 /* 118713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42792 /* 118715 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42793 /* 118717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42794 /* 118720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42795 /* 118726 */ GIR_RootConstrainSelectedInstOperands,
42796 /* 118727 */ // GIR_Coverage, 677,
42797 /* 118727 */ GIR_EraseRootFromParent_Done,
42798 /* 118728 */ // Label 3592: @118728
42799 /* 118728 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3593*/ GIMT_Encode4(118875), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3093 //
42800 /* 118735 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
42801 /* 118735 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
42802 /* 118738 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42803 /* 118742 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42804 /* 118747 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
42805 /* 118749 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
42806 /* 118752 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42807 /* 118756 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42808 /* 118761 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
42809 /* 118764 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42810 /* 118769 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42811 /* 118772 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42812 /* 118776 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42813 /* 118781 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
42814 /* 118784 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
42815 /* 118788 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
42816 /* 118791 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42817 /* 118796 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42818 /* 118801 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42819 /* 118806 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
42820 /* 118809 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
42821 /* 118813 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42822 /* 118818 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42823 /* 118821 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
42824 /* 118824 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42825 /* 118830 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42826 /* 118832 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42827 /* 118835 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42828 /* 118839 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42829 /* 118844 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42830 /* 118847 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42831 /* 118852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42832 /* 118855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42833 /* 118857 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42834 /* 118864 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42835 /* 118869 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42836 /* 118874 */ // GIR_Coverage, 3093,
42837 /* 118874 */ GIR_EraseRootFromParent_Done,
42838 /* 118875 */ // Label 3593: @118875
42839 /* 118875 */ GIM_Reject,
42840 /* 118876 */ // Label 3591: @118876
42841 /* 118876 */ GIM_Reject,
42842 /* 118877 */ // Label 3584: @118877
42843 /* 118877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3594*/ GIMT_Encode4(118913), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 676 //
42844 /* 118884 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42845 /* 118887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42846 /* 118891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42847 /* 118895 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
42848 /* 118895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD),
42849 /* 118898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42850 /* 118900 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
42851 /* 118902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42852 /* 118905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42853 /* 118911 */ GIR_RootConstrainSelectedInstOperands,
42854 /* 118912 */ // GIR_Coverage, 676,
42855 /* 118912 */ GIR_EraseRootFromParent_Done,
42856 /* 118913 */ // Label 3594: @118913
42857 /* 118913 */ GIM_Reject,
42858 /* 118914 */ // Label 3585: @118914
42859 /* 118914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3595*/ GIMT_Encode4(118950), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1678 //
42860 /* 118921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42861 /* 118924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42862 /* 118928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42863 /* 118932 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
42864 /* 118932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd),
42865 /* 118935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42866 /* 118937 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42867 /* 118939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42868 /* 118942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42869 /* 118948 */ GIR_RootConstrainSelectedInstOperands,
42870 /* 118949 */ // GIR_Coverage, 1678,
42871 /* 118949 */ GIR_EraseRootFromParent_Done,
42872 /* 118950 */ // Label 3595: @118950
42873 /* 118950 */ GIM_Reject,
42874 /* 118951 */ // Label 3586: @118951
42875 /* 118951 */ GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(119131),
42876 /* 118956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42877 /* 118959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3597*/ GIMT_Encode4(119043), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4491 //
42878 /* 118966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42879 /* 118970 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42880 /* 118974 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
42881 /* 118978 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
42882 /* 118982 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
42883 /* 118986 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42884 /* 118991 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42885 /* 118996 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42886 /* 118998 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42887 /* 118998 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42888 /* 119001 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42889 /* 119005 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42890 /* 119010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
42891 /* 119013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42892 /* 119015 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
42893 /* 119019 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
42894 /* 119023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42895 /* 119026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42896 /* 119032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42897 /* 119038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42898 /* 119041 */ GIR_RootConstrainSelectedInstOperands,
42899 /* 119042 */ // GIR_Coverage, 4491,
42900 /* 119042 */ GIR_EraseRootFromParent_Done,
42901 /* 119043 */ // Label 3597: @119043
42902 /* 119043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3598*/ GIMT_Encode4(119076), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1679 //
42903 /* 119050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42904 /* 119054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42905 /* 119058 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
42906 /* 119058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq),
42907 /* 119061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42908 /* 119063 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42909 /* 119065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42910 /* 119068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42911 /* 119074 */ GIR_RootConstrainSelectedInstOperands,
42912 /* 119075 */ // GIR_Coverage, 1679,
42913 /* 119075 */ GIR_EraseRootFromParent_Done,
42914 /* 119076 */ // Label 3598: @119076
42915 /* 119076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3599*/ GIMT_Encode4(119130), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4569 //
42916 /* 119083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42917 /* 119087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42918 /* 119091 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
42919 /* 119091 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42920 /* 119094 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42921 /* 119098 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42922 /* 119103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16),
42923 /* 119106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42924 /* 119108 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
42925 /* 119110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42926 /* 119113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42927 /* 119119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42928 /* 119125 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42929 /* 119128 */ GIR_RootConstrainSelectedInstOperands,
42930 /* 119129 */ // GIR_Coverage, 4569,
42931 /* 119129 */ GIR_EraseRootFromParent_Done,
42932 /* 119130 */ // Label 3599: @119130
42933 /* 119130 */ GIM_Reject,
42934 /* 119131 */ // Label 3596: @119131
42935 /* 119131 */ GIM_Reject,
42936 /* 119132 */ // Label 3587: @119132
42937 /* 119132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3600*/ GIMT_Encode4(119168), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1676 //
42938 /* 119139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42939 /* 119142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42940 /* 119146 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42941 /* 119150 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
42942 /* 119150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
42943 /* 119153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42944 /* 119155 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42945 /* 119157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42946 /* 119160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42947 /* 119166 */ GIR_RootConstrainSelectedInstOperands,
42948 /* 119167 */ // GIR_Coverage, 1676,
42949 /* 119167 */ GIR_EraseRootFromParent_Done,
42950 /* 119168 */ // Label 3600: @119168
42951 /* 119168 */ GIM_Reject,
42952 /* 119169 */ // Label 3588: @119169
42953 /* 119169 */ GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(119349),
42954 /* 119174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42955 /* 119177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3602*/ GIMT_Encode4(119261), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4492 //
42956 /* 119184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42957 /* 119188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42958 /* 119192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
42959 /* 119196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42960 /* 119200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
42961 /* 119204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42962 /* 119209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42963 /* 119214 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42964 /* 119216 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
42965 /* 119216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42966 /* 119219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42967 /* 119223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42968 /* 119228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
42969 /* 119231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42970 /* 119233 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
42971 /* 119237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
42972 /* 119241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42973 /* 119244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42974 /* 119250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42975 /* 119256 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42976 /* 119259 */ GIR_RootConstrainSelectedInstOperands,
42977 /* 119260 */ // GIR_Coverage, 4492,
42978 /* 119260 */ GIR_EraseRootFromParent_Done,
42979 /* 119261 */ // Label 3602: @119261
42980 /* 119261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3603*/ GIMT_Encode4(119294), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1677 //
42981 /* 119268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42982 /* 119272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42983 /* 119276 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
42984 /* 119276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq),
42985 /* 119279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42986 /* 119281 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42987 /* 119283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42988 /* 119286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42989 /* 119292 */ GIR_RootConstrainSelectedInstOperands,
42990 /* 119293 */ // GIR_Coverage, 1677,
42991 /* 119293 */ GIR_EraseRootFromParent_Done,
42992 /* 119294 */ // Label 3603: @119294
42993 /* 119294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3604*/ GIMT_Encode4(119348), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4571 //
42994 /* 119301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42995 /* 119305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42996 /* 119309 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
42997 /* 119309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42998 /* 119312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42999 /* 119316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43000 /* 119321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32),
43001 /* 119324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43002 /* 119326 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
43003 /* 119328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43004 /* 119331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43005 /* 119337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43006 /* 119343 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43007 /* 119346 */ GIR_RootConstrainSelectedInstOperands,
43008 /* 119347 */ // GIR_Coverage, 4571,
43009 /* 119347 */ GIR_EraseRootFromParent_Done,
43010 /* 119348 */ // Label 3604: @119348
43011 /* 119348 */ GIM_Reject,
43012 /* 119349 */ // Label 3601: @119349
43013 /* 119349 */ GIM_Reject,
43014 /* 119350 */ // Label 3589: @119350
43015 /* 119350 */ GIM_Reject,
43016 /* 119351 */ // Label 56: @119351
43017 /* 119351 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3612*/ GIMT_Encode4(119931),
43018 /* 119362 */ /*GILLT_s16*//*Label 3605*/ GIMT_Encode4(119414),
43019 /* 119366 */ /*GILLT_s32*//*Label 3606*/ GIMT_Encode4(119447),
43020 /* 119370 */ /*GILLT_s64*//*Label 3607*/ GIMT_Encode4(119480), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43021 /* 119398 */ /*GILLT_v4s16*//*Label 3608*/ GIMT_Encode4(119513),
43022 /* 119402 */ /*GILLT_v8s16*//*Label 3609*/ GIMT_Encode4(119546),
43023 /* 119406 */ /*GILLT_v2s32*//*Label 3610*/ GIMT_Encode4(119722),
43024 /* 119410 */ /*GILLT_v4s32*//*Label 3611*/ GIMT_Encode4(119755),
43025 /* 119414 */ // Label 3605: @119414
43026 /* 119414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3613*/ GIMT_Encode4(119446), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 665 //
43027 /* 119421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43028 /* 119424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43029 /* 119427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43030 /* 119431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43031 /* 119435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43032 /* 119439 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43033 /* 119439 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH),
43034 /* 119444 */ GIR_RootConstrainSelectedInstOperands,
43035 /* 119445 */ // GIR_Coverage, 665,
43036 /* 119445 */ GIR_Done,
43037 /* 119446 */ // Label 3613: @119446
43038 /* 119446 */ GIM_Reject,
43039 /* 119447 */ // Label 3606: @119447
43040 /* 119447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3614*/ GIMT_Encode4(119479), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 667 //
43041 /* 119454 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43042 /* 119457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43043 /* 119460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43044 /* 119464 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43045 /* 119468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43046 /* 119472 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43047 /* 119472 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS),
43048 /* 119477 */ GIR_RootConstrainSelectedInstOperands,
43049 /* 119478 */ // GIR_Coverage, 667,
43050 /* 119478 */ GIR_Done,
43051 /* 119479 */ // Label 3614: @119479
43052 /* 119479 */ GIM_Reject,
43053 /* 119480 */ // Label 3607: @119480
43054 /* 119480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3615*/ GIMT_Encode4(119512), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 669 //
43055 /* 119487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43056 /* 119490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43057 /* 119493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43058 /* 119497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43059 /* 119501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43060 /* 119505 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43061 /* 119505 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD),
43062 /* 119510 */ GIR_RootConstrainSelectedInstOperands,
43063 /* 119511 */ // GIR_Coverage, 669,
43064 /* 119511 */ GIR_Done,
43065 /* 119512 */ // Label 3615: @119512
43066 /* 119512 */ GIM_Reject,
43067 /* 119513 */ // Label 3608: @119513
43068 /* 119513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3616*/ GIMT_Encode4(119545), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1397 //
43069 /* 119520 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43070 /* 119523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43071 /* 119526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43072 /* 119530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43073 /* 119534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43074 /* 119538 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43075 /* 119538 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh),
43076 /* 119543 */ GIR_RootConstrainSelectedInstOperands,
43077 /* 119544 */ // GIR_Coverage, 1397,
43078 /* 119544 */ GIR_Done,
43079 /* 119545 */ // Label 3616: @119545
43080 /* 119545 */ GIM_Reject,
43081 /* 119546 */ // Label 3609: @119546
43082 /* 119546 */ GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(119721),
43083 /* 119551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43084 /* 119554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43085 /* 119557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3618*/ GIMT_Encode4(119634), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4586 //
43086 /* 119564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43087 /* 119568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43088 /* 119572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
43089 /* 119576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
43090 /* 119580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43091 /* 119585 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
43092 /* 119589 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
43093 /* 119593 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
43094 /* 119597 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43095 /* 119602 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43096 /* 119604 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
43097 /* 119604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
43098 /* 119607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43099 /* 119609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
43100 /* 119613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
43101 /* 119617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43102 /* 119620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43103 /* 119626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43104 /* 119632 */ GIR_RootConstrainSelectedInstOperands,
43105 /* 119633 */ // GIR_Coverage, 4586,
43106 /* 119633 */ GIR_EraseRootFromParent_Done,
43107 /* 119634 */ // Label 3618: @119634
43108 /* 119634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3619*/ GIMT_Encode4(119660), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1398 //
43109 /* 119641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43110 /* 119645 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43111 /* 119649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43112 /* 119653 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43113 /* 119653 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh),
43114 /* 119658 */ GIR_RootConstrainSelectedInstOperands,
43115 /* 119659 */ // GIR_Coverage, 1398,
43116 /* 119659 */ GIR_Done,
43117 /* 119660 */ // Label 3619: @119660
43118 /* 119660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3620*/ GIMT_Encode4(119720), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3686 //
43119 /* 119667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43120 /* 119671 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43121 /* 119675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43122 /* 119679 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
43123 /* 119679 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43124 /* 119682 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43125 /* 119686 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43126 /* 119691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
43127 /* 119694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43128 /* 119696 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43129 /* 119698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43130 /* 119700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43131 /* 119703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43132 /* 119709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43133 /* 119715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43134 /* 119718 */ GIR_RootConstrainSelectedInstOperands,
43135 /* 119719 */ // GIR_Coverage, 3686,
43136 /* 119719 */ GIR_EraseRootFromParent_Done,
43137 /* 119720 */ // Label 3620: @119720
43138 /* 119720 */ GIM_Reject,
43139 /* 119721 */ // Label 3617: @119721
43140 /* 119721 */ GIM_Reject,
43141 /* 119722 */ // Label 3610: @119722
43142 /* 119722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3621*/ GIMT_Encode4(119754), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1395 //
43143 /* 119729 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43144 /* 119732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43145 /* 119735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43146 /* 119739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43147 /* 119743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43148 /* 119747 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43149 /* 119747 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf),
43150 /* 119752 */ GIR_RootConstrainSelectedInstOperands,
43151 /* 119753 */ // GIR_Coverage, 1395,
43152 /* 119753 */ GIR_Done,
43153 /* 119754 */ // Label 3621: @119754
43154 /* 119754 */ GIM_Reject,
43155 /* 119755 */ // Label 3611: @119755
43156 /* 119755 */ GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(119930),
43157 /* 119760 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43158 /* 119763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43159 /* 119766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3623*/ GIMT_Encode4(119843), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4583 //
43160 /* 119773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43161 /* 119777 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43162 /* 119781 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
43163 /* 119785 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43164 /* 119789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43165 /* 119794 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
43166 /* 119798 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
43167 /* 119802 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
43168 /* 119806 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43169 /* 119811 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43170 /* 119813 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
43171 /* 119813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
43172 /* 119816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43173 /* 119818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
43174 /* 119822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
43175 /* 119826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43176 /* 119829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43177 /* 119835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43178 /* 119841 */ GIR_RootConstrainSelectedInstOperands,
43179 /* 119842 */ // GIR_Coverage, 4583,
43180 /* 119842 */ GIR_EraseRootFromParent_Done,
43181 /* 119843 */ // Label 3623: @119843
43182 /* 119843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3624*/ GIMT_Encode4(119869), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1396 //
43183 /* 119850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43184 /* 119854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43185 /* 119858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43186 /* 119862 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43187 /* 119862 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf),
43188 /* 119867 */ GIR_RootConstrainSelectedInstOperands,
43189 /* 119868 */ // GIR_Coverage, 1396,
43190 /* 119868 */ GIR_Done,
43191 /* 119869 */ // Label 3624: @119869
43192 /* 119869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3625*/ GIMT_Encode4(119929), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3681 //
43193 /* 119876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43194 /* 119880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43195 /* 119884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43196 /* 119888 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
43197 /* 119888 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43198 /* 119891 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43199 /* 119895 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43200 /* 119900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
43201 /* 119903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43202 /* 119905 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43203 /* 119907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43204 /* 119909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43205 /* 119912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43206 /* 119918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43207 /* 119924 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43208 /* 119927 */ GIR_RootConstrainSelectedInstOperands,
43209 /* 119928 */ // GIR_Coverage, 3681,
43210 /* 119928 */ GIR_EraseRootFromParent_Done,
43211 /* 119929 */ // Label 3625: @119929
43212 /* 119929 */ GIM_Reject,
43213 /* 119930 */ // Label 3622: @119930
43214 /* 119930 */ GIM_Reject,
43215 /* 119931 */ // Label 3612: @119931
43216 /* 119931 */ GIM_Reject,
43217 /* 119932 */ // Label 57: @119932
43218 /* 119932 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3633*/ GIMT_Encode4(120512),
43219 /* 119943 */ /*GILLT_s16*//*Label 3626*/ GIMT_Encode4(119995),
43220 /* 119947 */ /*GILLT_s32*//*Label 3627*/ GIMT_Encode4(120028),
43221 /* 119951 */ /*GILLT_s64*//*Label 3628*/ GIMT_Encode4(120061), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43222 /* 119979 */ /*GILLT_v4s16*//*Label 3629*/ GIMT_Encode4(120094),
43223 /* 119983 */ /*GILLT_v8s16*//*Label 3630*/ GIMT_Encode4(120127),
43224 /* 119987 */ /*GILLT_v2s32*//*Label 3631*/ GIMT_Encode4(120303),
43225 /* 119991 */ /*GILLT_v4s32*//*Label 3632*/ GIMT_Encode4(120336),
43226 /* 119995 */ // Label 3626: @119995
43227 /* 119995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3634*/ GIMT_Encode4(120027), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 659 //
43228 /* 120002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43229 /* 120005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43230 /* 120008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43231 /* 120012 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43232 /* 120016 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43233 /* 120020 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43234 /* 120020 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH),
43235 /* 120025 */ GIR_RootConstrainSelectedInstOperands,
43236 /* 120026 */ // GIR_Coverage, 659,
43237 /* 120026 */ GIR_Done,
43238 /* 120027 */ // Label 3634: @120027
43239 /* 120027 */ GIM_Reject,
43240 /* 120028 */ // Label 3627: @120028
43241 /* 120028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3635*/ GIMT_Encode4(120060), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 661 //
43242 /* 120035 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43243 /* 120038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43244 /* 120041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43245 /* 120045 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43246 /* 120049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43247 /* 120053 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43248 /* 120053 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS),
43249 /* 120058 */ GIR_RootConstrainSelectedInstOperands,
43250 /* 120059 */ // GIR_Coverage, 661,
43251 /* 120059 */ GIR_Done,
43252 /* 120060 */ // Label 3635: @120060
43253 /* 120060 */ GIM_Reject,
43254 /* 120061 */ // Label 3628: @120061
43255 /* 120061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3636*/ GIMT_Encode4(120093), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 663 //
43256 /* 120068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43257 /* 120071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43258 /* 120074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43259 /* 120078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43260 /* 120082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43261 /* 120086 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43262 /* 120086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD),
43263 /* 120091 */ GIR_RootConstrainSelectedInstOperands,
43264 /* 120092 */ // GIR_Coverage, 663,
43265 /* 120092 */ GIR_Done,
43266 /* 120093 */ // Label 3636: @120093
43267 /* 120093 */ GIM_Reject,
43268 /* 120094 */ // Label 3629: @120094
43269 /* 120094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3637*/ GIMT_Encode4(120126), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1377 //
43270 /* 120101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43271 /* 120104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43272 /* 120107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43273 /* 120111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43274 /* 120115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43275 /* 120119 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43276 /* 120119 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh),
43277 /* 120124 */ GIR_RootConstrainSelectedInstOperands,
43278 /* 120125 */ // GIR_Coverage, 1377,
43279 /* 120125 */ GIR_Done,
43280 /* 120126 */ // Label 3637: @120126
43281 /* 120126 */ GIM_Reject,
43282 /* 120127 */ // Label 3630: @120127
43283 /* 120127 */ GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(120302),
43284 /* 120132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43285 /* 120135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43286 /* 120138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3639*/ GIMT_Encode4(120215), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4580 //
43287 /* 120145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43288 /* 120149 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43289 /* 120153 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
43290 /* 120157 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
43291 /* 120161 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43292 /* 120166 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
43293 /* 120170 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
43294 /* 120174 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
43295 /* 120178 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43296 /* 120183 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43297 /* 120185 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
43298 /* 120185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
43299 /* 120188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43300 /* 120190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
43301 /* 120194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
43302 /* 120198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43303 /* 120201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43304 /* 120207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43305 /* 120213 */ GIR_RootConstrainSelectedInstOperands,
43306 /* 120214 */ // GIR_Coverage, 4580,
43307 /* 120214 */ GIR_EraseRootFromParent_Done,
43308 /* 120215 */ // Label 3639: @120215
43309 /* 120215 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3640*/ GIMT_Encode4(120241), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1378 //
43310 /* 120222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43311 /* 120226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43312 /* 120230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43313 /* 120234 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43314 /* 120234 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh),
43315 /* 120239 */ GIR_RootConstrainSelectedInstOperands,
43316 /* 120240 */ // GIR_Coverage, 1378,
43317 /* 120240 */ GIR_Done,
43318 /* 120241 */ // Label 3640: @120241
43319 /* 120241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3641*/ GIMT_Encode4(120301), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3676 //
43320 /* 120248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43321 /* 120252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43322 /* 120256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43323 /* 120260 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
43324 /* 120260 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43325 /* 120263 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43326 /* 120267 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43327 /* 120272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
43328 /* 120275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43329 /* 120277 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43330 /* 120279 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43331 /* 120281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43332 /* 120284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43333 /* 120290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43334 /* 120296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43335 /* 120299 */ GIR_RootConstrainSelectedInstOperands,
43336 /* 120300 */ // GIR_Coverage, 3676,
43337 /* 120300 */ GIR_EraseRootFromParent_Done,
43338 /* 120301 */ // Label 3641: @120301
43339 /* 120301 */ GIM_Reject,
43340 /* 120302 */ // Label 3638: @120302
43341 /* 120302 */ GIM_Reject,
43342 /* 120303 */ // Label 3631: @120303
43343 /* 120303 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3642*/ GIMT_Encode4(120335), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1375 //
43344 /* 120310 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43345 /* 120313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43346 /* 120316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43347 /* 120320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43348 /* 120324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43349 /* 120328 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43350 /* 120328 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf),
43351 /* 120333 */ GIR_RootConstrainSelectedInstOperands,
43352 /* 120334 */ // GIR_Coverage, 1375,
43353 /* 120334 */ GIR_Done,
43354 /* 120335 */ // Label 3642: @120335
43355 /* 120335 */ GIM_Reject,
43356 /* 120336 */ // Label 3632: @120336
43357 /* 120336 */ GIM_Try, /*On fail goto*//*Label 3643*/ GIMT_Encode4(120511),
43358 /* 120341 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43359 /* 120344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43360 /* 120347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3644*/ GIMT_Encode4(120424), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4577 //
43361 /* 120354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43362 /* 120358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43363 /* 120362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
43364 /* 120366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43365 /* 120370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43366 /* 120375 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
43367 /* 120379 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
43368 /* 120383 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
43369 /* 120387 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43370 /* 120392 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43371 /* 120394 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
43372 /* 120394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
43373 /* 120397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43374 /* 120399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
43375 /* 120403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
43376 /* 120407 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43377 /* 120410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43378 /* 120416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43379 /* 120422 */ GIR_RootConstrainSelectedInstOperands,
43380 /* 120423 */ // GIR_Coverage, 4577,
43381 /* 120423 */ GIR_EraseRootFromParent_Done,
43382 /* 120424 */ // Label 3644: @120424
43383 /* 120424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3645*/ GIMT_Encode4(120450), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1376 //
43384 /* 120431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43385 /* 120435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43386 /* 120439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43387 /* 120443 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43388 /* 120443 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf),
43389 /* 120448 */ GIR_RootConstrainSelectedInstOperands,
43390 /* 120449 */ // GIR_Coverage, 1376,
43391 /* 120449 */ GIR_Done,
43392 /* 120450 */ // Label 3645: @120450
43393 /* 120450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3646*/ GIMT_Encode4(120510), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3419 //
43394 /* 120457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43395 /* 120461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43396 /* 120465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43397 /* 120469 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
43398 /* 120469 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43399 /* 120472 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43400 /* 120476 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43401 /* 120481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
43402 /* 120484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43403 /* 120486 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43404 /* 120488 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43405 /* 120490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43406 /* 120493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43407 /* 120499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43408 /* 120505 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43409 /* 120508 */ GIR_RootConstrainSelectedInstOperands,
43410 /* 120509 */ // GIR_Coverage, 3419,
43411 /* 120509 */ GIR_EraseRootFromParent_Done,
43412 /* 120510 */ // Label 3646: @120510
43413 /* 120510 */ GIM_Reject,
43414 /* 120511 */ // Label 3643: @120511
43415 /* 120511 */ GIM_Reject,
43416 /* 120512 */ // Label 3633: @120512
43417 /* 120512 */ GIM_Reject,
43418 /* 120513 */ // Label 58: @120513
43419 /* 120513 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3653*/ GIMT_Encode4(121240),
43420 /* 120524 */ /*GILLT_s16*//*Label 3647*/ GIMT_Encode4(120576),
43421 /* 120528 */ /*GILLT_s32*//*Label 3648*/ GIMT_Encode4(120816), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43422 /* 120560 */ /*GILLT_v4s16*//*Label 3649*/ GIMT_Encode4(121056),
43423 /* 120564 */ /*GILLT_v8s16*//*Label 3650*/ GIMT_Encode4(121102),
43424 /* 120568 */ /*GILLT_v2s32*//*Label 3651*/ GIMT_Encode4(121148),
43425 /* 120572 */ /*GILLT_v4s32*//*Label 3652*/ GIMT_Encode4(121194),
43426 /* 120576 */ // Label 3647: @120576
43427 /* 120576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3654*/ GIMT_Encode4(120815), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3096 //
43428 /* 120583 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43429 /* 120586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43430 /* 120589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43431 /* 120593 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43432 /* 120597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43433 /* 120601 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43434 /* 120601 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
43435 /* 120604 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43436 /* 120608 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43437 /* 120613 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43438 /* 120615 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
43439 /* 120618 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43440 /* 120622 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43441 /* 120627 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43442 /* 120630 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43443 /* 120635 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
43444 /* 120638 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43445 /* 120642 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43446 /* 120647 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43447 /* 120650 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43448 /* 120654 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43449 /* 120657 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43450 /* 120662 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43451 /* 120667 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43452 /* 120672 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
43453 /* 120675 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43454 /* 120679 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43455 /* 120684 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43456 /* 120686 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
43457 /* 120689 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43458 /* 120693 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43459 /* 120698 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43460 /* 120701 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43461 /* 120706 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
43462 /* 120709 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43463 /* 120713 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43464 /* 120718 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43465 /* 120721 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43466 /* 120725 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43467 /* 120728 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43468 /* 120733 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43469 /* 120738 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43470 /* 120743 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43471 /* 120746 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
43472 /* 120750 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43473 /* 120755 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43474 /* 120758 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43475 /* 120761 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43476 /* 120764 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43477 /* 120770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43478 /* 120772 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
43479 /* 120775 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43480 /* 120779 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43481 /* 120784 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43482 /* 120787 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43483 /* 120792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43484 /* 120795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43485 /* 120797 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43486 /* 120804 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43487 /* 120809 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43488 /* 120814 */ // GIR_Coverage, 3096,
43489 /* 120814 */ GIR_EraseRootFromParent_Done,
43490 /* 120815 */ // Label 3654: @120815
43491 /* 120815 */ GIM_Reject,
43492 /* 120816 */ // Label 3648: @120816
43493 /* 120816 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3655*/ GIMT_Encode4(121055), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3098 //
43494 /* 120823 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43495 /* 120826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43496 /* 120829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43497 /* 120833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43498 /* 120837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43499 /* 120841 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43500 /* 120841 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
43501 /* 120844 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43502 /* 120848 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43503 /* 120853 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43504 /* 120855 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
43505 /* 120858 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43506 /* 120862 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43507 /* 120867 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43508 /* 120870 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43509 /* 120875 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
43510 /* 120878 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43511 /* 120882 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43512 /* 120887 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43513 /* 120890 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43514 /* 120894 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43515 /* 120897 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43516 /* 120902 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43517 /* 120907 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43518 /* 120912 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43519 /* 120915 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43520 /* 120919 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43521 /* 120924 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43522 /* 120926 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43523 /* 120929 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43524 /* 120933 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43525 /* 120938 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43526 /* 120941 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43527 /* 120946 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43528 /* 120949 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43529 /* 120953 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43530 /* 120958 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43531 /* 120961 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43532 /* 120965 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43533 /* 120968 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43534 /* 120973 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43535 /* 120978 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43536 /* 120983 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43537 /* 120986 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
43538 /* 120990 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43539 /* 120995 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43540 /* 120998 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43541 /* 121001 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43542 /* 121004 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43543 /* 121010 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43544 /* 121012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43545 /* 121015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43546 /* 121019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43547 /* 121024 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43548 /* 121027 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43549 /* 121032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43550 /* 121035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43551 /* 121037 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43552 /* 121044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43553 /* 121049 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43554 /* 121054 */ // GIR_Coverage, 3098,
43555 /* 121054 */ GIR_EraseRootFromParent_Done,
43556 /* 121055 */ // Label 3655: @121055
43557 /* 121055 */ GIM_Reject,
43558 /* 121056 */ // Label 3649: @121056
43559 /* 121056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3656*/ GIMT_Encode4(121101), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1393 //
43560 /* 121063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43561 /* 121066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43562 /* 121069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43563 /* 121073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43564 /* 121077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43565 /* 121081 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43566 /* 121081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
43567 /* 121084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43568 /* 121086 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43569 /* 121088 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43570 /* 121090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43571 /* 121093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43572 /* 121099 */ GIR_RootConstrainSelectedInstOperands,
43573 /* 121100 */ // GIR_Coverage, 1393,
43574 /* 121100 */ GIR_EraseRootFromParent_Done,
43575 /* 121101 */ // Label 3656: @121101
43576 /* 121101 */ GIM_Reject,
43577 /* 121102 */ // Label 3650: @121102
43578 /* 121102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3657*/ GIMT_Encode4(121147), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1394 //
43579 /* 121109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43580 /* 121112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43581 /* 121115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43582 /* 121119 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43583 /* 121123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43584 /* 121127 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43585 /* 121127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq),
43586 /* 121130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43587 /* 121132 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43588 /* 121134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43589 /* 121136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43590 /* 121139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43591 /* 121145 */ GIR_RootConstrainSelectedInstOperands,
43592 /* 121146 */ // GIR_Coverage, 1394,
43593 /* 121146 */ GIR_EraseRootFromParent_Done,
43594 /* 121147 */ // Label 3657: @121147
43595 /* 121147 */ GIM_Reject,
43596 /* 121148 */ // Label 3651: @121148
43597 /* 121148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3658*/ GIMT_Encode4(121193), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1391 //
43598 /* 121155 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43599 /* 121158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43600 /* 121161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43601 /* 121165 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43602 /* 121169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43603 /* 121173 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43604 /* 121173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
43605 /* 121176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43606 /* 121178 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43607 /* 121180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43608 /* 121182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43609 /* 121185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43610 /* 121191 */ GIR_RootConstrainSelectedInstOperands,
43611 /* 121192 */ // GIR_Coverage, 1391,
43612 /* 121192 */ GIR_EraseRootFromParent_Done,
43613 /* 121193 */ // Label 3658: @121193
43614 /* 121193 */ GIM_Reject,
43615 /* 121194 */ // Label 3652: @121194
43616 /* 121194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3659*/ GIMT_Encode4(121239), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1392 //
43617 /* 121201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43618 /* 121204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43619 /* 121207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43620 /* 121211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43621 /* 121215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43622 /* 121219 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43623 /* 121219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq),
43624 /* 121222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43625 /* 121224 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43626 /* 121226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43627 /* 121228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43628 /* 121231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43629 /* 121237 */ GIR_RootConstrainSelectedInstOperands,
43630 /* 121238 */ // GIR_Coverage, 1392,
43631 /* 121238 */ GIR_EraseRootFromParent_Done,
43632 /* 121239 */ // Label 3659: @121239
43633 /* 121239 */ GIM_Reject,
43634 /* 121240 */ // Label 3653: @121240
43635 /* 121240 */ GIM_Reject,
43636 /* 121241 */ // Label 59: @121241
43637 /* 121241 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3666*/ GIMT_Encode4(121968),
43638 /* 121252 */ /*GILLT_s16*//*Label 3660*/ GIMT_Encode4(121304),
43639 /* 121256 */ /*GILLT_s32*//*Label 3661*/ GIMT_Encode4(121544), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43640 /* 121288 */ /*GILLT_v4s16*//*Label 3662*/ GIMT_Encode4(121784),
43641 /* 121292 */ /*GILLT_v8s16*//*Label 3663*/ GIMT_Encode4(121830),
43642 /* 121296 */ /*GILLT_v2s32*//*Label 3664*/ GIMT_Encode4(121876),
43643 /* 121300 */ /*GILLT_v4s32*//*Label 3665*/ GIMT_Encode4(121922),
43644 /* 121304 */ // Label 3660: @121304
43645 /* 121304 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3667*/ GIMT_Encode4(121543), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3095 //
43646 /* 121311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43647 /* 121314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43648 /* 121317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43649 /* 121321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43650 /* 121325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43651 /* 121329 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43652 /* 121329 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
43653 /* 121332 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43654 /* 121336 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43655 /* 121341 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43656 /* 121343 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
43657 /* 121346 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43658 /* 121350 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43659 /* 121355 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43660 /* 121358 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43661 /* 121363 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
43662 /* 121366 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43663 /* 121370 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43664 /* 121375 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43665 /* 121378 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43666 /* 121382 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43667 /* 121385 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43668 /* 121390 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43669 /* 121395 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43670 /* 121400 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
43671 /* 121403 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43672 /* 121407 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43673 /* 121412 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43674 /* 121414 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
43675 /* 121417 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43676 /* 121421 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43677 /* 121426 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43678 /* 121429 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43679 /* 121434 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
43680 /* 121437 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43681 /* 121441 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43682 /* 121446 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43683 /* 121449 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43684 /* 121453 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43685 /* 121456 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43686 /* 121461 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43687 /* 121466 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43688 /* 121471 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43689 /* 121474 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
43690 /* 121478 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43691 /* 121483 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43692 /* 121486 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43693 /* 121489 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43694 /* 121492 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43695 /* 121498 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43696 /* 121500 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
43697 /* 121503 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43698 /* 121507 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43699 /* 121512 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43700 /* 121515 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43701 /* 121520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43702 /* 121523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43703 /* 121525 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43704 /* 121532 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43705 /* 121537 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43706 /* 121542 */ // GIR_Coverage, 3095,
43707 /* 121542 */ GIR_EraseRootFromParent_Done,
43708 /* 121543 */ // Label 3667: @121543
43709 /* 121543 */ GIM_Reject,
43710 /* 121544 */ // Label 3661: @121544
43711 /* 121544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3668*/ GIMT_Encode4(121783), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3097 //
43712 /* 121551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43713 /* 121554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43714 /* 121557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43715 /* 121561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43716 /* 121565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43717 /* 121569 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43718 /* 121569 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
43719 /* 121572 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43720 /* 121576 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43721 /* 121581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43722 /* 121583 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
43723 /* 121586 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43724 /* 121590 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43725 /* 121595 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43726 /* 121598 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43727 /* 121603 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
43728 /* 121606 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43729 /* 121610 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43730 /* 121615 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43731 /* 121618 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43732 /* 121622 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43733 /* 121625 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43734 /* 121630 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43735 /* 121635 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43736 /* 121640 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43737 /* 121643 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43738 /* 121647 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43739 /* 121652 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43740 /* 121654 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43741 /* 121657 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43742 /* 121661 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43743 /* 121666 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43744 /* 121669 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43745 /* 121674 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43746 /* 121677 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43747 /* 121681 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43748 /* 121686 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43749 /* 121689 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43750 /* 121693 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43751 /* 121696 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43752 /* 121701 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43753 /* 121706 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43754 /* 121711 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43755 /* 121714 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
43756 /* 121718 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43757 /* 121723 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43758 /* 121726 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43759 /* 121729 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43760 /* 121732 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43761 /* 121738 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43762 /* 121740 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43763 /* 121743 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43764 /* 121747 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43765 /* 121752 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43766 /* 121755 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43767 /* 121760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43768 /* 121763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43769 /* 121765 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43770 /* 121772 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43771 /* 121777 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43772 /* 121782 */ // GIR_Coverage, 3097,
43773 /* 121782 */ GIR_EraseRootFromParent_Done,
43774 /* 121783 */ // Label 3668: @121783
43775 /* 121783 */ GIM_Reject,
43776 /* 121784 */ // Label 3662: @121784
43777 /* 121784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3669*/ GIMT_Encode4(121829), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1373 //
43778 /* 121791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43779 /* 121794 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43780 /* 121797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43781 /* 121801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43782 /* 121805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43783 /* 121809 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43784 /* 121809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
43785 /* 121812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43786 /* 121814 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43787 /* 121816 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43788 /* 121818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43789 /* 121821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43790 /* 121827 */ GIR_RootConstrainSelectedInstOperands,
43791 /* 121828 */ // GIR_Coverage, 1373,
43792 /* 121828 */ GIR_EraseRootFromParent_Done,
43793 /* 121829 */ // Label 3669: @121829
43794 /* 121829 */ GIM_Reject,
43795 /* 121830 */ // Label 3663: @121830
43796 /* 121830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3670*/ GIMT_Encode4(121875), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1374 //
43797 /* 121837 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43798 /* 121840 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43799 /* 121843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43800 /* 121847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43801 /* 121851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43802 /* 121855 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43803 /* 121855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq),
43804 /* 121858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43805 /* 121860 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43806 /* 121862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43807 /* 121864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43808 /* 121867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43809 /* 121873 */ GIR_RootConstrainSelectedInstOperands,
43810 /* 121874 */ // GIR_Coverage, 1374,
43811 /* 121874 */ GIR_EraseRootFromParent_Done,
43812 /* 121875 */ // Label 3670: @121875
43813 /* 121875 */ GIM_Reject,
43814 /* 121876 */ // Label 3664: @121876
43815 /* 121876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3671*/ GIMT_Encode4(121921), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1371 //
43816 /* 121883 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43817 /* 121886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43818 /* 121889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43819 /* 121893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43820 /* 121897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43821 /* 121901 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43822 /* 121901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
43823 /* 121904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43824 /* 121906 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43825 /* 121908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43826 /* 121910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43827 /* 121913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43828 /* 121919 */ GIR_RootConstrainSelectedInstOperands,
43829 /* 121920 */ // GIR_Coverage, 1371,
43830 /* 121920 */ GIR_EraseRootFromParent_Done,
43831 /* 121921 */ // Label 3671: @121921
43832 /* 121921 */ GIM_Reject,
43833 /* 121922 */ // Label 3665: @121922
43834 /* 121922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3672*/ GIMT_Encode4(121967), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1372 //
43835 /* 121929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43836 /* 121932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43837 /* 121935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43838 /* 121939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43839 /* 121943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43840 /* 121947 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43841 /* 121947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq),
43842 /* 121950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43843 /* 121952 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43844 /* 121954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43845 /* 121956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43846 /* 121959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43847 /* 121965 */ GIR_RootConstrainSelectedInstOperands,
43848 /* 121966 */ // GIR_Coverage, 1372,
43849 /* 121966 */ GIR_EraseRootFromParent_Done,
43850 /* 121967 */ // Label 3672: @121967
43851 /* 121967 */ GIM_Reject,
43852 /* 121968 */ // Label 3666: @121968
43853 /* 121968 */ GIM_Reject,
43854 /* 121969 */ // Label 60: @121969
43855 /* 121969 */ GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(122001), // Rule ID 2800 //
43856 /* 121974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43857 /* 121977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
43858 /* 121981 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] })
43859 /* 121981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
43860 /* 121984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
43861 /* 121986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43862 /* 121989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43863 /* 121995 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43864 /* 121999 */ GIR_RootConstrainSelectedInstOperands,
43865 /* 122000 */ // GIR_Coverage, 2800,
43866 /* 122000 */ GIR_EraseRootFromParent_Done,
43867 /* 122001 */ // Label 3673: @122001
43868 /* 122001 */ GIM_Reject,
43869 /* 122002 */ // Label 61: @122002
43870 /* 122002 */ GIM_Try, /*On fail goto*//*Label 3674*/ GIMT_Encode4(122037), // Rule ID 2801 //
43871 /* 122007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43872 /* 122010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
43873 /* 122014 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
43874 /* 122014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
43875 /* 122017 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt
43876 /* 122019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43877 /* 122022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43878 /* 122028 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
43879 /* 122031 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43880 /* 122035 */ GIR_RootConstrainSelectedInstOperands,
43881 /* 122036 */ // GIR_Coverage, 2801,
43882 /* 122036 */ GIR_EraseRootFromParent_Done,
43883 /* 122037 */ // Label 3674: @122037
43884 /* 122037 */ GIM_Reject,
43885 /* 122038 */ // Label 62: @122038
43886 /* 122038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3675*/ GIMT_Encode4(122101), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2802 //
43887 /* 122045 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] }))
43888 /* 122045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43889 /* 122048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi),
43890 /* 122052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43891 /* 122057 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
43892 /* 122060 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43893 /* 122063 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43894 /* 122069 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43895 /* 122075 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43896 /* 122077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
43897 /* 122080 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43898 /* 122083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43899 /* 122086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43900 /* 122092 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
43901 /* 122095 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43902 /* 122099 */ GIR_RootConstrainSelectedInstOperands,
43903 /* 122100 */ // GIR_Coverage, 2802,
43904 /* 122100 */ GIR_EraseRootFromParent_Done,
43905 /* 122101 */ // Label 3675: @122101
43906 /* 122101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3676*/ GIMT_Encode4(122164), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 2803 //
43907 /* 122108 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
43908 /* 122108 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43909 /* 122111 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
43910 /* 122115 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43911 /* 122120 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
43912 /* 122126 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
43913 /* 122129 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43914 /* 122132 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43915 /* 122138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43916 /* 122140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
43917 /* 122143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43918 /* 122146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43919 /* 122149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43920 /* 122155 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
43921 /* 122158 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43922 /* 122162 */ GIR_RootConstrainSelectedInstOperands,
43923 /* 122163 */ // GIR_Coverage, 2803,
43924 /* 122163 */ GIR_EraseRootFromParent_Done,
43925 /* 122164 */ // Label 3676: @122164
43926 /* 122164 */ GIM_Reject,
43927 /* 122165 */ // Label 63: @122165
43928 /* 122165 */ GIM_Try, /*On fail goto*//*Label 3677*/ GIMT_Encode4(122197), // Rule ID 2804 //
43929 /* 122170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43930 /* 122173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
43931 /* 122177 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] })
43932 /* 122177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
43933 /* 122180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
43934 /* 122182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43935 /* 122185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43936 /* 122191 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43937 /* 122195 */ GIR_RootConstrainSelectedInstOperands,
43938 /* 122196 */ // GIR_Coverage, 2804,
43939 /* 122196 */ GIR_EraseRootFromParent_Done,
43940 /* 122197 */ // Label 3677: @122197
43941 /* 122197 */ GIM_Reject,
43942 /* 122198 */ // Label 64: @122198
43943 /* 122198 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3684*/ GIMT_Encode4(122707),
43944 /* 122209 */ /*GILLT_v8s8*//*Label 3678*/ GIMT_Encode4(122233),
43945 /* 122213 */ /*GILLT_v16s8*//*Label 3679*/ GIMT_Encode4(122279),
43946 /* 122217 */ /*GILLT_v4s16*//*Label 3680*/ GIMT_Encode4(122391),
43947 /* 122221 */ /*GILLT_v8s16*//*Label 3681*/ GIMT_Encode4(122437),
43948 /* 122225 */ /*GILLT_v2s32*//*Label 3682*/ GIMT_Encode4(122549),
43949 /* 122229 */ /*GILLT_v4s32*//*Label 3683*/ GIMT_Encode4(122595),
43950 /* 122233 */ // Label 3678: @122233
43951 /* 122233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3685*/ GIMT_Encode4(122278), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1383 //
43952 /* 122240 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
43953 /* 122243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
43954 /* 122246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43955 /* 122250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43956 /* 122254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43957 /* 122258 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
43958 /* 122258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8),
43959 /* 122261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43960 /* 122263 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43961 /* 122265 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43962 /* 122267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43963 /* 122270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43964 /* 122276 */ GIR_RootConstrainSelectedInstOperands,
43965 /* 122277 */ // GIR_Coverage, 1383,
43966 /* 122277 */ GIR_EraseRootFromParent_Done,
43967 /* 122278 */ // Label 3685: @122278
43968 /* 122278 */ GIM_Reject,
43969 /* 122279 */ // Label 3679: @122279
43970 /* 122279 */ GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(122390),
43971 /* 122284 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
43972 /* 122287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
43973 /* 122290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3687*/ GIMT_Encode4(122329), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1384 //
43974 /* 122297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43975 /* 122301 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43976 /* 122305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43977 /* 122309 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
43978 /* 122309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8),
43979 /* 122312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43980 /* 122314 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43981 /* 122316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43982 /* 122318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43983 /* 122321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43984 /* 122327 */ GIR_RootConstrainSelectedInstOperands,
43985 /* 122328 */ // GIR_Coverage, 1384,
43986 /* 122328 */ GIR_EraseRootFromParent_Done,
43987 /* 122329 */ // Label 3687: @122329
43988 /* 122329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3688*/ GIMT_Encode4(122389), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3691 //
43989 /* 122336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43990 /* 122340 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43991 /* 122344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43992 /* 122348 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
43993 /* 122348 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43994 /* 122351 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43995 /* 122355 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43996 /* 122360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8),
43997 /* 122363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43998 /* 122365 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43999 /* 122367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44000 /* 122369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44001 /* 122372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44002 /* 122378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44003 /* 122384 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44004 /* 122387 */ GIR_RootConstrainSelectedInstOperands,
44005 /* 122388 */ // GIR_Coverage, 3691,
44006 /* 122388 */ GIR_EraseRootFromParent_Done,
44007 /* 122389 */ // Label 3688: @122389
44008 /* 122389 */ GIM_Reject,
44009 /* 122390 */ // Label 3686: @122390
44010 /* 122390 */ GIM_Reject,
44011 /* 122391 */ // Label 3680: @122391
44012 /* 122391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3689*/ GIMT_Encode4(122436), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1379 //
44013 /* 122398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44014 /* 122401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44015 /* 122404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44016 /* 122408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44017 /* 122412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44018 /* 122416 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44019 /* 122416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16),
44020 /* 122419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44021 /* 122421 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44022 /* 122423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44023 /* 122425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44024 /* 122428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44025 /* 122434 */ GIR_RootConstrainSelectedInstOperands,
44026 /* 122435 */ // GIR_Coverage, 1379,
44027 /* 122435 */ GIR_EraseRootFromParent_Done,
44028 /* 122436 */ // Label 3689: @122436
44029 /* 122436 */ GIM_Reject,
44030 /* 122437 */ // Label 3681: @122437
44031 /* 122437 */ GIM_Try, /*On fail goto*//*Label 3690*/ GIMT_Encode4(122548),
44032 /* 122442 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44033 /* 122445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44034 /* 122448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3691*/ GIMT_Encode4(122487), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1381 //
44035 /* 122455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44036 /* 122459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44037 /* 122463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44038 /* 122467 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44039 /* 122467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16),
44040 /* 122470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44041 /* 122472 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44042 /* 122474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44043 /* 122476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44044 /* 122479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44045 /* 122485 */ GIR_RootConstrainSelectedInstOperands,
44046 /* 122486 */ // GIR_Coverage, 1381,
44047 /* 122486 */ GIR_EraseRootFromParent_Done,
44048 /* 122487 */ // Label 3691: @122487
44049 /* 122487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3692*/ GIMT_Encode4(122547), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3694 //
44050 /* 122494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44051 /* 122498 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44052 /* 122502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44053 /* 122506 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44054 /* 122506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44055 /* 122509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44056 /* 122513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44057 /* 122518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16),
44058 /* 122521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44059 /* 122523 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44060 /* 122525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44061 /* 122527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44062 /* 122530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44063 /* 122536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44064 /* 122542 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44065 /* 122545 */ GIR_RootConstrainSelectedInstOperands,
44066 /* 122546 */ // GIR_Coverage, 3694,
44067 /* 122546 */ GIR_EraseRootFromParent_Done,
44068 /* 122547 */ // Label 3692: @122547
44069 /* 122547 */ GIM_Reject,
44070 /* 122548 */ // Label 3690: @122548
44071 /* 122548 */ GIM_Reject,
44072 /* 122549 */ // Label 3682: @122549
44073 /* 122549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3693*/ GIMT_Encode4(122594), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1380 //
44074 /* 122556 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44075 /* 122559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44076 /* 122562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44077 /* 122566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44078 /* 122570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44079 /* 122574 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44080 /* 122574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32),
44081 /* 122577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44082 /* 122579 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44083 /* 122581 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44084 /* 122583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44085 /* 122586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44086 /* 122592 */ GIR_RootConstrainSelectedInstOperands,
44087 /* 122593 */ // GIR_Coverage, 1380,
44088 /* 122593 */ GIR_EraseRootFromParent_Done,
44089 /* 122594 */ // Label 3693: @122594
44090 /* 122594 */ GIM_Reject,
44091 /* 122595 */ // Label 3683: @122595
44092 /* 122595 */ GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(122706),
44093 /* 122600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44094 /* 122603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44095 /* 122606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3695*/ GIMT_Encode4(122645), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1382 //
44096 /* 122613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44097 /* 122617 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44098 /* 122621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44099 /* 122625 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44100 /* 122625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32),
44101 /* 122628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44102 /* 122630 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44103 /* 122632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44104 /* 122634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44105 /* 122637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44106 /* 122643 */ GIR_RootConstrainSelectedInstOperands,
44107 /* 122644 */ // GIR_Coverage, 1382,
44108 /* 122644 */ GIR_EraseRootFromParent_Done,
44109 /* 122645 */ // Label 3695: @122645
44110 /* 122645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3696*/ GIMT_Encode4(122705), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3697 //
44111 /* 122652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44112 /* 122656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44113 /* 122660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44114 /* 122664 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44115 /* 122664 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44116 /* 122667 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44117 /* 122671 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44118 /* 122676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32),
44119 /* 122679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44120 /* 122681 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44121 /* 122683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44122 /* 122685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44123 /* 122688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44124 /* 122694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44125 /* 122700 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44126 /* 122703 */ GIR_RootConstrainSelectedInstOperands,
44127 /* 122704 */ // GIR_Coverage, 3697,
44128 /* 122704 */ GIR_EraseRootFromParent_Done,
44129 /* 122705 */ // Label 3696: @122705
44130 /* 122705 */ GIM_Reject,
44131 /* 122706 */ // Label 3694: @122706
44132 /* 122706 */ GIM_Reject,
44133 /* 122707 */ // Label 3684: @122707
44134 /* 122707 */ GIM_Reject,
44135 /* 122708 */ // Label 65: @122708
44136 /* 122708 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3703*/ GIMT_Encode4(123217),
44137 /* 122719 */ /*GILLT_v8s8*//*Label 3697*/ GIMT_Encode4(122743),
44138 /* 122723 */ /*GILLT_v16s8*//*Label 3698*/ GIMT_Encode4(122789),
44139 /* 122727 */ /*GILLT_v4s16*//*Label 3699*/ GIMT_Encode4(122901),
44140 /* 122731 */ /*GILLT_v8s16*//*Label 3700*/ GIMT_Encode4(122947),
44141 /* 122735 */ /*GILLT_v2s32*//*Label 3701*/ GIMT_Encode4(123059),
44142 /* 122739 */ /*GILLT_v4s32*//*Label 3702*/ GIMT_Encode4(123105),
44143 /* 122743 */ // Label 3697: @122743
44144 /* 122743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3704*/ GIMT_Encode4(122788), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1363 //
44145 /* 122750 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44146 /* 122753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
44147 /* 122756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44148 /* 122760 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44149 /* 122764 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44150 /* 122768 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44151 /* 122768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8),
44152 /* 122771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44153 /* 122773 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44154 /* 122775 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44155 /* 122777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44156 /* 122780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44157 /* 122786 */ GIR_RootConstrainSelectedInstOperands,
44158 /* 122787 */ // GIR_Coverage, 1363,
44159 /* 122787 */ GIR_EraseRootFromParent_Done,
44160 /* 122788 */ // Label 3704: @122788
44161 /* 122788 */ GIM_Reject,
44162 /* 122789 */ // Label 3698: @122789
44163 /* 122789 */ GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(122900),
44164 /* 122794 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44165 /* 122797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44166 /* 122800 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3706*/ GIMT_Encode4(122839), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1364 //
44167 /* 122807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44168 /* 122811 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44169 /* 122815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44170 /* 122819 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
44171 /* 122819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8),
44172 /* 122822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44173 /* 122824 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44174 /* 122826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44175 /* 122828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44176 /* 122831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44177 /* 122837 */ GIR_RootConstrainSelectedInstOperands,
44178 /* 122838 */ // GIR_Coverage, 1364,
44179 /* 122838 */ GIR_EraseRootFromParent_Done,
44180 /* 122839 */ // Label 3706: @122839
44181 /* 122839 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3707*/ GIMT_Encode4(122899), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3709 //
44182 /* 122846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44183 /* 122850 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44184 /* 122854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44185 /* 122858 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
44186 /* 122858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44187 /* 122861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44188 /* 122865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44189 /* 122870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8),
44190 /* 122873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44191 /* 122875 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44192 /* 122877 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44193 /* 122879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44194 /* 122882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44195 /* 122888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44196 /* 122894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44197 /* 122897 */ GIR_RootConstrainSelectedInstOperands,
44198 /* 122898 */ // GIR_Coverage, 3709,
44199 /* 122898 */ GIR_EraseRootFromParent_Done,
44200 /* 122899 */ // Label 3707: @122899
44201 /* 122899 */ GIM_Reject,
44202 /* 122900 */ // Label 3705: @122900
44203 /* 122900 */ GIM_Reject,
44204 /* 122901 */ // Label 3699: @122901
44205 /* 122901 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3708*/ GIMT_Encode4(122946), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1359 //
44206 /* 122908 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44207 /* 122911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44208 /* 122914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44209 /* 122918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44210 /* 122922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44211 /* 122926 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44212 /* 122926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16),
44213 /* 122929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44214 /* 122931 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44215 /* 122933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44216 /* 122935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44217 /* 122938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44218 /* 122944 */ GIR_RootConstrainSelectedInstOperands,
44219 /* 122945 */ // GIR_Coverage, 1359,
44220 /* 122945 */ GIR_EraseRootFromParent_Done,
44221 /* 122946 */ // Label 3708: @122946
44222 /* 122946 */ GIM_Reject,
44223 /* 122947 */ // Label 3700: @122947
44224 /* 122947 */ GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(123058),
44225 /* 122952 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44226 /* 122955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44227 /* 122958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3710*/ GIMT_Encode4(122997), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1361 //
44228 /* 122965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44229 /* 122969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44230 /* 122973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44231 /* 122977 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44232 /* 122977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16),
44233 /* 122980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44234 /* 122982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44235 /* 122984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44236 /* 122986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44237 /* 122989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44238 /* 122995 */ GIR_RootConstrainSelectedInstOperands,
44239 /* 122996 */ // GIR_Coverage, 1361,
44240 /* 122996 */ GIR_EraseRootFromParent_Done,
44241 /* 122997 */ // Label 3710: @122997
44242 /* 122997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3711*/ GIMT_Encode4(123057), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3712 //
44243 /* 123004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44244 /* 123008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44245 /* 123012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44246 /* 123016 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44247 /* 123016 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44248 /* 123019 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44249 /* 123023 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44250 /* 123028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16),
44251 /* 123031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44252 /* 123033 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44253 /* 123035 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44254 /* 123037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44255 /* 123040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44256 /* 123046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44257 /* 123052 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44258 /* 123055 */ GIR_RootConstrainSelectedInstOperands,
44259 /* 123056 */ // GIR_Coverage, 3712,
44260 /* 123056 */ GIR_EraseRootFromParent_Done,
44261 /* 123057 */ // Label 3711: @123057
44262 /* 123057 */ GIM_Reject,
44263 /* 123058 */ // Label 3709: @123058
44264 /* 123058 */ GIM_Reject,
44265 /* 123059 */ // Label 3701: @123059
44266 /* 123059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3712*/ GIMT_Encode4(123104), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1360 //
44267 /* 123066 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44268 /* 123069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44269 /* 123072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44270 /* 123076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44271 /* 123080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44272 /* 123084 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44273 /* 123084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32),
44274 /* 123087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44275 /* 123089 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44276 /* 123091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44277 /* 123093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44278 /* 123096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44279 /* 123102 */ GIR_RootConstrainSelectedInstOperands,
44280 /* 123103 */ // GIR_Coverage, 1360,
44281 /* 123103 */ GIR_EraseRootFromParent_Done,
44282 /* 123104 */ // Label 3712: @123104
44283 /* 123104 */ GIM_Reject,
44284 /* 123105 */ // Label 3702: @123105
44285 /* 123105 */ GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(123216),
44286 /* 123110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44287 /* 123113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44288 /* 123116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3714*/ GIMT_Encode4(123155), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1362 //
44289 /* 123123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44290 /* 123127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44291 /* 123131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44292 /* 123135 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44293 /* 123135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32),
44294 /* 123138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44295 /* 123140 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44296 /* 123142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44297 /* 123144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44298 /* 123147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44299 /* 123153 */ GIR_RootConstrainSelectedInstOperands,
44300 /* 123154 */ // GIR_Coverage, 1362,
44301 /* 123154 */ GIR_EraseRootFromParent_Done,
44302 /* 123155 */ // Label 3714: @123155
44303 /* 123155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3715*/ GIMT_Encode4(123215), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3715 //
44304 /* 123162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44305 /* 123166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44306 /* 123170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44307 /* 123174 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44308 /* 123174 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44309 /* 123177 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44310 /* 123181 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44311 /* 123186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32),
44312 /* 123189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44313 /* 123191 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44314 /* 123193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44315 /* 123195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44316 /* 123198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44317 /* 123204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44318 /* 123210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44319 /* 123213 */ GIR_RootConstrainSelectedInstOperands,
44320 /* 123214 */ // GIR_Coverage, 3715,
44321 /* 123214 */ GIR_EraseRootFromParent_Done,
44322 /* 123215 */ // Label 3715: @123215
44323 /* 123215 */ GIM_Reject,
44324 /* 123216 */ // Label 3713: @123216
44325 /* 123216 */ GIM_Reject,
44326 /* 123217 */ // Label 3703: @123217
44327 /* 123217 */ GIM_Reject,
44328 /* 123218 */ // Label 66: @123218
44329 /* 123218 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3722*/ GIMT_Encode4(124105),
44330 /* 123229 */ /*GILLT_v8s8*//*Label 3716*/ GIMT_Encode4(123253),
44331 /* 123233 */ /*GILLT_v16s8*//*Label 3717*/ GIMT_Encode4(123299),
44332 /* 123237 */ /*GILLT_v4s16*//*Label 3718*/ GIMT_Encode4(123537),
44333 /* 123241 */ /*GILLT_v8s16*//*Label 3719*/ GIMT_Encode4(123583),
44334 /* 123245 */ /*GILLT_v2s32*//*Label 3720*/ GIMT_Encode4(123821),
44335 /* 123249 */ /*GILLT_v4s32*//*Label 3721*/ GIMT_Encode4(123867),
44336 /* 123253 */ // Label 3716: @123253
44337 /* 123253 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3723*/ GIMT_Encode4(123298), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1389 //
44338 /* 123260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44339 /* 123263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
44340 /* 123266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44341 /* 123270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44342 /* 123274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44343 /* 123278 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44344 /* 123278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8),
44345 /* 123281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44346 /* 123283 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44347 /* 123285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44348 /* 123287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44349 /* 123290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44350 /* 123296 */ GIR_RootConstrainSelectedInstOperands,
44351 /* 123297 */ // GIR_Coverage, 1389,
44352 /* 123297 */ GIR_EraseRootFromParent_Done,
44353 /* 123298 */ // Label 3723: @123298
44354 /* 123298 */ GIM_Reject,
44355 /* 123299 */ // Label 3717: @123299
44356 /* 123299 */ GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(123536),
44357 /* 123304 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44358 /* 123307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44359 /* 123310 */ GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(123436),
44360 /* 123315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44361 /* 123319 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3726*/ GIMT_Encode4(123377), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6661 //
44362 /* 123326 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44363 /* 123330 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44364 /* 123334 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44365 /* 123338 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44366 /* 123343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44367 /* 123347 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44368 /* 123349 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44369 /* 123349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
44370 /* 123352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44371 /* 123354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44372 /* 123356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44373 /* 123360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44374 /* 123363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44375 /* 123369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44376 /* 123375 */ GIR_RootConstrainSelectedInstOperands,
44377 /* 123376 */ // GIR_Coverage, 6661,
44378 /* 123376 */ GIR_EraseRootFromParent_Done,
44379 /* 123377 */ // Label 3726: @123377
44380 /* 123377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3727*/ GIMT_Encode4(123435), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4096 //
44381 /* 123384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44382 /* 123388 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44383 /* 123392 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44384 /* 123396 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44385 /* 123400 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44386 /* 123405 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44387 /* 123407 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44388 /* 123407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
44389 /* 123410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44390 /* 123412 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44391 /* 123414 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44392 /* 123418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44393 /* 123421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44394 /* 123427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44395 /* 123433 */ GIR_RootConstrainSelectedInstOperands,
44396 /* 123434 */ // GIR_Coverage, 4096,
44397 /* 123434 */ GIR_EraseRootFromParent_Done,
44398 /* 123435 */ // Label 3727: @123435
44399 /* 123435 */ GIM_Reject,
44400 /* 123436 */ // Label 3725: @123436
44401 /* 123436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3728*/ GIMT_Encode4(123475), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1390 //
44402 /* 123443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44403 /* 123447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44404 /* 123451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44405 /* 123455 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
44406 /* 123455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8),
44407 /* 123458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44408 /* 123460 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44409 /* 123462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44410 /* 123464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44411 /* 123467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44412 /* 123473 */ GIR_RootConstrainSelectedInstOperands,
44413 /* 123474 */ // GIR_Coverage, 1390,
44414 /* 123474 */ GIR_EraseRootFromParent_Done,
44415 /* 123475 */ // Label 3728: @123475
44416 /* 123475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3729*/ GIMT_Encode4(123535), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3700 //
44417 /* 123482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44418 /* 123486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44419 /* 123490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44420 /* 123494 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
44421 /* 123494 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44422 /* 123497 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44423 /* 123501 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44424 /* 123506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8),
44425 /* 123509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44426 /* 123511 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44427 /* 123513 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44428 /* 123515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44429 /* 123518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44430 /* 123524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44431 /* 123530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44432 /* 123533 */ GIR_RootConstrainSelectedInstOperands,
44433 /* 123534 */ // GIR_Coverage, 3700,
44434 /* 123534 */ GIR_EraseRootFromParent_Done,
44435 /* 123535 */ // Label 3729: @123535
44436 /* 123535 */ GIM_Reject,
44437 /* 123536 */ // Label 3724: @123536
44438 /* 123536 */ GIM_Reject,
44439 /* 123537 */ // Label 3718: @123537
44440 /* 123537 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3730*/ GIMT_Encode4(123582), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1385 //
44441 /* 123544 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44442 /* 123547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44443 /* 123550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44444 /* 123554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44445 /* 123558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44446 /* 123562 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44447 /* 123562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16),
44448 /* 123565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44449 /* 123567 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44450 /* 123569 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44451 /* 123571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44452 /* 123574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44453 /* 123580 */ GIR_RootConstrainSelectedInstOperands,
44454 /* 123581 */ // GIR_Coverage, 1385,
44455 /* 123581 */ GIR_EraseRootFromParent_Done,
44456 /* 123582 */ // Label 3730: @123582
44457 /* 123582 */ GIM_Reject,
44458 /* 123583 */ // Label 3719: @123583
44459 /* 123583 */ GIM_Try, /*On fail goto*//*Label 3731*/ GIMT_Encode4(123820),
44460 /* 123588 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44461 /* 123591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44462 /* 123594 */ GIM_Try, /*On fail goto*//*Label 3732*/ GIMT_Encode4(123720),
44463 /* 123599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44464 /* 123603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3733*/ GIMT_Encode4(123661), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6662 //
44465 /* 123610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44466 /* 123614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44467 /* 123618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44468 /* 123622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44469 /* 123627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44470 /* 123631 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44471 /* 123633 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44472 /* 123633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
44473 /* 123636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44474 /* 123638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44475 /* 123640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44476 /* 123644 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44477 /* 123647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44478 /* 123653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44479 /* 123659 */ GIR_RootConstrainSelectedInstOperands,
44480 /* 123660 */ // GIR_Coverage, 6662,
44481 /* 123660 */ GIR_EraseRootFromParent_Done,
44482 /* 123661 */ // Label 3733: @123661
44483 /* 123661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3734*/ GIMT_Encode4(123719), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4098 //
44484 /* 123668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44485 /* 123672 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44486 /* 123676 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44487 /* 123680 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44488 /* 123684 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44489 /* 123689 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44490 /* 123691 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44491 /* 123691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
44492 /* 123694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44493 /* 123696 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44494 /* 123698 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44495 /* 123702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44496 /* 123705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44497 /* 123711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44498 /* 123717 */ GIR_RootConstrainSelectedInstOperands,
44499 /* 123718 */ // GIR_Coverage, 4098,
44500 /* 123718 */ GIR_EraseRootFromParent_Done,
44501 /* 123719 */ // Label 3734: @123719
44502 /* 123719 */ GIM_Reject,
44503 /* 123720 */ // Label 3732: @123720
44504 /* 123720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3735*/ GIMT_Encode4(123759), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1387 //
44505 /* 123727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44506 /* 123731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44507 /* 123735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44508 /* 123739 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44509 /* 123739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16),
44510 /* 123742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44511 /* 123744 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44512 /* 123746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44513 /* 123748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44514 /* 123751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44515 /* 123757 */ GIR_RootConstrainSelectedInstOperands,
44516 /* 123758 */ // GIR_Coverage, 1387,
44517 /* 123758 */ GIR_EraseRootFromParent_Done,
44518 /* 123759 */ // Label 3735: @123759
44519 /* 123759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3736*/ GIMT_Encode4(123819), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3703 //
44520 /* 123766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44521 /* 123770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44522 /* 123774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44523 /* 123778 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44524 /* 123778 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44525 /* 123781 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44526 /* 123785 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44527 /* 123790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16),
44528 /* 123793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44529 /* 123795 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44530 /* 123797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44531 /* 123799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44532 /* 123802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44533 /* 123808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44534 /* 123814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44535 /* 123817 */ GIR_RootConstrainSelectedInstOperands,
44536 /* 123818 */ // GIR_Coverage, 3703,
44537 /* 123818 */ GIR_EraseRootFromParent_Done,
44538 /* 123819 */ // Label 3736: @123819
44539 /* 123819 */ GIM_Reject,
44540 /* 123820 */ // Label 3731: @123820
44541 /* 123820 */ GIM_Reject,
44542 /* 123821 */ // Label 3720: @123821
44543 /* 123821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3737*/ GIMT_Encode4(123866), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1386 //
44544 /* 123828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44545 /* 123831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44546 /* 123834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44547 /* 123838 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44548 /* 123842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44549 /* 123846 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44550 /* 123846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32),
44551 /* 123849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44552 /* 123851 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44553 /* 123853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44554 /* 123855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44555 /* 123858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44556 /* 123864 */ GIR_RootConstrainSelectedInstOperands,
44557 /* 123865 */ // GIR_Coverage, 1386,
44558 /* 123865 */ GIR_EraseRootFromParent_Done,
44559 /* 123866 */ // Label 3737: @123866
44560 /* 123866 */ GIM_Reject,
44561 /* 123867 */ // Label 3721: @123867
44562 /* 123867 */ GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(124104),
44563 /* 123872 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44564 /* 123875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44565 /* 123878 */ GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(124004),
44566 /* 123883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44567 /* 123887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3740*/ GIMT_Encode4(123945), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6663 //
44568 /* 123894 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44569 /* 123898 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44570 /* 123902 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44571 /* 123906 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44572 /* 123911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44573 /* 123915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44574 /* 123917 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44575 /* 123917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
44576 /* 123920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44577 /* 123922 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44578 /* 123924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44579 /* 123928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44580 /* 123931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44581 /* 123937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44582 /* 123943 */ GIR_RootConstrainSelectedInstOperands,
44583 /* 123944 */ // GIR_Coverage, 6663,
44584 /* 123944 */ GIR_EraseRootFromParent_Done,
44585 /* 123945 */ // Label 3740: @123945
44586 /* 123945 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3741*/ GIMT_Encode4(124003), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4100 //
44587 /* 123952 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44588 /* 123956 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44589 /* 123960 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44590 /* 123964 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44591 /* 123968 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44592 /* 123973 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44593 /* 123975 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44594 /* 123975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
44595 /* 123978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44596 /* 123980 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44597 /* 123982 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44598 /* 123986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44599 /* 123989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44600 /* 123995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44601 /* 124001 */ GIR_RootConstrainSelectedInstOperands,
44602 /* 124002 */ // GIR_Coverage, 4100,
44603 /* 124002 */ GIR_EraseRootFromParent_Done,
44604 /* 124003 */ // Label 3741: @124003
44605 /* 124003 */ GIM_Reject,
44606 /* 124004 */ // Label 3739: @124004
44607 /* 124004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3742*/ GIMT_Encode4(124043), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1388 //
44608 /* 124011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44609 /* 124015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44610 /* 124019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44611 /* 124023 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44612 /* 124023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32),
44613 /* 124026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44614 /* 124028 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44615 /* 124030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44616 /* 124032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44617 /* 124035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44618 /* 124041 */ GIR_RootConstrainSelectedInstOperands,
44619 /* 124042 */ // GIR_Coverage, 1388,
44620 /* 124042 */ GIR_EraseRootFromParent_Done,
44621 /* 124043 */ // Label 3742: @124043
44622 /* 124043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3743*/ GIMT_Encode4(124103), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3706 //
44623 /* 124050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44624 /* 124054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44625 /* 124058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44626 /* 124062 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44627 /* 124062 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44628 /* 124065 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44629 /* 124069 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44630 /* 124074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32),
44631 /* 124077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44632 /* 124079 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44633 /* 124081 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44634 /* 124083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44635 /* 124086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44636 /* 124092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44637 /* 124098 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44638 /* 124101 */ GIR_RootConstrainSelectedInstOperands,
44639 /* 124102 */ // GIR_Coverage, 3706,
44640 /* 124102 */ GIR_EraseRootFromParent_Done,
44641 /* 124103 */ // Label 3743: @124103
44642 /* 124103 */ GIM_Reject,
44643 /* 124104 */ // Label 3738: @124104
44644 /* 124104 */ GIM_Reject,
44645 /* 124105 */ // Label 3722: @124105
44646 /* 124105 */ GIM_Reject,
44647 /* 124106 */ // Label 67: @124106
44648 /* 124106 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3750*/ GIMT_Encode4(124993),
44649 /* 124117 */ /*GILLT_v8s8*//*Label 3744*/ GIMT_Encode4(124141),
44650 /* 124121 */ /*GILLT_v16s8*//*Label 3745*/ GIMT_Encode4(124187),
44651 /* 124125 */ /*GILLT_v4s16*//*Label 3746*/ GIMT_Encode4(124425),
44652 /* 124129 */ /*GILLT_v8s16*//*Label 3747*/ GIMT_Encode4(124471),
44653 /* 124133 */ /*GILLT_v2s32*//*Label 3748*/ GIMT_Encode4(124709),
44654 /* 124137 */ /*GILLT_v4s32*//*Label 3749*/ GIMT_Encode4(124755),
44655 /* 124141 */ // Label 3744: @124141
44656 /* 124141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3751*/ GIMT_Encode4(124186), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1369 //
44657 /* 124148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44658 /* 124151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
44659 /* 124154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44660 /* 124158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44661 /* 124162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44662 /* 124166 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44663 /* 124166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8),
44664 /* 124169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44665 /* 124171 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44666 /* 124173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44667 /* 124175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44668 /* 124178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44669 /* 124184 */ GIR_RootConstrainSelectedInstOperands,
44670 /* 124185 */ // GIR_Coverage, 1369,
44671 /* 124185 */ GIR_EraseRootFromParent_Done,
44672 /* 124186 */ // Label 3751: @124186
44673 /* 124186 */ GIM_Reject,
44674 /* 124187 */ // Label 3745: @124187
44675 /* 124187 */ GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(124424),
44676 /* 124192 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44677 /* 124195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44678 /* 124198 */ GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(124324),
44679 /* 124203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44680 /* 124207 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3754*/ GIMT_Encode4(124265), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6664 //
44681 /* 124214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44682 /* 124218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44683 /* 124222 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44684 /* 124226 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44685 /* 124231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44686 /* 124235 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44687 /* 124237 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44688 /* 124237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
44689 /* 124240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44690 /* 124242 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44691 /* 124244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44692 /* 124248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44693 /* 124251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44694 /* 124257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44695 /* 124263 */ GIR_RootConstrainSelectedInstOperands,
44696 /* 124264 */ // GIR_Coverage, 6664,
44697 /* 124264 */ GIR_EraseRootFromParent_Done,
44698 /* 124265 */ // Label 3754: @124265
44699 /* 124265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3755*/ GIMT_Encode4(124323), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4102 //
44700 /* 124272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44701 /* 124276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44702 /* 124280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44703 /* 124284 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44704 /* 124288 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44705 /* 124293 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44706 /* 124295 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44707 /* 124295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
44708 /* 124298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44709 /* 124300 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44710 /* 124302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44711 /* 124306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44712 /* 124309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44713 /* 124315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44714 /* 124321 */ GIR_RootConstrainSelectedInstOperands,
44715 /* 124322 */ // GIR_Coverage, 4102,
44716 /* 124322 */ GIR_EraseRootFromParent_Done,
44717 /* 124323 */ // Label 3755: @124323
44718 /* 124323 */ GIM_Reject,
44719 /* 124324 */ // Label 3753: @124324
44720 /* 124324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3756*/ GIMT_Encode4(124363), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1370 //
44721 /* 124331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44722 /* 124335 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44723 /* 124339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44724 /* 124343 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
44725 /* 124343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8),
44726 /* 124346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44727 /* 124348 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44728 /* 124350 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44729 /* 124352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44730 /* 124355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44731 /* 124361 */ GIR_RootConstrainSelectedInstOperands,
44732 /* 124362 */ // GIR_Coverage, 1370,
44733 /* 124362 */ GIR_EraseRootFromParent_Done,
44734 /* 124363 */ // Label 3756: @124363
44735 /* 124363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3757*/ GIMT_Encode4(124423), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3718 //
44736 /* 124370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44737 /* 124374 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44738 /* 124378 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44739 /* 124382 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
44740 /* 124382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44741 /* 124385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44742 /* 124389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44743 /* 124394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8),
44744 /* 124397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44745 /* 124399 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44746 /* 124401 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44747 /* 124403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44748 /* 124406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44749 /* 124412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44750 /* 124418 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44751 /* 124421 */ GIR_RootConstrainSelectedInstOperands,
44752 /* 124422 */ // GIR_Coverage, 3718,
44753 /* 124422 */ GIR_EraseRootFromParent_Done,
44754 /* 124423 */ // Label 3757: @124423
44755 /* 124423 */ GIM_Reject,
44756 /* 124424 */ // Label 3752: @124424
44757 /* 124424 */ GIM_Reject,
44758 /* 124425 */ // Label 3746: @124425
44759 /* 124425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3758*/ GIMT_Encode4(124470), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1365 //
44760 /* 124432 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44761 /* 124435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44762 /* 124438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44763 /* 124442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44764 /* 124446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44765 /* 124450 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44766 /* 124450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16),
44767 /* 124453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44768 /* 124455 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44769 /* 124457 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44770 /* 124459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44771 /* 124462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44772 /* 124468 */ GIR_RootConstrainSelectedInstOperands,
44773 /* 124469 */ // GIR_Coverage, 1365,
44774 /* 124469 */ GIR_EraseRootFromParent_Done,
44775 /* 124470 */ // Label 3758: @124470
44776 /* 124470 */ GIM_Reject,
44777 /* 124471 */ // Label 3747: @124471
44778 /* 124471 */ GIM_Try, /*On fail goto*//*Label 3759*/ GIMT_Encode4(124708),
44779 /* 124476 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44780 /* 124479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44781 /* 124482 */ GIM_Try, /*On fail goto*//*Label 3760*/ GIMT_Encode4(124608),
44782 /* 124487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44783 /* 124491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3761*/ GIMT_Encode4(124549), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6665 //
44784 /* 124498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44785 /* 124502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44786 /* 124506 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44787 /* 124510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44788 /* 124515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44789 /* 124519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44790 /* 124521 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44791 /* 124521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
44792 /* 124524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44793 /* 124526 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44794 /* 124528 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44795 /* 124532 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44796 /* 124535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44797 /* 124541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44798 /* 124547 */ GIR_RootConstrainSelectedInstOperands,
44799 /* 124548 */ // GIR_Coverage, 6665,
44800 /* 124548 */ GIR_EraseRootFromParent_Done,
44801 /* 124549 */ // Label 3761: @124549
44802 /* 124549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3762*/ GIMT_Encode4(124607), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4104 //
44803 /* 124556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44804 /* 124560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44805 /* 124564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44806 /* 124568 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44807 /* 124572 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44808 /* 124577 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44809 /* 124579 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44810 /* 124579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
44811 /* 124582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44812 /* 124584 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44813 /* 124586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44814 /* 124590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44815 /* 124593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44816 /* 124599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44817 /* 124605 */ GIR_RootConstrainSelectedInstOperands,
44818 /* 124606 */ // GIR_Coverage, 4104,
44819 /* 124606 */ GIR_EraseRootFromParent_Done,
44820 /* 124607 */ // Label 3762: @124607
44821 /* 124607 */ GIM_Reject,
44822 /* 124608 */ // Label 3760: @124608
44823 /* 124608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3763*/ GIMT_Encode4(124647), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1367 //
44824 /* 124615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44825 /* 124619 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44826 /* 124623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44827 /* 124627 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44828 /* 124627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16),
44829 /* 124630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44830 /* 124632 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44831 /* 124634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44832 /* 124636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44833 /* 124639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44834 /* 124645 */ GIR_RootConstrainSelectedInstOperands,
44835 /* 124646 */ // GIR_Coverage, 1367,
44836 /* 124646 */ GIR_EraseRootFromParent_Done,
44837 /* 124647 */ // Label 3763: @124647
44838 /* 124647 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3764*/ GIMT_Encode4(124707), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3721 //
44839 /* 124654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44840 /* 124658 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44841 /* 124662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44842 /* 124666 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44843 /* 124666 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44844 /* 124669 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44845 /* 124673 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44846 /* 124678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16),
44847 /* 124681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44848 /* 124683 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44849 /* 124685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44850 /* 124687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44851 /* 124690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44852 /* 124696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44853 /* 124702 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44854 /* 124705 */ GIR_RootConstrainSelectedInstOperands,
44855 /* 124706 */ // GIR_Coverage, 3721,
44856 /* 124706 */ GIR_EraseRootFromParent_Done,
44857 /* 124707 */ // Label 3764: @124707
44858 /* 124707 */ GIM_Reject,
44859 /* 124708 */ // Label 3759: @124708
44860 /* 124708 */ GIM_Reject,
44861 /* 124709 */ // Label 3748: @124709
44862 /* 124709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3765*/ GIMT_Encode4(124754), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1366 //
44863 /* 124716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44864 /* 124719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44865 /* 124722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44866 /* 124726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44867 /* 124730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44868 /* 124734 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44869 /* 124734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32),
44870 /* 124737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44871 /* 124739 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44872 /* 124741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44873 /* 124743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44874 /* 124746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44875 /* 124752 */ GIR_RootConstrainSelectedInstOperands,
44876 /* 124753 */ // GIR_Coverage, 1366,
44877 /* 124753 */ GIR_EraseRootFromParent_Done,
44878 /* 124754 */ // Label 3765: @124754
44879 /* 124754 */ GIM_Reject,
44880 /* 124755 */ // Label 3749: @124755
44881 /* 124755 */ GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(124992),
44882 /* 124760 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44883 /* 124763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44884 /* 124766 */ GIM_Try, /*On fail goto*//*Label 3767*/ GIMT_Encode4(124892),
44885 /* 124771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44886 /* 124775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3768*/ GIMT_Encode4(124833), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6666 //
44887 /* 124782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44888 /* 124786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44889 /* 124790 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44890 /* 124794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44891 /* 124799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44892 /* 124803 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44893 /* 124805 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44894 /* 124805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
44895 /* 124808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44896 /* 124810 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44897 /* 124812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44898 /* 124816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44899 /* 124819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44900 /* 124825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44901 /* 124831 */ GIR_RootConstrainSelectedInstOperands,
44902 /* 124832 */ // GIR_Coverage, 6666,
44903 /* 124832 */ GIR_EraseRootFromParent_Done,
44904 /* 124833 */ // Label 3768: @124833
44905 /* 124833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3769*/ GIMT_Encode4(124891), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4106 //
44906 /* 124840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44907 /* 124844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44908 /* 124848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44909 /* 124852 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44910 /* 124856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44911 /* 124861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44912 /* 124863 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44913 /* 124863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
44914 /* 124866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44915 /* 124868 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44916 /* 124870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44917 /* 124874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44918 /* 124877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44919 /* 124883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44920 /* 124889 */ GIR_RootConstrainSelectedInstOperands,
44921 /* 124890 */ // GIR_Coverage, 4106,
44922 /* 124890 */ GIR_EraseRootFromParent_Done,
44923 /* 124891 */ // Label 3769: @124891
44924 /* 124891 */ GIM_Reject,
44925 /* 124892 */ // Label 3767: @124892
44926 /* 124892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3770*/ GIMT_Encode4(124931), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1368 //
44927 /* 124899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44928 /* 124903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44929 /* 124907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44930 /* 124911 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44931 /* 124911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32),
44932 /* 124914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44933 /* 124916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44934 /* 124918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44935 /* 124920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44936 /* 124923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44937 /* 124929 */ GIR_RootConstrainSelectedInstOperands,
44938 /* 124930 */ // GIR_Coverage, 1368,
44939 /* 124930 */ GIR_EraseRootFromParent_Done,
44940 /* 124931 */ // Label 3770: @124931
44941 /* 124931 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3771*/ GIMT_Encode4(124991), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3724 //
44942 /* 124938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44943 /* 124942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44944 /* 124946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44945 /* 124950 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44946 /* 124950 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44947 /* 124953 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44948 /* 124957 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44949 /* 124962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32),
44950 /* 124965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44951 /* 124967 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44952 /* 124969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44953 /* 124971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44954 /* 124974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44955 /* 124980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44956 /* 124986 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44957 /* 124989 */ GIR_RootConstrainSelectedInstOperands,
44958 /* 124990 */ // GIR_Coverage, 3724,
44959 /* 124990 */ GIR_EraseRootFromParent_Done,
44960 /* 124991 */ // Label 3771: @124991
44961 /* 124991 */ GIM_Reject,
44962 /* 124992 */ // Label 3766: @124992
44963 /* 124992 */ GIM_Reject,
44964 /* 124993 */ // Label 3750: @124993
44965 /* 124993 */ GIM_Reject,
44966 /* 124994 */ // Label 68: @124994
44967 /* 124994 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3778*/ GIMT_Encode4(125431),
44968 /* 125005 */ /*GILLT_v8s8*//*Label 3772*/ GIMT_Encode4(125029),
44969 /* 125009 */ /*GILLT_v16s8*//*Label 3773*/ GIMT_Encode4(125066),
44970 /* 125013 */ /*GILLT_v4s16*//*Label 3774*/ GIMT_Encode4(125163),
44971 /* 125017 */ /*GILLT_v8s16*//*Label 3775*/ GIMT_Encode4(125200),
44972 /* 125021 */ /*GILLT_v2s32*//*Label 3776*/ GIMT_Encode4(125297),
44973 /* 125025 */ /*GILLT_v4s32*//*Label 3777*/ GIMT_Encode4(125334),
44974 /* 125029 */ // Label 3772: @125029
44975 /* 125029 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3779*/ GIMT_Encode4(125065), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1670 //
44976 /* 125036 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44977 /* 125039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44978 /* 125043 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44979 /* 125047 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
44980 /* 125047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8),
44981 /* 125050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44982 /* 125052 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44983 /* 125054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44984 /* 125057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44985 /* 125063 */ GIR_RootConstrainSelectedInstOperands,
44986 /* 125064 */ // GIR_Coverage, 1670,
44987 /* 125064 */ GIR_EraseRootFromParent_Done,
44988 /* 125065 */ // Label 3779: @125065
44989 /* 125065 */ GIM_Reject,
44990 /* 125066 */ // Label 3773: @125066
44991 /* 125066 */ GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(125162),
44992 /* 125071 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44993 /* 125074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3781*/ GIMT_Encode4(125107), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1673 //
44994 /* 125081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44995 /* 125085 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44996 /* 125089 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
44997 /* 125089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8),
44998 /* 125092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44999 /* 125094 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45000 /* 125096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45001 /* 125099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45002 /* 125105 */ GIR_RootConstrainSelectedInstOperands,
45003 /* 125106 */ // GIR_Coverage, 1673,
45004 /* 125106 */ GIR_EraseRootFromParent_Done,
45005 /* 125107 */ // Label 3781: @125107
45006 /* 125107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3782*/ GIMT_Encode4(125161), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4057 //
45007 /* 125114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45008 /* 125118 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45009 /* 125122 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v)
45010 /* 125122 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45011 /* 125125 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45012 /* 125129 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45013 /* 125134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8),
45014 /* 125137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45015 /* 125139 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
45016 /* 125141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45017 /* 125144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45018 /* 125150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45019 /* 125156 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45020 /* 125159 */ GIR_RootConstrainSelectedInstOperands,
45021 /* 125160 */ // GIR_Coverage, 4057,
45022 /* 125160 */ GIR_EraseRootFromParent_Done,
45023 /* 125161 */ // Label 3782: @125161
45024 /* 125161 */ GIM_Reject,
45025 /* 125162 */ // Label 3780: @125162
45026 /* 125162 */ GIM_Reject,
45027 /* 125163 */ // Label 3774: @125163
45028 /* 125163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3783*/ GIMT_Encode4(125199), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1671 //
45029 /* 125170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45030 /* 125173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45031 /* 125177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45032 /* 125181 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
45033 /* 125181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16),
45034 /* 125184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45035 /* 125186 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45036 /* 125188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45037 /* 125191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45038 /* 125197 */ GIR_RootConstrainSelectedInstOperands,
45039 /* 125198 */ // GIR_Coverage, 1671,
45040 /* 125198 */ GIR_EraseRootFromParent_Done,
45041 /* 125199 */ // Label 3783: @125199
45042 /* 125199 */ GIM_Reject,
45043 /* 125200 */ // Label 3775: @125200
45044 /* 125200 */ GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(125296),
45045 /* 125205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45046 /* 125208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3785*/ GIMT_Encode4(125241), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1674 //
45047 /* 125215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45048 /* 125219 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45049 /* 125223 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
45050 /* 125223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16),
45051 /* 125226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45052 /* 125228 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45053 /* 125230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45054 /* 125233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45055 /* 125239 */ GIR_RootConstrainSelectedInstOperands,
45056 /* 125240 */ // GIR_Coverage, 1674,
45057 /* 125240 */ GIR_EraseRootFromParent_Done,
45058 /* 125241 */ // Label 3785: @125241
45059 /* 125241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3786*/ GIMT_Encode4(125295), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4063 //
45060 /* 125248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45061 /* 125252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45062 /* 125256 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v)
45063 /* 125256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45064 /* 125259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45065 /* 125263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45066 /* 125268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16),
45067 /* 125271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45068 /* 125273 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
45069 /* 125275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45070 /* 125278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45071 /* 125284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45072 /* 125290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45073 /* 125293 */ GIR_RootConstrainSelectedInstOperands,
45074 /* 125294 */ // GIR_Coverage, 4063,
45075 /* 125294 */ GIR_EraseRootFromParent_Done,
45076 /* 125295 */ // Label 3786: @125295
45077 /* 125295 */ GIM_Reject,
45078 /* 125296 */ // Label 3784: @125296
45079 /* 125296 */ GIM_Reject,
45080 /* 125297 */ // Label 3776: @125297
45081 /* 125297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3787*/ GIMT_Encode4(125333), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1672 //
45082 /* 125304 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45083 /* 125307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45084 /* 125311 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45085 /* 125315 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
45086 /* 125315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32),
45087 /* 125318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45088 /* 125320 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45089 /* 125322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45090 /* 125325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45091 /* 125331 */ GIR_RootConstrainSelectedInstOperands,
45092 /* 125332 */ // GIR_Coverage, 1672,
45093 /* 125332 */ GIR_EraseRootFromParent_Done,
45094 /* 125333 */ // Label 3787: @125333
45095 /* 125333 */ GIM_Reject,
45096 /* 125334 */ // Label 3777: @125334
45097 /* 125334 */ GIM_Try, /*On fail goto*//*Label 3788*/ GIMT_Encode4(125430),
45098 /* 125339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45099 /* 125342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3789*/ GIMT_Encode4(125375), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1675 //
45100 /* 125349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45101 /* 125353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45102 /* 125357 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
45103 /* 125357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32),
45104 /* 125360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45105 /* 125362 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45106 /* 125364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45107 /* 125367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45108 /* 125373 */ GIR_RootConstrainSelectedInstOperands,
45109 /* 125374 */ // GIR_Coverage, 1675,
45110 /* 125374 */ GIR_EraseRootFromParent_Done,
45111 /* 125375 */ // Label 3789: @125375
45112 /* 125375 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3790*/ GIMT_Encode4(125429), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4069 //
45113 /* 125382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45114 /* 125386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45115 /* 125390 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v)
45116 /* 125390 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45117 /* 125393 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45118 /* 125397 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45119 /* 125402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32),
45120 /* 125405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45121 /* 125407 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
45122 /* 125409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45123 /* 125412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45124 /* 125418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45125 /* 125424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45126 /* 125427 */ GIR_RootConstrainSelectedInstOperands,
45127 /* 125428 */ // GIR_Coverage, 4069,
45128 /* 125428 */ GIR_EraseRootFromParent_Done,
45129 /* 125429 */ // Label 3790: @125429
45130 /* 125429 */ GIM_Reject,
45131 /* 125430 */ // Label 3788: @125430
45132 /* 125430 */ GIM_Reject,
45133 /* 125431 */ // Label 3778: @125431
45134 /* 125431 */ GIM_Reject,
45135 /* 125432 */ // Label 69: @125432
45136 /* 125432 */ GIM_Try, /*On fail goto*//*Label 3791*/ GIMT_Encode4(125501),
45137 /* 125437 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
45138 /* 125440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3792*/ GIMT_Encode4(125454), GIMT_Encode2(GIFBS_IsARM), // Rule ID 31 //
45139 /* 125447 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target)
45140 /* 125447 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B),
45141 /* 125452 */ GIR_RootConstrainSelectedInstOperands,
45142 /* 125453 */ // GIR_Coverage, 31,
45143 /* 125453 */ GIR_Done,
45144 /* 125454 */ // Label 3792: @125454
45145 /* 125454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3793*/ GIMT_Encode4(125477), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 282 //
45146 /* 125461 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target)
45147 /* 125461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB),
45148 /* 125464 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
45149 /* 125466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45150 /* 125469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45151 /* 125475 */ GIR_RootConstrainSelectedInstOperands,
45152 /* 125476 */ // GIR_Coverage, 282,
45153 /* 125476 */ GIR_EraseRootFromParent_Done,
45154 /* 125477 */ // Label 3793: @125477
45155 /* 125477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3794*/ GIMT_Encode4(125500), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 576 //
45156 /* 125484 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target)
45157 /* 125484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B),
45158 /* 125487 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
45159 /* 125489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45160 /* 125492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45161 /* 125498 */ GIR_RootConstrainSelectedInstOperands,
45162 /* 125499 */ // GIR_Coverage, 576,
45163 /* 125499 */ GIR_EraseRootFromParent_Done,
45164 /* 125500 */ // Label 3794: @125500
45165 /* 125500 */ GIM_Reject,
45166 /* 125501 */ // Label 3791: @125501
45167 /* 125501 */ GIM_Reject,
45168 /* 125502 */ // Label 70: @125502
45169 /* 125502 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 3799*/ GIMT_Encode4(125777),
45170 /* 125513 */ /*GILLT_v8s8*//*Label 3795*/ GIMT_Encode4(125529),
45171 /* 125517 */ /*GILLT_v16s8*//*Label 3796*/ GIMT_Encode4(125591),
45172 /* 125521 */ /*GILLT_v4s16*//*Label 3797*/ GIMT_Encode4(125653),
45173 /* 125525 */ /*GILLT_v8s16*//*Label 3798*/ GIMT_Encode4(125715),
45174 /* 125529 */ // Label 3795: @125529
45175 /* 125529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3800*/ GIMT_Encode4(125590), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1733 //
45176 /* 125536 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
45177 /* 125539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45178 /* 125542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
45179 /* 125545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45180 /* 125549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45181 /* 125553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45182 /* 125557 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
45183 /* 125561 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45184 /* 125565 */ // MIs[1] Operand 1
45185 /* 125565 */ // No operand predicates
45186 /* 125565 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45187 /* 125567 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
45188 /* 125567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8),
45189 /* 125570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
45190 /* 125572 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
45191 /* 125574 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
45192 /* 125576 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45193 /* 125579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45194 /* 125582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45195 /* 125588 */ GIR_RootConstrainSelectedInstOperands,
45196 /* 125589 */ // GIR_Coverage, 1733,
45197 /* 125589 */ GIR_EraseRootFromParent_Done,
45198 /* 125590 */ // Label 3800: @125590
45199 /* 125590 */ GIM_Reject,
45200 /* 125591 */ // Label 3796: @125591
45201 /* 125591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3801*/ GIMT_Encode4(125652), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3832 //
45202 /* 125598 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45203 /* 125601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45204 /* 125604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
45205 /* 125607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45206 /* 125611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45207 /* 125615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45208 /* 125619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
45209 /* 125623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45210 /* 125627 */ // MIs[1] Operand 1
45211 /* 125627 */ // No operand predicates
45212 /* 125627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45213 /* 125629 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
45214 /* 125629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8),
45215 /* 125632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45216 /* 125634 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
45217 /* 125636 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
45218 /* 125638 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45219 /* 125641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45220 /* 125644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45221 /* 125650 */ GIR_RootConstrainSelectedInstOperands,
45222 /* 125651 */ // GIR_Coverage, 3832,
45223 /* 125651 */ GIR_EraseRootFromParent_Done,
45224 /* 125652 */ // Label 3801: @125652
45225 /* 125652 */ GIM_Reject,
45226 /* 125653 */ // Label 3797: @125653
45227 /* 125653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3802*/ GIMT_Encode4(125714), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1734 //
45228 /* 125660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45229 /* 125663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45230 /* 125666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
45231 /* 125669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45232 /* 125673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45233 /* 125677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45234 /* 125681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
45235 /* 125685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45236 /* 125689 */ // MIs[1] Operand 1
45237 /* 125689 */ // No operand predicates
45238 /* 125689 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45239 /* 125691 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
45240 /* 125691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16),
45241 /* 125694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
45242 /* 125696 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
45243 /* 125698 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
45244 /* 125700 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45245 /* 125703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45246 /* 125706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45247 /* 125712 */ GIR_RootConstrainSelectedInstOperands,
45248 /* 125713 */ // GIR_Coverage, 1734,
45249 /* 125713 */ GIR_EraseRootFromParent_Done,
45250 /* 125714 */ // Label 3802: @125714
45251 /* 125714 */ GIM_Reject,
45252 /* 125715 */ // Label 3798: @125715
45253 /* 125715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3803*/ GIMT_Encode4(125776), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3833 //
45254 /* 125722 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45255 /* 125725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45256 /* 125728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
45257 /* 125731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45258 /* 125735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45259 /* 125739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45260 /* 125743 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
45261 /* 125747 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45262 /* 125751 */ // MIs[1] Operand 1
45263 /* 125751 */ // No operand predicates
45264 /* 125751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45265 /* 125753 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
45266 /* 125753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16),
45267 /* 125756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45268 /* 125758 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
45269 /* 125760 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
45270 /* 125762 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45271 /* 125765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45272 /* 125768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45273 /* 125774 */ GIR_RootConstrainSelectedInstOperands,
45274 /* 125775 */ // GIR_Coverage, 3833,
45275 /* 125775 */ GIR_EraseRootFromParent_Done,
45276 /* 125776 */ // Label 3803: @125776
45277 /* 125776 */ GIM_Reject,
45278 /* 125777 */ // Label 3799: @125777
45279 /* 125777 */ GIM_Reject,
45280 /* 125778 */ // Label 71: @125778
45281 /* 125778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3804*/ GIMT_Encode4(125833), GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32), // Rule ID 1732 //
45282 /* 125785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45283 /* 125788 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45284 /* 125791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45285 /* 125794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45286 /* 125798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45287 /* 125802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
45288 /* 125806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45289 /* 125810 */ // MIs[1] Operand 1
45290 /* 125810 */ // No operand predicates
45291 /* 125810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45292 /* 125812 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)
45293 /* 125812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32),
45294 /* 125815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R]
45295 /* 125817 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
45296 /* 125819 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45297 /* 125822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45298 /* 125825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45299 /* 125831 */ GIR_RootConstrainSelectedInstOperands,
45300 /* 125832 */ // GIR_Coverage, 1732,
45301 /* 125832 */ GIR_EraseRootFromParent_Done,
45302 /* 125833 */ // Label 3804: @125833
45303 /* 125833 */ GIM_Reject,
45304 /* 125834 */ // Label 72: @125834
45305 /* 125834 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3812*/ GIMT_Encode4(126371),
45306 /* 125845 */ /*GILLT_s32*//*Label 3805*/ GIMT_Encode4(125893), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45307 /* 125869 */ /*GILLT_v8s8*//*Label 3806*/ GIMT_Encode4(125969),
45308 /* 125873 */ /*GILLT_v16s8*//*Label 3807*/ GIMT_Encode4(126006),
45309 /* 125877 */ /*GILLT_v4s16*//*Label 3808*/ GIMT_Encode4(126103),
45310 /* 125881 */ /*GILLT_v8s16*//*Label 3809*/ GIMT_Encode4(126140),
45311 /* 125885 */ /*GILLT_v2s32*//*Label 3810*/ GIMT_Encode4(126237),
45312 /* 125889 */ /*GILLT_v4s32*//*Label 3811*/ GIMT_Encode4(126274),
45313 /* 125893 */ // Label 3805: @125893
45314 /* 125893 */ GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(125968),
45315 /* 125898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45316 /* 125901 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3814*/ GIMT_Encode4(125934), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 196 //
45317 /* 125908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45318 /* 125912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45319 /* 125916 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45320 /* 125916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ),
45321 /* 125919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45322 /* 125921 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45323 /* 125923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45324 /* 125926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45325 /* 125932 */ GIR_RootConstrainSelectedInstOperands,
45326 /* 125933 */ // GIR_Coverage, 196,
45327 /* 125933 */ GIR_EraseRootFromParent_Done,
45328 /* 125934 */ // Label 3814: @125934
45329 /* 125934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3815*/ GIMT_Encode4(125967), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 533 //
45330 /* 125941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45331 /* 125945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45332 /* 125949 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45333 /* 125949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ),
45334 /* 125952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45335 /* 125954 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45336 /* 125956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45337 /* 125959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45338 /* 125965 */ GIR_RootConstrainSelectedInstOperands,
45339 /* 125966 */ // GIR_Coverage, 533,
45340 /* 125966 */ GIR_EraseRootFromParent_Done,
45341 /* 125967 */ // Label 3815: @125967
45342 /* 125967 */ GIM_Reject,
45343 /* 125968 */ // Label 3813: @125968
45344 /* 125968 */ GIM_Reject,
45345 /* 125969 */ // Label 3806: @125969
45346 /* 125969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3816*/ GIMT_Encode4(126005), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1708 //
45347 /* 125976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
45348 /* 125979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45349 /* 125983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45350 /* 125987 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45351 /* 125987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8),
45352 /* 125990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45353 /* 125992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45354 /* 125994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45355 /* 125997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45356 /* 126003 */ GIR_RootConstrainSelectedInstOperands,
45357 /* 126004 */ // GIR_Coverage, 1708,
45358 /* 126004 */ GIR_EraseRootFromParent_Done,
45359 /* 126005 */ // Label 3816: @126005
45360 /* 126005 */ GIM_Reject,
45361 /* 126006 */ // Label 3807: @126006
45362 /* 126006 */ GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(126102),
45363 /* 126011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45364 /* 126014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3818*/ GIMT_Encode4(126047), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1711 //
45365 /* 126021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45366 /* 126025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45367 /* 126029 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45368 /* 126029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8),
45369 /* 126032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45370 /* 126034 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45371 /* 126036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45372 /* 126039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45373 /* 126045 */ GIR_RootConstrainSelectedInstOperands,
45374 /* 126046 */ // GIR_Coverage, 1711,
45375 /* 126046 */ GIR_EraseRootFromParent_Done,
45376 /* 126047 */ // Label 3818: @126047
45377 /* 126047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3819*/ GIMT_Encode4(126101), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4051 //
45378 /* 126054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45379 /* 126058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45380 /* 126062 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
45381 /* 126062 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45382 /* 126065 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45383 /* 126069 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45384 /* 126074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8),
45385 /* 126077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45386 /* 126079 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45387 /* 126081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45388 /* 126084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45389 /* 126090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45390 /* 126096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45391 /* 126099 */ GIR_RootConstrainSelectedInstOperands,
45392 /* 126100 */ // GIR_Coverage, 4051,
45393 /* 126100 */ GIR_EraseRootFromParent_Done,
45394 /* 126101 */ // Label 3819: @126101
45395 /* 126101 */ GIM_Reject,
45396 /* 126102 */ // Label 3817: @126102
45397 /* 126102 */ GIM_Reject,
45398 /* 126103 */ // Label 3808: @126103
45399 /* 126103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3820*/ GIMT_Encode4(126139), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1709 //
45400 /* 126110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45401 /* 126113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45402 /* 126117 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45403 /* 126121 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
45404 /* 126121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16),
45405 /* 126124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45406 /* 126126 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45407 /* 126128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45408 /* 126131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45409 /* 126137 */ GIR_RootConstrainSelectedInstOperands,
45410 /* 126138 */ // GIR_Coverage, 1709,
45411 /* 126138 */ GIR_EraseRootFromParent_Done,
45412 /* 126139 */ // Label 3820: @126139
45413 /* 126139 */ GIM_Reject,
45414 /* 126140 */ // Label 3809: @126140
45415 /* 126140 */ GIM_Try, /*On fail goto*//*Label 3821*/ GIMT_Encode4(126236),
45416 /* 126145 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45417 /* 126148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3822*/ GIMT_Encode4(126181), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1712 //
45418 /* 126155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45419 /* 126159 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45420 /* 126163 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
45421 /* 126163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16),
45422 /* 126166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45423 /* 126168 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45424 /* 126170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45425 /* 126173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45426 /* 126179 */ GIR_RootConstrainSelectedInstOperands,
45427 /* 126180 */ // GIR_Coverage, 1712,
45428 /* 126180 */ GIR_EraseRootFromParent_Done,
45429 /* 126181 */ // Label 3822: @126181
45430 /* 126181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3823*/ GIMT_Encode4(126235), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4053 //
45431 /* 126188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45432 /* 126192 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45433 /* 126196 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
45434 /* 126196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45435 /* 126199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45436 /* 126203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45437 /* 126208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16),
45438 /* 126211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45439 /* 126213 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45440 /* 126215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45441 /* 126218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45442 /* 126224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45443 /* 126230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45444 /* 126233 */ GIR_RootConstrainSelectedInstOperands,
45445 /* 126234 */ // GIR_Coverage, 4053,
45446 /* 126234 */ GIR_EraseRootFromParent_Done,
45447 /* 126235 */ // Label 3823: @126235
45448 /* 126235 */ GIM_Reject,
45449 /* 126236 */ // Label 3821: @126236
45450 /* 126236 */ GIM_Reject,
45451 /* 126237 */ // Label 3810: @126237
45452 /* 126237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3824*/ GIMT_Encode4(126273), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1710 //
45453 /* 126244 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45454 /* 126247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45455 /* 126251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45456 /* 126255 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
45457 /* 126255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32),
45458 /* 126258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45459 /* 126260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45460 /* 126262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45461 /* 126265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45462 /* 126271 */ GIR_RootConstrainSelectedInstOperands,
45463 /* 126272 */ // GIR_Coverage, 1710,
45464 /* 126272 */ GIR_EraseRootFromParent_Done,
45465 /* 126273 */ // Label 3824: @126273
45466 /* 126273 */ GIM_Reject,
45467 /* 126274 */ // Label 3811: @126274
45468 /* 126274 */ GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(126370),
45469 /* 126279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45470 /* 126282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3826*/ GIMT_Encode4(126315), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1713 //
45471 /* 126289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45472 /* 126293 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45473 /* 126297 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
45474 /* 126297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32),
45475 /* 126300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45476 /* 126302 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45477 /* 126304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45478 /* 126307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45479 /* 126313 */ GIR_RootConstrainSelectedInstOperands,
45480 /* 126314 */ // GIR_Coverage, 1713,
45481 /* 126314 */ GIR_EraseRootFromParent_Done,
45482 /* 126315 */ // Label 3826: @126315
45483 /* 126315 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3827*/ GIMT_Encode4(126369), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4055 //
45484 /* 126322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45485 /* 126326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45486 /* 126330 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
45487 /* 126330 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45488 /* 126333 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45489 /* 126337 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45490 /* 126342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32),
45491 /* 126345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45492 /* 126347 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45493 /* 126349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45494 /* 126352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45495 /* 126358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45496 /* 126364 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45497 /* 126367 */ GIR_RootConstrainSelectedInstOperands,
45498 /* 126368 */ // GIR_Coverage, 4055,
45499 /* 126368 */ GIR_EraseRootFromParent_Done,
45500 /* 126369 */ // Label 3827: @126369
45501 /* 126369 */ GIM_Reject,
45502 /* 126370 */ // Label 3825: @126370
45503 /* 126370 */ GIM_Reject,
45504 /* 126371 */ // Label 3812: @126371
45505 /* 126371 */ GIM_Reject,
45506 /* 126372 */ // Label 73: @126372
45507 /* 126372 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3834*/ GIMT_Encode4(126809),
45508 /* 126383 */ /*GILLT_v8s8*//*Label 3828*/ GIMT_Encode4(126407),
45509 /* 126387 */ /*GILLT_v16s8*//*Label 3829*/ GIMT_Encode4(126444),
45510 /* 126391 */ /*GILLT_v4s16*//*Label 3830*/ GIMT_Encode4(126541),
45511 /* 126395 */ /*GILLT_v8s16*//*Label 3831*/ GIMT_Encode4(126578),
45512 /* 126399 */ /*GILLT_v2s32*//*Label 3832*/ GIMT_Encode4(126675),
45513 /* 126403 */ /*GILLT_v4s32*//*Label 3833*/ GIMT_Encode4(126712),
45514 /* 126407 */ // Label 3828: @126407
45515 /* 126407 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3835*/ GIMT_Encode4(126443), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1702 //
45516 /* 126414 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
45517 /* 126417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45518 /* 126421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45519 /* 126425 */ // (ctls:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45520 /* 126425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8),
45521 /* 126428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45522 /* 126430 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45523 /* 126432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45524 /* 126435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45525 /* 126441 */ GIR_RootConstrainSelectedInstOperands,
45526 /* 126442 */ // GIR_Coverage, 1702,
45527 /* 126442 */ GIR_EraseRootFromParent_Done,
45528 /* 126443 */ // Label 3835: @126443
45529 /* 126443 */ GIM_Reject,
45530 /* 126444 */ // Label 3829: @126444
45531 /* 126444 */ GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(126540),
45532 /* 126449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45533 /* 126452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3837*/ GIMT_Encode4(126485), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1705 //
45534 /* 126459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45535 /* 126463 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45536 /* 126467 */ // (ctls:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45537 /* 126467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8),
45538 /* 126470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45539 /* 126472 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45540 /* 126474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45541 /* 126477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45542 /* 126483 */ GIR_RootConstrainSelectedInstOperands,
45543 /* 126484 */ // GIR_Coverage, 1705,
45544 /* 126484 */ GIR_EraseRootFromParent_Done,
45545 /* 126485 */ // Label 3837: @126485
45546 /* 126485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3838*/ GIMT_Encode4(126539), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4045 //
45547 /* 126492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45548 /* 126496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45549 /* 126500 */ // (ctls:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
45550 /* 126500 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45551 /* 126503 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45552 /* 126507 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45553 /* 126512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8),
45554 /* 126515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45555 /* 126517 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45556 /* 126519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45557 /* 126522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45558 /* 126528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45559 /* 126534 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45560 /* 126537 */ GIR_RootConstrainSelectedInstOperands,
45561 /* 126538 */ // GIR_Coverage, 4045,
45562 /* 126538 */ GIR_EraseRootFromParent_Done,
45563 /* 126539 */ // Label 3838: @126539
45564 /* 126539 */ GIM_Reject,
45565 /* 126540 */ // Label 3836: @126540
45566 /* 126540 */ GIM_Reject,
45567 /* 126541 */ // Label 3830: @126541
45568 /* 126541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3839*/ GIMT_Encode4(126577), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1703 //
45569 /* 126548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45570 /* 126551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45571 /* 126555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45572 /* 126559 */ // (ctls:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
45573 /* 126559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16),
45574 /* 126562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45575 /* 126564 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45576 /* 126566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45577 /* 126569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45578 /* 126575 */ GIR_RootConstrainSelectedInstOperands,
45579 /* 126576 */ // GIR_Coverage, 1703,
45580 /* 126576 */ GIR_EraseRootFromParent_Done,
45581 /* 126577 */ // Label 3839: @126577
45582 /* 126577 */ GIM_Reject,
45583 /* 126578 */ // Label 3831: @126578
45584 /* 126578 */ GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(126674),
45585 /* 126583 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45586 /* 126586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3841*/ GIMT_Encode4(126619), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1706 //
45587 /* 126593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45588 /* 126597 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45589 /* 126601 */ // (ctls:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
45590 /* 126601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16),
45591 /* 126604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45592 /* 126606 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45593 /* 126608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45594 /* 126611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45595 /* 126617 */ GIR_RootConstrainSelectedInstOperands,
45596 /* 126618 */ // GIR_Coverage, 1706,
45597 /* 126618 */ GIR_EraseRootFromParent_Done,
45598 /* 126619 */ // Label 3841: @126619
45599 /* 126619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3842*/ GIMT_Encode4(126673), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4047 //
45600 /* 126626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45601 /* 126630 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45602 /* 126634 */ // (ctls:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
45603 /* 126634 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45604 /* 126637 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45605 /* 126641 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45606 /* 126646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16),
45607 /* 126649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45608 /* 126651 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45609 /* 126653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45610 /* 126656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45611 /* 126662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45612 /* 126668 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45613 /* 126671 */ GIR_RootConstrainSelectedInstOperands,
45614 /* 126672 */ // GIR_Coverage, 4047,
45615 /* 126672 */ GIR_EraseRootFromParent_Done,
45616 /* 126673 */ // Label 3842: @126673
45617 /* 126673 */ GIM_Reject,
45618 /* 126674 */ // Label 3840: @126674
45619 /* 126674 */ GIM_Reject,
45620 /* 126675 */ // Label 3832: @126675
45621 /* 126675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3843*/ GIMT_Encode4(126711), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1704 //
45622 /* 126682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45623 /* 126685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45624 /* 126689 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45625 /* 126693 */ // (ctls:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
45626 /* 126693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32),
45627 /* 126696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45628 /* 126698 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45629 /* 126700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45630 /* 126703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45631 /* 126709 */ GIR_RootConstrainSelectedInstOperands,
45632 /* 126710 */ // GIR_Coverage, 1704,
45633 /* 126710 */ GIR_EraseRootFromParent_Done,
45634 /* 126711 */ // Label 3843: @126711
45635 /* 126711 */ GIM_Reject,
45636 /* 126712 */ // Label 3833: @126712
45637 /* 126712 */ GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(126808),
45638 /* 126717 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45639 /* 126720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3845*/ GIMT_Encode4(126753), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1707 //
45640 /* 126727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45641 /* 126731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45642 /* 126735 */ // (ctls:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
45643 /* 126735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32),
45644 /* 126738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45645 /* 126740 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45646 /* 126742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45647 /* 126745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45648 /* 126751 */ GIR_RootConstrainSelectedInstOperands,
45649 /* 126752 */ // GIR_Coverage, 1707,
45650 /* 126752 */ GIR_EraseRootFromParent_Done,
45651 /* 126753 */ // Label 3845: @126753
45652 /* 126753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3846*/ GIMT_Encode4(126807), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4049 //
45653 /* 126760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45654 /* 126764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45655 /* 126768 */ // (ctls:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
45656 /* 126768 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45657 /* 126771 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45658 /* 126775 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45659 /* 126780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32),
45660 /* 126783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45661 /* 126785 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45662 /* 126787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45663 /* 126790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45664 /* 126796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45665 /* 126802 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45666 /* 126805 */ GIR_RootConstrainSelectedInstOperands,
45667 /* 126806 */ // GIR_Coverage, 4049,
45668 /* 126806 */ GIR_EraseRootFromParent_Done,
45669 /* 126807 */ // Label 3846: @126807
45670 /* 126807 */ GIM_Reject,
45671 /* 126808 */ // Label 3844: @126808
45672 /* 126808 */ GIM_Reject,
45673 /* 126809 */ // Label 3834: @126809
45674 /* 126809 */ GIM_Reject,
45675 /* 126810 */ // Label 74: @126810
45676 /* 126810 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 3849*/ GIMT_Encode4(126903),
45677 /* 126821 */ /*GILLT_v8s8*//*Label 3847*/ GIMT_Encode4(126829),
45678 /* 126825 */ /*GILLT_v16s8*//*Label 3848*/ GIMT_Encode4(126866),
45679 /* 126829 */ // Label 3847: @126829
45680 /* 126829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3850*/ GIMT_Encode4(126865), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1714 //
45681 /* 126836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
45682 /* 126839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45683 /* 126843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45684 /* 126847 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45685 /* 126847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd),
45686 /* 126850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45687 /* 126852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45688 /* 126854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45689 /* 126857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45690 /* 126863 */ GIR_RootConstrainSelectedInstOperands,
45691 /* 126864 */ // GIR_Coverage, 1714,
45692 /* 126864 */ GIR_EraseRootFromParent_Done,
45693 /* 126865 */ // Label 3850: @126865
45694 /* 126865 */ GIM_Reject,
45695 /* 126866 */ // Label 3848: @126866
45696 /* 126866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3851*/ GIMT_Encode4(126902), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1715 //
45697 /* 126873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45698 /* 126876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45699 /* 126880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45700 /* 126884 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45701 /* 126884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq),
45702 /* 126887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45703 /* 126889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45704 /* 126891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45705 /* 126894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45706 /* 126900 */ GIR_RootConstrainSelectedInstOperands,
45707 /* 126901 */ // GIR_Coverage, 1715,
45708 /* 126901 */ GIR_EraseRootFromParent_Done,
45709 /* 126902 */ // Label 3851: @126902
45710 /* 126902 */ GIM_Reject,
45711 /* 126903 */ // Label 3849: @126903
45712 /* 126903 */ GIM_Reject,
45713 /* 126904 */ // Label 75: @126904
45714 /* 126904 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3855*/ GIMT_Encode4(127188),
45715 /* 126915 */ /*GILLT_s32*//*Label 3852*/ GIMT_Encode4(126963), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45716 /* 126951 */ /*GILLT_v8s16*//*Label 3853*/ GIMT_Encode4(127072), GIMT_Encode4(0),
45717 /* 126959 */ /*GILLT_v4s32*//*Label 3854*/ GIMT_Encode4(127130),
45718 /* 126963 */ // Label 3852: @126963
45719 /* 126963 */ GIM_Try, /*On fail goto*//*Label 3856*/ GIMT_Encode4(127071),
45720 /* 126968 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45721 /* 126971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3857*/ GIMT_Encode4(127004), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 198 //
45722 /* 126978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45723 /* 126982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45724 /* 126986 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45725 /* 126986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV),
45726 /* 126989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45727 /* 126991 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45728 /* 126993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45729 /* 126996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45730 /* 127002 */ GIR_RootConstrainSelectedInstOperands,
45731 /* 127003 */ // GIR_Coverage, 198,
45732 /* 127003 */ GIR_EraseRootFromParent_Done,
45733 /* 127004 */ // Label 3857: @127004
45734 /* 127004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3858*/ GIMT_Encode4(127037), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 325 //
45735 /* 127011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
45736 /* 127015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
45737 /* 127019 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
45738 /* 127019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV),
45739 /* 127022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45740 /* 127024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45741 /* 127026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45742 /* 127029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45743 /* 127035 */ GIR_RootConstrainSelectedInstOperands,
45744 /* 127036 */ // GIR_Coverage, 325,
45745 /* 127036 */ GIR_EraseRootFromParent_Done,
45746 /* 127037 */ // Label 3858: @127037
45747 /* 127037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3859*/ GIMT_Encode4(127070), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 535 //
45748 /* 127044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45749 /* 127048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45750 /* 127052 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45751 /* 127052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV),
45752 /* 127055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45753 /* 127057 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45754 /* 127059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45755 /* 127062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45756 /* 127068 */ GIR_RootConstrainSelectedInstOperands,
45757 /* 127069 */ // GIR_Coverage, 535,
45758 /* 127069 */ GIR_EraseRootFromParent_Done,
45759 /* 127070 */ // Label 3859: @127070
45760 /* 127070 */ GIM_Reject,
45761 /* 127071 */ // Label 3856: @127071
45762 /* 127071 */ GIM_Reject,
45763 /* 127072 */ // Label 3853: @127072
45764 /* 127072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3860*/ GIMT_Encode4(127129), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3727 //
45765 /* 127079 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45766 /* 127082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45767 /* 127086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45768 /* 127090 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
45769 /* 127090 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45770 /* 127093 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45771 /* 127097 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45772 /* 127102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
45773 /* 127105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45774 /* 127107 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45775 /* 127109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45776 /* 127112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45777 /* 127118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45778 /* 127124 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45779 /* 127127 */ GIR_RootConstrainSelectedInstOperands,
45780 /* 127128 */ // GIR_Coverage, 3727,
45781 /* 127128 */ GIR_EraseRootFromParent_Done,
45782 /* 127129 */ // Label 3860: @127129
45783 /* 127129 */ GIM_Reject,
45784 /* 127130 */ // Label 3854: @127130
45785 /* 127130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3861*/ GIMT_Encode4(127187), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3728 //
45786 /* 127137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45787 /* 127140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45788 /* 127144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45789 /* 127148 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
45790 /* 127148 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45791 /* 127151 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45792 /* 127155 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45793 /* 127160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
45794 /* 127163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45795 /* 127165 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45796 /* 127167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45797 /* 127170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45798 /* 127176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45799 /* 127182 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45800 /* 127185 */ GIR_RootConstrainSelectedInstOperands,
45801 /* 127186 */ // GIR_Coverage, 3728,
45802 /* 127186 */ GIR_EraseRootFromParent_Done,
45803 /* 127187 */ // Label 3861: @127187
45804 /* 127187 */ GIM_Reject,
45805 /* 127188 */ // Label 3855: @127188
45806 /* 127188 */ GIM_Reject,
45807 /* 127189 */ // Label 76: @127189
45808 /* 127189 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3866*/ GIMT_Encode4(127603),
45809 /* 127200 */ /*GILLT_s32*//*Label 3862*/ GIMT_Encode4(127248), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45810 /* 127228 */ /*GILLT_v16s8*//*Label 3863*/ GIMT_Encode4(127324), GIMT_Encode4(0),
45811 /* 127236 */ /*GILLT_v8s16*//*Label 3864*/ GIMT_Encode4(127417), GIMT_Encode4(0),
45812 /* 127244 */ /*GILLT_v4s32*//*Label 3865*/ GIMT_Encode4(127510),
45813 /* 127248 */ // Label 3862: @127248
45814 /* 127248 */ GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(127323),
45815 /* 127253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45816 /* 127256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3868*/ GIMT_Encode4(127289), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 197 //
45817 /* 127263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45818 /* 127267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45819 /* 127271 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45820 /* 127271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT),
45821 /* 127274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45822 /* 127276 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45823 /* 127278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45824 /* 127281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45825 /* 127287 */ GIR_RootConstrainSelectedInstOperands,
45826 /* 127288 */ // GIR_Coverage, 197,
45827 /* 127288 */ GIR_EraseRootFromParent_Done,
45828 /* 127289 */ // Label 3868: @127289
45829 /* 127289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3869*/ GIMT_Encode4(127322), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 534 //
45830 /* 127296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45831 /* 127300 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45832 /* 127304 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45833 /* 127304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT),
45834 /* 127307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45835 /* 127309 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45836 /* 127311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45837 /* 127314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45838 /* 127320 */ GIR_RootConstrainSelectedInstOperands,
45839 /* 127321 */ // GIR_Coverage, 534,
45840 /* 127321 */ GIR_EraseRootFromParent_Done,
45841 /* 127322 */ // Label 3869: @127322
45842 /* 127322 */ GIM_Reject,
45843 /* 127323 */ // Label 3867: @127323
45844 /* 127323 */ GIM_Reject,
45845 /* 127324 */ // Label 3863: @127324
45846 /* 127324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3870*/ GIMT_Encode4(127416), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5280 //
45847 /* 127331 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45848 /* 127334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45849 /* 127338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45850 /* 127342 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
45851 /* 127342 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
45852 /* 127345 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45853 /* 127349 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45854 /* 127354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45855 /* 127357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
45856 /* 127361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45857 /* 127366 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
45858 /* 127369 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45859 /* 127372 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45860 /* 127378 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45861 /* 127384 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45862 /* 127386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
45863 /* 127389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45864 /* 127391 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
45865 /* 127393 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45866 /* 127396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45867 /* 127399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45868 /* 127405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45869 /* 127411 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
45870 /* 127414 */ GIR_RootConstrainSelectedInstOperands,
45871 /* 127415 */ // GIR_Coverage, 5280,
45872 /* 127415 */ GIR_EraseRootFromParent_Done,
45873 /* 127416 */ // Label 3870: @127416
45874 /* 127416 */ GIM_Reject,
45875 /* 127417 */ // Label 3864: @127417
45876 /* 127417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3871*/ GIMT_Encode4(127509), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5282 //
45877 /* 127424 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45878 /* 127427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45879 /* 127431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45880 /* 127435 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
45881 /* 127435 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
45882 /* 127438 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45883 /* 127442 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45884 /* 127447 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45885 /* 127450 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
45886 /* 127454 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45887 /* 127459 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
45888 /* 127462 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45889 /* 127465 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45890 /* 127471 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45891 /* 127477 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45892 /* 127479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
45893 /* 127482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45894 /* 127484 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
45895 /* 127486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45896 /* 127489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45897 /* 127492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45898 /* 127498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45899 /* 127504 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
45900 /* 127507 */ GIR_RootConstrainSelectedInstOperands,
45901 /* 127508 */ // GIR_Coverage, 5282,
45902 /* 127508 */ GIR_EraseRootFromParent_Done,
45903 /* 127509 */ // Label 3871: @127509
45904 /* 127509 */ GIM_Reject,
45905 /* 127510 */ // Label 3865: @127510
45906 /* 127510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3872*/ GIMT_Encode4(127602), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5281 //
45907 /* 127517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45908 /* 127520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45909 /* 127524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45910 /* 127528 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
45911 /* 127528 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
45912 /* 127531 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45913 /* 127535 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45914 /* 127540 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45915 /* 127543 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
45916 /* 127547 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45917 /* 127552 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
45918 /* 127555 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45919 /* 127558 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45920 /* 127564 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45921 /* 127570 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45922 /* 127572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
45923 /* 127575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45924 /* 127577 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
45925 /* 127579 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45926 /* 127582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45927 /* 127585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45928 /* 127591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45929 /* 127597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
45930 /* 127600 */ GIR_RootConstrainSelectedInstOperands,
45931 /* 127601 */ // GIR_Coverage, 5281,
45932 /* 127601 */ GIR_EraseRootFromParent_Done,
45933 /* 127602 */ // Label 3872: @127602
45934 /* 127602 */ GIM_Reject,
45935 /* 127603 */ // Label 3866: @127603
45936 /* 127603 */ GIM_Reject,
45937 /* 127604 */ // Label 77: @127604
45938 /* 127604 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3880*/ GIMT_Encode4(127969),
45939 /* 127615 */ /*GILLT_s16*//*Label 3873*/ GIMT_Encode4(127667),
45940 /* 127619 */ /*GILLT_s32*//*Label 3874*/ GIMT_Encode4(127693),
45941 /* 127623 */ /*GILLT_s64*//*Label 3875*/ GIMT_Encode4(127719), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45942 /* 127651 */ /*GILLT_v4s16*//*Label 3876*/ GIMT_Encode4(127745),
45943 /* 127655 */ /*GILLT_v8s16*//*Label 3877*/ GIMT_Encode4(127771),
45944 /* 127659 */ /*GILLT_v2s32*//*Label 3878*/ GIMT_Encode4(127857),
45945 /* 127663 */ /*GILLT_v4s32*//*Label 3879*/ GIMT_Encode4(127883),
45946 /* 127667 */ // Label 3873: @127667
45947 /* 127667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3881*/ GIMT_Encode4(127692), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 723 //
45948 /* 127674 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45949 /* 127677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45950 /* 127681 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45951 /* 127685 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
45952 /* 127685 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH),
45953 /* 127690 */ GIR_RootConstrainSelectedInstOperands,
45954 /* 127691 */ // GIR_Coverage, 723,
45955 /* 127691 */ GIR_Done,
45956 /* 127692 */ // Label 3881: @127692
45957 /* 127692 */ GIM_Reject,
45958 /* 127693 */ // Label 3874: @127693
45959 /* 127693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3882*/ GIMT_Encode4(127718), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 725 //
45960 /* 127700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45961 /* 127703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45962 /* 127707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45963 /* 127711 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
45964 /* 127711 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS),
45965 /* 127716 */ GIR_RootConstrainSelectedInstOperands,
45966 /* 127717 */ // GIR_Coverage, 725,
45967 /* 127717 */ GIR_Done,
45968 /* 127718 */ // Label 3882: @127718
45969 /* 127718 */ GIM_Reject,
45970 /* 127719 */ // Label 3875: @127719
45971 /* 127719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3883*/ GIMT_Encode4(127744), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 727 //
45972 /* 127726 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45973 /* 127729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45974 /* 127733 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45975 /* 127737 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
45976 /* 127737 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD),
45977 /* 127742 */ GIR_RootConstrainSelectedInstOperands,
45978 /* 127743 */ // GIR_Coverage, 727,
45979 /* 127743 */ GIR_Done,
45980 /* 127744 */ // Label 3883: @127744
45981 /* 127744 */ GIM_Reject,
45982 /* 127745 */ // Label 3876: @127745
45983 /* 127745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3884*/ GIMT_Encode4(127770), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1898 //
45984 /* 127752 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45985 /* 127755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45986 /* 127759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45987 /* 127763 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
45988 /* 127763 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh),
45989 /* 127768 */ GIR_RootConstrainSelectedInstOperands,
45990 /* 127769 */ // GIR_Coverage, 1898,
45991 /* 127769 */ GIR_Done,
45992 /* 127770 */ // Label 3884: @127770
45993 /* 127770 */ GIM_Reject,
45994 /* 127771 */ // Label 3877: @127771
45995 /* 127771 */ GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(127856),
45996 /* 127776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45997 /* 127779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3886*/ GIMT_Encode4(127801), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1900 //
45998 /* 127786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45999 /* 127790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46000 /* 127794 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
46001 /* 127794 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh),
46002 /* 127799 */ GIR_RootConstrainSelectedInstOperands,
46003 /* 127800 */ // GIR_Coverage, 1900,
46004 /* 127800 */ GIR_Done,
46005 /* 127801 */ // Label 3886: @127801
46006 /* 127801 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3887*/ GIMT_Encode4(127855), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4388 //
46007 /* 127808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46008 /* 127812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46009 /* 127816 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
46010 /* 127816 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46011 /* 127819 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46012 /* 127823 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46013 /* 127828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
46014 /* 127831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46015 /* 127833 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46016 /* 127835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46017 /* 127838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46018 /* 127844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46019 /* 127850 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46020 /* 127853 */ GIR_RootConstrainSelectedInstOperands,
46021 /* 127854 */ // GIR_Coverage, 4388,
46022 /* 127854 */ GIR_EraseRootFromParent_Done,
46023 /* 127855 */ // Label 3887: @127855
46024 /* 127855 */ GIM_Reject,
46025 /* 127856 */ // Label 3885: @127856
46026 /* 127856 */ GIM_Reject,
46027 /* 127857 */ // Label 3878: @127857
46028 /* 127857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3888*/ GIMT_Encode4(127882), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1894 //
46029 /* 127864 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46030 /* 127867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46031 /* 127871 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46032 /* 127875 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
46033 /* 127875 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf),
46034 /* 127880 */ GIR_RootConstrainSelectedInstOperands,
46035 /* 127881 */ // GIR_Coverage, 1894,
46036 /* 127881 */ GIR_Done,
46037 /* 127882 */ // Label 3888: @127882
46038 /* 127882 */ GIM_Reject,
46039 /* 127883 */ // Label 3879: @127883
46040 /* 127883 */ GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(127968),
46041 /* 127888 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46042 /* 127891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3890*/ GIMT_Encode4(127913), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1896 //
46043 /* 127898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46044 /* 127902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46045 /* 127906 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
46046 /* 127906 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf),
46047 /* 127911 */ GIR_RootConstrainSelectedInstOperands,
46048 /* 127912 */ // GIR_Coverage, 1896,
46049 /* 127912 */ GIR_Done,
46050 /* 127913 */ // Label 3890: @127913
46051 /* 127913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3891*/ GIMT_Encode4(127967), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4412 //
46052 /* 127920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46053 /* 127924 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46054 /* 127928 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46055 /* 127928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46056 /* 127931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46057 /* 127935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46058 /* 127940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
46059 /* 127943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46060 /* 127945 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46061 /* 127947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46062 /* 127950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46063 /* 127956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46064 /* 127962 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46065 /* 127965 */ GIR_RootConstrainSelectedInstOperands,
46066 /* 127966 */ // GIR_Coverage, 4412,
46067 /* 127966 */ GIR_EraseRootFromParent_Done,
46068 /* 127967 */ // Label 3891: @127967
46069 /* 127967 */ GIM_Reject,
46070 /* 127968 */ // Label 3889: @127968
46071 /* 127968 */ GIM_Reject,
46072 /* 127969 */ // Label 3880: @127969
46073 /* 127969 */ GIM_Reject,
46074 /* 127970 */ // Label 78: @127970
46075 /* 127970 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3895*/ GIMT_Encode4(128104),
46076 /* 127981 */ /*GILLT_s16*//*Label 3892*/ GIMT_Encode4(127993),
46077 /* 127985 */ /*GILLT_s32*//*Label 3893*/ GIMT_Encode4(128030),
46078 /* 127989 */ /*GILLT_s64*//*Label 3894*/ GIMT_Encode4(128067),
46079 /* 127993 */ // Label 3892: @127993
46080 /* 127993 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3896*/ GIMT_Encode4(128029), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 739 //
46081 /* 128000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46082 /* 128003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46083 /* 128007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46084 /* 128011 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46085 /* 128011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
46086 /* 128014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46087 /* 128016 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46088 /* 128018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46089 /* 128021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46090 /* 128027 */ GIR_RootConstrainSelectedInstOperands,
46091 /* 128028 */ // GIR_Coverage, 739,
46092 /* 128028 */ GIR_EraseRootFromParent_Done,
46093 /* 128029 */ // Label 3896: @128029
46094 /* 128029 */ GIM_Reject,
46095 /* 128030 */ // Label 3893: @128030
46096 /* 128030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3897*/ GIMT_Encode4(128066), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 737 //
46097 /* 128037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46098 /* 128040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46099 /* 128044 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46100 /* 128048 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46101 /* 128048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
46102 /* 128051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46103 /* 128053 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46104 /* 128055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46105 /* 128058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46106 /* 128064 */ GIR_RootConstrainSelectedInstOperands,
46107 /* 128065 */ // GIR_Coverage, 737,
46108 /* 128065 */ GIR_EraseRootFromParent_Done,
46109 /* 128066 */ // Label 3897: @128066
46110 /* 128066 */ GIM_Reject,
46111 /* 128067 */ // Label 3894: @128067
46112 /* 128067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3898*/ GIMT_Encode4(128103), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 735 //
46113 /* 128074 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46114 /* 128077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46115 /* 128081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46116 /* 128085 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46117 /* 128085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
46118 /* 128088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46119 /* 128090 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46120 /* 128092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46121 /* 128095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46122 /* 128101 */ GIR_RootConstrainSelectedInstOperands,
46123 /* 128102 */ // GIR_Coverage, 735,
46124 /* 128102 */ GIR_EraseRootFromParent_Done,
46125 /* 128103 */ // Label 3898: @128103
46126 /* 128103 */ GIM_Reject,
46127 /* 128104 */ // Label 3895: @128104
46128 /* 128104 */ GIM_Reject,
46129 /* 128105 */ // Label 79: @128105
46130 /* 128105 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3906*/ GIMT_Encode4(128470),
46131 /* 128116 */ /*GILLT_s16*//*Label 3899*/ GIMT_Encode4(128168),
46132 /* 128120 */ /*GILLT_s32*//*Label 3900*/ GIMT_Encode4(128194),
46133 /* 128124 */ /*GILLT_s64*//*Label 3901*/ GIMT_Encode4(128220), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46134 /* 128152 */ /*GILLT_v4s16*//*Label 3902*/ GIMT_Encode4(128246),
46135 /* 128156 */ /*GILLT_v8s16*//*Label 3903*/ GIMT_Encode4(128272),
46136 /* 128160 */ /*GILLT_v2s32*//*Label 3904*/ GIMT_Encode4(128358),
46137 /* 128164 */ /*GILLT_v4s32*//*Label 3905*/ GIMT_Encode4(128384),
46138 /* 128168 */ // Label 3899: @128168
46139 /* 128168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3907*/ GIMT_Encode4(128193), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 729 //
46140 /* 128175 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46141 /* 128178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46142 /* 128182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46143 /* 128186 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46144 /* 128186 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH),
46145 /* 128191 */ GIR_RootConstrainSelectedInstOperands,
46146 /* 128192 */ // GIR_Coverage, 729,
46147 /* 128192 */ GIR_Done,
46148 /* 128193 */ // Label 3907: @128193
46149 /* 128193 */ GIM_Reject,
46150 /* 128194 */ // Label 3900: @128194
46151 /* 128194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3908*/ GIMT_Encode4(128219), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 731 //
46152 /* 128201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46153 /* 128204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46154 /* 128208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46155 /* 128212 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46156 /* 128212 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS),
46157 /* 128217 */ GIR_RootConstrainSelectedInstOperands,
46158 /* 128218 */ // GIR_Coverage, 731,
46159 /* 128218 */ GIR_Done,
46160 /* 128219 */ // Label 3908: @128219
46161 /* 128219 */ GIM_Reject,
46162 /* 128220 */ // Label 3901: @128220
46163 /* 128220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3909*/ GIMT_Encode4(128245), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 733 //
46164 /* 128227 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46165 /* 128230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46166 /* 128234 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46167 /* 128238 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46168 /* 128238 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD),
46169 /* 128243 */ GIR_RootConstrainSelectedInstOperands,
46170 /* 128244 */ // GIR_Coverage, 733,
46171 /* 128244 */ GIR_Done,
46172 /* 128245 */ // Label 3909: @128245
46173 /* 128245 */ GIM_Reject,
46174 /* 128246 */ // Label 3902: @128246
46175 /* 128246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3910*/ GIMT_Encode4(128271), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1890 //
46176 /* 128253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46177 /* 128256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46178 /* 128260 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46179 /* 128264 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
46180 /* 128264 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh),
46181 /* 128269 */ GIR_RootConstrainSelectedInstOperands,
46182 /* 128270 */ // GIR_Coverage, 1890,
46183 /* 128270 */ GIR_Done,
46184 /* 128271 */ // Label 3910: @128271
46185 /* 128271 */ GIM_Reject,
46186 /* 128272 */ // Label 3903: @128272
46187 /* 128272 */ GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(128357),
46188 /* 128277 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46189 /* 128280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3912*/ GIMT_Encode4(128302), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1892 //
46190 /* 128287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46191 /* 128291 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46192 /* 128295 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
46193 /* 128295 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh),
46194 /* 128300 */ GIR_RootConstrainSelectedInstOperands,
46195 /* 128301 */ // GIR_Coverage, 1892,
46196 /* 128301 */ GIR_Done,
46197 /* 128302 */ // Label 3912: @128302
46198 /* 128302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3913*/ GIMT_Encode4(128356), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4384 //
46199 /* 128309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46200 /* 128313 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46201 /* 128317 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
46202 /* 128317 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46203 /* 128320 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46204 /* 128324 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46205 /* 128329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
46206 /* 128332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46207 /* 128334 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46208 /* 128336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46209 /* 128339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46210 /* 128345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46211 /* 128351 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46212 /* 128354 */ GIR_RootConstrainSelectedInstOperands,
46213 /* 128355 */ // GIR_Coverage, 4384,
46214 /* 128355 */ GIR_EraseRootFromParent_Done,
46215 /* 128356 */ // Label 3913: @128356
46216 /* 128356 */ GIM_Reject,
46217 /* 128357 */ // Label 3911: @128357
46218 /* 128357 */ GIM_Reject,
46219 /* 128358 */ // Label 3904: @128358
46220 /* 128358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3914*/ GIMT_Encode4(128383), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1886 //
46221 /* 128365 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46222 /* 128368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46223 /* 128372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46224 /* 128376 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
46225 /* 128376 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf),
46226 /* 128381 */ GIR_RootConstrainSelectedInstOperands,
46227 /* 128382 */ // GIR_Coverage, 1886,
46228 /* 128382 */ GIR_Done,
46229 /* 128383 */ // Label 3914: @128383
46230 /* 128383 */ GIM_Reject,
46231 /* 128384 */ // Label 3905: @128384
46232 /* 128384 */ GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(128469),
46233 /* 128389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46234 /* 128392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3916*/ GIMT_Encode4(128414), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1888 //
46235 /* 128399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46236 /* 128403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46237 /* 128407 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
46238 /* 128407 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf),
46239 /* 128412 */ GIR_RootConstrainSelectedInstOperands,
46240 /* 128413 */ // GIR_Coverage, 1888,
46241 /* 128413 */ GIR_Done,
46242 /* 128414 */ // Label 3916: @128414
46243 /* 128414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3917*/ GIMT_Encode4(128468), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4408 //
46244 /* 128421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46245 /* 128425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46246 /* 128429 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46247 /* 128429 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46248 /* 128432 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46249 /* 128436 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46250 /* 128441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
46251 /* 128444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46252 /* 128446 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46253 /* 128448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46254 /* 128451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46255 /* 128457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46256 /* 128463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46257 /* 128466 */ GIR_RootConstrainSelectedInstOperands,
46258 /* 128467 */ // GIR_Coverage, 4408,
46259 /* 128467 */ GIR_EraseRootFromParent_Done,
46260 /* 128468 */ // Label 3917: @128468
46261 /* 128468 */ GIM_Reject,
46262 /* 128469 */ // Label 3915: @128469
46263 /* 128469 */ GIM_Reject,
46264 /* 128470 */ // Label 3906: @128470
46265 /* 128470 */ GIM_Reject,
46266 /* 128471 */ // Label 80: @128471
46267 /* 128471 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3925*/ GIMT_Encode4(128869),
46268 /* 128482 */ /*GILLT_s16*//*Label 3918*/ GIMT_Encode4(128534),
46269 /* 128486 */ /*GILLT_s32*//*Label 3919*/ GIMT_Encode4(128571),
46270 /* 128490 */ /*GILLT_s64*//*Label 3920*/ GIMT_Encode4(128608), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46271 /* 128518 */ /*GILLT_v4s16*//*Label 3921*/ GIMT_Encode4(128645),
46272 /* 128522 */ /*GILLT_v8s16*//*Label 3922*/ GIMT_Encode4(128671),
46273 /* 128526 */ /*GILLT_v2s32*//*Label 3923*/ GIMT_Encode4(128757),
46274 /* 128530 */ /*GILLT_v4s32*//*Label 3924*/ GIMT_Encode4(128783),
46275 /* 128534 */ // Label 3918: @128534
46276 /* 128534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3926*/ GIMT_Encode4(128570), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 705 //
46277 /* 128541 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46278 /* 128544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46279 /* 128548 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46280 /* 128552 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46281 /* 128552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH),
46282 /* 128555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46283 /* 128557 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46284 /* 128559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46285 /* 128562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46286 /* 128568 */ GIR_RootConstrainSelectedInstOperands,
46287 /* 128569 */ // GIR_Coverage, 705,
46288 /* 128569 */ GIR_EraseRootFromParent_Done,
46289 /* 128570 */ // Label 3926: @128570
46290 /* 128570 */ GIM_Reject,
46291 /* 128571 */ // Label 3919: @128571
46292 /* 128571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3927*/ GIMT_Encode4(128607), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 707 //
46293 /* 128578 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46294 /* 128581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46295 /* 128585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46296 /* 128589 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46297 /* 128589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS),
46298 /* 128592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46299 /* 128594 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46300 /* 128596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46301 /* 128599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46302 /* 128605 */ GIR_RootConstrainSelectedInstOperands,
46303 /* 128606 */ // GIR_Coverage, 707,
46304 /* 128606 */ GIR_EraseRootFromParent_Done,
46305 /* 128607 */ // Label 3927: @128607
46306 /* 128607 */ GIM_Reject,
46307 /* 128608 */ // Label 3920: @128608
46308 /* 128608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3928*/ GIMT_Encode4(128644), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 709 //
46309 /* 128615 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46310 /* 128618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46311 /* 128622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46312 /* 128626 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46313 /* 128626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD),
46314 /* 128629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46315 /* 128631 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46316 /* 128633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46317 /* 128636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46318 /* 128642 */ GIR_RootConstrainSelectedInstOperands,
46319 /* 128643 */ // GIR_Coverage, 709,
46320 /* 128643 */ GIR_EraseRootFromParent_Done,
46321 /* 128644 */ // Label 3928: @128644
46322 /* 128644 */ GIM_Reject,
46323 /* 128645 */ // Label 3921: @128645
46324 /* 128645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3929*/ GIMT_Encode4(128670), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1866 //
46325 /* 128652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46326 /* 128655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46327 /* 128659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46328 /* 128663 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
46329 /* 128663 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh),
46330 /* 128668 */ GIR_RootConstrainSelectedInstOperands,
46331 /* 128669 */ // GIR_Coverage, 1866,
46332 /* 128669 */ GIR_Done,
46333 /* 128670 */ // Label 3929: @128670
46334 /* 128670 */ GIM_Reject,
46335 /* 128671 */ // Label 3922: @128671
46336 /* 128671 */ GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(128756),
46337 /* 128676 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46338 /* 128679 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3931*/ GIMT_Encode4(128701), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1868 //
46339 /* 128686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46340 /* 128690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46341 /* 128694 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
46342 /* 128694 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh),
46343 /* 128699 */ GIR_RootConstrainSelectedInstOperands,
46344 /* 128700 */ // GIR_Coverage, 1868,
46345 /* 128700 */ GIR_Done,
46346 /* 128701 */ // Label 3931: @128701
46347 /* 128701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3932*/ GIMT_Encode4(128755), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4372 //
46348 /* 128708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46349 /* 128712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46350 /* 128716 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
46351 /* 128716 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46352 /* 128719 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46353 /* 128723 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46354 /* 128728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
46355 /* 128731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46356 /* 128733 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46357 /* 128735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46358 /* 128738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46359 /* 128744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46360 /* 128750 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46361 /* 128753 */ GIR_RootConstrainSelectedInstOperands,
46362 /* 128754 */ // GIR_Coverage, 4372,
46363 /* 128754 */ GIR_EraseRootFromParent_Done,
46364 /* 128755 */ // Label 3932: @128755
46365 /* 128755 */ GIM_Reject,
46366 /* 128756 */ // Label 3930: @128756
46367 /* 128756 */ GIM_Reject,
46368 /* 128757 */ // Label 3923: @128757
46369 /* 128757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3933*/ GIMT_Encode4(128782), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1862 //
46370 /* 128764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46371 /* 128767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46372 /* 128771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46373 /* 128775 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
46374 /* 128775 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf),
46375 /* 128780 */ GIR_RootConstrainSelectedInstOperands,
46376 /* 128781 */ // GIR_Coverage, 1862,
46377 /* 128781 */ GIR_Done,
46378 /* 128782 */ // Label 3933: @128782
46379 /* 128782 */ GIM_Reject,
46380 /* 128783 */ // Label 3924: @128783
46381 /* 128783 */ GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(128868),
46382 /* 128788 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46383 /* 128791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3935*/ GIMT_Encode4(128813), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1864 //
46384 /* 128798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46385 /* 128802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46386 /* 128806 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
46387 /* 128806 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf),
46388 /* 128811 */ GIR_RootConstrainSelectedInstOperands,
46389 /* 128812 */ // GIR_Coverage, 1864,
46390 /* 128812 */ GIR_Done,
46391 /* 128813 */ // Label 3935: @128813
46392 /* 128813 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3936*/ GIMT_Encode4(128867), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4396 //
46393 /* 128820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46394 /* 128824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46395 /* 128828 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46396 /* 128828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46397 /* 128831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46398 /* 128835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46399 /* 128840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
46400 /* 128843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46401 /* 128845 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46402 /* 128847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46403 /* 128850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46404 /* 128856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46405 /* 128862 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46406 /* 128865 */ GIR_RootConstrainSelectedInstOperands,
46407 /* 128866 */ // GIR_Coverage, 4396,
46408 /* 128866 */ GIR_EraseRootFromParent_Done,
46409 /* 128867 */ // Label 3936: @128867
46410 /* 128867 */ GIM_Reject,
46411 /* 128868 */ // Label 3934: @128868
46412 /* 128868 */ GIM_Reject,
46413 /* 128869 */ // Label 3925: @128869
46414 /* 128869 */ GIM_Reject,
46415 /* 128870 */ // Label 81: @128870
46416 /* 128870 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3940*/ GIMT_Encode4(129004),
46417 /* 128881 */ /*GILLT_s16*//*Label 3937*/ GIMT_Encode4(128893),
46418 /* 128885 */ /*GILLT_s32*//*Label 3938*/ GIMT_Encode4(128930),
46419 /* 128889 */ /*GILLT_s64*//*Label 3939*/ GIMT_Encode4(128967),
46420 /* 128893 */ // Label 3937: @128893
46421 /* 128893 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3941*/ GIMT_Encode4(128929), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 699 //
46422 /* 128900 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46423 /* 128903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46424 /* 128907 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46425 /* 128911 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46426 /* 128911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH),
46427 /* 128914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46428 /* 128916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46429 /* 128918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46430 /* 128921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46431 /* 128927 */ GIR_RootConstrainSelectedInstOperands,
46432 /* 128928 */ // GIR_Coverage, 699,
46433 /* 128928 */ GIR_EraseRootFromParent_Done,
46434 /* 128929 */ // Label 3941: @128929
46435 /* 128929 */ GIM_Reject,
46436 /* 128930 */ // Label 3938: @128930
46437 /* 128930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3942*/ GIMT_Encode4(128966), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 701 //
46438 /* 128937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46439 /* 128940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46440 /* 128944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46441 /* 128948 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46442 /* 128948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS),
46443 /* 128951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46444 /* 128953 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46445 /* 128955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46446 /* 128958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46447 /* 128964 */ GIR_RootConstrainSelectedInstOperands,
46448 /* 128965 */ // GIR_Coverage, 701,
46449 /* 128965 */ GIR_EraseRootFromParent_Done,
46450 /* 128966 */ // Label 3942: @128966
46451 /* 128966 */ GIM_Reject,
46452 /* 128967 */ // Label 3939: @128967
46453 /* 128967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3943*/ GIMT_Encode4(129003), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 703 //
46454 /* 128974 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46455 /* 128977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46456 /* 128981 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46457 /* 128985 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46458 /* 128985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD),
46459 /* 128988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46460 /* 128990 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46461 /* 128992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46462 /* 128995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46463 /* 129001 */ GIR_RootConstrainSelectedInstOperands,
46464 /* 129002 */ // GIR_Coverage, 703,
46465 /* 129002 */ GIR_EraseRootFromParent_Done,
46466 /* 129003 */ // Label 3943: @129003
46467 /* 129003 */ GIM_Reject,
46468 /* 129004 */ // Label 3940: @129004
46469 /* 129004 */ GIM_Reject,
46470 /* 129005 */ // Label 82: @129005
46471 /* 129005 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3947*/ GIMT_Encode4(129166),
46472 /* 129016 */ /*GILLT_s16*//*Label 3944*/ GIMT_Encode4(129028),
46473 /* 129020 */ /*GILLT_s32*//*Label 3945*/ GIMT_Encode4(129074),
46474 /* 129024 */ /*GILLT_s64*//*Label 3946*/ GIMT_Encode4(129120),
46475 /* 129028 */ // Label 3944: @129028
46476 /* 129028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3948*/ GIMT_Encode4(129073), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 620 //
46477 /* 129035 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46478 /* 129038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46479 /* 129041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46480 /* 129045 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46481 /* 129049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46482 /* 129053 */ // (strict_fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46483 /* 129053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
46484 /* 129056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46485 /* 129058 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46486 /* 129060 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46487 /* 129062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46488 /* 129065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46489 /* 129071 */ GIR_RootConstrainSelectedInstOperands,
46490 /* 129072 */ // GIR_Coverage, 620,
46491 /* 129072 */ GIR_EraseRootFromParent_Done,
46492 /* 129073 */ // Label 3948: @129073
46493 /* 129073 */ GIM_Reject,
46494 /* 129074 */ // Label 3945: @129074
46495 /* 129074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3949*/ GIMT_Encode4(129119), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 618 //
46496 /* 129081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46497 /* 129084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46498 /* 129087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46499 /* 129091 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46500 /* 129095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46501 /* 129099 */ // (strict_fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46502 /* 129099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
46503 /* 129102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46504 /* 129104 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46505 /* 129106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46506 /* 129108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46507 /* 129111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46508 /* 129117 */ GIR_RootConstrainSelectedInstOperands,
46509 /* 129118 */ // GIR_Coverage, 618,
46510 /* 129118 */ GIR_EraseRootFromParent_Done,
46511 /* 129119 */ // Label 3949: @129119
46512 /* 129119 */ GIM_Reject,
46513 /* 129120 */ // Label 3946: @129120
46514 /* 129120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3950*/ GIMT_Encode4(129165), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 616 //
46515 /* 129127 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46516 /* 129130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46517 /* 129133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46518 /* 129137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46519 /* 129141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46520 /* 129145 */ // (strict_fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46521 /* 129145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
46522 /* 129148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46523 /* 129150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46524 /* 129152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46525 /* 129154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46526 /* 129157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46527 /* 129163 */ GIR_RootConstrainSelectedInstOperands,
46528 /* 129164 */ // GIR_Coverage, 616,
46529 /* 129164 */ GIR_EraseRootFromParent_Done,
46530 /* 129165 */ // Label 3950: @129165
46531 /* 129165 */ GIM_Reject,
46532 /* 129166 */ // Label 3947: @129166
46533 /* 129166 */ GIM_Reject,
46534 /* 129167 */ // Label 83: @129167
46535 /* 129167 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3954*/ GIMT_Encode4(129328),
46536 /* 129178 */ /*GILLT_s16*//*Label 3951*/ GIMT_Encode4(129190),
46537 /* 129182 */ /*GILLT_s32*//*Label 3952*/ GIMT_Encode4(129236),
46538 /* 129186 */ /*GILLT_s64*//*Label 3953*/ GIMT_Encode4(129282),
46539 /* 129190 */ // Label 3951: @129190
46540 /* 129190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3955*/ GIMT_Encode4(129235), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 626 //
46541 /* 129197 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46542 /* 129200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46543 /* 129203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46544 /* 129207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46545 /* 129211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46546 /* 129215 */ // (strict_fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46547 /* 129215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
46548 /* 129218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46549 /* 129220 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46550 /* 129222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46551 /* 129224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46552 /* 129227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46553 /* 129233 */ GIR_RootConstrainSelectedInstOperands,
46554 /* 129234 */ // GIR_Coverage, 626,
46555 /* 129234 */ GIR_EraseRootFromParent_Done,
46556 /* 129235 */ // Label 3955: @129235
46557 /* 129235 */ GIM_Reject,
46558 /* 129236 */ // Label 3952: @129236
46559 /* 129236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3956*/ GIMT_Encode4(129281), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 624 //
46560 /* 129243 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46561 /* 129246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46562 /* 129249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46563 /* 129253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46564 /* 129257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46565 /* 129261 */ // (strict_fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46566 /* 129261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
46567 /* 129264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46568 /* 129266 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46569 /* 129268 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46570 /* 129270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46571 /* 129273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46572 /* 129279 */ GIR_RootConstrainSelectedInstOperands,
46573 /* 129280 */ // GIR_Coverage, 624,
46574 /* 129280 */ GIR_EraseRootFromParent_Done,
46575 /* 129281 */ // Label 3956: @129281
46576 /* 129281 */ GIM_Reject,
46577 /* 129282 */ // Label 3953: @129282
46578 /* 129282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3957*/ GIMT_Encode4(129327), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 622 //
46579 /* 129289 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46580 /* 129292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46581 /* 129295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46582 /* 129299 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46583 /* 129303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46584 /* 129307 */ // (strict_fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46585 /* 129307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
46586 /* 129310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46587 /* 129312 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46588 /* 129314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46589 /* 129316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46590 /* 129319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46591 /* 129325 */ GIR_RootConstrainSelectedInstOperands,
46592 /* 129326 */ // GIR_Coverage, 622,
46593 /* 129326 */ GIR_EraseRootFromParent_Done,
46594 /* 129327 */ // Label 3957: @129327
46595 /* 129327 */ GIM_Reject,
46596 /* 129328 */ // Label 3954: @129328
46597 /* 129328 */ GIM_Reject,
46598 /* 129329 */ // Label 84: @129329
46599 /* 129329 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3961*/ GIMT_Encode4(129490),
46600 /* 129340 */ /*GILLT_s16*//*Label 3958*/ GIMT_Encode4(129352),
46601 /* 129344 */ /*GILLT_s32*//*Label 3959*/ GIMT_Encode4(129398),
46602 /* 129348 */ /*GILLT_s64*//*Label 3960*/ GIMT_Encode4(129444),
46603 /* 129352 */ // Label 3958: @129352
46604 /* 129352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3962*/ GIMT_Encode4(129397), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 638 //
46605 /* 129359 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46606 /* 129362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46607 /* 129365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46608 /* 129369 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46609 /* 129373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46610 /* 129377 */ // (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46611 /* 129377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
46612 /* 129380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46613 /* 129382 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46614 /* 129384 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46615 /* 129386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46616 /* 129389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46617 /* 129395 */ GIR_RootConstrainSelectedInstOperands,
46618 /* 129396 */ // GIR_Coverage, 638,
46619 /* 129396 */ GIR_EraseRootFromParent_Done,
46620 /* 129397 */ // Label 3962: @129397
46621 /* 129397 */ GIM_Reject,
46622 /* 129398 */ // Label 3959: @129398
46623 /* 129398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3963*/ GIMT_Encode4(129443), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 636 //
46624 /* 129405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46625 /* 129408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46626 /* 129411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46627 /* 129415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46628 /* 129419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46629 /* 129423 */ // (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46630 /* 129423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
46631 /* 129426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46632 /* 129428 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46633 /* 129430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46634 /* 129432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46635 /* 129435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46636 /* 129441 */ GIR_RootConstrainSelectedInstOperands,
46637 /* 129442 */ // GIR_Coverage, 636,
46638 /* 129442 */ GIR_EraseRootFromParent_Done,
46639 /* 129443 */ // Label 3963: @129443
46640 /* 129443 */ GIM_Reject,
46641 /* 129444 */ // Label 3960: @129444
46642 /* 129444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3964*/ GIMT_Encode4(129489), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 634 //
46643 /* 129451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46644 /* 129454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46645 /* 129457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46646 /* 129461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46647 /* 129465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46648 /* 129469 */ // (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46649 /* 129469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
46650 /* 129472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46651 /* 129474 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46652 /* 129476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46653 /* 129478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46654 /* 129481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46655 /* 129487 */ GIR_RootConstrainSelectedInstOperands,
46656 /* 129488 */ // GIR_Coverage, 634,
46657 /* 129488 */ GIR_EraseRootFromParent_Done,
46658 /* 129489 */ // Label 3964: @129489
46659 /* 129489 */ GIM_Reject,
46660 /* 129490 */ // Label 3961: @129490
46661 /* 129490 */ GIM_Reject,
46662 /* 129491 */ // Label 85: @129491
46663 /* 129491 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3968*/ GIMT_Encode4(129652),
46664 /* 129502 */ /*GILLT_s16*//*Label 3965*/ GIMT_Encode4(129514),
46665 /* 129506 */ /*GILLT_s32*//*Label 3966*/ GIMT_Encode4(129560),
46666 /* 129510 */ /*GILLT_s64*//*Label 3967*/ GIMT_Encode4(129606),
46667 /* 129514 */ // Label 3965: @129514
46668 /* 129514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3969*/ GIMT_Encode4(129559), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 632 //
46669 /* 129521 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46670 /* 129524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46671 /* 129527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46672 /* 129531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46673 /* 129535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46674 /* 129539 */ // (strict_fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46675 /* 129539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
46676 /* 129542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46677 /* 129544 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46678 /* 129546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46679 /* 129548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46680 /* 129551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46681 /* 129557 */ GIR_RootConstrainSelectedInstOperands,
46682 /* 129558 */ // GIR_Coverage, 632,
46683 /* 129558 */ GIR_EraseRootFromParent_Done,
46684 /* 129559 */ // Label 3969: @129559
46685 /* 129559 */ GIM_Reject,
46686 /* 129560 */ // Label 3966: @129560
46687 /* 129560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3970*/ GIMT_Encode4(129605), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 630 //
46688 /* 129567 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46689 /* 129570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46690 /* 129573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46691 /* 129577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46692 /* 129581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46693 /* 129585 */ // (strict_fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46694 /* 129585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
46695 /* 129588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46696 /* 129590 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46697 /* 129592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46698 /* 129594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46699 /* 129597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46700 /* 129603 */ GIR_RootConstrainSelectedInstOperands,
46701 /* 129604 */ // GIR_Coverage, 630,
46702 /* 129604 */ GIR_EraseRootFromParent_Done,
46703 /* 129605 */ // Label 3970: @129605
46704 /* 129605 */ GIM_Reject,
46705 /* 129606 */ // Label 3967: @129606
46706 /* 129606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3971*/ GIMT_Encode4(129651), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 628 //
46707 /* 129613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46708 /* 129616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46709 /* 129619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46710 /* 129623 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46711 /* 129627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46712 /* 129631 */ // (strict_fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46713 /* 129631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
46714 /* 129634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46715 /* 129636 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46716 /* 129638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46717 /* 129640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46718 /* 129643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46719 /* 129649 */ GIR_RootConstrainSelectedInstOperands,
46720 /* 129650 */ // GIR_Coverage, 628,
46721 /* 129650 */ GIR_EraseRootFromParent_Done,
46722 /* 129651 */ // Label 3971: @129651
46723 /* 129651 */ GIM_Reject,
46724 /* 129652 */ // Label 3968: @129652
46725 /* 129652 */ GIM_Reject,
46726 /* 129653 */ // Label 86: @129653
46727 /* 129653 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3975*/ GIMT_Encode4(130819),
46728 /* 129664 */ /*GILLT_s16*//*Label 3972*/ GIMT_Encode4(129676),
46729 /* 129668 */ /*GILLT_s32*//*Label 3973*/ GIMT_Encode4(130057),
46730 /* 129672 */ /*GILLT_s64*//*Label 3974*/ GIMT_Encode4(130438),
46731 /* 129676 */ // Label 3972: @129676
46732 /* 129676 */ GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(130056),
46733 /* 129681 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46734 /* 129684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46735 /* 129687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
46736 /* 129690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46737 /* 129694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3977*/ GIMT_Encode4(129767), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2774 //
46738 /* 129701 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46739 /* 129705 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46740 /* 129709 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46741 /* 129713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46742 /* 129718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46743 /* 129722 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46744 /* 129726 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46745 /* 129730 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
46746 /* 129734 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46747 /* 129739 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46748 /* 129741 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46749 /* 129741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
46750 /* 129744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46751 /* 129746 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46752 /* 129750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46753 /* 129754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46754 /* 129756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46755 /* 129759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46756 /* 129765 */ GIR_RootConstrainSelectedInstOperands,
46757 /* 129766 */ // GIR_Coverage, 2774,
46758 /* 129766 */ GIR_EraseRootFromParent_Done,
46759 /* 129767 */ // Label 3977: @129767
46760 /* 129767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3978*/ GIMT_Encode4(129840), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6339 //
46761 /* 129774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46762 /* 129778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46763 /* 129782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46764 /* 129786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46765 /* 129790 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46766 /* 129795 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46767 /* 129799 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46768 /* 129803 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
46769 /* 129807 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46770 /* 129812 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46771 /* 129814 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46772 /* 129814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
46773 /* 129817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46774 /* 129819 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46775 /* 129823 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46776 /* 129827 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46777 /* 129829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46778 /* 129832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46779 /* 129838 */ GIR_RootConstrainSelectedInstOperands,
46780 /* 129839 */ // GIR_Coverage, 6339,
46781 /* 129839 */ GIR_EraseRootFromParent_Done,
46782 /* 129840 */ // Label 3978: @129840
46783 /* 129840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3979*/ GIMT_Encode4(129898), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2754 //
46784 /* 129847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46785 /* 129851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46786 /* 129855 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46787 /* 129859 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46788 /* 129864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46789 /* 129868 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46790 /* 129872 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46791 /* 129874 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46792 /* 129874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
46793 /* 129877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46794 /* 129879 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46795 /* 129881 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46796 /* 129885 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46797 /* 129887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46798 /* 129890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46799 /* 129896 */ GIR_RootConstrainSelectedInstOperands,
46800 /* 129897 */ // GIR_Coverage, 2754,
46801 /* 129897 */ GIR_EraseRootFromParent_Done,
46802 /* 129898 */ // Label 3979: @129898
46803 /* 129898 */ GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(130055),
46804 /* 129903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46805 /* 129907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3981*/ GIMT_Encode4(129961), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6333 //
46806 /* 129914 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46807 /* 129918 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46808 /* 129922 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46809 /* 129926 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46810 /* 129931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46811 /* 129935 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46812 /* 129937 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46813 /* 129937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
46814 /* 129940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46815 /* 129942 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46816 /* 129944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46817 /* 129948 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46818 /* 129950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46819 /* 129953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46820 /* 129959 */ GIR_RootConstrainSelectedInstOperands,
46821 /* 129960 */ // GIR_Coverage, 6333,
46822 /* 129960 */ GIR_EraseRootFromParent_Done,
46823 /* 129961 */ // Label 3981: @129961
46824 /* 129961 */ GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(130054),
46825 /* 129966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46826 /* 129970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3983*/ GIMT_Encode4(130020), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2788 //
46827 /* 129977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46828 /* 129981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46829 /* 129985 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46830 /* 129989 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46831 /* 129994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46832 /* 129996 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46833 /* 129996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
46834 /* 129999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46835 /* 130001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
46836 /* 130005 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46837 /* 130007 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46838 /* 130009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46839 /* 130012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46840 /* 130018 */ GIR_RootConstrainSelectedInstOperands,
46841 /* 130019 */ // GIR_Coverage, 2788,
46842 /* 130019 */ GIR_EraseRootFromParent_Done,
46843 /* 130020 */ // Label 3983: @130020
46844 /* 130020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3984*/ GIMT_Encode4(130053), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2736 //
46845 /* 130027 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46846 /* 130031 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46847 /* 130031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
46848 /* 130034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46849 /* 130036 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46850 /* 130038 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46851 /* 130040 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46852 /* 130042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46853 /* 130045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46854 /* 130051 */ GIR_RootConstrainSelectedInstOperands,
46855 /* 130052 */ // GIR_Coverage, 2736,
46856 /* 130052 */ GIR_EraseRootFromParent_Done,
46857 /* 130053 */ // Label 3984: @130053
46858 /* 130053 */ GIM_Reject,
46859 /* 130054 */ // Label 3982: @130054
46860 /* 130054 */ GIM_Reject,
46861 /* 130055 */ // Label 3980: @130055
46862 /* 130055 */ GIM_Reject,
46863 /* 130056 */ // Label 3976: @130056
46864 /* 130056 */ GIM_Reject,
46865 /* 130057 */ // Label 3973: @130057
46866 /* 130057 */ GIM_Try, /*On fail goto*//*Label 3985*/ GIMT_Encode4(130437),
46867 /* 130062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46868 /* 130065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46869 /* 130068 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
46870 /* 130071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46871 /* 130075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3986*/ GIMT_Encode4(130148), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2772 //
46872 /* 130082 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46873 /* 130086 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46874 /* 130090 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46875 /* 130094 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46876 /* 130099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46877 /* 130103 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46878 /* 130107 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46879 /* 130111 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
46880 /* 130115 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46881 /* 130120 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46882 /* 130122 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46883 /* 130122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
46884 /* 130125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46885 /* 130127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46886 /* 130131 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46887 /* 130135 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46888 /* 130137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46889 /* 130140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46890 /* 130146 */ GIR_RootConstrainSelectedInstOperands,
46891 /* 130147 */ // GIR_Coverage, 2772,
46892 /* 130147 */ GIR_EraseRootFromParent_Done,
46893 /* 130148 */ // Label 3986: @130148
46894 /* 130148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3987*/ GIMT_Encode4(130221), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6337 //
46895 /* 130155 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46896 /* 130159 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46897 /* 130163 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46898 /* 130167 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46899 /* 130171 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46900 /* 130176 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46901 /* 130180 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46902 /* 130184 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
46903 /* 130188 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46904 /* 130193 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46905 /* 130195 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46906 /* 130195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
46907 /* 130198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46908 /* 130200 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46909 /* 130204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46910 /* 130208 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46911 /* 130210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46912 /* 130213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46913 /* 130219 */ GIR_RootConstrainSelectedInstOperands,
46914 /* 130220 */ // GIR_Coverage, 6337,
46915 /* 130220 */ GIR_EraseRootFromParent_Done,
46916 /* 130221 */ // Label 3987: @130221
46917 /* 130221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3988*/ GIMT_Encode4(130279), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2752 //
46918 /* 130228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46919 /* 130232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46920 /* 130236 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46921 /* 130240 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46922 /* 130245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46923 /* 130249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46924 /* 130253 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46925 /* 130255 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46926 /* 130255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
46927 /* 130258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46928 /* 130260 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46929 /* 130262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46930 /* 130266 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46931 /* 130268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46932 /* 130271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46933 /* 130277 */ GIR_RootConstrainSelectedInstOperands,
46934 /* 130278 */ // GIR_Coverage, 2752,
46935 /* 130278 */ GIR_EraseRootFromParent_Done,
46936 /* 130279 */ // Label 3988: @130279
46937 /* 130279 */ GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(130436),
46938 /* 130284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46939 /* 130288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3990*/ GIMT_Encode4(130342), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6331 //
46940 /* 130295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46941 /* 130299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46942 /* 130303 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46943 /* 130307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46944 /* 130312 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46945 /* 130316 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46946 /* 130318 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46947 /* 130318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
46948 /* 130321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46949 /* 130323 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46950 /* 130325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46951 /* 130329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46952 /* 130331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46953 /* 130334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46954 /* 130340 */ GIR_RootConstrainSelectedInstOperands,
46955 /* 130341 */ // GIR_Coverage, 6331,
46956 /* 130341 */ GIR_EraseRootFromParent_Done,
46957 /* 130342 */ // Label 3990: @130342
46958 /* 130342 */ GIM_Try, /*On fail goto*//*Label 3991*/ GIMT_Encode4(130435),
46959 /* 130347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46960 /* 130351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3992*/ GIMT_Encode4(130401), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2786 //
46961 /* 130358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46962 /* 130362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46963 /* 130366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46964 /* 130370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46965 /* 130375 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46966 /* 130377 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46967 /* 130377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
46968 /* 130380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46969 /* 130382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
46970 /* 130386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46971 /* 130388 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46972 /* 130390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46973 /* 130393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46974 /* 130399 */ GIR_RootConstrainSelectedInstOperands,
46975 /* 130400 */ // GIR_Coverage, 2786,
46976 /* 130400 */ GIR_EraseRootFromParent_Done,
46977 /* 130401 */ // Label 3992: @130401
46978 /* 130401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3993*/ GIMT_Encode4(130434), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2734 //
46979 /* 130408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46980 /* 130412 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46981 /* 130412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
46982 /* 130415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46983 /* 130417 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46984 /* 130419 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46985 /* 130421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46986 /* 130423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46987 /* 130426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46988 /* 130432 */ GIR_RootConstrainSelectedInstOperands,
46989 /* 130433 */ // GIR_Coverage, 2734,
46990 /* 130433 */ GIR_EraseRootFromParent_Done,
46991 /* 130434 */ // Label 3993: @130434
46992 /* 130434 */ GIM_Reject,
46993 /* 130435 */ // Label 3991: @130435
46994 /* 130435 */ GIM_Reject,
46995 /* 130436 */ // Label 3989: @130436
46996 /* 130436 */ GIM_Reject,
46997 /* 130437 */ // Label 3985: @130437
46998 /* 130437 */ GIM_Reject,
46999 /* 130438 */ // Label 3974: @130438
47000 /* 130438 */ GIM_Try, /*On fail goto*//*Label 3994*/ GIMT_Encode4(130818),
47001 /* 130443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
47002 /* 130446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47003 /* 130449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47004 /* 130452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47005 /* 130456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3995*/ GIMT_Encode4(130529), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2770 //
47006 /* 130463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47007 /* 130467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
47008 /* 130471 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
47009 /* 130475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47010 /* 130480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47011 /* 130484 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
47012 /* 130488 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
47013 /* 130492 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
47014 /* 130496 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47015 /* 130501 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
47016 /* 130503 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
47017 /* 130503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
47018 /* 130506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
47019 /* 130508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
47020 /* 130512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
47021 /* 130516 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
47022 /* 130518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47023 /* 130521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47024 /* 130527 */ GIR_RootConstrainSelectedInstOperands,
47025 /* 130528 */ // GIR_Coverage, 2770,
47026 /* 130528 */ GIR_EraseRootFromParent_Done,
47027 /* 130529 */ // Label 3995: @130529
47028 /* 130529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3996*/ GIMT_Encode4(130602), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6335 //
47029 /* 130536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47030 /* 130540 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47031 /* 130544 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
47032 /* 130548 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
47033 /* 130552 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47034 /* 130557 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
47035 /* 130561 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
47036 /* 130565 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
47037 /* 130569 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47038 /* 130574 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
47039 /* 130576 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
47040 /* 130576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
47041 /* 130579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
47042 /* 130581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
47043 /* 130585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
47044 /* 130589 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
47045 /* 130591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47046 /* 130594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47047 /* 130600 */ GIR_RootConstrainSelectedInstOperands,
47048 /* 130601 */ // GIR_Coverage, 6335,
47049 /* 130601 */ GIR_EraseRootFromParent_Done,
47050 /* 130602 */ // Label 3996: @130602
47051 /* 130602 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3997*/ GIMT_Encode4(130660), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2750 //
47052 /* 130609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47053 /* 130613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
47054 /* 130617 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
47055 /* 130621 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47056 /* 130626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47057 /* 130630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47058 /* 130634 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47059 /* 130636 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
47060 /* 130636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
47061 /* 130639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
47062 /* 130641 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
47063 /* 130643 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
47064 /* 130647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
47065 /* 130649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47066 /* 130652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47067 /* 130658 */ GIR_RootConstrainSelectedInstOperands,
47068 /* 130659 */ // GIR_Coverage, 2750,
47069 /* 130659 */ GIR_EraseRootFromParent_Done,
47070 /* 130660 */ // Label 3997: @130660
47071 /* 130660 */ GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(130817),
47072 /* 130665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47073 /* 130669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3999*/ GIMT_Encode4(130723), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6329 //
47074 /* 130676 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47075 /* 130680 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
47076 /* 130684 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
47077 /* 130688 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47078 /* 130693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47079 /* 130697 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47080 /* 130699 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
47081 /* 130699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
47082 /* 130702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
47083 /* 130704 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
47084 /* 130706 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
47085 /* 130710 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
47086 /* 130712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47087 /* 130715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47088 /* 130721 */ GIR_RootConstrainSelectedInstOperands,
47089 /* 130722 */ // GIR_Coverage, 6329,
47090 /* 130722 */ GIR_EraseRootFromParent_Done,
47091 /* 130723 */ // Label 3999: @130723
47092 /* 130723 */ GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(130816),
47093 /* 130728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47094 /* 130732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4001*/ GIMT_Encode4(130782), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2784 //
47095 /* 130739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47096 /* 130743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
47097 /* 130747 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
47098 /* 130751 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47099 /* 130756 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47100 /* 130758 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
47101 /* 130758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
47102 /* 130761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
47103 /* 130763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
47104 /* 130767 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
47105 /* 130769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
47106 /* 130771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47107 /* 130774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47108 /* 130780 */ GIR_RootConstrainSelectedInstOperands,
47109 /* 130781 */ // GIR_Coverage, 2784,
47110 /* 130781 */ GIR_EraseRootFromParent_Done,
47111 /* 130782 */ // Label 4001: @130782
47112 /* 130782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4002*/ GIMT_Encode4(130815), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2732 //
47113 /* 130789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47114 /* 130793 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
47115 /* 130793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
47116 /* 130796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
47117 /* 130798 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
47118 /* 130800 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
47119 /* 130802 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
47120 /* 130804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47121 /* 130807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47122 /* 130813 */ GIR_RootConstrainSelectedInstOperands,
47123 /* 130814 */ // GIR_Coverage, 2732,
47124 /* 130814 */ GIR_EraseRootFromParent_Done,
47125 /* 130815 */ // Label 4002: @130815
47126 /* 130815 */ GIM_Reject,
47127 /* 130816 */ // Label 4000: @130816
47128 /* 130816 */ GIM_Reject,
47129 /* 130817 */ // Label 3998: @130817
47130 /* 130817 */ GIM_Reject,
47131 /* 130818 */ // Label 3994: @130818
47132 /* 130818 */ GIM_Reject,
47133 /* 130819 */ // Label 3975: @130819
47134 /* 130819 */ GIM_Reject,
47135 /* 130820 */ // Label 87: @130820
47136 /* 130820 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 4006*/ GIMT_Encode4(130954),
47137 /* 130831 */ /*GILLT_s16*//*Label 4003*/ GIMT_Encode4(130843),
47138 /* 130835 */ /*GILLT_s32*//*Label 4004*/ GIMT_Encode4(130880),
47139 /* 130839 */ /*GILLT_s64*//*Label 4005*/ GIMT_Encode4(130917),
47140 /* 130843 */ // Label 4003: @130843
47141 /* 130843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4007*/ GIMT_Encode4(130879), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 738 //
47142 /* 130850 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
47143 /* 130853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
47144 /* 130857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
47145 /* 130861 */ // (strict_fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
47146 /* 130861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
47147 /* 130864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
47148 /* 130866 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
47149 /* 130868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47150 /* 130871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47151 /* 130877 */ GIR_RootConstrainSelectedInstOperands,
47152 /* 130878 */ // GIR_Coverage, 738,
47153 /* 130878 */ GIR_EraseRootFromParent_Done,
47154 /* 130879 */ // Label 4007: @130879
47155 /* 130879 */ GIM_Reject,
47156 /* 130880 */ // Label 4004: @130880
47157 /* 130880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4008*/ GIMT_Encode4(130916), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 736 //
47158 /* 130887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
47159 /* 130890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
47160 /* 130894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
47161 /* 130898 */ // (strict_fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
47162 /* 130898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
47163 /* 130901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
47164 /* 130903 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
47165 /* 130905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47166 /* 130908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47167 /* 130914 */ GIR_RootConstrainSelectedInstOperands,
47168 /* 130915 */ // GIR_Coverage, 736,
47169 /* 130915 */ GIR_EraseRootFromParent_Done,
47170 /* 130916 */ // Label 4008: @130916
47171 /* 130916 */ GIM_Reject,
47172 /* 130917 */ // Label 4005: @130917
47173 /* 130917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4009*/ GIMT_Encode4(130953), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 734 //
47174 /* 130924 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
47175 /* 130927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47176 /* 130931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47177 /* 130935 */ // (strict_fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
47178 /* 130935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
47179 /* 130938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
47180 /* 130940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
47181 /* 130942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47182 /* 130945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47183 /* 130951 */ GIR_RootConstrainSelectedInstOperands,
47184 /* 130952 */ // GIR_Coverage, 734,
47185 /* 130952 */ GIR_EraseRootFromParent_Done,
47186 /* 130953 */ // Label 4009: @130953
47187 /* 130953 */ GIM_Reject,
47188 /* 130954 */ // Label 4006: @130954
47189 /* 130954 */ GIM_Reject,
47190 /* 130955 */ // Label 88: @130955
47191 /* 130955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4010*/ GIMT_Encode4(130969), GIMT_Encode2(GIFBS_IsARM), // Rule ID 12 //
47192 /* 130962 */ // (trap) => (TRAP)
47193 /* 130962 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP),
47194 /* 130967 */ GIR_RootConstrainSelectedInstOperands,
47195 /* 130968 */ // GIR_Coverage, 12,
47196 /* 130968 */ GIR_Done,
47197 /* 130969 */ // Label 4010: @130969
47198 /* 130969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4011*/ GIMT_Encode4(130983), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 284 //
47199 /* 130976 */ // (trap) => (tTRAP)
47200 /* 130976 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP),
47201 /* 130981 */ GIR_RootConstrainSelectedInstOperands,
47202 /* 130982 */ // GIR_Coverage, 284,
47203 /* 130982 */ GIR_Done,
47204 /* 130983 */ // Label 4011: @130983
47205 /* 130983 */ GIM_Reject,
47206 /* 130984 */ // Label 89: @130984
47207 /* 130984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4012*/ GIMT_Encode4(130999), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 2026 //
47208 /* 130991 */ // (debugtrap) => (BKPT 0:{ *:[i32] })
47209 /* 130991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT),
47210 /* 130994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47211 /* 130997 */ GIR_RootConstrainSelectedInstOperands,
47212 /* 130998 */ // GIR_Coverage, 2026,
47213 /* 130998 */ GIR_EraseRootFromParent_Done,
47214 /* 130999 */ // Label 4012: @130999
47215 /* 130999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4013*/ GIMT_Encode4(131025), GIMT_Encode2(GIFBS_IsARM_NoV5T), // Rule ID 2027 //
47216 /* 131006 */ // (debugtrap) => (UDF 254:{ *:[i32] })
47217 /* 131006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
47218 /* 131009 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
47219 /* 131019 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
47220 /* 131023 */ GIR_RootConstrainSelectedInstOperands,
47221 /* 131024 */ // GIR_Coverage, 2027,
47222 /* 131024 */ GIR_EraseRootFromParent_Done,
47223 /* 131025 */ // Label 4013: @131025
47224 /* 131025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4014*/ GIMT_Encode4(131040), GIMT_Encode2(GIFBS_HasV5T_IsThumb), // Rule ID 2219 //
47225 /* 131032 */ // (debugtrap) => (tBKPT 0:{ *:[i32] })
47226 /* 131032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT),
47227 /* 131035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47228 /* 131038 */ GIR_RootConstrainSelectedInstOperands,
47229 /* 131039 */ // GIR_Coverage, 2219,
47230 /* 131039 */ GIR_EraseRootFromParent_Done,
47231 /* 131040 */ // Label 4014: @131040
47232 /* 131040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4015*/ GIMT_Encode4(131066), GIMT_Encode2(GIFBS_IsThumb_NoV5T), // Rule ID 2220 //
47233 /* 131047 */ // (debugtrap) => (tUDF 254:{ *:[i32] })
47234 /* 131047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
47235 /* 131050 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
47236 /* 131060 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
47237 /* 131064 */ GIR_RootConstrainSelectedInstOperands,
47238 /* 131065 */ // GIR_Coverage, 2220,
47239 /* 131065 */ GIR_EraseRootFromParent_Done,
47240 /* 131066 */ // Label 4015: @131066
47241 /* 131066 */ GIM_Reject,
47242 /* 131067 */ // Label 90: @131067
47243 /* 131067 */ GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(131440),
47244 /* 131072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47245 /* 131075 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4020*/ GIMT_Encode4(131439),
47246 /* 131086 */ /*GILLT_v16s8*//*Label 4017*/ GIMT_Encode4(131106), GIMT_Encode4(0),
47247 /* 131094 */ /*GILLT_v8s16*//*Label 4018*/ GIMT_Encode4(131217), GIMT_Encode4(0),
47248 /* 131102 */ /*GILLT_v4s32*//*Label 4019*/ GIMT_Encode4(131328),
47249 /* 131106 */ // Label 4017: @131106
47250 /* 131106 */ GIM_Try, /*On fail goto*//*Label 4021*/ GIMT_Encode4(131216),
47251 /* 131111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
47252 /* 131115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4022*/ GIMT_Encode4(131180), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3636 //
47253 /* 131122 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47254 /* 131126 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
47255 /* 131130 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47256 /* 131134 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
47257 /* 131138 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47258 /* 131143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47259 /* 131148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47260 /* 131150 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
47261 /* 131150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
47262 /* 131153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47263 /* 131155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
47264 /* 131159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
47265 /* 131163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47266 /* 131166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47267 /* 131172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47268 /* 131178 */ GIR_RootConstrainSelectedInstOperands,
47269 /* 131179 */ // GIR_Coverage, 3636,
47270 /* 131179 */ GIR_EraseRootFromParent_Done,
47271 /* 131180 */ // Label 4022: @131180
47272 /* 131180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4023*/ GIMT_Encode4(131215), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3440 //
47273 /* 131187 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47274 /* 131191 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec)
47275 /* 131191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc),
47276 /* 131194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
47277 /* 131196 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
47278 /* 131198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47279 /* 131201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47280 /* 131207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47281 /* 131213 */ GIR_RootConstrainSelectedInstOperands,
47282 /* 131214 */ // GIR_Coverage, 3440,
47283 /* 131214 */ GIR_EraseRootFromParent_Done,
47284 /* 131215 */ // Label 4023: @131215
47285 /* 131215 */ GIM_Reject,
47286 /* 131216 */ // Label 4021: @131216
47287 /* 131216 */ GIM_Reject,
47288 /* 131217 */ // Label 4018: @131217
47289 /* 131217 */ GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(131327),
47290 /* 131222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
47291 /* 131226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4025*/ GIMT_Encode4(131291), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3633 //
47292 /* 131233 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47293 /* 131237 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
47294 /* 131241 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47295 /* 131245 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
47296 /* 131249 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47297 /* 131254 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47298 /* 131259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47299 /* 131261 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
47300 /* 131261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
47301 /* 131264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47302 /* 131266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
47303 /* 131270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
47304 /* 131274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47305 /* 131277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47306 /* 131283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47307 /* 131289 */ GIR_RootConstrainSelectedInstOperands,
47308 /* 131290 */ // GIR_Coverage, 3633,
47309 /* 131290 */ GIR_EraseRootFromParent_Done,
47310 /* 131291 */ // Label 4025: @131291
47311 /* 131291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4026*/ GIMT_Encode4(131326), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3468 //
47312 /* 131298 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47313 /* 131302 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec)
47314 /* 131302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc),
47315 /* 131305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
47316 /* 131307 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
47317 /* 131309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47318 /* 131312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47319 /* 131318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47320 /* 131324 */ GIR_RootConstrainSelectedInstOperands,
47321 /* 131325 */ // GIR_Coverage, 3468,
47322 /* 131325 */ GIR_EraseRootFromParent_Done,
47323 /* 131326 */ // Label 4026: @131326
47324 /* 131326 */ GIM_Reject,
47325 /* 131327 */ // Label 4024: @131327
47326 /* 131327 */ GIM_Reject,
47327 /* 131328 */ // Label 4019: @131328
47328 /* 131328 */ GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(131438),
47329 /* 131333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
47330 /* 131337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4028*/ GIMT_Encode4(131402), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3632 //
47331 /* 131344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47332 /* 131348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
47333 /* 131352 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47334 /* 131356 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
47335 /* 131360 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47336 /* 131365 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47337 /* 131370 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47338 /* 131372 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
47339 /* 131372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
47340 /* 131375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47341 /* 131377 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
47342 /* 131381 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
47343 /* 131385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47344 /* 131388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47345 /* 131394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47346 /* 131400 */ GIR_RootConstrainSelectedInstOperands,
47347 /* 131401 */ // GIR_Coverage, 3632,
47348 /* 131401 */ GIR_EraseRootFromParent_Done,
47349 /* 131402 */ // Label 4028: @131402
47350 /* 131402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4029*/ GIMT_Encode4(131437), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3478 //
47351 /* 131409 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47352 /* 131413 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec)
47353 /* 131413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc),
47354 /* 131416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
47355 /* 131418 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
47356 /* 131420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47357 /* 131423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47358 /* 131429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47359 /* 131435 */ GIR_RootConstrainSelectedInstOperands,
47360 /* 131436 */ // GIR_Coverage, 3478,
47361 /* 131436 */ GIR_EraseRootFromParent_Done,
47362 /* 131437 */ // Label 4029: @131437
47363 /* 131437 */ GIM_Reject,
47364 /* 131438 */ // Label 4027: @131438
47365 /* 131438 */ GIM_Reject,
47366 /* 131439 */ // Label 4020: @131439
47367 /* 131439 */ GIM_Reject,
47368 /* 131440 */ // Label 4016: @131440
47369 /* 131440 */ GIM_Reject,
47370 /* 131441 */ // Label 91: @131441
47371 /* 131441 */ GIM_Try, /*On fail goto*//*Label 4030*/ GIMT_Encode4(131705),
47372 /* 131446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47373 /* 131449 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4034*/ GIMT_Encode4(131704),
47374 /* 131460 */ /*GILLT_v16s8*//*Label 4031*/ GIMT_Encode4(131480), GIMT_Encode4(0),
47375 /* 131468 */ /*GILLT_v8s16*//*Label 4032*/ GIMT_Encode4(131555), GIMT_Encode4(0),
47376 /* 131476 */ /*GILLT_v4s32*//*Label 4033*/ GIMT_Encode4(131622),
47377 /* 131480 */ // Label 4031: @131480
47378 /* 131480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4035*/ GIMT_Encode4(131554), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3536 //
47379 /* 131487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47380 /* 131491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47381 /* 131495 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47382 /* 131495 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47383 /* 131498 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
47384 /* 131502 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47385 /* 131507 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
47386 /* 131510 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47387 /* 131513 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47388 /* 131519 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47389 /* 131525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47390 /* 131527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
47391 /* 131530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47392 /* 131532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47393 /* 131535 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47394 /* 131537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47395 /* 131540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47396 /* 131546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47397 /* 131552 */ GIR_RootConstrainSelectedInstOperands,
47398 /* 131553 */ // GIR_Coverage, 3536,
47399 /* 131553 */ GIR_EraseRootFromParent_Done,
47400 /* 131554 */ // Label 4035: @131554
47401 /* 131554 */ GIM_Reject,
47402 /* 131555 */ // Label 4032: @131555
47403 /* 131555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4036*/ GIMT_Encode4(131621), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3537 //
47404 /* 131562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47405 /* 131566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47406 /* 131570 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47407 /* 131570 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47408 /* 131573 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
47409 /* 131577 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47410 /* 131582 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
47411 /* 131592 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47412 /* 131594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
47413 /* 131597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47414 /* 131599 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47415 /* 131602 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47416 /* 131604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47417 /* 131607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47418 /* 131613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47419 /* 131619 */ GIR_RootConstrainSelectedInstOperands,
47420 /* 131620 */ // GIR_Coverage, 3537,
47421 /* 131620 */ GIR_EraseRootFromParent_Done,
47422 /* 131621 */ // Label 4036: @131621
47423 /* 131621 */ GIM_Reject,
47424 /* 131622 */ // Label 4033: @131622
47425 /* 131622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4037*/ GIMT_Encode4(131703), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3538 //
47426 /* 131629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47427 /* 131633 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47428 /* 131637 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47429 /* 131637 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47430 /* 131640 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47431 /* 131644 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47432 /* 131649 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
47433 /* 131659 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47434 /* 131662 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47435 /* 131668 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47436 /* 131674 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47437 /* 131676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
47438 /* 131679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47439 /* 131681 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47440 /* 131684 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47441 /* 131686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47442 /* 131689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47443 /* 131695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47444 /* 131701 */ GIR_RootConstrainSelectedInstOperands,
47445 /* 131702 */ // GIR_Coverage, 3538,
47446 /* 131702 */ GIR_EraseRootFromParent_Done,
47447 /* 131703 */ // Label 4037: @131703
47448 /* 131703 */ GIM_Reject,
47449 /* 131704 */ // Label 4034: @131704
47450 /* 131704 */ GIM_Reject,
47451 /* 131705 */ // Label 4030: @131705
47452 /* 131705 */ GIM_Reject,
47453 /* 131706 */ // Label 92: @131706
47454 /* 131706 */ GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(131979),
47455 /* 131711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47456 /* 131714 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4042*/ GIMT_Encode4(131978),
47457 /* 131725 */ /*GILLT_v16s8*//*Label 4039*/ GIMT_Encode4(131745), GIMT_Encode4(0),
47458 /* 131733 */ /*GILLT_v8s16*//*Label 4040*/ GIMT_Encode4(131820), GIMT_Encode4(0),
47459 /* 131741 */ /*GILLT_v4s32*//*Label 4041*/ GIMT_Encode4(131896),
47460 /* 131745 */ // Label 4039: @131745
47461 /* 131745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4043*/ GIMT_Encode4(131819), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3542 //
47462 /* 131752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47463 /* 131756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47464 /* 131760 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47465 /* 131760 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47466 /* 131763 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47467 /* 131767 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47468 /* 131772 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
47469 /* 131775 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47470 /* 131778 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47471 /* 131784 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47472 /* 131790 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47473 /* 131792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
47474 /* 131795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47475 /* 131797 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47476 /* 131800 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47477 /* 131802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47478 /* 131805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47479 /* 131811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47480 /* 131817 */ GIR_RootConstrainSelectedInstOperands,
47481 /* 131818 */ // GIR_Coverage, 3542,
47482 /* 131818 */ GIR_EraseRootFromParent_Done,
47483 /* 131819 */ // Label 4043: @131819
47484 /* 131819 */ GIM_Reject,
47485 /* 131820 */ // Label 4040: @131820
47486 /* 131820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4044*/ GIMT_Encode4(131895), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3543 //
47487 /* 131827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47488 /* 131831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47489 /* 131835 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47490 /* 131835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47491 /* 131838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
47492 /* 131842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47493 /* 131847 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
47494 /* 131857 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47495 /* 131860 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47496 /* 131866 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47497 /* 131868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
47498 /* 131871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47499 /* 131873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47500 /* 131876 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47501 /* 131878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47502 /* 131881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47503 /* 131887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47504 /* 131893 */ GIR_RootConstrainSelectedInstOperands,
47505 /* 131894 */ // GIR_Coverage, 3543,
47506 /* 131894 */ GIR_EraseRootFromParent_Done,
47507 /* 131895 */ // Label 4044: @131895
47508 /* 131895 */ GIM_Reject,
47509 /* 131896 */ // Label 4041: @131896
47510 /* 131896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4045*/ GIMT_Encode4(131977), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3544 //
47511 /* 131903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47512 /* 131907 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47513 /* 131911 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47514 /* 131911 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47515 /* 131914 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
47516 /* 131918 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47517 /* 131923 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
47518 /* 131933 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47519 /* 131936 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47520 /* 131942 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47521 /* 131948 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47522 /* 131950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
47523 /* 131953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47524 /* 131955 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47525 /* 131958 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47526 /* 131960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47527 /* 131963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47528 /* 131969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47529 /* 131975 */ GIR_RootConstrainSelectedInstOperands,
47530 /* 131976 */ // GIR_Coverage, 3544,
47531 /* 131976 */ GIR_EraseRootFromParent_Done,
47532 /* 131977 */ // Label 4045: @131977
47533 /* 131977 */ GIM_Reject,
47534 /* 131978 */ // Label 4042: @131978
47535 /* 131978 */ GIM_Reject,
47536 /* 131979 */ // Label 4038: @131979
47537 /* 131979 */ GIM_Reject,
47538 /* 131980 */ // Label 93: @131980
47539 /* 131980 */ GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(132245),
47540 /* 131985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47541 /* 131988 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4050*/ GIMT_Encode4(132244),
47542 /* 131999 */ /*GILLT_v16s8*//*Label 4047*/ GIMT_Encode4(132019), GIMT_Encode4(0),
47543 /* 132007 */ /*GILLT_v8s16*//*Label 4048*/ GIMT_Encode4(132094), GIMT_Encode4(0),
47544 /* 132015 */ /*GILLT_v4s32*//*Label 4049*/ GIMT_Encode4(132169),
47545 /* 132019 */ // Label 4047: @132019
47546 /* 132019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4051*/ GIMT_Encode4(132093), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3539 //
47547 /* 132026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47548 /* 132030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47549 /* 132034 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47550 /* 132034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47551 /* 132037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47552 /* 132041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47553 /* 132046 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
47554 /* 132049 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47555 /* 132052 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47556 /* 132058 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47557 /* 132064 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47558 /* 132066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
47559 /* 132069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47560 /* 132071 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47561 /* 132074 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47562 /* 132076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47563 /* 132079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47564 /* 132085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47565 /* 132091 */ GIR_RootConstrainSelectedInstOperands,
47566 /* 132092 */ // GIR_Coverage, 3539,
47567 /* 132092 */ GIR_EraseRootFromParent_Done,
47568 /* 132093 */ // Label 4051: @132093
47569 /* 132093 */ GIM_Reject,
47570 /* 132094 */ // Label 4048: @132094
47571 /* 132094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4052*/ GIMT_Encode4(132168), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3540 //
47572 /* 132101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47573 /* 132105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47574 /* 132109 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47575 /* 132109 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47576 /* 132112 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47577 /* 132116 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47578 /* 132121 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
47579 /* 132124 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47580 /* 132127 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47581 /* 132133 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47582 /* 132139 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47583 /* 132141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
47584 /* 132144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47585 /* 132146 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47586 /* 132149 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47587 /* 132151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47588 /* 132154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47589 /* 132160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47590 /* 132166 */ GIR_RootConstrainSelectedInstOperands,
47591 /* 132167 */ // GIR_Coverage, 3540,
47592 /* 132167 */ GIR_EraseRootFromParent_Done,
47593 /* 132168 */ // Label 4052: @132168
47594 /* 132168 */ GIM_Reject,
47595 /* 132169 */ // Label 4049: @132169
47596 /* 132169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4053*/ GIMT_Encode4(132243), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3541 //
47597 /* 132176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47598 /* 132180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47599 /* 132184 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47600 /* 132184 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47601 /* 132187 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47602 /* 132191 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47603 /* 132196 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
47604 /* 132199 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47605 /* 132202 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47606 /* 132208 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47607 /* 132214 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47608 /* 132216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
47609 /* 132219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47610 /* 132221 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47611 /* 132224 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47612 /* 132226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47613 /* 132229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47614 /* 132235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47615 /* 132241 */ GIR_RootConstrainSelectedInstOperands,
47616 /* 132242 */ // GIR_Coverage, 3541,
47617 /* 132242 */ GIR_EraseRootFromParent_Done,
47618 /* 132243 */ // Label 4053: @132243
47619 /* 132243 */ GIM_Reject,
47620 /* 132244 */ // Label 4050: @132244
47621 /* 132244 */ GIM_Reject,
47622 /* 132245 */ // Label 4046: @132245
47623 /* 132245 */ GIM_Reject,
47624 /* 132246 */ // Label 94: @132246
47625 /* 132246 */ GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(132526),
47626 /* 132251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47627 /* 132254 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4058*/ GIMT_Encode4(132525),
47628 /* 132265 */ /*GILLT_v16s8*//*Label 4055*/ GIMT_Encode4(132285), GIMT_Encode4(0),
47629 /* 132273 */ /*GILLT_v8s16*//*Label 4056*/ GIMT_Encode4(132367), GIMT_Encode4(0),
47630 /* 132281 */ /*GILLT_v4s32*//*Label 4057*/ GIMT_Encode4(132443),
47631 /* 132285 */ // Label 4055: @132285
47632 /* 132285 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4059*/ GIMT_Encode4(132366), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3545 //
47633 /* 132292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47634 /* 132296 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47635 /* 132300 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47636 /* 132300 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47637 /* 132303 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47638 /* 132307 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47639 /* 132312 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255),
47640 /* 132322 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47641 /* 132325 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47642 /* 132331 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47643 /* 132337 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47644 /* 132339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
47645 /* 132342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47646 /* 132344 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47647 /* 132347 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47648 /* 132349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47649 /* 132352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47650 /* 132358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47651 /* 132364 */ GIR_RootConstrainSelectedInstOperands,
47652 /* 132365 */ // GIR_Coverage, 3545,
47653 /* 132365 */ GIR_EraseRootFromParent_Done,
47654 /* 132366 */ // Label 4059: @132366
47655 /* 132366 */ GIM_Reject,
47656 /* 132367 */ // Label 4056: @132367
47657 /* 132367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4060*/ GIMT_Encode4(132442), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3546 //
47658 /* 132374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47659 /* 132378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47660 /* 132382 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47661 /* 132382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47662 /* 132385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
47663 /* 132389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47664 /* 132394 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
47665 /* 132404 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47666 /* 132407 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47667 /* 132413 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47668 /* 132415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
47669 /* 132418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47670 /* 132420 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47671 /* 132423 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47672 /* 132425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47673 /* 132428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47674 /* 132434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47675 /* 132440 */ GIR_RootConstrainSelectedInstOperands,
47676 /* 132441 */ // GIR_Coverage, 3546,
47677 /* 132441 */ GIR_EraseRootFromParent_Done,
47678 /* 132442 */ // Label 4060: @132442
47679 /* 132442 */ GIM_Reject,
47680 /* 132443 */ // Label 4057: @132443
47681 /* 132443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4061*/ GIMT_Encode4(132524), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3547 //
47682 /* 132450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47683 /* 132454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47684 /* 132458 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47685 /* 132458 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47686 /* 132461 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47687 /* 132465 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47688 /* 132470 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295),
47689 /* 132480 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47690 /* 132483 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47691 /* 132489 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47692 /* 132495 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47693 /* 132497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
47694 /* 132500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47695 /* 132502 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47696 /* 132505 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47697 /* 132507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47698 /* 132510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47699 /* 132516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47700 /* 132522 */ GIR_RootConstrainSelectedInstOperands,
47701 /* 132523 */ // GIR_Coverage, 3547,
47702 /* 132523 */ GIR_EraseRootFromParent_Done,
47703 /* 132524 */ // Label 4061: @132524
47704 /* 132524 */ GIM_Reject,
47705 /* 132525 */ // Label 4058: @132525
47706 /* 132525 */ GIM_Reject,
47707 /* 132526 */ // Label 4054: @132526
47708 /* 132526 */ GIM_Reject,
47709 /* 132527 */ // Label 95: @132527
47710 /* 132527 */ GIM_Reject,
47711 /* 132528 */ }; // Size: 132528 bytes
47712 return MatchTable0;
47713}
47714#undef GIMT_Encode2
47715#undef GIMT_Encode4
47716#undef GIMT_Encode8
47717
47718
47719#endif // GET_GLOBALISEL_IMPL
47720
47721#ifdef GET_GLOBALISEL_PREDICATES_DECL
47722
47723PredicateBitset AvailableModuleFeatures;
47724mutable PredicateBitset AvailableFunctionFeatures;
47725PredicateBitset getAvailableFeatures() const {
47726 return AvailableModuleFeatures | AvailableFunctionFeatures;
47727}
47728PredicateBitset
47729computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
47730PredicateBitset
47731computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
47732 const MachineFunction *MF) const;
47733void setupGeneratedPerFunctionState(MachineFunction &MF) override;
47734
47735#endif // GET_GLOBALISEL_PREDICATES_DECL
47736
47737#ifdef GET_GLOBALISEL_PREDICATES_INIT
47738
47739AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
47740AvailableFunctionFeatures()
47741
47742#endif // GET_GLOBALISEL_PREDICATES_INIT
47743
47744