| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the ARM target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | |
| 11 | const unsigned MAX_SUBTARGET_PREDICATES = 83; |
| 12 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 13 | |
| 14 | #endif // GET_GLOBALISEL_PREDICATE_BITSET |
| 15 | |
| 16 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 17 | |
| 18 | mutable MatcherState State; |
| 19 | typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 20 | typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 21 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 22 | static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 23 | static ARMInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 24 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 25 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 26 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 27 | const uint8_t *getMatchTable() const override; |
| 28 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 29 | bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override; |
| 30 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 31 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 32 | |
| 33 | #endif // GET_GLOBALISEL_TEMPORARIES_DECL |
| 34 | |
| 35 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 36 | |
| 37 | , State(0), |
| 38 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 39 | |
| 40 | #endif // GET_GLOBALISEL_TEMPORARIES_INIT |
| 41 | |
| 42 | #ifdef GET_GLOBALISEL_IMPL |
| 43 | |
| 44 | // LLT Objects. |
| 45 | enum { |
| 46 | GILLT_s16, |
| 47 | GILLT_s32, |
| 48 | GILLT_s64, |
| 49 | GILLT_v2s1, |
| 50 | GILLT_v2s32, |
| 51 | GILLT_v2s64, |
| 52 | GILLT_v4s1, |
| 53 | GILLT_v4s16, |
| 54 | GILLT_v4s32, |
| 55 | GILLT_v4s64, |
| 56 | GILLT_v8s1, |
| 57 | GILLT_v8s8, |
| 58 | GILLT_v8s16, |
| 59 | GILLT_v8s64, |
| 60 | GILLT_v16s1, |
| 61 | GILLT_v16s8, |
| 62 | }; |
| 63 | const static size_t NumTypeObjects = 16; |
| 64 | const static LLT TypeObjects[] = { |
| 65 | LLT::scalar(16), |
| 66 | LLT::scalar(32), |
| 67 | LLT::scalar(64), |
| 68 | LLT::vector(ElementCount::getFixed(2), 1), |
| 69 | LLT::vector(ElementCount::getFixed(2), 32), |
| 70 | LLT::vector(ElementCount::getFixed(2), 64), |
| 71 | LLT::vector(ElementCount::getFixed(4), 1), |
| 72 | LLT::vector(ElementCount::getFixed(4), 16), |
| 73 | LLT::vector(ElementCount::getFixed(4), 32), |
| 74 | LLT::vector(ElementCount::getFixed(4), 64), |
| 75 | LLT::vector(ElementCount::getFixed(8), 1), |
| 76 | LLT::vector(ElementCount::getFixed(8), 8), |
| 77 | LLT::vector(ElementCount::getFixed(8), 16), |
| 78 | LLT::vector(ElementCount::getFixed(8), 64), |
| 79 | LLT::vector(ElementCount::getFixed(16), 1), |
| 80 | LLT::vector(ElementCount::getFixed(16), 8), |
| 81 | }; |
| 82 | |
| 83 | // Bits for subtarget features that participate in instruction matching. |
| 84 | enum SubtargetFeatureBits : uint8_t { |
| 85 | Feature_NoHonorSignDependentRoundingBit = 73, |
| 86 | Feature_HasV4TBit = 4, |
| 87 | Feature_NoV4TBit = 5, |
| 88 | Feature_HasV5TBit = 11, |
| 89 | Feature_NoV5TBit = 63, |
| 90 | Feature_HasV5TEBit = 9, |
| 91 | Feature_HasV6Bit = 0, |
| 92 | Feature_NoV6Bit = 7, |
| 93 | Feature_HasV6MBit = 26, |
| 94 | Feature_HasV8MBaselineBit = 33, |
| 95 | Feature_HasV8_1MMainlineBit = 39, |
| 96 | Feature_HasMVEIntBit = 61, |
| 97 | Feature_HasMVEFloatBit = 62, |
| 98 | Feature_HasCDEBit = 82, |
| 99 | Feature_HasFPRegsBit = 40, |
| 100 | Feature_HasFPRegs16Bit = 41, |
| 101 | Feature_HasFPRegs64Bit = 74, |
| 102 | Feature_HasV6T2Bit = 6, |
| 103 | Feature_HasV6KBit = 16, |
| 104 | Feature_HasV7Bit = 3, |
| 105 | Feature_HasV8Bit = 53, |
| 106 | Feature_PreV8Bit = 17, |
| 107 | Feature_HasV8_1aBit = 76, |
| 108 | Feature_HasV8_3aBit = 77, |
| 109 | Feature_NoVFPBit = 20, |
| 110 | Feature_HasVFP2Bit = 19, |
| 111 | Feature_HasVFP3Bit = 50, |
| 112 | Feature_HasVFP4Bit = 48, |
| 113 | Feature_HasDPVFPBit = 42, |
| 114 | Feature_HasFPARMv8Bit = 45, |
| 115 | Feature_HasNEONBit = 51, |
| 116 | Feature_HasSHA2Bit = 60, |
| 117 | Feature_HasAESBit = 52, |
| 118 | Feature_HasDotProdBit = 54, |
| 119 | Feature_HasCRCBit = 12, |
| 120 | Feature_HasLOBBit = 38, |
| 121 | Feature_HasFP16Bit = 59, |
| 122 | Feature_HasFullFP16Bit = 44, |
| 123 | Feature_HasMatMulInt8Bit = 55, |
| 124 | Feature_HasDivideInThumbBit = 35, |
| 125 | Feature_HasDivideInARMBit = 10, |
| 126 | Feature_HasDSPBit = 34, |
| 127 | Feature_HasDBBit = 13, |
| 128 | Feature_HasV7ClrexBit = 15, |
| 129 | Feature_HasAcquireReleaseBit = 14, |
| 130 | Feature_HasMPBit = 2, |
| 131 | Feature_Has8MSecExtBit = 27, |
| 132 | Feature_HasZCZBit = 56, |
| 133 | Feature_UseNEONForFPBit = 80, |
| 134 | Feature_DontUseNEONForFPBit = 43, |
| 135 | Feature_IsThumbBit = 24, |
| 136 | Feature_IsThumb1OnlyBit = 25, |
| 137 | Feature_IsThumb2Bit = 32, |
| 138 | Feature_IsNotMClassBit = 36, |
| 139 | Feature_IsARMBit = 1, |
| 140 | Feature_IsWindowsBit = 28, |
| 141 | Feature_IsNotWindowsBit = 29, |
| 142 | Feature_IsReadTPTPIDRURWBit = 66, |
| 143 | Feature_IsReadTPTPIDRUROBit = 67, |
| 144 | Feature_IsReadTPTPIDRPRWBit = 68, |
| 145 | Feature_IsReadTPSoftBit = 18, |
| 146 | Feature_UseMovtBit = 37, |
| 147 | Feature_DontUseMovtBit = 21, |
| 148 | Feature_UseMovtInPicBit = 22, |
| 149 | Feature_DontUseMovtInPicBit = 23, |
| 150 | Feature_UseFPVMLxBit = 47, |
| 151 | Feature_SLSBLRMitigationBit = 65, |
| 152 | Feature_NoSLSBLRMitigationBit = 64, |
| 153 | Feature_UseMulOpsBit = 8, |
| 154 | Feature_UseFusedMACBit = 49, |
| 155 | Feature_HasFastVGETLNi32Bit = 57, |
| 156 | Feature_HasSlowVGETLNi32Bit = 78, |
| 157 | Feature_HasFastVDUP32Bit = 58, |
| 158 | Feature_HasSlowVDUP32Bit = 79, |
| 159 | Feature_UseVMOVSRBit = 46, |
| 160 | Feature_DontUseVMOVSRBit = 81, |
| 161 | Feature_IsLEBit = 72, |
| 162 | Feature_IsBEBit = 75, |
| 163 | Feature_GenExecuteOnlyBit = 31, |
| 164 | Feature_DontGenExecuteOnlyBit = 30, |
| 165 | Feature_GenT1ExecuteOnlyBit = 71, |
| 166 | Feature_SignRetAddrBit = 70, |
| 167 | Feature_NoSignRetAddrBit = 69, |
| 168 | }; |
| 169 | |
| 170 | PredicateBitset ARMInstructionSelector:: |
| 171 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const { |
| 172 | PredicateBitset Features{}; |
| 173 | if (!TM.Options.HonorSignDependentRoundingFPMath()) |
| 174 | Features.set(Feature_NoHonorSignDependentRoundingBit); |
| 175 | if (Subtarget->hasV4TOps()) |
| 176 | Features.set(Feature_HasV4TBit); |
| 177 | if (!Subtarget->hasV4TOps()) |
| 178 | Features.set(Feature_NoV4TBit); |
| 179 | if (Subtarget->hasV5TOps()) |
| 180 | Features.set(Feature_HasV5TBit); |
| 181 | if (!Subtarget->hasV5TOps()) |
| 182 | Features.set(Feature_NoV5TBit); |
| 183 | if (Subtarget->hasV5TEOps()) |
| 184 | Features.set(Feature_HasV5TEBit); |
| 185 | if (Subtarget->hasV6Ops()) |
| 186 | Features.set(Feature_HasV6Bit); |
| 187 | if (!Subtarget->hasV6Ops()) |
| 188 | Features.set(Feature_NoV6Bit); |
| 189 | if (Subtarget->hasV6MOps()) |
| 190 | Features.set(Feature_HasV6MBit); |
| 191 | if (Subtarget->hasV8MBaselineOps()) |
| 192 | Features.set(Feature_HasV8MBaselineBit); |
| 193 | if (Subtarget->hasV8_1MMainlineOps()) |
| 194 | Features.set(Feature_HasV8_1MMainlineBit); |
| 195 | if (Subtarget->hasMVEIntegerOps()) |
| 196 | Features.set(Feature_HasMVEIntBit); |
| 197 | if (Subtarget->hasMVEFloatOps()) |
| 198 | Features.set(Feature_HasMVEFloatBit); |
| 199 | if (Subtarget->hasCDEOps()) |
| 200 | Features.set(Feature_HasCDEBit); |
| 201 | if (Subtarget->hasFPRegs()) |
| 202 | Features.set(Feature_HasFPRegsBit); |
| 203 | if (Subtarget->hasFPRegs16()) |
| 204 | Features.set(Feature_HasFPRegs16Bit); |
| 205 | if (Subtarget->hasFPRegs64()) |
| 206 | Features.set(Feature_HasFPRegs64Bit); |
| 207 | if (Subtarget->hasV6T2Ops()) |
| 208 | Features.set(Feature_HasV6T2Bit); |
| 209 | if (Subtarget->hasV6KOps()) |
| 210 | Features.set(Feature_HasV6KBit); |
| 211 | if (Subtarget->hasV7Ops()) |
| 212 | Features.set(Feature_HasV7Bit); |
| 213 | if (Subtarget->hasV8Ops()) |
| 214 | Features.set(Feature_HasV8Bit); |
| 215 | if (!Subtarget->hasV8Ops()) |
| 216 | Features.set(Feature_PreV8Bit); |
| 217 | if (Subtarget->hasV8_1aOps()) |
| 218 | Features.set(Feature_HasV8_1aBit); |
| 219 | if (Subtarget->hasV8_3aOps()) |
| 220 | Features.set(Feature_HasV8_3aBit); |
| 221 | if (!Subtarget->hasVFP2Base()) |
| 222 | Features.set(Feature_NoVFPBit); |
| 223 | if (Subtarget->hasVFP2Base()) |
| 224 | Features.set(Feature_HasVFP2Bit); |
| 225 | if (Subtarget->hasVFP3Base()) |
| 226 | Features.set(Feature_HasVFP3Bit); |
| 227 | if (Subtarget->hasVFP4Base()) |
| 228 | Features.set(Feature_HasVFP4Bit); |
| 229 | if (Subtarget->hasFP64()) |
| 230 | Features.set(Feature_HasDPVFPBit); |
| 231 | if (Subtarget->hasFPARMv8Base()) |
| 232 | Features.set(Feature_HasFPARMv8Bit); |
| 233 | if (Subtarget->hasNEON()) |
| 234 | Features.set(Feature_HasNEONBit); |
| 235 | if (Subtarget->hasSHA2()) |
| 236 | Features.set(Feature_HasSHA2Bit); |
| 237 | if (Subtarget->hasAES()) |
| 238 | Features.set(Feature_HasAESBit); |
| 239 | if (Subtarget->hasDotProd()) |
| 240 | Features.set(Feature_HasDotProdBit); |
| 241 | if (Subtarget->hasCRC()) |
| 242 | Features.set(Feature_HasCRCBit); |
| 243 | if (Subtarget->hasLOB()) |
| 244 | Features.set(Feature_HasLOBBit); |
| 245 | if (Subtarget->hasFP16()) |
| 246 | Features.set(Feature_HasFP16Bit); |
| 247 | if (Subtarget->hasFullFP16()) |
| 248 | Features.set(Feature_HasFullFP16Bit); |
| 249 | if (Subtarget->hasMatMulInt8()) |
| 250 | Features.set(Feature_HasMatMulInt8Bit); |
| 251 | if (Subtarget->hasDivideInThumbMode()) |
| 252 | Features.set(Feature_HasDivideInThumbBit); |
| 253 | if (Subtarget->hasDivideInARMMode()) |
| 254 | Features.set(Feature_HasDivideInARMBit); |
| 255 | if (Subtarget->hasDSP()) |
| 256 | Features.set(Feature_HasDSPBit); |
| 257 | if (Subtarget->hasDataBarrier()) |
| 258 | Features.set(Feature_HasDBBit); |
| 259 | if (Subtarget->hasV7Clrex()) |
| 260 | Features.set(Feature_HasV7ClrexBit); |
| 261 | if (Subtarget->hasAcquireRelease()) |
| 262 | Features.set(Feature_HasAcquireReleaseBit); |
| 263 | if (Subtarget->hasMPExtension()) |
| 264 | Features.set(Feature_HasMPBit); |
| 265 | if (Subtarget->has8MSecExt()) |
| 266 | Features.set(Feature_Has8MSecExtBit); |
| 267 | if (Subtarget->hasZeroCycleZeroing()) |
| 268 | Features.set(Feature_HasZCZBit); |
| 269 | if (Subtarget->useNEONForSinglePrecisionFP()) |
| 270 | Features.set(Feature_UseNEONForFPBit); |
| 271 | if (!Subtarget->useNEONForSinglePrecisionFP()) |
| 272 | Features.set(Feature_DontUseNEONForFPBit); |
| 273 | if (Subtarget->isThumb()) |
| 274 | Features.set(Feature_IsThumbBit); |
| 275 | if (Subtarget->isThumb1Only()) |
| 276 | Features.set(Feature_IsThumb1OnlyBit); |
| 277 | if (Subtarget->isThumb2()) |
| 278 | Features.set(Feature_IsThumb2Bit); |
| 279 | if (!Subtarget->isMClass()) |
| 280 | Features.set(Feature_IsNotMClassBit); |
| 281 | if (!Subtarget->isThumb()) |
| 282 | Features.set(Feature_IsARMBit); |
| 283 | if (Subtarget->isTargetWindows()) |
| 284 | Features.set(Feature_IsWindowsBit); |
| 285 | if (!Subtarget->isTargetWindows()) |
| 286 | Features.set(Feature_IsNotWindowsBit); |
| 287 | if (Subtarget->isReadTPTPIDRURW()) |
| 288 | Features.set(Feature_IsReadTPTPIDRURWBit); |
| 289 | if (Subtarget->isReadTPTPIDRURO()) |
| 290 | Features.set(Feature_IsReadTPTPIDRUROBit); |
| 291 | if (Subtarget->isReadTPTPIDRPRW()) |
| 292 | Features.set(Feature_IsReadTPTPIDRPRWBit); |
| 293 | if (Subtarget->isReadTPSoft()) |
| 294 | Features.set(Feature_IsReadTPSoftBit); |
| 295 | if (Subtarget->useMulOps()) |
| 296 | Features.set(Feature_UseMulOpsBit); |
| 297 | if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx()) |
| 298 | Features.set(Feature_UseFusedMACBit); |
| 299 | if (!Subtarget->hasSlowVGETLNi32()) |
| 300 | Features.set(Feature_HasFastVGETLNi32Bit); |
| 301 | if (Subtarget->hasSlowVGETLNi32()) |
| 302 | Features.set(Feature_HasSlowVGETLNi32Bit); |
| 303 | if (!Subtarget->hasSlowVDUP32()) |
| 304 | Features.set(Feature_HasFastVDUP32Bit); |
| 305 | if (Subtarget->hasSlowVDUP32()) |
| 306 | Features.set(Feature_HasSlowVDUP32Bit); |
| 307 | if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()) |
| 308 | Features.set(Feature_UseVMOVSRBit); |
| 309 | if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()) |
| 310 | Features.set(Feature_DontUseVMOVSRBit); |
| 311 | if (Subtarget->genExecuteOnly()) |
| 312 | Features.set(Feature_GenExecuteOnlyBit); |
| 313 | if (!Subtarget->genExecuteOnly()) |
| 314 | Features.set(Feature_DontGenExecuteOnlyBit); |
| 315 | if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps()) |
| 316 | Features.set(Feature_GenT1ExecuteOnlyBit); |
| 317 | return Features; |
| 318 | } |
| 319 | |
| 320 | void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 321 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF); |
| 322 | } |
| 323 | PredicateBitset ARMInstructionSelector:: |
| 324 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const { |
| 325 | PredicateBitset Features{}; |
| 326 | if (Subtarget->useMovt()) |
| 327 | Features.set(Feature_UseMovtBit); |
| 328 | if (!Subtarget->useMovt()) |
| 329 | Features.set(Feature_DontUseMovtBit); |
| 330 | if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()) |
| 331 | Features.set(Feature_UseMovtInPicBit); |
| 332 | if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()) |
| 333 | Features.set(Feature_DontUseMovtInPicBit); |
| 334 | if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize())) |
| 335 | Features.set(Feature_UseFPVMLxBit); |
| 336 | if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 337 | Features.set(Feature_SLSBLRMitigationBit); |
| 338 | if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 339 | Features.set(Feature_NoSLSBLRMitigationBit); |
| 340 | if (MF->getDataLayout().isLittleEndian()) |
| 341 | Features.set(Feature_IsLEBit); |
| 342 | if (MF->getDataLayout().isBigEndian()) |
| 343 | Features.set(Feature_IsBEBit); |
| 344 | if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 345 | Features.set(Feature_SignRetAddrBit); |
| 346 | if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 347 | Features.set(Feature_NoSignRetAddrBit); |
| 348 | return Features; |
| 349 | } |
| 350 | |
| 351 | // Feature bitsets. |
| 352 | enum { |
| 353 | GIFBS_Invalid, |
| 354 | GIFBS_HasDotProd, |
| 355 | GIFBS_HasFP16, |
| 356 | GIFBS_HasFPARMv8, |
| 357 | GIFBS_HasFPRegs, |
| 358 | GIFBS_HasFullFP16, |
| 359 | GIFBS_HasMVEFloat, |
| 360 | GIFBS_HasMVEInt, |
| 361 | GIFBS_HasMatMulInt8, |
| 362 | GIFBS_HasNEON, |
| 363 | GIFBS_HasVFP2, |
| 364 | GIFBS_HasVFP3, |
| 365 | GIFBS_HasVFP4, |
| 366 | GIFBS_IsARM, |
| 367 | GIFBS_IsThumb, |
| 368 | GIFBS_IsThumb2, |
| 369 | GIFBS_NoHonorSignDependentRounding, |
| 370 | GIFBS_DontUseNEONForFP_HasVFP2, |
| 371 | GIFBS_DontUseVMOVSR_HasNEON, |
| 372 | GIFBS_Has8MSecExt_IsThumb, |
| 373 | GIFBS_HasAES_HasV8, |
| 374 | GIFBS_HasCRC_IsARM, |
| 375 | GIFBS_HasCRC_IsThumb2, |
| 376 | GIFBS_HasDB_IsARM, |
| 377 | GIFBS_HasDB_IsThumb, |
| 378 | GIFBS_HasDPVFP_HasFPARMv8, |
| 379 | GIFBS_HasDPVFP_HasVFP2, |
| 380 | GIFBS_HasDPVFP_HasVFP3, |
| 381 | GIFBS_HasDPVFP_HasVFP4, |
| 382 | GIFBS_HasDPVFP_NoHonorSignDependentRounding, |
| 383 | GIFBS_HasDSP_IsThumb2, |
| 384 | GIFBS_HasDivideInARM_IsARM, |
| 385 | GIFBS_HasFP16_HasNEON, |
| 386 | GIFBS_HasFPARMv8_HasNEON, |
| 387 | GIFBS_HasFPRegs_HasFastVGETLNi32, |
| 388 | GIFBS_HasFPRegs_UseVMOVSR, |
| 389 | GIFBS_HasFullFP16_HasNEON, |
| 390 | GIFBS_HasMVEInt_HasV8_1MMainline, |
| 391 | GIFBS_HasMVEInt_IsBE, |
| 392 | GIFBS_HasMVEInt_IsLE, |
| 393 | GIFBS_HasNEON_HasV8, |
| 394 | GIFBS_HasNEON_HasV8_1a, |
| 395 | GIFBS_HasNEON_HasV8_3a, |
| 396 | GIFBS_HasNEON_HasVFP4, |
| 397 | GIFBS_HasNEON_IsBE, |
| 398 | GIFBS_HasNEON_IsLE, |
| 399 | GIFBS_HasNEON_UseNEONForFP, |
| 400 | GIFBS_HasSHA2_HasV8, |
| 401 | GIFBS_HasV5T_IsARM, |
| 402 | GIFBS_HasV5T_IsThumb, |
| 403 | GIFBS_HasV5TE_IsARM, |
| 404 | GIFBS_HasV6_IsARM, |
| 405 | GIFBS_HasV6K_IsARM, |
| 406 | GIFBS_HasV6M_IsThumb, |
| 407 | GIFBS_HasV6T2_IsARM, |
| 408 | GIFBS_HasV7_IsARM, |
| 409 | GIFBS_HasV7Clrex_IsThumb, |
| 410 | GIFBS_HasV8MBaseline_IsThumb, |
| 411 | GIFBS_IsARM_NoV5T, |
| 412 | GIFBS_IsARM_NoV6, |
| 413 | GIFBS_IsARM_PreV8, |
| 414 | GIFBS_IsThumb_IsThumb1Only, |
| 415 | GIFBS_IsThumb_IsWindows, |
| 416 | GIFBS_IsThumb_NoV5T, |
| 417 | GIFBS_IsThumb_UseMovt, |
| 418 | GIFBS_IsThumb2_PreV8, |
| 419 | GIFBS_IsThumb2_UseMulOps, |
| 420 | GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only, |
| 421 | GIFBS_HasDSP_IsThumb2_UseMulOps, |
| 422 | GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, |
| 423 | GIFBS_HasFPARMv8_HasFullFP16_HasNEON, |
| 424 | GIFBS_HasFullFP16_HasNEON_HasV8, |
| 425 | GIFBS_HasFullFP16_HasNEON_HasV8_3a, |
| 426 | GIFBS_HasFullFP16_HasNEON_UseFPVMLx, |
| 427 | GIFBS_HasFullFP16_HasNEON_UseFusedMAC, |
| 428 | GIFBS_HasLOB_HasV8_1MMainline_IsThumb2, |
| 429 | GIFBS_HasNEON_UseFPVMLx_UseNEONForFP, |
| 430 | GIFBS_HasV5TE_IsARM_UseMulOps, |
| 431 | GIFBS_HasV6_IsARM_UseMulOps, |
| 432 | GIFBS_HasV6_IsThumb_IsThumb1Only, |
| 433 | GIFBS_HasV6T2_IsARM_UseMulOps, |
| 434 | GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP, |
| 435 | GIFBS_IsARM_NoV6_UseMulOps, |
| 436 | }; |
| 437 | constexpr static PredicateBitset FeatureBitsets[] { |
| 438 | {}, // GIFBS_Invalid |
| 439 | {Feature_HasDotProdBit, }, |
| 440 | {Feature_HasFP16Bit, }, |
| 441 | {Feature_HasFPARMv8Bit, }, |
| 442 | {Feature_HasFPRegsBit, }, |
| 443 | {Feature_HasFullFP16Bit, }, |
| 444 | {Feature_HasMVEFloatBit, }, |
| 445 | {Feature_HasMVEIntBit, }, |
| 446 | {Feature_HasMatMulInt8Bit, }, |
| 447 | {Feature_HasNEONBit, }, |
| 448 | {Feature_HasVFP2Bit, }, |
| 449 | {Feature_HasVFP3Bit, }, |
| 450 | {Feature_HasVFP4Bit, }, |
| 451 | {Feature_IsARMBit, }, |
| 452 | {Feature_IsThumbBit, }, |
| 453 | {Feature_IsThumb2Bit, }, |
| 454 | {Feature_NoHonorSignDependentRoundingBit, }, |
| 455 | {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, }, |
| 456 | {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, }, |
| 457 | {Feature_Has8MSecExtBit, Feature_IsThumbBit, }, |
| 458 | {Feature_HasAESBit, Feature_HasV8Bit, }, |
| 459 | {Feature_HasCRCBit, Feature_IsARMBit, }, |
| 460 | {Feature_HasCRCBit, Feature_IsThumb2Bit, }, |
| 461 | {Feature_HasDBBit, Feature_IsARMBit, }, |
| 462 | {Feature_HasDBBit, Feature_IsThumbBit, }, |
| 463 | {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, }, |
| 464 | {Feature_HasDPVFPBit, Feature_HasVFP2Bit, }, |
| 465 | {Feature_HasDPVFPBit, Feature_HasVFP3Bit, }, |
| 466 | {Feature_HasDPVFPBit, Feature_HasVFP4Bit, }, |
| 467 | {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, }, |
| 468 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 469 | {Feature_HasDivideInARMBit, Feature_IsARMBit, }, |
| 470 | {Feature_HasFP16Bit, Feature_HasNEONBit, }, |
| 471 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 472 | {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, }, |
| 473 | {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, }, |
| 474 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 475 | {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, }, |
| 476 | {Feature_HasMVEIntBit, Feature_IsBEBit, }, |
| 477 | {Feature_HasMVEIntBit, Feature_IsLEBit, }, |
| 478 | {Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 479 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 480 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 481 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 482 | {Feature_HasNEONBit, Feature_IsBEBit, }, |
| 483 | {Feature_HasNEONBit, Feature_IsLEBit, }, |
| 484 | {Feature_HasNEONBit, Feature_UseNEONForFPBit, }, |
| 485 | {Feature_HasSHA2Bit, Feature_HasV8Bit, }, |
| 486 | {Feature_HasV5TBit, Feature_IsARMBit, }, |
| 487 | {Feature_HasV5TBit, Feature_IsThumbBit, }, |
| 488 | {Feature_HasV5TEBit, Feature_IsARMBit, }, |
| 489 | {Feature_HasV6Bit, Feature_IsARMBit, }, |
| 490 | {Feature_HasV6KBit, Feature_IsARMBit, }, |
| 491 | {Feature_HasV6MBit, Feature_IsThumbBit, }, |
| 492 | {Feature_HasV6T2Bit, Feature_IsARMBit, }, |
| 493 | {Feature_HasV7Bit, Feature_IsARMBit, }, |
| 494 | {Feature_HasV7ClrexBit, Feature_IsThumbBit, }, |
| 495 | {Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 496 | {Feature_IsARMBit, Feature_NoV5TBit, }, |
| 497 | {Feature_IsARMBit, Feature_NoV6Bit, }, |
| 498 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 499 | {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 500 | {Feature_IsThumbBit, Feature_IsWindowsBit, }, |
| 501 | {Feature_IsThumbBit, Feature_NoV5TBit, }, |
| 502 | {Feature_IsThumbBit, Feature_UseMovtBit, }, |
| 503 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 504 | {Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 505 | {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, }, |
| 506 | {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 507 | {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 508 | {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 509 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 510 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 511 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, }, |
| 512 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, }, |
| 513 | {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, }, |
| 514 | {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, }, |
| 515 | {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 516 | {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 517 | {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 518 | {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 519 | {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, }, |
| 520 | {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, }, |
| 521 | }; |
| 522 | |
| 523 | // ComplexPattern predicates. |
| 524 | enum { |
| 525 | GICP_Invalid, |
| 526 | }; |
| 527 | // See constructor for table contents |
| 528 | |
| 529 | ARMInstructionSelector::ComplexMatcherMemFn |
| 530 | ARMInstructionSelector::ComplexPredicateFns[] = { |
| 531 | nullptr, // GICP_Invalid |
| 532 | }; |
| 533 | |
| 534 | // PatFrag predicates. |
| 535 | enum { |
| 536 | GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1, |
| 537 | GICXXPred_MI_Predicate_ffloor_nnan, |
| 538 | GICXXPred_MI_Predicate_or_disjoint, |
| 539 | GICXXPred_MI_Predicate_vfp_f32imm, |
| 540 | GICXXPred_MI_Predicate_vfp_f64imm, |
| 541 | }; |
| 542 | bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 543 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 544 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 545 | const auto &Operands = State.RecordedOperands; |
| 546 | (void)Operands; |
| 547 | (void)MRI; |
| 548 | switch (PredicateID) { |
| 549 | case GICXXPred_MI_Predicate_bf_inv_mask_imm: { |
| 550 | |
| 551 | // There's better methods of implementing this check. IntImmLeaf<> would be |
| 552 | // equivalent and have less boilerplate but we need a test for C++ |
| 553 | // predicates and this one causes new rules to be imported into GlobalISel |
| 554 | // without requiring additional features first. |
| 555 | const auto &MO = MI.getOperand(1); |
| 556 | if (!MO.isCImm()) |
| 557 | return false; |
| 558 | return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); |
| 559 | |
| 560 | llvm_unreachable("bf_inv_mask_imm should have returned"); |
| 561 | } |
| 562 | case GICXXPred_MI_Predicate_ffloor_nnan: { |
| 563 | |
| 564 | return MI.getFlag(MachineInstr::FmNoNans); |
| 565 | |
| 566 | } |
| 567 | case GICXXPred_MI_Predicate_or_disjoint: { |
| 568 | |
| 569 | return MI.getFlag(MachineInstr::Disjoint); |
| 570 | |
| 571 | } |
| 572 | case GICXXPred_MI_Predicate_vfp_f32imm: { |
| 573 | |
| 574 | const auto &MO = MI.getOperand(1); |
| 575 | if (!MO.isFPImm()) |
| 576 | return false; |
| 577 | return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 578 | |
| 579 | llvm_unreachable("vfp_f32imm should have returned"); |
| 580 | } |
| 581 | case GICXXPred_MI_Predicate_vfp_f64imm: { |
| 582 | |
| 583 | const auto &MO = MI.getOperand(1); |
| 584 | if (!MO.isFPImm()) |
| 585 | return false; |
| 586 | return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 587 | |
| 588 | llvm_unreachable("vfp_f64imm should have returned"); |
| 589 | } |
| 590 | } |
| 591 | llvm_unreachable("Unknown predicate"); |
| 592 | return false; |
| 593 | } |
| 594 | // PatFrag predicates. |
| 595 | bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const { |
| 596 | const auto &Operands = State.RecordedOperands; |
| 597 | Register Reg = MO.getReg(); |
| 598 | (void)Operands; |
| 599 | (void)Reg; |
| 600 | llvm_unreachable("Unknown predicate"); |
| 601 | return false; |
| 602 | } |
| 603 | // PatFrag predicates. |
| 604 | enum { |
| 605 | GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1, |
| 606 | GICXXPred_I64_Predicate_VectorIndex16, |
| 607 | GICXXPred_I64_Predicate_VectorIndex32, |
| 608 | GICXXPred_I64_Predicate_VectorIndex32_Hi, |
| 609 | GICXXPred_I64_Predicate_VectorIndex64, |
| 610 | GICXXPred_I64_Predicate_asr_imm, |
| 611 | GICXXPred_I64_Predicate_imm0_7, |
| 612 | GICXXPred_I64_Predicate_imm0_15, |
| 613 | GICXXPred_I64_Predicate_imm0_31, |
| 614 | GICXXPred_I64_Predicate_imm0_32, |
| 615 | GICXXPred_I64_Predicate_imm0_63, |
| 616 | GICXXPred_I64_Predicate_imm0_239, |
| 617 | GICXXPred_I64_Predicate_imm0_255, |
| 618 | GICXXPred_I64_Predicate_imm0_255_expr, |
| 619 | GICXXPred_I64_Predicate_imm0_4095, |
| 620 | GICXXPred_I64_Predicate_imm0_65535, |
| 621 | GICXXPred_I64_Predicate_imm0_65535_expr, |
| 622 | GICXXPred_I64_Predicate_imm0_65535_neg, |
| 623 | GICXXPred_I64_Predicate_imm1_7, |
| 624 | GICXXPred_I64_Predicate_imm1_15, |
| 625 | GICXXPred_I64_Predicate_imm1_16, |
| 626 | GICXXPred_I64_Predicate_imm1_31, |
| 627 | GICXXPred_I64_Predicate_imm8, |
| 628 | GICXXPred_I64_Predicate_imm8_255, |
| 629 | GICXXPred_I64_Predicate_imm8_or_16, |
| 630 | GICXXPred_I64_Predicate_imm16, |
| 631 | GICXXPred_I64_Predicate_imm16_31, |
| 632 | GICXXPred_I64_Predicate_imm24b, |
| 633 | GICXXPred_I64_Predicate_imm32, |
| 634 | GICXXPred_I64_Predicate_imm256_510, |
| 635 | GICXXPred_I64_Predicate_imm_3b, |
| 636 | GICXXPred_I64_Predicate_imm_4b, |
| 637 | GICXXPred_I64_Predicate_imm_6b, |
| 638 | GICXXPred_I64_Predicate_imm_7b, |
| 639 | GICXXPred_I64_Predicate_imm_9b, |
| 640 | GICXXPred_I64_Predicate_imm_11b, |
| 641 | GICXXPred_I64_Predicate_imm_12b, |
| 642 | GICXXPred_I64_Predicate_imm_13b, |
| 643 | GICXXPred_I64_Predicate_imm_even, |
| 644 | GICXXPred_I64_Predicate_imm_odd, |
| 645 | GICXXPred_I64_Predicate_imm_sr, |
| 646 | GICXXPred_I64_Predicate_long_shift, |
| 647 | GICXXPred_I64_Predicate_mod_imm, |
| 648 | GICXXPred_I64_Predicate_mod_imm_not, |
| 649 | GICXXPred_I64_Predicate_pkh_asr_amt, |
| 650 | GICXXPred_I64_Predicate_pkh_lsl_amt, |
| 651 | GICXXPred_I64_Predicate_shr_imm8, |
| 652 | GICXXPred_I64_Predicate_shr_imm16, |
| 653 | GICXXPred_I64_Predicate_shr_imm32, |
| 654 | GICXXPred_I64_Predicate_shr_imm64, |
| 655 | GICXXPred_I64_Predicate_t2_so_imm, |
| 656 | GICXXPred_I64_Predicate_t2_so_imm_neg, |
| 657 | }; |
| 658 | bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 659 | switch (PredicateID) { |
| 660 | case GICXXPred_I64_Predicate_VectorIndex8: { |
| 661 | |
| 662 | return ((uint64_t)Imm) < 8; |
| 663 | |
| 664 | } |
| 665 | case GICXXPred_I64_Predicate_VectorIndex16: { |
| 666 | |
| 667 | return ((uint64_t)Imm) < 4; |
| 668 | |
| 669 | } |
| 670 | case GICXXPred_I64_Predicate_VectorIndex32: { |
| 671 | |
| 672 | return ((uint64_t)Imm) < 2; |
| 673 | |
| 674 | } |
| 675 | case GICXXPred_I64_Predicate_VectorIndex32_Hi: { |
| 676 | |
| 677 | return ((uint64_t)Imm) >= 2 && ((uint64_t)Imm) < 4; |
| 678 | |
| 679 | } |
| 680 | case GICXXPred_I64_Predicate_VectorIndex64: { |
| 681 | |
| 682 | return ((uint64_t)Imm) < 1; |
| 683 | |
| 684 | } |
| 685 | case GICXXPred_I64_Predicate_asr_imm: { |
| 686 | return Imm > 0 && Imm <= 32; |
| 687 | } |
| 688 | case GICXXPred_I64_Predicate_imm0_7: { |
| 689 | |
| 690 | return Imm >= 0 && Imm < 8; |
| 691 | |
| 692 | } |
| 693 | case GICXXPred_I64_Predicate_imm0_15: { |
| 694 | |
| 695 | return Imm >= 0 && Imm < 16; |
| 696 | |
| 697 | } |
| 698 | case GICXXPred_I64_Predicate_imm0_31: { |
| 699 | |
| 700 | return Imm >= 0 && Imm < 32; |
| 701 | |
| 702 | } |
| 703 | case GICXXPred_I64_Predicate_imm0_32: { |
| 704 | |
| 705 | return Imm >= 0 && Imm < 33; |
| 706 | |
| 707 | } |
| 708 | case GICXXPred_I64_Predicate_imm0_63: { |
| 709 | |
| 710 | return Imm >= 0 && Imm < 64; |
| 711 | |
| 712 | } |
| 713 | case GICXXPred_I64_Predicate_imm0_239: { |
| 714 | return Imm >= 0 && Imm < 240; |
| 715 | } |
| 716 | case GICXXPred_I64_Predicate_imm0_255: { |
| 717 | return Imm >= 0 && Imm < 256; |
| 718 | } |
| 719 | case GICXXPred_I64_Predicate_imm0_255_expr: { |
| 720 | return Imm >= 0 && Imm < 256; |
| 721 | } |
| 722 | case GICXXPred_I64_Predicate_imm0_4095: { |
| 723 | |
| 724 | return Imm >= 0 && Imm < 4096; |
| 725 | |
| 726 | } |
| 727 | case GICXXPred_I64_Predicate_imm0_65535: { |
| 728 | |
| 729 | return Imm >= 0 && Imm < 65536; |
| 730 | |
| 731 | } |
| 732 | case GICXXPred_I64_Predicate_imm0_65535_expr: { |
| 733 | |
| 734 | return Imm >= 0 && Imm < 65536; |
| 735 | |
| 736 | } |
| 737 | case GICXXPred_I64_Predicate_imm0_65535_neg: { |
| 738 | |
| 739 | return -Imm >= 0 && -Imm < 65536; |
| 740 | |
| 741 | } |
| 742 | case GICXXPred_I64_Predicate_imm1_7: { |
| 743 | return Imm > 0 && Imm < 8; |
| 744 | } |
| 745 | case GICXXPred_I64_Predicate_imm1_15: { |
| 746 | return Imm > 0 && Imm < 16; |
| 747 | } |
| 748 | case GICXXPred_I64_Predicate_imm1_16: { |
| 749 | |
| 750 | return Imm > 0 && Imm <= 16; |
| 751 | |
| 752 | } |
| 753 | case GICXXPred_I64_Predicate_imm1_31: { |
| 754 | return Imm > 0 && Imm < 32; |
| 755 | } |
| 756 | case GICXXPred_I64_Predicate_imm8: { |
| 757 | return Imm == 8; |
| 758 | } |
| 759 | case GICXXPred_I64_Predicate_imm8_255: { |
| 760 | |
| 761 | return Imm >= 8 && Imm < 256; |
| 762 | |
| 763 | } |
| 764 | case GICXXPred_I64_Predicate_imm8_or_16: { |
| 765 | return Imm == 8 || Imm == 16; |
| 766 | } |
| 767 | case GICXXPred_I64_Predicate_imm16: { |
| 768 | return Imm == 16; |
| 769 | } |
| 770 | case GICXXPred_I64_Predicate_imm16_31: { |
| 771 | |
| 772 | return (int32_t)Imm >= 16 && (int32_t)Imm < 32; |
| 773 | |
| 774 | } |
| 775 | case GICXXPred_I64_Predicate_imm24b: { |
| 776 | |
| 777 | return Imm >= 0 && Imm <= 0xffffff; |
| 778 | |
| 779 | } |
| 780 | case GICXXPred_I64_Predicate_imm32: { |
| 781 | return Imm == 32; |
| 782 | } |
| 783 | case GICXXPred_I64_Predicate_imm256_510: { |
| 784 | |
| 785 | return Imm >= 256 && Imm < 511; |
| 786 | |
| 787 | } |
| 788 | case GICXXPred_I64_Predicate_imm_3b: { |
| 789 | { return Imm >= 0 && Imm < (1 << 3); } |
| 790 | llvm_unreachable("imm_3b should have returned"); |
| 791 | } |
| 792 | case GICXXPred_I64_Predicate_imm_4b: { |
| 793 | { return Imm >= 0 && Imm < (1 << 4); } |
| 794 | llvm_unreachable("imm_4b should have returned"); |
| 795 | } |
| 796 | case GICXXPred_I64_Predicate_imm_6b: { |
| 797 | { return Imm >= 0 && Imm < (1 << 6); } |
| 798 | llvm_unreachable("imm_6b should have returned"); |
| 799 | } |
| 800 | case GICXXPred_I64_Predicate_imm_7b: { |
| 801 | { return Imm >= 0 && Imm < (1 << 7); } |
| 802 | llvm_unreachable("imm_7b should have returned"); |
| 803 | } |
| 804 | case GICXXPred_I64_Predicate_imm_9b: { |
| 805 | { return Imm >= 0 && Imm < (1 << 9); } |
| 806 | llvm_unreachable("imm_9b should have returned"); |
| 807 | } |
| 808 | case GICXXPred_I64_Predicate_imm_11b: { |
| 809 | { return Imm >= 0 && Imm < (1 << 11); } |
| 810 | llvm_unreachable("imm_11b should have returned"); |
| 811 | } |
| 812 | case GICXXPred_I64_Predicate_imm_12b: { |
| 813 | { return Imm >= 0 && Imm < (1 << 12); } |
| 814 | llvm_unreachable("imm_12b should have returned"); |
| 815 | } |
| 816 | case GICXXPred_I64_Predicate_imm_13b: { |
| 817 | { return Imm >= 0 && Imm < (1 << 13); } |
| 818 | llvm_unreachable("imm_13b should have returned"); |
| 819 | } |
| 820 | case GICXXPred_I64_Predicate_imm_even: { |
| 821 | return (Imm & 1) == 0; |
| 822 | } |
| 823 | case GICXXPred_I64_Predicate_imm_odd: { |
| 824 | return (Imm & 1) == 1; |
| 825 | } |
| 826 | case GICXXPred_I64_Predicate_imm_sr: { |
| 827 | |
| 828 | return Imm > 0 && Imm <= 32; |
| 829 | |
| 830 | } |
| 831 | case GICXXPred_I64_Predicate_long_shift: { |
| 832 | return Imm > 0 && Imm <= 32; |
| 833 | } |
| 834 | case GICXXPred_I64_Predicate_mod_imm: { |
| 835 | |
| 836 | return ARM_AM::getSOImmVal(Imm) != -1; |
| 837 | |
| 838 | } |
| 839 | case GICXXPred_I64_Predicate_mod_imm_not: { |
| 840 | |
| 841 | return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1; |
| 842 | |
| 843 | } |
| 844 | case GICXXPred_I64_Predicate_pkh_asr_amt: { |
| 845 | return Imm > 0 && Imm <= 32; |
| 846 | } |
| 847 | case GICXXPred_I64_Predicate_pkh_lsl_amt: { |
| 848 | return Imm >= 0 && Imm < 32; |
| 849 | } |
| 850 | case GICXXPred_I64_Predicate_shr_imm8: { |
| 851 | return Imm > 0 && Imm <= 8; |
| 852 | } |
| 853 | case GICXXPred_I64_Predicate_shr_imm16: { |
| 854 | return Imm > 0 && Imm <= 16; |
| 855 | } |
| 856 | case GICXXPred_I64_Predicate_shr_imm32: { |
| 857 | return Imm > 0 && Imm <= 32; |
| 858 | } |
| 859 | case GICXXPred_I64_Predicate_shr_imm64: { |
| 860 | return Imm > 0 && Imm <= 64; |
| 861 | } |
| 862 | case GICXXPred_I64_Predicate_t2_so_imm: { |
| 863 | |
| 864 | return ARM_AM::getT2SOImmVal(Imm) != -1; |
| 865 | |
| 866 | } |
| 867 | case GICXXPred_I64_Predicate_t2_so_imm_neg: { |
| 868 | |
| 869 | return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; |
| 870 | |
| 871 | } |
| 872 | } |
| 873 | llvm_unreachable("Unknown predicate"); |
| 874 | return false; |
| 875 | } |
| 876 | // PatFrag predicates. |
| 877 | bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 878 | llvm_unreachable("Unknown predicate"); |
| 879 | return false; |
| 880 | } |
| 881 | // PatFrag predicates. |
| 882 | enum { |
| 883 | GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1, |
| 884 | }; |
| 885 | bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 886 | switch (PredicateID) { |
| 887 | case GICXXPred_APInt_Predicate_arm_i32imm: { |
| 888 | |
| 889 | if (Subtarget->useMovt()) |
| 890 | return true; |
| 891 | if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) |
| 892 | return true; |
| 893 | return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); |
| 894 | |
| 895 | llvm_unreachable("arm_i32imm should have returned"); |
| 896 | } |
| 897 | } |
| 898 | llvm_unreachable("Unknown predicate"); |
| 899 | return false; |
| 900 | } |
| 901 | bool ARMInstructionSelector::testSimplePredicate(unsigned) const { |
| 902 | llvm_unreachable("ARMInstructionSelector does not support simple predicates!"); |
| 903 | return false; |
| 904 | } |
| 905 | // Custom renderers. |
| 906 | enum { |
| 907 | GICR_Invalid, |
| 908 | GICR_renderInvertedImm, |
| 909 | GICR_renderVFPF32Imm, |
| 910 | GICR_renderVFPF64Imm, |
| 911 | }; |
| 912 | ARMInstructionSelector::CustomRendererFn |
| 913 | ARMInstructionSelector::CustomRenderers[] = { |
| 914 | nullptr, // GICR_Invalid |
| 915 | &ARMInstructionSelector::renderInvertedImm, |
| 916 | &ARMInstructionSelector::renderVFPF32Imm, |
| 917 | &ARMInstructionSelector::renderVFPF64Imm, |
| 918 | }; |
| 919 | |
| 920 | bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 921 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 922 | MachineIRBuilder B(I); |
| 923 | State.MIs.clear(); |
| 924 | State.MIs.push_back(&I); |
| 925 | |
| 926 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 927 | return true; |
| 928 | } |
| 929 | |
| 930 | return false; |
| 931 | } |
| 932 | |
| 933 | bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 934 | llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!"); |
| 935 | } |
| 936 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 937 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8) |
| 938 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24) |
| 939 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56) |
| 940 | #else |
| 941 | #define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val) |
| 942 | #define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val) |
| 943 | #define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val) |
| 944 | #endif |
| 945 | const uint8_t *ARMInstructionSelector::getMatchTable() const { |
| 946 | constexpr static uint8_t MatchTable0[] = { |
| 947 | /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(321), /*)*//*default:*//*Label 92*/ GIMT_Encode4(142685), |
| 948 | /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1074), |
| 949 | /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(13001), |
| 950 | /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(16245), |
| 951 | /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(17949), |
| 952 | /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(18045), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 953 | /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(18141), |
| 954 | /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(21321), |
| 955 | /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(27130), |
| 956 | /* 58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(28825), |
| 957 | /* 62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(29368), |
| 958 | /* 66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(29911), |
| 959 | /* 70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(30150), |
| 960 | /* 74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(30389), |
| 961 | /* 78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(30628), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 962 | /* 130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(30867), GIMT_Encode4(0), GIMT_Encode4(0), |
| 963 | /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(31254), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 964 | /* 158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(40266), |
| 965 | /* 162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(40674), GIMT_Encode4(0), GIMT_Encode4(0), |
| 966 | /* 174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 18*/ GIMT_Encode4(41049), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 967 | /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(41424), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 968 | /* 310 */ /*TargetOpcode::G_FENCE*//*Label 20*/ GIMT_Encode4(41587), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 969 | /* 330 */ /*TargetOpcode::G_INTRINSIC*//*Label 21*/ GIMT_Encode4(41608), |
| 970 | /* 334 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 22*/ GIMT_Encode4(99016), GIMT_Encode4(0), GIMT_Encode4(0), |
| 971 | /* 346 */ /*TargetOpcode::G_ANYEXT*//*Label 23*/ GIMT_Encode4(106678), |
| 972 | /* 350 */ /*TargetOpcode::G_TRUNC*//*Label 24*/ GIMT_Encode4(106836), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 973 | /* 366 */ /*TargetOpcode::G_CONSTANT*//*Label 25*/ GIMT_Encode4(106994), |
| 974 | /* 370 */ /*TargetOpcode::G_FCONSTANT*//*Label 26*/ GIMT_Encode4(107315), GIMT_Encode4(0), GIMT_Encode4(0), |
| 975 | /* 382 */ /*TargetOpcode::G_SEXT*//*Label 27*/ GIMT_Encode4(107411), |
| 976 | /* 386 */ /*TargetOpcode::G_SEXT_INREG*//*Label 28*/ GIMT_Encode4(107569), |
| 977 | /* 390 */ /*TargetOpcode::G_ZEXT*//*Label 29*/ GIMT_Encode4(108174), |
| 978 | /* 394 */ /*TargetOpcode::G_SHL*//*Label 30*/ GIMT_Encode4(108890), |
| 979 | /* 398 */ /*TargetOpcode::G_LSHR*//*Label 31*/ GIMT_Encode4(109106), |
| 980 | /* 402 */ /*TargetOpcode::G_ASHR*//*Label 32*/ GIMT_Encode4(109214), GIMT_Encode4(0), GIMT_Encode4(0), |
| 981 | /* 414 */ /*TargetOpcode::G_ROTR*//*Label 33*/ GIMT_Encode4(109487), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 982 | /* 482 */ /*TargetOpcode::G_UMULH*//*Label 34*/ GIMT_Encode4(109819), |
| 983 | /* 486 */ /*TargetOpcode::G_SMULH*//*Label 35*/ GIMT_Encode4(110067), |
| 984 | /* 490 */ /*TargetOpcode::G_UADDSAT*//*Label 36*/ GIMT_Encode4(110436), |
| 985 | /* 494 */ /*TargetOpcode::G_SADDSAT*//*Label 37*/ GIMT_Encode4(111081), |
| 986 | /* 498 */ /*TargetOpcode::G_USUBSAT*//*Label 38*/ GIMT_Encode4(112381), |
| 987 | /* 502 */ /*TargetOpcode::G_SSUBSAT*//*Label 39*/ GIMT_Encode4(113026), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 988 | /* 546 */ /*TargetOpcode::G_FADD*//*Label 40*/ GIMT_Encode4(114046), |
| 989 | /* 550 */ /*TargetOpcode::G_FSUB*//*Label 41*/ GIMT_Encode4(116399), |
| 990 | /* 554 */ /*TargetOpcode::G_FMUL*//*Label 42*/ GIMT_Encode4(118076), |
| 991 | /* 558 */ /*TargetOpcode::G_FMA*//*Label 43*/ GIMT_Encode4(119057), GIMT_Encode4(0), |
| 992 | /* 566 */ /*TargetOpcode::G_FDIV*//*Label 44*/ GIMT_Encode4(121148), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 993 | /* 618 */ /*TargetOpcode::G_FNEG*//*Label 45*/ GIMT_Encode4(121313), |
| 994 | /* 622 */ /*TargetOpcode::G_FPEXT*//*Label 46*/ GIMT_Encode4(123753), |
| 995 | /* 626 */ /*TargetOpcode::G_FPTRUNC*//*Label 47*/ GIMT_Encode4(123989), |
| 996 | /* 630 */ /*TargetOpcode::G_FPTOSI*//*Label 48*/ GIMT_Encode4(124261), |
| 997 | /* 634 */ /*TargetOpcode::G_FPTOUI*//*Label 49*/ GIMT_Encode4(125595), |
| 998 | /* 638 */ /*TargetOpcode::G_SITOFP*//*Label 50*/ GIMT_Encode4(126929), |
| 999 | /* 642 */ /*TargetOpcode::G_UITOFP*//*Label 51*/ GIMT_Encode4(127581), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1000 | /* 654 */ /*TargetOpcode::G_FABS*//*Label 52*/ GIMT_Encode4(128233), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1001 | /* 670 */ /*TargetOpcode::G_FMINNUM*//*Label 53*/ GIMT_Encode4(129009), |
| 1002 | /* 674 */ /*TargetOpcode::G_FMAXNUM*//*Label 54*/ GIMT_Encode4(129601), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1003 | /* 686 */ /*TargetOpcode::G_FMINIMUM*//*Label 55*/ GIMT_Encode4(130193), |
| 1004 | /* 690 */ /*TargetOpcode::G_FMAXIMUM*//*Label 56*/ GIMT_Encode4(130927), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1005 | /* 702 */ /*TargetOpcode::G_GET_FPENV*//*Label 57*/ GIMT_Encode4(131661), |
| 1006 | /* 706 */ /*TargetOpcode::G_SET_FPENV*//*Label 58*/ GIMT_Encode4(131694), |
| 1007 | /* 710 */ /*TargetOpcode::G_RESET_FPENV*//*Label 59*/ GIMT_Encode4(131730), |
| 1008 | /* 714 */ /*TargetOpcode::G_GET_FPMODE*//*Label 60*/ GIMT_Encode4(131859), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1009 | /* 742 */ /*TargetOpcode::G_SMIN*//*Label 61*/ GIMT_Encode4(131892), |
| 1010 | /* 746 */ /*TargetOpcode::G_SMAX*//*Label 62*/ GIMT_Encode4(132435), |
| 1011 | /* 750 */ /*TargetOpcode::G_UMIN*//*Label 63*/ GIMT_Encode4(132978), |
| 1012 | /* 754 */ /*TargetOpcode::G_UMAX*//*Label 64*/ GIMT_Encode4(133899), |
| 1013 | /* 758 */ /*TargetOpcode::G_ABS*//*Label 65*/ GIMT_Encode4(134820), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1014 | /* 770 */ /*TargetOpcode::G_BR*//*Label 66*/ GIMT_Encode4(135291), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1015 | /* 790 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 67*/ GIMT_Encode4(135364), |
| 1016 | /* 794 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 68*/ GIMT_Encode4(135664), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1017 | /* 822 */ /*TargetOpcode::G_CTLZ*//*Label 69*/ GIMT_Encode4(135721), GIMT_Encode4(0), |
| 1018 | /* 830 */ /*TargetOpcode::G_CTLS*//*Label 70*/ GIMT_Encode4(136282), |
| 1019 | /* 834 */ /*TargetOpcode::G_CTPOP*//*Label 71*/ GIMT_Encode4(136753), |
| 1020 | /* 838 */ /*TargetOpcode::G_BSWAP*//*Label 72*/ GIMT_Encode4(136861), |
| 1021 | /* 842 */ /*TargetOpcode::G_BITREVERSE*//*Label 73*/ GIMT_Encode4(137151), |
| 1022 | /* 846 */ /*TargetOpcode::G_FCEIL*//*Label 74*/ GIMT_Encode4(137583), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1023 | /* 894 */ /*TargetOpcode::G_FSQRT*//*Label 75*/ GIMT_Encode4(137958), |
| 1024 | /* 898 */ /*TargetOpcode::G_FFLOOR*//*Label 76*/ GIMT_Encode4(138096), |
| 1025 | /* 902 */ /*TargetOpcode::G_FRINT*//*Label 77*/ GIMT_Encode4(138471), |
| 1026 | /* 906 */ /*TargetOpcode::G_FNEARBYINT*//*Label 78*/ GIMT_Encode4(138879), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1027 | /* 934 */ /*TargetOpcode::G_STRICT_FADD*//*Label 79*/ GIMT_Encode4(139017), |
| 1028 | /* 938 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 80*/ GIMT_Encode4(139182), |
| 1029 | /* 942 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 81*/ GIMT_Encode4(139347), |
| 1030 | /* 946 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 82*/ GIMT_Encode4(139512), GIMT_Encode4(0), |
| 1031 | /* 954 */ /*TargetOpcode::G_STRICT_FMA*//*Label 83*/ GIMT_Encode4(139677), |
| 1032 | /* 958 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 84*/ GIMT_Encode4(140862), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1033 | /* 994 */ /*TargetOpcode::G_TRAP*//*Label 85*/ GIMT_Encode4(141000), |
| 1034 | /* 998 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 86*/ GIMT_Encode4(141031), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1035 | /* 1038 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 87*/ GIMT_Encode4(141118), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1036 | /* 1058 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 88*/ GIMT_Encode4(141539), |
| 1037 | /* 1062 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 89*/ GIMT_Encode4(141819), |
| 1038 | /* 1066 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 90*/ GIMT_Encode4(142108), |
| 1039 | /* 1070 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 91*/ GIMT_Encode4(142389), |
| 1040 | /* 1074 */ // Label 0: @1074 |
| 1041 | /* 1074 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 102*/ GIMT_Encode4(13000), |
| 1042 | /* 1085 */ /*GILLT_s32*//*Label 93*/ GIMT_Encode4(1145), |
| 1043 | /* 1089 */ /*GILLT_s64*//*Label 94*/ GIMT_Encode4(6921), GIMT_Encode4(0), |
| 1044 | /* 1097 */ /*GILLT_v2s32*//*Label 95*/ GIMT_Encode4(6968), |
| 1045 | /* 1101 */ /*GILLT_v2s64*//*Label 96*/ GIMT_Encode4(7417), GIMT_Encode4(0), |
| 1046 | /* 1109 */ /*GILLT_v4s16*//*Label 97*/ GIMT_Encode4(8440), |
| 1047 | /* 1113 */ /*GILLT_v4s32*//*Label 98*/ GIMT_Encode4(8889), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1048 | /* 1125 */ /*GILLT_v8s8*//*Label 99*/ GIMT_Encode4(10453), |
| 1049 | /* 1129 */ /*GILLT_v8s16*//*Label 100*/ GIMT_Encode4(10902), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1050 | /* 1141 */ /*GILLT_v16s8*//*Label 101*/ GIMT_Encode4(12466), |
| 1051 | /* 1145 */ // Label 93: @1145 |
| 1052 | /* 1145 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(6920), |
| 1053 | /* 1150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1054 | /* 1153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1055 | /* 1156 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1231), // Rule ID 6250 // |
| 1056 | /* 1161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1057 | /* 1164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1058 | /* 1168 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1059 | /* 1172 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1060 | /* 1176 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1061 | /* 1180 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1062 | /* 1184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1063 | /* 1189 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1064 | /* 1200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1065 | /* 1204 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1066 | /* 1206 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1067 | /* 1206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1068 | /* 1209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1069 | /* 1211 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1070 | /* 1213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1071 | /* 1217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1072 | /* 1220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1073 | /* 1223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1074 | /* 1229 */ GIR_RootConstrainSelectedInstOperands, |
| 1075 | /* 1230 */ // GIR_Coverage, 6250, |
| 1076 | /* 1230 */ GIR_EraseRootFromParent_Done, |
| 1077 | /* 1231 */ // Label 104: @1231 |
| 1078 | /* 1231 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1306), // Rule ID 6251 // |
| 1079 | /* 1236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1080 | /* 1239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1081 | /* 1243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1082 | /* 1247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1083 | /* 1251 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1084 | /* 1255 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1085 | /* 1259 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1086 | /* 1264 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1087 | /* 1275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1088 | /* 1279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1089 | /* 1281 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1090 | /* 1281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1091 | /* 1284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1092 | /* 1286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1093 | /* 1288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1094 | /* 1292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1095 | /* 1295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1096 | /* 1298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1097 | /* 1304 */ GIR_RootConstrainSelectedInstOperands, |
| 1098 | /* 1305 */ // GIR_Coverage, 6251, |
| 1099 | /* 1305 */ GIR_EraseRootFromParent_Done, |
| 1100 | /* 1306 */ // Label 105: @1306 |
| 1101 | /* 1306 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1381), // Rule ID 6285 // |
| 1102 | /* 1311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1103 | /* 1314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1104 | /* 1318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1105 | /* 1322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1106 | /* 1326 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1107 | /* 1330 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1108 | /* 1334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1109 | /* 1339 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1110 | /* 1350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1111 | /* 1354 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1112 | /* 1356 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1113 | /* 1356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1114 | /* 1359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1115 | /* 1361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1116 | /* 1363 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1117 | /* 1367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1118 | /* 1370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1119 | /* 1373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1120 | /* 1379 */ GIR_RootConstrainSelectedInstOperands, |
| 1121 | /* 1380 */ // GIR_Coverage, 6285, |
| 1122 | /* 1380 */ GIR_EraseRootFromParent_Done, |
| 1123 | /* 1381 */ // Label 106: @1381 |
| 1124 | /* 1381 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1456), // Rule ID 6286 // |
| 1125 | /* 1386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1126 | /* 1389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1127 | /* 1393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1128 | /* 1397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1129 | /* 1401 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1130 | /* 1405 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1131 | /* 1409 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1132 | /* 1414 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1133 | /* 1425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1134 | /* 1429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1135 | /* 1431 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1136 | /* 1431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1137 | /* 1434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1138 | /* 1436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1139 | /* 1438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1140 | /* 1442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1141 | /* 1445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1142 | /* 1448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1143 | /* 1454 */ GIR_RootConstrainSelectedInstOperands, |
| 1144 | /* 1455 */ // GIR_Coverage, 6286, |
| 1145 | /* 1455 */ GIR_EraseRootFromParent_Done, |
| 1146 | /* 1456 */ // Label 107: @1456 |
| 1147 | /* 1456 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1531), // Rule ID 2185 // |
| 1148 | /* 1461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1149 | /* 1464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1150 | /* 1468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1151 | /* 1472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1152 | /* 1476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1153 | /* 1480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1154 | /* 1484 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1155 | /* 1488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1156 | /* 1493 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1157 | /* 1504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1158 | /* 1506 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1159 | /* 1506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1160 | /* 1509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1161 | /* 1511 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1162 | /* 1513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1163 | /* 1517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1164 | /* 1520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1165 | /* 1523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1166 | /* 1529 */ GIR_RootConstrainSelectedInstOperands, |
| 1167 | /* 1530 */ // GIR_Coverage, 2185, |
| 1168 | /* 1530 */ GIR_EraseRootFromParent_Done, |
| 1169 | /* 1531 */ // Label 108: @1531 |
| 1170 | /* 1531 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1606), // Rule ID 2186 // |
| 1171 | /* 1536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1172 | /* 1539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1173 | /* 1543 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1174 | /* 1547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1175 | /* 1551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1176 | /* 1555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1177 | /* 1559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1178 | /* 1563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1179 | /* 1568 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1180 | /* 1579 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1181 | /* 1581 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1182 | /* 1581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1183 | /* 1584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1184 | /* 1586 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1185 | /* 1588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1186 | /* 1592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1187 | /* 1595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1188 | /* 1598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1189 | /* 1604 */ GIR_RootConstrainSelectedInstOperands, |
| 1190 | /* 1605 */ // GIR_Coverage, 2186, |
| 1191 | /* 1605 */ GIR_EraseRootFromParent_Done, |
| 1192 | /* 1606 */ // Label 109: @1606 |
| 1193 | /* 1606 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1681), // Rule ID 2424 // |
| 1194 | /* 1611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1195 | /* 1614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1196 | /* 1618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1197 | /* 1622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1198 | /* 1626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1199 | /* 1630 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1200 | /* 1634 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1201 | /* 1638 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1202 | /* 1643 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1203 | /* 1654 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1204 | /* 1656 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1205 | /* 1656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1206 | /* 1659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1207 | /* 1661 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1208 | /* 1663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1209 | /* 1667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1210 | /* 1670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1211 | /* 1673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1212 | /* 1679 */ GIR_RootConstrainSelectedInstOperands, |
| 1213 | /* 1680 */ // GIR_Coverage, 2424, |
| 1214 | /* 1680 */ GIR_EraseRootFromParent_Done, |
| 1215 | /* 1681 */ // Label 110: @1681 |
| 1216 | /* 1681 */ GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(1756), // Rule ID 2425 // |
| 1217 | /* 1686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1218 | /* 1689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1219 | /* 1693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1220 | /* 1697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1221 | /* 1701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1222 | /* 1705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1223 | /* 1709 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1224 | /* 1713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1225 | /* 1718 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1226 | /* 1729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1227 | /* 1731 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1228 | /* 1731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1229 | /* 1734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1230 | /* 1736 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1231 | /* 1738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1232 | /* 1742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1233 | /* 1745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1234 | /* 1748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1235 | /* 1754 */ GIR_RootConstrainSelectedInstOperands, |
| 1236 | /* 1755 */ // GIR_Coverage, 2425, |
| 1237 | /* 1755 */ GIR_EraseRootFromParent_Done, |
| 1238 | /* 1756 */ // Label 111: @1756 |
| 1239 | /* 1756 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1884), // Rule ID 6261 // |
| 1240 | /* 1761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1241 | /* 1764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1242 | /* 1768 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1243 | /* 1772 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1244 | /* 1776 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1245 | /* 1780 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1246 | /* 1784 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1247 | /* 1788 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1248 | /* 1792 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1249 | /* 1796 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1250 | /* 1800 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1251 | /* 1804 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1252 | /* 1808 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1253 | /* 1812 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1254 | /* 1817 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1255 | /* 1821 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1256 | /* 1825 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1257 | /* 1829 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1258 | /* 1833 */ // MIs[4] Rm |
| 1259 | /* 1833 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1260 | /* 1838 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1261 | /* 1842 */ // MIs[1] Operand 2 |
| 1262 | /* 1842 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1263 | /* 1853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1264 | /* 1857 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1265 | /* 1859 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1266 | /* 1859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1267 | /* 1862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1268 | /* 1864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1269 | /* 1866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1270 | /* 1870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1271 | /* 1873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1272 | /* 1876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1273 | /* 1882 */ GIR_RootConstrainSelectedInstOperands, |
| 1274 | /* 1883 */ // GIR_Coverage, 6261, |
| 1275 | /* 1883 */ GIR_EraseRootFromParent_Done, |
| 1276 | /* 1884 */ // Label 112: @1884 |
| 1277 | /* 1884 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(2012), // Rule ID 6262 // |
| 1278 | /* 1889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1279 | /* 1892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1280 | /* 1896 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1281 | /* 1900 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1282 | /* 1904 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1283 | /* 1908 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1284 | /* 1912 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1285 | /* 1916 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1286 | /* 1920 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1287 | /* 1924 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1288 | /* 1928 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1289 | /* 1932 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1290 | /* 1936 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1291 | /* 1940 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1292 | /* 1945 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1293 | /* 1949 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1294 | /* 1953 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1295 | /* 1957 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1296 | /* 1961 */ // MIs[4] Rm |
| 1297 | /* 1961 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1298 | /* 1966 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1299 | /* 1970 */ // MIs[1] Operand 2 |
| 1300 | /* 1970 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1301 | /* 1981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1302 | /* 1985 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1303 | /* 1987 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1304 | /* 1987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1305 | /* 1990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1306 | /* 1992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1307 | /* 1994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1308 | /* 1998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1309 | /* 2001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1310 | /* 2004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1311 | /* 2010 */ GIR_RootConstrainSelectedInstOperands, |
| 1312 | /* 2011 */ // GIR_Coverage, 6262, |
| 1313 | /* 2011 */ GIR_EraseRootFromParent_Done, |
| 1314 | /* 2012 */ // Label 113: @2012 |
| 1315 | /* 2012 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(2140), // Rule ID 2291 // |
| 1316 | /* 2017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1317 | /* 2020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1318 | /* 2024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1319 | /* 2028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1320 | /* 2032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1321 | /* 2036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1322 | /* 2040 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1323 | /* 2044 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1324 | /* 2048 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1325 | /* 2052 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1326 | /* 2056 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1327 | /* 2060 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1328 | /* 2064 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1329 | /* 2068 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1330 | /* 2072 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1331 | /* 2077 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1332 | /* 2081 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1333 | /* 2085 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1334 | /* 2089 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1335 | /* 2093 */ // MIs[4] Rm |
| 1336 | /* 2093 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1337 | /* 2098 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1338 | /* 2102 */ // MIs[1] Operand 2 |
| 1339 | /* 2102 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1340 | /* 2113 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1341 | /* 2115 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1342 | /* 2115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1343 | /* 2118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1344 | /* 2120 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1345 | /* 2122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1346 | /* 2126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1347 | /* 2129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1348 | /* 2132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1349 | /* 2138 */ GIR_RootConstrainSelectedInstOperands, |
| 1350 | /* 2139 */ // GIR_Coverage, 2291, |
| 1351 | /* 2139 */ GIR_EraseRootFromParent_Done, |
| 1352 | /* 2140 */ // Label 114: @2140 |
| 1353 | /* 2140 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(2268), // Rule ID 6260 // |
| 1354 | /* 2145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1355 | /* 2148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1356 | /* 2152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1357 | /* 2156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1358 | /* 2160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1359 | /* 2164 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1360 | /* 2168 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1361 | /* 2172 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1362 | /* 2176 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1363 | /* 2180 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1364 | /* 2184 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1365 | /* 2188 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1366 | /* 2192 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1367 | /* 2196 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1368 | /* 2200 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1369 | /* 2205 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1370 | /* 2209 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1371 | /* 2213 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1372 | /* 2217 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1373 | /* 2221 */ // MIs[4] Rm |
| 1374 | /* 2221 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1375 | /* 2226 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1376 | /* 2230 */ // MIs[1] Operand 2 |
| 1377 | /* 2230 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1378 | /* 2241 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1379 | /* 2243 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1380 | /* 2243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1381 | /* 2246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1382 | /* 2248 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1383 | /* 2250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1384 | /* 2254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1385 | /* 2257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1386 | /* 2260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1387 | /* 2266 */ GIR_RootConstrainSelectedInstOperands, |
| 1388 | /* 2267 */ // GIR_Coverage, 6260, |
| 1389 | /* 2267 */ GIR_EraseRootFromParent_Done, |
| 1390 | /* 2268 */ // Label 115: @2268 |
| 1391 | /* 2268 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(2378), // Rule ID 5963 // |
| 1392 | /* 2273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1393 | /* 2276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1394 | /* 2280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1395 | /* 2284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1396 | /* 2288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1397 | /* 2292 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1398 | /* 2296 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1399 | /* 2300 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1400 | /* 2304 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1401 | /* 2308 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1402 | /* 2312 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1403 | /* 2317 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1404 | /* 2321 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1405 | /* 2325 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1406 | /* 2329 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1407 | /* 2333 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1408 | /* 2337 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1409 | /* 2342 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1410 | /* 2346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1411 | /* 2350 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1412 | /* 2352 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1413 | /* 2352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1414 | /* 2355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1415 | /* 2357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1416 | /* 2361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1417 | /* 2365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1418 | /* 2367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1419 | /* 2370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1420 | /* 2376 */ GIR_RootConstrainSelectedInstOperands, |
| 1421 | /* 2377 */ // GIR_Coverage, 5963, |
| 1422 | /* 2377 */ GIR_EraseRootFromParent_Done, |
| 1423 | /* 2378 */ // Label 116: @2378 |
| 1424 | /* 2378 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(2488), // Rule ID 6000 // |
| 1425 | /* 2383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1426 | /* 2386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1427 | /* 2390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1428 | /* 2394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1429 | /* 2398 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1430 | /* 2402 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1431 | /* 2406 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1432 | /* 2410 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1433 | /* 2414 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1434 | /* 2418 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1435 | /* 2422 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1436 | /* 2427 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1437 | /* 2431 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1438 | /* 2435 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1439 | /* 2439 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1440 | /* 2443 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1441 | /* 2447 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1442 | /* 2452 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1443 | /* 2456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1444 | /* 2460 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1445 | /* 2462 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1446 | /* 2462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1447 | /* 2465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1448 | /* 2467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1449 | /* 2471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1450 | /* 2475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1451 | /* 2477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1452 | /* 2480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1453 | /* 2486 */ GIR_RootConstrainSelectedInstOperands, |
| 1454 | /* 2487 */ // GIR_Coverage, 6000, |
| 1455 | /* 2487 */ GIR_EraseRootFromParent_Done, |
| 1456 | /* 2488 */ // Label 117: @2488 |
| 1457 | /* 2488 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(2598), // Rule ID 191 // |
| 1458 | /* 2493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1459 | /* 2496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1460 | /* 2500 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1461 | /* 2504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1462 | /* 2508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1463 | /* 2512 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1464 | /* 2516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1465 | /* 2520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1466 | /* 2524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1467 | /* 2528 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1468 | /* 2532 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1469 | /* 2536 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1470 | /* 2541 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1471 | /* 2545 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1472 | /* 2549 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1473 | /* 2553 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1474 | /* 2557 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1475 | /* 2561 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1476 | /* 2566 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1477 | /* 2570 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1478 | /* 2572 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1479 | /* 2572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1480 | /* 2575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1481 | /* 2577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1482 | /* 2581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1483 | /* 2585 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1484 | /* 2587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1485 | /* 2590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1486 | /* 2596 */ GIR_RootConstrainSelectedInstOperands, |
| 1487 | /* 2597 */ // GIR_Coverage, 191, |
| 1488 | /* 2597 */ GIR_EraseRootFromParent_Done, |
| 1489 | /* 2598 */ // Label 118: @2598 |
| 1490 | /* 2598 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2708), // Rule ID 520 // |
| 1491 | /* 2603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1492 | /* 2606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1493 | /* 2610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1494 | /* 2614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1495 | /* 2618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1496 | /* 2622 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1497 | /* 2626 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1498 | /* 2630 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1499 | /* 2634 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1500 | /* 2638 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1501 | /* 2642 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1502 | /* 2646 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1503 | /* 2651 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1504 | /* 2655 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1505 | /* 2659 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1506 | /* 2663 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1507 | /* 2667 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1508 | /* 2671 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1509 | /* 2676 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1510 | /* 2680 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1511 | /* 2682 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1512 | /* 2682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1513 | /* 2685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1514 | /* 2687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1515 | /* 2691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1516 | /* 2695 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1517 | /* 2697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1518 | /* 2700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1519 | /* 2706 */ GIR_RootConstrainSelectedInstOperands, |
| 1520 | /* 2707 */ // GIR_Coverage, 520, |
| 1521 | /* 2707 */ GIR_EraseRootFromParent_Done, |
| 1522 | /* 2708 */ // Label 119: @2708 |
| 1523 | /* 2708 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2821), // Rule ID 5962 // |
| 1524 | /* 2713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1525 | /* 2716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1526 | /* 2720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1527 | /* 2724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1528 | /* 2728 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1529 | /* 2732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1530 | /* 2736 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1531 | /* 2740 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1532 | /* 2744 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1533 | /* 2748 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1534 | /* 2752 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1535 | /* 2757 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1536 | /* 2761 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1537 | /* 2765 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1538 | /* 2769 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1539 | /* 2773 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1540 | /* 2778 */ // MIs[3] Operand 2 |
| 1541 | /* 2778 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1542 | /* 2789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1543 | /* 2793 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1544 | /* 2795 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1545 | /* 2795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1546 | /* 2798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1547 | /* 2800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1548 | /* 2804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1549 | /* 2808 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1550 | /* 2810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1551 | /* 2813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1552 | /* 2819 */ GIR_RootConstrainSelectedInstOperands, |
| 1553 | /* 2820 */ // GIR_Coverage, 5962, |
| 1554 | /* 2820 */ GIR_EraseRootFromParent_Done, |
| 1555 | /* 2821 */ // Label 120: @2821 |
| 1556 | /* 2821 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2934), // Rule ID 5999 // |
| 1557 | /* 2826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1558 | /* 2829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1559 | /* 2833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1560 | /* 2837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1561 | /* 2841 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1562 | /* 2845 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1563 | /* 2849 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1564 | /* 2853 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1565 | /* 2857 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1566 | /* 2861 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1567 | /* 2865 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1568 | /* 2870 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1569 | /* 2874 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1570 | /* 2878 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1571 | /* 2882 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1572 | /* 2886 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1573 | /* 2891 */ // MIs[3] Operand 2 |
| 1574 | /* 2891 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1575 | /* 2902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1576 | /* 2906 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1577 | /* 2908 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1578 | /* 2908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1579 | /* 2911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1580 | /* 2913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1581 | /* 2917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1582 | /* 2921 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1583 | /* 2923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1584 | /* 2926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1585 | /* 2932 */ GIR_RootConstrainSelectedInstOperands, |
| 1586 | /* 2933 */ // GIR_Coverage, 5999, |
| 1587 | /* 2933 */ GIR_EraseRootFromParent_Done, |
| 1588 | /* 2934 */ // Label 121: @2934 |
| 1589 | /* 2934 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(3047), // Rule ID 5961 // |
| 1590 | /* 2939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1591 | /* 2942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1592 | /* 2946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1593 | /* 2950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1594 | /* 2954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1595 | /* 2958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1596 | /* 2962 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1597 | /* 2966 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1598 | /* 2970 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1599 | /* 2974 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1600 | /* 2979 */ // MIs[2] Operand 2 |
| 1601 | /* 2979 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1602 | /* 2990 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1603 | /* 2994 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1604 | /* 2998 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1605 | /* 3002 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1606 | /* 3006 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1607 | /* 3011 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1608 | /* 3015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1609 | /* 3019 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1610 | /* 3021 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1611 | /* 3021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1612 | /* 3024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1613 | /* 3026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1614 | /* 3030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1615 | /* 3034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1616 | /* 3036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1617 | /* 3039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1618 | /* 3045 */ GIR_RootConstrainSelectedInstOperands, |
| 1619 | /* 3046 */ // GIR_Coverage, 5961, |
| 1620 | /* 3046 */ GIR_EraseRootFromParent_Done, |
| 1621 | /* 3047 */ // Label 122: @3047 |
| 1622 | /* 3047 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(3160), // Rule ID 5998 // |
| 1623 | /* 3052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1624 | /* 3055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1625 | /* 3059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1626 | /* 3063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1627 | /* 3067 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1628 | /* 3071 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1629 | /* 3075 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1630 | /* 3079 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1631 | /* 3083 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1632 | /* 3087 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1633 | /* 3092 */ // MIs[2] Operand 2 |
| 1634 | /* 3092 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1635 | /* 3103 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1636 | /* 3107 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1637 | /* 3111 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1638 | /* 3115 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1639 | /* 3119 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1640 | /* 3124 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1641 | /* 3128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1642 | /* 3132 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1643 | /* 3134 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1644 | /* 3134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1645 | /* 3137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1646 | /* 3139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1647 | /* 3143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1648 | /* 3147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1649 | /* 3149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1650 | /* 3152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1651 | /* 3158 */ GIR_RootConstrainSelectedInstOperands, |
| 1652 | /* 3159 */ // GIR_Coverage, 5998, |
| 1653 | /* 3159 */ GIR_EraseRootFromParent_Done, |
| 1654 | /* 3160 */ // Label 123: @3160 |
| 1655 | /* 3160 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(3273), // Rule ID 190 // |
| 1656 | /* 3165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1657 | /* 3168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1658 | /* 3172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1659 | /* 3176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1660 | /* 3180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1661 | /* 3184 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1662 | /* 3188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1663 | /* 3192 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1664 | /* 3196 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1665 | /* 3200 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1666 | /* 3204 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1667 | /* 3208 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1668 | /* 3213 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1669 | /* 3217 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1670 | /* 3221 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1671 | /* 3225 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1672 | /* 3229 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1673 | /* 3234 */ // MIs[3] Operand 2 |
| 1674 | /* 3234 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1675 | /* 3245 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1676 | /* 3247 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1677 | /* 3247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 1678 | /* 3250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1679 | /* 3252 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1680 | /* 3256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1681 | /* 3260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1682 | /* 3262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1683 | /* 3265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1684 | /* 3271 */ GIR_RootConstrainSelectedInstOperands, |
| 1685 | /* 3272 */ // GIR_Coverage, 190, |
| 1686 | /* 3272 */ GIR_EraseRootFromParent_Done, |
| 1687 | /* 3273 */ // Label 124: @3273 |
| 1688 | /* 3273 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(3386), // Rule ID 519 // |
| 1689 | /* 3278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1690 | /* 3281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1691 | /* 3285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1692 | /* 3289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1693 | /* 3293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1694 | /* 3297 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1695 | /* 3301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1696 | /* 3305 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1697 | /* 3309 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1698 | /* 3313 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1699 | /* 3317 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1700 | /* 3321 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1701 | /* 3326 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1702 | /* 3330 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1703 | /* 3334 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1704 | /* 3338 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1705 | /* 3342 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1706 | /* 3347 */ // MIs[3] Operand 2 |
| 1707 | /* 3347 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1708 | /* 3358 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1709 | /* 3360 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1710 | /* 3360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 1711 | /* 3363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1712 | /* 3365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1713 | /* 3369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1714 | /* 3373 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1715 | /* 3375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1716 | /* 3378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1717 | /* 3384 */ GIR_RootConstrainSelectedInstOperands, |
| 1718 | /* 3385 */ // GIR_Coverage, 519, |
| 1719 | /* 3385 */ GIR_EraseRootFromParent_Done, |
| 1720 | /* 3386 */ // Label 125: @3386 |
| 1721 | /* 3386 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(3499), // Rule ID 189 // |
| 1722 | /* 3391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1723 | /* 3394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1724 | /* 3398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1725 | /* 3402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1726 | /* 3406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1727 | /* 3410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1728 | /* 3414 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1729 | /* 3418 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1730 | /* 3422 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1731 | /* 3426 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1732 | /* 3430 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1733 | /* 3435 */ // MIs[2] Operand 2 |
| 1734 | /* 3435 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1735 | /* 3446 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1736 | /* 3450 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1737 | /* 3454 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1738 | /* 3458 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1739 | /* 3462 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1740 | /* 3467 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1741 | /* 3471 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1742 | /* 3473 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1743 | /* 3473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1744 | /* 3476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1745 | /* 3478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1746 | /* 3482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1747 | /* 3486 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1748 | /* 3488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1749 | /* 3491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1750 | /* 3497 */ GIR_RootConstrainSelectedInstOperands, |
| 1751 | /* 3498 */ // GIR_Coverage, 189, |
| 1752 | /* 3498 */ GIR_EraseRootFromParent_Done, |
| 1753 | /* 3499 */ // Label 126: @3499 |
| 1754 | /* 3499 */ GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(3612), // Rule ID 518 // |
| 1755 | /* 3504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1756 | /* 3507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1757 | /* 3511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1758 | /* 3515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1759 | /* 3519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1760 | /* 3523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1761 | /* 3527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1762 | /* 3531 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1763 | /* 3535 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1764 | /* 3539 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1765 | /* 3543 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1766 | /* 3548 */ // MIs[2] Operand 2 |
| 1767 | /* 3548 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1768 | /* 3559 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1769 | /* 3563 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1770 | /* 3567 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1771 | /* 3571 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1772 | /* 3575 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1773 | /* 3580 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1774 | /* 3584 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1775 | /* 3586 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1776 | /* 3586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1777 | /* 3589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1778 | /* 3591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1779 | /* 3595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1780 | /* 3599 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1781 | /* 3601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1782 | /* 3604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1783 | /* 3610 */ GIR_RootConstrainSelectedInstOperands, |
| 1784 | /* 3611 */ // GIR_Coverage, 518, |
| 1785 | /* 3611 */ GIR_EraseRootFromParent_Done, |
| 1786 | /* 3612 */ // Label 127: @3612 |
| 1787 | /* 3612 */ GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(3703), // Rule ID 6259 // |
| 1788 | /* 3617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1789 | /* 3620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1790 | /* 3624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1791 | /* 3628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1792 | /* 3632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1793 | /* 3636 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1794 | /* 3640 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1795 | /* 3644 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1796 | /* 3648 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1797 | /* 3652 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1798 | /* 3657 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1799 | /* 3661 */ // MIs[1] Operand 2 |
| 1800 | /* 3661 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1801 | /* 3672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1802 | /* 3676 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1803 | /* 3678 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1804 | /* 3678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1805 | /* 3681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1806 | /* 3683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1807 | /* 3685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1808 | /* 3689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1809 | /* 3692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1810 | /* 3695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1811 | /* 3701 */ GIR_RootConstrainSelectedInstOperands, |
| 1812 | /* 3702 */ // GIR_Coverage, 6259, |
| 1813 | /* 3702 */ GIR_EraseRootFromParent_Done, |
| 1814 | /* 3703 */ // Label 128: @3703 |
| 1815 | /* 3703 */ GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(3794), // Rule ID 2290 // |
| 1816 | /* 3708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1817 | /* 3711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1818 | /* 3715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1819 | /* 3719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1820 | /* 3723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1821 | /* 3727 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1822 | /* 3731 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1823 | /* 3735 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1824 | /* 3739 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1825 | /* 3743 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1826 | /* 3747 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1827 | /* 3752 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1828 | /* 3756 */ // MIs[1] Operand 2 |
| 1829 | /* 3756 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1830 | /* 3767 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1831 | /* 3769 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1832 | /* 3769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1833 | /* 3772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1834 | /* 3774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1835 | /* 3776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1836 | /* 3780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1837 | /* 3783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1838 | /* 3786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1839 | /* 3792 */ GIR_RootConstrainSelectedInstOperands, |
| 1840 | /* 3793 */ // GIR_Coverage, 2290, |
| 1841 | /* 3793 */ GIR_EraseRootFromParent_Done, |
| 1842 | /* 3794 */ // Label 129: @3794 |
| 1843 | /* 3794 */ GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(3910), // Rule ID 5960 // |
| 1844 | /* 3799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1845 | /* 3802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1846 | /* 3806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1847 | /* 3810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1848 | /* 3814 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1849 | /* 3818 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1850 | /* 3822 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1851 | /* 3826 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1852 | /* 3830 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1853 | /* 3834 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1854 | /* 3839 */ // MIs[2] Operand 2 |
| 1855 | /* 3839 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1856 | /* 3850 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1857 | /* 3854 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1858 | /* 3858 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1859 | /* 3862 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1860 | /* 3867 */ // MIs[3] Operand 2 |
| 1861 | /* 3867 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1862 | /* 3878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1863 | /* 3882 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1864 | /* 3884 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1865 | /* 3884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1866 | /* 3887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1867 | /* 3889 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1868 | /* 3893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1869 | /* 3897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1870 | /* 3899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1871 | /* 3902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1872 | /* 3908 */ GIR_RootConstrainSelectedInstOperands, |
| 1873 | /* 3909 */ // GIR_Coverage, 5960, |
| 1874 | /* 3909 */ GIR_EraseRootFromParent_Done, |
| 1875 | /* 3910 */ // Label 130: @3910 |
| 1876 | /* 3910 */ GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(4026), // Rule ID 5997 // |
| 1877 | /* 3915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1878 | /* 3918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1879 | /* 3922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1880 | /* 3926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1881 | /* 3930 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1882 | /* 3934 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1883 | /* 3938 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1884 | /* 3942 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1885 | /* 3946 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1886 | /* 3950 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1887 | /* 3955 */ // MIs[2] Operand 2 |
| 1888 | /* 3955 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1889 | /* 3966 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1890 | /* 3970 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1891 | /* 3974 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1892 | /* 3978 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1893 | /* 3983 */ // MIs[3] Operand 2 |
| 1894 | /* 3983 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1895 | /* 3994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1896 | /* 3998 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1897 | /* 4000 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1898 | /* 4000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1899 | /* 4003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1900 | /* 4005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1901 | /* 4009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1902 | /* 4013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1903 | /* 4015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1904 | /* 4018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1905 | /* 4024 */ GIR_RootConstrainSelectedInstOperands, |
| 1906 | /* 4025 */ // GIR_Coverage, 5997, |
| 1907 | /* 4025 */ GIR_EraseRootFromParent_Done, |
| 1908 | /* 4026 */ // Label 131: @4026 |
| 1909 | /* 4026 */ GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(4142), // Rule ID 188 // |
| 1910 | /* 4031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1911 | /* 4034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1912 | /* 4038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1913 | /* 4042 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1914 | /* 4046 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1915 | /* 4050 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1916 | /* 4054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1917 | /* 4058 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1918 | /* 4062 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1919 | /* 4066 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1920 | /* 4070 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1921 | /* 4075 */ // MIs[2] Operand 2 |
| 1922 | /* 4075 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1923 | /* 4086 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1924 | /* 4090 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1925 | /* 4094 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1926 | /* 4098 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1927 | /* 4103 */ // MIs[3] Operand 2 |
| 1928 | /* 4103 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1929 | /* 4114 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1930 | /* 4116 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1931 | /* 4116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1932 | /* 4119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1933 | /* 4121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1934 | /* 4125 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1935 | /* 4129 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1936 | /* 4131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1937 | /* 4134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1938 | /* 4140 */ GIR_RootConstrainSelectedInstOperands, |
| 1939 | /* 4141 */ // GIR_Coverage, 188, |
| 1940 | /* 4141 */ GIR_EraseRootFromParent_Done, |
| 1941 | /* 4142 */ // Label 132: @4142 |
| 1942 | /* 4142 */ GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(4258), // Rule ID 517 // |
| 1943 | /* 4147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1944 | /* 4150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1945 | /* 4154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1946 | /* 4158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1947 | /* 4162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1948 | /* 4166 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1949 | /* 4170 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1950 | /* 4174 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1951 | /* 4178 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1952 | /* 4182 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1953 | /* 4186 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1954 | /* 4191 */ // MIs[2] Operand 2 |
| 1955 | /* 4191 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1956 | /* 4202 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1957 | /* 4206 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1958 | /* 4210 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1959 | /* 4214 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1960 | /* 4219 */ // MIs[3] Operand 2 |
| 1961 | /* 4219 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1962 | /* 4230 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1963 | /* 4232 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1964 | /* 4232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1965 | /* 4235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1966 | /* 4237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1967 | /* 4241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1968 | /* 4245 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1969 | /* 4247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1970 | /* 4250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1971 | /* 4256 */ GIR_RootConstrainSelectedInstOperands, |
| 1972 | /* 4257 */ // GIR_Coverage, 517, |
| 1973 | /* 4257 */ GIR_EraseRootFromParent_Done, |
| 1974 | /* 4258 */ // Label 133: @4258 |
| 1975 | /* 4258 */ GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(4346), // Rule ID 3624 // |
| 1976 | /* 4263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 1977 | /* 4266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1978 | /* 4270 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1979 | /* 4274 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 1980 | /* 4278 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1981 | /* 4282 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1982 | /* 4286 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1983 | /* 4290 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1984 | /* 4294 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1985 | /* 4298 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1986 | /* 4303 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1987 | /* 4308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1988 | /* 4312 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1989 | /* 4314 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 1990 | /* 4314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 1991 | /* 4317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 1992 | /* 4319 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 1993 | /* 4321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 1994 | /* 4325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 1995 | /* 4329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1996 | /* 4332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1997 | /* 4338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1998 | /* 4344 */ GIR_RootConstrainSelectedInstOperands, |
| 1999 | /* 4345 */ // GIR_Coverage, 3624, |
| 2000 | /* 4345 */ GIR_EraseRootFromParent_Done, |
| 2001 | /* 4346 */ // Label 134: @4346 |
| 2002 | /* 4346 */ GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(4434), // Rule ID 3625 // |
| 2003 | /* 4351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2004 | /* 4354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2005 | /* 4358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2006 | /* 4362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2007 | /* 4366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2008 | /* 4370 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2009 | /* 4374 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2010 | /* 4378 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2011 | /* 4382 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2012 | /* 4386 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2013 | /* 4391 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2014 | /* 4396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2015 | /* 4400 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2016 | /* 4402 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 2017 | /* 4402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 2018 | /* 4405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2019 | /* 4407 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 2020 | /* 4409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2021 | /* 4413 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2022 | /* 4417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2023 | /* 4420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2024 | /* 4426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2025 | /* 4432 */ GIR_RootConstrainSelectedInstOperands, |
| 2026 | /* 4433 */ // GIR_Coverage, 3625, |
| 2027 | /* 4433 */ GIR_EraseRootFromParent_Done, |
| 2028 | /* 4434 */ // Label 135: @4434 |
| 2029 | /* 4434 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(4522), // Rule ID 3628 // |
| 2030 | /* 4439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2031 | /* 4442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2032 | /* 4446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2033 | /* 4450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2034 | /* 4454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2035 | /* 4458 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2036 | /* 4462 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2037 | /* 4466 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2038 | /* 4470 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2039 | /* 4474 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2040 | /* 4479 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2041 | /* 4484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2042 | /* 4488 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2043 | /* 4490 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2044 | /* 4490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2045 | /* 4493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2046 | /* 4495 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 2047 | /* 4497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2048 | /* 4501 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2049 | /* 4505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2050 | /* 4508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2051 | /* 4514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2052 | /* 4520 */ GIR_RootConstrainSelectedInstOperands, |
| 2053 | /* 4521 */ // GIR_Coverage, 3628, |
| 2054 | /* 4521 */ GIR_EraseRootFromParent_Done, |
| 2055 | /* 4522 */ // Label 136: @4522 |
| 2056 | /* 4522 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(4610), // Rule ID 6557 // |
| 2057 | /* 4527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2058 | /* 4530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2059 | /* 4534 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2060 | /* 4538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2061 | /* 4542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2062 | /* 4546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2063 | /* 4550 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2064 | /* 4554 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2065 | /* 4558 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2066 | /* 4562 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2067 | /* 4566 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2068 | /* 4571 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2069 | /* 4576 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2070 | /* 4578 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 2071 | /* 4578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 2072 | /* 4581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2073 | /* 4583 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2074 | /* 4585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2075 | /* 4589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2076 | /* 4593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2077 | /* 4596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2078 | /* 4602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2079 | /* 4608 */ GIR_RootConstrainSelectedInstOperands, |
| 2080 | /* 4609 */ // GIR_Coverage, 6557, |
| 2081 | /* 4609 */ GIR_EraseRootFromParent_Done, |
| 2082 | /* 4610 */ // Label 137: @4610 |
| 2083 | /* 4610 */ GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(4698), // Rule ID 6558 // |
| 2084 | /* 4615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2085 | /* 4618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2086 | /* 4622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2087 | /* 4626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2088 | /* 4630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2089 | /* 4634 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2090 | /* 4638 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2091 | /* 4642 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2092 | /* 4646 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2093 | /* 4650 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2094 | /* 4654 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2095 | /* 4659 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2096 | /* 4664 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2097 | /* 4666 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 2098 | /* 4666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 2099 | /* 4669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2100 | /* 4671 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2101 | /* 4673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2102 | /* 4677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2103 | /* 4681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2104 | /* 4684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2105 | /* 4690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2106 | /* 4696 */ GIR_RootConstrainSelectedInstOperands, |
| 2107 | /* 4697 */ // GIR_Coverage, 6558, |
| 2108 | /* 4697 */ GIR_EraseRootFromParent_Done, |
| 2109 | /* 4698 */ // Label 138: @4698 |
| 2110 | /* 4698 */ GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(4786), // Rule ID 6561 // |
| 2111 | /* 4703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2112 | /* 4706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2113 | /* 4710 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2114 | /* 4714 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2115 | /* 4718 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2116 | /* 4722 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2117 | /* 4726 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2118 | /* 4730 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2119 | /* 4734 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2120 | /* 4738 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2121 | /* 4742 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2122 | /* 4747 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2123 | /* 4752 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2124 | /* 4754 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2125 | /* 4754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2126 | /* 4757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2127 | /* 4759 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2128 | /* 4761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2129 | /* 4765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2130 | /* 4769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2131 | /* 4772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2132 | /* 4778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2133 | /* 4784 */ GIR_RootConstrainSelectedInstOperands, |
| 2134 | /* 4785 */ // GIR_Coverage, 6561, |
| 2135 | /* 4785 */ GIR_EraseRootFromParent_Done, |
| 2136 | /* 4786 */ // Label 139: @4786 |
| 2137 | /* 4786 */ GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(4843), // Rule ID 71 // |
| 2138 | /* 4791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 2139 | /* 4794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2140 | /* 4798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2141 | /* 4802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2142 | /* 4806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2143 | /* 4810 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 2144 | /* 4814 */ // MIs[1] Operand 1 |
| 2145 | /* 4814 */ // No operand predicates |
| 2146 | /* 4814 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2147 | /* 4816 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2148 | /* 4816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri), |
| 2149 | /* 4819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2150 | /* 4821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2151 | /* 4823 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2152 | /* 4826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2153 | /* 4829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2154 | /* 4835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2155 | /* 4841 */ GIR_RootConstrainSelectedInstOperands, |
| 2156 | /* 4842 */ // GIR_Coverage, 71, |
| 2157 | /* 4842 */ GIR_EraseRootFromParent_Done, |
| 2158 | /* 4843 */ // Label 140: @4843 |
| 2159 | /* 4843 */ GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(4900), // Rule ID 302 // |
| 2160 | /* 4848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 2161 | /* 4851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2162 | /* 4855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2163 | /* 4859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2164 | /* 4863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2165 | /* 4867 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 2166 | /* 4871 */ // MIs[1] Operand 1 |
| 2167 | /* 4871 */ // No operand predicates |
| 2168 | /* 4871 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2169 | /* 4873 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3) |
| 2170 | /* 4873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3), |
| 2171 | /* 4876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2172 | /* 4878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2173 | /* 4884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2174 | /* 4886 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3 |
| 2175 | /* 4889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2176 | /* 4892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2177 | /* 4898 */ GIR_RootConstrainSelectedInstOperands, |
| 2178 | /* 4899 */ // GIR_Coverage, 302, |
| 2179 | /* 4899 */ GIR_EraseRootFromParent_Done, |
| 2180 | /* 4900 */ // Label 141: @4900 |
| 2181 | /* 4900 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(4957), // Rule ID 303 // |
| 2182 | /* 4905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 2183 | /* 4908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2184 | /* 4912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2185 | /* 4916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2186 | /* 4920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2187 | /* 4924 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 2188 | /* 4928 */ // MIs[1] Operand 1 |
| 2189 | /* 4928 */ // No operand predicates |
| 2190 | /* 4928 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2191 | /* 4930 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8) |
| 2192 | /* 4930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8), |
| 2193 | /* 4933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 2194 | /* 4935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2195 | /* 4941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2196 | /* 4943 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 2197 | /* 4946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2198 | /* 4949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2199 | /* 4955 */ GIR_RootConstrainSelectedInstOperands, |
| 2200 | /* 4956 */ // GIR_Coverage, 303, |
| 2201 | /* 4956 */ GIR_EraseRootFromParent_Done, |
| 2202 | /* 4957 */ // Label 142: @4957 |
| 2203 | /* 4957 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(5014), // Rule ID 406 // |
| 2204 | /* 4962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2205 | /* 4965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2206 | /* 4969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2207 | /* 4973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2208 | /* 4977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2209 | /* 4981 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 2210 | /* 4985 */ // MIs[1] Operand 1 |
| 2211 | /* 4985 */ // No operand predicates |
| 2212 | /* 4985 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2213 | /* 4987 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2214 | /* 4987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri), |
| 2215 | /* 4990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2216 | /* 4992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2217 | /* 4994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2218 | /* 4997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2219 | /* 5000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2220 | /* 5006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2221 | /* 5012 */ GIR_RootConstrainSelectedInstOperands, |
| 2222 | /* 5013 */ // GIR_Coverage, 406, |
| 2223 | /* 5013 */ GIR_EraseRootFromParent_Done, |
| 2224 | /* 5014 */ // Label 143: @5014 |
| 2225 | /* 5014 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(5065), // Rule ID 407 // |
| 2226 | /* 5019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2227 | /* 5022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2228 | /* 5026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2229 | /* 5030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2230 | /* 5034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2231 | /* 5038 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 2232 | /* 5042 */ // MIs[1] Operand 1 |
| 2233 | /* 5042 */ // No operand predicates |
| 2234 | /* 5042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2235 | /* 5044 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2236 | /* 5044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12), |
| 2237 | /* 5047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2238 | /* 5049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2239 | /* 5051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2240 | /* 5054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2241 | /* 5057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2242 | /* 5063 */ GIR_RootConstrainSelectedInstOperands, |
| 2243 | /* 5064 */ // GIR_Coverage, 407, |
| 2244 | /* 5064 */ GIR_EraseRootFromParent_Done, |
| 2245 | /* 5065 */ // Label 144: @5065 |
| 2246 | /* 5065 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(5141), // Rule ID 170 // |
| 2247 | /* 5070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2248 | /* 5073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2249 | /* 5077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2250 | /* 5081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2251 | /* 5085 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2252 | /* 5089 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2253 | /* 5093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2254 | /* 5098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2255 | /* 5103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2256 | /* 5107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2257 | /* 5109 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2258 | /* 5109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2259 | /* 5112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2260 | /* 5114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2261 | /* 5118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2262 | /* 5122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2263 | /* 5124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2264 | /* 5127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2265 | /* 5133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2266 | /* 5139 */ GIR_RootConstrainSelectedInstOperands, |
| 2267 | /* 5140 */ // GIR_Coverage, 170, |
| 2268 | /* 5140 */ GIR_EraseRootFromParent_Done, |
| 2269 | /* 5141 */ // Label 145: @5141 |
| 2270 | /* 5141 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(5217), // Rule ID 171 // |
| 2271 | /* 5146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), |
| 2272 | /* 5149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2273 | /* 5153 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2274 | /* 5157 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2275 | /* 5161 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2276 | /* 5165 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2277 | /* 5169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2278 | /* 5174 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2279 | /* 5179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2280 | /* 5183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2281 | /* 5185 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2282 | /* 5185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2283 | /* 5188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2284 | /* 5190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2285 | /* 5194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2286 | /* 5198 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2287 | /* 5200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2288 | /* 5203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2289 | /* 5209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2290 | /* 5215 */ GIR_RootConstrainSelectedInstOperands, |
| 2291 | /* 5216 */ // GIR_Coverage, 171, |
| 2292 | /* 5216 */ GIR_EraseRootFromParent_Done, |
| 2293 | /* 5217 */ // Label 146: @5217 |
| 2294 | /* 5217 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(5287), // Rule ID 502 // |
| 2295 | /* 5222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 2296 | /* 5225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2297 | /* 5229 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2298 | /* 5233 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2299 | /* 5237 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2300 | /* 5241 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2301 | /* 5245 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2302 | /* 5250 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2303 | /* 5255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2304 | /* 5259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2305 | /* 5261 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2306 | /* 5261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2307 | /* 5264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2308 | /* 5266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2309 | /* 5270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2310 | /* 5274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2311 | /* 5276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2312 | /* 5279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2313 | /* 5285 */ GIR_RootConstrainSelectedInstOperands, |
| 2314 | /* 5286 */ // GIR_Coverage, 502, |
| 2315 | /* 5286 */ GIR_EraseRootFromParent_Done, |
| 2316 | /* 5287 */ // Label 147: @5287 |
| 2317 | /* 5287 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(5358), // Rule ID 6252 // |
| 2318 | /* 5292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2319 | /* 5295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2320 | /* 5299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2321 | /* 5303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2322 | /* 5307 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2323 | /* 5311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2324 | /* 5316 */ // MIs[1] Operand 2 |
| 2325 | /* 5316 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2326 | /* 5327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2327 | /* 5331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2328 | /* 5333 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2329 | /* 5333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2330 | /* 5336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2331 | /* 5338 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2332 | /* 5340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2333 | /* 5344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2334 | /* 5347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2335 | /* 5350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2336 | /* 5356 */ GIR_RootConstrainSelectedInstOperands, |
| 2337 | /* 5357 */ // GIR_Coverage, 6252, |
| 2338 | /* 5357 */ GIR_EraseRootFromParent_Done, |
| 2339 | /* 5358 */ // Label 148: @5358 |
| 2340 | /* 5358 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(5429), // Rule ID 6253 // |
| 2341 | /* 5363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2342 | /* 5366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2343 | /* 5370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2344 | /* 5374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2345 | /* 5378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2346 | /* 5382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2347 | /* 5387 */ // MIs[1] Operand 2 |
| 2348 | /* 5387 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2349 | /* 5398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2350 | /* 5402 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2351 | /* 5404 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2352 | /* 5404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2353 | /* 5407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2354 | /* 5409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2355 | /* 5411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2356 | /* 5415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2357 | /* 5418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2358 | /* 5421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2359 | /* 5427 */ GIR_RootConstrainSelectedInstOperands, |
| 2360 | /* 5428 */ // GIR_Coverage, 6253, |
| 2361 | /* 5428 */ GIR_EraseRootFromParent_Done, |
| 2362 | /* 5429 */ // Label 149: @5429 |
| 2363 | /* 5429 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(5500), // Rule ID 6287 // |
| 2364 | /* 5434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2365 | /* 5437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2366 | /* 5441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2367 | /* 5445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2368 | /* 5449 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2369 | /* 5453 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2370 | /* 5458 */ // MIs[1] Operand 2 |
| 2371 | /* 5458 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2372 | /* 5469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2373 | /* 5473 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2374 | /* 5475 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2375 | /* 5475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2376 | /* 5478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2377 | /* 5480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2378 | /* 5482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2379 | /* 5486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2380 | /* 5489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2381 | /* 5492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2382 | /* 5498 */ GIR_RootConstrainSelectedInstOperands, |
| 2383 | /* 5499 */ // GIR_Coverage, 6287, |
| 2384 | /* 5499 */ GIR_EraseRootFromParent_Done, |
| 2385 | /* 5500 */ // Label 150: @5500 |
| 2386 | /* 5500 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(5571), // Rule ID 6288 // |
| 2387 | /* 5505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2388 | /* 5508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2389 | /* 5512 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2390 | /* 5516 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2391 | /* 5520 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2392 | /* 5524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2393 | /* 5529 */ // MIs[1] Operand 2 |
| 2394 | /* 5529 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2395 | /* 5540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2396 | /* 5544 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2397 | /* 5546 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2398 | /* 5546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2399 | /* 5549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2400 | /* 5551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2401 | /* 5553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2402 | /* 5557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2403 | /* 5560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2404 | /* 5563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2405 | /* 5569 */ GIR_RootConstrainSelectedInstOperands, |
| 2406 | /* 5570 */ // GIR_Coverage, 6288, |
| 2407 | /* 5570 */ GIR_EraseRootFromParent_Done, |
| 2408 | /* 5571 */ // Label 151: @5571 |
| 2409 | /* 5571 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(5641), // Rule ID 179 // |
| 2410 | /* 5576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2411 | /* 5579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2412 | /* 5583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2413 | /* 5587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2414 | /* 5591 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2415 | /* 5595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2416 | /* 5599 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2417 | /* 5604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2418 | /* 5609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2419 | /* 5613 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2420 | /* 5615 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2421 | /* 5615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2422 | /* 5618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2423 | /* 5620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2424 | /* 5624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2425 | /* 5628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2426 | /* 5630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2427 | /* 5633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2428 | /* 5639 */ GIR_RootConstrainSelectedInstOperands, |
| 2429 | /* 5640 */ // GIR_Coverage, 179, |
| 2430 | /* 5640 */ GIR_EraseRootFromParent_Done, |
| 2431 | /* 5641 */ // Label 152: @5641 |
| 2432 | /* 5641 */ GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(5711), // Rule ID 508 // |
| 2433 | /* 5646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 2434 | /* 5649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2435 | /* 5653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2436 | /* 5657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2437 | /* 5661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2438 | /* 5665 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2439 | /* 5669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2440 | /* 5674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2441 | /* 5679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2442 | /* 5683 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2443 | /* 5685 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2444 | /* 5685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2445 | /* 5688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2446 | /* 5690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2447 | /* 5694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2448 | /* 5698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2449 | /* 5700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2450 | /* 5703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2451 | /* 5709 */ GIR_RootConstrainSelectedInstOperands, |
| 2452 | /* 5710 */ // GIR_Coverage, 508, |
| 2453 | /* 5710 */ GIR_EraseRootFromParent_Done, |
| 2454 | /* 5711 */ // Label 153: @5711 |
| 2455 | /* 5711 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(5774), // Rule ID 3429 // |
| 2456 | /* 5716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2457 | /* 5719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2458 | /* 5723 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2459 | /* 5727 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2460 | /* 5731 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2461 | /* 5735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2462 | /* 5740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2463 | /* 5744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2464 | /* 5746 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2465 | /* 5746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2466 | /* 5749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2467 | /* 5751 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2468 | /* 5753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2469 | /* 5757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2470 | /* 5760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2471 | /* 5766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2472 | /* 5772 */ GIR_RootConstrainSelectedInstOperands, |
| 2473 | /* 5773 */ // GIR_Coverage, 3429, |
| 2474 | /* 5773 */ GIR_EraseRootFromParent_Done, |
| 2475 | /* 5774 */ // Label 154: @5774 |
| 2476 | /* 5774 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(5837), // Rule ID 3457 // |
| 2477 | /* 5779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2478 | /* 5782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2479 | /* 5786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2480 | /* 5790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2481 | /* 5794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2482 | /* 5798 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2483 | /* 5803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2484 | /* 5807 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2485 | /* 5809 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2486 | /* 5809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2487 | /* 5812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2488 | /* 5814 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2489 | /* 5816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2490 | /* 5820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2491 | /* 5823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2492 | /* 5829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2493 | /* 5835 */ GIR_RootConstrainSelectedInstOperands, |
| 2494 | /* 5836 */ // GIR_Coverage, 3457, |
| 2495 | /* 5836 */ GIR_EraseRootFromParent_Done, |
| 2496 | /* 5837 */ // Label 155: @5837 |
| 2497 | /* 5837 */ GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(5900), // Rule ID 3467 // |
| 2498 | /* 5842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2499 | /* 5845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2500 | /* 5849 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2501 | /* 5853 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2502 | /* 5857 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2503 | /* 5861 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2504 | /* 5866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2505 | /* 5870 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2506 | /* 5872 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2507 | /* 5872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2508 | /* 5875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2509 | /* 5877 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2510 | /* 5879 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2511 | /* 5883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2512 | /* 5886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2513 | /* 5892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2514 | /* 5898 */ GIR_RootConstrainSelectedInstOperands, |
| 2515 | /* 5899 */ // GIR_Coverage, 3467, |
| 2516 | /* 5899 */ GIR_EraseRootFromParent_Done, |
| 2517 | /* 5900 */ // Label 156: @5900 |
| 2518 | /* 5900 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(5976), // Rule ID 5957 // |
| 2519 | /* 5905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2520 | /* 5908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2521 | /* 5912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2522 | /* 5916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2523 | /* 5920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2524 | /* 5924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2525 | /* 5928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2526 | /* 5932 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2527 | /* 5937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2528 | /* 5942 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2529 | /* 5944 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2530 | /* 5944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2531 | /* 5947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2532 | /* 5949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2533 | /* 5953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2534 | /* 5957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2535 | /* 5959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2536 | /* 5962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2537 | /* 5968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2538 | /* 5974 */ GIR_RootConstrainSelectedInstOperands, |
| 2539 | /* 5975 */ // GIR_Coverage, 5957, |
| 2540 | /* 5975 */ GIR_EraseRootFromParent_Done, |
| 2541 | /* 5976 */ // Label 157: @5976 |
| 2542 | /* 5976 */ GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(6052), // Rule ID 5958 // |
| 2543 | /* 5981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), |
| 2544 | /* 5984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2545 | /* 5988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2546 | /* 5992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2547 | /* 5996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2548 | /* 6000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2549 | /* 6004 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2550 | /* 6008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2551 | /* 6013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2552 | /* 6018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2553 | /* 6020 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2554 | /* 6020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2555 | /* 6023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2556 | /* 6025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2557 | /* 6029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2558 | /* 6033 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2559 | /* 6035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2560 | /* 6038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2561 | /* 6044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2562 | /* 6050 */ GIR_RootConstrainSelectedInstOperands, |
| 2563 | /* 6051 */ // GIR_Coverage, 5958, |
| 2564 | /* 6051 */ GIR_EraseRootFromParent_Done, |
| 2565 | /* 6052 */ // Label 158: @6052 |
| 2566 | /* 6052 */ GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(6122), // Rule ID 5995 // |
| 2567 | /* 6057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 2568 | /* 6060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2569 | /* 6064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2570 | /* 6068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2571 | /* 6072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2572 | /* 6076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2573 | /* 6080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2574 | /* 6084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2575 | /* 6089 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2576 | /* 6094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2577 | /* 6096 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2578 | /* 6096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2579 | /* 6099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2580 | /* 6101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2581 | /* 6105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2582 | /* 6109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2583 | /* 6111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2584 | /* 6114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2585 | /* 6120 */ GIR_RootConstrainSelectedInstOperands, |
| 2586 | /* 6121 */ // GIR_Coverage, 5995, |
| 2587 | /* 6121 */ GIR_EraseRootFromParent_Done, |
| 2588 | /* 6122 */ // Label 159: @6122 |
| 2589 | /* 6122 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(6193), // Rule ID 2189 // |
| 2590 | /* 6127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2591 | /* 6130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2592 | /* 6134 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2593 | /* 6138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2594 | /* 6142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2595 | /* 6146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2596 | /* 6150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2597 | /* 6155 */ // MIs[1] Operand 2 |
| 2598 | /* 6155 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2599 | /* 6166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2600 | /* 6168 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2601 | /* 6168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2602 | /* 6171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2603 | /* 6173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2604 | /* 6175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2605 | /* 6179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2606 | /* 6182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2607 | /* 6185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2608 | /* 6191 */ GIR_RootConstrainSelectedInstOperands, |
| 2609 | /* 6192 */ // GIR_Coverage, 2189, |
| 2610 | /* 6192 */ GIR_EraseRootFromParent_Done, |
| 2611 | /* 6193 */ // Label 160: @6193 |
| 2612 | /* 6193 */ GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(6264), // Rule ID 2190 // |
| 2613 | /* 6198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2614 | /* 6201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2615 | /* 6205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2616 | /* 6209 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2617 | /* 6213 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2618 | /* 6217 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2619 | /* 6221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2620 | /* 6226 */ // MIs[1] Operand 2 |
| 2621 | /* 6226 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2622 | /* 6237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2623 | /* 6239 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2624 | /* 6239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2625 | /* 6242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2626 | /* 6244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2627 | /* 6246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2628 | /* 6250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2629 | /* 6253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2630 | /* 6256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2631 | /* 6262 */ GIR_RootConstrainSelectedInstOperands, |
| 2632 | /* 6263 */ // GIR_Coverage, 2190, |
| 2633 | /* 6263 */ GIR_EraseRootFromParent_Done, |
| 2634 | /* 6264 */ // Label 161: @6264 |
| 2635 | /* 6264 */ GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(6335), // Rule ID 2428 // |
| 2636 | /* 6269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2637 | /* 6272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2638 | /* 6276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2639 | /* 6280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2640 | /* 6284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2641 | /* 6288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2642 | /* 6292 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2643 | /* 6297 */ // MIs[1] Operand 2 |
| 2644 | /* 6297 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2645 | /* 6308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2646 | /* 6310 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2647 | /* 6310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2648 | /* 6313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2649 | /* 6315 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2650 | /* 6317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2651 | /* 6321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2652 | /* 6324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2653 | /* 6327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2654 | /* 6333 */ GIR_RootConstrainSelectedInstOperands, |
| 2655 | /* 6334 */ // GIR_Coverage, 2428, |
| 2656 | /* 6334 */ GIR_EraseRootFromParent_Done, |
| 2657 | /* 6335 */ // Label 162: @6335 |
| 2658 | /* 6335 */ GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(6406), // Rule ID 2429 // |
| 2659 | /* 6340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2660 | /* 6343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2661 | /* 6347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2662 | /* 6351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2663 | /* 6355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2664 | /* 6359 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2665 | /* 6363 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2666 | /* 6368 */ // MIs[1] Operand 2 |
| 2667 | /* 6368 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2668 | /* 6379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2669 | /* 6381 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2670 | /* 6381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2671 | /* 6384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2672 | /* 6386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2673 | /* 6388 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2674 | /* 6392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2675 | /* 6395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2676 | /* 6398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2677 | /* 6404 */ GIR_RootConstrainSelectedInstOperands, |
| 2678 | /* 6405 */ // GIR_Coverage, 2429, |
| 2679 | /* 6405 */ GIR_EraseRootFromParent_Done, |
| 2680 | /* 6406 */ // Label 163: @6406 |
| 2681 | /* 6406 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(6476), // Rule ID 5959 // |
| 2682 | /* 6411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2683 | /* 6414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2684 | /* 6418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2685 | /* 6422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2686 | /* 6426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2687 | /* 6430 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2688 | /* 6434 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2689 | /* 6438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2690 | /* 6443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2691 | /* 6448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2692 | /* 6450 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2693 | /* 6450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2694 | /* 6453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2695 | /* 6455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2696 | /* 6459 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2697 | /* 6463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2698 | /* 6465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2699 | /* 6468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2700 | /* 6474 */ GIR_RootConstrainSelectedInstOperands, |
| 2701 | /* 6475 */ // GIR_Coverage, 5959, |
| 2702 | /* 6475 */ GIR_EraseRootFromParent_Done, |
| 2703 | /* 6476 */ // Label 164: @6476 |
| 2704 | /* 6476 */ GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(6546), // Rule ID 5996 // |
| 2705 | /* 6481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 2706 | /* 6484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2707 | /* 6488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2708 | /* 6492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2709 | /* 6496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2710 | /* 6500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2711 | /* 6504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2712 | /* 6508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2713 | /* 6513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2714 | /* 6518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2715 | /* 6520 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2716 | /* 6520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2717 | /* 6523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2718 | /* 6525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2719 | /* 6529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2720 | /* 6533 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2721 | /* 6535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2722 | /* 6538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2723 | /* 6544 */ GIR_RootConstrainSelectedInstOperands, |
| 2724 | /* 6545 */ // GIR_Coverage, 5996, |
| 2725 | /* 6545 */ GIR_EraseRootFromParent_Done, |
| 2726 | /* 6546 */ // Label 165: @6546 |
| 2727 | /* 6546 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(6609), // Rule ID 6533 // |
| 2728 | /* 6551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2729 | /* 6554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2730 | /* 6558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2731 | /* 6562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2732 | /* 6566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2733 | /* 6570 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2734 | /* 6574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2735 | /* 6579 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2736 | /* 6581 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2737 | /* 6581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2738 | /* 6584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2739 | /* 6586 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2740 | /* 6588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2741 | /* 6592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2742 | /* 6595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2743 | /* 6601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2744 | /* 6607 */ GIR_RootConstrainSelectedInstOperands, |
| 2745 | /* 6608 */ // GIR_Coverage, 6533, |
| 2746 | /* 6608 */ GIR_EraseRootFromParent_Done, |
| 2747 | /* 6609 */ // Label 166: @6609 |
| 2748 | /* 6609 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(6672), // Rule ID 6547 // |
| 2749 | /* 6614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2750 | /* 6617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2751 | /* 6621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2752 | /* 6625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2753 | /* 6629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2754 | /* 6633 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2755 | /* 6637 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2756 | /* 6642 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2757 | /* 6644 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2758 | /* 6644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2759 | /* 6647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2760 | /* 6649 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2761 | /* 6651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2762 | /* 6655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2763 | /* 6658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2764 | /* 6664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2765 | /* 6670 */ GIR_RootConstrainSelectedInstOperands, |
| 2766 | /* 6671 */ // GIR_Coverage, 6547, |
| 2767 | /* 6671 */ GIR_EraseRootFromParent_Done, |
| 2768 | /* 6672 */ // Label 167: @6672 |
| 2769 | /* 6672 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(6735), // Rule ID 6552 // |
| 2770 | /* 6677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2771 | /* 6680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2772 | /* 6684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2773 | /* 6688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2774 | /* 6692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2775 | /* 6696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2776 | /* 6700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2777 | /* 6705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2778 | /* 6707 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2779 | /* 6707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2780 | /* 6710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2781 | /* 6712 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2782 | /* 6714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2783 | /* 6718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2784 | /* 6721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2785 | /* 6727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2786 | /* 6733 */ GIR_RootConstrainSelectedInstOperands, |
| 2787 | /* 6734 */ // GIR_Coverage, 6552, |
| 2788 | /* 6734 */ GIR_EraseRootFromParent_Done, |
| 2789 | /* 6735 */ // Label 168: @6735 |
| 2790 | /* 6735 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(6781), // Rule ID 72 // |
| 2791 | /* 6740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 2792 | /* 6743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2793 | /* 6747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2794 | /* 6751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2795 | /* 6755 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 2796 | /* 6755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr), |
| 2797 | /* 6758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2798 | /* 6760 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2799 | /* 6762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2800 | /* 6764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2801 | /* 6767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2802 | /* 6773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2803 | /* 6779 */ GIR_RootConstrainSelectedInstOperands, |
| 2804 | /* 6780 */ // GIR_Coverage, 72, |
| 2805 | /* 6780 */ GIR_EraseRootFromParent_Done, |
| 2806 | /* 6781 */ // Label 169: @6781 |
| 2807 | /* 6781 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(6827), // Rule ID 304 // |
| 2808 | /* 6786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 2809 | /* 6789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2810 | /* 6793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2811 | /* 6797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2812 | /* 6801 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 2813 | /* 6801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr), |
| 2814 | /* 6804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2815 | /* 6806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2816 | /* 6812 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2817 | /* 6814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2818 | /* 6816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2819 | /* 6819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2820 | /* 6825 */ GIR_RootConstrainSelectedInstOperands, |
| 2821 | /* 6826 */ // GIR_Coverage, 304, |
| 2822 | /* 6826 */ GIR_EraseRootFromParent_Done, |
| 2823 | /* 6827 */ // Label 170: @6827 |
| 2824 | /* 6827 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(6873), // Rule ID 408 // |
| 2825 | /* 6832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2826 | /* 6835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2827 | /* 6839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2828 | /* 6843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2829 | /* 6847 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2830 | /* 6847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2831 | /* 6850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2832 | /* 6852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2833 | /* 6854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2834 | /* 6856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2835 | /* 6859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2836 | /* 6865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2837 | /* 6871 */ GIR_RootConstrainSelectedInstOperands, |
| 2838 | /* 6872 */ // GIR_Coverage, 408, |
| 2839 | /* 6872 */ GIR_EraseRootFromParent_Done, |
| 2840 | /* 6873 */ // Label 171: @6873 |
| 2841 | /* 6873 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(6919), // Rule ID 5977 // |
| 2842 | /* 6878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2843 | /* 6881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2844 | /* 6885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2845 | /* 6889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2846 | /* 6893 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2847 | /* 6893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2848 | /* 6896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2849 | /* 6898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2850 | /* 6900 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2851 | /* 6902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2852 | /* 6905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2853 | /* 6911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2854 | /* 6917 */ GIR_RootConstrainSelectedInstOperands, |
| 2855 | /* 6918 */ // GIR_Coverage, 5977, |
| 2856 | /* 6918 */ GIR_EraseRootFromParent_Done, |
| 2857 | /* 6919 */ // Label 172: @6919 |
| 2858 | /* 6919 */ GIM_Reject, |
| 2859 | /* 6920 */ // Label 103: @6920 |
| 2860 | /* 6920 */ GIM_Reject, |
| 2861 | /* 6921 */ // Label 94: @6921 |
| 2862 | /* 6921 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(6967), // Rule ID 881 // |
| 2863 | /* 6926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2864 | /* 6929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2865 | /* 6932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 2866 | /* 6935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2867 | /* 6939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2868 | /* 6943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2869 | /* 6947 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 2870 | /* 6947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64), |
| 2871 | /* 6950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2872 | /* 6952 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2873 | /* 6954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2874 | /* 6956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2875 | /* 6959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2876 | /* 6965 */ GIR_RootConstrainSelectedInstOperands, |
| 2877 | /* 6966 */ // GIR_Coverage, 881, |
| 2878 | /* 6966 */ GIR_EraseRootFromParent_Done, |
| 2879 | /* 6967 */ // Label 173: @6967 |
| 2880 | /* 6967 */ GIM_Reject, |
| 2881 | /* 6968 */ // Label 95: @6968 |
| 2882 | /* 6968 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(7416), |
| 2883 | /* 6973 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2884 | /* 6976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2885 | /* 6979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2886 | /* 6983 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(7049), // Rule ID 6182 // |
| 2887 | /* 6988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2888 | /* 6991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2889 | /* 6995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 2890 | /* 6999 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2891 | /* 7003 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2892 | /* 7007 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2893 | /* 7012 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2894 | /* 7017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2895 | /* 7021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2896 | /* 7023 */ // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2897 | /* 7023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32), |
| 2898 | /* 7026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2899 | /* 7028 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2900 | /* 7030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2901 | /* 7034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2902 | /* 7038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2903 | /* 7041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2904 | /* 7047 */ GIR_RootConstrainSelectedInstOperands, |
| 2905 | /* 7048 */ // GIR_Coverage, 6182, |
| 2906 | /* 7048 */ GIR_EraseRootFromParent_Done, |
| 2907 | /* 7049 */ // Label 175: @7049 |
| 2908 | /* 7049 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(7115), // Rule ID 6188 // |
| 2909 | /* 7054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2910 | /* 7057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2911 | /* 7061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 2912 | /* 7065 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2913 | /* 7069 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2914 | /* 7073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2915 | /* 7078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2916 | /* 7083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2917 | /* 7087 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2918 | /* 7089 */ // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2919 | /* 7089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32), |
| 2920 | /* 7092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2921 | /* 7094 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2922 | /* 7096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2923 | /* 7100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2924 | /* 7104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2925 | /* 7107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2926 | /* 7113 */ GIR_RootConstrainSelectedInstOperands, |
| 2927 | /* 7114 */ // GIR_Coverage, 6188, |
| 2928 | /* 7114 */ GIR_EraseRootFromParent_Done, |
| 2929 | /* 7115 */ // Label 176: @7115 |
| 2930 | /* 7115 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(7181), // Rule ID 6070 // |
| 2931 | /* 7120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2932 | /* 7123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2933 | /* 7127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2934 | /* 7131 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2935 | /* 7135 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2936 | /* 7139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2937 | /* 7144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2938 | /* 7149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2939 | /* 7153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2940 | /* 7155 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2941 | /* 7155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 2942 | /* 7158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2943 | /* 7160 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2944 | /* 7162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2945 | /* 7166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2946 | /* 7170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2947 | /* 7173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2948 | /* 7179 */ GIR_RootConstrainSelectedInstOperands, |
| 2949 | /* 7180 */ // GIR_Coverage, 6070, |
| 2950 | /* 7180 */ GIR_EraseRootFromParent_Done, |
| 2951 | /* 7181 */ // Label 177: @7181 |
| 2952 | /* 7181 */ GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(7247), // Rule ID 1342 // |
| 2953 | /* 7186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2954 | /* 7189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2955 | /* 7193 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2956 | /* 7197 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 2957 | /* 7201 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2958 | /* 7205 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2959 | /* 7209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2960 | /* 7214 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2961 | /* 7219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2962 | /* 7221 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2963 | /* 7221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32), |
| 2964 | /* 7224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2965 | /* 7226 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2966 | /* 7228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2967 | /* 7232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2968 | /* 7236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2969 | /* 7239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2970 | /* 7245 */ GIR_RootConstrainSelectedInstOperands, |
| 2971 | /* 7246 */ // GIR_Coverage, 1342, |
| 2972 | /* 7246 */ GIR_EraseRootFromParent_Done, |
| 2973 | /* 7247 */ // Label 178: @7247 |
| 2974 | /* 7247 */ GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(7313), // Rule ID 1348 // |
| 2975 | /* 7252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2976 | /* 7255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2977 | /* 7259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2978 | /* 7263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 2979 | /* 7267 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2980 | /* 7271 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2981 | /* 7275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2982 | /* 7280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2983 | /* 7285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2984 | /* 7287 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2985 | /* 7287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32), |
| 2986 | /* 7290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2987 | /* 7292 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2988 | /* 7294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2989 | /* 7298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2990 | /* 7302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2991 | /* 7305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2992 | /* 7311 */ GIR_RootConstrainSelectedInstOperands, |
| 2993 | /* 7312 */ // GIR_Coverage, 1348, |
| 2994 | /* 7312 */ GIR_EraseRootFromParent_Done, |
| 2995 | /* 7313 */ // Label 179: @7313 |
| 2996 | /* 7313 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(7379), // Rule ID 1008 // |
| 2997 | /* 7318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2998 | /* 7321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2999 | /* 7325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3000 | /* 7329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3001 | /* 7333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3002 | /* 7337 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3003 | /* 7341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3004 | /* 7346 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3005 | /* 7351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3006 | /* 7353 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3007 | /* 7353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 3008 | /* 7356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3009 | /* 7358 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3010 | /* 7360 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3011 | /* 7364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3012 | /* 7368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3013 | /* 7371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3014 | /* 7377 */ GIR_RootConstrainSelectedInstOperands, |
| 3015 | /* 7378 */ // GIR_Coverage, 1008, |
| 3016 | /* 7378 */ GIR_EraseRootFromParent_Done, |
| 3017 | /* 7379 */ // Label 180: @7379 |
| 3018 | /* 7379 */ GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(7415), // Rule ID 877 // |
| 3019 | /* 7384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3020 | /* 7387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3021 | /* 7391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3022 | /* 7395 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3023 | /* 7395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32), |
| 3024 | /* 7398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3025 | /* 7400 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3026 | /* 7402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3027 | /* 7404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3028 | /* 7407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3029 | /* 7413 */ GIR_RootConstrainSelectedInstOperands, |
| 3030 | /* 7414 */ // GIR_Coverage, 877, |
| 3031 | /* 7414 */ GIR_EraseRootFromParent_Done, |
| 3032 | /* 7415 */ // Label 181: @7415 |
| 3033 | /* 7415 */ GIM_Reject, |
| 3034 | /* 7416 */ // Label 174: @7416 |
| 3035 | /* 7416 */ GIM_Reject, |
| 3036 | /* 7417 */ // Label 96: @7417 |
| 3037 | /* 7417 */ GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(8439), |
| 3038 | /* 7422 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3039 | /* 7425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 3040 | /* 7428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3041 | /* 7432 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(7500), // Rule ID 901 // |
| 3042 | /* 7437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3043 | /* 7440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3044 | /* 7444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3045 | /* 7448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3046 | /* 7452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3047 | /* 7457 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3048 | /* 7461 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3049 | /* 7465 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3050 | /* 7469 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3051 | /* 7474 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3052 | /* 7476 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3053 | /* 7476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 3054 | /* 7479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3055 | /* 7481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3056 | /* 7485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3057 | /* 7489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3058 | /* 7492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3059 | /* 7498 */ GIR_RootConstrainSelectedInstOperands, |
| 3060 | /* 7499 */ // GIR_Coverage, 901, |
| 3061 | /* 7499 */ GIR_EraseRootFromParent_Done, |
| 3062 | /* 7500 */ // Label 183: @7500 |
| 3063 | /* 7500 */ GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(7568), // Rule ID 900 // |
| 3064 | /* 7505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3065 | /* 7508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3066 | /* 7512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3067 | /* 7516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3068 | /* 7520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3069 | /* 7525 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3070 | /* 7529 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3071 | /* 7533 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3072 | /* 7537 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3073 | /* 7542 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3074 | /* 7544 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3075 | /* 7544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 3076 | /* 7547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3077 | /* 7549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3078 | /* 7553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3079 | /* 7557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3080 | /* 7560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3081 | /* 7566 */ GIR_RootConstrainSelectedInstOperands, |
| 3082 | /* 7567 */ // GIR_Coverage, 900, |
| 3083 | /* 7567 */ GIR_EraseRootFromParent_Done, |
| 3084 | /* 7568 */ // Label 184: @7568 |
| 3085 | /* 7568 */ GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(7636), // Rule ID 889 // |
| 3086 | /* 7573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3087 | /* 7576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3088 | /* 7580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3089 | /* 7584 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3090 | /* 7588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3091 | /* 7593 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3092 | /* 7597 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3093 | /* 7601 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3094 | /* 7605 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3095 | /* 7610 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3096 | /* 7612 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3097 | /* 7612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64), |
| 3098 | /* 7615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3099 | /* 7617 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3100 | /* 7621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3101 | /* 7625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3102 | /* 7628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3103 | /* 7634 */ GIR_RootConstrainSelectedInstOperands, |
| 3104 | /* 7635 */ // GIR_Coverage, 889, |
| 3105 | /* 7635 */ GIR_EraseRootFromParent_Done, |
| 3106 | /* 7636 */ // Label 185: @7636 |
| 3107 | /* 7636 */ GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(7714), // Rule ID 6194 // |
| 3108 | /* 7641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3109 | /* 7644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3110 | /* 7648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3111 | /* 7652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3112 | /* 7656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3113 | /* 7660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3114 | /* 7664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3115 | /* 7668 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3116 | /* 7672 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3117 | /* 7677 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3118 | /* 7682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3119 | /* 7686 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3120 | /* 7688 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3121 | /* 7688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64), |
| 3122 | /* 7691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3123 | /* 7693 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3124 | /* 7695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3125 | /* 7699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3126 | /* 7703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3127 | /* 7706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3128 | /* 7712 */ GIR_RootConstrainSelectedInstOperands, |
| 3129 | /* 7713 */ // GIR_Coverage, 6194, |
| 3130 | /* 7713 */ GIR_EraseRootFromParent_Done, |
| 3131 | /* 7714 */ // Label 186: @7714 |
| 3132 | /* 7714 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(7792), // Rule ID 6197 // |
| 3133 | /* 7719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3134 | /* 7722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3135 | /* 7726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3136 | /* 7730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3137 | /* 7734 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3138 | /* 7738 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3139 | /* 7742 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3140 | /* 7746 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3141 | /* 7750 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3142 | /* 7755 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3143 | /* 7760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3144 | /* 7764 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3145 | /* 7766 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3146 | /* 7766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64), |
| 3147 | /* 7769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3148 | /* 7771 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3149 | /* 7773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3150 | /* 7777 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3151 | /* 7781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3152 | /* 7784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3153 | /* 7790 */ GIR_RootConstrainSelectedInstOperands, |
| 3154 | /* 7791 */ // GIR_Coverage, 6197, |
| 3155 | /* 7791 */ GIR_EraseRootFromParent_Done, |
| 3156 | /* 7792 */ // Label 187: @7792 |
| 3157 | /* 7792 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(7860), // Rule ID 899 // |
| 3158 | /* 7797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3159 | /* 7800 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3160 | /* 7804 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3161 | /* 7808 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3162 | /* 7812 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3163 | /* 7817 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3164 | /* 7821 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3165 | /* 7825 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3166 | /* 7829 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3167 | /* 7834 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3168 | /* 7836 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3169 | /* 7836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 3170 | /* 7839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3171 | /* 7841 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3172 | /* 7845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3173 | /* 7849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3174 | /* 7852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3175 | /* 7858 */ GIR_RootConstrainSelectedInstOperands, |
| 3176 | /* 7859 */ // GIR_Coverage, 899, |
| 3177 | /* 7859 */ GIR_EraseRootFromParent_Done, |
| 3178 | /* 7860 */ // Label 188: @7860 |
| 3179 | /* 7860 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(7928), // Rule ID 898 // |
| 3180 | /* 7865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3181 | /* 7868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3182 | /* 7872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3183 | /* 7876 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3184 | /* 7880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3185 | /* 7885 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3186 | /* 7889 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3187 | /* 7893 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3188 | /* 7897 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3189 | /* 7902 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3190 | /* 7904 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3191 | /* 7904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 3192 | /* 7907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3193 | /* 7909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3194 | /* 7913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3195 | /* 7917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3196 | /* 7920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3197 | /* 7926 */ GIR_RootConstrainSelectedInstOperands, |
| 3198 | /* 7927 */ // GIR_Coverage, 898, |
| 3199 | /* 7927 */ GIR_EraseRootFromParent_Done, |
| 3200 | /* 7928 */ // Label 189: @7928 |
| 3201 | /* 7928 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(8006), // Rule ID 1354 // |
| 3202 | /* 7933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3203 | /* 7936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3204 | /* 7940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3205 | /* 7944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3206 | /* 7948 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3207 | /* 7952 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3208 | /* 7956 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3209 | /* 7960 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3210 | /* 7964 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3211 | /* 7968 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3212 | /* 7973 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3213 | /* 7978 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3214 | /* 7980 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3215 | /* 7980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64), |
| 3216 | /* 7983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3217 | /* 7985 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3218 | /* 7987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3219 | /* 7991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3220 | /* 7995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3221 | /* 7998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3222 | /* 8004 */ GIR_RootConstrainSelectedInstOperands, |
| 3223 | /* 8005 */ // GIR_Coverage, 1354, |
| 3224 | /* 8005 */ GIR_EraseRootFromParent_Done, |
| 3225 | /* 8006 */ // Label 190: @8006 |
| 3226 | /* 8006 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(8084), // Rule ID 1357 // |
| 3227 | /* 8011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3228 | /* 8014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3229 | /* 8018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3230 | /* 8022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3231 | /* 8026 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3232 | /* 8030 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3233 | /* 8034 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3234 | /* 8038 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3235 | /* 8042 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3236 | /* 8046 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3237 | /* 8051 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3238 | /* 8056 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3239 | /* 8058 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3240 | /* 8058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64), |
| 3241 | /* 8061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3242 | /* 8063 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3243 | /* 8065 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3244 | /* 8069 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3245 | /* 8073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3246 | /* 8076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3247 | /* 8082 */ GIR_RootConstrainSelectedInstOperands, |
| 3248 | /* 8083 */ // GIR_Coverage, 1357, |
| 3249 | /* 8083 */ GIR_EraseRootFromParent_Done, |
| 3250 | /* 8084 */ // Label 191: @8084 |
| 3251 | /* 8084 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(8137), // Rule ID 6049 // |
| 3252 | /* 8089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3253 | /* 8092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3254 | /* 8096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3255 | /* 8100 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3256 | /* 8104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3257 | /* 8109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3258 | /* 8113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3259 | /* 8115 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3260 | /* 8115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3261 | /* 8118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3262 | /* 8120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3263 | /* 8122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3264 | /* 8126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3265 | /* 8129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3266 | /* 8135 */ GIR_RootConstrainSelectedInstOperands, |
| 3267 | /* 8136 */ // GIR_Coverage, 6049, |
| 3268 | /* 8136 */ GIR_EraseRootFromParent_Done, |
| 3269 | /* 8137 */ // Label 192: @8137 |
| 3270 | /* 8137 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(8190), // Rule ID 6043 // |
| 3271 | /* 8142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3272 | /* 8145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3273 | /* 8149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3274 | /* 8153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3275 | /* 8157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3276 | /* 8162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3277 | /* 8166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3278 | /* 8168 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3279 | /* 8168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 3280 | /* 8171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3281 | /* 8173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3282 | /* 8175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3283 | /* 8179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3284 | /* 8182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3285 | /* 8188 */ GIR_RootConstrainSelectedInstOperands, |
| 3286 | /* 8189 */ // GIR_Coverage, 6043, |
| 3287 | /* 8189 */ GIR_EraseRootFromParent_Done, |
| 3288 | /* 8190 */ // Label 193: @8190 |
| 3289 | /* 8190 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(8243), // Rule ID 6048 // |
| 3290 | /* 8195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3291 | /* 8198 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3292 | /* 8202 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3293 | /* 8206 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3294 | /* 8210 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3295 | /* 8215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3296 | /* 8219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3297 | /* 8221 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3298 | /* 8221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3299 | /* 8224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3300 | /* 8226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3301 | /* 8228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3302 | /* 8232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3303 | /* 8235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3304 | /* 8241 */ GIR_RootConstrainSelectedInstOperands, |
| 3305 | /* 8242 */ // GIR_Coverage, 6048, |
| 3306 | /* 8242 */ GIR_EraseRootFromParent_Done, |
| 3307 | /* 8243 */ // Label 194: @8243 |
| 3308 | /* 8243 */ GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(8296), // Rule ID 910 // |
| 3309 | /* 8248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3310 | /* 8251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3311 | /* 8255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3312 | /* 8259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3313 | /* 8263 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3314 | /* 8267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3315 | /* 8272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3316 | /* 8274 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3317 | /* 8274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3318 | /* 8277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3319 | /* 8279 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3320 | /* 8281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3321 | /* 8285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3322 | /* 8288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3323 | /* 8294 */ GIR_RootConstrainSelectedInstOperands, |
| 3324 | /* 8295 */ // GIR_Coverage, 910, |
| 3325 | /* 8295 */ GIR_EraseRootFromParent_Done, |
| 3326 | /* 8296 */ // Label 195: @8296 |
| 3327 | /* 8296 */ GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(8349), // Rule ID 904 // |
| 3328 | /* 8301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3329 | /* 8304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3330 | /* 8308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3331 | /* 8312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3332 | /* 8316 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3333 | /* 8320 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3334 | /* 8325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3335 | /* 8327 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3336 | /* 8327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 3337 | /* 8330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3338 | /* 8332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3339 | /* 8334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3340 | /* 8338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3341 | /* 8341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3342 | /* 8347 */ GIR_RootConstrainSelectedInstOperands, |
| 3343 | /* 8348 */ // GIR_Coverage, 904, |
| 3344 | /* 8348 */ GIR_EraseRootFromParent_Done, |
| 3345 | /* 8349 */ // Label 196: @8349 |
| 3346 | /* 8349 */ GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(8402), // Rule ID 909 // |
| 3347 | /* 8354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3348 | /* 8357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3349 | /* 8361 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3350 | /* 8365 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3351 | /* 8369 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3352 | /* 8373 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3353 | /* 8378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3354 | /* 8380 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3355 | /* 8380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3356 | /* 8383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3357 | /* 8385 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3358 | /* 8387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3359 | /* 8391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3360 | /* 8394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3361 | /* 8400 */ GIR_RootConstrainSelectedInstOperands, |
| 3362 | /* 8401 */ // GIR_Coverage, 909, |
| 3363 | /* 8401 */ GIR_EraseRootFromParent_Done, |
| 3364 | /* 8402 */ // Label 197: @8402 |
| 3365 | /* 8402 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(8438), // Rule ID 882 // |
| 3366 | /* 8407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3367 | /* 8410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3368 | /* 8414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3369 | /* 8418 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 3370 | /* 8418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64), |
| 3371 | /* 8421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3372 | /* 8423 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3373 | /* 8425 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3374 | /* 8427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3375 | /* 8430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3376 | /* 8436 */ GIR_RootConstrainSelectedInstOperands, |
| 3377 | /* 8437 */ // GIR_Coverage, 882, |
| 3378 | /* 8437 */ GIR_EraseRootFromParent_Done, |
| 3379 | /* 8438 */ // Label 198: @8438 |
| 3380 | /* 8438 */ GIM_Reject, |
| 3381 | /* 8439 */ // Label 182: @8439 |
| 3382 | /* 8439 */ GIM_Reject, |
| 3383 | /* 8440 */ // Label 97: @8440 |
| 3384 | /* 8440 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(8888), |
| 3385 | /* 8445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3386 | /* 8448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3387 | /* 8451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3388 | /* 8455 */ GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(8521), // Rule ID 6181 // |
| 3389 | /* 8460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3390 | /* 8463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3391 | /* 8467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3392 | /* 8471 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3393 | /* 8475 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3394 | /* 8479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3395 | /* 8484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3396 | /* 8489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3397 | /* 8493 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3398 | /* 8495 */ // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3399 | /* 8495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16), |
| 3400 | /* 8498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3401 | /* 8500 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3402 | /* 8502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3403 | /* 8506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3404 | /* 8510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3405 | /* 8513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3406 | /* 8519 */ GIR_RootConstrainSelectedInstOperands, |
| 3407 | /* 8520 */ // GIR_Coverage, 6181, |
| 3408 | /* 8520 */ GIR_EraseRootFromParent_Done, |
| 3409 | /* 8521 */ // Label 200: @8521 |
| 3410 | /* 8521 */ GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(8587), // Rule ID 6187 // |
| 3411 | /* 8526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3412 | /* 8529 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3413 | /* 8533 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3414 | /* 8537 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3415 | /* 8541 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3416 | /* 8545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3417 | /* 8550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3418 | /* 8555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3419 | /* 8559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3420 | /* 8561 */ // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3421 | /* 8561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16), |
| 3422 | /* 8564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3423 | /* 8566 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3424 | /* 8568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3425 | /* 8572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3426 | /* 8576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3427 | /* 8579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3428 | /* 8585 */ GIR_RootConstrainSelectedInstOperands, |
| 3429 | /* 8586 */ // GIR_Coverage, 6187, |
| 3430 | /* 8586 */ GIR_EraseRootFromParent_Done, |
| 3431 | /* 8587 */ // Label 201: @8587 |
| 3432 | /* 8587 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(8653), // Rule ID 6069 // |
| 3433 | /* 8592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3434 | /* 8595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3435 | /* 8599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3436 | /* 8603 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3437 | /* 8607 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3438 | /* 8611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3439 | /* 8616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3440 | /* 8621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3441 | /* 8625 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3442 | /* 8627 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3443 | /* 8627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3444 | /* 8630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3445 | /* 8632 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3446 | /* 8634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3447 | /* 8638 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3448 | /* 8642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3449 | /* 8645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3450 | /* 8651 */ GIR_RootConstrainSelectedInstOperands, |
| 3451 | /* 8652 */ // GIR_Coverage, 6069, |
| 3452 | /* 8652 */ GIR_EraseRootFromParent_Done, |
| 3453 | /* 8653 */ // Label 202: @8653 |
| 3454 | /* 8653 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(8719), // Rule ID 1341 // |
| 3455 | /* 8658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3456 | /* 8661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3457 | /* 8665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3458 | /* 8669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3459 | /* 8673 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3460 | /* 8677 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3461 | /* 8681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3462 | /* 8686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3463 | /* 8691 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3464 | /* 8693 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3465 | /* 8693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16), |
| 3466 | /* 8696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3467 | /* 8698 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3468 | /* 8700 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3469 | /* 8704 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3470 | /* 8708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3471 | /* 8711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3472 | /* 8717 */ GIR_RootConstrainSelectedInstOperands, |
| 3473 | /* 8718 */ // GIR_Coverage, 1341, |
| 3474 | /* 8718 */ GIR_EraseRootFromParent_Done, |
| 3475 | /* 8719 */ // Label 203: @8719 |
| 3476 | /* 8719 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(8785), // Rule ID 1347 // |
| 3477 | /* 8724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3478 | /* 8727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3479 | /* 8731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3480 | /* 8735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3481 | /* 8739 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3482 | /* 8743 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3483 | /* 8747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3484 | /* 8752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3485 | /* 8757 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3486 | /* 8759 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3487 | /* 8759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16), |
| 3488 | /* 8762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3489 | /* 8764 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3490 | /* 8766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3491 | /* 8770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3492 | /* 8774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3493 | /* 8777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3494 | /* 8783 */ GIR_RootConstrainSelectedInstOperands, |
| 3495 | /* 8784 */ // GIR_Coverage, 1347, |
| 3496 | /* 8784 */ GIR_EraseRootFromParent_Done, |
| 3497 | /* 8785 */ // Label 204: @8785 |
| 3498 | /* 8785 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(8851), // Rule ID 1007 // |
| 3499 | /* 8790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3500 | /* 8793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3501 | /* 8797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3502 | /* 8801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3503 | /* 8805 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3504 | /* 8809 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3505 | /* 8813 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3506 | /* 8818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3507 | /* 8823 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3508 | /* 8825 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3509 | /* 8825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3510 | /* 8828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3511 | /* 8830 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3512 | /* 8832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3513 | /* 8836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3514 | /* 8840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3515 | /* 8843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3516 | /* 8849 */ GIR_RootConstrainSelectedInstOperands, |
| 3517 | /* 8850 */ // GIR_Coverage, 1007, |
| 3518 | /* 8850 */ GIR_EraseRootFromParent_Done, |
| 3519 | /* 8851 */ // Label 205: @8851 |
| 3520 | /* 8851 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(8887), // Rule ID 876 // |
| 3521 | /* 8856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3522 | /* 8859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3523 | /* 8863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3524 | /* 8867 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3525 | /* 8867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16), |
| 3526 | /* 8870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3527 | /* 8872 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3528 | /* 8874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3529 | /* 8876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3530 | /* 8879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3531 | /* 8885 */ GIR_RootConstrainSelectedInstOperands, |
| 3532 | /* 8886 */ // GIR_Coverage, 876, |
| 3533 | /* 8886 */ GIR_EraseRootFromParent_Done, |
| 3534 | /* 8887 */ // Label 206: @8887 |
| 3535 | /* 8887 */ GIM_Reject, |
| 3536 | /* 8888 */ // Label 199: @8888 |
| 3537 | /* 8888 */ GIM_Reject, |
| 3538 | /* 8889 */ // Label 98: @8889 |
| 3539 | /* 8889 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(10452), |
| 3540 | /* 8894 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3541 | /* 8897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3542 | /* 8900 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(8972), // Rule ID 897 // |
| 3543 | /* 8905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3544 | /* 8908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3545 | /* 8912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3546 | /* 8916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3547 | /* 8920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3548 | /* 8924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3549 | /* 8929 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3550 | /* 8933 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3551 | /* 8937 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3552 | /* 8941 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3553 | /* 8946 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3554 | /* 8948 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3555 | /* 8948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3556 | /* 8951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3557 | /* 8953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3558 | /* 8957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3559 | /* 8961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3560 | /* 8964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3561 | /* 8970 */ GIR_RootConstrainSelectedInstOperands, |
| 3562 | /* 8971 */ // GIR_Coverage, 897, |
| 3563 | /* 8971 */ GIR_EraseRootFromParent_Done, |
| 3564 | /* 8972 */ // Label 208: @8972 |
| 3565 | /* 8972 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(9044), // Rule ID 896 // |
| 3566 | /* 8977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3567 | /* 8980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3568 | /* 8984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3569 | /* 8988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3570 | /* 8992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3571 | /* 8996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3572 | /* 9001 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3573 | /* 9005 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3574 | /* 9009 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3575 | /* 9013 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3576 | /* 9018 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3577 | /* 9020 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3578 | /* 9020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3579 | /* 9023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3580 | /* 9025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3581 | /* 9029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3582 | /* 9033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3583 | /* 9036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3584 | /* 9042 */ GIR_RootConstrainSelectedInstOperands, |
| 3585 | /* 9043 */ // GIR_Coverage, 896, |
| 3586 | /* 9043 */ GIR_EraseRootFromParent_Done, |
| 3587 | /* 9044 */ // Label 209: @9044 |
| 3588 | /* 9044 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(9116), // Rule ID 888 // |
| 3589 | /* 9049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3590 | /* 9052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3591 | /* 9056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3592 | /* 9060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3593 | /* 9064 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3594 | /* 9068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3595 | /* 9073 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3596 | /* 9077 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3597 | /* 9081 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3598 | /* 9085 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3599 | /* 9090 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3600 | /* 9092 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3601 | /* 9092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32), |
| 3602 | /* 9095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3603 | /* 9097 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3604 | /* 9101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3605 | /* 9105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3606 | /* 9108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3607 | /* 9114 */ GIR_RootConstrainSelectedInstOperands, |
| 3608 | /* 9115 */ // GIR_Coverage, 888, |
| 3609 | /* 9115 */ GIR_EraseRootFromParent_Done, |
| 3610 | /* 9116 */ // Label 210: @9116 |
| 3611 | /* 9116 */ GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(9198), // Rule ID 6193 // |
| 3612 | /* 9121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3613 | /* 9124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3614 | /* 9128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3615 | /* 9132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3616 | /* 9136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3617 | /* 9140 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3618 | /* 9144 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3619 | /* 9148 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3620 | /* 9152 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3621 | /* 9156 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3622 | /* 9161 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3623 | /* 9166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3624 | /* 9170 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3625 | /* 9172 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3626 | /* 9172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32), |
| 3627 | /* 9175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3628 | /* 9177 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3629 | /* 9179 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3630 | /* 9183 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3631 | /* 9187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3632 | /* 9190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3633 | /* 9196 */ GIR_RootConstrainSelectedInstOperands, |
| 3634 | /* 9197 */ // GIR_Coverage, 6193, |
| 3635 | /* 9197 */ GIR_EraseRootFromParent_Done, |
| 3636 | /* 9198 */ // Label 211: @9198 |
| 3637 | /* 9198 */ GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(9280), // Rule ID 6196 // |
| 3638 | /* 9203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3639 | /* 9206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3640 | /* 9210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3641 | /* 9214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3642 | /* 9218 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3643 | /* 9222 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3644 | /* 9226 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3645 | /* 9230 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3646 | /* 9234 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3647 | /* 9238 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3648 | /* 9243 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3649 | /* 9248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3650 | /* 9252 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3651 | /* 9254 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3652 | /* 9254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32), |
| 3653 | /* 9257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3654 | /* 9259 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3655 | /* 9261 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3656 | /* 9265 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3657 | /* 9269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3658 | /* 9272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3659 | /* 9278 */ GIR_RootConstrainSelectedInstOperands, |
| 3660 | /* 9279 */ // GIR_Coverage, 6196, |
| 3661 | /* 9279 */ GIR_EraseRootFromParent_Done, |
| 3662 | /* 9280 */ // Label 212: @9280 |
| 3663 | /* 9280 */ GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(9352), // Rule ID 895 // |
| 3664 | /* 9285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3665 | /* 9288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3666 | /* 9292 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3667 | /* 9296 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3668 | /* 9300 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3669 | /* 9304 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3670 | /* 9309 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3671 | /* 9313 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3672 | /* 9317 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3673 | /* 9321 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3674 | /* 9326 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3675 | /* 9328 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3676 | /* 9328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3677 | /* 9331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3678 | /* 9333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3679 | /* 9337 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3680 | /* 9341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3681 | /* 9344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3682 | /* 9350 */ GIR_RootConstrainSelectedInstOperands, |
| 3683 | /* 9351 */ // GIR_Coverage, 895, |
| 3684 | /* 9351 */ GIR_EraseRootFromParent_Done, |
| 3685 | /* 9352 */ // Label 213: @9352 |
| 3686 | /* 9352 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(9424), // Rule ID 894 // |
| 3687 | /* 9357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3688 | /* 9360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3689 | /* 9364 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3690 | /* 9368 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3691 | /* 9372 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3692 | /* 9376 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3693 | /* 9381 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3694 | /* 9385 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3695 | /* 9389 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3696 | /* 9393 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3697 | /* 9398 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3698 | /* 9400 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3699 | /* 9400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3700 | /* 9403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3701 | /* 9405 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3702 | /* 9409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3703 | /* 9413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3704 | /* 9416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3705 | /* 9422 */ GIR_RootConstrainSelectedInstOperands, |
| 3706 | /* 9423 */ // GIR_Coverage, 894, |
| 3707 | /* 9423 */ GIR_EraseRootFromParent_Done, |
| 3708 | /* 9424 */ // Label 214: @9424 |
| 3709 | /* 9424 */ GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(9506), // Rule ID 1353 // |
| 3710 | /* 9429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3711 | /* 9432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3712 | /* 9436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3713 | /* 9440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3714 | /* 9444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3715 | /* 9448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3716 | /* 9452 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3717 | /* 9456 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3718 | /* 9460 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3719 | /* 9464 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3720 | /* 9468 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3721 | /* 9473 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3722 | /* 9478 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3723 | /* 9480 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3724 | /* 9480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32), |
| 3725 | /* 9483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3726 | /* 9485 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3727 | /* 9487 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3728 | /* 9491 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3729 | /* 9495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3730 | /* 9498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3731 | /* 9504 */ GIR_RootConstrainSelectedInstOperands, |
| 3732 | /* 9505 */ // GIR_Coverage, 1353, |
| 3733 | /* 9505 */ GIR_EraseRootFromParent_Done, |
| 3734 | /* 9506 */ // Label 215: @9506 |
| 3735 | /* 9506 */ GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(9588), // Rule ID 1356 // |
| 3736 | /* 9511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3737 | /* 9514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3738 | /* 9518 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3739 | /* 9522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3740 | /* 9526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3741 | /* 9530 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3742 | /* 9534 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3743 | /* 9538 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3744 | /* 9542 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3745 | /* 9546 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3746 | /* 9550 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3747 | /* 9555 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3748 | /* 9560 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3749 | /* 9562 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3750 | /* 9562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32), |
| 3751 | /* 9565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3752 | /* 9567 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3753 | /* 9569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3754 | /* 9573 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3755 | /* 9577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3756 | /* 9580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3757 | /* 9586 */ GIR_RootConstrainSelectedInstOperands, |
| 3758 | /* 9587 */ // GIR_Coverage, 1356, |
| 3759 | /* 9587 */ GIR_EraseRootFromParent_Done, |
| 3760 | /* 9588 */ // Label 216: @9588 |
| 3761 | /* 9588 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(9658), // Rule ID 6185 // |
| 3762 | /* 9593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3763 | /* 9596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3764 | /* 9600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3765 | /* 9604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3766 | /* 9608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3767 | /* 9612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3768 | /* 9616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3769 | /* 9621 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3770 | /* 9626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3771 | /* 9630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3772 | /* 9632 */ // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3773 | /* 9632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32), |
| 3774 | /* 9635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3775 | /* 9637 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3776 | /* 9639 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3777 | /* 9643 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3778 | /* 9647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3779 | /* 9650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3780 | /* 9656 */ GIR_RootConstrainSelectedInstOperands, |
| 3781 | /* 9657 */ // GIR_Coverage, 6185, |
| 3782 | /* 9657 */ GIR_EraseRootFromParent_Done, |
| 3783 | /* 9658 */ // Label 217: @9658 |
| 3784 | /* 9658 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(9728), // Rule ID 6191 // |
| 3785 | /* 9663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3786 | /* 9666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3787 | /* 9670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3788 | /* 9674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3789 | /* 9678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3790 | /* 9682 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3791 | /* 9686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3792 | /* 9691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3793 | /* 9696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3794 | /* 9700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3795 | /* 9702 */ // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3796 | /* 9702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32), |
| 3797 | /* 9705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3798 | /* 9707 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3799 | /* 9709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3800 | /* 9713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3801 | /* 9717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3802 | /* 9720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3803 | /* 9726 */ GIR_RootConstrainSelectedInstOperands, |
| 3804 | /* 9727 */ // GIR_Coverage, 6191, |
| 3805 | /* 9727 */ GIR_EraseRootFromParent_Done, |
| 3806 | /* 9728 */ // Label 218: @9728 |
| 3807 | /* 9728 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(9798), // Rule ID 6073 // |
| 3808 | /* 9733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3809 | /* 9736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3810 | /* 9740 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3811 | /* 9744 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3812 | /* 9748 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3813 | /* 9752 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3814 | /* 9756 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3815 | /* 9761 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3816 | /* 9766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3817 | /* 9770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3818 | /* 9772 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3819 | /* 9772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 3820 | /* 9775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3821 | /* 9777 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3822 | /* 9779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3823 | /* 9783 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3824 | /* 9787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3825 | /* 9790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3826 | /* 9796 */ GIR_RootConstrainSelectedInstOperands, |
| 3827 | /* 9797 */ // GIR_Coverage, 6073, |
| 3828 | /* 9797 */ GIR_EraseRootFromParent_Done, |
| 3829 | /* 9798 */ // Label 219: @9798 |
| 3830 | /* 9798 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(9855), // Rule ID 6047 // |
| 3831 | /* 9803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3832 | /* 9806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3833 | /* 9810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3834 | /* 9814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3835 | /* 9818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3836 | /* 9822 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3837 | /* 9827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3838 | /* 9831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3839 | /* 9833 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3840 | /* 9833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 3841 | /* 9836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3842 | /* 9838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3843 | /* 9840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3844 | /* 9844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3845 | /* 9847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3846 | /* 9853 */ GIR_RootConstrainSelectedInstOperands, |
| 3847 | /* 9854 */ // GIR_Coverage, 6047, |
| 3848 | /* 9854 */ GIR_EraseRootFromParent_Done, |
| 3849 | /* 9855 */ // Label 220: @9855 |
| 3850 | /* 9855 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(9912), // Rule ID 6042 // |
| 3851 | /* 9860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3852 | /* 9863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3853 | /* 9867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3854 | /* 9871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3855 | /* 9875 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3856 | /* 9879 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3857 | /* 9884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3858 | /* 9888 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3859 | /* 9890 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3860 | /* 9890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 3861 | /* 9893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3862 | /* 9895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3863 | /* 9897 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3864 | /* 9901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3865 | /* 9904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3866 | /* 9910 */ GIR_RootConstrainSelectedInstOperands, |
| 3867 | /* 9911 */ // GIR_Coverage, 6042, |
| 3868 | /* 9911 */ GIR_EraseRootFromParent_Done, |
| 3869 | /* 9912 */ // Label 221: @9912 |
| 3870 | /* 9912 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(9969), // Rule ID 6046 // |
| 3871 | /* 9917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3872 | /* 9920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3873 | /* 9924 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3874 | /* 9928 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3875 | /* 9932 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3876 | /* 9936 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3877 | /* 9941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3878 | /* 9945 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3879 | /* 9947 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3880 | /* 9947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 3881 | /* 9950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3882 | /* 9952 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3883 | /* 9954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3884 | /* 9958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3885 | /* 9961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3886 | /* 9967 */ GIR_RootConstrainSelectedInstOperands, |
| 3887 | /* 9968 */ // GIR_Coverage, 6046, |
| 3888 | /* 9968 */ GIR_EraseRootFromParent_Done, |
| 3889 | /* 9969 */ // Label 222: @9969 |
| 3890 | /* 9969 */ GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(10039), // Rule ID 1345 // |
| 3891 | /* 9974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3892 | /* 9977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3893 | /* 9981 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3894 | /* 9985 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3895 | /* 9989 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3896 | /* 9993 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3897 | /* 9997 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3898 | /* 10001 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3899 | /* 10006 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3900 | /* 10011 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3901 | /* 10013 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3902 | /* 10013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32), |
| 3903 | /* 10016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3904 | /* 10018 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3905 | /* 10020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3906 | /* 10024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3907 | /* 10028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3908 | /* 10031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3909 | /* 10037 */ GIR_RootConstrainSelectedInstOperands, |
| 3910 | /* 10038 */ // GIR_Coverage, 1345, |
| 3911 | /* 10038 */ GIR_EraseRootFromParent_Done, |
| 3912 | /* 10039 */ // Label 223: @10039 |
| 3913 | /* 10039 */ GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(10109), // Rule ID 1351 // |
| 3914 | /* 10044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3915 | /* 10047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3916 | /* 10051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3917 | /* 10055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3918 | /* 10059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3919 | /* 10063 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3920 | /* 10067 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3921 | /* 10071 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3922 | /* 10076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3923 | /* 10081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3924 | /* 10083 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3925 | /* 10083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32), |
| 3926 | /* 10086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3927 | /* 10088 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3928 | /* 10090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3929 | /* 10094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3930 | /* 10098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3931 | /* 10101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3932 | /* 10107 */ GIR_RootConstrainSelectedInstOperands, |
| 3933 | /* 10108 */ // GIR_Coverage, 1351, |
| 3934 | /* 10108 */ GIR_EraseRootFromParent_Done, |
| 3935 | /* 10109 */ // Label 224: @10109 |
| 3936 | /* 10109 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(10179), // Rule ID 1011 // |
| 3937 | /* 10114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3938 | /* 10117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3939 | /* 10121 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3940 | /* 10125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3941 | /* 10129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3942 | /* 10133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3943 | /* 10137 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3944 | /* 10141 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3945 | /* 10146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3946 | /* 10151 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3947 | /* 10153 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3948 | /* 10153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 3949 | /* 10156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3950 | /* 10158 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3951 | /* 10160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3952 | /* 10164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3953 | /* 10168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3954 | /* 10171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3955 | /* 10177 */ GIR_RootConstrainSelectedInstOperands, |
| 3956 | /* 10178 */ // GIR_Coverage, 1011, |
| 3957 | /* 10178 */ GIR_EraseRootFromParent_Done, |
| 3958 | /* 10179 */ // Label 225: @10179 |
| 3959 | /* 10179 */ GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(10236), // Rule ID 908 // |
| 3960 | /* 10184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3961 | /* 10187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3962 | /* 10191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3963 | /* 10195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3964 | /* 10199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3965 | /* 10203 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3966 | /* 10207 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3967 | /* 10212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3968 | /* 10214 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3969 | /* 10214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 3970 | /* 10217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3971 | /* 10219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3972 | /* 10221 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3973 | /* 10225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3974 | /* 10228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3975 | /* 10234 */ GIR_RootConstrainSelectedInstOperands, |
| 3976 | /* 10235 */ // GIR_Coverage, 908, |
| 3977 | /* 10235 */ GIR_EraseRootFromParent_Done, |
| 3978 | /* 10236 */ // Label 226: @10236 |
| 3979 | /* 10236 */ GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(10293), // Rule ID 903 // |
| 3980 | /* 10241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3981 | /* 10244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3982 | /* 10248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3983 | /* 10252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3984 | /* 10256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3985 | /* 10260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3986 | /* 10264 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3987 | /* 10269 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3988 | /* 10271 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3989 | /* 10271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 3990 | /* 10274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3991 | /* 10276 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3992 | /* 10278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3993 | /* 10282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3994 | /* 10285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3995 | /* 10291 */ GIR_RootConstrainSelectedInstOperands, |
| 3996 | /* 10292 */ // GIR_Coverage, 903, |
| 3997 | /* 10292 */ GIR_EraseRootFromParent_Done, |
| 3998 | /* 10293 */ // Label 227: @10293 |
| 3999 | /* 10293 */ GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(10350), // Rule ID 907 // |
| 4000 | /* 10298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4001 | /* 10301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4002 | /* 10305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4003 | /* 10309 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4004 | /* 10313 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4005 | /* 10317 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4006 | /* 10321 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4007 | /* 10326 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4008 | /* 10328 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4009 | /* 10328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4010 | /* 10331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4011 | /* 10333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4012 | /* 10335 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4013 | /* 10339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4014 | /* 10342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4015 | /* 10348 */ GIR_RootConstrainSelectedInstOperands, |
| 4016 | /* 10349 */ // GIR_Coverage, 907, |
| 4017 | /* 10349 */ GIR_EraseRootFromParent_Done, |
| 4018 | /* 10350 */ // Label 228: @10350 |
| 4019 | /* 10350 */ GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(10390), // Rule ID 880 // |
| 4020 | /* 10355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4021 | /* 10358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4022 | /* 10362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4023 | /* 10366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4024 | /* 10370 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4025 | /* 10370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32), |
| 4026 | /* 10373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4027 | /* 10375 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4028 | /* 10377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4029 | /* 10379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4030 | /* 10382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4031 | /* 10388 */ GIR_RootConstrainSelectedInstOperands, |
| 4032 | /* 10389 */ // GIR_Coverage, 880, |
| 4033 | /* 10389 */ GIR_EraseRootFromParent_Done, |
| 4034 | /* 10390 */ // Label 229: @10390 |
| 4035 | /* 10390 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(10451), // Rule ID 3878 // |
| 4036 | /* 10395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4037 | /* 10398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4038 | /* 10402 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4039 | /* 10406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4040 | /* 10410 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 4041 | /* 10410 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4042 | /* 10413 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4043 | /* 10417 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 4044 | /* 10422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32), |
| 4045 | /* 10425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4046 | /* 10427 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4047 | /* 10429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4048 | /* 10431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4049 | /* 10434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4050 | /* 10440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4051 | /* 10446 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4052 | /* 10449 */ GIR_RootConstrainSelectedInstOperands, |
| 4053 | /* 10450 */ // GIR_Coverage, 3878, |
| 4054 | /* 10450 */ GIR_EraseRootFromParent_Done, |
| 4055 | /* 10451 */ // Label 230: @10451 |
| 4056 | /* 10451 */ GIM_Reject, |
| 4057 | /* 10452 */ // Label 207: @10452 |
| 4058 | /* 10452 */ GIM_Reject, |
| 4059 | /* 10453 */ // Label 99: @10453 |
| 4060 | /* 10453 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(10901), |
| 4061 | /* 10458 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4062 | /* 10461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4063 | /* 10464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4064 | /* 10468 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(10534), // Rule ID 6180 // |
| 4065 | /* 10473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4066 | /* 10476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4067 | /* 10480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4068 | /* 10484 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4069 | /* 10488 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4070 | /* 10492 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4071 | /* 10497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4072 | /* 10502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4073 | /* 10506 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4074 | /* 10508 */ // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4075 | /* 10508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8), |
| 4076 | /* 10511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4077 | /* 10513 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4078 | /* 10515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4079 | /* 10519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4080 | /* 10523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4081 | /* 10526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4082 | /* 10532 */ GIR_RootConstrainSelectedInstOperands, |
| 4083 | /* 10533 */ // GIR_Coverage, 6180, |
| 4084 | /* 10533 */ GIR_EraseRootFromParent_Done, |
| 4085 | /* 10534 */ // Label 232: @10534 |
| 4086 | /* 10534 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(10600), // Rule ID 6186 // |
| 4087 | /* 10539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4088 | /* 10542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4089 | /* 10546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4090 | /* 10550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4091 | /* 10554 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4092 | /* 10558 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4093 | /* 10563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4094 | /* 10568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4095 | /* 10572 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4096 | /* 10574 */ // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4097 | /* 10574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8), |
| 4098 | /* 10577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4099 | /* 10579 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4100 | /* 10581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4101 | /* 10585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4102 | /* 10589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4103 | /* 10592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4104 | /* 10598 */ GIR_RootConstrainSelectedInstOperands, |
| 4105 | /* 10599 */ // GIR_Coverage, 6186, |
| 4106 | /* 10599 */ GIR_EraseRootFromParent_Done, |
| 4107 | /* 10600 */ // Label 233: @10600 |
| 4108 | /* 10600 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(10666), // Rule ID 6068 // |
| 4109 | /* 10605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4110 | /* 10608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4111 | /* 10612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4112 | /* 10616 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4113 | /* 10620 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4114 | /* 10624 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4115 | /* 10629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4116 | /* 10634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4117 | /* 10638 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4118 | /* 10640 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4119 | /* 10640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 4120 | /* 10643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4121 | /* 10645 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4122 | /* 10647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4123 | /* 10651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4124 | /* 10655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4125 | /* 10658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4126 | /* 10664 */ GIR_RootConstrainSelectedInstOperands, |
| 4127 | /* 10665 */ // GIR_Coverage, 6068, |
| 4128 | /* 10665 */ GIR_EraseRootFromParent_Done, |
| 4129 | /* 10666 */ // Label 234: @10666 |
| 4130 | /* 10666 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(10732), // Rule ID 1340 // |
| 4131 | /* 10671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4132 | /* 10674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4133 | /* 10678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4134 | /* 10682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4135 | /* 10686 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4136 | /* 10690 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4137 | /* 10694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4138 | /* 10699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4139 | /* 10704 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4140 | /* 10706 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4141 | /* 10706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8), |
| 4142 | /* 10709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4143 | /* 10711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4144 | /* 10713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4145 | /* 10717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4146 | /* 10721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4147 | /* 10724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4148 | /* 10730 */ GIR_RootConstrainSelectedInstOperands, |
| 4149 | /* 10731 */ // GIR_Coverage, 1340, |
| 4150 | /* 10731 */ GIR_EraseRootFromParent_Done, |
| 4151 | /* 10732 */ // Label 235: @10732 |
| 4152 | /* 10732 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(10798), // Rule ID 1346 // |
| 4153 | /* 10737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4154 | /* 10740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4155 | /* 10744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4156 | /* 10748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4157 | /* 10752 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4158 | /* 10756 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4159 | /* 10760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4160 | /* 10765 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4161 | /* 10770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4162 | /* 10772 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4163 | /* 10772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8), |
| 4164 | /* 10775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4165 | /* 10777 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4166 | /* 10779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4167 | /* 10783 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4168 | /* 10787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4169 | /* 10790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4170 | /* 10796 */ GIR_RootConstrainSelectedInstOperands, |
| 4171 | /* 10797 */ // GIR_Coverage, 1346, |
| 4172 | /* 10797 */ GIR_EraseRootFromParent_Done, |
| 4173 | /* 10798 */ // Label 236: @10798 |
| 4174 | /* 10798 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(10864), // Rule ID 1006 // |
| 4175 | /* 10803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4176 | /* 10806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4177 | /* 10810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4178 | /* 10814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4179 | /* 10818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4180 | /* 10822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4181 | /* 10826 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4182 | /* 10831 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4183 | /* 10836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4184 | /* 10838 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4185 | /* 10838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 4186 | /* 10841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4187 | /* 10843 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4188 | /* 10845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4189 | /* 10849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4190 | /* 10853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4191 | /* 10856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4192 | /* 10862 */ GIR_RootConstrainSelectedInstOperands, |
| 4193 | /* 10863 */ // GIR_Coverage, 1006, |
| 4194 | /* 10863 */ GIR_EraseRootFromParent_Done, |
| 4195 | /* 10864 */ // Label 237: @10864 |
| 4196 | /* 10864 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(10900), // Rule ID 875 // |
| 4197 | /* 10869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4198 | /* 10872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4199 | /* 10876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4200 | /* 10880 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4201 | /* 10880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8), |
| 4202 | /* 10883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4203 | /* 10885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4204 | /* 10887 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4205 | /* 10889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4206 | /* 10892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4207 | /* 10898 */ GIR_RootConstrainSelectedInstOperands, |
| 4208 | /* 10899 */ // GIR_Coverage, 875, |
| 4209 | /* 10899 */ GIR_EraseRootFromParent_Done, |
| 4210 | /* 10900 */ // Label 238: @10900 |
| 4211 | /* 10900 */ GIM_Reject, |
| 4212 | /* 10901 */ // Label 231: @10901 |
| 4213 | /* 10901 */ GIM_Reject, |
| 4214 | /* 10902 */ // Label 100: @10902 |
| 4215 | /* 10902 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(12465), |
| 4216 | /* 10907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4217 | /* 10910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4218 | /* 10913 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(10985), // Rule ID 893 // |
| 4219 | /* 10918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4220 | /* 10921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4221 | /* 10925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4222 | /* 10929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4223 | /* 10933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4224 | /* 10937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4225 | /* 10942 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4226 | /* 10946 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4227 | /* 10950 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4228 | /* 10954 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4229 | /* 10959 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4230 | /* 10961 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4231 | /* 10961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 4232 | /* 10964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4233 | /* 10966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4234 | /* 10970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4235 | /* 10974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4236 | /* 10977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4237 | /* 10983 */ GIR_RootConstrainSelectedInstOperands, |
| 4238 | /* 10984 */ // GIR_Coverage, 893, |
| 4239 | /* 10984 */ GIR_EraseRootFromParent_Done, |
| 4240 | /* 10985 */ // Label 240: @10985 |
| 4241 | /* 10985 */ GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(11057), // Rule ID 892 // |
| 4242 | /* 10990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4243 | /* 10993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4244 | /* 10997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4245 | /* 11001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4246 | /* 11005 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4247 | /* 11009 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4248 | /* 11014 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4249 | /* 11018 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4250 | /* 11022 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4251 | /* 11026 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4252 | /* 11031 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4253 | /* 11033 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4254 | /* 11033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 4255 | /* 11036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4256 | /* 11038 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4257 | /* 11042 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4258 | /* 11046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4259 | /* 11049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4260 | /* 11055 */ GIR_RootConstrainSelectedInstOperands, |
| 4261 | /* 11056 */ // GIR_Coverage, 892, |
| 4262 | /* 11056 */ GIR_EraseRootFromParent_Done, |
| 4263 | /* 11057 */ // Label 241: @11057 |
| 4264 | /* 11057 */ GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(11129), // Rule ID 887 // |
| 4265 | /* 11062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4266 | /* 11065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4267 | /* 11069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4268 | /* 11073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4269 | /* 11077 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4270 | /* 11081 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4271 | /* 11086 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4272 | /* 11090 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4273 | /* 11094 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4274 | /* 11098 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4275 | /* 11103 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4276 | /* 11105 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4277 | /* 11105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16), |
| 4278 | /* 11108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4279 | /* 11110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4280 | /* 11114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4281 | /* 11118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4282 | /* 11121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4283 | /* 11127 */ GIR_RootConstrainSelectedInstOperands, |
| 4284 | /* 11128 */ // GIR_Coverage, 887, |
| 4285 | /* 11128 */ GIR_EraseRootFromParent_Done, |
| 4286 | /* 11129 */ // Label 242: @11129 |
| 4287 | /* 11129 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(11211), // Rule ID 6192 // |
| 4288 | /* 11134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4289 | /* 11137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4290 | /* 11141 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4291 | /* 11145 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4292 | /* 11149 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4293 | /* 11153 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4294 | /* 11157 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4295 | /* 11161 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4296 | /* 11165 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4297 | /* 11169 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4298 | /* 11174 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4299 | /* 11179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4300 | /* 11183 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4301 | /* 11185 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4302 | /* 11185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16), |
| 4303 | /* 11188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4304 | /* 11190 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4305 | /* 11192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4306 | /* 11196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4307 | /* 11200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4308 | /* 11203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4309 | /* 11209 */ GIR_RootConstrainSelectedInstOperands, |
| 4310 | /* 11210 */ // GIR_Coverage, 6192, |
| 4311 | /* 11210 */ GIR_EraseRootFromParent_Done, |
| 4312 | /* 11211 */ // Label 243: @11211 |
| 4313 | /* 11211 */ GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(11293), // Rule ID 6195 // |
| 4314 | /* 11216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4315 | /* 11219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4316 | /* 11223 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4317 | /* 11227 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4318 | /* 11231 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4319 | /* 11235 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4320 | /* 11239 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4321 | /* 11243 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4322 | /* 11247 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4323 | /* 11251 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4324 | /* 11256 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4325 | /* 11261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4326 | /* 11265 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4327 | /* 11267 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4328 | /* 11267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16), |
| 4329 | /* 11270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4330 | /* 11272 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4331 | /* 11274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4332 | /* 11278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4333 | /* 11282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4334 | /* 11285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4335 | /* 11291 */ GIR_RootConstrainSelectedInstOperands, |
| 4336 | /* 11292 */ // GIR_Coverage, 6195, |
| 4337 | /* 11292 */ GIR_EraseRootFromParent_Done, |
| 4338 | /* 11293 */ // Label 244: @11293 |
| 4339 | /* 11293 */ GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(11365), // Rule ID 891 // |
| 4340 | /* 11298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4341 | /* 11301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4342 | /* 11305 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4343 | /* 11309 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4344 | /* 11313 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4345 | /* 11317 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4346 | /* 11322 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4347 | /* 11326 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4348 | /* 11330 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4349 | /* 11334 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4350 | /* 11339 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4351 | /* 11341 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4352 | /* 11341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 4353 | /* 11344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4354 | /* 11346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4355 | /* 11350 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4356 | /* 11354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4357 | /* 11357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4358 | /* 11363 */ GIR_RootConstrainSelectedInstOperands, |
| 4359 | /* 11364 */ // GIR_Coverage, 891, |
| 4360 | /* 11364 */ GIR_EraseRootFromParent_Done, |
| 4361 | /* 11365 */ // Label 245: @11365 |
| 4362 | /* 11365 */ GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(11437), // Rule ID 890 // |
| 4363 | /* 11370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4364 | /* 11373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4365 | /* 11377 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4366 | /* 11381 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4367 | /* 11385 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4368 | /* 11389 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4369 | /* 11394 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4370 | /* 11398 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4371 | /* 11402 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4372 | /* 11406 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4373 | /* 11411 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4374 | /* 11413 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4375 | /* 11413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 4376 | /* 11416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4377 | /* 11418 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4378 | /* 11422 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4379 | /* 11426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4380 | /* 11429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4381 | /* 11435 */ GIR_RootConstrainSelectedInstOperands, |
| 4382 | /* 11436 */ // GIR_Coverage, 890, |
| 4383 | /* 11436 */ GIR_EraseRootFromParent_Done, |
| 4384 | /* 11437 */ // Label 246: @11437 |
| 4385 | /* 11437 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(11519), // Rule ID 1352 // |
| 4386 | /* 11442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4387 | /* 11445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4388 | /* 11449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4389 | /* 11453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4390 | /* 11457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4391 | /* 11461 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4392 | /* 11465 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4393 | /* 11469 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4394 | /* 11473 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4395 | /* 11477 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4396 | /* 11481 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4397 | /* 11486 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4398 | /* 11491 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4399 | /* 11493 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4400 | /* 11493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16), |
| 4401 | /* 11496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4402 | /* 11498 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4403 | /* 11500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4404 | /* 11504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4405 | /* 11508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4406 | /* 11511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4407 | /* 11517 */ GIR_RootConstrainSelectedInstOperands, |
| 4408 | /* 11518 */ // GIR_Coverage, 1352, |
| 4409 | /* 11518 */ GIR_EraseRootFromParent_Done, |
| 4410 | /* 11519 */ // Label 247: @11519 |
| 4411 | /* 11519 */ GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(11601), // Rule ID 1355 // |
| 4412 | /* 11524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4413 | /* 11527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4414 | /* 11531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4415 | /* 11535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4416 | /* 11539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4417 | /* 11543 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4418 | /* 11547 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4419 | /* 11551 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4420 | /* 11555 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4421 | /* 11559 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4422 | /* 11563 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4423 | /* 11568 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4424 | /* 11573 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4425 | /* 11575 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4426 | /* 11575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16), |
| 4427 | /* 11578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4428 | /* 11580 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4429 | /* 11582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4430 | /* 11586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4431 | /* 11590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4432 | /* 11593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4433 | /* 11599 */ GIR_RootConstrainSelectedInstOperands, |
| 4434 | /* 11600 */ // GIR_Coverage, 1355, |
| 4435 | /* 11600 */ GIR_EraseRootFromParent_Done, |
| 4436 | /* 11601 */ // Label 248: @11601 |
| 4437 | /* 11601 */ GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(11671), // Rule ID 6184 // |
| 4438 | /* 11606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4439 | /* 11609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4440 | /* 11613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4441 | /* 11617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4442 | /* 11621 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4443 | /* 11625 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4444 | /* 11629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4445 | /* 11634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4446 | /* 11639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4447 | /* 11643 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4448 | /* 11645 */ // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4449 | /* 11645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16), |
| 4450 | /* 11648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4451 | /* 11650 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4452 | /* 11652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4453 | /* 11656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4454 | /* 11660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4455 | /* 11663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4456 | /* 11669 */ GIR_RootConstrainSelectedInstOperands, |
| 4457 | /* 11670 */ // GIR_Coverage, 6184, |
| 4458 | /* 11670 */ GIR_EraseRootFromParent_Done, |
| 4459 | /* 11671 */ // Label 249: @11671 |
| 4460 | /* 11671 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(11741), // Rule ID 6190 // |
| 4461 | /* 11676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4462 | /* 11679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4463 | /* 11683 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4464 | /* 11687 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4465 | /* 11691 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4466 | /* 11695 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4467 | /* 11699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4468 | /* 11704 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4469 | /* 11709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4470 | /* 11713 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4471 | /* 11715 */ // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4472 | /* 11715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16), |
| 4473 | /* 11718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4474 | /* 11720 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4475 | /* 11722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4476 | /* 11726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4477 | /* 11730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4478 | /* 11733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4479 | /* 11739 */ GIR_RootConstrainSelectedInstOperands, |
| 4480 | /* 11740 */ // GIR_Coverage, 6190, |
| 4481 | /* 11740 */ GIR_EraseRootFromParent_Done, |
| 4482 | /* 11741 */ // Label 250: @11741 |
| 4483 | /* 11741 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(11811), // Rule ID 6072 // |
| 4484 | /* 11746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4485 | /* 11749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4486 | /* 11753 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4487 | /* 11757 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4488 | /* 11761 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4489 | /* 11765 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4490 | /* 11769 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4491 | /* 11774 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4492 | /* 11779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4493 | /* 11783 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4494 | /* 11785 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4495 | /* 11785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 4496 | /* 11788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4497 | /* 11790 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4498 | /* 11792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4499 | /* 11796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4500 | /* 11800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4501 | /* 11803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4502 | /* 11809 */ GIR_RootConstrainSelectedInstOperands, |
| 4503 | /* 11810 */ // GIR_Coverage, 6072, |
| 4504 | /* 11810 */ GIR_EraseRootFromParent_Done, |
| 4505 | /* 11811 */ // Label 251: @11811 |
| 4506 | /* 11811 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(11868), // Rule ID 6045 // |
| 4507 | /* 11816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4508 | /* 11819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4509 | /* 11823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4510 | /* 11827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4511 | /* 11831 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4512 | /* 11835 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4513 | /* 11840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4514 | /* 11844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4515 | /* 11846 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4516 | /* 11846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 4517 | /* 11849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4518 | /* 11851 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4519 | /* 11853 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4520 | /* 11857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4521 | /* 11860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4522 | /* 11866 */ GIR_RootConstrainSelectedInstOperands, |
| 4523 | /* 11867 */ // GIR_Coverage, 6045, |
| 4524 | /* 11867 */ GIR_EraseRootFromParent_Done, |
| 4525 | /* 11868 */ // Label 252: @11868 |
| 4526 | /* 11868 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(11925), // Rule ID 6041 // |
| 4527 | /* 11873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4528 | /* 11876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4529 | /* 11880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4530 | /* 11884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4531 | /* 11888 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4532 | /* 11892 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4533 | /* 11897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4534 | /* 11901 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4535 | /* 11903 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4536 | /* 11903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 4537 | /* 11906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4538 | /* 11908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4539 | /* 11910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4540 | /* 11914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4541 | /* 11917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4542 | /* 11923 */ GIR_RootConstrainSelectedInstOperands, |
| 4543 | /* 11924 */ // GIR_Coverage, 6041, |
| 4544 | /* 11924 */ GIR_EraseRootFromParent_Done, |
| 4545 | /* 11925 */ // Label 253: @11925 |
| 4546 | /* 11925 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(11982), // Rule ID 6044 // |
| 4547 | /* 11930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4548 | /* 11933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4549 | /* 11937 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4550 | /* 11941 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4551 | /* 11945 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4552 | /* 11949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4553 | /* 11954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4554 | /* 11958 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4555 | /* 11960 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4556 | /* 11960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 4557 | /* 11963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4558 | /* 11965 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4559 | /* 11967 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4560 | /* 11971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4561 | /* 11974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4562 | /* 11980 */ GIR_RootConstrainSelectedInstOperands, |
| 4563 | /* 11981 */ // GIR_Coverage, 6044, |
| 4564 | /* 11981 */ GIR_EraseRootFromParent_Done, |
| 4565 | /* 11982 */ // Label 254: @11982 |
| 4566 | /* 11982 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(12052), // Rule ID 1344 // |
| 4567 | /* 11987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4568 | /* 11990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4569 | /* 11994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4570 | /* 11998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4571 | /* 12002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4572 | /* 12006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4573 | /* 12010 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4574 | /* 12014 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4575 | /* 12019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4576 | /* 12024 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4577 | /* 12026 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4578 | /* 12026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16), |
| 4579 | /* 12029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4580 | /* 12031 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4581 | /* 12033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4582 | /* 12037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4583 | /* 12041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4584 | /* 12044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4585 | /* 12050 */ GIR_RootConstrainSelectedInstOperands, |
| 4586 | /* 12051 */ // GIR_Coverage, 1344, |
| 4587 | /* 12051 */ GIR_EraseRootFromParent_Done, |
| 4588 | /* 12052 */ // Label 255: @12052 |
| 4589 | /* 12052 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(12122), // Rule ID 1350 // |
| 4590 | /* 12057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4591 | /* 12060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4592 | /* 12064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4593 | /* 12068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4594 | /* 12072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4595 | /* 12076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4596 | /* 12080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4597 | /* 12084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4598 | /* 12089 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4599 | /* 12094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4600 | /* 12096 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4601 | /* 12096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16), |
| 4602 | /* 12099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4603 | /* 12101 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4604 | /* 12103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4605 | /* 12107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4606 | /* 12111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4607 | /* 12114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4608 | /* 12120 */ GIR_RootConstrainSelectedInstOperands, |
| 4609 | /* 12121 */ // GIR_Coverage, 1350, |
| 4610 | /* 12121 */ GIR_EraseRootFromParent_Done, |
| 4611 | /* 12122 */ // Label 256: @12122 |
| 4612 | /* 12122 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(12192), // Rule ID 1010 // |
| 4613 | /* 12127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4614 | /* 12130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4615 | /* 12134 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4616 | /* 12138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4617 | /* 12142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4618 | /* 12146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4619 | /* 12150 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4620 | /* 12154 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4621 | /* 12159 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4622 | /* 12164 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4623 | /* 12166 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4624 | /* 12166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 4625 | /* 12169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4626 | /* 12171 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4627 | /* 12173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4628 | /* 12177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4629 | /* 12181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4630 | /* 12184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4631 | /* 12190 */ GIR_RootConstrainSelectedInstOperands, |
| 4632 | /* 12191 */ // GIR_Coverage, 1010, |
| 4633 | /* 12191 */ GIR_EraseRootFromParent_Done, |
| 4634 | /* 12192 */ // Label 257: @12192 |
| 4635 | /* 12192 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(12249), // Rule ID 906 // |
| 4636 | /* 12197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4637 | /* 12200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4638 | /* 12204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4639 | /* 12208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4640 | /* 12212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4641 | /* 12216 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4642 | /* 12220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4643 | /* 12225 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4644 | /* 12227 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4645 | /* 12227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 4646 | /* 12230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4647 | /* 12232 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4648 | /* 12234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4649 | /* 12238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4650 | /* 12241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4651 | /* 12247 */ GIR_RootConstrainSelectedInstOperands, |
| 4652 | /* 12248 */ // GIR_Coverage, 906, |
| 4653 | /* 12248 */ GIR_EraseRootFromParent_Done, |
| 4654 | /* 12249 */ // Label 258: @12249 |
| 4655 | /* 12249 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(12306), // Rule ID 902 // |
| 4656 | /* 12254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4657 | /* 12257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4658 | /* 12261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4659 | /* 12265 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4660 | /* 12269 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4661 | /* 12273 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4662 | /* 12277 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4663 | /* 12282 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4664 | /* 12284 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4665 | /* 12284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 4666 | /* 12287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4667 | /* 12289 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4668 | /* 12291 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4669 | /* 12295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4670 | /* 12298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4671 | /* 12304 */ GIR_RootConstrainSelectedInstOperands, |
| 4672 | /* 12305 */ // GIR_Coverage, 902, |
| 4673 | /* 12305 */ GIR_EraseRootFromParent_Done, |
| 4674 | /* 12306 */ // Label 259: @12306 |
| 4675 | /* 12306 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(12363), // Rule ID 905 // |
| 4676 | /* 12311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4677 | /* 12314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4678 | /* 12318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4679 | /* 12322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4680 | /* 12326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4681 | /* 12330 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4682 | /* 12334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4683 | /* 12339 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4684 | /* 12341 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4685 | /* 12341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 4686 | /* 12344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4687 | /* 12346 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4688 | /* 12348 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4689 | /* 12352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4690 | /* 12355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4691 | /* 12361 */ GIR_RootConstrainSelectedInstOperands, |
| 4692 | /* 12362 */ // GIR_Coverage, 905, |
| 4693 | /* 12362 */ GIR_EraseRootFromParent_Done, |
| 4694 | /* 12363 */ // Label 260: @12363 |
| 4695 | /* 12363 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(12403), // Rule ID 879 // |
| 4696 | /* 12368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4697 | /* 12371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4698 | /* 12375 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4699 | /* 12379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4700 | /* 12383 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4701 | /* 12383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16), |
| 4702 | /* 12386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4703 | /* 12388 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4704 | /* 12390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4705 | /* 12392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4706 | /* 12395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4707 | /* 12401 */ GIR_RootConstrainSelectedInstOperands, |
| 4708 | /* 12402 */ // GIR_Coverage, 879, |
| 4709 | /* 12402 */ GIR_EraseRootFromParent_Done, |
| 4710 | /* 12403 */ // Label 261: @12403 |
| 4711 | /* 12403 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(12464), // Rule ID 3874 // |
| 4712 | /* 12408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4713 | /* 12411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4714 | /* 12415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4715 | /* 12419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4716 | /* 12423 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 4717 | /* 12423 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4718 | /* 12426 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4719 | /* 12430 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 4720 | /* 12435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16), |
| 4721 | /* 12438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4722 | /* 12440 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4723 | /* 12442 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4724 | /* 12444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4725 | /* 12447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4726 | /* 12453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4727 | /* 12459 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4728 | /* 12462 */ GIR_RootConstrainSelectedInstOperands, |
| 4729 | /* 12463 */ // GIR_Coverage, 3874, |
| 4730 | /* 12463 */ GIR_EraseRootFromParent_Done, |
| 4731 | /* 12464 */ // Label 262: @12464 |
| 4732 | /* 12464 */ GIM_Reject, |
| 4733 | /* 12465 */ // Label 239: @12465 |
| 4734 | /* 12465 */ GIM_Reject, |
| 4735 | /* 12466 */ // Label 101: @12466 |
| 4736 | /* 12466 */ GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(12999), |
| 4737 | /* 12471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4738 | /* 12474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4739 | /* 12477 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(12547), // Rule ID 6183 // |
| 4740 | /* 12482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4741 | /* 12485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4742 | /* 12489 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4743 | /* 12493 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4744 | /* 12497 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4745 | /* 12501 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4746 | /* 12505 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4747 | /* 12510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4748 | /* 12515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4749 | /* 12519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4750 | /* 12521 */ // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4751 | /* 12521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8), |
| 4752 | /* 12524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4753 | /* 12526 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4754 | /* 12528 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4755 | /* 12532 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4756 | /* 12536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4757 | /* 12539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4758 | /* 12545 */ GIR_RootConstrainSelectedInstOperands, |
| 4759 | /* 12546 */ // GIR_Coverage, 6183, |
| 4760 | /* 12546 */ GIR_EraseRootFromParent_Done, |
| 4761 | /* 12547 */ // Label 264: @12547 |
| 4762 | /* 12547 */ GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(12617), // Rule ID 6189 // |
| 4763 | /* 12552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4764 | /* 12555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4765 | /* 12559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4766 | /* 12563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4767 | /* 12567 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4768 | /* 12571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4769 | /* 12575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4770 | /* 12580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4771 | /* 12585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4772 | /* 12589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4773 | /* 12591 */ // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4774 | /* 12591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8), |
| 4775 | /* 12594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4776 | /* 12596 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4777 | /* 12598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4778 | /* 12602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4779 | /* 12606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4780 | /* 12609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4781 | /* 12615 */ GIR_RootConstrainSelectedInstOperands, |
| 4782 | /* 12616 */ // GIR_Coverage, 6189, |
| 4783 | /* 12616 */ GIR_EraseRootFromParent_Done, |
| 4784 | /* 12617 */ // Label 265: @12617 |
| 4785 | /* 12617 */ GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(12687), // Rule ID 6071 // |
| 4786 | /* 12622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4787 | /* 12625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4788 | /* 12629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4789 | /* 12633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4790 | /* 12637 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4791 | /* 12641 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4792 | /* 12645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4793 | /* 12650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4794 | /* 12655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4795 | /* 12659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4796 | /* 12661 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4797 | /* 12661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 4798 | /* 12664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4799 | /* 12666 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4800 | /* 12668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4801 | /* 12672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4802 | /* 12676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4803 | /* 12679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4804 | /* 12685 */ GIR_RootConstrainSelectedInstOperands, |
| 4805 | /* 12686 */ // GIR_Coverage, 6071, |
| 4806 | /* 12686 */ GIR_EraseRootFromParent_Done, |
| 4807 | /* 12687 */ // Label 266: @12687 |
| 4808 | /* 12687 */ GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(12757), // Rule ID 1343 // |
| 4809 | /* 12692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4810 | /* 12695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4811 | /* 12699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4812 | /* 12703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4813 | /* 12707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4814 | /* 12711 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4815 | /* 12715 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4816 | /* 12719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4817 | /* 12724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4818 | /* 12729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4819 | /* 12731 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4820 | /* 12731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8), |
| 4821 | /* 12734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4822 | /* 12736 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4823 | /* 12738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4824 | /* 12742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4825 | /* 12746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4826 | /* 12749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4827 | /* 12755 */ GIR_RootConstrainSelectedInstOperands, |
| 4828 | /* 12756 */ // GIR_Coverage, 1343, |
| 4829 | /* 12756 */ GIR_EraseRootFromParent_Done, |
| 4830 | /* 12757 */ // Label 267: @12757 |
| 4831 | /* 12757 */ GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(12827), // Rule ID 1349 // |
| 4832 | /* 12762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4833 | /* 12765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4834 | /* 12769 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4835 | /* 12773 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4836 | /* 12777 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4837 | /* 12781 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4838 | /* 12785 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4839 | /* 12789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4840 | /* 12794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4841 | /* 12799 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4842 | /* 12801 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4843 | /* 12801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8), |
| 4844 | /* 12804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4845 | /* 12806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4846 | /* 12808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4847 | /* 12812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4848 | /* 12816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4849 | /* 12819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4850 | /* 12825 */ GIR_RootConstrainSelectedInstOperands, |
| 4851 | /* 12826 */ // GIR_Coverage, 1349, |
| 4852 | /* 12826 */ GIR_EraseRootFromParent_Done, |
| 4853 | /* 12827 */ // Label 268: @12827 |
| 4854 | /* 12827 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(12897), // Rule ID 1009 // |
| 4855 | /* 12832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4856 | /* 12835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4857 | /* 12839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4858 | /* 12843 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4859 | /* 12847 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4860 | /* 12851 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4861 | /* 12855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4862 | /* 12859 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4863 | /* 12864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4864 | /* 12869 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4865 | /* 12871 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4866 | /* 12871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 4867 | /* 12874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4868 | /* 12876 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4869 | /* 12878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4870 | /* 12882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4871 | /* 12886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4872 | /* 12889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4873 | /* 12895 */ GIR_RootConstrainSelectedInstOperands, |
| 4874 | /* 12896 */ // GIR_Coverage, 1009, |
| 4875 | /* 12896 */ GIR_EraseRootFromParent_Done, |
| 4876 | /* 12897 */ // Label 269: @12897 |
| 4877 | /* 12897 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(12937), // Rule ID 878 // |
| 4878 | /* 12902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4879 | /* 12905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4880 | /* 12909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4881 | /* 12913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4882 | /* 12917 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4883 | /* 12917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8), |
| 4884 | /* 12920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4885 | /* 12922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4886 | /* 12924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4887 | /* 12926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4888 | /* 12929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4889 | /* 12935 */ GIR_RootConstrainSelectedInstOperands, |
| 4890 | /* 12936 */ // GIR_Coverage, 878, |
| 4891 | /* 12936 */ GIR_EraseRootFromParent_Done, |
| 4892 | /* 12937 */ // Label 270: @12937 |
| 4893 | /* 12937 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(12998), // Rule ID 3870 // |
| 4894 | /* 12942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4895 | /* 12945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4896 | /* 12949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4897 | /* 12953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4898 | /* 12957 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 4899 | /* 12957 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4900 | /* 12960 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4901 | /* 12964 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 4902 | /* 12969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8), |
| 4903 | /* 12972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4904 | /* 12974 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4905 | /* 12976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4906 | /* 12978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4907 | /* 12981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4908 | /* 12987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4909 | /* 12993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4910 | /* 12996 */ GIR_RootConstrainSelectedInstOperands, |
| 4911 | /* 12997 */ // GIR_Coverage, 3870, |
| 4912 | /* 12997 */ GIR_EraseRootFromParent_Done, |
| 4913 | /* 12998 */ // Label 271: @12998 |
| 4914 | /* 12998 */ GIM_Reject, |
| 4915 | /* 12999 */ // Label 263: @12999 |
| 4916 | /* 12999 */ GIM_Reject, |
| 4917 | /* 13000 */ // Label 102: @13000 |
| 4918 | /* 13000 */ GIM_Reject, |
| 4919 | /* 13001 */ // Label 1: @13001 |
| 4920 | /* 13001 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 281*/ GIMT_Encode4(16244), |
| 4921 | /* 13012 */ /*GILLT_s32*//*Label 272*/ GIMT_Encode4(13072), |
| 4922 | /* 13016 */ /*GILLT_s64*//*Label 273*/ GIMT_Encode4(13686), GIMT_Encode4(0), |
| 4923 | /* 13024 */ /*GILLT_v2s32*//*Label 274*/ GIMT_Encode4(13733), |
| 4924 | /* 13028 */ /*GILLT_v2s64*//*Label 275*/ GIMT_Encode4(13848), GIMT_Encode4(0), |
| 4925 | /* 13036 */ /*GILLT_v4s16*//*Label 276*/ GIMT_Encode4(14400), |
| 4926 | /* 13040 */ /*GILLT_v4s32*//*Label 277*/ GIMT_Encode4(14515), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4927 | /* 13052 */ /*GILLT_v8s8*//*Label 278*/ GIMT_Encode4(15230), |
| 4928 | /* 13056 */ /*GILLT_v8s16*//*Label 279*/ GIMT_Encode4(15345), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4929 | /* 13068 */ /*GILLT_v16s8*//*Label 280*/ GIMT_Encode4(16060), |
| 4930 | /* 13072 */ // Label 272: @13072 |
| 4931 | /* 13072 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(13685), |
| 4932 | /* 13077 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4933 | /* 13080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4934 | /* 13083 */ GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(13127), // Rule ID 329 // |
| 4935 | /* 13088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 4936 | /* 13091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4937 | /* 13095 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 4938 | /* 13099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4939 | /* 13103 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 4940 | /* 13103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB), |
| 4941 | /* 13106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4942 | /* 13108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 4943 | /* 13114 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4944 | /* 13116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4945 | /* 13119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4946 | /* 13125 */ GIR_RootConstrainSelectedInstOperands, |
| 4947 | /* 13126 */ // GIR_Coverage, 329, |
| 4948 | /* 13126 */ GIR_EraseRootFromParent_Done, |
| 4949 | /* 13127 */ // Label 283: @13127 |
| 4950 | /* 13127 */ GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(13184), // Rule ID 95 // |
| 4951 | /* 13132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4952 | /* 13135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4953 | /* 13139 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4954 | /* 13143 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4955 | /* 13147 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4956 | /* 13151 */ // MIs[1] Operand 1 |
| 4957 | /* 13151 */ // No operand predicates |
| 4958 | /* 13151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4959 | /* 13155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4960 | /* 13157 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4961 | /* 13157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri), |
| 4962 | /* 13160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4963 | /* 13162 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4964 | /* 13164 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4965 | /* 13167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4966 | /* 13170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4967 | /* 13176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4968 | /* 13182 */ GIR_RootConstrainSelectedInstOperands, |
| 4969 | /* 13183 */ // GIR_Coverage, 95, |
| 4970 | /* 13183 */ GIR_EraseRootFromParent_Done, |
| 4971 | /* 13184 */ // Label 284: @13184 |
| 4972 | /* 13184 */ GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(13241), // Rule ID 426 // |
| 4973 | /* 13189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4974 | /* 13192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4975 | /* 13196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4976 | /* 13200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4977 | /* 13204 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4978 | /* 13208 */ // MIs[1] Operand 1 |
| 4979 | /* 13208 */ // No operand predicates |
| 4980 | /* 13208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4981 | /* 13212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4982 | /* 13214 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4983 | /* 13214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri), |
| 4984 | /* 13217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4985 | /* 13219 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4986 | /* 13221 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4987 | /* 13224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4988 | /* 13227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4989 | /* 13233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4990 | /* 13239 */ GIR_RootConstrainSelectedInstOperands, |
| 4991 | /* 13240 */ // GIR_Coverage, 426, |
| 4992 | /* 13240 */ GIR_EraseRootFromParent_Done, |
| 4993 | /* 13241 */ // Label 285: @13241 |
| 4994 | /* 13241 */ GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(13298), // Rule ID 75 // |
| 4995 | /* 13246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4996 | /* 13249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4997 | /* 13253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4998 | /* 13257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4999 | /* 13261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5000 | /* 13265 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 5001 | /* 13269 */ // MIs[1] Operand 1 |
| 5002 | /* 13269 */ // No operand predicates |
| 5003 | /* 13269 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5004 | /* 13271 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5005 | /* 13271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri), |
| 5006 | /* 13274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5007 | /* 13276 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5008 | /* 13278 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 5009 | /* 13281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5010 | /* 13284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5011 | /* 13290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5012 | /* 13296 */ GIR_RootConstrainSelectedInstOperands, |
| 5013 | /* 13297 */ // GIR_Coverage, 75, |
| 5014 | /* 13297 */ GIR_EraseRootFromParent_Done, |
| 5015 | /* 13298 */ // Label 286: @13298 |
| 5016 | /* 13298 */ GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(13355), // Rule ID 410 // |
| 5017 | /* 13303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5018 | /* 13306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5019 | /* 13310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5020 | /* 13314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5021 | /* 13318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5022 | /* 13322 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 5023 | /* 13326 */ // MIs[1] Operand 1 |
| 5024 | /* 13326 */ // No operand predicates |
| 5025 | /* 13326 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5026 | /* 13328 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5027 | /* 13328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri), |
| 5028 | /* 13331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5029 | /* 13333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5030 | /* 13335 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 5031 | /* 13338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5032 | /* 13341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5033 | /* 13347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5034 | /* 13353 */ GIR_RootConstrainSelectedInstOperands, |
| 5035 | /* 13354 */ // GIR_Coverage, 410, |
| 5036 | /* 13354 */ GIR_EraseRootFromParent_Done, |
| 5037 | /* 13355 */ // Label 287: @13355 |
| 5038 | /* 13355 */ GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(13406), // Rule ID 411 // |
| 5039 | /* 13360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5040 | /* 13363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5041 | /* 13367 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5042 | /* 13371 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5043 | /* 13375 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5044 | /* 13379 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 5045 | /* 13383 */ // MIs[1] Operand 1 |
| 5046 | /* 13383 */ // No operand predicates |
| 5047 | /* 13383 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5048 | /* 13385 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5049 | /* 13385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12), |
| 5050 | /* 13388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5051 | /* 13390 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5052 | /* 13392 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 5053 | /* 13395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5054 | /* 13398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5055 | /* 13404 */ GIR_RootConstrainSelectedInstOperands, |
| 5056 | /* 13405 */ // GIR_Coverage, 411, |
| 5057 | /* 13405 */ GIR_EraseRootFromParent_Done, |
| 5058 | /* 13406 */ // Label 288: @13406 |
| 5059 | /* 13406 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(13476), // Rule ID 172 // |
| 5060 | /* 13411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), |
| 5061 | /* 13414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5062 | /* 13418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5063 | /* 13422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5064 | /* 13426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5065 | /* 13430 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5066 | /* 13434 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5067 | /* 13438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5068 | /* 13443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5069 | /* 13448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5070 | /* 13450 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 5071 | /* 13450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS), |
| 5072 | /* 13453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5073 | /* 13455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5074 | /* 13459 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 5075 | /* 13463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 5076 | /* 13465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5077 | /* 13468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5078 | /* 13474 */ GIR_RootConstrainSelectedInstOperands, |
| 5079 | /* 13475 */ // GIR_Coverage, 172, |
| 5080 | /* 13475 */ GIR_EraseRootFromParent_Done, |
| 5081 | /* 13476 */ // Label 289: @13476 |
| 5082 | /* 13476 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(13546), // Rule ID 503 // |
| 5083 | /* 13481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 5084 | /* 13484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5085 | /* 13488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5086 | /* 13492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5087 | /* 13496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5088 | /* 13500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5089 | /* 13504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5090 | /* 13508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5091 | /* 13513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5092 | /* 13518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5093 | /* 13520 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 5094 | /* 13520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS), |
| 5095 | /* 13523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5096 | /* 13525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5097 | /* 13529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 5098 | /* 13533 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 5099 | /* 13535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5100 | /* 13538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5101 | /* 13544 */ GIR_RootConstrainSelectedInstOperands, |
| 5102 | /* 13545 */ // GIR_Coverage, 503, |
| 5103 | /* 13545 */ GIR_EraseRootFromParent_Done, |
| 5104 | /* 13546 */ // Label 290: @13546 |
| 5105 | /* 13546 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(13592), // Rule ID 76 // |
| 5106 | /* 13551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 5107 | /* 13554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5108 | /* 13558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5109 | /* 13562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5110 | /* 13566 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5111 | /* 13566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr), |
| 5112 | /* 13569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5113 | /* 13571 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5114 | /* 13573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5115 | /* 13575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5116 | /* 13578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5117 | /* 13584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5118 | /* 13590 */ GIR_RootConstrainSelectedInstOperands, |
| 5119 | /* 13591 */ // GIR_Coverage, 76, |
| 5120 | /* 13591 */ GIR_EraseRootFromParent_Done, |
| 5121 | /* 13592 */ // Label 291: @13592 |
| 5122 | /* 13592 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(13638), // Rule ID 332 // |
| 5123 | /* 13597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 5124 | /* 13600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 5125 | /* 13604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 5126 | /* 13608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 5127 | /* 13612 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 5128 | /* 13612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr), |
| 5129 | /* 13615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5130 | /* 13617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 5131 | /* 13623 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5132 | /* 13625 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5133 | /* 13627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5134 | /* 13630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5135 | /* 13636 */ GIR_RootConstrainSelectedInstOperands, |
| 5136 | /* 13637 */ // GIR_Coverage, 332, |
| 5137 | /* 13637 */ GIR_EraseRootFromParent_Done, |
| 5138 | /* 13638 */ // Label 292: @13638 |
| 5139 | /* 13638 */ GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(13684), // Rule ID 412 // |
| 5140 | /* 13643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5141 | /* 13646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5142 | /* 13650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5143 | /* 13654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5144 | /* 13658 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5145 | /* 13658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr), |
| 5146 | /* 13661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5147 | /* 13663 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5148 | /* 13665 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5149 | /* 13667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5150 | /* 13670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5151 | /* 13676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5152 | /* 13682 */ GIR_RootConstrainSelectedInstOperands, |
| 5153 | /* 13683 */ // GIR_Coverage, 412, |
| 5154 | /* 13683 */ GIR_EraseRootFromParent_Done, |
| 5155 | /* 13684 */ // Label 293: @13684 |
| 5156 | /* 13684 */ GIM_Reject, |
| 5157 | /* 13685 */ // Label 282: @13685 |
| 5158 | /* 13685 */ GIM_Reject, |
| 5159 | /* 13686 */ // Label 273: @13686 |
| 5160 | /* 13686 */ GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(13732), // Rule ID 1127 // |
| 5161 | /* 13691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5162 | /* 13694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 5163 | /* 13697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5164 | /* 13700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5165 | /* 13704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5166 | /* 13708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5167 | /* 13712 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 5168 | /* 13712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64), |
| 5169 | /* 13715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5170 | /* 13717 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5171 | /* 13719 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5172 | /* 13721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5173 | /* 13724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5174 | /* 13730 */ GIR_RootConstrainSelectedInstOperands, |
| 5175 | /* 13731 */ // GIR_Coverage, 1127, |
| 5176 | /* 13731 */ GIR_EraseRootFromParent_Done, |
| 5177 | /* 13732 */ // Label 294: @13732 |
| 5178 | /* 13732 */ GIM_Reject, |
| 5179 | /* 13733 */ // Label 274: @13733 |
| 5180 | /* 13733 */ GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(13847), |
| 5181 | /* 13738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5182 | /* 13741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5183 | /* 13744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5184 | /* 13748 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5185 | /* 13752 */ GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(13814), // Rule ID 1054 // |
| 5186 | /* 13757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5187 | /* 13760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5188 | /* 13764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5189 | /* 13768 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5190 | /* 13772 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5191 | /* 13776 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5192 | /* 13781 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5193 | /* 13786 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5194 | /* 13788 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5195 | /* 13788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32), |
| 5196 | /* 13791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5197 | /* 13793 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5198 | /* 13795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5199 | /* 13799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5200 | /* 13803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5201 | /* 13806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5202 | /* 13812 */ GIR_RootConstrainSelectedInstOperands, |
| 5203 | /* 13813 */ // GIR_Coverage, 1054, |
| 5204 | /* 13813 */ GIR_EraseRootFromParent_Done, |
| 5205 | /* 13814 */ // Label 296: @13814 |
| 5206 | /* 13814 */ GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(13846), // Rule ID 1123 // |
| 5207 | /* 13819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5208 | /* 13822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5209 | /* 13826 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5210 | /* 13826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32), |
| 5211 | /* 13829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5212 | /* 13831 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5213 | /* 13833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5214 | /* 13835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5215 | /* 13838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5216 | /* 13844 */ GIR_RootConstrainSelectedInstOperands, |
| 5217 | /* 13845 */ // GIR_Coverage, 1123, |
| 5218 | /* 13845 */ GIR_EraseRootFromParent_Done, |
| 5219 | /* 13846 */ // Label 297: @13846 |
| 5220 | /* 13846 */ GIM_Reject, |
| 5221 | /* 13847 */ // Label 295: @13847 |
| 5222 | /* 13847 */ GIM_Reject, |
| 5223 | /* 13848 */ // Label 275: @13848 |
| 5224 | /* 13848 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(14399), |
| 5225 | /* 13853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 5226 | /* 13856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5227 | /* 13859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5228 | /* 13863 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(13931), // Rule ID 1147 // |
| 5229 | /* 13868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5230 | /* 13871 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5231 | /* 13875 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5232 | /* 13879 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5233 | /* 13883 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5234 | /* 13888 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5235 | /* 13892 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5236 | /* 13896 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5237 | /* 13900 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5238 | /* 13905 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5239 | /* 13907 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5240 | /* 13907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5241 | /* 13910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5242 | /* 13912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5243 | /* 13916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5244 | /* 13920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5245 | /* 13923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5246 | /* 13929 */ GIR_RootConstrainSelectedInstOperands, |
| 5247 | /* 13930 */ // GIR_Coverage, 1147, |
| 5248 | /* 13930 */ GIR_EraseRootFromParent_Done, |
| 5249 | /* 13931 */ // Label 299: @13931 |
| 5250 | /* 13931 */ GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(13999), // Rule ID 1146 // |
| 5251 | /* 13936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5252 | /* 13939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5253 | /* 13943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5254 | /* 13947 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5255 | /* 13951 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5256 | /* 13956 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5257 | /* 13960 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5258 | /* 13964 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5259 | /* 13968 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5260 | /* 13973 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5261 | /* 13975 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5262 | /* 13975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5263 | /* 13978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5264 | /* 13980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5265 | /* 13984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5266 | /* 13988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5267 | /* 13991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5268 | /* 13997 */ GIR_RootConstrainSelectedInstOperands, |
| 5269 | /* 13998 */ // GIR_Coverage, 1146, |
| 5270 | /* 13998 */ GIR_EraseRootFromParent_Done, |
| 5271 | /* 13999 */ // Label 300: @13999 |
| 5272 | /* 13999 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(14067), // Rule ID 1135 // |
| 5273 | /* 14004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5274 | /* 14007 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5275 | /* 14011 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5276 | /* 14015 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5277 | /* 14019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5278 | /* 14024 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5279 | /* 14028 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5280 | /* 14032 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5281 | /* 14036 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5282 | /* 14041 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5283 | /* 14043 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5284 | /* 14043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64), |
| 5285 | /* 14046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5286 | /* 14048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5287 | /* 14052 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5288 | /* 14056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5289 | /* 14059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5290 | /* 14065 */ GIR_RootConstrainSelectedInstOperands, |
| 5291 | /* 14066 */ // GIR_Coverage, 1135, |
| 5292 | /* 14066 */ GIR_EraseRootFromParent_Done, |
| 5293 | /* 14067 */ // Label 301: @14067 |
| 5294 | /* 14067 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(14135), // Rule ID 1145 // |
| 5295 | /* 14072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5296 | /* 14075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5297 | /* 14079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5298 | /* 14083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5299 | /* 14087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5300 | /* 14092 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5301 | /* 14096 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5302 | /* 14100 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5303 | /* 14104 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5304 | /* 14109 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5305 | /* 14111 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5306 | /* 14111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5307 | /* 14114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5308 | /* 14116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5309 | /* 14120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5310 | /* 14124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5311 | /* 14127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5312 | /* 14133 */ GIR_RootConstrainSelectedInstOperands, |
| 5313 | /* 14134 */ // GIR_Coverage, 1145, |
| 5314 | /* 14134 */ GIR_EraseRootFromParent_Done, |
| 5315 | /* 14135 */ // Label 302: @14135 |
| 5316 | /* 14135 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(14203), // Rule ID 1144 // |
| 5317 | /* 14140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5318 | /* 14143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5319 | /* 14147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5320 | /* 14151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5321 | /* 14155 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5322 | /* 14160 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5323 | /* 14164 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5324 | /* 14168 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5325 | /* 14172 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5326 | /* 14177 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5327 | /* 14179 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5328 | /* 14179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5329 | /* 14182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5330 | /* 14184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5331 | /* 14188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5332 | /* 14192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5333 | /* 14195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5334 | /* 14201 */ GIR_RootConstrainSelectedInstOperands, |
| 5335 | /* 14202 */ // GIR_Coverage, 1144, |
| 5336 | /* 14202 */ GIR_EraseRootFromParent_Done, |
| 5337 | /* 14203 */ // Label 303: @14203 |
| 5338 | /* 14203 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(14256), // Rule ID 1156 // |
| 5339 | /* 14208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5340 | /* 14211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5341 | /* 14215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5342 | /* 14219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5343 | /* 14223 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5344 | /* 14227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5345 | /* 14232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5346 | /* 14234 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5347 | /* 14234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 5348 | /* 14237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5349 | /* 14239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5350 | /* 14241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5351 | /* 14245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5352 | /* 14248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5353 | /* 14254 */ GIR_RootConstrainSelectedInstOperands, |
| 5354 | /* 14255 */ // GIR_Coverage, 1156, |
| 5355 | /* 14255 */ GIR_EraseRootFromParent_Done, |
| 5356 | /* 14256 */ // Label 304: @14256 |
| 5357 | /* 14256 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(14309), // Rule ID 1150 // |
| 5358 | /* 14261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5359 | /* 14264 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5360 | /* 14268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5361 | /* 14272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5362 | /* 14276 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5363 | /* 14280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5364 | /* 14285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5365 | /* 14287 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5366 | /* 14287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64), |
| 5367 | /* 14290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5368 | /* 14292 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5369 | /* 14294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5370 | /* 14298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5371 | /* 14301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5372 | /* 14307 */ GIR_RootConstrainSelectedInstOperands, |
| 5373 | /* 14308 */ // GIR_Coverage, 1150, |
| 5374 | /* 14308 */ GIR_EraseRootFromParent_Done, |
| 5375 | /* 14309 */ // Label 305: @14309 |
| 5376 | /* 14309 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(14362), // Rule ID 1155 // |
| 5377 | /* 14314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5378 | /* 14317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5379 | /* 14321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5380 | /* 14325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5381 | /* 14329 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5382 | /* 14333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5383 | /* 14338 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5384 | /* 14340 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5385 | /* 14340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 5386 | /* 14343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5387 | /* 14345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5388 | /* 14347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5389 | /* 14351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5390 | /* 14354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5391 | /* 14360 */ GIR_RootConstrainSelectedInstOperands, |
| 5392 | /* 14361 */ // GIR_Coverage, 1155, |
| 5393 | /* 14361 */ GIR_EraseRootFromParent_Done, |
| 5394 | /* 14362 */ // Label 306: @14362 |
| 5395 | /* 14362 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(14398), // Rule ID 1128 // |
| 5396 | /* 14367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5397 | /* 14370 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5398 | /* 14374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5399 | /* 14378 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 5400 | /* 14378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64), |
| 5401 | /* 14381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5402 | /* 14383 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5403 | /* 14385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5404 | /* 14387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5405 | /* 14390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5406 | /* 14396 */ GIR_RootConstrainSelectedInstOperands, |
| 5407 | /* 14397 */ // GIR_Coverage, 1128, |
| 5408 | /* 14397 */ GIR_EraseRootFromParent_Done, |
| 5409 | /* 14398 */ // Label 307: @14398 |
| 5410 | /* 14398 */ GIM_Reject, |
| 5411 | /* 14399 */ // Label 298: @14399 |
| 5412 | /* 14399 */ GIM_Reject, |
| 5413 | /* 14400 */ // Label 276: @14400 |
| 5414 | /* 14400 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(14514), |
| 5415 | /* 14405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5416 | /* 14408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5417 | /* 14411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5418 | /* 14415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5419 | /* 14419 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(14481), // Rule ID 1053 // |
| 5420 | /* 14424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5421 | /* 14427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5422 | /* 14431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5423 | /* 14435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5424 | /* 14439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5425 | /* 14443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5426 | /* 14448 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5427 | /* 14453 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5428 | /* 14455 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5429 | /* 14455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16), |
| 5430 | /* 14458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5431 | /* 14460 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5432 | /* 14462 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5433 | /* 14466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5434 | /* 14470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5435 | /* 14473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5436 | /* 14479 */ GIR_RootConstrainSelectedInstOperands, |
| 5437 | /* 14480 */ // GIR_Coverage, 1053, |
| 5438 | /* 14480 */ GIR_EraseRootFromParent_Done, |
| 5439 | /* 14481 */ // Label 309: @14481 |
| 5440 | /* 14481 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(14513), // Rule ID 1122 // |
| 5441 | /* 14486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5442 | /* 14489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5443 | /* 14493 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5444 | /* 14493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16), |
| 5445 | /* 14496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5446 | /* 14498 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5447 | /* 14500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5448 | /* 14502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5449 | /* 14505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5450 | /* 14511 */ GIR_RootConstrainSelectedInstOperands, |
| 5451 | /* 14512 */ // GIR_Coverage, 1122, |
| 5452 | /* 14512 */ GIR_EraseRootFromParent_Done, |
| 5453 | /* 14513 */ // Label 310: @14513 |
| 5454 | /* 14513 */ GIM_Reject, |
| 5455 | /* 14514 */ // Label 308: @14514 |
| 5456 | /* 14514 */ GIM_Reject, |
| 5457 | /* 14515 */ // Label 277: @14515 |
| 5458 | /* 14515 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(15229), |
| 5459 | /* 14520 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5460 | /* 14523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5461 | /* 14526 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(14598), // Rule ID 1143 // |
| 5462 | /* 14531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5463 | /* 14534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5464 | /* 14538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5465 | /* 14542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5466 | /* 14546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5467 | /* 14550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5468 | /* 14555 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5469 | /* 14559 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5470 | /* 14563 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5471 | /* 14567 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5472 | /* 14572 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5473 | /* 14574 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5474 | /* 14574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5475 | /* 14577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5476 | /* 14579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5477 | /* 14583 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5478 | /* 14587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5479 | /* 14590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5480 | /* 14596 */ GIR_RootConstrainSelectedInstOperands, |
| 5481 | /* 14597 */ // GIR_Coverage, 1143, |
| 5482 | /* 14597 */ GIR_EraseRootFromParent_Done, |
| 5483 | /* 14598 */ // Label 312: @14598 |
| 5484 | /* 14598 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(14670), // Rule ID 1142 // |
| 5485 | /* 14603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5486 | /* 14606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5487 | /* 14610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5488 | /* 14614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5489 | /* 14618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5490 | /* 14622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5491 | /* 14627 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5492 | /* 14631 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5493 | /* 14635 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5494 | /* 14639 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5495 | /* 14644 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5496 | /* 14646 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5497 | /* 14646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5498 | /* 14649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5499 | /* 14651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5500 | /* 14655 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5501 | /* 14659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5502 | /* 14662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5503 | /* 14668 */ GIR_RootConstrainSelectedInstOperands, |
| 5504 | /* 14669 */ // GIR_Coverage, 1142, |
| 5505 | /* 14669 */ GIR_EraseRootFromParent_Done, |
| 5506 | /* 14670 */ // Label 313: @14670 |
| 5507 | /* 14670 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(14742), // Rule ID 1134 // |
| 5508 | /* 14675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5509 | /* 14678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5510 | /* 14682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5511 | /* 14686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5512 | /* 14690 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5513 | /* 14694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5514 | /* 14699 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5515 | /* 14703 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5516 | /* 14707 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5517 | /* 14711 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5518 | /* 14716 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5519 | /* 14718 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5520 | /* 14718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32), |
| 5521 | /* 14721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5522 | /* 14723 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5523 | /* 14727 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5524 | /* 14731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5525 | /* 14734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5526 | /* 14740 */ GIR_RootConstrainSelectedInstOperands, |
| 5527 | /* 14741 */ // GIR_Coverage, 1134, |
| 5528 | /* 14741 */ GIR_EraseRootFromParent_Done, |
| 5529 | /* 14742 */ // Label 314: @14742 |
| 5530 | /* 14742 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(14814), // Rule ID 1141 // |
| 5531 | /* 14747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5532 | /* 14750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5533 | /* 14754 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5534 | /* 14758 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5535 | /* 14762 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5536 | /* 14766 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5537 | /* 14771 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5538 | /* 14775 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5539 | /* 14779 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5540 | /* 14783 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5541 | /* 14788 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5542 | /* 14790 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5543 | /* 14790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5544 | /* 14793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5545 | /* 14795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5546 | /* 14799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5547 | /* 14803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5548 | /* 14806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5549 | /* 14812 */ GIR_RootConstrainSelectedInstOperands, |
| 5550 | /* 14813 */ // GIR_Coverage, 1141, |
| 5551 | /* 14813 */ GIR_EraseRootFromParent_Done, |
| 5552 | /* 14814 */ // Label 315: @14814 |
| 5553 | /* 14814 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(14886), // Rule ID 1140 // |
| 5554 | /* 14819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5555 | /* 14822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5556 | /* 14826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5557 | /* 14830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5558 | /* 14834 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5559 | /* 14838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5560 | /* 14843 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5561 | /* 14847 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5562 | /* 14851 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5563 | /* 14855 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5564 | /* 14860 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5565 | /* 14862 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5566 | /* 14862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5567 | /* 14865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5568 | /* 14867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5569 | /* 14871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5570 | /* 14875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5571 | /* 14878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5572 | /* 14884 */ GIR_RootConstrainSelectedInstOperands, |
| 5573 | /* 14885 */ // GIR_Coverage, 1140, |
| 5574 | /* 14885 */ GIR_EraseRootFromParent_Done, |
| 5575 | /* 14886 */ // Label 316: @14886 |
| 5576 | /* 14886 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(14956), // Rule ID 1057 // |
| 5577 | /* 14891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5578 | /* 14894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5579 | /* 14898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5580 | /* 14902 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5581 | /* 14906 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5582 | /* 14910 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5583 | /* 14914 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5584 | /* 14918 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5585 | /* 14923 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5586 | /* 14928 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5587 | /* 14930 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5588 | /* 14930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32), |
| 5589 | /* 14933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5590 | /* 14935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5591 | /* 14937 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5592 | /* 14941 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5593 | /* 14945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5594 | /* 14948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5595 | /* 14954 */ GIR_RootConstrainSelectedInstOperands, |
| 5596 | /* 14955 */ // GIR_Coverage, 1057, |
| 5597 | /* 14955 */ GIR_EraseRootFromParent_Done, |
| 5598 | /* 14956 */ // Label 317: @14956 |
| 5599 | /* 14956 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(15013), // Rule ID 1154 // |
| 5600 | /* 14961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5601 | /* 14964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5602 | /* 14968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5603 | /* 14972 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5604 | /* 14976 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5605 | /* 14980 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5606 | /* 14984 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5607 | /* 14989 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5608 | /* 14991 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5609 | /* 14991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 5610 | /* 14994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5611 | /* 14996 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5612 | /* 14998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5613 | /* 15002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5614 | /* 15005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5615 | /* 15011 */ GIR_RootConstrainSelectedInstOperands, |
| 5616 | /* 15012 */ // GIR_Coverage, 1154, |
| 5617 | /* 15012 */ GIR_EraseRootFromParent_Done, |
| 5618 | /* 15013 */ // Label 318: @15013 |
| 5619 | /* 15013 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(15070), // Rule ID 1149 // |
| 5620 | /* 15018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5621 | /* 15021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5622 | /* 15025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5623 | /* 15029 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5624 | /* 15033 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5625 | /* 15037 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5626 | /* 15041 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5627 | /* 15046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5628 | /* 15048 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5629 | /* 15048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32), |
| 5630 | /* 15051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5631 | /* 15053 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5632 | /* 15055 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5633 | /* 15059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5634 | /* 15062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5635 | /* 15068 */ GIR_RootConstrainSelectedInstOperands, |
| 5636 | /* 15069 */ // GIR_Coverage, 1149, |
| 5637 | /* 15069 */ GIR_EraseRootFromParent_Done, |
| 5638 | /* 15070 */ // Label 319: @15070 |
| 5639 | /* 15070 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(15127), // Rule ID 1153 // |
| 5640 | /* 15075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5641 | /* 15078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5642 | /* 15082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5643 | /* 15086 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5644 | /* 15090 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5645 | /* 15094 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5646 | /* 15098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5647 | /* 15103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5648 | /* 15105 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5649 | /* 15105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 5650 | /* 15108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5651 | /* 15110 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5652 | /* 15112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5653 | /* 15116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5654 | /* 15119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5655 | /* 15125 */ GIR_RootConstrainSelectedInstOperands, |
| 5656 | /* 15126 */ // GIR_Coverage, 1153, |
| 5657 | /* 15126 */ GIR_EraseRootFromParent_Done, |
| 5658 | /* 15127 */ // Label 320: @15127 |
| 5659 | /* 15127 */ GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(15167), // Rule ID 1126 // |
| 5660 | /* 15132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5661 | /* 15135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5662 | /* 15139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5663 | /* 15143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5664 | /* 15147 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5665 | /* 15147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32), |
| 5666 | /* 15150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5667 | /* 15152 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5668 | /* 15154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5669 | /* 15156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5670 | /* 15159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5671 | /* 15165 */ GIR_RootConstrainSelectedInstOperands, |
| 5672 | /* 15166 */ // GIR_Coverage, 1126, |
| 5673 | /* 15166 */ GIR_EraseRootFromParent_Done, |
| 5674 | /* 15167 */ // Label 321: @15167 |
| 5675 | /* 15167 */ GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(15228), // Rule ID 3890 // |
| 5676 | /* 15172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5677 | /* 15175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5678 | /* 15179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5679 | /* 15183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5680 | /* 15187 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 5681 | /* 15187 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5682 | /* 15190 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5683 | /* 15194 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5684 | /* 15199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32), |
| 5685 | /* 15202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5686 | /* 15204 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5687 | /* 15206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5688 | /* 15208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5689 | /* 15211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5690 | /* 15217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5691 | /* 15223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5692 | /* 15226 */ GIR_RootConstrainSelectedInstOperands, |
| 5693 | /* 15227 */ // GIR_Coverage, 3890, |
| 5694 | /* 15227 */ GIR_EraseRootFromParent_Done, |
| 5695 | /* 15228 */ // Label 322: @15228 |
| 5696 | /* 15228 */ GIM_Reject, |
| 5697 | /* 15229 */ // Label 311: @15229 |
| 5698 | /* 15229 */ GIM_Reject, |
| 5699 | /* 15230 */ // Label 278: @15230 |
| 5700 | /* 15230 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(15344), |
| 5701 | /* 15235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5702 | /* 15238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 5703 | /* 15241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5704 | /* 15245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5705 | /* 15249 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(15311), // Rule ID 1052 // |
| 5706 | /* 15254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5707 | /* 15257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5708 | /* 15261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5709 | /* 15265 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5710 | /* 15269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 5711 | /* 15273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5712 | /* 15278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5713 | /* 15283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5714 | /* 15285 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5715 | /* 15285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8), |
| 5716 | /* 15288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5717 | /* 15290 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5718 | /* 15292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5719 | /* 15296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5720 | /* 15300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5721 | /* 15303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5722 | /* 15309 */ GIR_RootConstrainSelectedInstOperands, |
| 5723 | /* 15310 */ // GIR_Coverage, 1052, |
| 5724 | /* 15310 */ GIR_EraseRootFromParent_Done, |
| 5725 | /* 15311 */ // Label 324: @15311 |
| 5726 | /* 15311 */ GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(15343), // Rule ID 1121 // |
| 5727 | /* 15316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5728 | /* 15319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5729 | /* 15323 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5730 | /* 15323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8), |
| 5731 | /* 15326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5732 | /* 15328 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5733 | /* 15330 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5734 | /* 15332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5735 | /* 15335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5736 | /* 15341 */ GIR_RootConstrainSelectedInstOperands, |
| 5737 | /* 15342 */ // GIR_Coverage, 1121, |
| 5738 | /* 15342 */ GIR_EraseRootFromParent_Done, |
| 5739 | /* 15343 */ // Label 325: @15343 |
| 5740 | /* 15343 */ GIM_Reject, |
| 5741 | /* 15344 */ // Label 323: @15344 |
| 5742 | /* 15344 */ GIM_Reject, |
| 5743 | /* 15345 */ // Label 279: @15345 |
| 5744 | /* 15345 */ GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(16059), |
| 5745 | /* 15350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5746 | /* 15353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5747 | /* 15356 */ GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(15428), // Rule ID 1139 // |
| 5748 | /* 15361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5749 | /* 15364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5750 | /* 15368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5751 | /* 15372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5752 | /* 15376 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5753 | /* 15380 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5754 | /* 15385 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5755 | /* 15389 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5756 | /* 15393 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5757 | /* 15397 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5758 | /* 15402 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5759 | /* 15404 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5760 | /* 15404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5761 | /* 15407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5762 | /* 15409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5763 | /* 15413 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5764 | /* 15417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5765 | /* 15420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5766 | /* 15426 */ GIR_RootConstrainSelectedInstOperands, |
| 5767 | /* 15427 */ // GIR_Coverage, 1139, |
| 5768 | /* 15427 */ GIR_EraseRootFromParent_Done, |
| 5769 | /* 15428 */ // Label 327: @15428 |
| 5770 | /* 15428 */ GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(15500), // Rule ID 1138 // |
| 5771 | /* 15433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5772 | /* 15436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5773 | /* 15440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5774 | /* 15444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5775 | /* 15448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5776 | /* 15452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5777 | /* 15457 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5778 | /* 15461 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5779 | /* 15465 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5780 | /* 15469 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5781 | /* 15474 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5782 | /* 15476 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5783 | /* 15476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5784 | /* 15479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5785 | /* 15481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5786 | /* 15485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5787 | /* 15489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5788 | /* 15492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5789 | /* 15498 */ GIR_RootConstrainSelectedInstOperands, |
| 5790 | /* 15499 */ // GIR_Coverage, 1138, |
| 5791 | /* 15499 */ GIR_EraseRootFromParent_Done, |
| 5792 | /* 15500 */ // Label 328: @15500 |
| 5793 | /* 15500 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(15572), // Rule ID 1133 // |
| 5794 | /* 15505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5795 | /* 15508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5796 | /* 15512 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5797 | /* 15516 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5798 | /* 15520 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5799 | /* 15524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5800 | /* 15529 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5801 | /* 15533 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5802 | /* 15537 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5803 | /* 15541 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5804 | /* 15546 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5805 | /* 15548 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5806 | /* 15548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16), |
| 5807 | /* 15551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5808 | /* 15553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5809 | /* 15557 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5810 | /* 15561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5811 | /* 15564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5812 | /* 15570 */ GIR_RootConstrainSelectedInstOperands, |
| 5813 | /* 15571 */ // GIR_Coverage, 1133, |
| 5814 | /* 15571 */ GIR_EraseRootFromParent_Done, |
| 5815 | /* 15572 */ // Label 329: @15572 |
| 5816 | /* 15572 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(15644), // Rule ID 1137 // |
| 5817 | /* 15577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5818 | /* 15580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5819 | /* 15584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5820 | /* 15588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5821 | /* 15592 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5822 | /* 15596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5823 | /* 15601 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5824 | /* 15605 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5825 | /* 15609 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5826 | /* 15613 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5827 | /* 15618 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5828 | /* 15620 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5829 | /* 15620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5830 | /* 15623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5831 | /* 15625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5832 | /* 15629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5833 | /* 15633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5834 | /* 15636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5835 | /* 15642 */ GIR_RootConstrainSelectedInstOperands, |
| 5836 | /* 15643 */ // GIR_Coverage, 1137, |
| 5837 | /* 15643 */ GIR_EraseRootFromParent_Done, |
| 5838 | /* 15644 */ // Label 330: @15644 |
| 5839 | /* 15644 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(15716), // Rule ID 1136 // |
| 5840 | /* 15649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5841 | /* 15652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5842 | /* 15656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5843 | /* 15660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5844 | /* 15664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5845 | /* 15668 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5846 | /* 15673 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5847 | /* 15677 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5848 | /* 15681 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5849 | /* 15685 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5850 | /* 15690 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5851 | /* 15692 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5852 | /* 15692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5853 | /* 15695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5854 | /* 15697 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5855 | /* 15701 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5856 | /* 15705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5857 | /* 15708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5858 | /* 15714 */ GIR_RootConstrainSelectedInstOperands, |
| 5859 | /* 15715 */ // GIR_Coverage, 1136, |
| 5860 | /* 15715 */ GIR_EraseRootFromParent_Done, |
| 5861 | /* 15716 */ // Label 331: @15716 |
| 5862 | /* 15716 */ GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(15786), // Rule ID 1056 // |
| 5863 | /* 15721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5864 | /* 15724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5865 | /* 15728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5866 | /* 15732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5867 | /* 15736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5868 | /* 15740 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5869 | /* 15744 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5870 | /* 15748 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5871 | /* 15753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5872 | /* 15758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5873 | /* 15760 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5874 | /* 15760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16), |
| 5875 | /* 15763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5876 | /* 15765 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5877 | /* 15767 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5878 | /* 15771 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5879 | /* 15775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5880 | /* 15778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5881 | /* 15784 */ GIR_RootConstrainSelectedInstOperands, |
| 5882 | /* 15785 */ // GIR_Coverage, 1056, |
| 5883 | /* 15785 */ GIR_EraseRootFromParent_Done, |
| 5884 | /* 15786 */ // Label 332: @15786 |
| 5885 | /* 15786 */ GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(15843), // Rule ID 1152 // |
| 5886 | /* 15791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5887 | /* 15794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5888 | /* 15798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5889 | /* 15802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5890 | /* 15806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5891 | /* 15810 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5892 | /* 15814 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5893 | /* 15819 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5894 | /* 15821 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5895 | /* 15821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5896 | /* 15824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5897 | /* 15826 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5898 | /* 15828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5899 | /* 15832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5900 | /* 15835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5901 | /* 15841 */ GIR_RootConstrainSelectedInstOperands, |
| 5902 | /* 15842 */ // GIR_Coverage, 1152, |
| 5903 | /* 15842 */ GIR_EraseRootFromParent_Done, |
| 5904 | /* 15843 */ // Label 333: @15843 |
| 5905 | /* 15843 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(15900), // Rule ID 1148 // |
| 5906 | /* 15848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5907 | /* 15851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5908 | /* 15855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5909 | /* 15859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5910 | /* 15863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5911 | /* 15867 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5912 | /* 15871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5913 | /* 15876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5914 | /* 15878 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5915 | /* 15878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16), |
| 5916 | /* 15881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5917 | /* 15883 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5918 | /* 15885 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5919 | /* 15889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5920 | /* 15892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5921 | /* 15898 */ GIR_RootConstrainSelectedInstOperands, |
| 5922 | /* 15899 */ // GIR_Coverage, 1148, |
| 5923 | /* 15899 */ GIR_EraseRootFromParent_Done, |
| 5924 | /* 15900 */ // Label 334: @15900 |
| 5925 | /* 15900 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(15957), // Rule ID 1151 // |
| 5926 | /* 15905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5927 | /* 15908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5928 | /* 15912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5929 | /* 15916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5930 | /* 15920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5931 | /* 15924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5932 | /* 15928 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5933 | /* 15933 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5934 | /* 15935 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5935 | /* 15935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5936 | /* 15938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5937 | /* 15940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5938 | /* 15942 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5939 | /* 15946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5940 | /* 15949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5941 | /* 15955 */ GIR_RootConstrainSelectedInstOperands, |
| 5942 | /* 15956 */ // GIR_Coverage, 1151, |
| 5943 | /* 15956 */ GIR_EraseRootFromParent_Done, |
| 5944 | /* 15957 */ // Label 335: @15957 |
| 5945 | /* 15957 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(15997), // Rule ID 1125 // |
| 5946 | /* 15962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5947 | /* 15965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5948 | /* 15969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5949 | /* 15973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5950 | /* 15977 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5951 | /* 15977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16), |
| 5952 | /* 15980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5953 | /* 15982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5954 | /* 15984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5955 | /* 15986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5956 | /* 15989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5957 | /* 15995 */ GIR_RootConstrainSelectedInstOperands, |
| 5958 | /* 15996 */ // GIR_Coverage, 1125, |
| 5959 | /* 15996 */ GIR_EraseRootFromParent_Done, |
| 5960 | /* 15997 */ // Label 336: @15997 |
| 5961 | /* 15997 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(16058), // Rule ID 3886 // |
| 5962 | /* 16002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5963 | /* 16005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5964 | /* 16009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5965 | /* 16013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5966 | /* 16017 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 5967 | /* 16017 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5968 | /* 16020 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5969 | /* 16024 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5970 | /* 16029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16), |
| 5971 | /* 16032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5972 | /* 16034 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5973 | /* 16036 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5974 | /* 16038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5975 | /* 16041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5976 | /* 16047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5977 | /* 16053 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5978 | /* 16056 */ GIR_RootConstrainSelectedInstOperands, |
| 5979 | /* 16057 */ // GIR_Coverage, 3886, |
| 5980 | /* 16057 */ GIR_EraseRootFromParent_Done, |
| 5981 | /* 16058 */ // Label 337: @16058 |
| 5982 | /* 16058 */ GIM_Reject, |
| 5983 | /* 16059 */ // Label 326: @16059 |
| 5984 | /* 16059 */ GIM_Reject, |
| 5985 | /* 16060 */ // Label 280: @16060 |
| 5986 | /* 16060 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(16243), |
| 5987 | /* 16065 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5988 | /* 16068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5989 | /* 16071 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(16141), // Rule ID 1055 // |
| 5990 | /* 16076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5991 | /* 16079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5992 | /* 16083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5993 | /* 16087 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5994 | /* 16091 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5995 | /* 16095 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5996 | /* 16099 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5997 | /* 16103 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5998 | /* 16108 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5999 | /* 16113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6000 | /* 16115 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 6001 | /* 16115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8), |
| 6002 | /* 16118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6003 | /* 16120 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 6004 | /* 16122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 6005 | /* 16126 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 6006 | /* 16130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6007 | /* 16133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6008 | /* 16139 */ GIR_RootConstrainSelectedInstOperands, |
| 6009 | /* 16140 */ // GIR_Coverage, 1055, |
| 6010 | /* 16140 */ GIR_EraseRootFromParent_Done, |
| 6011 | /* 16141 */ // Label 339: @16141 |
| 6012 | /* 16141 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(16181), // Rule ID 1124 // |
| 6013 | /* 16146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6014 | /* 16149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6015 | /* 16153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6016 | /* 16157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6017 | /* 16161 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 6018 | /* 16161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8), |
| 6019 | /* 16164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6020 | /* 16166 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6021 | /* 16168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6022 | /* 16170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6023 | /* 16173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6024 | /* 16179 */ GIR_RootConstrainSelectedInstOperands, |
| 6025 | /* 16180 */ // GIR_Coverage, 1124, |
| 6026 | /* 16180 */ GIR_EraseRootFromParent_Done, |
| 6027 | /* 16181 */ // Label 340: @16181 |
| 6028 | /* 16181 */ GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(16242), // Rule ID 3882 // |
| 6029 | /* 16186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6030 | /* 16189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6031 | /* 16193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6032 | /* 16197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6033 | /* 16201 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 6034 | /* 16201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6035 | /* 16204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6036 | /* 16208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6037 | /* 16213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8), |
| 6038 | /* 16216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6039 | /* 16218 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6040 | /* 16220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6041 | /* 16222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6042 | /* 16225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6043 | /* 16231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6044 | /* 16237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6045 | /* 16240 */ GIR_RootConstrainSelectedInstOperands, |
| 6046 | /* 16241 */ // GIR_Coverage, 3882, |
| 6047 | /* 16241 */ GIR_EraseRootFromParent_Done, |
| 6048 | /* 16242 */ // Label 341: @16242 |
| 6049 | /* 16242 */ GIM_Reject, |
| 6050 | /* 16243 */ // Label 338: @16243 |
| 6051 | /* 16243 */ GIM_Reject, |
| 6052 | /* 16244 */ // Label 281: @16244 |
| 6053 | /* 16244 */ GIM_Reject, |
| 6054 | /* 16245 */ // Label 2: @16245 |
| 6055 | /* 16245 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 349*/ GIMT_Encode4(17948), |
| 6056 | /* 16256 */ /*GILLT_s32*//*Label 342*/ GIMT_Encode4(16316), GIMT_Encode4(0), GIMT_Encode4(0), |
| 6057 | /* 16268 */ /*GILLT_v2s32*//*Label 343*/ GIMT_Encode4(17235), GIMT_Encode4(0), GIMT_Encode4(0), |
| 6058 | /* 16280 */ /*GILLT_v4s16*//*Label 344*/ GIMT_Encode4(17282), |
| 6059 | /* 16284 */ /*GILLT_v4s32*//*Label 345*/ GIMT_Encode4(17329), GIMT_Encode4(0), GIMT_Encode4(0), |
| 6060 | /* 16296 */ /*GILLT_v8s8*//*Label 346*/ GIMT_Encode4(17558), |
| 6061 | /* 16300 */ /*GILLT_v8s16*//*Label 347*/ GIMT_Encode4(17605), GIMT_Encode4(0), GIMT_Encode4(0), |
| 6062 | /* 16312 */ /*GILLT_v16s8*//*Label 348*/ GIMT_Encode4(17834), |
| 6063 | /* 16316 */ // Label 342: @16316 |
| 6064 | /* 16316 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(17234), |
| 6065 | /* 16321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6066 | /* 16324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6067 | /* 16327 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(16415), // Rule ID 185 // |
| 6068 | /* 16332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 6069 | /* 16335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6070 | /* 16339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6071 | /* 16343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6072 | /* 16347 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6073 | /* 16351 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6074 | /* 16355 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6075 | /* 16360 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 6076 | /* 16364 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6077 | /* 16368 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6078 | /* 16372 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6079 | /* 16376 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6080 | /* 16380 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6081 | /* 16385 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 6082 | /* 16389 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6083 | /* 16391 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6084 | /* 16391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 6085 | /* 16394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6086 | /* 16396 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6087 | /* 16400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6088 | /* 16404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6089 | /* 16407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6090 | /* 16413 */ GIR_RootConstrainSelectedInstOperands, |
| 6091 | /* 16414 */ // GIR_Coverage, 185, |
| 6092 | /* 16414 */ GIR_EraseRootFromParent_Done, |
| 6093 | /* 16415 */ // Label 351: @16415 |
| 6094 | /* 16415 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(16503), // Rule ID 514 // |
| 6095 | /* 16420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6096 | /* 16423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6097 | /* 16427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6098 | /* 16431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6099 | /* 16435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6100 | /* 16439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6101 | /* 16443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6102 | /* 16448 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 6103 | /* 16452 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6104 | /* 16456 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6105 | /* 16460 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6106 | /* 16464 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6107 | /* 16468 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6108 | /* 16473 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 6109 | /* 16477 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6110 | /* 16479 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6111 | /* 16479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 6112 | /* 16482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6113 | /* 16484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6114 | /* 16488 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6115 | /* 16492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6116 | /* 16495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6117 | /* 16501 */ GIR_RootConstrainSelectedInstOperands, |
| 6118 | /* 16502 */ // GIR_Coverage, 514, |
| 6119 | /* 16502 */ GIR_EraseRootFromParent_Done, |
| 6120 | /* 16503 */ // Label 352: @16503 |
| 6121 | /* 16503 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(16594), // Rule ID 184 // |
| 6122 | /* 16508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 6123 | /* 16511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6124 | /* 16515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6125 | /* 16519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6126 | /* 16523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6127 | /* 16527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6128 | /* 16531 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6129 | /* 16536 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 6130 | /* 16540 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6131 | /* 16544 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6132 | /* 16548 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6133 | /* 16552 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6134 | /* 16557 */ // MIs[2] Operand 2 |
| 6135 | /* 16557 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6136 | /* 16568 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6137 | /* 16570 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6138 | /* 16570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 6139 | /* 16573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6140 | /* 16575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6141 | /* 16579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6142 | /* 16583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6143 | /* 16586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6144 | /* 16592 */ GIR_RootConstrainSelectedInstOperands, |
| 6145 | /* 16593 */ // GIR_Coverage, 184, |
| 6146 | /* 16593 */ GIR_EraseRootFromParent_Done, |
| 6147 | /* 16594 */ // Label 353: @16594 |
| 6148 | /* 16594 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(16685), // Rule ID 513 // |
| 6149 | /* 16599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6150 | /* 16602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6151 | /* 16606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6152 | /* 16610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6153 | /* 16614 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6154 | /* 16618 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6155 | /* 16622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6156 | /* 16627 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 6157 | /* 16631 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6158 | /* 16635 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6159 | /* 16639 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6160 | /* 16643 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6161 | /* 16648 */ // MIs[2] Operand 2 |
| 6162 | /* 16648 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6163 | /* 16659 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6164 | /* 16661 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6165 | /* 16661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 6166 | /* 16664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6167 | /* 16666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6168 | /* 16670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6169 | /* 16674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6170 | /* 16677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6171 | /* 16683 */ GIR_RootConstrainSelectedInstOperands, |
| 6172 | /* 16684 */ // GIR_Coverage, 513, |
| 6173 | /* 16684 */ GIR_EraseRootFromParent_Done, |
| 6174 | /* 16685 */ // Label 354: @16685 |
| 6175 | /* 16685 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(16776), // Rule ID 183 // |
| 6176 | /* 16690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 6177 | /* 16693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6178 | /* 16697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6179 | /* 16701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6180 | /* 16705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6181 | /* 16709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6182 | /* 16714 */ // MIs[1] Operand 2 |
| 6183 | /* 16714 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6184 | /* 16725 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6185 | /* 16729 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6186 | /* 16733 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6187 | /* 16737 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6188 | /* 16741 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6189 | /* 16746 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 6190 | /* 16750 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6191 | /* 16752 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6192 | /* 16752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 6193 | /* 16755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6194 | /* 16757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6195 | /* 16761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6196 | /* 16765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6197 | /* 16768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6198 | /* 16774 */ GIR_RootConstrainSelectedInstOperands, |
| 6199 | /* 16775 */ // GIR_Coverage, 183, |
| 6200 | /* 16775 */ GIR_EraseRootFromParent_Done, |
| 6201 | /* 16776 */ // Label 355: @16776 |
| 6202 | /* 16776 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(16867), // Rule ID 512 // |
| 6203 | /* 16781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6204 | /* 16784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6205 | /* 16788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6206 | /* 16792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6207 | /* 16796 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6208 | /* 16800 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6209 | /* 16805 */ // MIs[1] Operand 2 |
| 6210 | /* 16805 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6211 | /* 16816 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6212 | /* 16820 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6213 | /* 16824 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6214 | /* 16828 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6215 | /* 16832 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6216 | /* 16837 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 6217 | /* 16841 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6218 | /* 16843 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6219 | /* 16843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 6220 | /* 16846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6221 | /* 16848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6222 | /* 16852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6223 | /* 16856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6224 | /* 16859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6225 | /* 16865 */ GIR_RootConstrainSelectedInstOperands, |
| 6226 | /* 16866 */ // GIR_Coverage, 512, |
| 6227 | /* 16866 */ GIR_EraseRootFromParent_Done, |
| 6228 | /* 16867 */ // Label 356: @16867 |
| 6229 | /* 16867 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(16961), // Rule ID 182 // |
| 6230 | /* 16872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 6231 | /* 16875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6232 | /* 16879 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6233 | /* 16883 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6234 | /* 16887 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6235 | /* 16891 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6236 | /* 16896 */ // MIs[1] Operand 2 |
| 6237 | /* 16896 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6238 | /* 16907 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6239 | /* 16911 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6240 | /* 16915 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6241 | /* 16919 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6242 | /* 16924 */ // MIs[2] Operand 2 |
| 6243 | /* 16924 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6244 | /* 16935 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6245 | /* 16937 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6246 | /* 16937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 6247 | /* 16940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6248 | /* 16942 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6249 | /* 16946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6250 | /* 16950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6251 | /* 16953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6252 | /* 16959 */ GIR_RootConstrainSelectedInstOperands, |
| 6253 | /* 16960 */ // GIR_Coverage, 182, |
| 6254 | /* 16960 */ GIR_EraseRootFromParent_Done, |
| 6255 | /* 16961 */ // Label 357: @16961 |
| 6256 | /* 16961 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(17055), // Rule ID 511 // |
| 6257 | /* 16966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6258 | /* 16969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6259 | /* 16973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6260 | /* 16977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6261 | /* 16981 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6262 | /* 16985 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6263 | /* 16990 */ // MIs[1] Operand 2 |
| 6264 | /* 16990 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6265 | /* 17001 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6266 | /* 17005 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6267 | /* 17009 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6268 | /* 17013 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6269 | /* 17018 */ // MIs[2] Operand 2 |
| 6270 | /* 17018 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6271 | /* 17029 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6272 | /* 17031 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6273 | /* 17031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 6274 | /* 17034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6275 | /* 17036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6276 | /* 17040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6277 | /* 17044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6278 | /* 17047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6279 | /* 17053 */ GIR_RootConstrainSelectedInstOperands, |
| 6280 | /* 17054 */ // GIR_Coverage, 511, |
| 6281 | /* 17054 */ GIR_EraseRootFromParent_Done, |
| 6282 | /* 17055 */ // Label 358: @17055 |
| 6283 | /* 17055 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(17101), // Rule ID 168 // |
| 6284 | /* 17060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6285 | /* 17063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6286 | /* 17067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6287 | /* 17071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6288 | /* 17075 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 6289 | /* 17075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL), |
| 6290 | /* 17078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6291 | /* 17080 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6292 | /* 17082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6293 | /* 17084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6294 | /* 17087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6295 | /* 17093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6296 | /* 17099 */ GIR_RootConstrainSelectedInstOperands, |
| 6297 | /* 17100 */ // GIR_Coverage, 168, |
| 6298 | /* 17100 */ GIR_EraseRootFromParent_Done, |
| 6299 | /* 17101 */ // Label 359: @17101 |
| 6300 | /* 17101 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(17147), // Rule ID 169 // |
| 6301 | /* 17106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), |
| 6302 | /* 17109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6303 | /* 17113 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6304 | /* 17117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6305 | /* 17121 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 6306 | /* 17121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5), |
| 6307 | /* 17124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6308 | /* 17126 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6309 | /* 17128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6310 | /* 17130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6311 | /* 17133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6312 | /* 17139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6313 | /* 17145 */ GIR_RootConstrainSelectedInstOperands, |
| 6314 | /* 17146 */ // GIR_Coverage, 169, |
| 6315 | /* 17146 */ GIR_EraseRootFromParent_Done, |
| 6316 | /* 17147 */ // Label 360: @17147 |
| 6317 | /* 17147 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(17193), // Rule ID 322 // |
| 6318 | /* 17152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 6319 | /* 17155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6320 | /* 17159 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6321 | /* 17163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6322 | /* 17167 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6323 | /* 17167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL), |
| 6324 | /* 17170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6325 | /* 17172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 6326 | /* 17178 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6327 | /* 17180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6328 | /* 17182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6329 | /* 17185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6330 | /* 17191 */ GIR_RootConstrainSelectedInstOperands, |
| 6331 | /* 17192 */ // GIR_Coverage, 322, |
| 6332 | /* 17192 */ GIR_EraseRootFromParent_Done, |
| 6333 | /* 17193 */ // Label 361: @17193 |
| 6334 | /* 17193 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(17233), // Rule ID 501 // |
| 6335 | /* 17198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6336 | /* 17201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6337 | /* 17205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6338 | /* 17209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6339 | /* 17213 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6340 | /* 17213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL), |
| 6341 | /* 17216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6342 | /* 17218 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6343 | /* 17220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6344 | /* 17222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6345 | /* 17225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6346 | /* 17231 */ GIR_RootConstrainSelectedInstOperands, |
| 6347 | /* 17232 */ // GIR_Coverage, 501, |
| 6348 | /* 17232 */ GIR_EraseRootFromParent_Done, |
| 6349 | /* 17233 */ // Label 362: @17233 |
| 6350 | /* 17233 */ GIM_Reject, |
| 6351 | /* 17234 */ // Label 350: @17234 |
| 6352 | /* 17234 */ GIM_Reject, |
| 6353 | /* 17235 */ // Label 343: @17235 |
| 6354 | /* 17235 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(17281), // Rule ID 956 // |
| 6355 | /* 17240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6356 | /* 17243 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6357 | /* 17246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6358 | /* 17249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6359 | /* 17253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6360 | /* 17257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6361 | /* 17261 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 6362 | /* 17261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32), |
| 6363 | /* 17264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6364 | /* 17266 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6365 | /* 17268 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6366 | /* 17270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6367 | /* 17273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6368 | /* 17279 */ GIR_RootConstrainSelectedInstOperands, |
| 6369 | /* 17280 */ // GIR_Coverage, 956, |
| 6370 | /* 17280 */ GIR_EraseRootFromParent_Done, |
| 6371 | /* 17281 */ // Label 363: @17281 |
| 6372 | /* 17281 */ GIM_Reject, |
| 6373 | /* 17282 */ // Label 344: @17282 |
| 6374 | /* 17282 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(17328), // Rule ID 955 // |
| 6375 | /* 17287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6376 | /* 17290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6377 | /* 17293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6378 | /* 17296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6379 | /* 17300 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6380 | /* 17304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6381 | /* 17308 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 6382 | /* 17308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16), |
| 6383 | /* 17311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6384 | /* 17313 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6385 | /* 17315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6386 | /* 17317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6387 | /* 17320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6388 | /* 17326 */ GIR_RootConstrainSelectedInstOperands, |
| 6389 | /* 17327 */ // GIR_Coverage, 955, |
| 6390 | /* 17327 */ GIR_EraseRootFromParent_Done, |
| 6391 | /* 17328 */ // Label 364: @17328 |
| 6392 | /* 17328 */ GIM_Reject, |
| 6393 | /* 17329 */ // Label 345: @17329 |
| 6394 | /* 17329 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(17557), |
| 6395 | /* 17334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6396 | /* 17337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6397 | /* 17340 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(17455), // Rule ID 4911 // |
| 6398 | /* 17345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6399 | /* 17348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6400 | /* 17352 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6401 | /* 17356 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6402 | /* 17360 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6403 | /* 17364 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6404 | /* 17369 */ // MIs[1] Operand 2 |
| 6405 | /* 17369 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6406 | /* 17380 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6407 | /* 17384 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6408 | /* 17388 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6409 | /* 17392 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6410 | /* 17397 */ // MIs[2] Operand 2 |
| 6411 | /* 17397 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6412 | /* 17408 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6413 | /* 17410 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2) |
| 6414 | /* 17410 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6415 | /* 17413 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6416 | /* 17417 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6417 | /* 17422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 6418 | /* 17425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6419 | /* 17427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6420 | /* 17431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6421 | /* 17435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6422 | /* 17438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6423 | /* 17444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6424 | /* 17450 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6425 | /* 17453 */ GIR_RootConstrainSelectedInstOperands, |
| 6426 | /* 17454 */ // GIR_Coverage, 4911, |
| 6427 | /* 17454 */ GIR_EraseRootFromParent_Done, |
| 6428 | /* 17455 */ // Label 366: @17455 |
| 6429 | /* 17455 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(17495), // Rule ID 959 // |
| 6430 | /* 17460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6431 | /* 17463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6432 | /* 17467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6433 | /* 17471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6434 | /* 17475 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 6435 | /* 17475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32), |
| 6436 | /* 17478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6437 | /* 17480 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6438 | /* 17482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6439 | /* 17484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6440 | /* 17487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6441 | /* 17493 */ GIR_RootConstrainSelectedInstOperands, |
| 6442 | /* 17494 */ // GIR_Coverage, 959, |
| 6443 | /* 17494 */ GIR_EraseRootFromParent_Done, |
| 6444 | /* 17495 */ // Label 367: @17495 |
| 6445 | /* 17495 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(17556), // Rule ID 3848 // |
| 6446 | /* 17500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6447 | /* 17503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6448 | /* 17507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6449 | /* 17511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6450 | /* 17515 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 6451 | /* 17515 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6452 | /* 17518 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6453 | /* 17522 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6454 | /* 17527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32), |
| 6455 | /* 17530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6456 | /* 17532 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6457 | /* 17534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6458 | /* 17536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6459 | /* 17539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6460 | /* 17545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6461 | /* 17551 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6462 | /* 17554 */ GIR_RootConstrainSelectedInstOperands, |
| 6463 | /* 17555 */ // GIR_Coverage, 3848, |
| 6464 | /* 17555 */ GIR_EraseRootFromParent_Done, |
| 6465 | /* 17556 */ // Label 368: @17556 |
| 6466 | /* 17556 */ GIM_Reject, |
| 6467 | /* 17557 */ // Label 365: @17557 |
| 6468 | /* 17557 */ GIM_Reject, |
| 6469 | /* 17558 */ // Label 346: @17558 |
| 6470 | /* 17558 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(17604), // Rule ID 954 // |
| 6471 | /* 17563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6472 | /* 17566 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6473 | /* 17569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 6474 | /* 17572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6475 | /* 17576 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6476 | /* 17580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6477 | /* 17584 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 6478 | /* 17584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8), |
| 6479 | /* 17587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6480 | /* 17589 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6481 | /* 17591 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6482 | /* 17593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6483 | /* 17596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6484 | /* 17602 */ GIR_RootConstrainSelectedInstOperands, |
| 6485 | /* 17603 */ // GIR_Coverage, 954, |
| 6486 | /* 17603 */ GIR_EraseRootFromParent_Done, |
| 6487 | /* 17604 */ // Label 369: @17604 |
| 6488 | /* 17604 */ GIM_Reject, |
| 6489 | /* 17605 */ // Label 347: @17605 |
| 6490 | /* 17605 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(17833), |
| 6491 | /* 17610 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6492 | /* 17613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6493 | /* 17616 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(17731), // Rule ID 4916 // |
| 6494 | /* 17621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6495 | /* 17624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6496 | /* 17628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6497 | /* 17632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6498 | /* 17636 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6499 | /* 17640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6500 | /* 17645 */ // MIs[1] Operand 2 |
| 6501 | /* 17645 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 6502 | /* 17656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6503 | /* 17660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6504 | /* 17664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6505 | /* 17668 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6506 | /* 17673 */ // MIs[2] Operand 2 |
| 6507 | /* 17673 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8), |
| 6508 | /* 17684 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6509 | /* 17686 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2) |
| 6510 | /* 17686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6511 | /* 17689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6512 | /* 17693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6513 | /* 17698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 6514 | /* 17701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6515 | /* 17703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6516 | /* 17707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6517 | /* 17711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6518 | /* 17714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6519 | /* 17720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6520 | /* 17726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6521 | /* 17729 */ GIR_RootConstrainSelectedInstOperands, |
| 6522 | /* 17730 */ // GIR_Coverage, 4916, |
| 6523 | /* 17730 */ GIR_EraseRootFromParent_Done, |
| 6524 | /* 17731 */ // Label 371: @17731 |
| 6525 | /* 17731 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(17771), // Rule ID 958 // |
| 6526 | /* 17736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6527 | /* 17739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6528 | /* 17743 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6529 | /* 17747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6530 | /* 17751 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 6531 | /* 17751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16), |
| 6532 | /* 17754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6533 | /* 17756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6534 | /* 17758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6535 | /* 17760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6536 | /* 17763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6537 | /* 17769 */ GIR_RootConstrainSelectedInstOperands, |
| 6538 | /* 17770 */ // GIR_Coverage, 958, |
| 6539 | /* 17770 */ GIR_EraseRootFromParent_Done, |
| 6540 | /* 17771 */ // Label 372: @17771 |
| 6541 | /* 17771 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(17832), // Rule ID 3844 // |
| 6542 | /* 17776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6543 | /* 17779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6544 | /* 17783 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6545 | /* 17787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6546 | /* 17791 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 6547 | /* 17791 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6548 | /* 17794 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6549 | /* 17798 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6550 | /* 17803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16), |
| 6551 | /* 17806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6552 | /* 17808 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6553 | /* 17810 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6554 | /* 17812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6555 | /* 17815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6556 | /* 17821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6557 | /* 17827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6558 | /* 17830 */ GIR_RootConstrainSelectedInstOperands, |
| 6559 | /* 17831 */ // GIR_Coverage, 3844, |
| 6560 | /* 17831 */ GIR_EraseRootFromParent_Done, |
| 6561 | /* 17832 */ // Label 373: @17832 |
| 6562 | /* 17832 */ GIM_Reject, |
| 6563 | /* 17833 */ // Label 370: @17833 |
| 6564 | /* 17833 */ GIM_Reject, |
| 6565 | /* 17834 */ // Label 348: @17834 |
| 6566 | /* 17834 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(17947), |
| 6567 | /* 17839 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 6568 | /* 17842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6569 | /* 17845 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(17885), // Rule ID 957 // |
| 6570 | /* 17850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6571 | /* 17853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6572 | /* 17857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6573 | /* 17861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6574 | /* 17865 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 6575 | /* 17865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8), |
| 6576 | /* 17868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6577 | /* 17870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6578 | /* 17872 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6579 | /* 17874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6580 | /* 17877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6581 | /* 17883 */ GIR_RootConstrainSelectedInstOperands, |
| 6582 | /* 17884 */ // GIR_Coverage, 957, |
| 6583 | /* 17884 */ GIR_EraseRootFromParent_Done, |
| 6584 | /* 17885 */ // Label 375: @17885 |
| 6585 | /* 17885 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(17946), // Rule ID 3840 // |
| 6586 | /* 17890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6587 | /* 17893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6588 | /* 17897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6589 | /* 17901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6590 | /* 17905 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 6591 | /* 17905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6592 | /* 17908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6593 | /* 17912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6594 | /* 17917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8), |
| 6595 | /* 17920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6596 | /* 17922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6597 | /* 17924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6598 | /* 17926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6599 | /* 17929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6600 | /* 17935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6601 | /* 17941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6602 | /* 17944 */ GIR_RootConstrainSelectedInstOperands, |
| 6603 | /* 17945 */ // GIR_Coverage, 3840, |
| 6604 | /* 17945 */ GIR_EraseRootFromParent_Done, |
| 6605 | /* 17946 */ // Label 376: @17946 |
| 6606 | /* 17946 */ GIM_Reject, |
| 6607 | /* 17947 */ // Label 374: @17947 |
| 6608 | /* 17947 */ GIM_Reject, |
| 6609 | /* 17948 */ // Label 349: @17948 |
| 6610 | /* 17948 */ GIM_Reject, |
| 6611 | /* 17949 */ // Label 3: @17949 |
| 6612 | /* 17949 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(18044), |
| 6613 | /* 17954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6614 | /* 17957 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6615 | /* 17960 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6616 | /* 17963 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(18003), // Rule ID 194 // |
| 6617 | /* 17968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), |
| 6618 | /* 17971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6619 | /* 17975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6620 | /* 17979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6621 | /* 17983 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6622 | /* 17983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV), |
| 6623 | /* 17986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6624 | /* 17988 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6625 | /* 17990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6626 | /* 17992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6627 | /* 17995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6628 | /* 18001 */ GIR_RootConstrainSelectedInstOperands, |
| 6629 | /* 18002 */ // GIR_Coverage, 194, |
| 6630 | /* 18002 */ GIR_EraseRootFromParent_Done, |
| 6631 | /* 18003 */ // Label 378: @18003 |
| 6632 | /* 18003 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(18043), // Rule ID 531 // |
| 6633 | /* 18008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), |
| 6634 | /* 18011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6635 | /* 18015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6636 | /* 18019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6637 | /* 18023 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6638 | /* 18023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV), |
| 6639 | /* 18026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6640 | /* 18028 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6641 | /* 18030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6642 | /* 18032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6643 | /* 18035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6644 | /* 18041 */ GIR_RootConstrainSelectedInstOperands, |
| 6645 | /* 18042 */ // GIR_Coverage, 531, |
| 6646 | /* 18042 */ GIR_EraseRootFromParent_Done, |
| 6647 | /* 18043 */ // Label 379: @18043 |
| 6648 | /* 18043 */ GIM_Reject, |
| 6649 | /* 18044 */ // Label 377: @18044 |
| 6650 | /* 18044 */ GIM_Reject, |
| 6651 | /* 18045 */ // Label 4: @18045 |
| 6652 | /* 18045 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(18140), |
| 6653 | /* 18050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6654 | /* 18053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6655 | /* 18056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6656 | /* 18059 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(18099), // Rule ID 195 // |
| 6657 | /* 18064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), |
| 6658 | /* 18067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6659 | /* 18071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6660 | /* 18075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6661 | /* 18079 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6662 | /* 18079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV), |
| 6663 | /* 18082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6664 | /* 18084 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6665 | /* 18086 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6666 | /* 18088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6667 | /* 18091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6668 | /* 18097 */ GIR_RootConstrainSelectedInstOperands, |
| 6669 | /* 18098 */ // GIR_Coverage, 195, |
| 6670 | /* 18098 */ GIR_EraseRootFromParent_Done, |
| 6671 | /* 18099 */ // Label 381: @18099 |
| 6672 | /* 18099 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(18139), // Rule ID 532 // |
| 6673 | /* 18104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), |
| 6674 | /* 18107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6675 | /* 18111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6676 | /* 18115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6677 | /* 18119 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6678 | /* 18119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV), |
| 6679 | /* 18122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6680 | /* 18124 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6681 | /* 18126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6682 | /* 18128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6683 | /* 18131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6684 | /* 18137 */ GIR_RootConstrainSelectedInstOperands, |
| 6685 | /* 18138 */ // GIR_Coverage, 532, |
| 6686 | /* 18138 */ GIR_EraseRootFromParent_Done, |
| 6687 | /* 18139 */ // Label 382: @18139 |
| 6688 | /* 18139 */ GIM_Reject, |
| 6689 | /* 18140 */ // Label 380: @18140 |
| 6690 | /* 18140 */ GIM_Reject, |
| 6691 | /* 18141 */ // Label 5: @18141 |
| 6692 | /* 18141 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 396*/ GIMT_Encode4(21320), |
| 6693 | /* 18152 */ /*GILLT_s32*//*Label 383*/ GIMT_Encode4(18212), |
| 6694 | /* 18156 */ /*GILLT_s64*//*Label 384*/ GIMT_Encode4(20204), |
| 6695 | /* 18160 */ /*GILLT_v2s1*//*Label 385*/ GIMT_Encode4(20251), |
| 6696 | /* 18164 */ /*GILLT_v2s32*//*Label 386*/ GIMT_Encode4(20369), |
| 6697 | /* 18168 */ /*GILLT_v2s64*//*Label 387*/ GIMT_Encode4(20416), |
| 6698 | /* 18172 */ /*GILLT_v4s1*//*Label 388*/ GIMT_Encode4(20530), |
| 6699 | /* 18176 */ /*GILLT_v4s16*//*Label 389*/ GIMT_Encode4(20648), |
| 6700 | /* 18180 */ /*GILLT_v4s32*//*Label 390*/ GIMT_Encode4(20695), GIMT_Encode4(0), |
| 6701 | /* 18188 */ /*GILLT_v8s1*//*Label 391*/ GIMT_Encode4(20809), |
| 6702 | /* 18192 */ /*GILLT_v8s8*//*Label 392*/ GIMT_Encode4(20927), |
| 6703 | /* 18196 */ /*GILLT_v8s16*//*Label 393*/ GIMT_Encode4(20974), GIMT_Encode4(0), |
| 6704 | /* 18204 */ /*GILLT_v16s1*//*Label 394*/ GIMT_Encode4(21088), |
| 6705 | /* 18208 */ /*GILLT_v16s8*//*Label 395*/ GIMT_Encode4(21206), |
| 6706 | /* 18212 */ // Label 383: @18212 |
| 6707 | /* 18212 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(20203), |
| 6708 | /* 18217 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6709 | /* 18220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6710 | /* 18223 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(18296), // Rule ID 2040 // |
| 6711 | /* 18228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6712 | /* 18231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6713 | /* 18235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6714 | /* 18239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6715 | /* 18243 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6716 | /* 18247 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6717 | /* 18251 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6718 | /* 18256 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 6719 | /* 18260 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6720 | /* 18271 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6721 | /* 18273 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 6722 | /* 18273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 6723 | /* 18276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6724 | /* 18278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 6725 | /* 18282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 6726 | /* 18285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6727 | /* 18288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6728 | /* 18294 */ GIR_RootConstrainSelectedInstOperands, |
| 6729 | /* 18295 */ // GIR_Coverage, 2040, |
| 6730 | /* 18295 */ GIR_EraseRootFromParent_Done, |
| 6731 | /* 18296 */ // Label 398: @18296 |
| 6732 | /* 18296 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(18369), // Rule ID 2297 // |
| 6733 | /* 18301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6734 | /* 18304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6735 | /* 18308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6736 | /* 18312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6737 | /* 18316 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6738 | /* 18320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6739 | /* 18324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6740 | /* 18329 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 6741 | /* 18333 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6742 | /* 18344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6743 | /* 18346 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 6744 | /* 18346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 6745 | /* 18349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6746 | /* 18351 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 6747 | /* 18355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 6748 | /* 18358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6749 | /* 18361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6750 | /* 18367 */ GIR_RootConstrainSelectedInstOperands, |
| 6751 | /* 18368 */ // GIR_Coverage, 2297, |
| 6752 | /* 18368 */ GIR_EraseRootFromParent_Done, |
| 6753 | /* 18369 */ // Label 399: @18369 |
| 6754 | /* 18369 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(18417), // Rule ID 2182 // |
| 6755 | /* 18374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6756 | /* 18377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6757 | /* 18381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6758 | /* 18385 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6759 | /* 18396 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6760 | /* 18396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB), |
| 6761 | /* 18399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6762 | /* 18401 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6763 | /* 18403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6764 | /* 18406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6765 | /* 18409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6766 | /* 18415 */ GIR_RootConstrainSelectedInstOperands, |
| 6767 | /* 18416 */ // GIR_Coverage, 2182, |
| 6768 | /* 18416 */ GIR_EraseRootFromParent_Done, |
| 6769 | /* 18417 */ // Label 400: @18417 |
| 6770 | /* 18417 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(18465), // Rule ID 2183 // |
| 6771 | /* 18422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6772 | /* 18425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6773 | /* 18429 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6774 | /* 18433 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6775 | /* 18444 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6776 | /* 18444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH), |
| 6777 | /* 18447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6778 | /* 18449 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6779 | /* 18451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6780 | /* 18454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6781 | /* 18457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6782 | /* 18463 */ GIR_RootConstrainSelectedInstOperands, |
| 6783 | /* 18464 */ // GIR_Coverage, 2183, |
| 6784 | /* 18464 */ GIR_EraseRootFromParent_Done, |
| 6785 | /* 18465 */ // Label 401: @18465 |
| 6786 | /* 18465 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(18513), // Rule ID 2184 // |
| 6787 | /* 18470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6788 | /* 18473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6789 | /* 18477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6790 | /* 18481 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6791 | /* 18492 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6792 | /* 18492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 6793 | /* 18495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6794 | /* 18497 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6795 | /* 18499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6796 | /* 18502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6797 | /* 18505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6798 | /* 18511 */ GIR_RootConstrainSelectedInstOperands, |
| 6799 | /* 18512 */ // GIR_Coverage, 2184, |
| 6800 | /* 18512 */ GIR_EraseRootFromParent_Done, |
| 6801 | /* 18513 */ // Label 402: @18513 |
| 6802 | /* 18513 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(18561), // Rule ID 2421 // |
| 6803 | /* 18518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6804 | /* 18521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6805 | /* 18525 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6806 | /* 18529 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6807 | /* 18540 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6808 | /* 18540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB), |
| 6809 | /* 18543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6810 | /* 18545 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6811 | /* 18547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6812 | /* 18550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6813 | /* 18553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6814 | /* 18559 */ GIR_RootConstrainSelectedInstOperands, |
| 6815 | /* 18560 */ // GIR_Coverage, 2421, |
| 6816 | /* 18560 */ GIR_EraseRootFromParent_Done, |
| 6817 | /* 18561 */ // Label 403: @18561 |
| 6818 | /* 18561 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(18609), // Rule ID 2422 // |
| 6819 | /* 18566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6820 | /* 18569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6821 | /* 18573 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6822 | /* 18577 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6823 | /* 18588 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6824 | /* 18588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH), |
| 6825 | /* 18591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6826 | /* 18593 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6827 | /* 18595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6828 | /* 18598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6829 | /* 18601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6830 | /* 18607 */ GIR_RootConstrainSelectedInstOperands, |
| 6831 | /* 18608 */ // GIR_Coverage, 2422, |
| 6832 | /* 18608 */ GIR_EraseRootFromParent_Done, |
| 6833 | /* 18609 */ // Label 404: @18609 |
| 6834 | /* 18609 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(18657), // Rule ID 2423 // |
| 6835 | /* 18614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6836 | /* 18617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6837 | /* 18621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6838 | /* 18625 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6839 | /* 18636 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6840 | /* 18636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 6841 | /* 18639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6842 | /* 18641 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6843 | /* 18643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6844 | /* 18646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6845 | /* 18649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6846 | /* 18655 */ GIR_RootConstrainSelectedInstOperands, |
| 6847 | /* 18656 */ // GIR_Coverage, 2423, |
| 6848 | /* 18656 */ GIR_EraseRootFromParent_Done, |
| 6849 | /* 18657 */ // Label 405: @18657 |
| 6850 | /* 18657 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(18734), // Rule ID 5953 // |
| 6851 | /* 18662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6852 | /* 18665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6853 | /* 18669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6854 | /* 18673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6855 | /* 18677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6856 | /* 18681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6857 | /* 18685 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6858 | /* 18689 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6859 | /* 18693 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6860 | /* 18697 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6861 | /* 18701 */ // MIs[2] Operand 1 |
| 6862 | /* 18701 */ // No operand predicates |
| 6863 | /* 18701 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6864 | /* 18705 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6865 | /* 18707 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6866 | /* 18707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6867 | /* 18710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6868 | /* 18712 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6869 | /* 18714 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6870 | /* 18717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6871 | /* 18720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6872 | /* 18726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6873 | /* 18732 */ GIR_RootConstrainSelectedInstOperands, |
| 6874 | /* 18733 */ // GIR_Coverage, 5953, |
| 6875 | /* 18733 */ GIR_EraseRootFromParent_Done, |
| 6876 | /* 18734 */ // Label 406: @18734 |
| 6877 | /* 18734 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(18811), // Rule ID 5986 // |
| 6878 | /* 18739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6879 | /* 18742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6880 | /* 18746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6881 | /* 18750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6882 | /* 18754 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6883 | /* 18758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6884 | /* 18762 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6885 | /* 18766 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6886 | /* 18770 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6887 | /* 18774 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6888 | /* 18778 */ // MIs[2] Operand 1 |
| 6889 | /* 18778 */ // No operand predicates |
| 6890 | /* 18778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6891 | /* 18782 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6892 | /* 18784 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6893 | /* 18784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6894 | /* 18787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6895 | /* 18789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6896 | /* 18791 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6897 | /* 18794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6898 | /* 18797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6899 | /* 18803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6900 | /* 18809 */ GIR_RootConstrainSelectedInstOperands, |
| 6901 | /* 18810 */ // GIR_Coverage, 5986, |
| 6902 | /* 18810 */ GIR_EraseRootFromParent_Done, |
| 6903 | /* 18811 */ // Label 407: @18811 |
| 6904 | /* 18811 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(18888), // Rule ID 5952 // |
| 6905 | /* 18816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6906 | /* 18819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6907 | /* 18823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6908 | /* 18827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6909 | /* 18831 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6910 | /* 18835 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6911 | /* 18839 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6912 | /* 18843 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6913 | /* 18847 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6914 | /* 18851 */ // MIs[2] Operand 1 |
| 6915 | /* 18851 */ // No operand predicates |
| 6916 | /* 18851 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6917 | /* 18855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6918 | /* 18859 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6919 | /* 18861 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6920 | /* 18861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6921 | /* 18864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6922 | /* 18866 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6923 | /* 18868 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6924 | /* 18871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6925 | /* 18874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6926 | /* 18880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6927 | /* 18886 */ GIR_RootConstrainSelectedInstOperands, |
| 6928 | /* 18887 */ // GIR_Coverage, 5952, |
| 6929 | /* 18887 */ GIR_EraseRootFromParent_Done, |
| 6930 | /* 18888 */ // Label 408: @18888 |
| 6931 | /* 18888 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(18965), // Rule ID 5985 // |
| 6932 | /* 18893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6933 | /* 18896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6934 | /* 18900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6935 | /* 18904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6936 | /* 18908 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6937 | /* 18912 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6938 | /* 18916 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6939 | /* 18920 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6940 | /* 18924 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6941 | /* 18928 */ // MIs[2] Operand 1 |
| 6942 | /* 18928 */ // No operand predicates |
| 6943 | /* 18928 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6944 | /* 18932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6945 | /* 18936 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6946 | /* 18938 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6947 | /* 18938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6948 | /* 18941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6949 | /* 18943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6950 | /* 18945 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6951 | /* 18948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6952 | /* 18951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6953 | /* 18957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6954 | /* 18963 */ GIR_RootConstrainSelectedInstOperands, |
| 6955 | /* 18964 */ // GIR_Coverage, 5985, |
| 6956 | /* 18964 */ GIR_EraseRootFromParent_Done, |
| 6957 | /* 18965 */ // Label 409: @18965 |
| 6958 | /* 18965 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(19042), // Rule ID 5951 // |
| 6959 | /* 18970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6960 | /* 18973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6961 | /* 18977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6962 | /* 18981 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6963 | /* 18985 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6964 | /* 18989 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6965 | /* 18993 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6966 | /* 18997 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6967 | /* 19001 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6968 | /* 19005 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6969 | /* 19009 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6970 | /* 19013 */ // MIs[2] Operand 1 |
| 6971 | /* 19013 */ // No operand predicates |
| 6972 | /* 19013 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6973 | /* 19015 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6974 | /* 19015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6975 | /* 19018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6976 | /* 19020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6977 | /* 19022 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6978 | /* 19025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6979 | /* 19028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6980 | /* 19034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6981 | /* 19040 */ GIR_RootConstrainSelectedInstOperands, |
| 6982 | /* 19041 */ // GIR_Coverage, 5951, |
| 6983 | /* 19041 */ GIR_EraseRootFromParent_Done, |
| 6984 | /* 19042 */ // Label 410: @19042 |
| 6985 | /* 19042 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(19119), // Rule ID 5984 // |
| 6986 | /* 19047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6987 | /* 19050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6988 | /* 19054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6989 | /* 19058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6990 | /* 19062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6991 | /* 19066 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6992 | /* 19070 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6993 | /* 19074 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6994 | /* 19078 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6995 | /* 19082 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6996 | /* 19086 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6997 | /* 19090 */ // MIs[2] Operand 1 |
| 6998 | /* 19090 */ // No operand predicates |
| 6999 | /* 19090 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 7000 | /* 19092 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7001 | /* 19092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 7002 | /* 19095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7003 | /* 19097 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7004 | /* 19099 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 7005 | /* 19102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7006 | /* 19105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7007 | /* 19111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7008 | /* 19117 */ GIR_RootConstrainSelectedInstOperands, |
| 7009 | /* 19118 */ // GIR_Coverage, 5984, |
| 7010 | /* 19118 */ GIR_EraseRootFromParent_Done, |
| 7011 | /* 19119 */ // Label 411: @19119 |
| 7012 | /* 19119 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(19196), // Rule ID 158 // |
| 7013 | /* 19124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7014 | /* 19127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7015 | /* 19131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7016 | /* 19135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7017 | /* 19139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7018 | /* 19143 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7019 | /* 19147 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7020 | /* 19151 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7021 | /* 19155 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7022 | /* 19159 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 7023 | /* 19163 */ // MIs[2] Operand 1 |
| 7024 | /* 19163 */ // No operand predicates |
| 7025 | /* 19163 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7026 | /* 19167 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 7027 | /* 19169 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7028 | /* 19169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 7029 | /* 19172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7030 | /* 19174 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7031 | /* 19176 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 7032 | /* 19179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7033 | /* 19182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7034 | /* 19188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7035 | /* 19194 */ GIR_RootConstrainSelectedInstOperands, |
| 7036 | /* 19195 */ // GIR_Coverage, 158, |
| 7037 | /* 19195 */ GIR_EraseRootFromParent_Done, |
| 7038 | /* 19196 */ // Label 412: @19196 |
| 7039 | /* 19196 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(19273), // Rule ID 489 // |
| 7040 | /* 19201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7041 | /* 19204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7042 | /* 19208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7043 | /* 19212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7044 | /* 19216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7045 | /* 19220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7046 | /* 19224 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7047 | /* 19228 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7048 | /* 19232 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7049 | /* 19236 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 7050 | /* 19240 */ // MIs[2] Operand 1 |
| 7051 | /* 19240 */ // No operand predicates |
| 7052 | /* 19240 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7053 | /* 19244 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 7054 | /* 19246 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7055 | /* 19246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 7056 | /* 19249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7057 | /* 19251 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7058 | /* 19253 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 7059 | /* 19256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7060 | /* 19259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7061 | /* 19265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7062 | /* 19271 */ GIR_RootConstrainSelectedInstOperands, |
| 7063 | /* 19272 */ // GIR_Coverage, 489, |
| 7064 | /* 19272 */ GIR_EraseRootFromParent_Done, |
| 7065 | /* 19273 */ // Label 413: @19273 |
| 7066 | /* 19273 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(19344), // Rule ID 5954 // |
| 7067 | /* 19278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7068 | /* 19281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7069 | /* 19285 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7070 | /* 19289 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7071 | /* 19293 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7072 | /* 19297 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7073 | /* 19301 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7074 | /* 19306 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7075 | /* 19310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7076 | /* 19314 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7077 | /* 19316 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 7078 | /* 19316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 7079 | /* 19319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7080 | /* 19321 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 7081 | /* 19323 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7082 | /* 19327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7083 | /* 19330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7084 | /* 19336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7085 | /* 19342 */ GIR_RootConstrainSelectedInstOperands, |
| 7086 | /* 19343 */ // GIR_Coverage, 5954, |
| 7087 | /* 19343 */ GIR_EraseRootFromParent_Done, |
| 7088 | /* 19344 */ // Label 414: @19344 |
| 7089 | /* 19344 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(19415), // Rule ID 5975 // |
| 7090 | /* 19349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 7091 | /* 19352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7092 | /* 19356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7093 | /* 19360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7094 | /* 19364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7095 | /* 19368 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7096 | /* 19372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7097 | /* 19377 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7098 | /* 19381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7099 | /* 19385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7100 | /* 19387 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 7101 | /* 19387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 7102 | /* 19390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 7103 | /* 19392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 7104 | /* 19398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 7105 | /* 19400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7106 | /* 19404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7107 | /* 19407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7108 | /* 19413 */ GIR_RootConstrainSelectedInstOperands, |
| 7109 | /* 19414 */ // GIR_Coverage, 5975, |
| 7110 | /* 19414 */ GIR_EraseRootFromParent_Done, |
| 7111 | /* 19415 */ // Label 415: @19415 |
| 7112 | /* 19415 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(19486), // Rule ID 5987 // |
| 7113 | /* 19420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7114 | /* 19423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7115 | /* 19427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7116 | /* 19431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7117 | /* 19435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7118 | /* 19439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7119 | /* 19443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7120 | /* 19448 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7121 | /* 19452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7122 | /* 19456 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7123 | /* 19458 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 7124 | /* 19458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 7125 | /* 19461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7126 | /* 19463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 7127 | /* 19465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7128 | /* 19469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7129 | /* 19472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7130 | /* 19478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7131 | /* 19484 */ GIR_RootConstrainSelectedInstOperands, |
| 7132 | /* 19485 */ // GIR_Coverage, 5987, |
| 7133 | /* 19485 */ GIR_EraseRootFromParent_Done, |
| 7134 | /* 19486 */ // Label 416: @19486 |
| 7135 | /* 19486 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(19557), // Rule ID 159 // |
| 7136 | /* 19491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7137 | /* 19494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7138 | /* 19498 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7139 | /* 19502 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7140 | /* 19506 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7141 | /* 19510 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7142 | /* 19514 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7143 | /* 19518 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7144 | /* 19523 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7145 | /* 19527 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7146 | /* 19529 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 7147 | /* 19529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 7148 | /* 19532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7149 | /* 19534 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7150 | /* 19536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7151 | /* 19540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7152 | /* 19543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7153 | /* 19549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7154 | /* 19555 */ GIR_RootConstrainSelectedInstOperands, |
| 7155 | /* 19556 */ // GIR_Coverage, 159, |
| 7156 | /* 19556 */ GIR_EraseRootFromParent_Done, |
| 7157 | /* 19557 */ // Label 417: @19557 |
| 7158 | /* 19557 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(19628), // Rule ID 312 // |
| 7159 | /* 19562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 7160 | /* 19565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7161 | /* 19569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7162 | /* 19573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7163 | /* 19577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7164 | /* 19581 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7165 | /* 19585 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7166 | /* 19589 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7167 | /* 19594 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7168 | /* 19598 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7169 | /* 19600 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 7170 | /* 19600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 7171 | /* 19603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 7172 | /* 19605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 7173 | /* 19611 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7174 | /* 19613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7175 | /* 19617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7176 | /* 19620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7177 | /* 19626 */ GIR_RootConstrainSelectedInstOperands, |
| 7178 | /* 19627 */ // GIR_Coverage, 312, |
| 7179 | /* 19627 */ GIR_EraseRootFromParent_Done, |
| 7180 | /* 19628 */ // Label 418: @19628 |
| 7181 | /* 19628 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(19699), // Rule ID 490 // |
| 7182 | /* 19633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7183 | /* 19636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7184 | /* 19640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7185 | /* 19644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7186 | /* 19648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 7187 | /* 19652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7188 | /* 19656 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7189 | /* 19660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7190 | /* 19665 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 7191 | /* 19669 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7192 | /* 19671 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 7193 | /* 19671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 7194 | /* 19674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7195 | /* 19676 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7196 | /* 19678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7197 | /* 19682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7198 | /* 19685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7199 | /* 19691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7200 | /* 19697 */ GIR_RootConstrainSelectedInstOperands, |
| 7201 | /* 19698 */ // GIR_Coverage, 490, |
| 7202 | /* 19698 */ GIR_EraseRootFromParent_Done, |
| 7203 | /* 19699 */ // Label 419: @19699 |
| 7204 | /* 19699 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(19744), // Rule ID 344 // |
| 7205 | /* 19704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 7206 | /* 19707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7207 | /* 19711 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7208 | /* 19715 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 7209 | /* 19726 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 7210 | /* 19726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB), |
| 7211 | /* 19729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7212 | /* 19731 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 7213 | /* 19733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7214 | /* 19736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7215 | /* 19742 */ GIR_RootConstrainSelectedInstOperands, |
| 7216 | /* 19743 */ // GIR_Coverage, 344, |
| 7217 | /* 19743 */ GIR_EraseRootFromParent_Done, |
| 7218 | /* 19744 */ // Label 420: @19744 |
| 7219 | /* 19744 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(19789), // Rule ID 345 // |
| 7220 | /* 19749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 7221 | /* 19752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7222 | /* 19756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7223 | /* 19760 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 7224 | /* 19771 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 7225 | /* 19771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH), |
| 7226 | /* 19774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7227 | /* 19776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 7228 | /* 19778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7229 | /* 19781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7230 | /* 19787 */ GIR_RootConstrainSelectedInstOperands, |
| 7231 | /* 19788 */ // GIR_Coverage, 345, |
| 7232 | /* 19788 */ GIR_EraseRootFromParent_Done, |
| 7233 | /* 19789 */ // Label 421: @19789 |
| 7234 | /* 19789 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(19848), // Rule ID 2079 // |
| 7235 | /* 19794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7236 | /* 19797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7237 | /* 19801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7238 | /* 19805 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7239 | /* 19809 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7240 | /* 19813 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 7241 | /* 19817 */ // MIs[1] Operand 1 |
| 7242 | /* 19817 */ // No operand predicates |
| 7243 | /* 19817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7244 | /* 19819 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm)) |
| 7245 | /* 19819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 7246 | /* 19822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7247 | /* 19824 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 7248 | /* 19826 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 7249 | /* 19831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7250 | /* 19834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7251 | /* 19840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7252 | /* 19846 */ GIR_RootConstrainSelectedInstOperands, |
| 7253 | /* 19847 */ // GIR_Coverage, 2079, |
| 7254 | /* 19847 */ GIR_EraseRootFromParent_Done, |
| 7255 | /* 19848 */ // Label 422: @19848 |
| 7256 | /* 19848 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(19905), // Rule ID 146 // |
| 7257 | /* 19853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7258 | /* 19856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7259 | /* 19860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7260 | /* 19864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7261 | /* 19868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7262 | /* 19872 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 7263 | /* 19876 */ // MIs[1] Operand 1 |
| 7264 | /* 19876 */ // No operand predicates |
| 7265 | /* 19876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7266 | /* 19878 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7267 | /* 19878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri), |
| 7268 | /* 19881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7269 | /* 19883 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7270 | /* 19885 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7271 | /* 19888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7272 | /* 19891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7273 | /* 19897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7274 | /* 19903 */ GIR_RootConstrainSelectedInstOperands, |
| 7275 | /* 19904 */ // GIR_Coverage, 146, |
| 7276 | /* 19904 */ GIR_EraseRootFromParent_Done, |
| 7277 | /* 19905 */ // Label 423: @19905 |
| 7278 | /* 19905 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(19962), // Rule ID 480 // |
| 7279 | /* 19910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7280 | /* 19913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7281 | /* 19917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7282 | /* 19921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7283 | /* 19925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7284 | /* 19929 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 7285 | /* 19933 */ // MIs[1] Operand 1 |
| 7286 | /* 19933 */ // No operand predicates |
| 7287 | /* 19933 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7288 | /* 19935 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7289 | /* 19935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri), |
| 7290 | /* 19938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7291 | /* 19940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7292 | /* 19942 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7293 | /* 19945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7294 | /* 19948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7295 | /* 19954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7296 | /* 19960 */ GIR_RootConstrainSelectedInstOperands, |
| 7297 | /* 19961 */ // GIR_Coverage, 480, |
| 7298 | /* 19961 */ GIR_EraseRootFromParent_Done, |
| 7299 | /* 19962 */ // Label 424: @19962 |
| 7300 | /* 19962 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(20013), // Rule ID 162 // |
| 7301 | /* 19967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 7302 | /* 19970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7303 | /* 19974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7304 | /* 19978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7305 | /* 19982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7306 | /* 19986 */ // MIs[1] Operand 1 |
| 7307 | /* 19986 */ // No operand predicates |
| 7308 | /* 19986 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 7309 | /* 19990 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7310 | /* 19992 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 7311 | /* 19992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC), |
| 7312 | /* 19995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7313 | /* 19997 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 7314 | /* 19999 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7315 | /* 20002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7316 | /* 20005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7317 | /* 20011 */ GIR_RootConstrainSelectedInstOperands, |
| 7318 | /* 20012 */ // GIR_Coverage, 162, |
| 7319 | /* 20012 */ GIR_EraseRootFromParent_Done, |
| 7320 | /* 20013 */ // Label 425: @20013 |
| 7321 | /* 20013 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(20064), // Rule ID 492 // |
| 7322 | /* 20018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7323 | /* 20021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7324 | /* 20025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7325 | /* 20029 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7326 | /* 20033 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7327 | /* 20037 */ // MIs[1] Operand 1 |
| 7328 | /* 20037 */ // No operand predicates |
| 7329 | /* 20037 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 7330 | /* 20041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7331 | /* 20043 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 7332 | /* 20043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC), |
| 7333 | /* 20046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7334 | /* 20048 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 7335 | /* 20050 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7336 | /* 20053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7337 | /* 20056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7338 | /* 20062 */ GIR_RootConstrainSelectedInstOperands, |
| 7339 | /* 20063 */ // GIR_Coverage, 492, |
| 7340 | /* 20063 */ GIR_EraseRootFromParent_Done, |
| 7341 | /* 20064 */ // Label 426: @20064 |
| 7342 | /* 20064 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(20110), // Rule ID 147 // |
| 7343 | /* 20069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7344 | /* 20072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7345 | /* 20076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7346 | /* 20080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7347 | /* 20084 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 7348 | /* 20084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr), |
| 7349 | /* 20087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7350 | /* 20089 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7351 | /* 20091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7352 | /* 20093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7353 | /* 20096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7354 | /* 20102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7355 | /* 20108 */ GIR_RootConstrainSelectedInstOperands, |
| 7356 | /* 20109 */ // GIR_Coverage, 147, |
| 7357 | /* 20109 */ GIR_EraseRootFromParent_Done, |
| 7358 | /* 20110 */ // Label 427: @20110 |
| 7359 | /* 20110 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(20156), // Rule ID 309 // |
| 7360 | /* 20115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 7361 | /* 20118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7362 | /* 20122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7363 | /* 20126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7364 | /* 20130 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 7365 | /* 20130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND), |
| 7366 | /* 20133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 7367 | /* 20135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 7368 | /* 20141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7369 | /* 20143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7370 | /* 20145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7371 | /* 20148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7372 | /* 20154 */ GIR_RootConstrainSelectedInstOperands, |
| 7373 | /* 20155 */ // GIR_Coverage, 309, |
| 7374 | /* 20155 */ GIR_EraseRootFromParent_Done, |
| 7375 | /* 20156 */ // Label 428: @20156 |
| 7376 | /* 20156 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(20202), // Rule ID 481 // |
| 7377 | /* 20161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7378 | /* 20164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7379 | /* 20168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7380 | /* 20172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7381 | /* 20176 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 7382 | /* 20176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7383 | /* 20179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7384 | /* 20181 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7385 | /* 20183 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7386 | /* 20185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7387 | /* 20188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7388 | /* 20194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7389 | /* 20200 */ GIR_RootConstrainSelectedInstOperands, |
| 7390 | /* 20201 */ // GIR_Coverage, 481, |
| 7391 | /* 20201 */ GIR_EraseRootFromParent_Done, |
| 7392 | /* 20202 */ // Label 429: @20202 |
| 7393 | /* 20202 */ GIM_Reject, |
| 7394 | /* 20203 */ // Label 397: @20203 |
| 7395 | /* 20203 */ GIM_Reject, |
| 7396 | /* 20204 */ // Label 384: @20204 |
| 7397 | /* 20204 */ GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(20250), // Rule ID 2900 // |
| 7398 | /* 20209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7399 | /* 20212 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 7400 | /* 20215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 7401 | /* 20218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7402 | /* 20222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7403 | /* 20226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7404 | /* 20230 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 7405 | /* 20230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7406 | /* 20233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7407 | /* 20235 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7408 | /* 20237 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7409 | /* 20239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7410 | /* 20242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7411 | /* 20248 */ GIR_RootConstrainSelectedInstOperands, |
| 7412 | /* 20249 */ // GIR_Coverage, 2900, |
| 7413 | /* 20249 */ GIR_EraseRootFromParent_Done, |
| 7414 | /* 20250 */ // Label 430: @20250 |
| 7415 | /* 20250 */ GIM_Reject, |
| 7416 | /* 20251 */ // Label 385: @20251 |
| 7417 | /* 20251 */ GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(20368), // Rule ID 2011 // |
| 7418 | /* 20256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7419 | /* 20259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 7420 | /* 20262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 7421 | /* 20265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7422 | /* 20269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7423 | /* 20273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7424 | /* 20277 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7425 | /* 20277 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7426 | /* 20280 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7427 | /* 20284 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7428 | /* 20289 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7429 | /* 20293 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7430 | /* 20298 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7431 | /* 20301 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7432 | /* 20305 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7433 | /* 20310 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7434 | /* 20314 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7435 | /* 20319 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7436 | /* 20322 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7437 | /* 20326 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7438 | /* 20331 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7439 | /* 20334 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7440 | /* 20337 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7441 | /* 20340 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7442 | /* 20346 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7443 | /* 20352 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7444 | /* 20354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7445 | /* 20357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7446 | /* 20359 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7447 | /* 20362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7448 | /* 20367 */ // GIR_Coverage, 2011, |
| 7449 | /* 20367 */ GIR_EraseRootFromParent_Done, |
| 7450 | /* 20368 */ // Label 431: @20368 |
| 7451 | /* 20368 */ GIM_Reject, |
| 7452 | /* 20369 */ // Label 386: @20369 |
| 7453 | /* 20369 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(20415), // Rule ID 1294 // |
| 7454 | /* 20374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7455 | /* 20377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 7456 | /* 20380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 7457 | /* 20383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7458 | /* 20387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7459 | /* 20391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7460 | /* 20395 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 7461 | /* 20395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7462 | /* 20398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7463 | /* 20400 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7464 | /* 20402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7465 | /* 20404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7466 | /* 20407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7467 | /* 20413 */ GIR_RootConstrainSelectedInstOperands, |
| 7468 | /* 20414 */ // GIR_Coverage, 1294, |
| 7469 | /* 20414 */ GIR_EraseRootFromParent_Done, |
| 7470 | /* 20415 */ // Label 432: @20415 |
| 7471 | /* 20415 */ GIM_Reject, |
| 7472 | /* 20416 */ // Label 387: @20416 |
| 7473 | /* 20416 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(20529), |
| 7474 | /* 20421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 7475 | /* 20424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7476 | /* 20427 */ GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(20467), // Rule ID 2903 // |
| 7477 | /* 20432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7478 | /* 20435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7479 | /* 20439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7480 | /* 20443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7481 | /* 20447 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 7482 | /* 20447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7483 | /* 20450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7484 | /* 20452 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7485 | /* 20454 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7486 | /* 20456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7487 | /* 20459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7488 | /* 20465 */ GIR_RootConstrainSelectedInstOperands, |
| 7489 | /* 20466 */ // GIR_Coverage, 2903, |
| 7490 | /* 20466 */ GIR_EraseRootFromParent_Done, |
| 7491 | /* 20467 */ // Label 434: @20467 |
| 7492 | /* 20467 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(20528), // Rule ID 3752 // |
| 7493 | /* 20472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7494 | /* 20475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7495 | /* 20479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7496 | /* 20483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7497 | /* 20487 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 7498 | /* 20487 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7499 | /* 20490 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7500 | /* 20494 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7501 | /* 20499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7502 | /* 20502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7503 | /* 20504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7504 | /* 20506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7505 | /* 20508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7506 | /* 20511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7507 | /* 20517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7508 | /* 20523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7509 | /* 20526 */ GIR_RootConstrainSelectedInstOperands, |
| 7510 | /* 20527 */ // GIR_Coverage, 3752, |
| 7511 | /* 20527 */ GIR_EraseRootFromParent_Done, |
| 7512 | /* 20528 */ // Label 435: @20528 |
| 7513 | /* 20528 */ GIM_Reject, |
| 7514 | /* 20529 */ // Label 433: @20529 |
| 7515 | /* 20529 */ GIM_Reject, |
| 7516 | /* 20530 */ // Label 388: @20530 |
| 7517 | /* 20530 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(20647), // Rule ID 2012 // |
| 7518 | /* 20535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7519 | /* 20538 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 7520 | /* 20541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 7521 | /* 20544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7522 | /* 20548 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7523 | /* 20552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7524 | /* 20556 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7525 | /* 20556 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7526 | /* 20559 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7527 | /* 20563 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7528 | /* 20568 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7529 | /* 20572 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7530 | /* 20577 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7531 | /* 20580 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7532 | /* 20584 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7533 | /* 20589 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7534 | /* 20593 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7535 | /* 20598 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7536 | /* 20601 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7537 | /* 20605 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7538 | /* 20610 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7539 | /* 20613 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7540 | /* 20616 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7541 | /* 20619 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7542 | /* 20625 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7543 | /* 20631 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7544 | /* 20633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7545 | /* 20636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7546 | /* 20638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7547 | /* 20641 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7548 | /* 20646 */ // GIR_Coverage, 2012, |
| 7549 | /* 20646 */ GIR_EraseRootFromParent_Done, |
| 7550 | /* 20647 */ // Label 436: @20647 |
| 7551 | /* 20647 */ GIM_Reject, |
| 7552 | /* 20648 */ // Label 389: @20648 |
| 7553 | /* 20648 */ GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(20694), // Rule ID 2899 // |
| 7554 | /* 20653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7555 | /* 20656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 7556 | /* 20659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 7557 | /* 20662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7558 | /* 20666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7559 | /* 20670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7560 | /* 20674 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 7561 | /* 20674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7562 | /* 20677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7563 | /* 20679 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7564 | /* 20681 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7565 | /* 20683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7566 | /* 20686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7567 | /* 20692 */ GIR_RootConstrainSelectedInstOperands, |
| 7568 | /* 20693 */ // GIR_Coverage, 2899, |
| 7569 | /* 20693 */ GIR_EraseRootFromParent_Done, |
| 7570 | /* 20694 */ // Label 437: @20694 |
| 7571 | /* 20694 */ GIM_Reject, |
| 7572 | /* 20695 */ // Label 390: @20695 |
| 7573 | /* 20695 */ GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(20808), |
| 7574 | /* 20700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7575 | /* 20703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7576 | /* 20706 */ GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(20746), // Rule ID 1295 // |
| 7577 | /* 20711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7578 | /* 20714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7579 | /* 20718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7580 | /* 20722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7581 | /* 20726 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 7582 | /* 20726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7583 | /* 20729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7584 | /* 20731 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7585 | /* 20733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7586 | /* 20735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7587 | /* 20738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7588 | /* 20744 */ GIR_RootConstrainSelectedInstOperands, |
| 7589 | /* 20745 */ // GIR_Coverage, 1295, |
| 7590 | /* 20745 */ GIR_EraseRootFromParent_Done, |
| 7591 | /* 20746 */ // Label 439: @20746 |
| 7592 | /* 20746 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(20807), // Rule ID 3748 // |
| 7593 | /* 20751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7594 | /* 20754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7595 | /* 20758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7596 | /* 20762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7597 | /* 20766 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 7598 | /* 20766 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7599 | /* 20769 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7600 | /* 20773 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7601 | /* 20778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7602 | /* 20781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7603 | /* 20783 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7604 | /* 20785 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7605 | /* 20787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7606 | /* 20790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7607 | /* 20796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7608 | /* 20802 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7609 | /* 20805 */ GIR_RootConstrainSelectedInstOperands, |
| 7610 | /* 20806 */ // GIR_Coverage, 3748, |
| 7611 | /* 20806 */ GIR_EraseRootFromParent_Done, |
| 7612 | /* 20807 */ // Label 440: @20807 |
| 7613 | /* 20807 */ GIM_Reject, |
| 7614 | /* 20808 */ // Label 438: @20808 |
| 7615 | /* 20808 */ GIM_Reject, |
| 7616 | /* 20809 */ // Label 391: @20809 |
| 7617 | /* 20809 */ GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(20926), // Rule ID 2013 // |
| 7618 | /* 20814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7619 | /* 20817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 7620 | /* 20820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 7621 | /* 20823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7622 | /* 20827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7623 | /* 20831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7624 | /* 20835 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7625 | /* 20835 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7626 | /* 20838 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7627 | /* 20842 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7628 | /* 20847 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7629 | /* 20851 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7630 | /* 20856 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7631 | /* 20859 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7632 | /* 20863 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7633 | /* 20868 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7634 | /* 20872 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7635 | /* 20877 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7636 | /* 20880 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7637 | /* 20884 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7638 | /* 20889 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7639 | /* 20892 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7640 | /* 20895 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7641 | /* 20898 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7642 | /* 20904 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7643 | /* 20910 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7644 | /* 20912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7645 | /* 20915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7646 | /* 20917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7647 | /* 20920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7648 | /* 20925 */ // GIR_Coverage, 2013, |
| 7649 | /* 20925 */ GIR_EraseRootFromParent_Done, |
| 7650 | /* 20926 */ // Label 441: @20926 |
| 7651 | /* 20926 */ GIM_Reject, |
| 7652 | /* 20927 */ // Label 392: @20927 |
| 7653 | /* 20927 */ GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(20973), // Rule ID 2898 // |
| 7654 | /* 20932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7655 | /* 20935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7656 | /* 20938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 7657 | /* 20941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7658 | /* 20945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7659 | /* 20949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7660 | /* 20953 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 7661 | /* 20953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7662 | /* 20956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7663 | /* 20958 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7664 | /* 20960 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7665 | /* 20962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7666 | /* 20965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7667 | /* 20971 */ GIR_RootConstrainSelectedInstOperands, |
| 7668 | /* 20972 */ // GIR_Coverage, 2898, |
| 7669 | /* 20972 */ GIR_EraseRootFromParent_Done, |
| 7670 | /* 20973 */ // Label 442: @20973 |
| 7671 | /* 20973 */ GIM_Reject, |
| 7672 | /* 20974 */ // Label 393: @20974 |
| 7673 | /* 20974 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(21087), |
| 7674 | /* 20979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7675 | /* 20982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7676 | /* 20985 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(21025), // Rule ID 2902 // |
| 7677 | /* 20990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7678 | /* 20993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7679 | /* 20997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7680 | /* 21001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7681 | /* 21005 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 7682 | /* 21005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7683 | /* 21008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7684 | /* 21010 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7685 | /* 21012 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7686 | /* 21014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7687 | /* 21017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7688 | /* 21023 */ GIR_RootConstrainSelectedInstOperands, |
| 7689 | /* 21024 */ // GIR_Coverage, 2902, |
| 7690 | /* 21024 */ GIR_EraseRootFromParent_Done, |
| 7691 | /* 21025 */ // Label 444: @21025 |
| 7692 | /* 21025 */ GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(21086), // Rule ID 3744 // |
| 7693 | /* 21030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7694 | /* 21033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7695 | /* 21037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7696 | /* 21041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7697 | /* 21045 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 7698 | /* 21045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7699 | /* 21048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7700 | /* 21052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7701 | /* 21057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7702 | /* 21060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7703 | /* 21062 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7704 | /* 21064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7705 | /* 21066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7706 | /* 21069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7707 | /* 21075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7708 | /* 21081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7709 | /* 21084 */ GIR_RootConstrainSelectedInstOperands, |
| 7710 | /* 21085 */ // GIR_Coverage, 3744, |
| 7711 | /* 21085 */ GIR_EraseRootFromParent_Done, |
| 7712 | /* 21086 */ // Label 445: @21086 |
| 7713 | /* 21086 */ GIM_Reject, |
| 7714 | /* 21087 */ // Label 443: @21087 |
| 7715 | /* 21087 */ GIM_Reject, |
| 7716 | /* 21088 */ // Label 394: @21088 |
| 7717 | /* 21088 */ GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(21205), // Rule ID 2014 // |
| 7718 | /* 21093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7719 | /* 21096 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 7720 | /* 21099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 7721 | /* 21102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7722 | /* 21106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7723 | /* 21110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7724 | /* 21114 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7725 | /* 21114 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7726 | /* 21117 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7727 | /* 21121 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7728 | /* 21126 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7729 | /* 21130 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7730 | /* 21135 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7731 | /* 21138 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7732 | /* 21142 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7733 | /* 21147 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7734 | /* 21151 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7735 | /* 21156 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7736 | /* 21159 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7737 | /* 21163 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7738 | /* 21168 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7739 | /* 21171 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7740 | /* 21174 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7741 | /* 21177 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7742 | /* 21183 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7743 | /* 21189 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7744 | /* 21191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7745 | /* 21194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7746 | /* 21196 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7747 | /* 21199 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7748 | /* 21204 */ // GIR_Coverage, 2014, |
| 7749 | /* 21204 */ GIR_EraseRootFromParent_Done, |
| 7750 | /* 21205 */ // Label 446: @21205 |
| 7751 | /* 21205 */ GIM_Reject, |
| 7752 | /* 21206 */ // Label 395: @21206 |
| 7753 | /* 21206 */ GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(21319), |
| 7754 | /* 21211 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7755 | /* 21214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7756 | /* 21217 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(21257), // Rule ID 2901 // |
| 7757 | /* 21222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7758 | /* 21225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7759 | /* 21229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7760 | /* 21233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7761 | /* 21237 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 7762 | /* 21237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7763 | /* 21240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7764 | /* 21242 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7765 | /* 21244 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7766 | /* 21246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7767 | /* 21249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7768 | /* 21255 */ GIR_RootConstrainSelectedInstOperands, |
| 7769 | /* 21256 */ // GIR_Coverage, 2901, |
| 7770 | /* 21256 */ GIR_EraseRootFromParent_Done, |
| 7771 | /* 21257 */ // Label 448: @21257 |
| 7772 | /* 21257 */ GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(21318), // Rule ID 3740 // |
| 7773 | /* 21262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7774 | /* 21265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7775 | /* 21269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7776 | /* 21273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7777 | /* 21277 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 7778 | /* 21277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7779 | /* 21280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7780 | /* 21284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7781 | /* 21289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7782 | /* 21292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7783 | /* 21294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7784 | /* 21296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7785 | /* 21298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7786 | /* 21301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7787 | /* 21307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7788 | /* 21313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7789 | /* 21316 */ GIR_RootConstrainSelectedInstOperands, |
| 7790 | /* 21317 */ // GIR_Coverage, 3740, |
| 7791 | /* 21317 */ GIR_EraseRootFromParent_Done, |
| 7792 | /* 21318 */ // Label 449: @21318 |
| 7793 | /* 21318 */ GIM_Reject, |
| 7794 | /* 21319 */ // Label 447: @21319 |
| 7795 | /* 21319 */ GIM_Reject, |
| 7796 | /* 21320 */ // Label 396: @21320 |
| 7797 | /* 21320 */ GIM_Reject, |
| 7798 | /* 21321 */ // Label 6: @21321 |
| 7799 | /* 21321 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 463*/ GIMT_Encode4(27129), |
| 7800 | /* 21332 */ /*GILLT_s32*//*Label 450*/ GIMT_Encode4(21392), |
| 7801 | /* 21336 */ /*GILLT_s64*//*Label 451*/ GIMT_Encode4(26013), |
| 7802 | /* 21340 */ /*GILLT_v2s1*//*Label 452*/ GIMT_Encode4(26060), |
| 7803 | /* 21344 */ /*GILLT_v2s32*//*Label 453*/ GIMT_Encode4(26178), |
| 7804 | /* 21348 */ /*GILLT_v2s64*//*Label 454*/ GIMT_Encode4(26225), |
| 7805 | /* 21352 */ /*GILLT_v4s1*//*Label 455*/ GIMT_Encode4(26339), |
| 7806 | /* 21356 */ /*GILLT_v4s16*//*Label 456*/ GIMT_Encode4(26457), |
| 7807 | /* 21360 */ /*GILLT_v4s32*//*Label 457*/ GIMT_Encode4(26504), GIMT_Encode4(0), |
| 7808 | /* 21368 */ /*GILLT_v8s1*//*Label 458*/ GIMT_Encode4(26618), |
| 7809 | /* 21372 */ /*GILLT_v8s8*//*Label 459*/ GIMT_Encode4(26736), |
| 7810 | /* 21376 */ /*GILLT_v8s16*//*Label 460*/ GIMT_Encode4(26783), GIMT_Encode4(0), |
| 7811 | /* 21384 */ /*GILLT_v16s1*//*Label 461*/ GIMT_Encode4(26897), |
| 7812 | /* 21388 */ /*GILLT_v16s8*//*Label 462*/ GIMT_Encode4(27015), |
| 7813 | /* 21392 */ // Label 450: @21392 |
| 7814 | /* 21392 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(26012), |
| 7815 | /* 21397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 7816 | /* 21400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 7817 | /* 21403 */ GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(21530), // Rule ID 6235 // |
| 7818 | /* 21408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7819 | /* 21411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7820 | /* 21415 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7821 | /* 21419 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7822 | /* 21423 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7823 | /* 21427 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7824 | /* 21431 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7825 | /* 21435 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7826 | /* 21439 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7827 | /* 21443 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7828 | /* 21447 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7829 | /* 21452 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 7830 | /* 21456 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 7831 | /* 21467 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7832 | /* 21471 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7833 | /* 21475 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7834 | /* 21479 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7835 | /* 21483 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7836 | /* 21487 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7837 | /* 21491 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7838 | /* 21495 */ // MIs[4] Rm |
| 7839 | /* 21495 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7840 | /* 21500 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 7841 | /* 21504 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 7842 | /* 21508 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7843 | /* 21510 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7844 | /* 21510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 7845 | /* 21513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7846 | /* 21515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7847 | /* 21519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7848 | /* 21522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7849 | /* 21528 */ GIR_RootConstrainSelectedInstOperands, |
| 7850 | /* 21529 */ // GIR_Coverage, 6235, |
| 7851 | /* 21529 */ GIR_EraseRootFromParent_Done, |
| 7852 | /* 21530 */ // Label 465: @21530 |
| 7853 | /* 21530 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(21657), // Rule ID 6277 // |
| 7854 | /* 21535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7855 | /* 21538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7856 | /* 21542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7857 | /* 21546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7858 | /* 21550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7859 | /* 21554 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7860 | /* 21558 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7861 | /* 21562 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7862 | /* 21566 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7863 | /* 21570 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7864 | /* 21574 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7865 | /* 21579 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 7866 | /* 21583 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 7867 | /* 21594 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7868 | /* 21598 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7869 | /* 21602 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7870 | /* 21606 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7871 | /* 21610 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7872 | /* 21614 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7873 | /* 21618 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7874 | /* 21622 */ // MIs[4] Rm |
| 7875 | /* 21622 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7876 | /* 21627 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 7877 | /* 21631 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 7878 | /* 21635 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7879 | /* 21637 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7880 | /* 21637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7881 | /* 21640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7882 | /* 21642 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7883 | /* 21646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7884 | /* 21649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7885 | /* 21655 */ GIR_RootConstrainSelectedInstOperands, |
| 7886 | /* 21656 */ // GIR_Coverage, 6277, |
| 7887 | /* 21656 */ GIR_EraseRootFromParent_Done, |
| 7888 | /* 21657 */ // Label 466: @21657 |
| 7889 | /* 21657 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(21784), // Rule ID 2099 // |
| 7890 | /* 21662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7891 | /* 21665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7892 | /* 21669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7893 | /* 21673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7894 | /* 21677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7895 | /* 21681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7896 | /* 21685 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7897 | /* 21689 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7898 | /* 21693 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7899 | /* 21697 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7900 | /* 21701 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7901 | /* 21706 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7902 | /* 21710 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7903 | /* 21714 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7904 | /* 21718 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7905 | /* 21722 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7906 | /* 21726 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7907 | /* 21730 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7908 | /* 21734 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7909 | /* 21738 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7910 | /* 21742 */ // MIs[4] Rm |
| 7911 | /* 21742 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7912 | /* 21747 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7913 | /* 21751 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7914 | /* 21762 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7915 | /* 21764 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7916 | /* 21764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 7917 | /* 21767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7918 | /* 21769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7919 | /* 21773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7920 | /* 21776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7921 | /* 21782 */ GIR_RootConstrainSelectedInstOperands, |
| 7922 | /* 21783 */ // GIR_Coverage, 2099, |
| 7923 | /* 21783 */ GIR_EraseRootFromParent_Done, |
| 7924 | /* 21784 */ // Label 467: @21784 |
| 7925 | /* 21784 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(21911), // Rule ID 2381 // |
| 7926 | /* 21789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7927 | /* 21792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7928 | /* 21796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7929 | /* 21800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7930 | /* 21804 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7931 | /* 21808 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7932 | /* 21812 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7933 | /* 21816 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7934 | /* 21820 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7935 | /* 21824 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7936 | /* 21828 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7937 | /* 21833 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7938 | /* 21837 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7939 | /* 21841 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7940 | /* 21845 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7941 | /* 21849 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7942 | /* 21853 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7943 | /* 21857 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7944 | /* 21861 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7945 | /* 21865 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7946 | /* 21869 */ // MIs[4] Rm |
| 7947 | /* 21869 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7948 | /* 21874 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7949 | /* 21878 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7950 | /* 21889 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7951 | /* 21891 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7952 | /* 21891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7953 | /* 21894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7954 | /* 21896 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7955 | /* 21900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7956 | /* 21903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7957 | /* 21909 */ GIR_RootConstrainSelectedInstOperands, |
| 7958 | /* 21910 */ // GIR_Coverage, 2381, |
| 7959 | /* 21910 */ GIR_EraseRootFromParent_Done, |
| 7960 | /* 21911 */ // Label 468: @21911 |
| 7961 | /* 21911 */ GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(22044), // Rule ID 5967 // |
| 7962 | /* 21916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7963 | /* 21919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7964 | /* 21923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7965 | /* 21927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7966 | /* 21931 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7967 | /* 21935 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7968 | /* 21939 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7969 | /* 21943 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7970 | /* 21947 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7971 | /* 21951 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7972 | /* 21955 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7973 | /* 21960 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7974 | /* 21964 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7975 | /* 21968 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7976 | /* 21972 */ // MIs[3] Operand 1 |
| 7977 | /* 21972 */ // No operand predicates |
| 7978 | /* 21972 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7979 | /* 21983 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7980 | /* 21987 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7981 | /* 21991 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7982 | /* 21995 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7983 | /* 21999 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7984 | /* 22004 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7985 | /* 22015 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7986 | /* 22017 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7987 | /* 22017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7988 | /* 22020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7989 | /* 22022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7990 | /* 22026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7991 | /* 22030 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7992 | /* 22033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7993 | /* 22036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7994 | /* 22042 */ GIR_RootConstrainSelectedInstOperands, |
| 7995 | /* 22043 */ // GIR_Coverage, 5967, |
| 7996 | /* 22043 */ GIR_EraseRootFromParent_Done, |
| 7997 | /* 22044 */ // Label 469: @22044 |
| 7998 | /* 22044 */ GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(22177), // Rule ID 6004 // |
| 7999 | /* 22049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8000 | /* 22052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8001 | /* 22056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8002 | /* 22060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8003 | /* 22064 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8004 | /* 22068 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8005 | /* 22072 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8006 | /* 22076 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8007 | /* 22080 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8008 | /* 22084 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8009 | /* 22088 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8010 | /* 22093 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8011 | /* 22097 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8012 | /* 22101 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 8013 | /* 22105 */ // MIs[3] Operand 1 |
| 8014 | /* 22105 */ // No operand predicates |
| 8015 | /* 22105 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8016 | /* 22116 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 8017 | /* 22120 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 8018 | /* 22124 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 8019 | /* 22128 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 8020 | /* 22132 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8021 | /* 22137 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 8022 | /* 22148 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8023 | /* 22150 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8024 | /* 22150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8025 | /* 22153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8026 | /* 22155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 8027 | /* 22159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8028 | /* 22163 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8029 | /* 22166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8030 | /* 22169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8031 | /* 22175 */ GIR_RootConstrainSelectedInstOperands, |
| 8032 | /* 22176 */ // GIR_Coverage, 6004, |
| 8033 | /* 22176 */ GIR_EraseRootFromParent_Done, |
| 8034 | /* 22177 */ // Label 470: @22177 |
| 8035 | /* 22177 */ GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(22310), // Rule ID 6240 // |
| 8036 | /* 22182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8037 | /* 22185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8038 | /* 22189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8039 | /* 22193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8040 | /* 22197 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8041 | /* 22201 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8042 | /* 22205 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8043 | /* 22209 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8044 | /* 22213 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8045 | /* 22217 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8046 | /* 22221 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8047 | /* 22226 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8048 | /* 22230 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8049 | /* 22234 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 8050 | /* 22238 */ // MIs[3] Operand 1 |
| 8051 | /* 22238 */ // No operand predicates |
| 8052 | /* 22238 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8053 | /* 22249 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 8054 | /* 22253 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 8055 | /* 22257 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 8056 | /* 22261 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 8057 | /* 22265 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8058 | /* 22270 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 8059 | /* 22281 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8060 | /* 22283 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 8061 | /* 22283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8062 | /* 22286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8063 | /* 22288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 8064 | /* 22292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8065 | /* 22296 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8066 | /* 22299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8067 | /* 22302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8068 | /* 22308 */ GIR_RootConstrainSelectedInstOperands, |
| 8069 | /* 22309 */ // GIR_Coverage, 6240, |
| 8070 | /* 22309 */ GIR_EraseRootFromParent_Done, |
| 8071 | /* 22310 */ // Label 471: @22310 |
| 8072 | /* 22310 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(22443), // Rule ID 6282 // |
| 8073 | /* 22315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8074 | /* 22318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8075 | /* 22322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8076 | /* 22326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8077 | /* 22330 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8078 | /* 22334 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8079 | /* 22338 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8080 | /* 22342 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8081 | /* 22346 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8082 | /* 22350 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8083 | /* 22354 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8084 | /* 22359 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8085 | /* 22363 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8086 | /* 22367 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 8087 | /* 22371 */ // MIs[3] Operand 1 |
| 8088 | /* 22371 */ // No operand predicates |
| 8089 | /* 22371 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8090 | /* 22382 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 8091 | /* 22386 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 8092 | /* 22390 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 8093 | /* 22394 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 8094 | /* 22398 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8095 | /* 22403 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 8096 | /* 22414 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8097 | /* 22416 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 8098 | /* 22416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8099 | /* 22419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8100 | /* 22421 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 8101 | /* 22425 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8102 | /* 22429 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8103 | /* 22432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8104 | /* 22435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8105 | /* 22441 */ GIR_RootConstrainSelectedInstOperands, |
| 8106 | /* 22442 */ // GIR_Coverage, 6282, |
| 8107 | /* 22442 */ GIR_EraseRootFromParent_Done, |
| 8108 | /* 22443 */ // Label 472: @22443 |
| 8109 | /* 22443 */ GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(22576), // Rule ID 5966 // |
| 8110 | /* 22448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8111 | /* 22451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8112 | /* 22455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8113 | /* 22459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8114 | /* 22463 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8115 | /* 22467 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8116 | /* 22471 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8117 | /* 22475 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8118 | /* 22479 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8119 | /* 22483 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8120 | /* 22487 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8121 | /* 22492 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8122 | /* 22496 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8123 | /* 22500 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8124 | /* 22504 */ // MIs[3] Operand 1 |
| 8125 | /* 22504 */ // No operand predicates |
| 8126 | /* 22504 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8127 | /* 22515 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 8128 | /* 22519 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 8129 | /* 22523 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 8130 | /* 22527 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 8131 | /* 22531 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8132 | /* 22536 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 8133 | /* 22547 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8134 | /* 22549 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8135 | /* 22549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8136 | /* 22552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8137 | /* 22554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 8138 | /* 22558 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8139 | /* 22562 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8140 | /* 22565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8141 | /* 22568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8142 | /* 22574 */ GIR_RootConstrainSelectedInstOperands, |
| 8143 | /* 22575 */ // GIR_Coverage, 5966, |
| 8144 | /* 22575 */ GIR_EraseRootFromParent_Done, |
| 8145 | /* 22576 */ // Label 473: @22576 |
| 8146 | /* 22576 */ GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(22709), // Rule ID 6003 // |
| 8147 | /* 22581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8148 | /* 22584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8149 | /* 22588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8150 | /* 22592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8151 | /* 22596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8152 | /* 22600 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8153 | /* 22604 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8154 | /* 22608 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8155 | /* 22612 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8156 | /* 22616 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8157 | /* 22620 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8158 | /* 22625 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8159 | /* 22629 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8160 | /* 22633 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8161 | /* 22637 */ // MIs[3] Operand 1 |
| 8162 | /* 22637 */ // No operand predicates |
| 8163 | /* 22637 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8164 | /* 22648 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 8165 | /* 22652 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 8166 | /* 22656 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 8167 | /* 22660 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 8168 | /* 22664 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8169 | /* 22669 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 8170 | /* 22680 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8171 | /* 22682 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8172 | /* 22682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8173 | /* 22685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8174 | /* 22687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 8175 | /* 22691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8176 | /* 22695 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8177 | /* 22698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8178 | /* 22701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8179 | /* 22707 */ GIR_RootConstrainSelectedInstOperands, |
| 8180 | /* 22708 */ // GIR_Coverage, 6003, |
| 8181 | /* 22708 */ GIR_EraseRootFromParent_Done, |
| 8182 | /* 22709 */ // Label 474: @22709 |
| 8183 | /* 22709 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(22842), // Rule ID 202 // |
| 8184 | /* 22714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8185 | /* 22717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8186 | /* 22721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8187 | /* 22725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8188 | /* 22729 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8189 | /* 22733 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8190 | /* 22737 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8191 | /* 22742 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8192 | /* 22753 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8193 | /* 22757 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8194 | /* 22761 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8195 | /* 22765 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8196 | /* 22769 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8197 | /* 22773 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8198 | /* 22777 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8199 | /* 22781 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8200 | /* 22785 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8201 | /* 22790 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8202 | /* 22794 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8203 | /* 22798 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 8204 | /* 22802 */ // MIs[4] Operand 1 |
| 8205 | /* 22802 */ // No operand predicates |
| 8206 | /* 22802 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8207 | /* 22813 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8208 | /* 22815 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8209 | /* 22815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8210 | /* 22818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8211 | /* 22820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8212 | /* 22824 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8213 | /* 22828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8214 | /* 22831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8215 | /* 22834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8216 | /* 22840 */ GIR_RootConstrainSelectedInstOperands, |
| 8217 | /* 22841 */ // GIR_Coverage, 202, |
| 8218 | /* 22841 */ GIR_EraseRootFromParent_Done, |
| 8219 | /* 22842 */ // Label 475: @22842 |
| 8220 | /* 22842 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(22975), // Rule ID 539 // |
| 8221 | /* 22847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8222 | /* 22850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8223 | /* 22854 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8224 | /* 22858 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8225 | /* 22862 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8226 | /* 22866 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8227 | /* 22870 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8228 | /* 22875 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8229 | /* 22886 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8230 | /* 22890 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8231 | /* 22894 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8232 | /* 22898 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8233 | /* 22902 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8234 | /* 22906 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8235 | /* 22910 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8236 | /* 22914 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8237 | /* 22918 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8238 | /* 22923 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8239 | /* 22927 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8240 | /* 22931 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 8241 | /* 22935 */ // MIs[4] Operand 1 |
| 8242 | /* 22935 */ // No operand predicates |
| 8243 | /* 22935 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8244 | /* 22946 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8245 | /* 22948 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8246 | /* 22948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8247 | /* 22951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8248 | /* 22953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8249 | /* 22957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8250 | /* 22961 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8251 | /* 22964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8252 | /* 22967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8253 | /* 22973 */ GIR_RootConstrainSelectedInstOperands, |
| 8254 | /* 22974 */ // GIR_Coverage, 539, |
| 8255 | /* 22974 */ GIR_EraseRootFromParent_Done, |
| 8256 | /* 22975 */ // Label 476: @22975 |
| 8257 | /* 22975 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(23108), // Rule ID 2104 // |
| 8258 | /* 22980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8259 | /* 22983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8260 | /* 22987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8261 | /* 22991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8262 | /* 22995 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8263 | /* 22999 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8264 | /* 23003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8265 | /* 23008 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8266 | /* 23019 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8267 | /* 23023 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8268 | /* 23027 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8269 | /* 23031 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8270 | /* 23035 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8271 | /* 23039 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8272 | /* 23043 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8273 | /* 23047 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8274 | /* 23051 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8275 | /* 23056 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8276 | /* 23060 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8277 | /* 23064 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 8278 | /* 23068 */ // MIs[4] Operand 1 |
| 8279 | /* 23068 */ // No operand predicates |
| 8280 | /* 23068 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8281 | /* 23079 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8282 | /* 23081 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 8283 | /* 23081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8284 | /* 23084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8285 | /* 23086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8286 | /* 23090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 8287 | /* 23094 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8288 | /* 23097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8289 | /* 23100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8290 | /* 23106 */ GIR_RootConstrainSelectedInstOperands, |
| 8291 | /* 23107 */ // GIR_Coverage, 2104, |
| 8292 | /* 23107 */ GIR_EraseRootFromParent_Done, |
| 8293 | /* 23108 */ // Label 477: @23108 |
| 8294 | /* 23108 */ GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(23241), // Rule ID 2386 // |
| 8295 | /* 23113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8296 | /* 23116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8297 | /* 23120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8298 | /* 23124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8299 | /* 23128 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8300 | /* 23132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8301 | /* 23136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8302 | /* 23141 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8303 | /* 23152 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8304 | /* 23156 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8305 | /* 23160 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8306 | /* 23164 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8307 | /* 23168 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8308 | /* 23172 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8309 | /* 23176 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8310 | /* 23180 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8311 | /* 23184 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8312 | /* 23189 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8313 | /* 23193 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8314 | /* 23197 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 8315 | /* 23201 */ // MIs[4] Operand 1 |
| 8316 | /* 23201 */ // No operand predicates |
| 8317 | /* 23201 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8318 | /* 23212 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8319 | /* 23214 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 8320 | /* 23214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8321 | /* 23217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8322 | /* 23219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8323 | /* 23223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 8324 | /* 23227 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8325 | /* 23230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8326 | /* 23233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8327 | /* 23239 */ GIR_RootConstrainSelectedInstOperands, |
| 8328 | /* 23240 */ // GIR_Coverage, 2386, |
| 8329 | /* 23240 */ GIR_EraseRootFromParent_Done, |
| 8330 | /* 23241 */ // Label 478: @23241 |
| 8331 | /* 23241 */ GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(23374), // Rule ID 201 // |
| 8332 | /* 23246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8333 | /* 23249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8334 | /* 23253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8335 | /* 23257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8336 | /* 23261 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8337 | /* 23265 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8338 | /* 23269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8339 | /* 23274 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8340 | /* 23285 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8341 | /* 23289 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8342 | /* 23293 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8343 | /* 23297 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8344 | /* 23301 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8345 | /* 23305 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8346 | /* 23309 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8347 | /* 23313 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8348 | /* 23317 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8349 | /* 23322 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8350 | /* 23326 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8351 | /* 23330 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8352 | /* 23334 */ // MIs[4] Operand 1 |
| 8353 | /* 23334 */ // No operand predicates |
| 8354 | /* 23334 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8355 | /* 23345 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8356 | /* 23347 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8357 | /* 23347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8358 | /* 23350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8359 | /* 23352 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8360 | /* 23356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8361 | /* 23360 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8362 | /* 23363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8363 | /* 23366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8364 | /* 23372 */ GIR_RootConstrainSelectedInstOperands, |
| 8365 | /* 23373 */ // GIR_Coverage, 201, |
| 8366 | /* 23373 */ GIR_EraseRootFromParent_Done, |
| 8367 | /* 23374 */ // Label 479: @23374 |
| 8368 | /* 23374 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(23507), // Rule ID 538 // |
| 8369 | /* 23379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8370 | /* 23382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8371 | /* 23386 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8372 | /* 23390 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8373 | /* 23394 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8374 | /* 23398 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8375 | /* 23402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8376 | /* 23407 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8377 | /* 23418 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8378 | /* 23422 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8379 | /* 23426 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8380 | /* 23430 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8381 | /* 23434 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8382 | /* 23438 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8383 | /* 23442 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8384 | /* 23446 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8385 | /* 23450 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8386 | /* 23455 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8387 | /* 23459 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8388 | /* 23463 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8389 | /* 23467 */ // MIs[4] Operand 1 |
| 8390 | /* 23467 */ // No operand predicates |
| 8391 | /* 23467 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8392 | /* 23478 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8393 | /* 23480 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8394 | /* 23480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8395 | /* 23483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8396 | /* 23485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8397 | /* 23489 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8398 | /* 23493 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8399 | /* 23496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8400 | /* 23499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8401 | /* 23505 */ GIR_RootConstrainSelectedInstOperands, |
| 8402 | /* 23506 */ // GIR_Coverage, 538, |
| 8403 | /* 23506 */ GIR_EraseRootFromParent_Done, |
| 8404 | /* 23507 */ // Label 480: @23507 |
| 8405 | /* 23507 */ GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(23612), // Rule ID 2100 // |
| 8406 | /* 23512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8407 | /* 23515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8408 | /* 23519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8409 | /* 23523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8410 | /* 23527 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8411 | /* 23531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8412 | /* 23535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8413 | /* 23540 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8414 | /* 23551 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8415 | /* 23555 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8416 | /* 23559 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8417 | /* 23563 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8418 | /* 23567 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8419 | /* 23572 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8420 | /* 23583 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8421 | /* 23585 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 8422 | /* 23585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8423 | /* 23588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8424 | /* 23590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8425 | /* 23594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8426 | /* 23598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8427 | /* 23601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8428 | /* 23604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8429 | /* 23610 */ GIR_RootConstrainSelectedInstOperands, |
| 8430 | /* 23611 */ // GIR_Coverage, 2100, |
| 8431 | /* 23611 */ GIR_EraseRootFromParent_Done, |
| 8432 | /* 23612 */ // Label 481: @23612 |
| 8433 | /* 23612 */ GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(23717), // Rule ID 2382 // |
| 8434 | /* 23617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8435 | /* 23620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8436 | /* 23624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8437 | /* 23628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8438 | /* 23632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8439 | /* 23636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8440 | /* 23640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8441 | /* 23645 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8442 | /* 23656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8443 | /* 23660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8444 | /* 23664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8445 | /* 23668 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8446 | /* 23672 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8447 | /* 23677 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8448 | /* 23688 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8449 | /* 23690 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 8450 | /* 23690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8451 | /* 23693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8452 | /* 23695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8453 | /* 23699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8454 | /* 23703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8455 | /* 23706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8456 | /* 23709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8457 | /* 23715 */ GIR_RootConstrainSelectedInstOperands, |
| 8458 | /* 23716 */ // GIR_Coverage, 2382, |
| 8459 | /* 23716 */ GIR_EraseRootFromParent_Done, |
| 8460 | /* 23717 */ // Label 482: @23717 |
| 8461 | /* 23717 */ GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(23822), // Rule ID 6236 // |
| 8462 | /* 23722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8463 | /* 23725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8464 | /* 23729 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8465 | /* 23733 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8466 | /* 23737 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8467 | /* 23741 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8468 | /* 23745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8469 | /* 23750 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8470 | /* 23761 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8471 | /* 23765 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8472 | /* 23769 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8473 | /* 23773 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8474 | /* 23777 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8475 | /* 23782 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8476 | /* 23793 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8477 | /* 23795 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 8478 | /* 23795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8479 | /* 23798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8480 | /* 23800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 8481 | /* 23804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8482 | /* 23808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8483 | /* 23811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8484 | /* 23814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8485 | /* 23820 */ GIR_RootConstrainSelectedInstOperands, |
| 8486 | /* 23821 */ // GIR_Coverage, 6236, |
| 8487 | /* 23821 */ GIR_EraseRootFromParent_Done, |
| 8488 | /* 23822 */ // Label 483: @23822 |
| 8489 | /* 23822 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(23927), // Rule ID 6278 // |
| 8490 | /* 23827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8491 | /* 23830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8492 | /* 23834 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8493 | /* 23838 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8494 | /* 23842 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8495 | /* 23846 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8496 | /* 23850 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8497 | /* 23855 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8498 | /* 23866 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8499 | /* 23870 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8500 | /* 23874 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8501 | /* 23878 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8502 | /* 23882 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8503 | /* 23887 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8504 | /* 23898 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8505 | /* 23900 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 8506 | /* 23900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8507 | /* 23903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8508 | /* 23905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 8509 | /* 23909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8510 | /* 23913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8511 | /* 23916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8512 | /* 23919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8513 | /* 23925 */ GIR_RootConstrainSelectedInstOperands, |
| 8514 | /* 23926 */ // GIR_Coverage, 6278, |
| 8515 | /* 23926 */ GIR_EraseRootFromParent_Done, |
| 8516 | /* 23927 */ // Label 484: @23927 |
| 8517 | /* 23927 */ GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(24033), // Rule ID 2103 // |
| 8518 | /* 23932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8519 | /* 23935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8520 | /* 23939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8521 | /* 23943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8522 | /* 23947 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8523 | /* 23951 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8524 | /* 23955 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8525 | /* 23960 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8526 | /* 23971 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8527 | /* 23975 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8528 | /* 23979 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8529 | /* 23983 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8530 | /* 23987 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8531 | /* 23992 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8532 | /* 23996 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8533 | /* 24000 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8534 | /* 24004 */ // MIs[3] Operand 1 |
| 8535 | /* 24004 */ // No operand predicates |
| 8536 | /* 24004 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8537 | /* 24006 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8538 | /* 24006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8539 | /* 24009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8540 | /* 24011 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8541 | /* 24015 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8542 | /* 24019 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8543 | /* 24022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8544 | /* 24025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8545 | /* 24031 */ GIR_RootConstrainSelectedInstOperands, |
| 8546 | /* 24032 */ // GIR_Coverage, 2103, |
| 8547 | /* 24032 */ GIR_EraseRootFromParent_Done, |
| 8548 | /* 24033 */ // Label 485: @24033 |
| 8549 | /* 24033 */ GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(24139), // Rule ID 2385 // |
| 8550 | /* 24038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8551 | /* 24041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8552 | /* 24045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8553 | /* 24049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8554 | /* 24053 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8555 | /* 24057 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8556 | /* 24061 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8557 | /* 24066 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8558 | /* 24077 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8559 | /* 24081 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8560 | /* 24085 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8561 | /* 24089 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8562 | /* 24093 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8563 | /* 24098 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8564 | /* 24102 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8565 | /* 24106 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8566 | /* 24110 */ // MIs[3] Operand 1 |
| 8567 | /* 24110 */ // No operand predicates |
| 8568 | /* 24110 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8569 | /* 24112 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8570 | /* 24112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8571 | /* 24115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8572 | /* 24117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8573 | /* 24121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8574 | /* 24125 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8575 | /* 24128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8576 | /* 24131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8577 | /* 24137 */ GIR_RootConstrainSelectedInstOperands, |
| 8578 | /* 24138 */ // GIR_Coverage, 2385, |
| 8579 | /* 24138 */ GIR_EraseRootFromParent_Done, |
| 8580 | /* 24139 */ // Label 486: @24139 |
| 8581 | /* 24139 */ GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(24245), // Rule ID 2102 // |
| 8582 | /* 24144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8583 | /* 24147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8584 | /* 24151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8585 | /* 24155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8586 | /* 24159 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8587 | /* 24163 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8588 | /* 24167 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8589 | /* 24172 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8590 | /* 24183 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8591 | /* 24187 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8592 | /* 24191 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8593 | /* 24195 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8594 | /* 24199 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8595 | /* 24204 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8596 | /* 24208 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8597 | /* 24212 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8598 | /* 24216 */ // MIs[3] Operand 1 |
| 8599 | /* 24216 */ // No operand predicates |
| 8600 | /* 24216 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8601 | /* 24218 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8602 | /* 24218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8603 | /* 24221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8604 | /* 24223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8605 | /* 24227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8606 | /* 24231 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8607 | /* 24234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8608 | /* 24237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8609 | /* 24243 */ GIR_RootConstrainSelectedInstOperands, |
| 8610 | /* 24244 */ // GIR_Coverage, 2102, |
| 8611 | /* 24244 */ GIR_EraseRootFromParent_Done, |
| 8612 | /* 24245 */ // Label 487: @24245 |
| 8613 | /* 24245 */ GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(24351), // Rule ID 2384 // |
| 8614 | /* 24250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8615 | /* 24253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8616 | /* 24257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8617 | /* 24261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8618 | /* 24265 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8619 | /* 24269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8620 | /* 24273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8621 | /* 24278 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8622 | /* 24289 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8623 | /* 24293 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8624 | /* 24297 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8625 | /* 24301 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8626 | /* 24305 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8627 | /* 24310 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8628 | /* 24314 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8629 | /* 24318 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8630 | /* 24322 */ // MIs[3] Operand 1 |
| 8631 | /* 24322 */ // No operand predicates |
| 8632 | /* 24322 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8633 | /* 24324 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8634 | /* 24324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8635 | /* 24327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8636 | /* 24329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8637 | /* 24333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8638 | /* 24337 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8639 | /* 24340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8640 | /* 24343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8641 | /* 24349 */ GIR_RootConstrainSelectedInstOperands, |
| 8642 | /* 24350 */ // GIR_Coverage, 2384, |
| 8643 | /* 24350 */ GIR_EraseRootFromParent_Done, |
| 8644 | /* 24351 */ // Label 488: @24351 |
| 8645 | /* 24351 */ GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(24457), // Rule ID 2101 // |
| 8646 | /* 24356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8647 | /* 24359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8648 | /* 24363 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8649 | /* 24367 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8650 | /* 24371 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8651 | /* 24375 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8652 | /* 24379 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8653 | /* 24384 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8654 | /* 24395 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8655 | /* 24399 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8656 | /* 24403 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8657 | /* 24407 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8658 | /* 24411 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8659 | /* 24416 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8660 | /* 24420 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8661 | /* 24424 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8662 | /* 24428 */ // MIs[3] Operand 1 |
| 8663 | /* 24428 */ // No operand predicates |
| 8664 | /* 24428 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8665 | /* 24430 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8666 | /* 24430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8667 | /* 24433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8668 | /* 24435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8669 | /* 24439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8670 | /* 24443 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8671 | /* 24446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8672 | /* 24449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8673 | /* 24455 */ GIR_RootConstrainSelectedInstOperands, |
| 8674 | /* 24456 */ // GIR_Coverage, 2101, |
| 8675 | /* 24456 */ GIR_EraseRootFromParent_Done, |
| 8676 | /* 24457 */ // Label 489: @24457 |
| 8677 | /* 24457 */ GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(24563), // Rule ID 2383 // |
| 8678 | /* 24462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8679 | /* 24465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8680 | /* 24469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8681 | /* 24473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8682 | /* 24477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8683 | /* 24481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8684 | /* 24485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8685 | /* 24490 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8686 | /* 24501 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8687 | /* 24505 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8688 | /* 24509 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8689 | /* 24513 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8690 | /* 24517 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8691 | /* 24522 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8692 | /* 24526 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8693 | /* 24530 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8694 | /* 24534 */ // MIs[3] Operand 1 |
| 8695 | /* 24534 */ // No operand predicates |
| 8696 | /* 24534 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8697 | /* 24536 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8698 | /* 24536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8699 | /* 24539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8700 | /* 24541 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8701 | /* 24545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8702 | /* 24549 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8703 | /* 24552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8704 | /* 24555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8705 | /* 24561 */ GIR_RootConstrainSelectedInstOperands, |
| 8706 | /* 24562 */ // GIR_Coverage, 2383, |
| 8707 | /* 24562 */ GIR_EraseRootFromParent_Done, |
| 8708 | /* 24563 */ // Label 490: @24563 |
| 8709 | /* 24563 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(24669), // Rule ID 6239 // |
| 8710 | /* 24568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8711 | /* 24571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8712 | /* 24575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8713 | /* 24579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8714 | /* 24583 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8715 | /* 24587 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8716 | /* 24591 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8717 | /* 24596 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8718 | /* 24600 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8719 | /* 24604 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8720 | /* 24608 */ // MIs[2] Operand 1 |
| 8721 | /* 24608 */ // No operand predicates |
| 8722 | /* 24608 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8723 | /* 24612 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8724 | /* 24616 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8725 | /* 24620 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8726 | /* 24624 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8727 | /* 24629 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8728 | /* 24640 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8729 | /* 24642 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8730 | /* 24642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8731 | /* 24645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8732 | /* 24647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8733 | /* 24651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8734 | /* 24655 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8735 | /* 24658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8736 | /* 24661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8737 | /* 24667 */ GIR_RootConstrainSelectedInstOperands, |
| 8738 | /* 24668 */ // GIR_Coverage, 6239, |
| 8739 | /* 24668 */ GIR_EraseRootFromParent_Done, |
| 8740 | /* 24669 */ // Label 491: @24669 |
| 8741 | /* 24669 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(24775), // Rule ID 6281 // |
| 8742 | /* 24674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8743 | /* 24677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8744 | /* 24681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8745 | /* 24685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8746 | /* 24689 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8747 | /* 24693 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8748 | /* 24697 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8749 | /* 24702 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8750 | /* 24706 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8751 | /* 24710 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8752 | /* 24714 */ // MIs[2] Operand 1 |
| 8753 | /* 24714 */ // No operand predicates |
| 8754 | /* 24714 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8755 | /* 24718 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8756 | /* 24722 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8757 | /* 24726 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8758 | /* 24730 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8759 | /* 24735 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8760 | /* 24746 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8761 | /* 24748 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8762 | /* 24748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8763 | /* 24751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8764 | /* 24753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8765 | /* 24757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8766 | /* 24761 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8767 | /* 24764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8768 | /* 24767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8769 | /* 24773 */ GIR_RootConstrainSelectedInstOperands, |
| 8770 | /* 24774 */ // GIR_Coverage, 6281, |
| 8771 | /* 24774 */ GIR_EraseRootFromParent_Done, |
| 8772 | /* 24775 */ // Label 492: @24775 |
| 8773 | /* 24775 */ GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(24881), // Rule ID 6238 // |
| 8774 | /* 24780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8775 | /* 24783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8776 | /* 24787 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8777 | /* 24791 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8778 | /* 24795 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8779 | /* 24799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8780 | /* 24803 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8781 | /* 24808 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8782 | /* 24812 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8783 | /* 24816 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8784 | /* 24820 */ // MIs[2] Operand 1 |
| 8785 | /* 24820 */ // No operand predicates |
| 8786 | /* 24820 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8787 | /* 24824 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8788 | /* 24828 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8789 | /* 24832 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8790 | /* 24836 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8791 | /* 24841 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8792 | /* 24852 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8793 | /* 24854 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8794 | /* 24854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8795 | /* 24857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8796 | /* 24859 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8797 | /* 24863 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8798 | /* 24867 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8799 | /* 24870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8800 | /* 24873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8801 | /* 24879 */ GIR_RootConstrainSelectedInstOperands, |
| 8802 | /* 24880 */ // GIR_Coverage, 6238, |
| 8803 | /* 24880 */ GIR_EraseRootFromParent_Done, |
| 8804 | /* 24881 */ // Label 493: @24881 |
| 8805 | /* 24881 */ GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(24987), // Rule ID 6280 // |
| 8806 | /* 24886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8807 | /* 24889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8808 | /* 24893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8809 | /* 24897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8810 | /* 24901 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8811 | /* 24905 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8812 | /* 24909 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8813 | /* 24914 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8814 | /* 24918 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8815 | /* 24922 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8816 | /* 24926 */ // MIs[2] Operand 1 |
| 8817 | /* 24926 */ // No operand predicates |
| 8818 | /* 24926 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8819 | /* 24930 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8820 | /* 24934 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8821 | /* 24938 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8822 | /* 24942 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8823 | /* 24947 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8824 | /* 24958 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8825 | /* 24960 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8826 | /* 24960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8827 | /* 24963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8828 | /* 24965 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8829 | /* 24969 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8830 | /* 24973 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8831 | /* 24976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8832 | /* 24979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8833 | /* 24985 */ GIR_RootConstrainSelectedInstOperands, |
| 8834 | /* 24986 */ // GIR_Coverage, 6280, |
| 8835 | /* 24986 */ GIR_EraseRootFromParent_Done, |
| 8836 | /* 24987 */ // Label 494: @24987 |
| 8837 | /* 24987 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(25093), // Rule ID 6237 // |
| 8838 | /* 24992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 8839 | /* 24995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8840 | /* 24999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8841 | /* 25003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8842 | /* 25007 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8843 | /* 25011 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8844 | /* 25015 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8845 | /* 25020 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8846 | /* 25024 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8847 | /* 25028 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8848 | /* 25032 */ // MIs[2] Operand 1 |
| 8849 | /* 25032 */ // No operand predicates |
| 8850 | /* 25032 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8851 | /* 25036 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8852 | /* 25040 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8853 | /* 25044 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8854 | /* 25048 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8855 | /* 25053 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 8856 | /* 25064 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8857 | /* 25066 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8858 | /* 25066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8859 | /* 25069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8860 | /* 25071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 8861 | /* 25075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8862 | /* 25079 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8863 | /* 25082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8864 | /* 25085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8865 | /* 25091 */ GIR_RootConstrainSelectedInstOperands, |
| 8866 | /* 25092 */ // GIR_Coverage, 6237, |
| 8867 | /* 25092 */ GIR_EraseRootFromParent_Done, |
| 8868 | /* 25093 */ // Label 495: @25093 |
| 8869 | /* 25093 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(25199), // Rule ID 6279 // |
| 8870 | /* 25098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 8871 | /* 25101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8872 | /* 25105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8873 | /* 25109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8874 | /* 25113 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8875 | /* 25117 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8876 | /* 25121 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8877 | /* 25126 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8878 | /* 25130 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8879 | /* 25134 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8880 | /* 25138 */ // MIs[2] Operand 1 |
| 8881 | /* 25138 */ // No operand predicates |
| 8882 | /* 25138 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8883 | /* 25142 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8884 | /* 25146 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8885 | /* 25150 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8886 | /* 25154 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8887 | /* 25159 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 8888 | /* 25170 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8889 | /* 25172 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8890 | /* 25172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8891 | /* 25175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8892 | /* 25177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8893 | /* 25181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8894 | /* 25185 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8895 | /* 25188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8896 | /* 25191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8897 | /* 25197 */ GIR_RootConstrainSelectedInstOperands, |
| 8898 | /* 25198 */ // GIR_Coverage, 6279, |
| 8899 | /* 25198 */ GIR_EraseRootFromParent_Done, |
| 8900 | /* 25199 */ // Label 496: @25199 |
| 8901 | /* 25199 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(25276), // Rule ID 5991 // |
| 8902 | /* 25204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8903 | /* 25207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8904 | /* 25211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8905 | /* 25215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8906 | /* 25219 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8907 | /* 25223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8908 | /* 25227 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 8909 | /* 25231 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8910 | /* 25235 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8911 | /* 25239 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8912 | /* 25243 */ // MIs[2] Operand 1 |
| 8913 | /* 25243 */ // No operand predicates |
| 8914 | /* 25243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8915 | /* 25247 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8916 | /* 25249 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8917 | /* 25249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8918 | /* 25252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8919 | /* 25254 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8920 | /* 25256 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8921 | /* 25259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8922 | /* 25262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8923 | /* 25268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8924 | /* 25274 */ GIR_RootConstrainSelectedInstOperands, |
| 8925 | /* 25275 */ // GIR_Coverage, 5991, |
| 8926 | /* 25275 */ GIR_EraseRootFromParent_Done, |
| 8927 | /* 25276 */ // Label 497: @25276 |
| 8928 | /* 25276 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(25353), // Rule ID 5990 // |
| 8929 | /* 25281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8930 | /* 25284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8931 | /* 25288 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8932 | /* 25292 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8933 | /* 25296 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8934 | /* 25300 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8935 | /* 25304 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8936 | /* 25308 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8937 | /* 25312 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8938 | /* 25316 */ // MIs[2] Operand 1 |
| 8939 | /* 25316 */ // No operand predicates |
| 8940 | /* 25316 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8941 | /* 25320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8942 | /* 25324 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8943 | /* 25326 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8944 | /* 25326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8945 | /* 25329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8946 | /* 25331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8947 | /* 25333 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8948 | /* 25336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8949 | /* 25339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8950 | /* 25345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8951 | /* 25351 */ GIR_RootConstrainSelectedInstOperands, |
| 8952 | /* 25352 */ // GIR_Coverage, 5990, |
| 8953 | /* 25352 */ GIR_EraseRootFromParent_Done, |
| 8954 | /* 25353 */ // Label 498: @25353 |
| 8955 | /* 25353 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(25430), // Rule ID 5989 // |
| 8956 | /* 25358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8957 | /* 25361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8958 | /* 25365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8959 | /* 25369 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8960 | /* 25373 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8961 | /* 25377 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8962 | /* 25381 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8963 | /* 25385 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 8964 | /* 25389 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8965 | /* 25393 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8966 | /* 25397 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8967 | /* 25401 */ // MIs[2] Operand 1 |
| 8968 | /* 25401 */ // No operand predicates |
| 8969 | /* 25401 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8970 | /* 25403 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8971 | /* 25403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8972 | /* 25406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8973 | /* 25408 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8974 | /* 25410 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8975 | /* 25413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8976 | /* 25416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8977 | /* 25422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8978 | /* 25428 */ GIR_RootConstrainSelectedInstOperands, |
| 8979 | /* 25429 */ // GIR_Coverage, 5989, |
| 8980 | /* 25429 */ GIR_EraseRootFromParent_Done, |
| 8981 | /* 25430 */ // Label 499: @25430 |
| 8982 | /* 25430 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(25507), // Rule ID 495 // |
| 8983 | /* 25435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8984 | /* 25438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8985 | /* 25442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8986 | /* 25446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8987 | /* 25450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8988 | /* 25454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8989 | /* 25458 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8990 | /* 25462 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8991 | /* 25466 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8992 | /* 25470 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8993 | /* 25474 */ // MIs[2] Operand 1 |
| 8994 | /* 25474 */ // No operand predicates |
| 8995 | /* 25474 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8996 | /* 25478 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8997 | /* 25480 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8998 | /* 25480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8999 | /* 25483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9000 | /* 25485 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9001 | /* 25487 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 9002 | /* 25490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9003 | /* 25493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9004 | /* 25499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9005 | /* 25505 */ GIR_RootConstrainSelectedInstOperands, |
| 9006 | /* 25506 */ // GIR_Coverage, 495, |
| 9007 | /* 25506 */ GIR_EraseRootFromParent_Done, |
| 9008 | /* 25507 */ // Label 500: @25507 |
| 9009 | /* 25507 */ GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(25578), // Rule ID 5992 // |
| 9010 | /* 25512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9011 | /* 25515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9012 | /* 25519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9013 | /* 25523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9014 | /* 25527 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9015 | /* 25531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9016 | /* 25535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9017 | /* 25540 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 9018 | /* 25544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9019 | /* 25548 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9020 | /* 25550 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 9021 | /* 25550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 9022 | /* 25553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9023 | /* 25555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 9024 | /* 25557 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 9025 | /* 25561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9026 | /* 25564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9027 | /* 25570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9028 | /* 25576 */ GIR_RootConstrainSelectedInstOperands, |
| 9029 | /* 25577 */ // GIR_Coverage, 5992, |
| 9030 | /* 25577 */ GIR_EraseRootFromParent_Done, |
| 9031 | /* 25578 */ // Label 501: @25578 |
| 9032 | /* 25578 */ GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(25649), // Rule ID 496 // |
| 9033 | /* 25583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9034 | /* 25586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9035 | /* 25590 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9036 | /* 25594 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9037 | /* 25598 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9038 | /* 25602 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9039 | /* 25606 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9040 | /* 25610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9041 | /* 25615 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 9042 | /* 25619 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9043 | /* 25621 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 9044 | /* 25621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 9045 | /* 25624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9046 | /* 25626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9047 | /* 25628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 9048 | /* 25632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9049 | /* 25635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9050 | /* 25641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9051 | /* 25647 */ GIR_RootConstrainSelectedInstOperands, |
| 9052 | /* 25648 */ // GIR_Coverage, 496, |
| 9053 | /* 25648 */ GIR_EraseRootFromParent_Done, |
| 9054 | /* 25649 */ // Label 502: @25649 |
| 9055 | /* 25649 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(25704), // Rule ID 2033 // |
| 9056 | /* 25654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 9057 | /* 25657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 9058 | /* 25661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9059 | /* 25665 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 9060 | /* 25676 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 9061 | /* 25676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16), |
| 9062 | /* 25679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9063 | /* 25681 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9064 | /* 25683 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 9065 | /* 25693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9066 | /* 25696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9067 | /* 25702 */ GIR_RootConstrainSelectedInstOperands, |
| 9068 | /* 25703 */ // GIR_Coverage, 2033, |
| 9069 | /* 25703 */ GIR_EraseRootFromParent_Done, |
| 9070 | /* 25704 */ // Label 503: @25704 |
| 9071 | /* 25704 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(25759), // Rule ID 2279 // |
| 9072 | /* 25709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9073 | /* 25712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9074 | /* 25716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9075 | /* 25720 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 9076 | /* 25731 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 9077 | /* 25731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16), |
| 9078 | /* 25734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9079 | /* 25736 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9080 | /* 25738 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 9081 | /* 25748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9082 | /* 25751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9083 | /* 25757 */ GIR_RootConstrainSelectedInstOperands, |
| 9084 | /* 25758 */ // GIR_Coverage, 2279, |
| 9085 | /* 25758 */ GIR_EraseRootFromParent_Done, |
| 9086 | /* 25759 */ // Label 504: @25759 |
| 9087 | /* 25759 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(25816), // Rule ID 150 // |
| 9088 | /* 25764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 9089 | /* 25767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9090 | /* 25771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9091 | /* 25775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9092 | /* 25779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9093 | /* 25783 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 9094 | /* 25787 */ // MIs[1] Operand 1 |
| 9095 | /* 25787 */ // No operand predicates |
| 9096 | /* 25787 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9097 | /* 25789 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9098 | /* 25789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri), |
| 9099 | /* 25792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9100 | /* 25794 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9101 | /* 25796 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9102 | /* 25799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9103 | /* 25802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9104 | /* 25808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9105 | /* 25814 */ GIR_RootConstrainSelectedInstOperands, |
| 9106 | /* 25815 */ // GIR_Coverage, 150, |
| 9107 | /* 25815 */ GIR_EraseRootFromParent_Done, |
| 9108 | /* 25816 */ // Label 505: @25816 |
| 9109 | /* 25816 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(25873), // Rule ID 483 // |
| 9110 | /* 25821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9111 | /* 25824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9112 | /* 25828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9113 | /* 25832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9114 | /* 25836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9115 | /* 25840 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9116 | /* 25844 */ // MIs[1] Operand 1 |
| 9117 | /* 25844 */ // No operand predicates |
| 9118 | /* 25844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9119 | /* 25846 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9120 | /* 25846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri), |
| 9121 | /* 25849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9122 | /* 25851 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9123 | /* 25853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9124 | /* 25856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9125 | /* 25859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9126 | /* 25865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9127 | /* 25871 */ GIR_RootConstrainSelectedInstOperands, |
| 9128 | /* 25872 */ // GIR_Coverage, 483, |
| 9129 | /* 25872 */ GIR_EraseRootFromParent_Done, |
| 9130 | /* 25873 */ // Label 506: @25873 |
| 9131 | /* 25873 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(25919), // Rule ID 151 // |
| 9132 | /* 25878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 9133 | /* 25881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9134 | /* 25885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9135 | /* 25889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9136 | /* 25893 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 9137 | /* 25893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr), |
| 9138 | /* 25896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9139 | /* 25898 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9140 | /* 25900 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9141 | /* 25902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9142 | /* 25905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9143 | /* 25911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9144 | /* 25917 */ GIR_RootConstrainSelectedInstOperands, |
| 9145 | /* 25918 */ // GIR_Coverage, 151, |
| 9146 | /* 25918 */ GIR_EraseRootFromParent_Done, |
| 9147 | /* 25919 */ // Label 507: @25919 |
| 9148 | /* 25919 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(25965), // Rule ID 324 // |
| 9149 | /* 25924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 9150 | /* 25927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9151 | /* 25931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9152 | /* 25935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9153 | /* 25939 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 9154 | /* 25939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR), |
| 9155 | /* 25942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 9156 | /* 25944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 9157 | /* 25950 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9158 | /* 25952 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9159 | /* 25954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9160 | /* 25957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9161 | /* 25963 */ GIR_RootConstrainSelectedInstOperands, |
| 9162 | /* 25964 */ // GIR_Coverage, 324, |
| 9163 | /* 25964 */ GIR_EraseRootFromParent_Done, |
| 9164 | /* 25965 */ // Label 508: @25965 |
| 9165 | /* 25965 */ GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(26011), // Rule ID 484 // |
| 9166 | /* 25970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9167 | /* 25973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9168 | /* 25977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9169 | /* 25981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9170 | /* 25985 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 9171 | /* 25985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 9172 | /* 25988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9173 | /* 25990 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9174 | /* 25992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9175 | /* 25994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9176 | /* 25997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9177 | /* 26003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9178 | /* 26009 */ GIR_RootConstrainSelectedInstOperands, |
| 9179 | /* 26010 */ // GIR_Coverage, 484, |
| 9180 | /* 26010 */ GIR_EraseRootFromParent_Done, |
| 9181 | /* 26011 */ // Label 509: @26011 |
| 9182 | /* 26011 */ GIM_Reject, |
| 9183 | /* 26012 */ // Label 464: @26012 |
| 9184 | /* 26012 */ GIM_Reject, |
| 9185 | /* 26013 */ // Label 451: @26013 |
| 9186 | /* 26013 */ GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(26059), // Rule ID 2906 // |
| 9187 | /* 26018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9188 | /* 26021 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9189 | /* 26024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9190 | /* 26027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9191 | /* 26031 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9192 | /* 26035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9193 | /* 26039 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 9194 | /* 26039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9195 | /* 26042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9196 | /* 26044 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9197 | /* 26046 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9198 | /* 26048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9199 | /* 26051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9200 | /* 26057 */ GIR_RootConstrainSelectedInstOperands, |
| 9201 | /* 26058 */ // GIR_Coverage, 2906, |
| 9202 | /* 26058 */ GIR_EraseRootFromParent_Done, |
| 9203 | /* 26059 */ // Label 510: @26059 |
| 9204 | /* 26059 */ GIM_Reject, |
| 9205 | /* 26060 */ // Label 452: @26060 |
| 9206 | /* 26060 */ GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(26177), // Rule ID 2019 // |
| 9207 | /* 26065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9208 | /* 26068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 9209 | /* 26071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 9210 | /* 26074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9211 | /* 26078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9212 | /* 26082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9213 | /* 26086 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9214 | /* 26086 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9215 | /* 26089 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9216 | /* 26093 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9217 | /* 26098 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9218 | /* 26102 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9219 | /* 26107 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9220 | /* 26110 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9221 | /* 26114 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9222 | /* 26119 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9223 | /* 26123 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9224 | /* 26128 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9225 | /* 26131 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 9226 | /* 26135 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9227 | /* 26140 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9228 | /* 26143 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9229 | /* 26146 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9230 | /* 26149 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9231 | /* 26155 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9232 | /* 26161 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9233 | /* 26163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9234 | /* 26166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9235 | /* 26168 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9236 | /* 26171 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9237 | /* 26176 */ // GIR_Coverage, 2019, |
| 9238 | /* 26176 */ GIR_EraseRootFromParent_Done, |
| 9239 | /* 26177 */ // Label 511: @26177 |
| 9240 | /* 26177 */ GIM_Reject, |
| 9241 | /* 26178 */ // Label 453: @26178 |
| 9242 | /* 26178 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(26224), // Rule ID 1298 // |
| 9243 | /* 26183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9244 | /* 26186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9245 | /* 26189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9246 | /* 26192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9247 | /* 26196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9248 | /* 26200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9249 | /* 26204 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9250 | /* 26204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9251 | /* 26207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9252 | /* 26209 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9253 | /* 26211 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9254 | /* 26213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9255 | /* 26216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9256 | /* 26222 */ GIR_RootConstrainSelectedInstOperands, |
| 9257 | /* 26223 */ // GIR_Coverage, 1298, |
| 9258 | /* 26223 */ GIR_EraseRootFromParent_Done, |
| 9259 | /* 26224 */ // Label 512: @26224 |
| 9260 | /* 26224 */ GIM_Reject, |
| 9261 | /* 26225 */ // Label 454: @26225 |
| 9262 | /* 26225 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(26338), |
| 9263 | /* 26230 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9264 | /* 26233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9265 | /* 26236 */ GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(26276), // Rule ID 2909 // |
| 9266 | /* 26241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9267 | /* 26244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9268 | /* 26248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9269 | /* 26252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9270 | /* 26256 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 9271 | /* 26256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9272 | /* 26259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9273 | /* 26261 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9274 | /* 26263 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9275 | /* 26265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9276 | /* 26268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9277 | /* 26274 */ GIR_RootConstrainSelectedInstOperands, |
| 9278 | /* 26275 */ // GIR_Coverage, 2909, |
| 9279 | /* 26275 */ GIR_EraseRootFromParent_Done, |
| 9280 | /* 26276 */ // Label 514: @26276 |
| 9281 | /* 26276 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(26337), // Rule ID 3766 // |
| 9282 | /* 26281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9283 | /* 26284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9284 | /* 26288 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9285 | /* 26292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9286 | /* 26296 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 9287 | /* 26296 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9288 | /* 26299 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9289 | /* 26303 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9290 | /* 26308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9291 | /* 26311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9292 | /* 26313 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9293 | /* 26315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9294 | /* 26317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9295 | /* 26320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9296 | /* 26326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9297 | /* 26332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9298 | /* 26335 */ GIR_RootConstrainSelectedInstOperands, |
| 9299 | /* 26336 */ // GIR_Coverage, 3766, |
| 9300 | /* 26336 */ GIR_EraseRootFromParent_Done, |
| 9301 | /* 26337 */ // Label 515: @26337 |
| 9302 | /* 26337 */ GIM_Reject, |
| 9303 | /* 26338 */ // Label 513: @26338 |
| 9304 | /* 26338 */ GIM_Reject, |
| 9305 | /* 26339 */ // Label 455: @26339 |
| 9306 | /* 26339 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(26456), // Rule ID 2020 // |
| 9307 | /* 26344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9308 | /* 26347 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 9309 | /* 26350 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 9310 | /* 26353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9311 | /* 26357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9312 | /* 26361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9313 | /* 26365 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9314 | /* 26365 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9315 | /* 26368 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9316 | /* 26372 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9317 | /* 26377 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9318 | /* 26381 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9319 | /* 26386 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9320 | /* 26389 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9321 | /* 26393 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9322 | /* 26398 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9323 | /* 26402 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9324 | /* 26407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9325 | /* 26410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 9326 | /* 26414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9327 | /* 26419 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9328 | /* 26422 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9329 | /* 26425 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9330 | /* 26428 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9331 | /* 26434 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9332 | /* 26440 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9333 | /* 26442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9334 | /* 26445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9335 | /* 26447 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9336 | /* 26450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9337 | /* 26455 */ // GIR_Coverage, 2020, |
| 9338 | /* 26455 */ GIR_EraseRootFromParent_Done, |
| 9339 | /* 26456 */ // Label 516: @26456 |
| 9340 | /* 26456 */ GIM_Reject, |
| 9341 | /* 26457 */ // Label 456: @26457 |
| 9342 | /* 26457 */ GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(26503), // Rule ID 2905 // |
| 9343 | /* 26462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9344 | /* 26465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9345 | /* 26468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9346 | /* 26471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9347 | /* 26475 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9348 | /* 26479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9349 | /* 26483 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 9350 | /* 26483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9351 | /* 26486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9352 | /* 26488 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9353 | /* 26490 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9354 | /* 26492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9355 | /* 26495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9356 | /* 26501 */ GIR_RootConstrainSelectedInstOperands, |
| 9357 | /* 26502 */ // GIR_Coverage, 2905, |
| 9358 | /* 26502 */ GIR_EraseRootFromParent_Done, |
| 9359 | /* 26503 */ // Label 517: @26503 |
| 9360 | /* 26503 */ GIM_Reject, |
| 9361 | /* 26504 */ // Label 457: @26504 |
| 9362 | /* 26504 */ GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(26617), |
| 9363 | /* 26509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9364 | /* 26512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9365 | /* 26515 */ GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(26555), // Rule ID 1299 // |
| 9366 | /* 26520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9367 | /* 26523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9368 | /* 26527 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9369 | /* 26531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9370 | /* 26535 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9371 | /* 26535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9372 | /* 26538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9373 | /* 26540 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9374 | /* 26542 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9375 | /* 26544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9376 | /* 26547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9377 | /* 26553 */ GIR_RootConstrainSelectedInstOperands, |
| 9378 | /* 26554 */ // GIR_Coverage, 1299, |
| 9379 | /* 26554 */ GIR_EraseRootFromParent_Done, |
| 9380 | /* 26555 */ // Label 519: @26555 |
| 9381 | /* 26555 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(26616), // Rule ID 3762 // |
| 9382 | /* 26560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9383 | /* 26563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9384 | /* 26567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9385 | /* 26571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9386 | /* 26575 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9387 | /* 26575 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9388 | /* 26578 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9389 | /* 26582 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9390 | /* 26587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9391 | /* 26590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9392 | /* 26592 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9393 | /* 26594 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9394 | /* 26596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9395 | /* 26599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9396 | /* 26605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9397 | /* 26611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9398 | /* 26614 */ GIR_RootConstrainSelectedInstOperands, |
| 9399 | /* 26615 */ // GIR_Coverage, 3762, |
| 9400 | /* 26615 */ GIR_EraseRootFromParent_Done, |
| 9401 | /* 26616 */ // Label 520: @26616 |
| 9402 | /* 26616 */ GIM_Reject, |
| 9403 | /* 26617 */ // Label 518: @26617 |
| 9404 | /* 26617 */ GIM_Reject, |
| 9405 | /* 26618 */ // Label 458: @26618 |
| 9406 | /* 26618 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(26735), // Rule ID 2021 // |
| 9407 | /* 26623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9408 | /* 26626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 9409 | /* 26629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 9410 | /* 26632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9411 | /* 26636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9412 | /* 26640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9413 | /* 26644 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9414 | /* 26644 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9415 | /* 26647 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9416 | /* 26651 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9417 | /* 26656 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9418 | /* 26660 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9419 | /* 26665 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9420 | /* 26668 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9421 | /* 26672 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9422 | /* 26677 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9423 | /* 26681 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9424 | /* 26686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9425 | /* 26689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 9426 | /* 26693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9427 | /* 26698 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9428 | /* 26701 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9429 | /* 26704 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9430 | /* 26707 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9431 | /* 26713 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9432 | /* 26719 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9433 | /* 26721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9434 | /* 26724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9435 | /* 26726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9436 | /* 26729 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9437 | /* 26734 */ // GIR_Coverage, 2021, |
| 9438 | /* 26734 */ GIR_EraseRootFromParent_Done, |
| 9439 | /* 26735 */ // Label 521: @26735 |
| 9440 | /* 26735 */ GIM_Reject, |
| 9441 | /* 26736 */ // Label 459: @26736 |
| 9442 | /* 26736 */ GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(26782), // Rule ID 2904 // |
| 9443 | /* 26741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9444 | /* 26744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9445 | /* 26747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9446 | /* 26750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9447 | /* 26754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9448 | /* 26758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9449 | /* 26762 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 9450 | /* 26762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9451 | /* 26765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9452 | /* 26767 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9453 | /* 26769 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9454 | /* 26771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9455 | /* 26774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9456 | /* 26780 */ GIR_RootConstrainSelectedInstOperands, |
| 9457 | /* 26781 */ // GIR_Coverage, 2904, |
| 9458 | /* 26781 */ GIR_EraseRootFromParent_Done, |
| 9459 | /* 26782 */ // Label 522: @26782 |
| 9460 | /* 26782 */ GIM_Reject, |
| 9461 | /* 26783 */ // Label 460: @26783 |
| 9462 | /* 26783 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(26896), |
| 9463 | /* 26788 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9464 | /* 26791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9465 | /* 26794 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(26834), // Rule ID 2908 // |
| 9466 | /* 26799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9467 | /* 26802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9468 | /* 26806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9469 | /* 26810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9470 | /* 26814 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 9471 | /* 26814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9472 | /* 26817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9473 | /* 26819 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9474 | /* 26821 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9475 | /* 26823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9476 | /* 26826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9477 | /* 26832 */ GIR_RootConstrainSelectedInstOperands, |
| 9478 | /* 26833 */ // GIR_Coverage, 2908, |
| 9479 | /* 26833 */ GIR_EraseRootFromParent_Done, |
| 9480 | /* 26834 */ // Label 524: @26834 |
| 9481 | /* 26834 */ GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(26895), // Rule ID 3758 // |
| 9482 | /* 26839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9483 | /* 26842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9484 | /* 26846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9485 | /* 26850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9486 | /* 26854 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9487 | /* 26854 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9488 | /* 26857 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9489 | /* 26861 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9490 | /* 26866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9491 | /* 26869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9492 | /* 26871 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9493 | /* 26873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9494 | /* 26875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9495 | /* 26878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9496 | /* 26884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9497 | /* 26890 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9498 | /* 26893 */ GIR_RootConstrainSelectedInstOperands, |
| 9499 | /* 26894 */ // GIR_Coverage, 3758, |
| 9500 | /* 26894 */ GIR_EraseRootFromParent_Done, |
| 9501 | /* 26895 */ // Label 525: @26895 |
| 9502 | /* 26895 */ GIM_Reject, |
| 9503 | /* 26896 */ // Label 523: @26896 |
| 9504 | /* 26896 */ GIM_Reject, |
| 9505 | /* 26897 */ // Label 461: @26897 |
| 9506 | /* 26897 */ GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(27014), // Rule ID 2022 // |
| 9507 | /* 26902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9508 | /* 26905 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 9509 | /* 26908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 9510 | /* 26911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9511 | /* 26915 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9512 | /* 26919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9513 | /* 26923 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9514 | /* 26923 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9515 | /* 26926 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9516 | /* 26930 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9517 | /* 26935 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9518 | /* 26939 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9519 | /* 26944 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9520 | /* 26947 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9521 | /* 26951 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9522 | /* 26956 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9523 | /* 26960 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9524 | /* 26965 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9525 | /* 26968 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 9526 | /* 26972 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9527 | /* 26977 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9528 | /* 26980 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9529 | /* 26983 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9530 | /* 26986 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9531 | /* 26992 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9532 | /* 26998 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9533 | /* 27000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9534 | /* 27003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9535 | /* 27005 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9536 | /* 27008 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9537 | /* 27013 */ // GIR_Coverage, 2022, |
| 9538 | /* 27013 */ GIR_EraseRootFromParent_Done, |
| 9539 | /* 27014 */ // Label 526: @27014 |
| 9540 | /* 27014 */ GIM_Reject, |
| 9541 | /* 27015 */ // Label 462: @27015 |
| 9542 | /* 27015 */ GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(27128), |
| 9543 | /* 27020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9544 | /* 27023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9545 | /* 27026 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(27066), // Rule ID 2907 // |
| 9546 | /* 27031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9547 | /* 27034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9548 | /* 27038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9549 | /* 27042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9550 | /* 27046 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 9551 | /* 27046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9552 | /* 27049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9553 | /* 27051 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9554 | /* 27053 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9555 | /* 27055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9556 | /* 27058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9557 | /* 27064 */ GIR_RootConstrainSelectedInstOperands, |
| 9558 | /* 27065 */ // GIR_Coverage, 2907, |
| 9559 | /* 27065 */ GIR_EraseRootFromParent_Done, |
| 9560 | /* 27066 */ // Label 528: @27066 |
| 9561 | /* 27066 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(27127), // Rule ID 3754 // |
| 9562 | /* 27071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9563 | /* 27074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9564 | /* 27078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9565 | /* 27082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9566 | /* 27086 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9567 | /* 27086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9568 | /* 27089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9569 | /* 27093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9570 | /* 27098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9571 | /* 27101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9572 | /* 27103 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9573 | /* 27105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9574 | /* 27107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9575 | /* 27110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9576 | /* 27116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9577 | /* 27122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9578 | /* 27125 */ GIR_RootConstrainSelectedInstOperands, |
| 9579 | /* 27126 */ // GIR_Coverage, 3754, |
| 9580 | /* 27126 */ GIR_EraseRootFromParent_Done, |
| 9581 | /* 27127 */ // Label 529: @27127 |
| 9582 | /* 27127 */ GIM_Reject, |
| 9583 | /* 27128 */ // Label 527: @27128 |
| 9584 | /* 27128 */ GIM_Reject, |
| 9585 | /* 27129 */ // Label 463: @27129 |
| 9586 | /* 27129 */ GIM_Reject, |
| 9587 | /* 27130 */ // Label 7: @27130 |
| 9588 | /* 27130 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 543*/ GIMT_Encode4(28824), |
| 9589 | /* 27141 */ /*GILLT_s32*//*Label 530*/ GIMT_Encode4(27201), |
| 9590 | /* 27145 */ /*GILLT_s64*//*Label 531*/ GIMT_Encode4(27708), |
| 9591 | /* 27149 */ /*GILLT_v2s1*//*Label 532*/ GIMT_Encode4(27755), |
| 9592 | /* 27153 */ /*GILLT_v2s32*//*Label 533*/ GIMT_Encode4(27873), |
| 9593 | /* 27157 */ /*GILLT_v2s64*//*Label 534*/ GIMT_Encode4(27920), |
| 9594 | /* 27161 */ /*GILLT_v4s1*//*Label 535*/ GIMT_Encode4(28034), |
| 9595 | /* 27165 */ /*GILLT_v4s16*//*Label 536*/ GIMT_Encode4(28152), |
| 9596 | /* 27169 */ /*GILLT_v4s32*//*Label 537*/ GIMT_Encode4(28199), GIMT_Encode4(0), |
| 9597 | /* 27177 */ /*GILLT_v8s1*//*Label 538*/ GIMT_Encode4(28313), |
| 9598 | /* 27181 */ /*GILLT_v8s8*//*Label 539*/ GIMT_Encode4(28431), |
| 9599 | /* 27185 */ /*GILLT_v8s16*//*Label 540*/ GIMT_Encode4(28478), GIMT_Encode4(0), |
| 9600 | /* 27193 */ /*GILLT_v16s1*//*Label 541*/ GIMT_Encode4(28592), |
| 9601 | /* 27197 */ /*GILLT_v16s8*//*Label 542*/ GIMT_Encode4(28710), |
| 9602 | /* 27201 */ // Label 530: @27201 |
| 9603 | /* 27201 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(27707), |
| 9604 | /* 27206 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 9605 | /* 27209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9606 | /* 27212 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(27267), // Rule ID 5994 // |
| 9607 | /* 27217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9608 | /* 27220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9609 | /* 27224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 255, |
| 9610 | /* 27228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9611 | /* 27232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9612 | /* 27236 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9613 | /* 27240 */ // MIs[1] Operand 1 |
| 9614 | /* 27240 */ // No operand predicates |
| 9615 | /* 27240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9616 | /* 27242 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 9617 | /* 27242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 9618 | /* 27245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9619 | /* 27247 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9620 | /* 27250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9621 | /* 27253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9622 | /* 27259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9623 | /* 27265 */ GIR_RootConstrainSelectedInstOperands, |
| 9624 | /* 27266 */ // GIR_Coverage, 5994, |
| 9625 | /* 27266 */ GIR_EraseRootFromParent_Done, |
| 9626 | /* 27267 */ // Label 545: @27267 |
| 9627 | /* 27267 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(27322), // Rule ID 498 // |
| 9628 | /* 27272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9629 | /* 27275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9630 | /* 27279 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9631 | /* 27283 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9632 | /* 27287 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9633 | /* 27291 */ // MIs[1] Operand 1 |
| 9634 | /* 27291 */ // No operand predicates |
| 9635 | /* 27291 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9636 | /* 27295 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9637 | /* 27297 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 9638 | /* 27297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 9639 | /* 27300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9640 | /* 27302 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9641 | /* 27305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9642 | /* 27308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9643 | /* 27314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9644 | /* 27320 */ GIR_RootConstrainSelectedInstOperands, |
| 9645 | /* 27321 */ // GIR_Coverage, 498, |
| 9646 | /* 27321 */ GIR_EraseRootFromParent_Done, |
| 9647 | /* 27322 */ // Label 546: @27322 |
| 9648 | /* 27322 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(27366), // Rule ID 499 // |
| 9649 | /* 27327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9650 | /* 27330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9651 | /* 27334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9652 | /* 27338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9653 | /* 27342 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 9654 | /* 27342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr), |
| 9655 | /* 27345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9656 | /* 27347 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 9657 | /* 27349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9658 | /* 27352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9659 | /* 27358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9660 | /* 27364 */ GIR_RootConstrainSelectedInstOperands, |
| 9661 | /* 27365 */ // GIR_Coverage, 499, |
| 9662 | /* 27365 */ GIR_EraseRootFromParent_Done, |
| 9663 | /* 27366 */ // Label 547: @27366 |
| 9664 | /* 27366 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(27410), // Rule ID 164 // |
| 9665 | /* 27371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 9666 | /* 27374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9667 | /* 27378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9668 | /* 27382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9669 | /* 27386 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 9670 | /* 27386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr), |
| 9671 | /* 27389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9672 | /* 27391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 9673 | /* 27393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9674 | /* 27396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9675 | /* 27402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9676 | /* 27408 */ GIR_RootConstrainSelectedInstOperands, |
| 9677 | /* 27409 */ // GIR_Coverage, 164, |
| 9678 | /* 27409 */ GIR_EraseRootFromParent_Done, |
| 9679 | /* 27410 */ // Label 548: @27410 |
| 9680 | /* 27410 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(27454), // Rule ID 323 // |
| 9681 | /* 27415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 9682 | /* 27418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9683 | /* 27422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9684 | /* 27426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9685 | /* 27430 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 9686 | /* 27430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN), |
| 9687 | /* 27433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9688 | /* 27435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 9689 | /* 27441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9690 | /* 27443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9691 | /* 27446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9692 | /* 27452 */ GIR_RootConstrainSelectedInstOperands, |
| 9693 | /* 27453 */ // GIR_Coverage, 323, |
| 9694 | /* 27453 */ GIR_EraseRootFromParent_Done, |
| 9695 | /* 27454 */ // Label 549: @27454 |
| 9696 | /* 27454 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(27511), // Rule ID 154 // |
| 9697 | /* 27459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 9698 | /* 27462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9699 | /* 27466 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9700 | /* 27470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9701 | /* 27474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9702 | /* 27478 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 9703 | /* 27482 */ // MIs[1] Operand 1 |
| 9704 | /* 27482 */ // No operand predicates |
| 9705 | /* 27482 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9706 | /* 27484 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9707 | /* 27484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri), |
| 9708 | /* 27487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9709 | /* 27489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9710 | /* 27491 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9711 | /* 27494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9712 | /* 27497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9713 | /* 27503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9714 | /* 27509 */ GIR_RootConstrainSelectedInstOperands, |
| 9715 | /* 27510 */ // GIR_Coverage, 154, |
| 9716 | /* 27510 */ GIR_EraseRootFromParent_Done, |
| 9717 | /* 27511 */ // Label 550: @27511 |
| 9718 | /* 27511 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(27568), // Rule ID 486 // |
| 9719 | /* 27516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9720 | /* 27519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9721 | /* 27523 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9722 | /* 27527 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9723 | /* 27531 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9724 | /* 27535 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9725 | /* 27539 */ // MIs[1] Operand 1 |
| 9726 | /* 27539 */ // No operand predicates |
| 9727 | /* 27539 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9728 | /* 27541 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9729 | /* 27541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri), |
| 9730 | /* 27544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9731 | /* 27546 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9732 | /* 27548 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9733 | /* 27551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9734 | /* 27554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9735 | /* 27560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9736 | /* 27566 */ GIR_RootConstrainSelectedInstOperands, |
| 9737 | /* 27567 */ // GIR_Coverage, 486, |
| 9738 | /* 27567 */ GIR_EraseRootFromParent_Done, |
| 9739 | /* 27568 */ // Label 551: @27568 |
| 9740 | /* 27568 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(27614), // Rule ID 155 // |
| 9741 | /* 27573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 9742 | /* 27576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9743 | /* 27580 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9744 | /* 27584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9745 | /* 27588 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 9746 | /* 27588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr), |
| 9747 | /* 27591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9748 | /* 27593 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9749 | /* 27595 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9750 | /* 27597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9751 | /* 27600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9752 | /* 27606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9753 | /* 27612 */ GIR_RootConstrainSelectedInstOperands, |
| 9754 | /* 27613 */ // GIR_Coverage, 155, |
| 9755 | /* 27613 */ GIR_EraseRootFromParent_Done, |
| 9756 | /* 27614 */ // Label 552: @27614 |
| 9757 | /* 27614 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(27660), // Rule ID 316 // |
| 9758 | /* 27619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 9759 | /* 27622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9760 | /* 27626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9761 | /* 27630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9762 | /* 27634 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 9763 | /* 27634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR), |
| 9764 | /* 27637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 9765 | /* 27639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 9766 | /* 27645 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9767 | /* 27647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9768 | /* 27649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9769 | /* 27652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9770 | /* 27658 */ GIR_RootConstrainSelectedInstOperands, |
| 9771 | /* 27659 */ // GIR_Coverage, 316, |
| 9772 | /* 27659 */ GIR_EraseRootFromParent_Done, |
| 9773 | /* 27660 */ // Label 553: @27660 |
| 9774 | /* 27660 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(27706), // Rule ID 487 // |
| 9775 | /* 27665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 9776 | /* 27668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9777 | /* 27672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9778 | /* 27676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9779 | /* 27680 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 9780 | /* 27680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9781 | /* 27683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9782 | /* 27685 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9783 | /* 27687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9784 | /* 27689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9785 | /* 27692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9786 | /* 27698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9787 | /* 27704 */ GIR_RootConstrainSelectedInstOperands, |
| 9788 | /* 27705 */ // GIR_Coverage, 487, |
| 9789 | /* 27705 */ GIR_EraseRootFromParent_Done, |
| 9790 | /* 27706 */ // Label 554: @27706 |
| 9791 | /* 27706 */ GIM_Reject, |
| 9792 | /* 27707 */ // Label 544: @27707 |
| 9793 | /* 27707 */ GIM_Reject, |
| 9794 | /* 27708 */ // Label 531: @27708 |
| 9795 | /* 27708 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(27754), // Rule ID 2912 // |
| 9796 | /* 27713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9797 | /* 27716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9798 | /* 27719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9799 | /* 27722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9800 | /* 27726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9801 | /* 27730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9802 | /* 27734 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 9803 | /* 27734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9804 | /* 27737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9805 | /* 27739 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9806 | /* 27741 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9807 | /* 27743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9808 | /* 27746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9809 | /* 27752 */ GIR_RootConstrainSelectedInstOperands, |
| 9810 | /* 27753 */ // GIR_Coverage, 2912, |
| 9811 | /* 27753 */ GIR_EraseRootFromParent_Done, |
| 9812 | /* 27754 */ // Label 555: @27754 |
| 9813 | /* 27754 */ GIM_Reject, |
| 9814 | /* 27755 */ // Label 532: @27755 |
| 9815 | /* 27755 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(27872), // Rule ID 2015 // |
| 9816 | /* 27760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9817 | /* 27763 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 9818 | /* 27766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 9819 | /* 27769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9820 | /* 27773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9821 | /* 27777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9822 | /* 27781 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9823 | /* 27781 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9824 | /* 27784 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9825 | /* 27788 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9826 | /* 27793 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9827 | /* 27797 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9828 | /* 27802 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9829 | /* 27805 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9830 | /* 27809 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9831 | /* 27814 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9832 | /* 27818 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9833 | /* 27823 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9834 | /* 27826 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9835 | /* 27830 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9836 | /* 27835 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9837 | /* 27838 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9838 | /* 27841 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9839 | /* 27844 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9840 | /* 27850 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9841 | /* 27856 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9842 | /* 27858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9843 | /* 27861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9844 | /* 27863 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9845 | /* 27866 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9846 | /* 27871 */ // GIR_Coverage, 2015, |
| 9847 | /* 27871 */ GIR_EraseRootFromParent_Done, |
| 9848 | /* 27872 */ // Label 556: @27872 |
| 9849 | /* 27872 */ GIM_Reject, |
| 9850 | /* 27873 */ // Label 533: @27873 |
| 9851 | /* 27873 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(27919), // Rule ID 1296 // |
| 9852 | /* 27878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9853 | /* 27881 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9854 | /* 27884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9855 | /* 27887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9856 | /* 27891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9857 | /* 27895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9858 | /* 27899 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9859 | /* 27899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9860 | /* 27902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9861 | /* 27904 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9862 | /* 27906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9863 | /* 27908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9864 | /* 27911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9865 | /* 27917 */ GIR_RootConstrainSelectedInstOperands, |
| 9866 | /* 27918 */ // GIR_Coverage, 1296, |
| 9867 | /* 27918 */ GIR_EraseRootFromParent_Done, |
| 9868 | /* 27919 */ // Label 557: @27919 |
| 9869 | /* 27919 */ GIM_Reject, |
| 9870 | /* 27920 */ // Label 534: @27920 |
| 9871 | /* 27920 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(28033), |
| 9872 | /* 27925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9873 | /* 27928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9874 | /* 27931 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(27971), // Rule ID 2915 // |
| 9875 | /* 27936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9876 | /* 27939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9877 | /* 27943 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9878 | /* 27947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9879 | /* 27951 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 9880 | /* 27951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9881 | /* 27954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9882 | /* 27956 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9883 | /* 27958 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9884 | /* 27960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9885 | /* 27963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9886 | /* 27969 */ GIR_RootConstrainSelectedInstOperands, |
| 9887 | /* 27970 */ // GIR_Coverage, 2915, |
| 9888 | /* 27970 */ GIR_EraseRootFromParent_Done, |
| 9889 | /* 27971 */ // Label 559: @27971 |
| 9890 | /* 27971 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(28032), // Rule ID 3780 // |
| 9891 | /* 27976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9892 | /* 27979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9893 | /* 27983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9894 | /* 27987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9895 | /* 27991 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 9896 | /* 27991 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9897 | /* 27994 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9898 | /* 27998 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9899 | /* 28003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9900 | /* 28006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9901 | /* 28008 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9902 | /* 28010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9903 | /* 28012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9904 | /* 28015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9905 | /* 28021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9906 | /* 28027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9907 | /* 28030 */ GIR_RootConstrainSelectedInstOperands, |
| 9908 | /* 28031 */ // GIR_Coverage, 3780, |
| 9909 | /* 28031 */ GIR_EraseRootFromParent_Done, |
| 9910 | /* 28032 */ // Label 560: @28032 |
| 9911 | /* 28032 */ GIM_Reject, |
| 9912 | /* 28033 */ // Label 558: @28033 |
| 9913 | /* 28033 */ GIM_Reject, |
| 9914 | /* 28034 */ // Label 535: @28034 |
| 9915 | /* 28034 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(28151), // Rule ID 2016 // |
| 9916 | /* 28039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9917 | /* 28042 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 9918 | /* 28045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 9919 | /* 28048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9920 | /* 28052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9921 | /* 28056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9922 | /* 28060 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9923 | /* 28060 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9924 | /* 28063 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9925 | /* 28067 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9926 | /* 28072 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9927 | /* 28076 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9928 | /* 28081 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9929 | /* 28084 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9930 | /* 28088 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9931 | /* 28093 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9932 | /* 28097 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9933 | /* 28102 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9934 | /* 28105 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9935 | /* 28109 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9936 | /* 28114 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9937 | /* 28117 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9938 | /* 28120 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9939 | /* 28123 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9940 | /* 28129 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9941 | /* 28135 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9942 | /* 28137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9943 | /* 28140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9944 | /* 28142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9945 | /* 28145 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9946 | /* 28150 */ // GIR_Coverage, 2016, |
| 9947 | /* 28150 */ GIR_EraseRootFromParent_Done, |
| 9948 | /* 28151 */ // Label 561: @28151 |
| 9949 | /* 28151 */ GIM_Reject, |
| 9950 | /* 28152 */ // Label 536: @28152 |
| 9951 | /* 28152 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(28198), // Rule ID 2911 // |
| 9952 | /* 28157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9953 | /* 28160 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9954 | /* 28163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9955 | /* 28166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9956 | /* 28170 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9957 | /* 28174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9958 | /* 28178 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 9959 | /* 28178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9960 | /* 28181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9961 | /* 28183 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9962 | /* 28185 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9963 | /* 28187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9964 | /* 28190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9965 | /* 28196 */ GIR_RootConstrainSelectedInstOperands, |
| 9966 | /* 28197 */ // GIR_Coverage, 2911, |
| 9967 | /* 28197 */ GIR_EraseRootFromParent_Done, |
| 9968 | /* 28198 */ // Label 562: @28198 |
| 9969 | /* 28198 */ GIM_Reject, |
| 9970 | /* 28199 */ // Label 537: @28199 |
| 9971 | /* 28199 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(28312), |
| 9972 | /* 28204 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9973 | /* 28207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9974 | /* 28210 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(28250), // Rule ID 1297 // |
| 9975 | /* 28215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9976 | /* 28218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9977 | /* 28222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9978 | /* 28226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9979 | /* 28230 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9980 | /* 28230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9981 | /* 28233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9982 | /* 28235 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9983 | /* 28237 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9984 | /* 28239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9985 | /* 28242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9986 | /* 28248 */ GIR_RootConstrainSelectedInstOperands, |
| 9987 | /* 28249 */ // GIR_Coverage, 1297, |
| 9988 | /* 28249 */ GIR_EraseRootFromParent_Done, |
| 9989 | /* 28250 */ // Label 564: @28250 |
| 9990 | /* 28250 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(28311), // Rule ID 3776 // |
| 9991 | /* 28255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9992 | /* 28258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9993 | /* 28262 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9994 | /* 28266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9995 | /* 28270 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9996 | /* 28270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9997 | /* 28273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9998 | /* 28277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9999 | /* 28282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 10000 | /* 28285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10001 | /* 28287 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10002 | /* 28289 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10003 | /* 28291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10004 | /* 28294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10005 | /* 28300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10006 | /* 28306 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10007 | /* 28309 */ GIR_RootConstrainSelectedInstOperands, |
| 10008 | /* 28310 */ // GIR_Coverage, 3776, |
| 10009 | /* 28310 */ GIR_EraseRootFromParent_Done, |
| 10010 | /* 28311 */ // Label 565: @28311 |
| 10011 | /* 28311 */ GIM_Reject, |
| 10012 | /* 28312 */ // Label 563: @28312 |
| 10013 | /* 28312 */ GIM_Reject, |
| 10014 | /* 28313 */ // Label 538: @28313 |
| 10015 | /* 28313 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(28430), // Rule ID 2017 // |
| 10016 | /* 28318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10017 | /* 28321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 10018 | /* 28324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 10019 | /* 28327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 10020 | /* 28331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 10021 | /* 28335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 10022 | /* 28339 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 10023 | /* 28339 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 10024 | /* 28342 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10025 | /* 28346 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10026 | /* 28351 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 10027 | /* 28355 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 10028 | /* 28360 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 10029 | /* 28363 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10030 | /* 28367 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10031 | /* 28372 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 10032 | /* 28376 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 10033 | /* 28381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 10034 | /* 28384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 10035 | /* 28388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10036 | /* 28393 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10037 | /* 28396 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 10038 | /* 28399 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 10039 | /* 28402 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10040 | /* 28408 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10041 | /* 28414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10042 | /* 28416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10043 | /* 28419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10044 | /* 28421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10045 | /* 28424 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 10046 | /* 28429 */ // GIR_Coverage, 2017, |
| 10047 | /* 28429 */ GIR_EraseRootFromParent_Done, |
| 10048 | /* 28430 */ // Label 566: @28430 |
| 10049 | /* 28430 */ GIM_Reject, |
| 10050 | /* 28431 */ // Label 539: @28431 |
| 10051 | /* 28431 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(28477), // Rule ID 2910 // |
| 10052 | /* 28436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10053 | /* 28439 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10054 | /* 28442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 10055 | /* 28445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10056 | /* 28449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10057 | /* 28453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10058 | /* 28457 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 10059 | /* 28457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 10060 | /* 28460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10061 | /* 28462 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 10062 | /* 28464 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 10063 | /* 28466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10064 | /* 28469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10065 | /* 28475 */ GIR_RootConstrainSelectedInstOperands, |
| 10066 | /* 28476 */ // GIR_Coverage, 2910, |
| 10067 | /* 28476 */ GIR_EraseRootFromParent_Done, |
| 10068 | /* 28477 */ // Label 567: @28477 |
| 10069 | /* 28477 */ GIM_Reject, |
| 10070 | /* 28478 */ // Label 540: @28478 |
| 10071 | /* 28478 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(28591), |
| 10072 | /* 28483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10073 | /* 28486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10074 | /* 28489 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(28529), // Rule ID 2914 // |
| 10075 | /* 28494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10076 | /* 28497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10077 | /* 28501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10078 | /* 28505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10079 | /* 28509 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 10080 | /* 28509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 10081 | /* 28512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10082 | /* 28514 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 10083 | /* 28516 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 10084 | /* 28518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10085 | /* 28521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10086 | /* 28527 */ GIR_RootConstrainSelectedInstOperands, |
| 10087 | /* 28528 */ // GIR_Coverage, 2914, |
| 10088 | /* 28528 */ GIR_EraseRootFromParent_Done, |
| 10089 | /* 28529 */ // Label 569: @28529 |
| 10090 | /* 28529 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(28590), // Rule ID 3772 // |
| 10091 | /* 28534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10092 | /* 28537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10093 | /* 28541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10094 | /* 28545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10095 | /* 28549 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10096 | /* 28549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10097 | /* 28552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10098 | /* 28556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10099 | /* 28561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 10100 | /* 28564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10101 | /* 28566 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10102 | /* 28568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10103 | /* 28570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10104 | /* 28573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10105 | /* 28579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10106 | /* 28585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10107 | /* 28588 */ GIR_RootConstrainSelectedInstOperands, |
| 10108 | /* 28589 */ // GIR_Coverage, 3772, |
| 10109 | /* 28589 */ GIR_EraseRootFromParent_Done, |
| 10110 | /* 28590 */ // Label 570: @28590 |
| 10111 | /* 28590 */ GIM_Reject, |
| 10112 | /* 28591 */ // Label 568: @28591 |
| 10113 | /* 28591 */ GIM_Reject, |
| 10114 | /* 28592 */ // Label 541: @28592 |
| 10115 | /* 28592 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(28709), // Rule ID 2018 // |
| 10116 | /* 28597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10117 | /* 28600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 10118 | /* 28603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 10119 | /* 28606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 10120 | /* 28610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 10121 | /* 28614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 10122 | /* 28618 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 10123 | /* 28618 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 10124 | /* 28621 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10125 | /* 28625 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10126 | /* 28630 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 10127 | /* 28634 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 10128 | /* 28639 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 10129 | /* 28642 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10130 | /* 28646 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10131 | /* 28651 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 10132 | /* 28655 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 10133 | /* 28660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 10134 | /* 28663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 10135 | /* 28667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10136 | /* 28672 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10137 | /* 28675 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 10138 | /* 28678 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 10139 | /* 28681 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10140 | /* 28687 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10141 | /* 28693 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10142 | /* 28695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10143 | /* 28698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10144 | /* 28700 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10145 | /* 28703 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 10146 | /* 28708 */ // GIR_Coverage, 2018, |
| 10147 | /* 28708 */ GIR_EraseRootFromParent_Done, |
| 10148 | /* 28709 */ // Label 571: @28709 |
| 10149 | /* 28709 */ GIM_Reject, |
| 10150 | /* 28710 */ // Label 542: @28710 |
| 10151 | /* 28710 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(28823), |
| 10152 | /* 28715 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10153 | /* 28718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10154 | /* 28721 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(28761), // Rule ID 2913 // |
| 10155 | /* 28726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10156 | /* 28729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10157 | /* 28733 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10158 | /* 28737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10159 | /* 28741 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 10160 | /* 28741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 10161 | /* 28744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10162 | /* 28746 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 10163 | /* 28748 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 10164 | /* 28750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10165 | /* 28753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10166 | /* 28759 */ GIR_RootConstrainSelectedInstOperands, |
| 10167 | /* 28760 */ // GIR_Coverage, 2913, |
| 10168 | /* 28760 */ GIR_EraseRootFromParent_Done, |
| 10169 | /* 28761 */ // Label 573: @28761 |
| 10170 | /* 28761 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(28822), // Rule ID 3768 // |
| 10171 | /* 28766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10172 | /* 28769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10173 | /* 28773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10174 | /* 28777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10175 | /* 28781 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10176 | /* 28781 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10177 | /* 28784 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10178 | /* 28788 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10179 | /* 28793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 10180 | /* 28796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10181 | /* 28798 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10182 | /* 28800 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10183 | /* 28802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10184 | /* 28805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10185 | /* 28811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10186 | /* 28817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10187 | /* 28820 */ GIR_RootConstrainSelectedInstOperands, |
| 10188 | /* 28821 */ // GIR_Coverage, 3768, |
| 10189 | /* 28821 */ GIR_EraseRootFromParent_Done, |
| 10190 | /* 28822 */ // Label 574: @28822 |
| 10191 | /* 28822 */ GIM_Reject, |
| 10192 | /* 28823 */ // Label 572: @28823 |
| 10193 | /* 28823 */ GIM_Reject, |
| 10194 | /* 28824 */ // Label 543: @28824 |
| 10195 | /* 28824 */ GIM_Reject, |
| 10196 | /* 28825 */ // Label 8: @28825 |
| 10197 | /* 28825 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 581*/ GIMT_Encode4(29367), |
| 10198 | /* 28836 */ /*GILLT_v2s32*//*Label 575*/ GIMT_Encode4(28884), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10199 | /* 28848 */ /*GILLT_v4s16*//*Label 576*/ GIMT_Encode4(28931), |
| 10200 | /* 28852 */ /*GILLT_v4s32*//*Label 577*/ GIMT_Encode4(28978), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10201 | /* 28864 */ /*GILLT_v8s8*//*Label 578*/ GIMT_Encode4(29092), |
| 10202 | /* 28868 */ /*GILLT_v8s16*//*Label 579*/ GIMT_Encode4(29139), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10203 | /* 28880 */ /*GILLT_v16s8*//*Label 580*/ GIMT_Encode4(29253), |
| 10204 | /* 28884 */ // Label 575: @28884 |
| 10205 | /* 28884 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(28930), // Rule ID 1319 // |
| 10206 | /* 28889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10207 | /* 28892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10208 | /* 28895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10209 | /* 28898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10210 | /* 28902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10211 | /* 28906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10212 | /* 28910 */ // (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 10213 | /* 28910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32), |
| 10214 | /* 28913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10215 | /* 28915 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10216 | /* 28917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10217 | /* 28919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10218 | /* 28922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10219 | /* 28928 */ GIR_RootConstrainSelectedInstOperands, |
| 10220 | /* 28929 */ // GIR_Coverage, 1319, |
| 10221 | /* 28929 */ GIR_EraseRootFromParent_Done, |
| 10222 | /* 28930 */ // Label 582: @28930 |
| 10223 | /* 28930 */ GIM_Reject, |
| 10224 | /* 28931 */ // Label 576: @28931 |
| 10225 | /* 28931 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(28977), // Rule ID 1318 // |
| 10226 | /* 28936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10227 | /* 28939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10228 | /* 28942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 10229 | /* 28945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10230 | /* 28949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10231 | /* 28953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10232 | /* 28957 */ // (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 10233 | /* 28957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16), |
| 10234 | /* 28960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10235 | /* 28962 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10236 | /* 28964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10237 | /* 28966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10238 | /* 28969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10239 | /* 28975 */ GIR_RootConstrainSelectedInstOperands, |
| 10240 | /* 28976 */ // GIR_Coverage, 1318, |
| 10241 | /* 28976 */ GIR_EraseRootFromParent_Done, |
| 10242 | /* 28977 */ // Label 583: @28977 |
| 10243 | /* 28977 */ GIM_Reject, |
| 10244 | /* 28978 */ // Label 577: @28978 |
| 10245 | /* 28978 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(29091), |
| 10246 | /* 28983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10247 | /* 28986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10248 | /* 28989 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(29029), // Rule ID 1321 // |
| 10249 | /* 28994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10250 | /* 28997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10251 | /* 29001 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10252 | /* 29005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10253 | /* 29009 */ // (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 10254 | /* 29009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32), |
| 10255 | /* 29012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10256 | /* 29014 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10257 | /* 29016 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10258 | /* 29018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10259 | /* 29021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10260 | /* 29027 */ GIR_RootConstrainSelectedInstOperands, |
| 10261 | /* 29028 */ // GIR_Coverage, 1321, |
| 10262 | /* 29028 */ GIR_EraseRootFromParent_Done, |
| 10263 | /* 29029 */ // Label 585: @29029 |
| 10264 | /* 29029 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(29090), // Rule ID 3938 // |
| 10265 | /* 29034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10266 | /* 29037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10267 | /* 29041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10268 | /* 29045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10269 | /* 29049 */ // (abds:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10270 | /* 29049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10271 | /* 29052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10272 | /* 29056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10273 | /* 29061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 10274 | /* 29064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10275 | /* 29066 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10276 | /* 29068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10277 | /* 29070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10278 | /* 29073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10279 | /* 29079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10280 | /* 29085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10281 | /* 29088 */ GIR_RootConstrainSelectedInstOperands, |
| 10282 | /* 29089 */ // GIR_Coverage, 3938, |
| 10283 | /* 29089 */ GIR_EraseRootFromParent_Done, |
| 10284 | /* 29090 */ // Label 586: @29090 |
| 10285 | /* 29090 */ GIM_Reject, |
| 10286 | /* 29091 */ // Label 584: @29091 |
| 10287 | /* 29091 */ GIM_Reject, |
| 10288 | /* 29092 */ // Label 578: @29092 |
| 10289 | /* 29092 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(29138), // Rule ID 1322 // |
| 10290 | /* 29097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10291 | /* 29100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10292 | /* 29103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 10293 | /* 29106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10294 | /* 29110 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10295 | /* 29114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10296 | /* 29118 */ // (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 10297 | /* 29118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8), |
| 10298 | /* 29121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10299 | /* 29123 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10300 | /* 29125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10301 | /* 29127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10302 | /* 29130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10303 | /* 29136 */ GIR_RootConstrainSelectedInstOperands, |
| 10304 | /* 29137 */ // GIR_Coverage, 1322, |
| 10305 | /* 29137 */ GIR_EraseRootFromParent_Done, |
| 10306 | /* 29138 */ // Label 587: @29138 |
| 10307 | /* 29138 */ GIM_Reject, |
| 10308 | /* 29139 */ // Label 579: @29139 |
| 10309 | /* 29139 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(29252), |
| 10310 | /* 29144 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10311 | /* 29147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10312 | /* 29150 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(29190), // Rule ID 1320 // |
| 10313 | /* 29155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10314 | /* 29158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10315 | /* 29162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10316 | /* 29166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10317 | /* 29170 */ // (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 10318 | /* 29170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16), |
| 10319 | /* 29173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10320 | /* 29175 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10321 | /* 29177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10322 | /* 29179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10323 | /* 29182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10324 | /* 29188 */ GIR_RootConstrainSelectedInstOperands, |
| 10325 | /* 29189 */ // GIR_Coverage, 1320, |
| 10326 | /* 29189 */ GIR_EraseRootFromParent_Done, |
| 10327 | /* 29190 */ // Label 589: @29190 |
| 10328 | /* 29190 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(29251), // Rule ID 3934 // |
| 10329 | /* 29195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10330 | /* 29198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10331 | /* 29202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10332 | /* 29206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10333 | /* 29210 */ // (abds:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10334 | /* 29210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10335 | /* 29213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10336 | /* 29217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10337 | /* 29222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 10338 | /* 29225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10339 | /* 29227 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10340 | /* 29229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10341 | /* 29231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10342 | /* 29234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10343 | /* 29240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10344 | /* 29246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10345 | /* 29249 */ GIR_RootConstrainSelectedInstOperands, |
| 10346 | /* 29250 */ // GIR_Coverage, 3934, |
| 10347 | /* 29250 */ GIR_EraseRootFromParent_Done, |
| 10348 | /* 29251 */ // Label 590: @29251 |
| 10349 | /* 29251 */ GIM_Reject, |
| 10350 | /* 29252 */ // Label 588: @29252 |
| 10351 | /* 29252 */ GIM_Reject, |
| 10352 | /* 29253 */ // Label 580: @29253 |
| 10353 | /* 29253 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(29366), |
| 10354 | /* 29258 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10355 | /* 29261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10356 | /* 29264 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(29304), // Rule ID 1323 // |
| 10357 | /* 29269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10358 | /* 29272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10359 | /* 29276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10360 | /* 29280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10361 | /* 29284 */ // (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 10362 | /* 29284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8), |
| 10363 | /* 29287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10364 | /* 29289 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10365 | /* 29291 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10366 | /* 29293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10367 | /* 29296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10368 | /* 29302 */ GIR_RootConstrainSelectedInstOperands, |
| 10369 | /* 29303 */ // GIR_Coverage, 1323, |
| 10370 | /* 29303 */ GIR_EraseRootFromParent_Done, |
| 10371 | /* 29304 */ // Label 592: @29304 |
| 10372 | /* 29304 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(29365), // Rule ID 3931 // |
| 10373 | /* 29309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10374 | /* 29312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10375 | /* 29316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10376 | /* 29320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10377 | /* 29324 */ // (abds:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10378 | /* 29324 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10379 | /* 29327 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10380 | /* 29331 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10381 | /* 29336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 10382 | /* 29339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10383 | /* 29341 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10384 | /* 29343 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10385 | /* 29345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10386 | /* 29348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10387 | /* 29354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10388 | /* 29360 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10389 | /* 29363 */ GIR_RootConstrainSelectedInstOperands, |
| 10390 | /* 29364 */ // GIR_Coverage, 3931, |
| 10391 | /* 29364 */ GIR_EraseRootFromParent_Done, |
| 10392 | /* 29365 */ // Label 593: @29365 |
| 10393 | /* 29365 */ GIM_Reject, |
| 10394 | /* 29366 */ // Label 591: @29366 |
| 10395 | /* 29366 */ GIM_Reject, |
| 10396 | /* 29367 */ // Label 581: @29367 |
| 10397 | /* 29367 */ GIM_Reject, |
| 10398 | /* 29368 */ // Label 9: @29368 |
| 10399 | /* 29368 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 600*/ GIMT_Encode4(29910), |
| 10400 | /* 29379 */ /*GILLT_v2s32*//*Label 594*/ GIMT_Encode4(29427), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10401 | /* 29391 */ /*GILLT_v4s16*//*Label 595*/ GIMT_Encode4(29474), |
| 10402 | /* 29395 */ /*GILLT_v4s32*//*Label 596*/ GIMT_Encode4(29521), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10403 | /* 29407 */ /*GILLT_v8s8*//*Label 597*/ GIMT_Encode4(29635), |
| 10404 | /* 29411 */ /*GILLT_v8s16*//*Label 598*/ GIMT_Encode4(29682), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10405 | /* 29423 */ /*GILLT_v16s8*//*Label 599*/ GIMT_Encode4(29796), |
| 10406 | /* 29427 */ // Label 594: @29427 |
| 10407 | /* 29427 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(29473), // Rule ID 1325 // |
| 10408 | /* 29432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10409 | /* 29435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10410 | /* 29438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10411 | /* 29441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10412 | /* 29445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10413 | /* 29449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10414 | /* 29453 */ // (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 10415 | /* 29453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32), |
| 10416 | /* 29456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10417 | /* 29458 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10418 | /* 29460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10419 | /* 29462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10420 | /* 29465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10421 | /* 29471 */ GIR_RootConstrainSelectedInstOperands, |
| 10422 | /* 29472 */ // GIR_Coverage, 1325, |
| 10423 | /* 29472 */ GIR_EraseRootFromParent_Done, |
| 10424 | /* 29473 */ // Label 601: @29473 |
| 10425 | /* 29473 */ GIM_Reject, |
| 10426 | /* 29474 */ // Label 595: @29474 |
| 10427 | /* 29474 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(29520), // Rule ID 1324 // |
| 10428 | /* 29479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10429 | /* 29482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10430 | /* 29485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 10431 | /* 29488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10432 | /* 29492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10433 | /* 29496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10434 | /* 29500 */ // (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 10435 | /* 29500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16), |
| 10436 | /* 29503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10437 | /* 29505 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10438 | /* 29507 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10439 | /* 29509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10440 | /* 29512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10441 | /* 29518 */ GIR_RootConstrainSelectedInstOperands, |
| 10442 | /* 29519 */ // GIR_Coverage, 1324, |
| 10443 | /* 29519 */ GIR_EraseRootFromParent_Done, |
| 10444 | /* 29520 */ // Label 602: @29520 |
| 10445 | /* 29520 */ GIM_Reject, |
| 10446 | /* 29521 */ // Label 596: @29521 |
| 10447 | /* 29521 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(29634), |
| 10448 | /* 29526 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10449 | /* 29529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10450 | /* 29532 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(29572), // Rule ID 1327 // |
| 10451 | /* 29537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10452 | /* 29540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10453 | /* 29544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10454 | /* 29548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10455 | /* 29552 */ // (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 10456 | /* 29552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32), |
| 10457 | /* 29555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10458 | /* 29557 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10459 | /* 29559 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10460 | /* 29561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10461 | /* 29564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10462 | /* 29570 */ GIR_RootConstrainSelectedInstOperands, |
| 10463 | /* 29571 */ // GIR_Coverage, 1327, |
| 10464 | /* 29571 */ GIR_EraseRootFromParent_Done, |
| 10465 | /* 29572 */ // Label 604: @29572 |
| 10466 | /* 29572 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(29633), // Rule ID 3950 // |
| 10467 | /* 29577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10468 | /* 29580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10469 | /* 29584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10470 | /* 29588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10471 | /* 29592 */ // (abdu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10472 | /* 29592 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10473 | /* 29595 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10474 | /* 29599 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10475 | /* 29604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 10476 | /* 29607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10477 | /* 29609 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10478 | /* 29611 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10479 | /* 29613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10480 | /* 29616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10481 | /* 29622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10482 | /* 29628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10483 | /* 29631 */ GIR_RootConstrainSelectedInstOperands, |
| 10484 | /* 29632 */ // GIR_Coverage, 3950, |
| 10485 | /* 29632 */ GIR_EraseRootFromParent_Done, |
| 10486 | /* 29633 */ // Label 605: @29633 |
| 10487 | /* 29633 */ GIM_Reject, |
| 10488 | /* 29634 */ // Label 603: @29634 |
| 10489 | /* 29634 */ GIM_Reject, |
| 10490 | /* 29635 */ // Label 597: @29635 |
| 10491 | /* 29635 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(29681), // Rule ID 1328 // |
| 10492 | /* 29640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10493 | /* 29643 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10494 | /* 29646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 10495 | /* 29649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10496 | /* 29653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10497 | /* 29657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10498 | /* 29661 */ // (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 10499 | /* 29661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8), |
| 10500 | /* 29664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10501 | /* 29666 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10502 | /* 29668 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10503 | /* 29670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10504 | /* 29673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10505 | /* 29679 */ GIR_RootConstrainSelectedInstOperands, |
| 10506 | /* 29680 */ // GIR_Coverage, 1328, |
| 10507 | /* 29680 */ GIR_EraseRootFromParent_Done, |
| 10508 | /* 29681 */ // Label 606: @29681 |
| 10509 | /* 29681 */ GIM_Reject, |
| 10510 | /* 29682 */ // Label 598: @29682 |
| 10511 | /* 29682 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(29795), |
| 10512 | /* 29687 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10513 | /* 29690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10514 | /* 29693 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(29733), // Rule ID 1326 // |
| 10515 | /* 29698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10516 | /* 29701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10517 | /* 29705 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10518 | /* 29709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10519 | /* 29713 */ // (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 10520 | /* 29713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16), |
| 10521 | /* 29716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10522 | /* 29718 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10523 | /* 29720 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10524 | /* 29722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10525 | /* 29725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10526 | /* 29731 */ GIR_RootConstrainSelectedInstOperands, |
| 10527 | /* 29732 */ // GIR_Coverage, 1326, |
| 10528 | /* 29732 */ GIR_EraseRootFromParent_Done, |
| 10529 | /* 29733 */ // Label 608: @29733 |
| 10530 | /* 29733 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(29794), // Rule ID 3946 // |
| 10531 | /* 29738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10532 | /* 29741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10533 | /* 29745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10534 | /* 29749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10535 | /* 29753 */ // (abdu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10536 | /* 29753 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10537 | /* 29756 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10538 | /* 29760 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10539 | /* 29765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 10540 | /* 29768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10541 | /* 29770 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10542 | /* 29772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10543 | /* 29774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10544 | /* 29777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10545 | /* 29783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10546 | /* 29789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10547 | /* 29792 */ GIR_RootConstrainSelectedInstOperands, |
| 10548 | /* 29793 */ // GIR_Coverage, 3946, |
| 10549 | /* 29793 */ GIR_EraseRootFromParent_Done, |
| 10550 | /* 29794 */ // Label 609: @29794 |
| 10551 | /* 29794 */ GIM_Reject, |
| 10552 | /* 29795 */ // Label 607: @29795 |
| 10553 | /* 29795 */ GIM_Reject, |
| 10554 | /* 29796 */ // Label 599: @29796 |
| 10555 | /* 29796 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(29909), |
| 10556 | /* 29801 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10557 | /* 29804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10558 | /* 29807 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(29847), // Rule ID 1329 // |
| 10559 | /* 29812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10560 | /* 29815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10561 | /* 29819 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10562 | /* 29823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10563 | /* 29827 */ // (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 10564 | /* 29827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8), |
| 10565 | /* 29830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10566 | /* 29832 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10567 | /* 29834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10568 | /* 29836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10569 | /* 29839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10570 | /* 29845 */ GIR_RootConstrainSelectedInstOperands, |
| 10571 | /* 29846 */ // GIR_Coverage, 1329, |
| 10572 | /* 29846 */ GIR_EraseRootFromParent_Done, |
| 10573 | /* 29847 */ // Label 611: @29847 |
| 10574 | /* 29847 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(29908), // Rule ID 3942 // |
| 10575 | /* 29852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10576 | /* 29855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10577 | /* 29859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10578 | /* 29863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10579 | /* 29867 */ // (abdu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10580 | /* 29867 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10581 | /* 29870 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10582 | /* 29874 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10583 | /* 29879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 10584 | /* 29882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10585 | /* 29884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10586 | /* 29886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10587 | /* 29888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10588 | /* 29891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10589 | /* 29897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10590 | /* 29903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10591 | /* 29906 */ GIR_RootConstrainSelectedInstOperands, |
| 10592 | /* 29907 */ // GIR_Coverage, 3942, |
| 10593 | /* 29907 */ GIR_EraseRootFromParent_Done, |
| 10594 | /* 29908 */ // Label 612: @29908 |
| 10595 | /* 29908 */ GIM_Reject, |
| 10596 | /* 29909 */ // Label 610: @29909 |
| 10597 | /* 29909 */ GIM_Reject, |
| 10598 | /* 29910 */ // Label 600: @29910 |
| 10599 | /* 29910 */ GIM_Reject, |
| 10600 | /* 29911 */ // Label 10: @29911 |
| 10601 | /* 29911 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 616*/ GIMT_Encode4(30149), |
| 10602 | /* 29922 */ /*GILLT_v4s32*//*Label 613*/ GIMT_Encode4(29954), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10603 | /* 29938 */ /*GILLT_v8s16*//*Label 614*/ GIMT_Encode4(30019), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10604 | /* 29950 */ /*GILLT_v16s8*//*Label 615*/ GIMT_Encode4(30084), |
| 10605 | /* 29954 */ // Label 613: @29954 |
| 10606 | /* 29954 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(30018), // Rule ID 3998 // |
| 10607 | /* 29959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10608 | /* 29962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10609 | /* 29965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10610 | /* 29969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10611 | /* 29973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10612 | /* 29977 */ // (avgflooru:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10613 | /* 29977 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10614 | /* 29980 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10615 | /* 29984 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10616 | /* 29989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 10617 | /* 29992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10618 | /* 29994 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10619 | /* 29996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10620 | /* 29998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10621 | /* 30001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10622 | /* 30007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10623 | /* 30013 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10624 | /* 30016 */ GIR_RootConstrainSelectedInstOperands, |
| 10625 | /* 30017 */ // GIR_Coverage, 3998, |
| 10626 | /* 30017 */ GIR_EraseRootFromParent_Done, |
| 10627 | /* 30018 */ // Label 617: @30018 |
| 10628 | /* 30018 */ GIM_Reject, |
| 10629 | /* 30019 */ // Label 614: @30019 |
| 10630 | /* 30019 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(30083), // Rule ID 3994 // |
| 10631 | /* 30024 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10632 | /* 30027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10633 | /* 30030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10634 | /* 30034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10635 | /* 30038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10636 | /* 30042 */ // (avgflooru:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10637 | /* 30042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10638 | /* 30045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10639 | /* 30049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10640 | /* 30054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 10641 | /* 30057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10642 | /* 30059 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10643 | /* 30061 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10644 | /* 30063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10645 | /* 30066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10646 | /* 30072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10647 | /* 30078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10648 | /* 30081 */ GIR_RootConstrainSelectedInstOperands, |
| 10649 | /* 30082 */ // GIR_Coverage, 3994, |
| 10650 | /* 30082 */ GIR_EraseRootFromParent_Done, |
| 10651 | /* 30083 */ // Label 618: @30083 |
| 10652 | /* 30083 */ GIM_Reject, |
| 10653 | /* 30084 */ // Label 615: @30084 |
| 10654 | /* 30084 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(30148), // Rule ID 3990 // |
| 10655 | /* 30089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10656 | /* 30092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10657 | /* 30095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10658 | /* 30099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10659 | /* 30103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10660 | /* 30107 */ // (avgflooru:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10661 | /* 30107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10662 | /* 30110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10663 | /* 30114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10664 | /* 30119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 10665 | /* 30122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10666 | /* 30124 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10667 | /* 30126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10668 | /* 30128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10669 | /* 30131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10670 | /* 30137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10671 | /* 30143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10672 | /* 30146 */ GIR_RootConstrainSelectedInstOperands, |
| 10673 | /* 30147 */ // GIR_Coverage, 3990, |
| 10674 | /* 30147 */ GIR_EraseRootFromParent_Done, |
| 10675 | /* 30148 */ // Label 619: @30148 |
| 10676 | /* 30148 */ GIM_Reject, |
| 10677 | /* 30149 */ // Label 616: @30149 |
| 10678 | /* 30149 */ GIM_Reject, |
| 10679 | /* 30150 */ // Label 11: @30150 |
| 10680 | /* 30150 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 623*/ GIMT_Encode4(30388), |
| 10681 | /* 30161 */ /*GILLT_v4s32*//*Label 620*/ GIMT_Encode4(30193), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10682 | /* 30177 */ /*GILLT_v8s16*//*Label 621*/ GIMT_Encode4(30258), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10683 | /* 30189 */ /*GILLT_v16s8*//*Label 622*/ GIMT_Encode4(30323), |
| 10684 | /* 30193 */ // Label 620: @30193 |
| 10685 | /* 30193 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(30257), // Rule ID 3974 // |
| 10686 | /* 30198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10687 | /* 30201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10688 | /* 30204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10689 | /* 30208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10690 | /* 30212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10691 | /* 30216 */ // (avgceilu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10692 | /* 30216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10693 | /* 30219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10694 | /* 30223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10695 | /* 30228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 10696 | /* 30231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10697 | /* 30233 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10698 | /* 30235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10699 | /* 30237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10700 | /* 30240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10701 | /* 30246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10702 | /* 30252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10703 | /* 30255 */ GIR_RootConstrainSelectedInstOperands, |
| 10704 | /* 30256 */ // GIR_Coverage, 3974, |
| 10705 | /* 30256 */ GIR_EraseRootFromParent_Done, |
| 10706 | /* 30257 */ // Label 624: @30257 |
| 10707 | /* 30257 */ GIM_Reject, |
| 10708 | /* 30258 */ // Label 621: @30258 |
| 10709 | /* 30258 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(30322), // Rule ID 3970 // |
| 10710 | /* 30263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10711 | /* 30266 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10712 | /* 30269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10713 | /* 30273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10714 | /* 30277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10715 | /* 30281 */ // (avgceilu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10716 | /* 30281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10717 | /* 30284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10718 | /* 30288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10719 | /* 30293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 10720 | /* 30296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10721 | /* 30298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10722 | /* 30300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10723 | /* 30302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10724 | /* 30305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10725 | /* 30311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10726 | /* 30317 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10727 | /* 30320 */ GIR_RootConstrainSelectedInstOperands, |
| 10728 | /* 30321 */ // GIR_Coverage, 3970, |
| 10729 | /* 30321 */ GIR_EraseRootFromParent_Done, |
| 10730 | /* 30322 */ // Label 625: @30322 |
| 10731 | /* 30322 */ GIM_Reject, |
| 10732 | /* 30323 */ // Label 622: @30323 |
| 10733 | /* 30323 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(30387), // Rule ID 3966 // |
| 10734 | /* 30328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10735 | /* 30331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10736 | /* 30334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10737 | /* 30338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10738 | /* 30342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10739 | /* 30346 */ // (avgceilu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10740 | /* 30346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10741 | /* 30349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10742 | /* 30353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10743 | /* 30358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 10744 | /* 30361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10745 | /* 30363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10746 | /* 30365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10747 | /* 30367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10748 | /* 30370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10749 | /* 30376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10750 | /* 30382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10751 | /* 30385 */ GIR_RootConstrainSelectedInstOperands, |
| 10752 | /* 30386 */ // GIR_Coverage, 3966, |
| 10753 | /* 30386 */ GIR_EraseRootFromParent_Done, |
| 10754 | /* 30387 */ // Label 626: @30387 |
| 10755 | /* 30387 */ GIM_Reject, |
| 10756 | /* 30388 */ // Label 623: @30388 |
| 10757 | /* 30388 */ GIM_Reject, |
| 10758 | /* 30389 */ // Label 12: @30389 |
| 10759 | /* 30389 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 630*/ GIMT_Encode4(30627), |
| 10760 | /* 30400 */ /*GILLT_v4s32*//*Label 627*/ GIMT_Encode4(30432), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10761 | /* 30416 */ /*GILLT_v8s16*//*Label 628*/ GIMT_Encode4(30497), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10762 | /* 30428 */ /*GILLT_v16s8*//*Label 629*/ GIMT_Encode4(30562), |
| 10763 | /* 30432 */ // Label 627: @30432 |
| 10764 | /* 30432 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(30496), // Rule ID 3986 // |
| 10765 | /* 30437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10766 | /* 30440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10767 | /* 30443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10768 | /* 30447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10769 | /* 30451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10770 | /* 30455 */ // (avgfloors:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10771 | /* 30455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10772 | /* 30458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10773 | /* 30462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10774 | /* 30467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 10775 | /* 30470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10776 | /* 30472 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10777 | /* 30474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10778 | /* 30476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10779 | /* 30479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10780 | /* 30485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10781 | /* 30491 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10782 | /* 30494 */ GIR_RootConstrainSelectedInstOperands, |
| 10783 | /* 30495 */ // GIR_Coverage, 3986, |
| 10784 | /* 30495 */ GIR_EraseRootFromParent_Done, |
| 10785 | /* 30496 */ // Label 631: @30496 |
| 10786 | /* 30496 */ GIM_Reject, |
| 10787 | /* 30497 */ // Label 628: @30497 |
| 10788 | /* 30497 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(30561), // Rule ID 3982 // |
| 10789 | /* 30502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10790 | /* 30505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10791 | /* 30508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10792 | /* 30512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10793 | /* 30516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10794 | /* 30520 */ // (avgfloors:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10795 | /* 30520 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10796 | /* 30523 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10797 | /* 30527 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10798 | /* 30532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 10799 | /* 30535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10800 | /* 30537 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10801 | /* 30539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10802 | /* 30541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10803 | /* 30544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10804 | /* 30550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10805 | /* 30556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10806 | /* 30559 */ GIR_RootConstrainSelectedInstOperands, |
| 10807 | /* 30560 */ // GIR_Coverage, 3982, |
| 10808 | /* 30560 */ GIR_EraseRootFromParent_Done, |
| 10809 | /* 30561 */ // Label 632: @30561 |
| 10810 | /* 30561 */ GIM_Reject, |
| 10811 | /* 30562 */ // Label 629: @30562 |
| 10812 | /* 30562 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(30626), // Rule ID 3979 // |
| 10813 | /* 30567 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10814 | /* 30570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10815 | /* 30573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10816 | /* 30577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10817 | /* 30581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10818 | /* 30585 */ // (avgfloors:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10819 | /* 30585 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10820 | /* 30588 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10821 | /* 30592 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10822 | /* 30597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 10823 | /* 30600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10824 | /* 30602 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10825 | /* 30604 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10826 | /* 30606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10827 | /* 30609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10828 | /* 30615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10829 | /* 30621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10830 | /* 30624 */ GIR_RootConstrainSelectedInstOperands, |
| 10831 | /* 30625 */ // GIR_Coverage, 3979, |
| 10832 | /* 30625 */ GIR_EraseRootFromParent_Done, |
| 10833 | /* 30626 */ // Label 633: @30626 |
| 10834 | /* 30626 */ GIM_Reject, |
| 10835 | /* 30627 */ // Label 630: @30627 |
| 10836 | /* 30627 */ GIM_Reject, |
| 10837 | /* 30628 */ // Label 13: @30628 |
| 10838 | /* 30628 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 637*/ GIMT_Encode4(30866), |
| 10839 | /* 30639 */ /*GILLT_v4s32*//*Label 634*/ GIMT_Encode4(30671), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10840 | /* 30655 */ /*GILLT_v8s16*//*Label 635*/ GIMT_Encode4(30736), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10841 | /* 30667 */ /*GILLT_v16s8*//*Label 636*/ GIMT_Encode4(30801), |
| 10842 | /* 30671 */ // Label 634: @30671 |
| 10843 | /* 30671 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(30735), // Rule ID 3962 // |
| 10844 | /* 30676 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10845 | /* 30679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10846 | /* 30682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10847 | /* 30686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10848 | /* 30690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10849 | /* 30694 */ // (avgceils:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10850 | /* 30694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10851 | /* 30697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10852 | /* 30701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10853 | /* 30706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 10854 | /* 30709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10855 | /* 30711 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10856 | /* 30713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10857 | /* 30715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10858 | /* 30718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10859 | /* 30724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10860 | /* 30730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10861 | /* 30733 */ GIR_RootConstrainSelectedInstOperands, |
| 10862 | /* 30734 */ // GIR_Coverage, 3962, |
| 10863 | /* 30734 */ GIR_EraseRootFromParent_Done, |
| 10864 | /* 30735 */ // Label 638: @30735 |
| 10865 | /* 30735 */ GIM_Reject, |
| 10866 | /* 30736 */ // Label 635: @30736 |
| 10867 | /* 30736 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(30800), // Rule ID 3958 // |
| 10868 | /* 30741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10869 | /* 30744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10870 | /* 30747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10871 | /* 30751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10872 | /* 30755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10873 | /* 30759 */ // (avgceils:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10874 | /* 30759 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10875 | /* 30762 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10876 | /* 30766 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10877 | /* 30771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 10878 | /* 30774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10879 | /* 30776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10880 | /* 30778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10881 | /* 30780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10882 | /* 30783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10883 | /* 30789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10884 | /* 30795 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10885 | /* 30798 */ GIR_RootConstrainSelectedInstOperands, |
| 10886 | /* 30799 */ // GIR_Coverage, 3958, |
| 10887 | /* 30799 */ GIR_EraseRootFromParent_Done, |
| 10888 | /* 30800 */ // Label 639: @30800 |
| 10889 | /* 30800 */ GIM_Reject, |
| 10890 | /* 30801 */ // Label 636: @30801 |
| 10891 | /* 30801 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(30865), // Rule ID 3955 // |
| 10892 | /* 30806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10893 | /* 30809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10894 | /* 30812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10895 | /* 30816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10896 | /* 30820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10897 | /* 30824 */ // (avgceils:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10898 | /* 30824 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10899 | /* 30827 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10900 | /* 30831 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10901 | /* 30836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 10902 | /* 30839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10903 | /* 30841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10904 | /* 30843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10905 | /* 30845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10906 | /* 30848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10907 | /* 30854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10908 | /* 30860 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10909 | /* 30863 */ GIR_RootConstrainSelectedInstOperands, |
| 10910 | /* 30864 */ // GIR_Coverage, 3955, |
| 10911 | /* 30864 */ GIR_EraseRootFromParent_Done, |
| 10912 | /* 30865 */ // Label 640: @30865 |
| 10913 | /* 30865 */ GIM_Reject, |
| 10914 | /* 30866 */ // Label 637: @30866 |
| 10915 | /* 30866 */ GIM_Reject, |
| 10916 | /* 30867 */ // Label 14: @30867 |
| 10917 | /* 30867 */ GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(31253), |
| 10918 | /* 30872 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 10919 | /* 30875 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(16), /*)*//*default:*//*Label 646*/ GIMT_Encode4(31252), |
| 10920 | /* 30886 */ /*GILLT_v2s64*//*Label 642*/ GIMT_Encode4(30930), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10921 | /* 30898 */ /*GILLT_v4s32*//*Label 643*/ GIMT_Encode4(30988), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10922 | /* 30914 */ /*GILLT_v8s16*//*Label 644*/ GIMT_Encode4(31091), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10923 | /* 30926 */ /*GILLT_v16s8*//*Label 645*/ GIMT_Encode4(31194), |
| 10924 | /* 30930 */ // Label 642: @30930 |
| 10925 | /* 30930 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(30987), // Rule ID 3398 // |
| 10926 | /* 30935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10927 | /* 30938 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10928 | /* 30941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 10929 | /* 30944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10930 | /* 30948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10931 | /* 30952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10932 | /* 30956 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] }) |
| 10933 | /* 30956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 10934 | /* 30959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10935 | /* 30961 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 10936 | /* 30963 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 10937 | /* 30966 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10938 | /* 30968 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 10939 | /* 30971 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10940 | /* 30976 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 10941 | /* 30981 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 10942 | /* 30986 */ // GIR_Coverage, 3398, |
| 10943 | /* 30986 */ GIR_EraseRootFromParent_Done, |
| 10944 | /* 30987 */ // Label 647: @30987 |
| 10945 | /* 30987 */ GIM_Reject, |
| 10946 | /* 30988 */ // Label 643: @30988 |
| 10947 | /* 30988 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(31090), |
| 10948 | /* 30993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10949 | /* 30996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10950 | /* 30999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10951 | /* 31003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10952 | /* 31007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10953 | /* 31011 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(31050), // Rule ID 3399 // |
| 10954 | /* 31016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10955 | /* 31019 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] }) |
| 10956 | /* 31019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 10957 | /* 31022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10958 | /* 31024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 10959 | /* 31026 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 10960 | /* 31029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10961 | /* 31031 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 10962 | /* 31034 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10963 | /* 31039 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 10964 | /* 31044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 10965 | /* 31049 */ // GIR_Coverage, 3399, |
| 10966 | /* 31049 */ GIR_EraseRootFromParent_Done, |
| 10967 | /* 31050 */ // Label 649: @31050 |
| 10968 | /* 31050 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(31089), // Rule ID 3402 // |
| 10969 | /* 31055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10970 | /* 31058 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] }) |
| 10971 | /* 31058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 10972 | /* 31061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10973 | /* 31063 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 10974 | /* 31065 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 10975 | /* 31068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10976 | /* 31070 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 10977 | /* 31073 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10978 | /* 31078 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 10979 | /* 31083 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 10980 | /* 31088 */ // GIR_Coverage, 3402, |
| 10981 | /* 31088 */ GIR_EraseRootFromParent_Done, |
| 10982 | /* 31089 */ // Label 650: @31089 |
| 10983 | /* 31089 */ GIM_Reject, |
| 10984 | /* 31090 */ // Label 648: @31090 |
| 10985 | /* 31090 */ GIM_Reject, |
| 10986 | /* 31091 */ // Label 644: @31091 |
| 10987 | /* 31091 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(31193), |
| 10988 | /* 31096 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10989 | /* 31099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 10990 | /* 31102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10991 | /* 31106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10992 | /* 31110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10993 | /* 31114 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(31153), // Rule ID 3400 // |
| 10994 | /* 31119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10995 | /* 31122 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] }) |
| 10996 | /* 31122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 10997 | /* 31125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10998 | /* 31127 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 10999 | /* 31129 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 11000 | /* 31132 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 11001 | /* 31134 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 11002 | /* 31137 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11003 | /* 31142 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 11004 | /* 31147 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 11005 | /* 31152 */ // GIR_Coverage, 3400, |
| 11006 | /* 31152 */ GIR_EraseRootFromParent_Done, |
| 11007 | /* 31153 */ // Label 652: @31153 |
| 11008 | /* 31153 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(31192), // Rule ID 3403 // |
| 11009 | /* 31158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11010 | /* 31161 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] }) |
| 11011 | /* 31161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 11012 | /* 31164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 11013 | /* 31166 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 11014 | /* 31168 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 11015 | /* 31171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 11016 | /* 31173 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 11017 | /* 31176 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11018 | /* 31181 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 11019 | /* 31186 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 11020 | /* 31191 */ // GIR_Coverage, 3403, |
| 11021 | /* 31191 */ GIR_EraseRootFromParent_Done, |
| 11022 | /* 31192 */ // Label 653: @31192 |
| 11023 | /* 31192 */ GIM_Reject, |
| 11024 | /* 31193 */ // Label 651: @31193 |
| 11025 | /* 31193 */ GIM_Reject, |
| 11026 | /* 31194 */ // Label 645: @31194 |
| 11027 | /* 31194 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(31251), // Rule ID 3401 // |
| 11028 | /* 31199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11029 | /* 31202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11030 | /* 31205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 11031 | /* 31208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11032 | /* 31212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11033 | /* 31216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11034 | /* 31220 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] }) |
| 11035 | /* 31220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 11036 | /* 31223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 11037 | /* 31225 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 11038 | /* 31227 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 11039 | /* 31230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 11040 | /* 31232 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 11041 | /* 31235 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11042 | /* 31240 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 11043 | /* 31245 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 11044 | /* 31250 */ // GIR_Coverage, 3401, |
| 11045 | /* 31250 */ GIR_EraseRootFromParent_Done, |
| 11046 | /* 31251 */ // Label 654: @31251 |
| 11047 | /* 31251 */ GIM_Reject, |
| 11048 | /* 31252 */ // Label 646: @31252 |
| 11049 | /* 31252 */ GIM_Reject, |
| 11050 | /* 31253 */ // Label 641: @31253 |
| 11051 | /* 31253 */ GIM_Reject, |
| 11052 | /* 31254 */ // Label 15: @31254 |
| 11053 | /* 31254 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 664*/ GIMT_Encode4(40265), |
| 11054 | /* 31265 */ /*GILLT_s32*//*Label 655*/ GIMT_Encode4(31325), |
| 11055 | /* 31269 */ /*GILLT_s64*//*Label 656*/ GIMT_Encode4(31473), GIMT_Encode4(0), |
| 11056 | /* 31277 */ /*GILLT_v2s32*//*Label 657*/ GIMT_Encode4(32228), |
| 11057 | /* 31281 */ /*GILLT_v2s64*//*Label 658*/ GIMT_Encode4(32983), GIMT_Encode4(0), |
| 11058 | /* 31289 */ /*GILLT_v4s16*//*Label 659*/ GIMT_Encode4(34702), |
| 11059 | /* 31293 */ /*GILLT_v4s32*//*Label 660*/ GIMT_Encode4(35457), GIMT_Encode4(0), GIMT_Encode4(0), |
| 11060 | /* 31305 */ /*GILLT_v8s8*//*Label 661*/ GIMT_Encode4(37176), |
| 11061 | /* 31309 */ /*GILLT_v8s16*//*Label 662*/ GIMT_Encode4(37591), GIMT_Encode4(0), GIMT_Encode4(0), |
| 11062 | /* 31321 */ /*GILLT_v16s8*//*Label 663*/ GIMT_Encode4(39310), |
| 11063 | /* 31325 */ // Label 655: @31325 |
| 11064 | /* 31325 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(31472), |
| 11065 | /* 31330 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11066 | /* 31333 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(31367), // Rule ID 739 // |
| 11067 | /* 31338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 11068 | /* 31341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 11069 | /* 31345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 11070 | /* 31349 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn) |
| 11071 | /* 31349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS), |
| 11072 | /* 31352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 11073 | /* 31354 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 11074 | /* 31356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11075 | /* 31359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11076 | /* 31365 */ GIR_RootConstrainSelectedInstOperands, |
| 11077 | /* 31366 */ // GIR_Coverage, 739, |
| 11078 | /* 31366 */ GIR_EraseRootFromParent_Done, |
| 11079 | /* 31367 */ // Label 666: @31367 |
| 11080 | /* 31367 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(31401), // Rule ID 740 // |
| 11081 | /* 31372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), |
| 11082 | /* 31375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 11083 | /* 31379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 11084 | /* 31383 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt) |
| 11085 | /* 31383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR), |
| 11086 | /* 31386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn] |
| 11087 | /* 31388 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 11088 | /* 31390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11089 | /* 31393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11090 | /* 31399 */ GIR_RootConstrainSelectedInstOperands, |
| 11091 | /* 31400 */ // GIR_Coverage, 740, |
| 11092 | /* 31400 */ GIR_EraseRootFromParent_Done, |
| 11093 | /* 31401 */ // Label 667: @31401 |
| 11094 | /* 31401 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(31471), // Rule ID 3092 // |
| 11095 | /* 31406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), |
| 11096 | /* 31409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 11097 | /* 31413 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 11098 | /* 31417 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] }) |
| 11099 | /* 31417 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 11100 | /* 31420 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR), |
| 11101 | /* 31424 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11102 | /* 31429 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 11103 | /* 31433 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 11104 | /* 31437 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 11105 | /* 31440 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11106 | /* 31446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11107 | /* 31448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11108 | /* 31451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 11109 | /* 31453 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 11110 | /* 31460 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 11111 | /* 31465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 11112 | /* 31470 */ // GIR_Coverage, 3092, |
| 11113 | /* 31470 */ GIR_EraseRootFromParent_Done, |
| 11114 | /* 31471 */ // Label 668: @31471 |
| 11115 | /* 31471 */ GIM_Reject, |
| 11116 | /* 31472 */ // Label 665: @31472 |
| 11117 | /* 31472 */ GIM_Reject, |
| 11118 | /* 31473 */ // Label 656: @31473 |
| 11119 | /* 31473 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(31505), // Rule ID 3094 // |
| 11120 | /* 31478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11121 | /* 31481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11122 | /* 31484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11123 | /* 31488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11124 | /* 31492 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src |
| 11125 | /* 31492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11126 | /* 31495 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11127 | /* 31497 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11128 | /* 31499 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11129 | /* 31504 */ // GIR_Coverage, 3094, |
| 11130 | /* 31504 */ GIR_EraseRootFromParent_Done, |
| 11131 | /* 31505 */ // Label 669: @31505 |
| 11132 | /* 31505 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(31537), // Rule ID 3095 // |
| 11133 | /* 31510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11134 | /* 31513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11135 | /* 31516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11136 | /* 31520 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11137 | /* 31524 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src |
| 11138 | /* 31524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11139 | /* 31527 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11140 | /* 31529 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11141 | /* 31531 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11142 | /* 31536 */ // GIR_Coverage, 3095, |
| 11143 | /* 31536 */ GIR_EraseRootFromParent_Done, |
| 11144 | /* 31537 */ // Label 670: @31537 |
| 11145 | /* 31537 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(31569), // Rule ID 3106 // |
| 11146 | /* 31542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11147 | /* 31545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11148 | /* 31548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11149 | /* 31552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11150 | /* 31556 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src |
| 11151 | /* 31556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11152 | /* 31559 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11153 | /* 31561 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11154 | /* 31563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11155 | /* 31568 */ // GIR_Coverage, 3106, |
| 11156 | /* 31568 */ GIR_EraseRootFromParent_Done, |
| 11157 | /* 31569 */ // Label 671: @31569 |
| 11158 | /* 31569 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(31601), // Rule ID 3107 // |
| 11159 | /* 31574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11160 | /* 31577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11161 | /* 31580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11162 | /* 31584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11163 | /* 31588 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src |
| 11164 | /* 31588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11165 | /* 31591 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11166 | /* 31593 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11167 | /* 31595 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11168 | /* 31600 */ // GIR_Coverage, 3107, |
| 11169 | /* 31600 */ GIR_EraseRootFromParent_Done, |
| 11170 | /* 31601 */ // Label 672: @31601 |
| 11171 | /* 31601 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(31633), // Rule ID 3108 // |
| 11172 | /* 31606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11173 | /* 31609 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11174 | /* 31612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11175 | /* 31616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11176 | /* 31620 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src |
| 11177 | /* 31620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11178 | /* 31623 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11179 | /* 31625 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11180 | /* 31627 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11181 | /* 31632 */ // GIR_Coverage, 3108, |
| 11182 | /* 31632 */ GIR_EraseRootFromParent_Done, |
| 11183 | /* 31633 */ // Label 673: @31633 |
| 11184 | /* 31633 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(31665), // Rule ID 3109 // |
| 11185 | /* 31638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11186 | /* 31641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11187 | /* 31644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11188 | /* 31648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11189 | /* 31652 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src |
| 11190 | /* 31652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11191 | /* 31655 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11192 | /* 31657 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11193 | /* 31659 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11194 | /* 31664 */ // GIR_Coverage, 3109, |
| 11195 | /* 31664 */ GIR_EraseRootFromParent_Done, |
| 11196 | /* 31665 */ // Label 674: @31665 |
| 11197 | /* 31665 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(31697), // Rule ID 3110 // |
| 11198 | /* 31670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11199 | /* 31673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11200 | /* 31676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11201 | /* 31680 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11202 | /* 31684 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src |
| 11203 | /* 31684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11204 | /* 31687 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11205 | /* 31689 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11206 | /* 31691 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11207 | /* 31696 */ // GIR_Coverage, 3110, |
| 11208 | /* 31696 */ GIR_EraseRootFromParent_Done, |
| 11209 | /* 31697 */ // Label 675: @31697 |
| 11210 | /* 31697 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(31729), // Rule ID 3111 // |
| 11211 | /* 31702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11212 | /* 31705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11213 | /* 31708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11214 | /* 31712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11215 | /* 31716 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 11216 | /* 31716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11217 | /* 31719 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11218 | /* 31721 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11219 | /* 31723 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11220 | /* 31728 */ // GIR_Coverage, 3111, |
| 11221 | /* 31728 */ GIR_EraseRootFromParent_Done, |
| 11222 | /* 31729 */ // Label 676: @31729 |
| 11223 | /* 31729 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(31761), // Rule ID 3112 // |
| 11224 | /* 31734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11225 | /* 31737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11226 | /* 31740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11227 | /* 31744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11228 | /* 31748 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 11229 | /* 31748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11230 | /* 31751 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11231 | /* 31753 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11232 | /* 31755 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11233 | /* 31760 */ // GIR_Coverage, 3112, |
| 11234 | /* 31760 */ GIR_EraseRootFromParent_Done, |
| 11235 | /* 31761 */ // Label 677: @31761 |
| 11236 | /* 31761 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(31793), // Rule ID 3113 // |
| 11237 | /* 31766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11238 | /* 31769 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11239 | /* 31772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11240 | /* 31776 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11241 | /* 31780 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 11242 | /* 31780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11243 | /* 31783 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11244 | /* 31785 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11245 | /* 31787 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11246 | /* 31792 */ // GIR_Coverage, 3113, |
| 11247 | /* 31792 */ GIR_EraseRootFromParent_Done, |
| 11248 | /* 31793 */ // Label 678: @31793 |
| 11249 | /* 31793 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(31825), // Rule ID 3114 // |
| 11250 | /* 31798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11251 | /* 31801 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11252 | /* 31804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11253 | /* 31808 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11254 | /* 31812 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 11255 | /* 31812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11256 | /* 31815 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11257 | /* 31817 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11258 | /* 31819 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11259 | /* 31824 */ // GIR_Coverage, 3114, |
| 11260 | /* 31824 */ GIR_EraseRootFromParent_Done, |
| 11261 | /* 31825 */ // Label 679: @31825 |
| 11262 | /* 31825 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(31857), // Rule ID 3115 // |
| 11263 | /* 31830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11264 | /* 31833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11265 | /* 31836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11266 | /* 31840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11267 | /* 31844 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src |
| 11268 | /* 31844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11269 | /* 31847 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11270 | /* 31849 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11271 | /* 31851 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11272 | /* 31856 */ // GIR_Coverage, 3115, |
| 11273 | /* 31856 */ GIR_EraseRootFromParent_Done, |
| 11274 | /* 31857 */ // Label 680: @31857 |
| 11275 | /* 31857 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(31894), // Rule ID 3178 // |
| 11276 | /* 31862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11277 | /* 31865 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11278 | /* 31868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11279 | /* 31872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11280 | /* 31876 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src) |
| 11281 | /* 31876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11282 | /* 31879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11283 | /* 31881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11284 | /* 31883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11285 | /* 31886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11286 | /* 31892 */ GIR_RootConstrainSelectedInstOperands, |
| 11287 | /* 31893 */ // GIR_Coverage, 3178, |
| 11288 | /* 31893 */ GIR_EraseRootFromParent_Done, |
| 11289 | /* 31894 */ // Label 681: @31894 |
| 11290 | /* 31894 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(31931), // Rule ID 3179 // |
| 11291 | /* 31899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11292 | /* 31902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11293 | /* 31905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11294 | /* 31909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11295 | /* 31913 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src) |
| 11296 | /* 31913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11297 | /* 31916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11298 | /* 31918 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11299 | /* 31920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11300 | /* 31923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11301 | /* 31929 */ GIR_RootConstrainSelectedInstOperands, |
| 11302 | /* 31930 */ // GIR_Coverage, 3179, |
| 11303 | /* 31930 */ GIR_EraseRootFromParent_Done, |
| 11304 | /* 31931 */ // Label 682: @31931 |
| 11305 | /* 31931 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(31968), // Rule ID 3180 // |
| 11306 | /* 31936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11307 | /* 31939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11308 | /* 31942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11309 | /* 31946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11310 | /* 31950 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src) |
| 11311 | /* 31950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11312 | /* 31953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11313 | /* 31955 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11314 | /* 31957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11315 | /* 31960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11316 | /* 31966 */ GIR_RootConstrainSelectedInstOperands, |
| 11317 | /* 31967 */ // GIR_Coverage, 3180, |
| 11318 | /* 31967 */ GIR_EraseRootFromParent_Done, |
| 11319 | /* 31968 */ // Label 683: @31968 |
| 11320 | /* 31968 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(32005), // Rule ID 3181 // |
| 11321 | /* 31973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11322 | /* 31976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11323 | /* 31979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11324 | /* 31983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11325 | /* 31987 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src) |
| 11326 | /* 31987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11327 | /* 31990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11328 | /* 31992 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11329 | /* 31994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11330 | /* 31997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11331 | /* 32003 */ GIR_RootConstrainSelectedInstOperands, |
| 11332 | /* 32004 */ // GIR_Coverage, 3181, |
| 11333 | /* 32004 */ GIR_EraseRootFromParent_Done, |
| 11334 | /* 32005 */ // Label 684: @32005 |
| 11335 | /* 32005 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(32042), // Rule ID 3182 // |
| 11336 | /* 32010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11337 | /* 32013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11338 | /* 32016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11339 | /* 32020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11340 | /* 32024 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src) |
| 11341 | /* 32024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11342 | /* 32027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11343 | /* 32029 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11344 | /* 32031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11345 | /* 32034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11346 | /* 32040 */ GIR_RootConstrainSelectedInstOperands, |
| 11347 | /* 32041 */ // GIR_Coverage, 3182, |
| 11348 | /* 32041 */ GIR_EraseRootFromParent_Done, |
| 11349 | /* 32042 */ // Label 685: @32042 |
| 11350 | /* 32042 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(32079), // Rule ID 3183 // |
| 11351 | /* 32047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11352 | /* 32050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11353 | /* 32053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11354 | /* 32057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11355 | /* 32061 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) |
| 11356 | /* 32061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11357 | /* 32064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11358 | /* 32066 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11359 | /* 32068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11360 | /* 32071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11361 | /* 32077 */ GIR_RootConstrainSelectedInstOperands, |
| 11362 | /* 32078 */ // GIR_Coverage, 3183, |
| 11363 | /* 32078 */ GIR_EraseRootFromParent_Done, |
| 11364 | /* 32079 */ // Label 686: @32079 |
| 11365 | /* 32079 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(32116), // Rule ID 3184 // |
| 11366 | /* 32084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11367 | /* 32087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11368 | /* 32090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11369 | /* 32094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11370 | /* 32098 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) |
| 11371 | /* 32098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11372 | /* 32101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11373 | /* 32103 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11374 | /* 32105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11375 | /* 32108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11376 | /* 32114 */ GIR_RootConstrainSelectedInstOperands, |
| 11377 | /* 32115 */ // GIR_Coverage, 3184, |
| 11378 | /* 32115 */ GIR_EraseRootFromParent_Done, |
| 11379 | /* 32116 */ // Label 687: @32116 |
| 11380 | /* 32116 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(32153), // Rule ID 3185 // |
| 11381 | /* 32121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11382 | /* 32124 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11383 | /* 32127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11384 | /* 32131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11385 | /* 32135 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) |
| 11386 | /* 32135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11387 | /* 32138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11388 | /* 32140 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11389 | /* 32142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11390 | /* 32145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11391 | /* 32151 */ GIR_RootConstrainSelectedInstOperands, |
| 11392 | /* 32152 */ // GIR_Coverage, 3185, |
| 11393 | /* 32152 */ GIR_EraseRootFromParent_Done, |
| 11394 | /* 32153 */ // Label 688: @32153 |
| 11395 | /* 32153 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(32190), // Rule ID 3186 // |
| 11396 | /* 32158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11397 | /* 32161 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11398 | /* 32164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11399 | /* 32168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11400 | /* 32172 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) |
| 11401 | /* 32172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11402 | /* 32175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11403 | /* 32177 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11404 | /* 32179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11405 | /* 32182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11406 | /* 32188 */ GIR_RootConstrainSelectedInstOperands, |
| 11407 | /* 32189 */ // GIR_Coverage, 3186, |
| 11408 | /* 32189 */ GIR_EraseRootFromParent_Done, |
| 11409 | /* 32190 */ // Label 689: @32190 |
| 11410 | /* 32190 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(32227), // Rule ID 3187 // |
| 11411 | /* 32195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11412 | /* 32198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11413 | /* 32201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11414 | /* 32205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11415 | /* 32209 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) |
| 11416 | /* 32209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11417 | /* 32212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11418 | /* 32214 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11419 | /* 32216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11420 | /* 32219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11421 | /* 32225 */ GIR_RootConstrainSelectedInstOperands, |
| 11422 | /* 32226 */ // GIR_Coverage, 3187, |
| 11423 | /* 32226 */ GIR_EraseRootFromParent_Done, |
| 11424 | /* 32227 */ // Label 690: @32227 |
| 11425 | /* 32227 */ GIM_Reject, |
| 11426 | /* 32228 */ // Label 657: @32228 |
| 11427 | /* 32228 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(32260), // Rule ID 3096 // |
| 11428 | /* 32233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11429 | /* 32236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11430 | /* 32239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11431 | /* 32243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11432 | /* 32247 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src |
| 11433 | /* 32247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11434 | /* 32250 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11435 | /* 32252 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11436 | /* 32254 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11437 | /* 32259 */ // GIR_Coverage, 3096, |
| 11438 | /* 32259 */ GIR_EraseRootFromParent_Done, |
| 11439 | /* 32260 */ // Label 691: @32260 |
| 11440 | /* 32260 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(32292), // Rule ID 3097 // |
| 11441 | /* 32265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11442 | /* 32268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11443 | /* 32271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11444 | /* 32275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11445 | /* 32279 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src |
| 11446 | /* 32279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11447 | /* 32282 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11448 | /* 32284 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11449 | /* 32286 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11450 | /* 32291 */ // GIR_Coverage, 3097, |
| 11451 | /* 32291 */ GIR_EraseRootFromParent_Done, |
| 11452 | /* 32292 */ // Label 692: @32292 |
| 11453 | /* 32292 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(32324), // Rule ID 3116 // |
| 11454 | /* 32297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11455 | /* 32300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11456 | /* 32303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11457 | /* 32307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11458 | /* 32311 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 11459 | /* 32311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11460 | /* 32314 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11461 | /* 32316 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11462 | /* 32318 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11463 | /* 32323 */ // GIR_Coverage, 3116, |
| 11464 | /* 32323 */ GIR_EraseRootFromParent_Done, |
| 11465 | /* 32324 */ // Label 693: @32324 |
| 11466 | /* 32324 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(32356), // Rule ID 3117 // |
| 11467 | /* 32329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11468 | /* 32332 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11469 | /* 32335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11470 | /* 32339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11471 | /* 32343 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 11472 | /* 32343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11473 | /* 32346 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11474 | /* 32348 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11475 | /* 32350 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11476 | /* 32355 */ // GIR_Coverage, 3117, |
| 11477 | /* 32355 */ GIR_EraseRootFromParent_Done, |
| 11478 | /* 32356 */ // Label 694: @32356 |
| 11479 | /* 32356 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(32388), // Rule ID 3118 // |
| 11480 | /* 32361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11481 | /* 32364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11482 | /* 32367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11483 | /* 32371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11484 | /* 32375 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 11485 | /* 32375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11486 | /* 32378 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11487 | /* 32380 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11488 | /* 32382 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11489 | /* 32387 */ // GIR_Coverage, 3118, |
| 11490 | /* 32387 */ GIR_EraseRootFromParent_Done, |
| 11491 | /* 32388 */ // Label 695: @32388 |
| 11492 | /* 32388 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(32420), // Rule ID 3119 // |
| 11493 | /* 32393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11494 | /* 32396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11495 | /* 32399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11496 | /* 32403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11497 | /* 32407 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 11498 | /* 32407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11499 | /* 32410 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11500 | /* 32412 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11501 | /* 32414 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11502 | /* 32419 */ // GIR_Coverage, 3119, |
| 11503 | /* 32419 */ GIR_EraseRootFromParent_Done, |
| 11504 | /* 32420 */ // Label 696: @32420 |
| 11505 | /* 32420 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(32452), // Rule ID 3120 // |
| 11506 | /* 32425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11507 | /* 32428 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11508 | /* 32431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11509 | /* 32435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11510 | /* 32439 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src |
| 11511 | /* 32439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11512 | /* 32442 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11513 | /* 32444 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11514 | /* 32446 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11515 | /* 32451 */ // GIR_Coverage, 3120, |
| 11516 | /* 32451 */ GIR_EraseRootFromParent_Done, |
| 11517 | /* 32452 */ // Label 697: @32452 |
| 11518 | /* 32452 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(32484), // Rule ID 3121 // |
| 11519 | /* 32457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11520 | /* 32460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11521 | /* 32463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11522 | /* 32467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11523 | /* 32471 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 11524 | /* 32471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11525 | /* 32474 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11526 | /* 32476 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11527 | /* 32478 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11528 | /* 32483 */ // GIR_Coverage, 3121, |
| 11529 | /* 32483 */ GIR_EraseRootFromParent_Done, |
| 11530 | /* 32484 */ // Label 698: @32484 |
| 11531 | /* 32484 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(32516), // Rule ID 3122 // |
| 11532 | /* 32489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11533 | /* 32492 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11534 | /* 32495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11535 | /* 32499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11536 | /* 32503 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 11537 | /* 32503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11538 | /* 32506 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11539 | /* 32508 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11540 | /* 32510 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11541 | /* 32515 */ // GIR_Coverage, 3122, |
| 11542 | /* 32515 */ GIR_EraseRootFromParent_Done, |
| 11543 | /* 32516 */ // Label 699: @32516 |
| 11544 | /* 32516 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(32548), // Rule ID 3123 // |
| 11545 | /* 32521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11546 | /* 32524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11547 | /* 32527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11548 | /* 32531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11549 | /* 32535 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 11550 | /* 32535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11551 | /* 32538 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11552 | /* 32540 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11553 | /* 32542 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11554 | /* 32547 */ // GIR_Coverage, 3123, |
| 11555 | /* 32547 */ GIR_EraseRootFromParent_Done, |
| 11556 | /* 32548 */ // Label 700: @32548 |
| 11557 | /* 32548 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(32580), // Rule ID 3124 // |
| 11558 | /* 32553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11559 | /* 32556 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11560 | /* 32559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11561 | /* 32563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11562 | /* 32567 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 11563 | /* 32567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11564 | /* 32570 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11565 | /* 32572 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11566 | /* 32574 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11567 | /* 32579 */ // GIR_Coverage, 3124, |
| 11568 | /* 32579 */ GIR_EraseRootFromParent_Done, |
| 11569 | /* 32580 */ // Label 701: @32580 |
| 11570 | /* 32580 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(32612), // Rule ID 3125 // |
| 11571 | /* 32585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11572 | /* 32588 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11573 | /* 32591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11574 | /* 32595 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11575 | /* 32599 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src |
| 11576 | /* 32599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11577 | /* 32602 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11578 | /* 32604 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11579 | /* 32606 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11580 | /* 32611 */ // GIR_Coverage, 3125, |
| 11581 | /* 32611 */ GIR_EraseRootFromParent_Done, |
| 11582 | /* 32612 */ // Label 702: @32612 |
| 11583 | /* 32612 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(32649), // Rule ID 3188 // |
| 11584 | /* 32617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11585 | /* 32620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11586 | /* 32623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11587 | /* 32627 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11588 | /* 32631 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src) |
| 11589 | /* 32631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11590 | /* 32634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11591 | /* 32636 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11592 | /* 32638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11593 | /* 32641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11594 | /* 32647 */ GIR_RootConstrainSelectedInstOperands, |
| 11595 | /* 32648 */ // GIR_Coverage, 3188, |
| 11596 | /* 32648 */ GIR_EraseRootFromParent_Done, |
| 11597 | /* 32649 */ // Label 703: @32649 |
| 11598 | /* 32649 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(32686), // Rule ID 3189 // |
| 11599 | /* 32654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11600 | /* 32657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11601 | /* 32660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11602 | /* 32664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11603 | /* 32668 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) |
| 11604 | /* 32668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11605 | /* 32671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11606 | /* 32673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11607 | /* 32675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11608 | /* 32678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11609 | /* 32684 */ GIR_RootConstrainSelectedInstOperands, |
| 11610 | /* 32685 */ // GIR_Coverage, 3189, |
| 11611 | /* 32685 */ GIR_EraseRootFromParent_Done, |
| 11612 | /* 32686 */ // Label 704: @32686 |
| 11613 | /* 32686 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(32723), // Rule ID 3190 // |
| 11614 | /* 32691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11615 | /* 32694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11616 | /* 32697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11617 | /* 32701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11618 | /* 32705 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) |
| 11619 | /* 32705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11620 | /* 32708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11621 | /* 32710 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11622 | /* 32712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11623 | /* 32715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11624 | /* 32721 */ GIR_RootConstrainSelectedInstOperands, |
| 11625 | /* 32722 */ // GIR_Coverage, 3190, |
| 11626 | /* 32722 */ GIR_EraseRootFromParent_Done, |
| 11627 | /* 32723 */ // Label 705: @32723 |
| 11628 | /* 32723 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(32760), // Rule ID 3191 // |
| 11629 | /* 32728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11630 | /* 32731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11631 | /* 32734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11632 | /* 32738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11633 | /* 32742 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) |
| 11634 | /* 32742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11635 | /* 32745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11636 | /* 32747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11637 | /* 32749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11638 | /* 32752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11639 | /* 32758 */ GIR_RootConstrainSelectedInstOperands, |
| 11640 | /* 32759 */ // GIR_Coverage, 3191, |
| 11641 | /* 32759 */ GIR_EraseRootFromParent_Done, |
| 11642 | /* 32760 */ // Label 706: @32760 |
| 11643 | /* 32760 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(32797), // Rule ID 3192 // |
| 11644 | /* 32765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11645 | /* 32768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11646 | /* 32771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11647 | /* 32775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11648 | /* 32779 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) |
| 11649 | /* 32779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11650 | /* 32782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11651 | /* 32784 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11652 | /* 32786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11653 | /* 32789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11654 | /* 32795 */ GIR_RootConstrainSelectedInstOperands, |
| 11655 | /* 32796 */ // GIR_Coverage, 3192, |
| 11656 | /* 32796 */ GIR_EraseRootFromParent_Done, |
| 11657 | /* 32797 */ // Label 707: @32797 |
| 11658 | /* 32797 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(32834), // Rule ID 3193 // |
| 11659 | /* 32802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11660 | /* 32805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11661 | /* 32808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11662 | /* 32812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11663 | /* 32816 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src) |
| 11664 | /* 32816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11665 | /* 32819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11666 | /* 32821 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11667 | /* 32823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11668 | /* 32826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11669 | /* 32832 */ GIR_RootConstrainSelectedInstOperands, |
| 11670 | /* 32833 */ // GIR_Coverage, 3193, |
| 11671 | /* 32833 */ GIR_EraseRootFromParent_Done, |
| 11672 | /* 32834 */ // Label 708: @32834 |
| 11673 | /* 32834 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(32871), // Rule ID 3194 // |
| 11674 | /* 32839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11675 | /* 32842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11676 | /* 32845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11677 | /* 32849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11678 | /* 32853 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) |
| 11679 | /* 32853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11680 | /* 32856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11681 | /* 32858 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11682 | /* 32860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11683 | /* 32863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11684 | /* 32869 */ GIR_RootConstrainSelectedInstOperands, |
| 11685 | /* 32870 */ // GIR_Coverage, 3194, |
| 11686 | /* 32870 */ GIR_EraseRootFromParent_Done, |
| 11687 | /* 32871 */ // Label 709: @32871 |
| 11688 | /* 32871 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(32908), // Rule ID 3195 // |
| 11689 | /* 32876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11690 | /* 32879 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11691 | /* 32882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11692 | /* 32886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11693 | /* 32890 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) |
| 11694 | /* 32890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11695 | /* 32893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11696 | /* 32895 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11697 | /* 32897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11698 | /* 32900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11699 | /* 32906 */ GIR_RootConstrainSelectedInstOperands, |
| 11700 | /* 32907 */ // GIR_Coverage, 3195, |
| 11701 | /* 32907 */ GIR_EraseRootFromParent_Done, |
| 11702 | /* 32908 */ // Label 710: @32908 |
| 11703 | /* 32908 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(32945), // Rule ID 3196 // |
| 11704 | /* 32913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11705 | /* 32916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11706 | /* 32919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11707 | /* 32923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11708 | /* 32927 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) |
| 11709 | /* 32927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11710 | /* 32930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11711 | /* 32932 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11712 | /* 32934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11713 | /* 32937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11714 | /* 32943 */ GIR_RootConstrainSelectedInstOperands, |
| 11715 | /* 32944 */ // GIR_Coverage, 3196, |
| 11716 | /* 32944 */ GIR_EraseRootFromParent_Done, |
| 11717 | /* 32945 */ // Label 711: @32945 |
| 11718 | /* 32945 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(32982), // Rule ID 3197 // |
| 11719 | /* 32950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11720 | /* 32953 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11721 | /* 32956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11722 | /* 32960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11723 | /* 32964 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) |
| 11724 | /* 32964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11725 | /* 32967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11726 | /* 32969 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11727 | /* 32971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11728 | /* 32974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11729 | /* 32980 */ GIR_RootConstrainSelectedInstOperands, |
| 11730 | /* 32981 */ // GIR_Coverage, 3197, |
| 11731 | /* 32981 */ GIR_EraseRootFromParent_Done, |
| 11732 | /* 32982 */ // Label 712: @32982 |
| 11733 | /* 32982 */ GIM_Reject, |
| 11734 | /* 32983 */ // Label 658: @32983 |
| 11735 | /* 32983 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(33015), // Rule ID 3100 // |
| 11736 | /* 32988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11737 | /* 32991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11738 | /* 32994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11739 | /* 32998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11740 | /* 33002 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src |
| 11741 | /* 33002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11742 | /* 33005 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11743 | /* 33007 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11744 | /* 33009 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11745 | /* 33014 */ // GIR_Coverage, 3100, |
| 11746 | /* 33014 */ GIR_EraseRootFromParent_Done, |
| 11747 | /* 33015 */ // Label 713: @33015 |
| 11748 | /* 33015 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(33047), // Rule ID 3101 // |
| 11749 | /* 33020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11750 | /* 33023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11751 | /* 33026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11752 | /* 33030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11753 | /* 33034 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src |
| 11754 | /* 33034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11755 | /* 33037 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11756 | /* 33039 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11757 | /* 33041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11758 | /* 33046 */ // GIR_Coverage, 3101, |
| 11759 | /* 33046 */ GIR_EraseRootFromParent_Done, |
| 11760 | /* 33047 */ // Label 714: @33047 |
| 11761 | /* 33047 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(33079), // Rule ID 3142 // |
| 11762 | /* 33052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11763 | /* 33055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11764 | /* 33058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11765 | /* 33062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11766 | /* 33066 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 11767 | /* 33066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11768 | /* 33069 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11769 | /* 33071 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11770 | /* 33073 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11771 | /* 33078 */ // GIR_Coverage, 3142, |
| 11772 | /* 33078 */ GIR_EraseRootFromParent_Done, |
| 11773 | /* 33079 */ // Label 715: @33079 |
| 11774 | /* 33079 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(33111), // Rule ID 3143 // |
| 11775 | /* 33084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11776 | /* 33087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11777 | /* 33090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11778 | /* 33094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11779 | /* 33098 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 11780 | /* 33098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11781 | /* 33101 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11782 | /* 33103 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11783 | /* 33105 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11784 | /* 33110 */ // GIR_Coverage, 3143, |
| 11785 | /* 33110 */ GIR_EraseRootFromParent_Done, |
| 11786 | /* 33111 */ // Label 716: @33111 |
| 11787 | /* 33111 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(33143), // Rule ID 3144 // |
| 11788 | /* 33116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11789 | /* 33119 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11790 | /* 33122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11791 | /* 33126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11792 | /* 33130 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 11793 | /* 33130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11794 | /* 33133 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11795 | /* 33135 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11796 | /* 33137 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11797 | /* 33142 */ // GIR_Coverage, 3144, |
| 11798 | /* 33142 */ GIR_EraseRootFromParent_Done, |
| 11799 | /* 33143 */ // Label 717: @33143 |
| 11800 | /* 33143 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(33175), // Rule ID 3145 // |
| 11801 | /* 33148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11802 | /* 33151 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11803 | /* 33154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11804 | /* 33158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11805 | /* 33162 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 11806 | /* 33162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11807 | /* 33165 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11808 | /* 33167 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11809 | /* 33169 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11810 | /* 33174 */ // GIR_Coverage, 3145, |
| 11811 | /* 33174 */ GIR_EraseRootFromParent_Done, |
| 11812 | /* 33175 */ // Label 718: @33175 |
| 11813 | /* 33175 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(33207), // Rule ID 3146 // |
| 11814 | /* 33180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11815 | /* 33183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11816 | /* 33186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11817 | /* 33190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11818 | /* 33194 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src |
| 11819 | /* 33194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11820 | /* 33197 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11821 | /* 33199 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11822 | /* 33201 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11823 | /* 33206 */ // GIR_Coverage, 3146, |
| 11824 | /* 33206 */ GIR_EraseRootFromParent_Done, |
| 11825 | /* 33207 */ // Label 719: @33207 |
| 11826 | /* 33207 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(33239), // Rule ID 3147 // |
| 11827 | /* 33212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11828 | /* 33215 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11829 | /* 33218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11830 | /* 33222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11831 | /* 33226 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 11832 | /* 33226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11833 | /* 33229 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11834 | /* 33231 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11835 | /* 33233 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11836 | /* 33238 */ // GIR_Coverage, 3147, |
| 11837 | /* 33238 */ GIR_EraseRootFromParent_Done, |
| 11838 | /* 33239 */ // Label 720: @33239 |
| 11839 | /* 33239 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(33271), // Rule ID 3148 // |
| 11840 | /* 33244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11841 | /* 33247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11842 | /* 33250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11843 | /* 33254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11844 | /* 33258 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 11845 | /* 33258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11846 | /* 33261 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11847 | /* 33263 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11848 | /* 33265 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11849 | /* 33270 */ // GIR_Coverage, 3148, |
| 11850 | /* 33270 */ GIR_EraseRootFromParent_Done, |
| 11851 | /* 33271 */ // Label 721: @33271 |
| 11852 | /* 33271 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(33303), // Rule ID 3149 // |
| 11853 | /* 33276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11854 | /* 33279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11855 | /* 33282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11856 | /* 33286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11857 | /* 33290 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 11858 | /* 33290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11859 | /* 33293 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11860 | /* 33295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11861 | /* 33297 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11862 | /* 33302 */ // GIR_Coverage, 3149, |
| 11863 | /* 33302 */ GIR_EraseRootFromParent_Done, |
| 11864 | /* 33303 */ // Label 722: @33303 |
| 11865 | /* 33303 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(33335), // Rule ID 3150 // |
| 11866 | /* 33308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11867 | /* 33311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11868 | /* 33314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11869 | /* 33318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11870 | /* 33322 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 11871 | /* 33322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11872 | /* 33325 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11873 | /* 33327 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11874 | /* 33329 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11875 | /* 33334 */ // GIR_Coverage, 3150, |
| 11876 | /* 33334 */ GIR_EraseRootFromParent_Done, |
| 11877 | /* 33335 */ // Label 723: @33335 |
| 11878 | /* 33335 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(33367), // Rule ID 3151 // |
| 11879 | /* 33340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11880 | /* 33343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11881 | /* 33346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11882 | /* 33350 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11883 | /* 33354 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src |
| 11884 | /* 33354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11885 | /* 33357 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11886 | /* 33359 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11887 | /* 33361 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11888 | /* 33366 */ // GIR_Coverage, 3151, |
| 11889 | /* 33366 */ GIR_EraseRootFromParent_Done, |
| 11890 | /* 33367 */ // Label 724: @33367 |
| 11891 | /* 33367 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(33404), // Rule ID 3214 // |
| 11892 | /* 33372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11893 | /* 33375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11894 | /* 33378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11895 | /* 33382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11896 | /* 33386 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) |
| 11897 | /* 33386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11898 | /* 33389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11899 | /* 33391 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11900 | /* 33393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11901 | /* 33396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11902 | /* 33402 */ GIR_RootConstrainSelectedInstOperands, |
| 11903 | /* 33403 */ // GIR_Coverage, 3214, |
| 11904 | /* 33403 */ GIR_EraseRootFromParent_Done, |
| 11905 | /* 33404 */ // Label 725: @33404 |
| 11906 | /* 33404 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(33441), // Rule ID 3215 // |
| 11907 | /* 33409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11908 | /* 33412 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11909 | /* 33415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11910 | /* 33419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11911 | /* 33423 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) |
| 11912 | /* 33423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11913 | /* 33426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11914 | /* 33428 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11915 | /* 33430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11916 | /* 33433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11917 | /* 33439 */ GIR_RootConstrainSelectedInstOperands, |
| 11918 | /* 33440 */ // GIR_Coverage, 3215, |
| 11919 | /* 33440 */ GIR_EraseRootFromParent_Done, |
| 11920 | /* 33441 */ // Label 726: @33441 |
| 11921 | /* 33441 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(33478), // Rule ID 3216 // |
| 11922 | /* 33446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11923 | /* 33449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11924 | /* 33452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11925 | /* 33456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11926 | /* 33460 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) |
| 11927 | /* 33460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11928 | /* 33463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11929 | /* 33465 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11930 | /* 33467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11931 | /* 33470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11932 | /* 33476 */ GIR_RootConstrainSelectedInstOperands, |
| 11933 | /* 33477 */ // GIR_Coverage, 3216, |
| 11934 | /* 33477 */ GIR_EraseRootFromParent_Done, |
| 11935 | /* 33478 */ // Label 727: @33478 |
| 11936 | /* 33478 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(33515), // Rule ID 3217 // |
| 11937 | /* 33483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11938 | /* 33486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11939 | /* 33489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11940 | /* 33493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11941 | /* 33497 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) |
| 11942 | /* 33497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11943 | /* 33500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11944 | /* 33502 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11945 | /* 33504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11946 | /* 33507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11947 | /* 33513 */ GIR_RootConstrainSelectedInstOperands, |
| 11948 | /* 33514 */ // GIR_Coverage, 3217, |
| 11949 | /* 33514 */ GIR_EraseRootFromParent_Done, |
| 11950 | /* 33515 */ // Label 728: @33515 |
| 11951 | /* 33515 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(33552), // Rule ID 3218 // |
| 11952 | /* 33520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11953 | /* 33523 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11954 | /* 33526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11955 | /* 33530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11956 | /* 33534 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) |
| 11957 | /* 33534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 11958 | /* 33537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11959 | /* 33539 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11960 | /* 33541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11961 | /* 33544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11962 | /* 33550 */ GIR_RootConstrainSelectedInstOperands, |
| 11963 | /* 33551 */ // GIR_Coverage, 3218, |
| 11964 | /* 33551 */ GIR_EraseRootFromParent_Done, |
| 11965 | /* 33552 */ // Label 729: @33552 |
| 11966 | /* 33552 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(33589), // Rule ID 3219 // |
| 11967 | /* 33557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11968 | /* 33560 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11969 | /* 33563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11970 | /* 33567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11971 | /* 33571 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) |
| 11972 | /* 33571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11973 | /* 33574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11974 | /* 33576 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11975 | /* 33578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11976 | /* 33581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11977 | /* 33587 */ GIR_RootConstrainSelectedInstOperands, |
| 11978 | /* 33588 */ // GIR_Coverage, 3219, |
| 11979 | /* 33588 */ GIR_EraseRootFromParent_Done, |
| 11980 | /* 33589 */ // Label 730: @33589 |
| 11981 | /* 33589 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(33626), // Rule ID 3220 // |
| 11982 | /* 33594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11983 | /* 33597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11984 | /* 33600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11985 | /* 33604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11986 | /* 33608 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) |
| 11987 | /* 33608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11988 | /* 33611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11989 | /* 33613 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11990 | /* 33615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11991 | /* 33618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11992 | /* 33624 */ GIR_RootConstrainSelectedInstOperands, |
| 11993 | /* 33625 */ // GIR_Coverage, 3220, |
| 11994 | /* 33625 */ GIR_EraseRootFromParent_Done, |
| 11995 | /* 33626 */ // Label 731: @33626 |
| 11996 | /* 33626 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(33663), // Rule ID 3221 // |
| 11997 | /* 33631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11998 | /* 33634 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11999 | /* 33637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12000 | /* 33641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12001 | /* 33645 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) |
| 12002 | /* 33645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12003 | /* 33648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12004 | /* 33650 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12005 | /* 33652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12006 | /* 33655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12007 | /* 33661 */ GIR_RootConstrainSelectedInstOperands, |
| 12008 | /* 33662 */ // GIR_Coverage, 3221, |
| 12009 | /* 33662 */ GIR_EraseRootFromParent_Done, |
| 12010 | /* 33663 */ // Label 732: @33663 |
| 12011 | /* 33663 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(33700), // Rule ID 3222 // |
| 12012 | /* 33668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12013 | /* 33671 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12014 | /* 33674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12015 | /* 33678 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12016 | /* 33682 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) |
| 12017 | /* 33682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12018 | /* 33685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12019 | /* 33687 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12020 | /* 33689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12021 | /* 33692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12022 | /* 33698 */ GIR_RootConstrainSelectedInstOperands, |
| 12023 | /* 33699 */ // GIR_Coverage, 3222, |
| 12024 | /* 33699 */ GIR_EraseRootFromParent_Done, |
| 12025 | /* 33700 */ // Label 733: @33700 |
| 12026 | /* 33700 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(33737), // Rule ID 3223 // |
| 12027 | /* 33705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12028 | /* 33708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12029 | /* 33711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12030 | /* 33715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12031 | /* 33719 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) |
| 12032 | /* 33719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 12033 | /* 33722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12034 | /* 33724 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12035 | /* 33726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12036 | /* 33729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12037 | /* 33735 */ GIR_RootConstrainSelectedInstOperands, |
| 12038 | /* 33736 */ // GIR_Coverage, 3223, |
| 12039 | /* 33736 */ GIR_EraseRootFromParent_Done, |
| 12040 | /* 33737 */ // Label 734: @33737 |
| 12041 | /* 33737 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(33769), // Rule ID 5797 // |
| 12042 | /* 33742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 12043 | /* 33745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12044 | /* 33748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12045 | /* 33752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12046 | /* 33756 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 12047 | /* 33756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12048 | /* 33759 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12049 | /* 33761 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12050 | /* 33763 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12051 | /* 33768 */ // GIR_Coverage, 5797, |
| 12052 | /* 33768 */ GIR_EraseRootFromParent_Done, |
| 12053 | /* 33769 */ // Label 735: @33769 |
| 12054 | /* 33769 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(33801), // Rule ID 5798 // |
| 12055 | /* 33774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 12056 | /* 33777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12057 | /* 33780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12058 | /* 33784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12059 | /* 33788 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 12060 | /* 33788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12061 | /* 33791 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12062 | /* 33793 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12063 | /* 33795 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12064 | /* 33800 */ // GIR_Coverage, 5798, |
| 12065 | /* 33800 */ GIR_EraseRootFromParent_Done, |
| 12066 | /* 33801 */ // Label 736: @33801 |
| 12067 | /* 33801 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(33833), // Rule ID 5803 // |
| 12068 | /* 33806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12069 | /* 33809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12070 | /* 33812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12071 | /* 33816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12072 | /* 33820 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 12073 | /* 33820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12074 | /* 33823 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12075 | /* 33825 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12076 | /* 33827 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12077 | /* 33832 */ // GIR_Coverage, 5803, |
| 12078 | /* 33832 */ GIR_EraseRootFromParent_Done, |
| 12079 | /* 33833 */ // Label 737: @33833 |
| 12080 | /* 33833 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(33865), // Rule ID 5804 // |
| 12081 | /* 33838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12082 | /* 33841 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12083 | /* 33844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12084 | /* 33848 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12085 | /* 33852 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 12086 | /* 33852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12087 | /* 33855 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12088 | /* 33857 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12089 | /* 33859 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12090 | /* 33864 */ // GIR_Coverage, 5804, |
| 12091 | /* 33864 */ GIR_EraseRootFromParent_Done, |
| 12092 | /* 33865 */ // Label 738: @33865 |
| 12093 | /* 33865 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(33897), // Rule ID 5805 // |
| 12094 | /* 33870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12095 | /* 33873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12096 | /* 33876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12097 | /* 33880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12098 | /* 33884 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 12099 | /* 33884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12100 | /* 33887 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12101 | /* 33889 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12102 | /* 33891 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12103 | /* 33896 */ // GIR_Coverage, 5805, |
| 12104 | /* 33896 */ GIR_EraseRootFromParent_Done, |
| 12105 | /* 33897 */ // Label 739: @33897 |
| 12106 | /* 33897 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(33929), // Rule ID 5806 // |
| 12107 | /* 33902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12108 | /* 33905 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12109 | /* 33908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12110 | /* 33912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12111 | /* 33916 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 12112 | /* 33916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12113 | /* 33919 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12114 | /* 33921 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12115 | /* 33923 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12116 | /* 33928 */ // GIR_Coverage, 5806, |
| 12117 | /* 33928 */ GIR_EraseRootFromParent_Done, |
| 12118 | /* 33929 */ // Label 740: @33929 |
| 12119 | /* 33929 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(33961), // Rule ID 5807 // |
| 12120 | /* 33934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12121 | /* 33937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12122 | /* 33940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12123 | /* 33944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12124 | /* 33948 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 12125 | /* 33948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12126 | /* 33951 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12127 | /* 33953 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12128 | /* 33955 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12129 | /* 33960 */ // GIR_Coverage, 5807, |
| 12130 | /* 33960 */ GIR_EraseRootFromParent_Done, |
| 12131 | /* 33961 */ // Label 741: @33961 |
| 12132 | /* 33961 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(33993), // Rule ID 5808 // |
| 12133 | /* 33966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12134 | /* 33969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12135 | /* 33972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12136 | /* 33976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12137 | /* 33980 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 12138 | /* 33980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12139 | /* 33983 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12140 | /* 33985 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12141 | /* 33987 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12142 | /* 33992 */ // GIR_Coverage, 5808, |
| 12143 | /* 33992 */ GIR_EraseRootFromParent_Done, |
| 12144 | /* 33993 */ // Label 742: @33993 |
| 12145 | /* 33993 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(34025), // Rule ID 5809 // |
| 12146 | /* 33998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12147 | /* 34001 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12148 | /* 34004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12149 | /* 34008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12150 | /* 34012 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 12151 | /* 34012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12152 | /* 34015 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12153 | /* 34017 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12154 | /* 34019 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12155 | /* 34024 */ // GIR_Coverage, 5809, |
| 12156 | /* 34024 */ GIR_EraseRootFromParent_Done, |
| 12157 | /* 34025 */ // Label 743: @34025 |
| 12158 | /* 34025 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(34057), // Rule ID 5810 // |
| 12159 | /* 34030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12160 | /* 34033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12161 | /* 34036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12162 | /* 34040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12163 | /* 34044 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 12164 | /* 34044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12165 | /* 34047 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12166 | /* 34049 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12167 | /* 34051 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12168 | /* 34056 */ // GIR_Coverage, 5810, |
| 12169 | /* 34056 */ GIR_EraseRootFromParent_Done, |
| 12170 | /* 34057 */ // Label 744: @34057 |
| 12171 | /* 34057 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(34089), // Rule ID 5811 // |
| 12172 | /* 34062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12173 | /* 34065 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12174 | /* 34068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12175 | /* 34072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12176 | /* 34076 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 12177 | /* 34076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12178 | /* 34079 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12179 | /* 34081 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12180 | /* 34083 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12181 | /* 34088 */ // GIR_Coverage, 5811, |
| 12182 | /* 34088 */ GIR_EraseRootFromParent_Done, |
| 12183 | /* 34089 */ // Label 745: @34089 |
| 12184 | /* 34089 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(34121), // Rule ID 5812 // |
| 12185 | /* 34094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12186 | /* 34097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12187 | /* 34100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12188 | /* 34104 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12189 | /* 34108 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 12190 | /* 34108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12191 | /* 34111 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12192 | /* 34113 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12193 | /* 34115 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12194 | /* 34120 */ // GIR_Coverage, 5812, |
| 12195 | /* 34120 */ GIR_EraseRootFromParent_Done, |
| 12196 | /* 34121 */ // Label 746: @34121 |
| 12197 | /* 34121 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(34179), // Rule ID 5839 // |
| 12198 | /* 34126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12199 | /* 34129 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12200 | /* 34132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12201 | /* 34136 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12202 | /* 34140 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) |
| 12203 | /* 34140 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12204 | /* 34143 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12205 | /* 34147 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12206 | /* 34152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 12207 | /* 34155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12208 | /* 34157 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12209 | /* 34159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12210 | /* 34162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12211 | /* 34168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12212 | /* 34174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12213 | /* 34177 */ GIR_RootConstrainSelectedInstOperands, |
| 12214 | /* 34178 */ // GIR_Coverage, 5839, |
| 12215 | /* 34178 */ GIR_EraseRootFromParent_Done, |
| 12216 | /* 34179 */ // Label 747: @34179 |
| 12217 | /* 34179 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(34237), // Rule ID 5840 // |
| 12218 | /* 34184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12219 | /* 34187 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12220 | /* 34190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12221 | /* 34194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12222 | /* 34198 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) |
| 12223 | /* 34198 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12224 | /* 34201 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12225 | /* 34205 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12226 | /* 34210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 12227 | /* 34213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12228 | /* 34215 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12229 | /* 34217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12230 | /* 34220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12231 | /* 34226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12232 | /* 34232 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12233 | /* 34235 */ GIR_RootConstrainSelectedInstOperands, |
| 12234 | /* 34236 */ // GIR_Coverage, 5840, |
| 12235 | /* 34236 */ GIR_EraseRootFromParent_Done, |
| 12236 | /* 34237 */ // Label 748: @34237 |
| 12237 | /* 34237 */ GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(34295), // Rule ID 5841 // |
| 12238 | /* 34242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12239 | /* 34245 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12240 | /* 34248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12241 | /* 34252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12242 | /* 34256 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) |
| 12243 | /* 34256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12244 | /* 34259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12245 | /* 34263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12246 | /* 34268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12247 | /* 34271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12248 | /* 34273 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12249 | /* 34275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12250 | /* 34278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12251 | /* 34284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12252 | /* 34290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12253 | /* 34293 */ GIR_RootConstrainSelectedInstOperands, |
| 12254 | /* 34294 */ // GIR_Coverage, 5841, |
| 12255 | /* 34294 */ GIR_EraseRootFromParent_Done, |
| 12256 | /* 34295 */ // Label 749: @34295 |
| 12257 | /* 34295 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(34353), // Rule ID 5842 // |
| 12258 | /* 34300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12259 | /* 34303 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12260 | /* 34306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12261 | /* 34310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12262 | /* 34314 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) |
| 12263 | /* 34314 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12264 | /* 34317 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12265 | /* 34321 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12266 | /* 34326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12267 | /* 34329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12268 | /* 34331 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12269 | /* 34333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12270 | /* 34336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12271 | /* 34342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12272 | /* 34348 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12273 | /* 34351 */ GIR_RootConstrainSelectedInstOperands, |
| 12274 | /* 34352 */ // GIR_Coverage, 5842, |
| 12275 | /* 34352 */ GIR_EraseRootFromParent_Done, |
| 12276 | /* 34353 */ // Label 750: @34353 |
| 12277 | /* 34353 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(34411), // Rule ID 5843 // |
| 12278 | /* 34358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12279 | /* 34361 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12280 | /* 34364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12281 | /* 34368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12282 | /* 34372 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) |
| 12283 | /* 34372 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12284 | /* 34375 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12285 | /* 34379 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12286 | /* 34384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 12287 | /* 34387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12288 | /* 34389 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12289 | /* 34391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12290 | /* 34394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12291 | /* 34400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12292 | /* 34406 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12293 | /* 34409 */ GIR_RootConstrainSelectedInstOperands, |
| 12294 | /* 34410 */ // GIR_Coverage, 5843, |
| 12295 | /* 34410 */ GIR_EraseRootFromParent_Done, |
| 12296 | /* 34411 */ // Label 751: @34411 |
| 12297 | /* 34411 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(34469), // Rule ID 5844 // |
| 12298 | /* 34416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12299 | /* 34419 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12300 | /* 34422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12301 | /* 34426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12302 | /* 34430 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) |
| 12303 | /* 34430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12304 | /* 34433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12305 | /* 34437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12306 | /* 34442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 12307 | /* 34445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12308 | /* 34447 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12309 | /* 34449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12310 | /* 34452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12311 | /* 34458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12312 | /* 34464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12313 | /* 34467 */ GIR_RootConstrainSelectedInstOperands, |
| 12314 | /* 34468 */ // GIR_Coverage, 5844, |
| 12315 | /* 34468 */ GIR_EraseRootFromParent_Done, |
| 12316 | /* 34469 */ // Label 752: @34469 |
| 12317 | /* 34469 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(34527), // Rule ID 5845 // |
| 12318 | /* 34474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12319 | /* 34477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12320 | /* 34480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12321 | /* 34484 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12322 | /* 34488 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) |
| 12323 | /* 34488 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12324 | /* 34491 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12325 | /* 34495 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12326 | /* 34500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 12327 | /* 34503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12328 | /* 34505 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12329 | /* 34507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12330 | /* 34510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12331 | /* 34516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12332 | /* 34522 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12333 | /* 34525 */ GIR_RootConstrainSelectedInstOperands, |
| 12334 | /* 34526 */ // GIR_Coverage, 5845, |
| 12335 | /* 34526 */ GIR_EraseRootFromParent_Done, |
| 12336 | /* 34527 */ // Label 753: @34527 |
| 12337 | /* 34527 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(34585), // Rule ID 5846 // |
| 12338 | /* 34532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12339 | /* 34535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12340 | /* 34538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12341 | /* 34542 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12342 | /* 34546 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) |
| 12343 | /* 34546 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12344 | /* 34549 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12345 | /* 34553 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12346 | /* 34558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12347 | /* 34561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12348 | /* 34563 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12349 | /* 34565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12350 | /* 34568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12351 | /* 34574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12352 | /* 34580 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12353 | /* 34583 */ GIR_RootConstrainSelectedInstOperands, |
| 12354 | /* 34584 */ // GIR_Coverage, 5846, |
| 12355 | /* 34584 */ GIR_EraseRootFromParent_Done, |
| 12356 | /* 34585 */ // Label 754: @34585 |
| 12357 | /* 34585 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(34643), // Rule ID 5847 // |
| 12358 | /* 34590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12359 | /* 34593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12360 | /* 34596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12361 | /* 34600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12362 | /* 34604 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) |
| 12363 | /* 34604 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12364 | /* 34607 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12365 | /* 34611 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12366 | /* 34616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12367 | /* 34619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12368 | /* 34621 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12369 | /* 34623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12370 | /* 34626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12371 | /* 34632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12372 | /* 34638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12373 | /* 34641 */ GIR_RootConstrainSelectedInstOperands, |
| 12374 | /* 34642 */ // GIR_Coverage, 5847, |
| 12375 | /* 34642 */ GIR_EraseRootFromParent_Done, |
| 12376 | /* 34643 */ // Label 755: @34643 |
| 12377 | /* 34643 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(34701), // Rule ID 5848 // |
| 12378 | /* 34648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12379 | /* 34651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12380 | /* 34654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12381 | /* 34658 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12382 | /* 34662 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) |
| 12383 | /* 34662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12384 | /* 34665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12385 | /* 34669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12386 | /* 34674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 12387 | /* 34677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12388 | /* 34679 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12389 | /* 34681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12390 | /* 34684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12391 | /* 34690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12392 | /* 34696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12393 | /* 34699 */ GIR_RootConstrainSelectedInstOperands, |
| 12394 | /* 34700 */ // GIR_Coverage, 5848, |
| 12395 | /* 34700 */ GIR_EraseRootFromParent_Done, |
| 12396 | /* 34701 */ // Label 756: @34701 |
| 12397 | /* 34701 */ GIM_Reject, |
| 12398 | /* 34702 */ // Label 659: @34702 |
| 12399 | /* 34702 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(34734), // Rule ID 3098 // |
| 12400 | /* 34707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12401 | /* 34710 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12402 | /* 34713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12403 | /* 34717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12404 | /* 34721 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src |
| 12405 | /* 34721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12406 | /* 34724 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12407 | /* 34726 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12408 | /* 34728 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12409 | /* 34733 */ // GIR_Coverage, 3098, |
| 12410 | /* 34733 */ GIR_EraseRootFromParent_Done, |
| 12411 | /* 34734 */ // Label 757: @34734 |
| 12412 | /* 34734 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(34766), // Rule ID 3099 // |
| 12413 | /* 34739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12414 | /* 34742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12415 | /* 34745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12416 | /* 34749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12417 | /* 34753 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src |
| 12418 | /* 34753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12419 | /* 34756 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12420 | /* 34758 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12421 | /* 34760 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12422 | /* 34765 */ // GIR_Coverage, 3099, |
| 12423 | /* 34765 */ GIR_EraseRootFromParent_Done, |
| 12424 | /* 34766 */ // Label 758: @34766 |
| 12425 | /* 34766 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(34798), // Rule ID 3126 // |
| 12426 | /* 34771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12427 | /* 34774 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12428 | /* 34777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12429 | /* 34781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12430 | /* 34785 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 12431 | /* 34785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12432 | /* 34788 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12433 | /* 34790 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12434 | /* 34792 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12435 | /* 34797 */ // GIR_Coverage, 3126, |
| 12436 | /* 34797 */ GIR_EraseRootFromParent_Done, |
| 12437 | /* 34798 */ // Label 759: @34798 |
| 12438 | /* 34798 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(34830), // Rule ID 3127 // |
| 12439 | /* 34803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12440 | /* 34806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12441 | /* 34809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12442 | /* 34813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12443 | /* 34817 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 12444 | /* 34817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12445 | /* 34820 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12446 | /* 34822 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12447 | /* 34824 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12448 | /* 34829 */ // GIR_Coverage, 3127, |
| 12449 | /* 34829 */ GIR_EraseRootFromParent_Done, |
| 12450 | /* 34830 */ // Label 760: @34830 |
| 12451 | /* 34830 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(34862), // Rule ID 3128 // |
| 12452 | /* 34835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12453 | /* 34838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12454 | /* 34841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12455 | /* 34845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12456 | /* 34849 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 12457 | /* 34849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12458 | /* 34852 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12459 | /* 34854 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12460 | /* 34856 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12461 | /* 34861 */ // GIR_Coverage, 3128, |
| 12462 | /* 34861 */ GIR_EraseRootFromParent_Done, |
| 12463 | /* 34862 */ // Label 761: @34862 |
| 12464 | /* 34862 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(34894), // Rule ID 3129 // |
| 12465 | /* 34867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12466 | /* 34870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12467 | /* 34873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12468 | /* 34877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12469 | /* 34881 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 12470 | /* 34881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12471 | /* 34884 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12472 | /* 34886 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12473 | /* 34888 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12474 | /* 34893 */ // GIR_Coverage, 3129, |
| 12475 | /* 34893 */ GIR_EraseRootFromParent_Done, |
| 12476 | /* 34894 */ // Label 762: @34894 |
| 12477 | /* 34894 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(34926), // Rule ID 3130 // |
| 12478 | /* 34899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12479 | /* 34902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12480 | /* 34905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12481 | /* 34909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12482 | /* 34913 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src |
| 12483 | /* 34913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12484 | /* 34916 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12485 | /* 34918 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12486 | /* 34920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12487 | /* 34925 */ // GIR_Coverage, 3130, |
| 12488 | /* 34925 */ GIR_EraseRootFromParent_Done, |
| 12489 | /* 34926 */ // Label 763: @34926 |
| 12490 | /* 34926 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(34958), // Rule ID 3131 // |
| 12491 | /* 34931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12492 | /* 34934 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12493 | /* 34937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12494 | /* 34941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12495 | /* 34945 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 12496 | /* 34945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12497 | /* 34948 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12498 | /* 34950 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12499 | /* 34952 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12500 | /* 34957 */ // GIR_Coverage, 3131, |
| 12501 | /* 34957 */ GIR_EraseRootFromParent_Done, |
| 12502 | /* 34958 */ // Label 764: @34958 |
| 12503 | /* 34958 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(34990), // Rule ID 3132 // |
| 12504 | /* 34963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12505 | /* 34966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12506 | /* 34969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12507 | /* 34973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12508 | /* 34977 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 12509 | /* 34977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12510 | /* 34980 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12511 | /* 34982 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12512 | /* 34984 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12513 | /* 34989 */ // GIR_Coverage, 3132, |
| 12514 | /* 34989 */ GIR_EraseRootFromParent_Done, |
| 12515 | /* 34990 */ // Label 765: @34990 |
| 12516 | /* 34990 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(35022), // Rule ID 3133 // |
| 12517 | /* 34995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12518 | /* 34998 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12519 | /* 35001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12520 | /* 35005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12521 | /* 35009 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 12522 | /* 35009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12523 | /* 35012 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12524 | /* 35014 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12525 | /* 35016 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12526 | /* 35021 */ // GIR_Coverage, 3133, |
| 12527 | /* 35021 */ GIR_EraseRootFromParent_Done, |
| 12528 | /* 35022 */ // Label 766: @35022 |
| 12529 | /* 35022 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(35054), // Rule ID 3134 // |
| 12530 | /* 35027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12531 | /* 35030 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12532 | /* 35033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12533 | /* 35037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12534 | /* 35041 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 12535 | /* 35041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12536 | /* 35044 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12537 | /* 35046 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12538 | /* 35048 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12539 | /* 35053 */ // GIR_Coverage, 3134, |
| 12540 | /* 35053 */ GIR_EraseRootFromParent_Done, |
| 12541 | /* 35054 */ // Label 767: @35054 |
| 12542 | /* 35054 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(35086), // Rule ID 3135 // |
| 12543 | /* 35059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12544 | /* 35062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12545 | /* 35065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12546 | /* 35069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12547 | /* 35073 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src |
| 12548 | /* 35073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12549 | /* 35076 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12550 | /* 35078 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12551 | /* 35080 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12552 | /* 35085 */ // GIR_Coverage, 3135, |
| 12553 | /* 35085 */ GIR_EraseRootFromParent_Done, |
| 12554 | /* 35086 */ // Label 768: @35086 |
| 12555 | /* 35086 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(35123), // Rule ID 3198 // |
| 12556 | /* 35091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12557 | /* 35094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12558 | /* 35097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12559 | /* 35101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12560 | /* 35105 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src) |
| 12561 | /* 35105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 12562 | /* 35108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12563 | /* 35110 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12564 | /* 35112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12565 | /* 35115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12566 | /* 35121 */ GIR_RootConstrainSelectedInstOperands, |
| 12567 | /* 35122 */ // GIR_Coverage, 3198, |
| 12568 | /* 35122 */ GIR_EraseRootFromParent_Done, |
| 12569 | /* 35123 */ // Label 769: @35123 |
| 12570 | /* 35123 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(35160), // Rule ID 3199 // |
| 12571 | /* 35128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12572 | /* 35131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12573 | /* 35134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12574 | /* 35138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12575 | /* 35142 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) |
| 12576 | /* 35142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 12577 | /* 35145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12578 | /* 35147 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12579 | /* 35149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12580 | /* 35152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12581 | /* 35158 */ GIR_RootConstrainSelectedInstOperands, |
| 12582 | /* 35159 */ // GIR_Coverage, 3199, |
| 12583 | /* 35159 */ GIR_EraseRootFromParent_Done, |
| 12584 | /* 35160 */ // Label 770: @35160 |
| 12585 | /* 35160 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(35197), // Rule ID 3200 // |
| 12586 | /* 35165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12587 | /* 35168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12588 | /* 35171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12589 | /* 35175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12590 | /* 35179 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) |
| 12591 | /* 35179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12592 | /* 35182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12593 | /* 35184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12594 | /* 35186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12595 | /* 35189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12596 | /* 35195 */ GIR_RootConstrainSelectedInstOperands, |
| 12597 | /* 35196 */ // GIR_Coverage, 3200, |
| 12598 | /* 35196 */ GIR_EraseRootFromParent_Done, |
| 12599 | /* 35197 */ // Label 771: @35197 |
| 12600 | /* 35197 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(35234), // Rule ID 3201 // |
| 12601 | /* 35202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12602 | /* 35205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12603 | /* 35208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12604 | /* 35212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12605 | /* 35216 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) |
| 12606 | /* 35216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12607 | /* 35219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12608 | /* 35221 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12609 | /* 35223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12610 | /* 35226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12611 | /* 35232 */ GIR_RootConstrainSelectedInstOperands, |
| 12612 | /* 35233 */ // GIR_Coverage, 3201, |
| 12613 | /* 35233 */ GIR_EraseRootFromParent_Done, |
| 12614 | /* 35234 */ // Label 772: @35234 |
| 12615 | /* 35234 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(35271), // Rule ID 3202 // |
| 12616 | /* 35239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12617 | /* 35242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12618 | /* 35245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12619 | /* 35249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12620 | /* 35253 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) |
| 12621 | /* 35253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 12622 | /* 35256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12623 | /* 35258 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12624 | /* 35260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12625 | /* 35263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12626 | /* 35269 */ GIR_RootConstrainSelectedInstOperands, |
| 12627 | /* 35270 */ // GIR_Coverage, 3202, |
| 12628 | /* 35270 */ GIR_EraseRootFromParent_Done, |
| 12629 | /* 35271 */ // Label 773: @35271 |
| 12630 | /* 35271 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(35308), // Rule ID 3203 // |
| 12631 | /* 35276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12632 | /* 35279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12633 | /* 35282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12634 | /* 35286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12635 | /* 35290 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src) |
| 12636 | /* 35290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 12637 | /* 35293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12638 | /* 35295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12639 | /* 35297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12640 | /* 35300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12641 | /* 35306 */ GIR_RootConstrainSelectedInstOperands, |
| 12642 | /* 35307 */ // GIR_Coverage, 3203, |
| 12643 | /* 35307 */ GIR_EraseRootFromParent_Done, |
| 12644 | /* 35308 */ // Label 774: @35308 |
| 12645 | /* 35308 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(35345), // Rule ID 3204 // |
| 12646 | /* 35313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12647 | /* 35316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12648 | /* 35319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12649 | /* 35323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12650 | /* 35327 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) |
| 12651 | /* 35327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 12652 | /* 35330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12653 | /* 35332 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12654 | /* 35334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12655 | /* 35337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12656 | /* 35343 */ GIR_RootConstrainSelectedInstOperands, |
| 12657 | /* 35344 */ // GIR_Coverage, 3204, |
| 12658 | /* 35344 */ GIR_EraseRootFromParent_Done, |
| 12659 | /* 35345 */ // Label 775: @35345 |
| 12660 | /* 35345 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(35382), // Rule ID 3205 // |
| 12661 | /* 35350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12662 | /* 35353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12663 | /* 35356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12664 | /* 35360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12665 | /* 35364 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) |
| 12666 | /* 35364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12667 | /* 35367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12668 | /* 35369 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12669 | /* 35371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12670 | /* 35374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12671 | /* 35380 */ GIR_RootConstrainSelectedInstOperands, |
| 12672 | /* 35381 */ // GIR_Coverage, 3205, |
| 12673 | /* 35381 */ GIR_EraseRootFromParent_Done, |
| 12674 | /* 35382 */ // Label 776: @35382 |
| 12675 | /* 35382 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(35419), // Rule ID 3206 // |
| 12676 | /* 35387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12677 | /* 35390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12678 | /* 35393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12679 | /* 35397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12680 | /* 35401 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) |
| 12681 | /* 35401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12682 | /* 35404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12683 | /* 35406 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12684 | /* 35408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12685 | /* 35411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12686 | /* 35417 */ GIR_RootConstrainSelectedInstOperands, |
| 12687 | /* 35418 */ // GIR_Coverage, 3206, |
| 12688 | /* 35418 */ GIR_EraseRootFromParent_Done, |
| 12689 | /* 35419 */ // Label 777: @35419 |
| 12690 | /* 35419 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(35456), // Rule ID 3207 // |
| 12691 | /* 35424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12692 | /* 35427 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12693 | /* 35430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12694 | /* 35434 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12695 | /* 35438 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) |
| 12696 | /* 35438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 12697 | /* 35441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12698 | /* 35443 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12699 | /* 35445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12700 | /* 35448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12701 | /* 35454 */ GIR_RootConstrainSelectedInstOperands, |
| 12702 | /* 35455 */ // GIR_Coverage, 3207, |
| 12703 | /* 35455 */ GIR_EraseRootFromParent_Done, |
| 12704 | /* 35456 */ // Label 778: @35456 |
| 12705 | /* 35456 */ GIM_Reject, |
| 12706 | /* 35457 */ // Label 660: @35457 |
| 12707 | /* 35457 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(35489), // Rule ID 3102 // |
| 12708 | /* 35462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12709 | /* 35465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12710 | /* 35468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12711 | /* 35472 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12712 | /* 35476 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12713 | /* 35476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12714 | /* 35479 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12715 | /* 35481 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12716 | /* 35483 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12717 | /* 35488 */ // GIR_Coverage, 3102, |
| 12718 | /* 35488 */ GIR_EraseRootFromParent_Done, |
| 12719 | /* 35489 */ // Label 779: @35489 |
| 12720 | /* 35489 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(35521), // Rule ID 3103 // |
| 12721 | /* 35494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12722 | /* 35497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12723 | /* 35500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12724 | /* 35504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12725 | /* 35508 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12726 | /* 35508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12727 | /* 35511 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12728 | /* 35513 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12729 | /* 35515 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12730 | /* 35520 */ // GIR_Coverage, 3103, |
| 12731 | /* 35520 */ GIR_EraseRootFromParent_Done, |
| 12732 | /* 35521 */ // Label 780: @35521 |
| 12733 | /* 35521 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(35553), // Rule ID 3152 // |
| 12734 | /* 35526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12735 | /* 35529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12736 | /* 35532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12737 | /* 35536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12738 | /* 35540 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12739 | /* 35540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12740 | /* 35543 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12741 | /* 35545 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12742 | /* 35547 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12743 | /* 35552 */ // GIR_Coverage, 3152, |
| 12744 | /* 35552 */ GIR_EraseRootFromParent_Done, |
| 12745 | /* 35553 */ // Label 781: @35553 |
| 12746 | /* 35553 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(35585), // Rule ID 3153 // |
| 12747 | /* 35558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12748 | /* 35561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12749 | /* 35564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12750 | /* 35568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12751 | /* 35572 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12752 | /* 35572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12753 | /* 35575 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12754 | /* 35577 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12755 | /* 35579 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12756 | /* 35584 */ // GIR_Coverage, 3153, |
| 12757 | /* 35584 */ GIR_EraseRootFromParent_Done, |
| 12758 | /* 35585 */ // Label 782: @35585 |
| 12759 | /* 35585 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(35617), // Rule ID 3154 // |
| 12760 | /* 35590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12761 | /* 35593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12762 | /* 35596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12763 | /* 35600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12764 | /* 35604 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12765 | /* 35604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12766 | /* 35607 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12767 | /* 35609 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12768 | /* 35611 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12769 | /* 35616 */ // GIR_Coverage, 3154, |
| 12770 | /* 35616 */ GIR_EraseRootFromParent_Done, |
| 12771 | /* 35617 */ // Label 783: @35617 |
| 12772 | /* 35617 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(35649), // Rule ID 3155 // |
| 12773 | /* 35622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12774 | /* 35625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12775 | /* 35628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12776 | /* 35632 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12777 | /* 35636 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12778 | /* 35636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12779 | /* 35639 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12780 | /* 35641 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12781 | /* 35643 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12782 | /* 35648 */ // GIR_Coverage, 3155, |
| 12783 | /* 35648 */ GIR_EraseRootFromParent_Done, |
| 12784 | /* 35649 */ // Label 784: @35649 |
| 12785 | /* 35649 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(35681), // Rule ID 3156 // |
| 12786 | /* 35654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12787 | /* 35657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12788 | /* 35660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12789 | /* 35664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12790 | /* 35668 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12791 | /* 35668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12792 | /* 35671 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12793 | /* 35673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12794 | /* 35675 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12795 | /* 35680 */ // GIR_Coverage, 3156, |
| 12796 | /* 35680 */ GIR_EraseRootFromParent_Done, |
| 12797 | /* 35681 */ // Label 785: @35681 |
| 12798 | /* 35681 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(35713), // Rule ID 3157 // |
| 12799 | /* 35686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12800 | /* 35689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12801 | /* 35692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12802 | /* 35696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12803 | /* 35700 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12804 | /* 35700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12805 | /* 35703 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12806 | /* 35705 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12807 | /* 35707 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12808 | /* 35712 */ // GIR_Coverage, 3157, |
| 12809 | /* 35712 */ GIR_EraseRootFromParent_Done, |
| 12810 | /* 35713 */ // Label 786: @35713 |
| 12811 | /* 35713 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(35745), // Rule ID 3158 // |
| 12812 | /* 35718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12813 | /* 35721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12814 | /* 35724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12815 | /* 35728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12816 | /* 35732 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12817 | /* 35732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12818 | /* 35735 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12819 | /* 35737 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12820 | /* 35739 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12821 | /* 35744 */ // GIR_Coverage, 3158, |
| 12822 | /* 35744 */ GIR_EraseRootFromParent_Done, |
| 12823 | /* 35745 */ // Label 787: @35745 |
| 12824 | /* 35745 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(35777), // Rule ID 3159 // |
| 12825 | /* 35750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12826 | /* 35753 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12827 | /* 35756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12828 | /* 35760 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12829 | /* 35764 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12830 | /* 35764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12831 | /* 35767 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12832 | /* 35769 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12833 | /* 35771 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12834 | /* 35776 */ // GIR_Coverage, 3159, |
| 12835 | /* 35776 */ GIR_EraseRootFromParent_Done, |
| 12836 | /* 35777 */ // Label 788: @35777 |
| 12837 | /* 35777 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(35809), // Rule ID 3160 // |
| 12838 | /* 35782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12839 | /* 35785 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12840 | /* 35788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12841 | /* 35792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12842 | /* 35796 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12843 | /* 35796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12844 | /* 35799 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12845 | /* 35801 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12846 | /* 35803 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12847 | /* 35808 */ // GIR_Coverage, 3160, |
| 12848 | /* 35808 */ GIR_EraseRootFromParent_Done, |
| 12849 | /* 35809 */ // Label 789: @35809 |
| 12850 | /* 35809 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(35841), // Rule ID 3161 // |
| 12851 | /* 35814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12852 | /* 35817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12853 | /* 35820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12854 | /* 35824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12855 | /* 35828 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12856 | /* 35828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12857 | /* 35831 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12858 | /* 35833 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12859 | /* 35835 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12860 | /* 35840 */ // GIR_Coverage, 3161, |
| 12861 | /* 35840 */ GIR_EraseRootFromParent_Done, |
| 12862 | /* 35841 */ // Label 790: @35841 |
| 12863 | /* 35841 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(35878), // Rule ID 3224 // |
| 12864 | /* 35846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12865 | /* 35849 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12866 | /* 35852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12867 | /* 35856 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12868 | /* 35860 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) |
| 12869 | /* 35860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12870 | /* 35863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12871 | /* 35865 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12872 | /* 35867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12873 | /* 35870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12874 | /* 35876 */ GIR_RootConstrainSelectedInstOperands, |
| 12875 | /* 35877 */ // GIR_Coverage, 3224, |
| 12876 | /* 35877 */ GIR_EraseRootFromParent_Done, |
| 12877 | /* 35878 */ // Label 791: @35878 |
| 12878 | /* 35878 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(35915), // Rule ID 3225 // |
| 12879 | /* 35883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12880 | /* 35886 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12881 | /* 35889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12882 | /* 35893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12883 | /* 35897 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) |
| 12884 | /* 35897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12885 | /* 35900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12886 | /* 35902 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12887 | /* 35904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12888 | /* 35907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12889 | /* 35913 */ GIR_RootConstrainSelectedInstOperands, |
| 12890 | /* 35914 */ // GIR_Coverage, 3225, |
| 12891 | /* 35914 */ GIR_EraseRootFromParent_Done, |
| 12892 | /* 35915 */ // Label 792: @35915 |
| 12893 | /* 35915 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(35952), // Rule ID 3226 // |
| 12894 | /* 35920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12895 | /* 35923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12896 | /* 35926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12897 | /* 35930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12898 | /* 35934 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) |
| 12899 | /* 35934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12900 | /* 35937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12901 | /* 35939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12902 | /* 35941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12903 | /* 35944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12904 | /* 35950 */ GIR_RootConstrainSelectedInstOperands, |
| 12905 | /* 35951 */ // GIR_Coverage, 3226, |
| 12906 | /* 35951 */ GIR_EraseRootFromParent_Done, |
| 12907 | /* 35952 */ // Label 793: @35952 |
| 12908 | /* 35952 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(35989), // Rule ID 3227 // |
| 12909 | /* 35957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12910 | /* 35960 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12911 | /* 35963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12912 | /* 35967 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12913 | /* 35971 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) |
| 12914 | /* 35971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12915 | /* 35974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12916 | /* 35976 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12917 | /* 35978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12918 | /* 35981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12919 | /* 35987 */ GIR_RootConstrainSelectedInstOperands, |
| 12920 | /* 35988 */ // GIR_Coverage, 3227, |
| 12921 | /* 35988 */ GIR_EraseRootFromParent_Done, |
| 12922 | /* 35989 */ // Label 794: @35989 |
| 12923 | /* 35989 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(36026), // Rule ID 3228 // |
| 12924 | /* 35994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12925 | /* 35997 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12926 | /* 36000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12927 | /* 36004 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12928 | /* 36008 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) |
| 12929 | /* 36008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 12930 | /* 36011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12931 | /* 36013 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12932 | /* 36015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12933 | /* 36018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12934 | /* 36024 */ GIR_RootConstrainSelectedInstOperands, |
| 12935 | /* 36025 */ // GIR_Coverage, 3228, |
| 12936 | /* 36025 */ GIR_EraseRootFromParent_Done, |
| 12937 | /* 36026 */ // Label 795: @36026 |
| 12938 | /* 36026 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(36063), // Rule ID 3229 // |
| 12939 | /* 36031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12940 | /* 36034 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12941 | /* 36037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12942 | /* 36041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12943 | /* 36045 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) |
| 12944 | /* 36045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12945 | /* 36048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12946 | /* 36050 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12947 | /* 36052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12948 | /* 36055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12949 | /* 36061 */ GIR_RootConstrainSelectedInstOperands, |
| 12950 | /* 36062 */ // GIR_Coverage, 3229, |
| 12951 | /* 36062 */ GIR_EraseRootFromParent_Done, |
| 12952 | /* 36063 */ // Label 796: @36063 |
| 12953 | /* 36063 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(36100), // Rule ID 3230 // |
| 12954 | /* 36068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12955 | /* 36071 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12956 | /* 36074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12957 | /* 36078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12958 | /* 36082 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) |
| 12959 | /* 36082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12960 | /* 36085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12961 | /* 36087 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12962 | /* 36089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12963 | /* 36092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12964 | /* 36098 */ GIR_RootConstrainSelectedInstOperands, |
| 12965 | /* 36099 */ // GIR_Coverage, 3230, |
| 12966 | /* 36099 */ GIR_EraseRootFromParent_Done, |
| 12967 | /* 36100 */ // Label 797: @36100 |
| 12968 | /* 36100 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(36137), // Rule ID 3231 // |
| 12969 | /* 36105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12970 | /* 36108 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12971 | /* 36111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12972 | /* 36115 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12973 | /* 36119 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) |
| 12974 | /* 36119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12975 | /* 36122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12976 | /* 36124 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12977 | /* 36126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12978 | /* 36129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12979 | /* 36135 */ GIR_RootConstrainSelectedInstOperands, |
| 12980 | /* 36136 */ // GIR_Coverage, 3231, |
| 12981 | /* 36136 */ GIR_EraseRootFromParent_Done, |
| 12982 | /* 36137 */ // Label 798: @36137 |
| 12983 | /* 36137 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(36174), // Rule ID 3232 // |
| 12984 | /* 36142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12985 | /* 36145 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12986 | /* 36148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12987 | /* 36152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12988 | /* 36156 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) |
| 12989 | /* 36156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12990 | /* 36159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12991 | /* 36161 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12992 | /* 36163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12993 | /* 36166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12994 | /* 36172 */ GIR_RootConstrainSelectedInstOperands, |
| 12995 | /* 36173 */ // GIR_Coverage, 3232, |
| 12996 | /* 36173 */ GIR_EraseRootFromParent_Done, |
| 12997 | /* 36174 */ // Label 799: @36174 |
| 12998 | /* 36174 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(36211), // Rule ID 3233 // |
| 12999 | /* 36179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13000 | /* 36182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13001 | /* 36185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13002 | /* 36189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13003 | /* 36193 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) |
| 13004 | /* 36193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 13005 | /* 36196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13006 | /* 36198 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13007 | /* 36200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13008 | /* 36203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13009 | /* 36209 */ GIR_RootConstrainSelectedInstOperands, |
| 13010 | /* 36210 */ // GIR_Coverage, 3233, |
| 13011 | /* 36210 */ GIR_EraseRootFromParent_Done, |
| 13012 | /* 36211 */ // Label 800: @36211 |
| 13013 | /* 36211 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(36243), // Rule ID 5799 // |
| 13014 | /* 36216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 13015 | /* 36219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13016 | /* 36222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13017 | /* 36226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13018 | /* 36230 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13019 | /* 36230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13020 | /* 36233 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13021 | /* 36235 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13022 | /* 36237 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13023 | /* 36242 */ // GIR_Coverage, 5799, |
| 13024 | /* 36242 */ GIR_EraseRootFromParent_Done, |
| 13025 | /* 36243 */ // Label 801: @36243 |
| 13026 | /* 36243 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(36275), // Rule ID 5800 // |
| 13027 | /* 36248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 13028 | /* 36251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13029 | /* 36254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13030 | /* 36258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13031 | /* 36262 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13032 | /* 36262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13033 | /* 36265 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13034 | /* 36267 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13035 | /* 36269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13036 | /* 36274 */ // GIR_Coverage, 5800, |
| 13037 | /* 36274 */ GIR_EraseRootFromParent_Done, |
| 13038 | /* 36275 */ // Label 802: @36275 |
| 13039 | /* 36275 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(36307), // Rule ID 5813 // |
| 13040 | /* 36280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13041 | /* 36283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13042 | /* 36286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13043 | /* 36290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13044 | /* 36294 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13045 | /* 36294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13046 | /* 36297 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13047 | /* 36299 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13048 | /* 36301 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13049 | /* 36306 */ // GIR_Coverage, 5813, |
| 13050 | /* 36306 */ GIR_EraseRootFromParent_Done, |
| 13051 | /* 36307 */ // Label 803: @36307 |
| 13052 | /* 36307 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(36339), // Rule ID 5814 // |
| 13053 | /* 36312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13054 | /* 36315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13055 | /* 36318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13056 | /* 36322 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13057 | /* 36326 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13058 | /* 36326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13059 | /* 36329 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13060 | /* 36331 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13061 | /* 36333 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13062 | /* 36338 */ // GIR_Coverage, 5814, |
| 13063 | /* 36338 */ GIR_EraseRootFromParent_Done, |
| 13064 | /* 36339 */ // Label 804: @36339 |
| 13065 | /* 36339 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(36371), // Rule ID 5815 // |
| 13066 | /* 36344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13067 | /* 36347 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13068 | /* 36350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13069 | /* 36354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13070 | /* 36358 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13071 | /* 36358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13072 | /* 36361 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13073 | /* 36363 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13074 | /* 36365 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13075 | /* 36370 */ // GIR_Coverage, 5815, |
| 13076 | /* 36370 */ GIR_EraseRootFromParent_Done, |
| 13077 | /* 36371 */ // Label 805: @36371 |
| 13078 | /* 36371 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(36403), // Rule ID 5816 // |
| 13079 | /* 36376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13080 | /* 36379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13081 | /* 36382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13082 | /* 36386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13083 | /* 36390 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13084 | /* 36390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13085 | /* 36393 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13086 | /* 36395 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13087 | /* 36397 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13088 | /* 36402 */ // GIR_Coverage, 5816, |
| 13089 | /* 36402 */ GIR_EraseRootFromParent_Done, |
| 13090 | /* 36403 */ // Label 806: @36403 |
| 13091 | /* 36403 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(36435), // Rule ID 5817 // |
| 13092 | /* 36408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13093 | /* 36411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13094 | /* 36414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13095 | /* 36418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13096 | /* 36422 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13097 | /* 36422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13098 | /* 36425 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13099 | /* 36427 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13100 | /* 36429 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13101 | /* 36434 */ // GIR_Coverage, 5817, |
| 13102 | /* 36434 */ GIR_EraseRootFromParent_Done, |
| 13103 | /* 36435 */ // Label 807: @36435 |
| 13104 | /* 36435 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(36467), // Rule ID 5818 // |
| 13105 | /* 36440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13106 | /* 36443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13107 | /* 36446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13108 | /* 36450 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13109 | /* 36454 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13110 | /* 36454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13111 | /* 36457 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13112 | /* 36459 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13113 | /* 36461 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13114 | /* 36466 */ // GIR_Coverage, 5818, |
| 13115 | /* 36466 */ GIR_EraseRootFromParent_Done, |
| 13116 | /* 36467 */ // Label 808: @36467 |
| 13117 | /* 36467 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(36499), // Rule ID 5819 // |
| 13118 | /* 36472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13119 | /* 36475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13120 | /* 36478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13121 | /* 36482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13122 | /* 36486 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13123 | /* 36486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13124 | /* 36489 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13125 | /* 36491 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13126 | /* 36493 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13127 | /* 36498 */ // GIR_Coverage, 5819, |
| 13128 | /* 36498 */ GIR_EraseRootFromParent_Done, |
| 13129 | /* 36499 */ // Label 809: @36499 |
| 13130 | /* 36499 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(36531), // Rule ID 5820 // |
| 13131 | /* 36504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13132 | /* 36507 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13133 | /* 36510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13134 | /* 36514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13135 | /* 36518 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13136 | /* 36518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13137 | /* 36521 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13138 | /* 36523 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13139 | /* 36525 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13140 | /* 36530 */ // GIR_Coverage, 5820, |
| 13141 | /* 36530 */ GIR_EraseRootFromParent_Done, |
| 13142 | /* 36531 */ // Label 810: @36531 |
| 13143 | /* 36531 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(36563), // Rule ID 5821 // |
| 13144 | /* 36536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13145 | /* 36539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13146 | /* 36542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13147 | /* 36546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13148 | /* 36550 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13149 | /* 36550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13150 | /* 36553 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13151 | /* 36555 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13152 | /* 36557 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13153 | /* 36562 */ // GIR_Coverage, 5821, |
| 13154 | /* 36562 */ GIR_EraseRootFromParent_Done, |
| 13155 | /* 36563 */ // Label 811: @36563 |
| 13156 | /* 36563 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(36595), // Rule ID 5822 // |
| 13157 | /* 36568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13158 | /* 36571 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13159 | /* 36574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13160 | /* 36578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13161 | /* 36582 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13162 | /* 36582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13163 | /* 36585 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13164 | /* 36587 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13165 | /* 36589 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13166 | /* 36594 */ // GIR_Coverage, 5822, |
| 13167 | /* 36594 */ GIR_EraseRootFromParent_Done, |
| 13168 | /* 36595 */ // Label 812: @36595 |
| 13169 | /* 36595 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(36653), // Rule ID 5849 // |
| 13170 | /* 36600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13171 | /* 36603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13172 | /* 36606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13173 | /* 36610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13174 | /* 36614 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) |
| 13175 | /* 36614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13176 | /* 36617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13177 | /* 36621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13178 | /* 36626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13179 | /* 36629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13180 | /* 36631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13181 | /* 36633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13182 | /* 36636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13183 | /* 36642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13184 | /* 36648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13185 | /* 36651 */ GIR_RootConstrainSelectedInstOperands, |
| 13186 | /* 36652 */ // GIR_Coverage, 5849, |
| 13187 | /* 36652 */ GIR_EraseRootFromParent_Done, |
| 13188 | /* 36653 */ // Label 813: @36653 |
| 13189 | /* 36653 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(36711), // Rule ID 5850 // |
| 13190 | /* 36658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13191 | /* 36661 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13192 | /* 36664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13193 | /* 36668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13194 | /* 36672 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) |
| 13195 | /* 36672 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13196 | /* 36675 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13197 | /* 36679 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13198 | /* 36684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13199 | /* 36687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13200 | /* 36689 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13201 | /* 36691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13202 | /* 36694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13203 | /* 36700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13204 | /* 36706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13205 | /* 36709 */ GIR_RootConstrainSelectedInstOperands, |
| 13206 | /* 36710 */ // GIR_Coverage, 5850, |
| 13207 | /* 36710 */ GIR_EraseRootFromParent_Done, |
| 13208 | /* 36711 */ // Label 814: @36711 |
| 13209 | /* 36711 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(36769), // Rule ID 5851 // |
| 13210 | /* 36716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13211 | /* 36719 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13212 | /* 36722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13213 | /* 36726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13214 | /* 36730 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) |
| 13215 | /* 36730 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13216 | /* 36733 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13217 | /* 36737 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13218 | /* 36742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 13219 | /* 36745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13220 | /* 36747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13221 | /* 36749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13222 | /* 36752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13223 | /* 36758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13224 | /* 36764 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13225 | /* 36767 */ GIR_RootConstrainSelectedInstOperands, |
| 13226 | /* 36768 */ // GIR_Coverage, 5851, |
| 13227 | /* 36768 */ GIR_EraseRootFromParent_Done, |
| 13228 | /* 36769 */ // Label 815: @36769 |
| 13229 | /* 36769 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(36827), // Rule ID 5852 // |
| 13230 | /* 36774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13231 | /* 36777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13232 | /* 36780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13233 | /* 36784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13234 | /* 36788 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) |
| 13235 | /* 36788 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13236 | /* 36791 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13237 | /* 36795 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13238 | /* 36800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 13239 | /* 36803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13240 | /* 36805 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13241 | /* 36807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13242 | /* 36810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13243 | /* 36816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13244 | /* 36822 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13245 | /* 36825 */ GIR_RootConstrainSelectedInstOperands, |
| 13246 | /* 36826 */ // GIR_Coverage, 5852, |
| 13247 | /* 36826 */ GIR_EraseRootFromParent_Done, |
| 13248 | /* 36827 */ // Label 816: @36827 |
| 13249 | /* 36827 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(36885), // Rule ID 5853 // |
| 13250 | /* 36832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13251 | /* 36835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13252 | /* 36838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13253 | /* 36842 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13254 | /* 36846 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) |
| 13255 | /* 36846 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13256 | /* 36849 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13257 | /* 36853 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13258 | /* 36858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 13259 | /* 36861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13260 | /* 36863 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13261 | /* 36865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13262 | /* 36868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13263 | /* 36874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13264 | /* 36880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13265 | /* 36883 */ GIR_RootConstrainSelectedInstOperands, |
| 13266 | /* 36884 */ // GIR_Coverage, 5853, |
| 13267 | /* 36884 */ GIR_EraseRootFromParent_Done, |
| 13268 | /* 36885 */ // Label 817: @36885 |
| 13269 | /* 36885 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(36943), // Rule ID 5854 // |
| 13270 | /* 36890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13271 | /* 36893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13272 | /* 36896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13273 | /* 36900 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13274 | /* 36904 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) |
| 13275 | /* 36904 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13276 | /* 36907 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13277 | /* 36911 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13278 | /* 36916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13279 | /* 36919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13280 | /* 36921 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13281 | /* 36923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13282 | /* 36926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13283 | /* 36932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13284 | /* 36938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13285 | /* 36941 */ GIR_RootConstrainSelectedInstOperands, |
| 13286 | /* 36942 */ // GIR_Coverage, 5854, |
| 13287 | /* 36942 */ GIR_EraseRootFromParent_Done, |
| 13288 | /* 36943 */ // Label 818: @36943 |
| 13289 | /* 36943 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(37001), // Rule ID 5855 // |
| 13290 | /* 36948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13291 | /* 36951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13292 | /* 36954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13293 | /* 36958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13294 | /* 36962 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) |
| 13295 | /* 36962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13296 | /* 36965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13297 | /* 36969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13298 | /* 36974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13299 | /* 36977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13300 | /* 36979 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13301 | /* 36981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13302 | /* 36984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13303 | /* 36990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13304 | /* 36996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13305 | /* 36999 */ GIR_RootConstrainSelectedInstOperands, |
| 13306 | /* 37000 */ // GIR_Coverage, 5855, |
| 13307 | /* 37000 */ GIR_EraseRootFromParent_Done, |
| 13308 | /* 37001 */ // Label 819: @37001 |
| 13309 | /* 37001 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(37059), // Rule ID 5856 // |
| 13310 | /* 37006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13311 | /* 37009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13312 | /* 37012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13313 | /* 37016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13314 | /* 37020 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) |
| 13315 | /* 37020 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13316 | /* 37023 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13317 | /* 37027 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13318 | /* 37032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 13319 | /* 37035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13320 | /* 37037 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13321 | /* 37039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13322 | /* 37042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13323 | /* 37048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13324 | /* 37054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13325 | /* 37057 */ GIR_RootConstrainSelectedInstOperands, |
| 13326 | /* 37058 */ // GIR_Coverage, 5856, |
| 13327 | /* 37058 */ GIR_EraseRootFromParent_Done, |
| 13328 | /* 37059 */ // Label 820: @37059 |
| 13329 | /* 37059 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(37117), // Rule ID 5857 // |
| 13330 | /* 37064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13331 | /* 37067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13332 | /* 37070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13333 | /* 37074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13334 | /* 37078 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 13335 | /* 37078 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13336 | /* 37081 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13337 | /* 37085 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13338 | /* 37090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 13339 | /* 37093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13340 | /* 37095 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13341 | /* 37097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13342 | /* 37100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13343 | /* 37106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13344 | /* 37112 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13345 | /* 37115 */ GIR_RootConstrainSelectedInstOperands, |
| 13346 | /* 37116 */ // GIR_Coverage, 5857, |
| 13347 | /* 37116 */ GIR_EraseRootFromParent_Done, |
| 13348 | /* 37117 */ // Label 821: @37117 |
| 13349 | /* 37117 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(37175), // Rule ID 5858 // |
| 13350 | /* 37122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 13351 | /* 37125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13352 | /* 37128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13353 | /* 37132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13354 | /* 37136 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) |
| 13355 | /* 37136 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13356 | /* 37139 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13357 | /* 37143 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13358 | /* 37148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 13359 | /* 37151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13360 | /* 37153 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13361 | /* 37155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13362 | /* 37158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13363 | /* 37164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13364 | /* 37170 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13365 | /* 37173 */ GIR_RootConstrainSelectedInstOperands, |
| 13366 | /* 37174 */ // GIR_Coverage, 5858, |
| 13367 | /* 37174 */ GIR_EraseRootFromParent_Done, |
| 13368 | /* 37175 */ // Label 822: @37175 |
| 13369 | /* 37175 */ GIM_Reject, |
| 13370 | /* 37176 */ // Label 661: @37176 |
| 13371 | /* 37176 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(37208), // Rule ID 3136 // |
| 13372 | /* 37181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13373 | /* 37184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13374 | /* 37187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13375 | /* 37191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13376 | /* 37195 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 13377 | /* 37195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13378 | /* 37198 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13379 | /* 37200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13380 | /* 37202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 13381 | /* 37207 */ // GIR_Coverage, 3136, |
| 13382 | /* 37207 */ GIR_EraseRootFromParent_Done, |
| 13383 | /* 37208 */ // Label 823: @37208 |
| 13384 | /* 37208 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(37240), // Rule ID 3137 // |
| 13385 | /* 37213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13386 | /* 37216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13387 | /* 37219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13388 | /* 37223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13389 | /* 37227 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 13390 | /* 37227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13391 | /* 37230 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13392 | /* 37232 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13393 | /* 37234 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 13394 | /* 37239 */ // GIR_Coverage, 3137, |
| 13395 | /* 37239 */ GIR_EraseRootFromParent_Done, |
| 13396 | /* 37240 */ // Label 824: @37240 |
| 13397 | /* 37240 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(37272), // Rule ID 3138 // |
| 13398 | /* 37245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13399 | /* 37248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13400 | /* 37251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13401 | /* 37255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13402 | /* 37259 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 13403 | /* 37259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13404 | /* 37262 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13405 | /* 37264 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13406 | /* 37266 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 13407 | /* 37271 */ // GIR_Coverage, 3138, |
| 13408 | /* 37271 */ GIR_EraseRootFromParent_Done, |
| 13409 | /* 37272 */ // Label 825: @37272 |
| 13410 | /* 37272 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(37304), // Rule ID 3139 // |
| 13411 | /* 37277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13412 | /* 37280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13413 | /* 37283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13414 | /* 37287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13415 | /* 37291 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 13416 | /* 37291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13417 | /* 37294 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13418 | /* 37296 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13419 | /* 37298 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 13420 | /* 37303 */ // GIR_Coverage, 3139, |
| 13421 | /* 37303 */ GIR_EraseRootFromParent_Done, |
| 13422 | /* 37304 */ // Label 826: @37304 |
| 13423 | /* 37304 */ GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(37336), // Rule ID 3140 // |
| 13424 | /* 37309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13425 | /* 37312 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13426 | /* 37315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13427 | /* 37319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13428 | /* 37323 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 13429 | /* 37323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13430 | /* 37326 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13431 | /* 37328 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13432 | /* 37330 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 13433 | /* 37335 */ // GIR_Coverage, 3140, |
| 13434 | /* 37335 */ GIR_EraseRootFromParent_Done, |
| 13435 | /* 37336 */ // Label 827: @37336 |
| 13436 | /* 37336 */ GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(37368), // Rule ID 3141 // |
| 13437 | /* 37341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13438 | /* 37344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13439 | /* 37347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13440 | /* 37351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13441 | /* 37355 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 13442 | /* 37355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13443 | /* 37358 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13444 | /* 37360 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13445 | /* 37362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 13446 | /* 37367 */ // GIR_Coverage, 3141, |
| 13447 | /* 37367 */ GIR_EraseRootFromParent_Done, |
| 13448 | /* 37368 */ // Label 828: @37368 |
| 13449 | /* 37368 */ GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(37405), // Rule ID 3208 // |
| 13450 | /* 37373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13451 | /* 37376 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13452 | /* 37379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13453 | /* 37383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13454 | /* 37387 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src) |
| 13455 | /* 37387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 13456 | /* 37390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13457 | /* 37392 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13458 | /* 37394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13459 | /* 37397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13460 | /* 37403 */ GIR_RootConstrainSelectedInstOperands, |
| 13461 | /* 37404 */ // GIR_Coverage, 3208, |
| 13462 | /* 37404 */ GIR_EraseRootFromParent_Done, |
| 13463 | /* 37405 */ // Label 829: @37405 |
| 13464 | /* 37405 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(37442), // Rule ID 3209 // |
| 13465 | /* 37410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13466 | /* 37413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13467 | /* 37416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13468 | /* 37420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13469 | /* 37424 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) |
| 13470 | /* 37424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 13471 | /* 37427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13472 | /* 37429 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13473 | /* 37431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13474 | /* 37434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13475 | /* 37440 */ GIR_RootConstrainSelectedInstOperands, |
| 13476 | /* 37441 */ // GIR_Coverage, 3209, |
| 13477 | /* 37441 */ GIR_EraseRootFromParent_Done, |
| 13478 | /* 37442 */ // Label 830: @37442 |
| 13479 | /* 37442 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(37479), // Rule ID 3210 // |
| 13480 | /* 37447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13481 | /* 37450 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13482 | /* 37453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13483 | /* 37457 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13484 | /* 37461 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) |
| 13485 | /* 37461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 13486 | /* 37464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13487 | /* 37466 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13488 | /* 37468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13489 | /* 37471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13490 | /* 37477 */ GIR_RootConstrainSelectedInstOperands, |
| 13491 | /* 37478 */ // GIR_Coverage, 3210, |
| 13492 | /* 37478 */ GIR_EraseRootFromParent_Done, |
| 13493 | /* 37479 */ // Label 831: @37479 |
| 13494 | /* 37479 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(37516), // Rule ID 3211 // |
| 13495 | /* 37484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13496 | /* 37487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13497 | /* 37490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13498 | /* 37494 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13499 | /* 37498 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) |
| 13500 | /* 37498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 13501 | /* 37501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13502 | /* 37503 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13503 | /* 37505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13504 | /* 37508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13505 | /* 37514 */ GIR_RootConstrainSelectedInstOperands, |
| 13506 | /* 37515 */ // GIR_Coverage, 3211, |
| 13507 | /* 37515 */ GIR_EraseRootFromParent_Done, |
| 13508 | /* 37516 */ // Label 832: @37516 |
| 13509 | /* 37516 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(37553), // Rule ID 3212 // |
| 13510 | /* 37521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13511 | /* 37524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13512 | /* 37527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13513 | /* 37531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13514 | /* 37535 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) |
| 13515 | /* 37535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 13516 | /* 37538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13517 | /* 37540 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13518 | /* 37542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13519 | /* 37545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13520 | /* 37551 */ GIR_RootConstrainSelectedInstOperands, |
| 13521 | /* 37552 */ // GIR_Coverage, 3212, |
| 13522 | /* 37552 */ GIR_EraseRootFromParent_Done, |
| 13523 | /* 37553 */ // Label 833: @37553 |
| 13524 | /* 37553 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(37590), // Rule ID 3213 // |
| 13525 | /* 37558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13526 | /* 37561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13527 | /* 37564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13528 | /* 37568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13529 | /* 37572 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) |
| 13530 | /* 37572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 13531 | /* 37575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13532 | /* 37577 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13533 | /* 37579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13534 | /* 37582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13535 | /* 37588 */ GIR_RootConstrainSelectedInstOperands, |
| 13536 | /* 37589 */ // GIR_Coverage, 3213, |
| 13537 | /* 37589 */ GIR_EraseRootFromParent_Done, |
| 13538 | /* 37590 */ // Label 834: @37590 |
| 13539 | /* 37590 */ GIM_Reject, |
| 13540 | /* 37591 */ // Label 662: @37591 |
| 13541 | /* 37591 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(37623), // Rule ID 3104 // |
| 13542 | /* 37596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13543 | /* 37599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13544 | /* 37602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13545 | /* 37606 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13546 | /* 37610 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src |
| 13547 | /* 37610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13548 | /* 37613 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13549 | /* 37615 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13550 | /* 37617 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13551 | /* 37622 */ // GIR_Coverage, 3104, |
| 13552 | /* 37622 */ GIR_EraseRootFromParent_Done, |
| 13553 | /* 37623 */ // Label 835: @37623 |
| 13554 | /* 37623 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(37655), // Rule ID 3105 // |
| 13555 | /* 37628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13556 | /* 37631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13557 | /* 37634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13558 | /* 37638 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13559 | /* 37642 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src |
| 13560 | /* 37642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13561 | /* 37645 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13562 | /* 37647 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13563 | /* 37649 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13564 | /* 37654 */ // GIR_Coverage, 3105, |
| 13565 | /* 37654 */ GIR_EraseRootFromParent_Done, |
| 13566 | /* 37655 */ // Label 836: @37655 |
| 13567 | /* 37655 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(37687), // Rule ID 3162 // |
| 13568 | /* 37660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13569 | /* 37663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13570 | /* 37666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13571 | /* 37670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13572 | /* 37674 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 13573 | /* 37674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13574 | /* 37677 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13575 | /* 37679 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13576 | /* 37681 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13577 | /* 37686 */ // GIR_Coverage, 3162, |
| 13578 | /* 37686 */ GIR_EraseRootFromParent_Done, |
| 13579 | /* 37687 */ // Label 837: @37687 |
| 13580 | /* 37687 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(37719), // Rule ID 3163 // |
| 13581 | /* 37692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13582 | /* 37695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13583 | /* 37698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13584 | /* 37702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13585 | /* 37706 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 13586 | /* 37706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13587 | /* 37709 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13588 | /* 37711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13589 | /* 37713 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13590 | /* 37718 */ // GIR_Coverage, 3163, |
| 13591 | /* 37718 */ GIR_EraseRootFromParent_Done, |
| 13592 | /* 37719 */ // Label 838: @37719 |
| 13593 | /* 37719 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(37751), // Rule ID 3164 // |
| 13594 | /* 37724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13595 | /* 37727 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13596 | /* 37730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13597 | /* 37734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13598 | /* 37738 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 13599 | /* 37738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13600 | /* 37741 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13601 | /* 37743 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13602 | /* 37745 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13603 | /* 37750 */ // GIR_Coverage, 3164, |
| 13604 | /* 37750 */ GIR_EraseRootFromParent_Done, |
| 13605 | /* 37751 */ // Label 839: @37751 |
| 13606 | /* 37751 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(37783), // Rule ID 3165 // |
| 13607 | /* 37756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13608 | /* 37759 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13609 | /* 37762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13610 | /* 37766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13611 | /* 37770 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 13612 | /* 37770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13613 | /* 37773 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13614 | /* 37775 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13615 | /* 37777 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13616 | /* 37782 */ // GIR_Coverage, 3165, |
| 13617 | /* 37782 */ GIR_EraseRootFromParent_Done, |
| 13618 | /* 37783 */ // Label 840: @37783 |
| 13619 | /* 37783 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(37815), // Rule ID 3166 // |
| 13620 | /* 37788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13621 | /* 37791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13622 | /* 37794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13623 | /* 37798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13624 | /* 37802 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src |
| 13625 | /* 37802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13626 | /* 37805 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13627 | /* 37807 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13628 | /* 37809 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13629 | /* 37814 */ // GIR_Coverage, 3166, |
| 13630 | /* 37814 */ GIR_EraseRootFromParent_Done, |
| 13631 | /* 37815 */ // Label 841: @37815 |
| 13632 | /* 37815 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(37847), // Rule ID 3167 // |
| 13633 | /* 37820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13634 | /* 37823 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13635 | /* 37826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13636 | /* 37830 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13637 | /* 37834 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 13638 | /* 37834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13639 | /* 37837 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13640 | /* 37839 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13641 | /* 37841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13642 | /* 37846 */ // GIR_Coverage, 3167, |
| 13643 | /* 37846 */ GIR_EraseRootFromParent_Done, |
| 13644 | /* 37847 */ // Label 842: @37847 |
| 13645 | /* 37847 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(37879), // Rule ID 3168 // |
| 13646 | /* 37852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13647 | /* 37855 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13648 | /* 37858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13649 | /* 37862 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13650 | /* 37866 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 13651 | /* 37866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13652 | /* 37869 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13653 | /* 37871 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13654 | /* 37873 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13655 | /* 37878 */ // GIR_Coverage, 3168, |
| 13656 | /* 37878 */ GIR_EraseRootFromParent_Done, |
| 13657 | /* 37879 */ // Label 843: @37879 |
| 13658 | /* 37879 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(37911), // Rule ID 3169 // |
| 13659 | /* 37884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13660 | /* 37887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13661 | /* 37890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13662 | /* 37894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13663 | /* 37898 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 13664 | /* 37898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13665 | /* 37901 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13666 | /* 37903 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13667 | /* 37905 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13668 | /* 37910 */ // GIR_Coverage, 3169, |
| 13669 | /* 37910 */ GIR_EraseRootFromParent_Done, |
| 13670 | /* 37911 */ // Label 844: @37911 |
| 13671 | /* 37911 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(37943), // Rule ID 3170 // |
| 13672 | /* 37916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13673 | /* 37919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13674 | /* 37922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13675 | /* 37926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13676 | /* 37930 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 13677 | /* 37930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13678 | /* 37933 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13679 | /* 37935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13680 | /* 37937 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13681 | /* 37942 */ // GIR_Coverage, 3170, |
| 13682 | /* 37942 */ GIR_EraseRootFromParent_Done, |
| 13683 | /* 37943 */ // Label 845: @37943 |
| 13684 | /* 37943 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(37975), // Rule ID 3171 // |
| 13685 | /* 37948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 13686 | /* 37951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13687 | /* 37954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13688 | /* 37958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13689 | /* 37962 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src |
| 13690 | /* 37962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13691 | /* 37965 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13692 | /* 37967 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13693 | /* 37969 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13694 | /* 37974 */ // GIR_Coverage, 3171, |
| 13695 | /* 37974 */ GIR_EraseRootFromParent_Done, |
| 13696 | /* 37975 */ // Label 846: @37975 |
| 13697 | /* 37975 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(38012), // Rule ID 3234 // |
| 13698 | /* 37980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13699 | /* 37983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13700 | /* 37986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13701 | /* 37990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13702 | /* 37994 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) |
| 13703 | /* 37994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13704 | /* 37997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13705 | /* 37999 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13706 | /* 38001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13707 | /* 38004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13708 | /* 38010 */ GIR_RootConstrainSelectedInstOperands, |
| 13709 | /* 38011 */ // GIR_Coverage, 3234, |
| 13710 | /* 38011 */ GIR_EraseRootFromParent_Done, |
| 13711 | /* 38012 */ // Label 847: @38012 |
| 13712 | /* 38012 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(38049), // Rule ID 3235 // |
| 13713 | /* 38017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13714 | /* 38020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13715 | /* 38023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13716 | /* 38027 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13717 | /* 38031 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) |
| 13718 | /* 38031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13719 | /* 38034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13720 | /* 38036 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13721 | /* 38038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13722 | /* 38041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13723 | /* 38047 */ GIR_RootConstrainSelectedInstOperands, |
| 13724 | /* 38048 */ // GIR_Coverage, 3235, |
| 13725 | /* 38048 */ GIR_EraseRootFromParent_Done, |
| 13726 | /* 38049 */ // Label 848: @38049 |
| 13727 | /* 38049 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(38086), // Rule ID 3236 // |
| 13728 | /* 38054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13729 | /* 38057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13730 | /* 38060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13731 | /* 38064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13732 | /* 38068 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) |
| 13733 | /* 38068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 13734 | /* 38071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13735 | /* 38073 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13736 | /* 38075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13737 | /* 38078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13738 | /* 38084 */ GIR_RootConstrainSelectedInstOperands, |
| 13739 | /* 38085 */ // GIR_Coverage, 3236, |
| 13740 | /* 38085 */ GIR_EraseRootFromParent_Done, |
| 13741 | /* 38086 */ // Label 849: @38086 |
| 13742 | /* 38086 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(38123), // Rule ID 3237 // |
| 13743 | /* 38091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13744 | /* 38094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13745 | /* 38097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13746 | /* 38101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13747 | /* 38105 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) |
| 13748 | /* 38105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 13749 | /* 38108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13750 | /* 38110 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13751 | /* 38112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13752 | /* 38115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13753 | /* 38121 */ GIR_RootConstrainSelectedInstOperands, |
| 13754 | /* 38122 */ // GIR_Coverage, 3237, |
| 13755 | /* 38122 */ GIR_EraseRootFromParent_Done, |
| 13756 | /* 38123 */ // Label 850: @38123 |
| 13757 | /* 38123 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(38160), // Rule ID 3238 // |
| 13758 | /* 38128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13759 | /* 38131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13760 | /* 38134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13761 | /* 38138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13762 | /* 38142 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) |
| 13763 | /* 38142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 13764 | /* 38145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13765 | /* 38147 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13766 | /* 38149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13767 | /* 38152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13768 | /* 38158 */ GIR_RootConstrainSelectedInstOperands, |
| 13769 | /* 38159 */ // GIR_Coverage, 3238, |
| 13770 | /* 38159 */ GIR_EraseRootFromParent_Done, |
| 13771 | /* 38160 */ // Label 851: @38160 |
| 13772 | /* 38160 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(38197), // Rule ID 3239 // |
| 13773 | /* 38165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13774 | /* 38168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13775 | /* 38171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13776 | /* 38175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13777 | /* 38179 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) |
| 13778 | /* 38179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13779 | /* 38182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13780 | /* 38184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13781 | /* 38186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13782 | /* 38189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13783 | /* 38195 */ GIR_RootConstrainSelectedInstOperands, |
| 13784 | /* 38196 */ // GIR_Coverage, 3239, |
| 13785 | /* 38196 */ GIR_EraseRootFromParent_Done, |
| 13786 | /* 38197 */ // Label 852: @38197 |
| 13787 | /* 38197 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(38234), // Rule ID 3240 // |
| 13788 | /* 38202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13789 | /* 38205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13790 | /* 38208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13791 | /* 38212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13792 | /* 38216 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) |
| 13793 | /* 38216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13794 | /* 38219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13795 | /* 38221 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13796 | /* 38223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13797 | /* 38226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13798 | /* 38232 */ GIR_RootConstrainSelectedInstOperands, |
| 13799 | /* 38233 */ // GIR_Coverage, 3240, |
| 13800 | /* 38233 */ GIR_EraseRootFromParent_Done, |
| 13801 | /* 38234 */ // Label 853: @38234 |
| 13802 | /* 38234 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(38271), // Rule ID 3241 // |
| 13803 | /* 38239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13804 | /* 38242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13805 | /* 38245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13806 | /* 38249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13807 | /* 38253 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) |
| 13808 | /* 38253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 13809 | /* 38256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13810 | /* 38258 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13811 | /* 38260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13812 | /* 38263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13813 | /* 38269 */ GIR_RootConstrainSelectedInstOperands, |
| 13814 | /* 38270 */ // GIR_Coverage, 3241, |
| 13815 | /* 38270 */ GIR_EraseRootFromParent_Done, |
| 13816 | /* 38271 */ // Label 854: @38271 |
| 13817 | /* 38271 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(38308), // Rule ID 3242 // |
| 13818 | /* 38276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13819 | /* 38279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13820 | /* 38282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13821 | /* 38286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13822 | /* 38290 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) |
| 13823 | /* 38290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 13824 | /* 38293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13825 | /* 38295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13826 | /* 38297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13827 | /* 38300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13828 | /* 38306 */ GIR_RootConstrainSelectedInstOperands, |
| 13829 | /* 38307 */ // GIR_Coverage, 3242, |
| 13830 | /* 38307 */ GIR_EraseRootFromParent_Done, |
| 13831 | /* 38308 */ // Label 855: @38308 |
| 13832 | /* 38308 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(38345), // Rule ID 3243 // |
| 13833 | /* 38313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 13834 | /* 38316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13835 | /* 38319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13836 | /* 38323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13837 | /* 38327 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) |
| 13838 | /* 38327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 13839 | /* 38330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13840 | /* 38332 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13841 | /* 38334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13842 | /* 38337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13843 | /* 38343 */ GIR_RootConstrainSelectedInstOperands, |
| 13844 | /* 38344 */ // GIR_Coverage, 3243, |
| 13845 | /* 38344 */ GIR_EraseRootFromParent_Done, |
| 13846 | /* 38345 */ // Label 856: @38345 |
| 13847 | /* 38345 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(38377), // Rule ID 5801 // |
| 13848 | /* 38350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 13849 | /* 38353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13850 | /* 38356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13851 | /* 38360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13852 | /* 38364 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 13853 | /* 38364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13854 | /* 38367 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13855 | /* 38369 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13856 | /* 38371 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13857 | /* 38376 */ // GIR_Coverage, 5801, |
| 13858 | /* 38376 */ GIR_EraseRootFromParent_Done, |
| 13859 | /* 38377 */ // Label 857: @38377 |
| 13860 | /* 38377 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(38409), // Rule ID 5802 // |
| 13861 | /* 38382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 13862 | /* 38385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13863 | /* 38388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13864 | /* 38392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13865 | /* 38396 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 13866 | /* 38396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13867 | /* 38399 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13868 | /* 38401 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13869 | /* 38403 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13870 | /* 38408 */ // GIR_Coverage, 5802, |
| 13871 | /* 38408 */ GIR_EraseRootFromParent_Done, |
| 13872 | /* 38409 */ // Label 858: @38409 |
| 13873 | /* 38409 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(38441), // Rule ID 5823 // |
| 13874 | /* 38414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13875 | /* 38417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13876 | /* 38420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13877 | /* 38424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13878 | /* 38428 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 13879 | /* 38428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13880 | /* 38431 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13881 | /* 38433 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13882 | /* 38435 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13883 | /* 38440 */ // GIR_Coverage, 5823, |
| 13884 | /* 38440 */ GIR_EraseRootFromParent_Done, |
| 13885 | /* 38441 */ // Label 859: @38441 |
| 13886 | /* 38441 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(38473), // Rule ID 5824 // |
| 13887 | /* 38446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13888 | /* 38449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13889 | /* 38452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13890 | /* 38456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13891 | /* 38460 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 13892 | /* 38460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13893 | /* 38463 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13894 | /* 38465 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13895 | /* 38467 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13896 | /* 38472 */ // GIR_Coverage, 5824, |
| 13897 | /* 38472 */ GIR_EraseRootFromParent_Done, |
| 13898 | /* 38473 */ // Label 860: @38473 |
| 13899 | /* 38473 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(38505), // Rule ID 5825 // |
| 13900 | /* 38478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13901 | /* 38481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13902 | /* 38484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13903 | /* 38488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13904 | /* 38492 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 13905 | /* 38492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13906 | /* 38495 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13907 | /* 38497 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13908 | /* 38499 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13909 | /* 38504 */ // GIR_Coverage, 5825, |
| 13910 | /* 38504 */ GIR_EraseRootFromParent_Done, |
| 13911 | /* 38505 */ // Label 861: @38505 |
| 13912 | /* 38505 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(38537), // Rule ID 5826 // |
| 13913 | /* 38510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13914 | /* 38513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13915 | /* 38516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13916 | /* 38520 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13917 | /* 38524 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 13918 | /* 38524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13919 | /* 38527 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13920 | /* 38529 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13921 | /* 38531 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13922 | /* 38536 */ // GIR_Coverage, 5826, |
| 13923 | /* 38536 */ GIR_EraseRootFromParent_Done, |
| 13924 | /* 38537 */ // Label 862: @38537 |
| 13925 | /* 38537 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(38569), // Rule ID 5827 // |
| 13926 | /* 38542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13927 | /* 38545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13928 | /* 38548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13929 | /* 38552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13930 | /* 38556 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 13931 | /* 38556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13932 | /* 38559 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13933 | /* 38561 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13934 | /* 38563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13935 | /* 38568 */ // GIR_Coverage, 5827, |
| 13936 | /* 38568 */ GIR_EraseRootFromParent_Done, |
| 13937 | /* 38569 */ // Label 863: @38569 |
| 13938 | /* 38569 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(38601), // Rule ID 5828 // |
| 13939 | /* 38574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13940 | /* 38577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13941 | /* 38580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13942 | /* 38584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13943 | /* 38588 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 13944 | /* 38588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13945 | /* 38591 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13946 | /* 38593 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13947 | /* 38595 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13948 | /* 38600 */ // GIR_Coverage, 5828, |
| 13949 | /* 38600 */ GIR_EraseRootFromParent_Done, |
| 13950 | /* 38601 */ // Label 864: @38601 |
| 13951 | /* 38601 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(38633), // Rule ID 5829 // |
| 13952 | /* 38606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13953 | /* 38609 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13954 | /* 38612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13955 | /* 38616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13956 | /* 38620 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 13957 | /* 38620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13958 | /* 38623 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13959 | /* 38625 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13960 | /* 38627 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13961 | /* 38632 */ // GIR_Coverage, 5829, |
| 13962 | /* 38632 */ GIR_EraseRootFromParent_Done, |
| 13963 | /* 38633 */ // Label 865: @38633 |
| 13964 | /* 38633 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(38665), // Rule ID 5830 // |
| 13965 | /* 38638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13966 | /* 38641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13967 | /* 38644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13968 | /* 38648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13969 | /* 38652 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 13970 | /* 38652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13971 | /* 38655 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13972 | /* 38657 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13973 | /* 38659 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13974 | /* 38664 */ // GIR_Coverage, 5830, |
| 13975 | /* 38664 */ GIR_EraseRootFromParent_Done, |
| 13976 | /* 38665 */ // Label 866: @38665 |
| 13977 | /* 38665 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(38697), // Rule ID 5831 // |
| 13978 | /* 38670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13979 | /* 38673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13980 | /* 38676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13981 | /* 38680 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13982 | /* 38684 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 13983 | /* 38684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13984 | /* 38687 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13985 | /* 38689 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13986 | /* 38691 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13987 | /* 38696 */ // GIR_Coverage, 5831, |
| 13988 | /* 38696 */ GIR_EraseRootFromParent_Done, |
| 13989 | /* 38697 */ // Label 867: @38697 |
| 13990 | /* 38697 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(38729), // Rule ID 5832 // |
| 13991 | /* 38702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 13992 | /* 38705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13993 | /* 38708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13994 | /* 38712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13995 | /* 38716 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 13996 | /* 38716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13997 | /* 38719 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13998 | /* 38721 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13999 | /* 38723 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14000 | /* 38728 */ // GIR_Coverage, 5832, |
| 14001 | /* 38728 */ GIR_EraseRootFromParent_Done, |
| 14002 | /* 38729 */ // Label 868: @38729 |
| 14003 | /* 38729 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(38787), // Rule ID 5859 // |
| 14004 | /* 38734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14005 | /* 38737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14006 | /* 38740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14007 | /* 38744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14008 | /* 38748 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) |
| 14009 | /* 38748 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14010 | /* 38751 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14011 | /* 38755 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14012 | /* 38760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 14013 | /* 38763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14014 | /* 38765 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14015 | /* 38767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14016 | /* 38770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14017 | /* 38776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14018 | /* 38782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14019 | /* 38785 */ GIR_RootConstrainSelectedInstOperands, |
| 14020 | /* 38786 */ // GIR_Coverage, 5859, |
| 14021 | /* 38786 */ GIR_EraseRootFromParent_Done, |
| 14022 | /* 38787 */ // Label 869: @38787 |
| 14023 | /* 38787 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(38845), // Rule ID 5860 // |
| 14024 | /* 38792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14025 | /* 38795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14026 | /* 38798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14027 | /* 38802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14028 | /* 38806 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) |
| 14029 | /* 38806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14030 | /* 38809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14031 | /* 38813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14032 | /* 38818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 14033 | /* 38821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14034 | /* 38823 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14035 | /* 38825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14036 | /* 38828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14037 | /* 38834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14038 | /* 38840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14039 | /* 38843 */ GIR_RootConstrainSelectedInstOperands, |
| 14040 | /* 38844 */ // GIR_Coverage, 5860, |
| 14041 | /* 38844 */ GIR_EraseRootFromParent_Done, |
| 14042 | /* 38845 */ // Label 870: @38845 |
| 14043 | /* 38845 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(38903), // Rule ID 5861 // |
| 14044 | /* 38850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14045 | /* 38853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14046 | /* 38856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14047 | /* 38860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14048 | /* 38864 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) |
| 14049 | /* 38864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14050 | /* 38867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14051 | /* 38871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14052 | /* 38876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 14053 | /* 38879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14054 | /* 38881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14055 | /* 38883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14056 | /* 38886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14057 | /* 38892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14058 | /* 38898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14059 | /* 38901 */ GIR_RootConstrainSelectedInstOperands, |
| 14060 | /* 38902 */ // GIR_Coverage, 5861, |
| 14061 | /* 38902 */ GIR_EraseRootFromParent_Done, |
| 14062 | /* 38903 */ // Label 871: @38903 |
| 14063 | /* 38903 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(38961), // Rule ID 5862 // |
| 14064 | /* 38908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14065 | /* 38911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14066 | /* 38914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14067 | /* 38918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14068 | /* 38922 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) |
| 14069 | /* 38922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14070 | /* 38925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14071 | /* 38929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14072 | /* 38934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 14073 | /* 38937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14074 | /* 38939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14075 | /* 38941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14076 | /* 38944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14077 | /* 38950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14078 | /* 38956 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14079 | /* 38959 */ GIR_RootConstrainSelectedInstOperands, |
| 14080 | /* 38960 */ // GIR_Coverage, 5862, |
| 14081 | /* 38960 */ GIR_EraseRootFromParent_Done, |
| 14082 | /* 38961 */ // Label 872: @38961 |
| 14083 | /* 38961 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(39019), // Rule ID 5863 // |
| 14084 | /* 38966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14085 | /* 38969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14086 | /* 38972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14087 | /* 38976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14088 | /* 38980 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) |
| 14089 | /* 38980 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14090 | /* 38983 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14091 | /* 38987 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14092 | /* 38992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 14093 | /* 38995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14094 | /* 38997 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14095 | /* 38999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14096 | /* 39002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14097 | /* 39008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14098 | /* 39014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14099 | /* 39017 */ GIR_RootConstrainSelectedInstOperands, |
| 14100 | /* 39018 */ // GIR_Coverage, 5863, |
| 14101 | /* 39018 */ GIR_EraseRootFromParent_Done, |
| 14102 | /* 39019 */ // Label 873: @39019 |
| 14103 | /* 39019 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(39077), // Rule ID 5864 // |
| 14104 | /* 39024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14105 | /* 39027 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14106 | /* 39030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14107 | /* 39034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14108 | /* 39038 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) |
| 14109 | /* 39038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14110 | /* 39041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14111 | /* 39045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14112 | /* 39050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 14113 | /* 39053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14114 | /* 39055 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14115 | /* 39057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14116 | /* 39060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14117 | /* 39066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14118 | /* 39072 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14119 | /* 39075 */ GIR_RootConstrainSelectedInstOperands, |
| 14120 | /* 39076 */ // GIR_Coverage, 5864, |
| 14121 | /* 39076 */ GIR_EraseRootFromParent_Done, |
| 14122 | /* 39077 */ // Label 874: @39077 |
| 14123 | /* 39077 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(39135), // Rule ID 5865 // |
| 14124 | /* 39082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14125 | /* 39085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14126 | /* 39088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14127 | /* 39092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14128 | /* 39096 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) |
| 14129 | /* 39096 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14130 | /* 39099 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14131 | /* 39103 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14132 | /* 39108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 14133 | /* 39111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14134 | /* 39113 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14135 | /* 39115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14136 | /* 39118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14137 | /* 39124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14138 | /* 39130 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14139 | /* 39133 */ GIR_RootConstrainSelectedInstOperands, |
| 14140 | /* 39134 */ // GIR_Coverage, 5865, |
| 14141 | /* 39134 */ GIR_EraseRootFromParent_Done, |
| 14142 | /* 39135 */ // Label 875: @39135 |
| 14143 | /* 39135 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(39193), // Rule ID 5866 // |
| 14144 | /* 39140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14145 | /* 39143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14146 | /* 39146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14147 | /* 39150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14148 | /* 39154 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) |
| 14149 | /* 39154 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14150 | /* 39157 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14151 | /* 39161 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14152 | /* 39166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 14153 | /* 39169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14154 | /* 39171 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14155 | /* 39173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14156 | /* 39176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14157 | /* 39182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14158 | /* 39188 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14159 | /* 39191 */ GIR_RootConstrainSelectedInstOperands, |
| 14160 | /* 39192 */ // GIR_Coverage, 5866, |
| 14161 | /* 39192 */ GIR_EraseRootFromParent_Done, |
| 14162 | /* 39193 */ // Label 876: @39193 |
| 14163 | /* 39193 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(39251), // Rule ID 5867 // |
| 14164 | /* 39198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14165 | /* 39201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14166 | /* 39204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14167 | /* 39208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14168 | /* 39212 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) |
| 14169 | /* 39212 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14170 | /* 39215 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14171 | /* 39219 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14172 | /* 39224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 14173 | /* 39227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14174 | /* 39229 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14175 | /* 39231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14176 | /* 39234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14177 | /* 39240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14178 | /* 39246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14179 | /* 39249 */ GIR_RootConstrainSelectedInstOperands, |
| 14180 | /* 39250 */ // GIR_Coverage, 5867, |
| 14181 | /* 39250 */ GIR_EraseRootFromParent_Done, |
| 14182 | /* 39251 */ // Label 877: @39251 |
| 14183 | /* 39251 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(39309), // Rule ID 5868 // |
| 14184 | /* 39256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14185 | /* 39259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14186 | /* 39262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14187 | /* 39266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14188 | /* 39270 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 14189 | /* 39270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14190 | /* 39273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14191 | /* 39277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14192 | /* 39282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 14193 | /* 39285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14194 | /* 39287 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14195 | /* 39289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14196 | /* 39292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14197 | /* 39298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14198 | /* 39304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14199 | /* 39307 */ GIR_RootConstrainSelectedInstOperands, |
| 14200 | /* 39308 */ // GIR_Coverage, 5868, |
| 14201 | /* 39308 */ GIR_EraseRootFromParent_Done, |
| 14202 | /* 39309 */ // Label 878: @39309 |
| 14203 | /* 39309 */ GIM_Reject, |
| 14204 | /* 39310 */ // Label 663: @39310 |
| 14205 | /* 39310 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(39342), // Rule ID 3172 // |
| 14206 | /* 39315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 14207 | /* 39318 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14208 | /* 39321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14209 | /* 39325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14210 | /* 39329 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 14211 | /* 39329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14212 | /* 39332 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14213 | /* 39334 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14214 | /* 39336 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 14215 | /* 39341 */ // GIR_Coverage, 3172, |
| 14216 | /* 39341 */ GIR_EraseRootFromParent_Done, |
| 14217 | /* 39342 */ // Label 879: @39342 |
| 14218 | /* 39342 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(39374), // Rule ID 3173 // |
| 14219 | /* 39347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 14220 | /* 39350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14221 | /* 39353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14222 | /* 39357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14223 | /* 39361 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 14224 | /* 39361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14225 | /* 39364 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14226 | /* 39366 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14227 | /* 39368 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 14228 | /* 39373 */ // GIR_Coverage, 3173, |
| 14229 | /* 39373 */ GIR_EraseRootFromParent_Done, |
| 14230 | /* 39374 */ // Label 880: @39374 |
| 14231 | /* 39374 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(39406), // Rule ID 3174 // |
| 14232 | /* 39379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 14233 | /* 39382 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14234 | /* 39385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14235 | /* 39389 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14236 | /* 39393 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 14237 | /* 39393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14238 | /* 39396 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14239 | /* 39398 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14240 | /* 39400 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 14241 | /* 39405 */ // GIR_Coverage, 3174, |
| 14242 | /* 39405 */ GIR_EraseRootFromParent_Done, |
| 14243 | /* 39406 */ // Label 881: @39406 |
| 14244 | /* 39406 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(39438), // Rule ID 3175 // |
| 14245 | /* 39411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 14246 | /* 39414 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14247 | /* 39417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14248 | /* 39421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14249 | /* 39425 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 14250 | /* 39425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14251 | /* 39428 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14252 | /* 39430 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14253 | /* 39432 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 14254 | /* 39437 */ // GIR_Coverage, 3175, |
| 14255 | /* 39437 */ GIR_EraseRootFromParent_Done, |
| 14256 | /* 39438 */ // Label 882: @39438 |
| 14257 | /* 39438 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(39470), // Rule ID 3176 // |
| 14258 | /* 39443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 14259 | /* 39446 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14260 | /* 39449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14261 | /* 39453 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14262 | /* 39457 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 14263 | /* 39457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14264 | /* 39460 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14265 | /* 39462 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14266 | /* 39464 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 14267 | /* 39469 */ // GIR_Coverage, 3176, |
| 14268 | /* 39469 */ GIR_EraseRootFromParent_Done, |
| 14269 | /* 39470 */ // Label 883: @39470 |
| 14270 | /* 39470 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(39502), // Rule ID 3177 // |
| 14271 | /* 39475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 14272 | /* 39478 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14273 | /* 39481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14274 | /* 39485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14275 | /* 39489 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 14276 | /* 39489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14277 | /* 39492 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14278 | /* 39494 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14279 | /* 39496 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 14280 | /* 39501 */ // GIR_Coverage, 3177, |
| 14281 | /* 39501 */ GIR_EraseRootFromParent_Done, |
| 14282 | /* 39502 */ // Label 884: @39502 |
| 14283 | /* 39502 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(39539), // Rule ID 3244 // |
| 14284 | /* 39507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 14285 | /* 39510 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14286 | /* 39513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14287 | /* 39517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14288 | /* 39521 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) |
| 14289 | /* 39521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 14290 | /* 39524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14291 | /* 39526 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14292 | /* 39528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14293 | /* 39531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14294 | /* 39537 */ GIR_RootConstrainSelectedInstOperands, |
| 14295 | /* 39538 */ // GIR_Coverage, 3244, |
| 14296 | /* 39538 */ GIR_EraseRootFromParent_Done, |
| 14297 | /* 39539 */ // Label 885: @39539 |
| 14298 | /* 39539 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(39576), // Rule ID 3245 // |
| 14299 | /* 39544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 14300 | /* 39547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14301 | /* 39550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14302 | /* 39554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14303 | /* 39558 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) |
| 14304 | /* 39558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 14305 | /* 39561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14306 | /* 39563 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14307 | /* 39565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14308 | /* 39568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14309 | /* 39574 */ GIR_RootConstrainSelectedInstOperands, |
| 14310 | /* 39575 */ // GIR_Coverage, 3245, |
| 14311 | /* 39575 */ GIR_EraseRootFromParent_Done, |
| 14312 | /* 39576 */ // Label 886: @39576 |
| 14313 | /* 39576 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(39613), // Rule ID 3246 // |
| 14314 | /* 39581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 14315 | /* 39584 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14316 | /* 39587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14317 | /* 39591 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14318 | /* 39595 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) |
| 14319 | /* 39595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 14320 | /* 39598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14321 | /* 39600 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14322 | /* 39602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14323 | /* 39605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14324 | /* 39611 */ GIR_RootConstrainSelectedInstOperands, |
| 14325 | /* 39612 */ // GIR_Coverage, 3246, |
| 14326 | /* 39612 */ GIR_EraseRootFromParent_Done, |
| 14327 | /* 39613 */ // Label 887: @39613 |
| 14328 | /* 39613 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(39650), // Rule ID 3247 // |
| 14329 | /* 39618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 14330 | /* 39621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14331 | /* 39624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14332 | /* 39628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14333 | /* 39632 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) |
| 14334 | /* 39632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 14335 | /* 39635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14336 | /* 39637 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14337 | /* 39639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14338 | /* 39642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14339 | /* 39648 */ GIR_RootConstrainSelectedInstOperands, |
| 14340 | /* 39649 */ // GIR_Coverage, 3247, |
| 14341 | /* 39649 */ GIR_EraseRootFromParent_Done, |
| 14342 | /* 39650 */ // Label 888: @39650 |
| 14343 | /* 39650 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(39687), // Rule ID 3248 // |
| 14344 | /* 39655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 14345 | /* 39658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14346 | /* 39661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14347 | /* 39665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14348 | /* 39669 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) |
| 14349 | /* 39669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 14350 | /* 39672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14351 | /* 39674 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14352 | /* 39676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14353 | /* 39679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14354 | /* 39685 */ GIR_RootConstrainSelectedInstOperands, |
| 14355 | /* 39686 */ // GIR_Coverage, 3248, |
| 14356 | /* 39686 */ GIR_EraseRootFromParent_Done, |
| 14357 | /* 39687 */ // Label 889: @39687 |
| 14358 | /* 39687 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(39724), // Rule ID 3249 // |
| 14359 | /* 39692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 14360 | /* 39695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14361 | /* 39698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14362 | /* 39702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14363 | /* 39706 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) |
| 14364 | /* 39706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 14365 | /* 39709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14366 | /* 39711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14367 | /* 39713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14368 | /* 39716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14369 | /* 39722 */ GIR_RootConstrainSelectedInstOperands, |
| 14370 | /* 39723 */ // GIR_Coverage, 3249, |
| 14371 | /* 39723 */ GIR_EraseRootFromParent_Done, |
| 14372 | /* 39724 */ // Label 890: @39724 |
| 14373 | /* 39724 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(39756), // Rule ID 5833 // |
| 14374 | /* 39729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 14375 | /* 39732 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14376 | /* 39735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14377 | /* 39739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14378 | /* 39743 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 14379 | /* 39743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14380 | /* 39746 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14381 | /* 39748 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14382 | /* 39750 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14383 | /* 39755 */ // GIR_Coverage, 5833, |
| 14384 | /* 39755 */ GIR_EraseRootFromParent_Done, |
| 14385 | /* 39756 */ // Label 891: @39756 |
| 14386 | /* 39756 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(39788), // Rule ID 5834 // |
| 14387 | /* 39761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 14388 | /* 39764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14389 | /* 39767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14390 | /* 39771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14391 | /* 39775 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 14392 | /* 39775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14393 | /* 39778 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14394 | /* 39780 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14395 | /* 39782 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14396 | /* 39787 */ // GIR_Coverage, 5834, |
| 14397 | /* 39787 */ GIR_EraseRootFromParent_Done, |
| 14398 | /* 39788 */ // Label 892: @39788 |
| 14399 | /* 39788 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(39820), // Rule ID 5835 // |
| 14400 | /* 39793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 14401 | /* 39796 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14402 | /* 39799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14403 | /* 39803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14404 | /* 39807 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 14405 | /* 39807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14406 | /* 39810 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14407 | /* 39812 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14408 | /* 39814 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14409 | /* 39819 */ // GIR_Coverage, 5835, |
| 14410 | /* 39819 */ GIR_EraseRootFromParent_Done, |
| 14411 | /* 39820 */ // Label 893: @39820 |
| 14412 | /* 39820 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(39852), // Rule ID 5836 // |
| 14413 | /* 39825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 14414 | /* 39828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14415 | /* 39831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14416 | /* 39835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14417 | /* 39839 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 14418 | /* 39839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14419 | /* 39842 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14420 | /* 39844 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14421 | /* 39846 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14422 | /* 39851 */ // GIR_Coverage, 5836, |
| 14423 | /* 39851 */ GIR_EraseRootFromParent_Done, |
| 14424 | /* 39852 */ // Label 894: @39852 |
| 14425 | /* 39852 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(39884), // Rule ID 5837 // |
| 14426 | /* 39857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 14427 | /* 39860 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14428 | /* 39863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14429 | /* 39867 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14430 | /* 39871 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 14431 | /* 39871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14432 | /* 39874 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14433 | /* 39876 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14434 | /* 39878 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14435 | /* 39883 */ // GIR_Coverage, 5837, |
| 14436 | /* 39883 */ GIR_EraseRootFromParent_Done, |
| 14437 | /* 39884 */ // Label 895: @39884 |
| 14438 | /* 39884 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(39916), // Rule ID 5838 // |
| 14439 | /* 39889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 14440 | /* 39892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14441 | /* 39895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14442 | /* 39899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14443 | /* 39903 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 14444 | /* 39903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14445 | /* 39906 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14446 | /* 39908 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14447 | /* 39910 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14448 | /* 39915 */ // GIR_Coverage, 5838, |
| 14449 | /* 39915 */ GIR_EraseRootFromParent_Done, |
| 14450 | /* 39916 */ // Label 896: @39916 |
| 14451 | /* 39916 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(39974), // Rule ID 5869 // |
| 14452 | /* 39921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14453 | /* 39924 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14454 | /* 39927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14455 | /* 39931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14456 | /* 39935 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) |
| 14457 | /* 39935 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14458 | /* 39938 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14459 | /* 39942 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14460 | /* 39947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 14461 | /* 39950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14462 | /* 39952 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14463 | /* 39954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14464 | /* 39957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14465 | /* 39963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14466 | /* 39969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14467 | /* 39972 */ GIR_RootConstrainSelectedInstOperands, |
| 14468 | /* 39973 */ // GIR_Coverage, 5869, |
| 14469 | /* 39973 */ GIR_EraseRootFromParent_Done, |
| 14470 | /* 39974 */ // Label 897: @39974 |
| 14471 | /* 39974 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(40032), // Rule ID 5870 // |
| 14472 | /* 39979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14473 | /* 39982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14474 | /* 39985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14475 | /* 39989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14476 | /* 39993 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) |
| 14477 | /* 39993 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14478 | /* 39996 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14479 | /* 40000 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14480 | /* 40005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 14481 | /* 40008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14482 | /* 40010 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14483 | /* 40012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14484 | /* 40015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14485 | /* 40021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14486 | /* 40027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14487 | /* 40030 */ GIR_RootConstrainSelectedInstOperands, |
| 14488 | /* 40031 */ // GIR_Coverage, 5870, |
| 14489 | /* 40031 */ GIR_EraseRootFromParent_Done, |
| 14490 | /* 40032 */ // Label 898: @40032 |
| 14491 | /* 40032 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(40090), // Rule ID 5871 // |
| 14492 | /* 40037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14493 | /* 40040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14494 | /* 40043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14495 | /* 40047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14496 | /* 40051 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) |
| 14497 | /* 40051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14498 | /* 40054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14499 | /* 40058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14500 | /* 40063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 14501 | /* 40066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14502 | /* 40068 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14503 | /* 40070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14504 | /* 40073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14505 | /* 40079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14506 | /* 40085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14507 | /* 40088 */ GIR_RootConstrainSelectedInstOperands, |
| 14508 | /* 40089 */ // GIR_Coverage, 5871, |
| 14509 | /* 40089 */ GIR_EraseRootFromParent_Done, |
| 14510 | /* 40090 */ // Label 899: @40090 |
| 14511 | /* 40090 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(40148), // Rule ID 5872 // |
| 14512 | /* 40095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14513 | /* 40098 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14514 | /* 40101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14515 | /* 40105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14516 | /* 40109 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) |
| 14517 | /* 40109 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14518 | /* 40112 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14519 | /* 40116 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14520 | /* 40121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 14521 | /* 40124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14522 | /* 40126 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14523 | /* 40128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14524 | /* 40131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14525 | /* 40137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14526 | /* 40143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14527 | /* 40146 */ GIR_RootConstrainSelectedInstOperands, |
| 14528 | /* 40147 */ // GIR_Coverage, 5872, |
| 14529 | /* 40147 */ GIR_EraseRootFromParent_Done, |
| 14530 | /* 40148 */ // Label 900: @40148 |
| 14531 | /* 40148 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(40206), // Rule ID 5873 // |
| 14532 | /* 40153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14533 | /* 40156 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14534 | /* 40159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14535 | /* 40163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14536 | /* 40167 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) |
| 14537 | /* 40167 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14538 | /* 40170 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14539 | /* 40174 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14540 | /* 40179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 14541 | /* 40182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14542 | /* 40184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14543 | /* 40186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14544 | /* 40189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14545 | /* 40195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14546 | /* 40201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14547 | /* 40204 */ GIR_RootConstrainSelectedInstOperands, |
| 14548 | /* 40205 */ // GIR_Coverage, 5873, |
| 14549 | /* 40205 */ GIR_EraseRootFromParent_Done, |
| 14550 | /* 40206 */ // Label 901: @40206 |
| 14551 | /* 40206 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(40264), // Rule ID 5874 // |
| 14552 | /* 40211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 14553 | /* 40214 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14554 | /* 40217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14555 | /* 40221 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14556 | /* 40225 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) |
| 14557 | /* 40225 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14558 | /* 40228 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14559 | /* 40232 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14560 | /* 40237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 14561 | /* 40240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14562 | /* 40242 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 14563 | /* 40244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14564 | /* 40247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14565 | /* 40253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14566 | /* 40259 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14567 | /* 40262 */ GIR_RootConstrainSelectedInstOperands, |
| 14568 | /* 40263 */ // GIR_Coverage, 5874, |
| 14569 | /* 40263 */ GIR_EraseRootFromParent_Done, |
| 14570 | /* 40264 */ // Label 902: @40264 |
| 14571 | /* 40264 */ GIM_Reject, |
| 14572 | /* 40265 */ // Label 664: @40265 |
| 14573 | /* 40265 */ GIM_Reject, |
| 14574 | /* 40266 */ // Label 16: @40266 |
| 14575 | /* 40266 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 910*/ GIMT_Encode4(40673), |
| 14576 | /* 40277 */ /*GILLT_s16*//*Label 903*/ GIMT_Encode4(40329), |
| 14577 | /* 40281 */ /*GILLT_s32*//*Label 904*/ GIMT_Encode4(40367), |
| 14578 | /* 40285 */ /*GILLT_s64*//*Label 905*/ GIMT_Encode4(40405), GIMT_Encode4(0), |
| 14579 | /* 40293 */ /*GILLT_v2s32*//*Label 906*/ GIMT_Encode4(40443), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14580 | /* 40305 */ /*GILLT_v4s16*//*Label 907*/ GIMT_Encode4(40470), |
| 14581 | /* 40309 */ /*GILLT_v4s32*//*Label 908*/ GIMT_Encode4(40497), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14582 | /* 40325 */ /*GILLT_v8s16*//*Label 909*/ GIMT_Encode4(40585), |
| 14583 | /* 40329 */ // Label 903: @40329 |
| 14584 | /* 40329 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(40366), // Rule ID 692 // |
| 14585 | /* 40334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 14586 | /* 40337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 14587 | /* 40340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 14588 | /* 40344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 14589 | /* 40348 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 14590 | /* 40348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH), |
| 14591 | /* 40351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14592 | /* 40353 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 14593 | /* 40355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14594 | /* 40358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14595 | /* 40364 */ GIR_RootConstrainSelectedInstOperands, |
| 14596 | /* 40365 */ // GIR_Coverage, 692, |
| 14597 | /* 40365 */ GIR_EraseRootFromParent_Done, |
| 14598 | /* 40366 */ // Label 911: @40366 |
| 14599 | /* 40366 */ GIM_Reject, |
| 14600 | /* 40367 */ // Label 904: @40367 |
| 14601 | /* 40367 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(40404), // Rule ID 694 // |
| 14602 | /* 40372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 14603 | /* 40375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14604 | /* 40378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14605 | /* 40382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14606 | /* 40386 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 14607 | /* 40386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS), |
| 14608 | /* 40389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14609 | /* 40391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 14610 | /* 40393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14611 | /* 40396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14612 | /* 40402 */ GIR_RootConstrainSelectedInstOperands, |
| 14613 | /* 40403 */ // GIR_Coverage, 694, |
| 14614 | /* 40403 */ GIR_EraseRootFromParent_Done, |
| 14615 | /* 40404 */ // Label 912: @40404 |
| 14616 | /* 40404 */ GIM_Reject, |
| 14617 | /* 40405 */ // Label 905: @40405 |
| 14618 | /* 40405 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(40442), // Rule ID 696 // |
| 14619 | /* 40410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 14620 | /* 40413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14621 | /* 40416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14622 | /* 40420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14623 | /* 40424 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 14624 | /* 40424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD), |
| 14625 | /* 40427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 14626 | /* 40429 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 14627 | /* 40431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14628 | /* 40434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14629 | /* 40440 */ GIR_RootConstrainSelectedInstOperands, |
| 14630 | /* 40441 */ // GIR_Coverage, 696, |
| 14631 | /* 40441 */ GIR_EraseRootFromParent_Done, |
| 14632 | /* 40442 */ // Label 913: @40442 |
| 14633 | /* 40442 */ GIM_Reject, |
| 14634 | /* 40443 */ // Label 906: @40443 |
| 14635 | /* 40443 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(40469), // Rule ID 1877 // |
| 14636 | /* 40448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14637 | /* 40451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 14638 | /* 40454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14639 | /* 40458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14640 | /* 40462 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14641 | /* 40462 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf), |
| 14642 | /* 40467 */ GIR_RootConstrainSelectedInstOperands, |
| 14643 | /* 40468 */ // GIR_Coverage, 1877, |
| 14644 | /* 40468 */ GIR_Done, |
| 14645 | /* 40469 */ // Label 914: @40469 |
| 14646 | /* 40469 */ GIM_Reject, |
| 14647 | /* 40470 */ // Label 907: @40470 |
| 14648 | /* 40470 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(40496), // Rule ID 1881 // |
| 14649 | /* 40475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14650 | /* 40478 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 14651 | /* 40481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14652 | /* 40485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14653 | /* 40489 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14654 | /* 40489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh), |
| 14655 | /* 40494 */ GIR_RootConstrainSelectedInstOperands, |
| 14656 | /* 40495 */ // GIR_Coverage, 1881, |
| 14657 | /* 40495 */ GIR_Done, |
| 14658 | /* 40496 */ // Label 915: @40496 |
| 14659 | /* 40496 */ GIM_Reject, |
| 14660 | /* 40497 */ // Label 908: @40497 |
| 14661 | /* 40497 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(40584), |
| 14662 | /* 40502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14663 | /* 40505 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(40528), // Rule ID 1879 // |
| 14664 | /* 40510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14665 | /* 40513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14666 | /* 40517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14667 | /* 40521 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14668 | /* 40521 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf), |
| 14669 | /* 40526 */ GIR_RootConstrainSelectedInstOperands, |
| 14670 | /* 40527 */ // GIR_Coverage, 1879, |
| 14671 | /* 40527 */ GIR_Done, |
| 14672 | /* 40528 */ // Label 917: @40528 |
| 14673 | /* 40528 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(40583), // Rule ID 4383 // |
| 14674 | /* 40533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14675 | /* 40536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14676 | /* 40540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14677 | /* 40544 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 14678 | /* 40544 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14679 | /* 40547 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14680 | /* 40551 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14681 | /* 40556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 14682 | /* 40559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14683 | /* 40561 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14684 | /* 40563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14685 | /* 40566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14686 | /* 40572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14687 | /* 40578 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14688 | /* 40581 */ GIR_RootConstrainSelectedInstOperands, |
| 14689 | /* 40582 */ // GIR_Coverage, 4383, |
| 14690 | /* 40582 */ GIR_EraseRootFromParent_Done, |
| 14691 | /* 40583 */ // Label 918: @40583 |
| 14692 | /* 40583 */ GIM_Reject, |
| 14693 | /* 40584 */ // Label 916: @40584 |
| 14694 | /* 40584 */ GIM_Reject, |
| 14695 | /* 40585 */ // Label 909: @40585 |
| 14696 | /* 40585 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(40672), |
| 14697 | /* 40590 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14698 | /* 40593 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(40616), // Rule ID 1883 // |
| 14699 | /* 40598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14700 | /* 40601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14701 | /* 40605 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14702 | /* 40609 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14703 | /* 40609 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh), |
| 14704 | /* 40614 */ GIR_RootConstrainSelectedInstOperands, |
| 14705 | /* 40615 */ // GIR_Coverage, 1883, |
| 14706 | /* 40615 */ GIR_Done, |
| 14707 | /* 40616 */ // Label 920: @40616 |
| 14708 | /* 40616 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(40671), // Rule ID 4359 // |
| 14709 | /* 40621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14710 | /* 40624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14711 | /* 40628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14712 | /* 40632 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 14713 | /* 40632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14714 | /* 40635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14715 | /* 40639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14716 | /* 40644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 14717 | /* 40647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14718 | /* 40649 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14719 | /* 40651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14720 | /* 40654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14721 | /* 40660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14722 | /* 40666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14723 | /* 40669 */ GIR_RootConstrainSelectedInstOperands, |
| 14724 | /* 40670 */ // GIR_Coverage, 4359, |
| 14725 | /* 40670 */ GIR_EraseRootFromParent_Done, |
| 14726 | /* 40671 */ // Label 921: @40671 |
| 14727 | /* 40671 */ GIM_Reject, |
| 14728 | /* 40672 */ // Label 919: @40672 |
| 14729 | /* 40672 */ GIM_Reject, |
| 14730 | /* 40673 */ // Label 910: @40673 |
| 14731 | /* 40673 */ GIM_Reject, |
| 14732 | /* 40674 */ // Label 17: @40674 |
| 14733 | /* 40674 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 929*/ GIMT_Encode4(41048), |
| 14734 | /* 40685 */ /*GILLT_s16*//*Label 922*/ GIMT_Encode4(40737), |
| 14735 | /* 40689 */ /*GILLT_s32*//*Label 923*/ GIMT_Encode4(40764), |
| 14736 | /* 40693 */ /*GILLT_s64*//*Label 924*/ GIMT_Encode4(40791), GIMT_Encode4(0), |
| 14737 | /* 40701 */ /*GILLT_v2s32*//*Label 925*/ GIMT_Encode4(40818), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14738 | /* 40713 */ /*GILLT_v4s16*//*Label 926*/ GIMT_Encode4(40845), |
| 14739 | /* 40717 */ /*GILLT_v4s32*//*Label 927*/ GIMT_Encode4(40872), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14740 | /* 40733 */ /*GILLT_v8s16*//*Label 928*/ GIMT_Encode4(40960), |
| 14741 | /* 40737 */ // Label 922: @40737 |
| 14742 | /* 40737 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(40763), // Rule ID 710 // |
| 14743 | /* 40742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 14744 | /* 40745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 14745 | /* 40748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 14746 | /* 40752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 14747 | /* 40756 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 14748 | /* 40756 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH), |
| 14749 | /* 40761 */ GIR_RootConstrainSelectedInstOperands, |
| 14750 | /* 40762 */ // GIR_Coverage, 710, |
| 14751 | /* 40762 */ GIR_Done, |
| 14752 | /* 40763 */ // Label 930: @40763 |
| 14753 | /* 40763 */ GIM_Reject, |
| 14754 | /* 40764 */ // Label 923: @40764 |
| 14755 | /* 40764 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(40790), // Rule ID 712 // |
| 14756 | /* 40769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 14757 | /* 40772 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14758 | /* 40775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14759 | /* 40779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14760 | /* 40783 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 14761 | /* 40783 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS), |
| 14762 | /* 40788 */ GIR_RootConstrainSelectedInstOperands, |
| 14763 | /* 40789 */ // GIR_Coverage, 712, |
| 14764 | /* 40789 */ GIR_Done, |
| 14765 | /* 40790 */ // Label 931: @40790 |
| 14766 | /* 40790 */ GIM_Reject, |
| 14767 | /* 40791 */ // Label 924: @40791 |
| 14768 | /* 40791 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(40817), // Rule ID 714 // |
| 14769 | /* 40796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 14770 | /* 40799 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14771 | /* 40802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14772 | /* 40806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14773 | /* 40810 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 14774 | /* 40810 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD), |
| 14775 | /* 40815 */ GIR_RootConstrainSelectedInstOperands, |
| 14776 | /* 40816 */ // GIR_Coverage, 714, |
| 14777 | /* 40816 */ GIR_Done, |
| 14778 | /* 40817 */ // Label 932: @40817 |
| 14779 | /* 40817 */ GIM_Reject, |
| 14780 | /* 40818 */ // Label 925: @40818 |
| 14781 | /* 40818 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(40844), // Rule ID 1869 // |
| 14782 | /* 40823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14783 | /* 40826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 14784 | /* 40829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14785 | /* 40833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14786 | /* 40837 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14787 | /* 40837 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf), |
| 14788 | /* 40842 */ GIR_RootConstrainSelectedInstOperands, |
| 14789 | /* 40843 */ // GIR_Coverage, 1869, |
| 14790 | /* 40843 */ GIR_Done, |
| 14791 | /* 40844 */ // Label 933: @40844 |
| 14792 | /* 40844 */ GIM_Reject, |
| 14793 | /* 40845 */ // Label 926: @40845 |
| 14794 | /* 40845 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(40871), // Rule ID 1873 // |
| 14795 | /* 40850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14796 | /* 40853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 14797 | /* 40856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14798 | /* 40860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14799 | /* 40864 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14800 | /* 40864 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh), |
| 14801 | /* 40869 */ GIR_RootConstrainSelectedInstOperands, |
| 14802 | /* 40870 */ // GIR_Coverage, 1873, |
| 14803 | /* 40870 */ GIR_Done, |
| 14804 | /* 40871 */ // Label 934: @40871 |
| 14805 | /* 40871 */ GIM_Reject, |
| 14806 | /* 40872 */ // Label 927: @40872 |
| 14807 | /* 40872 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(40959), |
| 14808 | /* 40877 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14809 | /* 40880 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(40903), // Rule ID 1871 // |
| 14810 | /* 40885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14811 | /* 40888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14812 | /* 40892 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14813 | /* 40896 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14814 | /* 40896 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf), |
| 14815 | /* 40901 */ GIR_RootConstrainSelectedInstOperands, |
| 14816 | /* 40902 */ // GIR_Coverage, 1871, |
| 14817 | /* 40902 */ GIR_Done, |
| 14818 | /* 40903 */ // Label 936: @40903 |
| 14819 | /* 40903 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(40958), // Rule ID 4379 // |
| 14820 | /* 40908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14821 | /* 40911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14822 | /* 40915 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14823 | /* 40919 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 14824 | /* 40919 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14825 | /* 40922 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14826 | /* 40926 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14827 | /* 40931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 14828 | /* 40934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14829 | /* 40936 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14830 | /* 40938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14831 | /* 40941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14832 | /* 40947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14833 | /* 40953 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14834 | /* 40956 */ GIR_RootConstrainSelectedInstOperands, |
| 14835 | /* 40957 */ // GIR_Coverage, 4379, |
| 14836 | /* 40957 */ GIR_EraseRootFromParent_Done, |
| 14837 | /* 40958 */ // Label 937: @40958 |
| 14838 | /* 40958 */ GIM_Reject, |
| 14839 | /* 40959 */ // Label 935: @40959 |
| 14840 | /* 40959 */ GIM_Reject, |
| 14841 | /* 40960 */ // Label 928: @40960 |
| 14842 | /* 40960 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(41047), |
| 14843 | /* 40965 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14844 | /* 40968 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(40991), // Rule ID 1875 // |
| 14845 | /* 40973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14846 | /* 40976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14847 | /* 40980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14848 | /* 40984 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14849 | /* 40984 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh), |
| 14850 | /* 40989 */ GIR_RootConstrainSelectedInstOperands, |
| 14851 | /* 40990 */ // GIR_Coverage, 1875, |
| 14852 | /* 40990 */ GIR_Done, |
| 14853 | /* 40991 */ // Label 939: @40991 |
| 14854 | /* 40991 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(41046), // Rule ID 4355 // |
| 14855 | /* 40996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14856 | /* 40999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14857 | /* 41003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14858 | /* 41007 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 14859 | /* 41007 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14860 | /* 41010 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14861 | /* 41014 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14862 | /* 41019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 14863 | /* 41022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14864 | /* 41024 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14865 | /* 41026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14866 | /* 41029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14867 | /* 41035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14868 | /* 41041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14869 | /* 41044 */ GIR_RootConstrainSelectedInstOperands, |
| 14870 | /* 41045 */ // GIR_Coverage, 4355, |
| 14871 | /* 41045 */ GIR_EraseRootFromParent_Done, |
| 14872 | /* 41046 */ // Label 940: @41046 |
| 14873 | /* 41046 */ GIM_Reject, |
| 14874 | /* 41047 */ // Label 938: @41047 |
| 14875 | /* 41047 */ GIM_Reject, |
| 14876 | /* 41048 */ // Label 929: @41048 |
| 14877 | /* 41048 */ GIM_Reject, |
| 14878 | /* 41049 */ // Label 18: @41049 |
| 14879 | /* 41049 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 948*/ GIMT_Encode4(41423), |
| 14880 | /* 41060 */ /*GILLT_s16*//*Label 941*/ GIMT_Encode4(41112), |
| 14881 | /* 41064 */ /*GILLT_s32*//*Label 942*/ GIMT_Encode4(41139), |
| 14882 | /* 41068 */ /*GILLT_s64*//*Label 943*/ GIMT_Encode4(41166), GIMT_Encode4(0), |
| 14883 | /* 41076 */ /*GILLT_v2s32*//*Label 944*/ GIMT_Encode4(41193), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14884 | /* 41088 */ /*GILLT_v4s16*//*Label 945*/ GIMT_Encode4(41220), |
| 14885 | /* 41092 */ /*GILLT_v4s32*//*Label 946*/ GIMT_Encode4(41247), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14886 | /* 41108 */ /*GILLT_v8s16*//*Label 947*/ GIMT_Encode4(41335), |
| 14887 | /* 41112 */ // Label 941: @41112 |
| 14888 | /* 41112 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(41138), // Rule ID 716 // |
| 14889 | /* 41117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 14890 | /* 41120 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 14891 | /* 41123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 14892 | /* 41127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 14893 | /* 41131 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 14894 | /* 41131 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH), |
| 14895 | /* 41136 */ GIR_RootConstrainSelectedInstOperands, |
| 14896 | /* 41137 */ // GIR_Coverage, 716, |
| 14897 | /* 41137 */ GIR_Done, |
| 14898 | /* 41138 */ // Label 949: @41138 |
| 14899 | /* 41138 */ GIM_Reject, |
| 14900 | /* 41139 */ // Label 942: @41139 |
| 14901 | /* 41139 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(41165), // Rule ID 718 // |
| 14902 | /* 41144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 14903 | /* 41147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14904 | /* 41150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14905 | /* 41154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14906 | /* 41158 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 14907 | /* 41158 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS), |
| 14908 | /* 41163 */ GIR_RootConstrainSelectedInstOperands, |
| 14909 | /* 41164 */ // GIR_Coverage, 718, |
| 14910 | /* 41164 */ GIR_Done, |
| 14911 | /* 41165 */ // Label 950: @41165 |
| 14912 | /* 41165 */ GIM_Reject, |
| 14913 | /* 41166 */ // Label 943: @41166 |
| 14914 | /* 41166 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(41192), // Rule ID 720 // |
| 14915 | /* 41171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 14916 | /* 41174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14917 | /* 41177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14918 | /* 41181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14919 | /* 41185 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 14920 | /* 41185 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND), |
| 14921 | /* 41190 */ GIR_RootConstrainSelectedInstOperands, |
| 14922 | /* 41191 */ // GIR_Coverage, 720, |
| 14923 | /* 41191 */ GIR_Done, |
| 14924 | /* 41192 */ // Label 951: @41192 |
| 14925 | /* 41192 */ GIM_Reject, |
| 14926 | /* 41193 */ // Label 944: @41193 |
| 14927 | /* 41193 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(41219), // Rule ID 1853 // |
| 14928 | /* 41198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14929 | /* 41201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 14930 | /* 41204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14931 | /* 41208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14932 | /* 41212 */ // (froundeven:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14933 | /* 41212 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf), |
| 14934 | /* 41217 */ GIR_RootConstrainSelectedInstOperands, |
| 14935 | /* 41218 */ // GIR_Coverage, 1853, |
| 14936 | /* 41218 */ GIR_Done, |
| 14937 | /* 41219 */ // Label 952: @41219 |
| 14938 | /* 41219 */ GIM_Reject, |
| 14939 | /* 41220 */ // Label 945: @41220 |
| 14940 | /* 41220 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(41246), // Rule ID 1857 // |
| 14941 | /* 41225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14942 | /* 41228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 14943 | /* 41231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14944 | /* 41235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14945 | /* 41239 */ // (froundeven:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14946 | /* 41239 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh), |
| 14947 | /* 41244 */ GIR_RootConstrainSelectedInstOperands, |
| 14948 | /* 41245 */ // GIR_Coverage, 1857, |
| 14949 | /* 41245 */ GIR_Done, |
| 14950 | /* 41246 */ // Label 953: @41246 |
| 14951 | /* 41246 */ GIM_Reject, |
| 14952 | /* 41247 */ // Label 946: @41247 |
| 14953 | /* 41247 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(41334), |
| 14954 | /* 41252 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14955 | /* 41255 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(41278), // Rule ID 1855 // |
| 14956 | /* 41260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14957 | /* 41263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14958 | /* 41267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14959 | /* 41271 */ // (froundeven:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14960 | /* 41271 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf), |
| 14961 | /* 41276 */ GIR_RootConstrainSelectedInstOperands, |
| 14962 | /* 41277 */ // GIR_Coverage, 1855, |
| 14963 | /* 41277 */ GIR_Done, |
| 14964 | /* 41278 */ // Label 955: @41278 |
| 14965 | /* 41278 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(41333), // Rule ID 4371 // |
| 14966 | /* 41283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14967 | /* 41286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14968 | /* 41290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14969 | /* 41294 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 14970 | /* 41294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14971 | /* 41297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14972 | /* 41301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14973 | /* 41306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 14974 | /* 41309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14975 | /* 41311 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14976 | /* 41313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14977 | /* 41316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14978 | /* 41322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14979 | /* 41328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14980 | /* 41331 */ GIR_RootConstrainSelectedInstOperands, |
| 14981 | /* 41332 */ // GIR_Coverage, 4371, |
| 14982 | /* 41332 */ GIR_EraseRootFromParent_Done, |
| 14983 | /* 41333 */ // Label 956: @41333 |
| 14984 | /* 41333 */ GIM_Reject, |
| 14985 | /* 41334 */ // Label 954: @41334 |
| 14986 | /* 41334 */ GIM_Reject, |
| 14987 | /* 41335 */ // Label 947: @41335 |
| 14988 | /* 41335 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(41422), |
| 14989 | /* 41340 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14990 | /* 41343 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(41366), // Rule ID 1859 // |
| 14991 | /* 41348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14992 | /* 41351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14993 | /* 41355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14994 | /* 41359 */ // (froundeven:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14995 | /* 41359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh), |
| 14996 | /* 41364 */ GIR_RootConstrainSelectedInstOperands, |
| 14997 | /* 41365 */ // GIR_Coverage, 1859, |
| 14998 | /* 41365 */ GIR_Done, |
| 14999 | /* 41366 */ // Label 958: @41366 |
| 15000 | /* 41366 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(41421), // Rule ID 4347 // |
| 15001 | /* 41371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15002 | /* 41374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15003 | /* 41378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15004 | /* 41382 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15005 | /* 41382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15006 | /* 41385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15007 | /* 41389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15008 | /* 41394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 15009 | /* 41397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15010 | /* 41399 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 15011 | /* 41401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15012 | /* 41404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15013 | /* 41410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15014 | /* 41416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15015 | /* 41419 */ GIR_RootConstrainSelectedInstOperands, |
| 15016 | /* 41420 */ // GIR_Coverage, 4347, |
| 15017 | /* 41420 */ GIR_EraseRootFromParent_Done, |
| 15018 | /* 41421 */ // Label 959: @41421 |
| 15019 | /* 41421 */ GIM_Reject, |
| 15020 | /* 41422 */ // Label 957: @41422 |
| 15021 | /* 41422 */ GIM_Reject, |
| 15022 | /* 41423 */ // Label 948: @41423 |
| 15023 | /* 41423 */ GIM_Reject, |
| 15024 | /* 41424 */ // Label 19: @41424 |
| 15025 | /* 41424 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(41586), |
| 15026 | /* 41429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15027 | /* 41432 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15028 | /* 41435 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(41510), // Rule ID 2238 // |
| 15029 | /* 41440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 15030 | /* 41443 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 15031 | /* 41450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 15032 | /* 41454 */ // MIs[0] Rn |
| 15033 | /* 41454 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 15034 | /* 41458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 15035 | /* 41462 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 15036 | /* 41462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15037 | /* 41465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 15038 | /* 41469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15039 | /* 41474 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 15040 | /* 41480 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 15041 | /* 41483 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 15042 | /* 41486 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15043 | /* 41492 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15044 | /* 41494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB), |
| 15045 | /* 41497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 15046 | /* 41499 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 15047 | /* 41501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15048 | /* 41504 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15049 | /* 41508 */ GIR_RootConstrainSelectedInstOperands, |
| 15050 | /* 41509 */ // GIR_Coverage, 2238, |
| 15051 | /* 41509 */ GIR_EraseRootFromParent_Done, |
| 15052 | /* 41510 */ // Label 961: @41510 |
| 15053 | /* 41510 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(41585), // Rule ID 2239 // |
| 15054 | /* 41515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 15055 | /* 41518 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 15056 | /* 41525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 15057 | /* 41529 */ // MIs[0] Rn |
| 15058 | /* 41529 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 15059 | /* 41533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 15060 | /* 41537 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 15061 | /* 41537 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15062 | /* 41540 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 15063 | /* 41544 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15064 | /* 41549 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 15065 | /* 41555 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 15066 | /* 41558 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 15067 | /* 41561 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15068 | /* 41567 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15069 | /* 41569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH), |
| 15070 | /* 41572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 15071 | /* 41574 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 15072 | /* 41576 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15073 | /* 41579 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15074 | /* 41583 */ GIR_RootConstrainSelectedInstOperands, |
| 15075 | /* 41584 */ // GIR_Coverage, 2239, |
| 15076 | /* 41584 */ GIR_EraseRootFromParent_Done, |
| 15077 | /* 41585 */ // Label 962: @41585 |
| 15078 | /* 41585 */ GIM_Reject, |
| 15079 | /* 41586 */ // Label 960: @41586 |
| 15080 | /* 41586 */ GIM_Reject, |
| 15081 | /* 41587 */ // Label 20: @41587 |
| 15082 | /* 41587 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(41607), // Rule ID 5935 // |
| 15083 | /* 41592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 15084 | /* 41595 */ // MIs[0] Operand 0 |
| 15085 | /* 41595 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 15086 | /* 41598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 15087 | /* 41602 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER) |
| 15088 | /* 41602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER), |
| 15089 | /* 41605 */ GIR_RootConstrainSelectedInstOperands, |
| 15090 | /* 41606 */ // GIR_Coverage, 5935, |
| 15091 | /* 41606 */ GIR_EraseRootFromParent_Done, |
| 15092 | /* 41607 */ // Label 963: @41607 |
| 15093 | /* 41607 */ GIM_Reject, |
| 15094 | /* 41608 */ // Label 21: @41608 |
| 15095 | /* 41608 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(46662), |
| 15096 | /* 41613 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 15097 | /* 41616 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(41664), // Rule ID 2041 // |
| 15098 | /* 41621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 15099 | /* 41624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 15100 | /* 41629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15101 | /* 41632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15102 | /* 41635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15103 | /* 41639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 15104 | /* 41643 */ // (intrinsic_wo_chain:{ *:[i32] } 4197:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 15105 | /* 41643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 15106 | /* 41646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15107 | /* 41648 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 15108 | /* 41650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15109 | /* 41653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15110 | /* 41656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15111 | /* 41662 */ GIR_RootConstrainSelectedInstOperands, |
| 15112 | /* 41663 */ // GIR_Coverage, 2041, |
| 15113 | /* 41663 */ GIR_EraseRootFromParent_Done, |
| 15114 | /* 41664 */ // Label 965: @41664 |
| 15115 | /* 41664 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(41712), // Rule ID 2295 // |
| 15116 | /* 41669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 15117 | /* 41672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 15118 | /* 41677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15119 | /* 41680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15120 | /* 41683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15121 | /* 41687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15122 | /* 41691 */ // (intrinsic_wo_chain:{ *:[i32] } 4197:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 15123 | /* 41691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 15124 | /* 41694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15125 | /* 41696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 15126 | /* 41698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15127 | /* 41701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15128 | /* 41704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15129 | /* 41710 */ GIR_RootConstrainSelectedInstOperands, |
| 15130 | /* 41711 */ // GIR_Coverage, 2295, |
| 15131 | /* 41711 */ GIR_EraseRootFromParent_Done, |
| 15132 | /* 41712 */ // Label 966: @41712 |
| 15133 | /* 41712 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(41757), // Rule ID 743 // |
| 15134 | /* 41717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 15135 | /* 41720 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 15136 | /* 41725 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15137 | /* 41728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 15138 | /* 41731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 15139 | /* 41735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15140 | /* 41739 */ // (intrinsic_wo_chain:{ *:[f32] } 4198:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 15141 | /* 41739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD), |
| 15142 | /* 41742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 15143 | /* 41744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 15144 | /* 41746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15145 | /* 41749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15146 | /* 41755 */ GIR_RootConstrainSelectedInstOperands, |
| 15147 | /* 41756 */ // GIR_Coverage, 743, |
| 15148 | /* 41756 */ GIR_EraseRootFromParent_Done, |
| 15149 | /* 41757 */ // Label 967: @41757 |
| 15150 | /* 41757 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(41802), // Rule ID 744 // |
| 15151 | /* 41762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 15152 | /* 41765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 15153 | /* 41770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15154 | /* 41773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15155 | /* 41776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 15156 | /* 41780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 15157 | /* 41784 */ // (intrinsic_wo_chain:{ *:[f32] } 4198:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 15158 | /* 41784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS), |
| 15159 | /* 41787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 15160 | /* 41789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 15161 | /* 41791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15162 | /* 41794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15163 | /* 41800 */ GIR_RootConstrainSelectedInstOperands, |
| 15164 | /* 41801 */ // GIR_Coverage, 744, |
| 15165 | /* 41801 */ GIR_EraseRootFromParent_Done, |
| 15166 | /* 41802 */ // Label 968: @41802 |
| 15167 | /* 41802 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(41847), // Rule ID 745 // |
| 15168 | /* 41807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 15169 | /* 41810 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 15170 | /* 41815 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15171 | /* 41818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 15172 | /* 41821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 15173 | /* 41825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15174 | /* 41829 */ // (intrinsic_wo_chain:{ *:[f32] } 4199:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 15175 | /* 41829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD), |
| 15176 | /* 41832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 15177 | /* 41834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 15178 | /* 41836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15179 | /* 41839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15180 | /* 41845 */ GIR_RootConstrainSelectedInstOperands, |
| 15181 | /* 41846 */ // GIR_Coverage, 745, |
| 15182 | /* 41846 */ GIR_EraseRootFromParent_Done, |
| 15183 | /* 41847 */ // Label 969: @41847 |
| 15184 | /* 41847 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(41892), // Rule ID 746 // |
| 15185 | /* 41852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 15186 | /* 41855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 15187 | /* 41860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15188 | /* 41863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15189 | /* 41866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 15190 | /* 41870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 15191 | /* 41874 */ // (intrinsic_wo_chain:{ *:[f32] } 4199:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 15192 | /* 41874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS), |
| 15193 | /* 41877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 15194 | /* 41879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 15195 | /* 41881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15196 | /* 41884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15197 | /* 41890 */ GIR_RootConstrainSelectedInstOperands, |
| 15198 | /* 41891 */ // GIR_Coverage, 746, |
| 15199 | /* 41891 */ GIR_EraseRootFromParent_Done, |
| 15200 | /* 41892 */ // Label 970: @41892 |
| 15201 | /* 41892 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(41937), // Rule ID 1403 // |
| 15202 | /* 41897 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15203 | /* 41900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 15204 | /* 41905 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15205 | /* 41908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 15206 | /* 41911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15207 | /* 41915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15208 | /* 41919 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4055:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 15209 | /* 41919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8), |
| 15210 | /* 41922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15211 | /* 41924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15212 | /* 41926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15213 | /* 41929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15214 | /* 41935 */ GIR_RootConstrainSelectedInstOperands, |
| 15215 | /* 41936 */ // GIR_Coverage, 1403, |
| 15216 | /* 41936 */ GIR_EraseRootFromParent_Done, |
| 15217 | /* 41937 */ // Label 971: @41937 |
| 15218 | /* 41937 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(41982), // Rule ID 1404 // |
| 15219 | /* 41942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15220 | /* 41945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 15221 | /* 41950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15222 | /* 41953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15223 | /* 41956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15224 | /* 41960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15225 | /* 41964 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4055:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 15226 | /* 41964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16), |
| 15227 | /* 41967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15228 | /* 41969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15229 | /* 41971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15230 | /* 41974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15231 | /* 41980 */ GIR_RootConstrainSelectedInstOperands, |
| 15232 | /* 41981 */ // GIR_Coverage, 1404, |
| 15233 | /* 41981 */ GIR_EraseRootFromParent_Done, |
| 15234 | /* 41982 */ // Label 972: @41982 |
| 15235 | /* 41982 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(42027), // Rule ID 1405 // |
| 15236 | /* 41987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15237 | /* 41990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 15238 | /* 41995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 15239 | /* 41998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15240 | /* 42001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15241 | /* 42005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15242 | /* 42009 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4055:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 15243 | /* 42009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32), |
| 15244 | /* 42012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15245 | /* 42014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15246 | /* 42016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15247 | /* 42019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15248 | /* 42025 */ GIR_RootConstrainSelectedInstOperands, |
| 15249 | /* 42026 */ // GIR_Coverage, 1405, |
| 15250 | /* 42026 */ GIR_EraseRootFromParent_Done, |
| 15251 | /* 42027 */ // Label 973: @42027 |
| 15252 | /* 42027 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(42072), // Rule ID 1406 // |
| 15253 | /* 42032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15254 | /* 42035 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 15255 | /* 42040 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15256 | /* 42043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15257 | /* 42046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15258 | /* 42050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15259 | /* 42054 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4055:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 15260 | /* 42054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8), |
| 15261 | /* 42057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15262 | /* 42059 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15263 | /* 42061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15264 | /* 42064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15265 | /* 42070 */ GIR_RootConstrainSelectedInstOperands, |
| 15266 | /* 42071 */ // GIR_Coverage, 1406, |
| 15267 | /* 42071 */ GIR_EraseRootFromParent_Done, |
| 15268 | /* 42072 */ // Label 974: @42072 |
| 15269 | /* 42072 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(42117), // Rule ID 1407 // |
| 15270 | /* 42077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15271 | /* 42080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 15272 | /* 42085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15273 | /* 42088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15274 | /* 42091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15275 | /* 42095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15276 | /* 42099 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4055:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 15277 | /* 42099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16), |
| 15278 | /* 42102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15279 | /* 42104 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15280 | /* 42106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15281 | /* 42109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15282 | /* 42115 */ GIR_RootConstrainSelectedInstOperands, |
| 15283 | /* 42116 */ // GIR_Coverage, 1407, |
| 15284 | /* 42116 */ GIR_EraseRootFromParent_Done, |
| 15285 | /* 42117 */ // Label 975: @42117 |
| 15286 | /* 42117 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(42162), // Rule ID 1408 // |
| 15287 | /* 42122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15288 | /* 42125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 15289 | /* 42130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 15290 | /* 42133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15291 | /* 42136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15292 | /* 42140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15293 | /* 42144 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4055:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 15294 | /* 42144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32), |
| 15295 | /* 42147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15296 | /* 42149 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15297 | /* 42151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15298 | /* 42154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15299 | /* 42160 */ GIR_RootConstrainSelectedInstOperands, |
| 15300 | /* 42161 */ // GIR_Coverage, 1408, |
| 15301 | /* 42161 */ GIR_EraseRootFromParent_Done, |
| 15302 | /* 42162 */ // Label 976: @42162 |
| 15303 | /* 42162 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(42207), // Rule ID 1409 // |
| 15304 | /* 42167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15305 | /* 42170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 15306 | /* 42175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15307 | /* 42178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 15308 | /* 42181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15309 | /* 42185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15310 | /* 42189 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4056:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 15311 | /* 42189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8), |
| 15312 | /* 42192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15313 | /* 42194 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15314 | /* 42196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15315 | /* 42199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15316 | /* 42205 */ GIR_RootConstrainSelectedInstOperands, |
| 15317 | /* 42206 */ // GIR_Coverage, 1409, |
| 15318 | /* 42206 */ GIR_EraseRootFromParent_Done, |
| 15319 | /* 42207 */ // Label 977: @42207 |
| 15320 | /* 42207 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(42252), // Rule ID 1410 // |
| 15321 | /* 42212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15322 | /* 42215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 15323 | /* 42220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15324 | /* 42223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15325 | /* 42226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15326 | /* 42230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15327 | /* 42234 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4056:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 15328 | /* 42234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16), |
| 15329 | /* 42237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15330 | /* 42239 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15331 | /* 42241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15332 | /* 42244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15333 | /* 42250 */ GIR_RootConstrainSelectedInstOperands, |
| 15334 | /* 42251 */ // GIR_Coverage, 1410, |
| 15335 | /* 42251 */ GIR_EraseRootFromParent_Done, |
| 15336 | /* 42252 */ // Label 978: @42252 |
| 15337 | /* 42252 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(42297), // Rule ID 1411 // |
| 15338 | /* 42257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15339 | /* 42260 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 15340 | /* 42265 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 15341 | /* 42268 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15342 | /* 42271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15343 | /* 42275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15344 | /* 42279 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4056:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 15345 | /* 42279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32), |
| 15346 | /* 42282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15347 | /* 42284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15348 | /* 42286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15349 | /* 42289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15350 | /* 42295 */ GIR_RootConstrainSelectedInstOperands, |
| 15351 | /* 42296 */ // GIR_Coverage, 1411, |
| 15352 | /* 42296 */ GIR_EraseRootFromParent_Done, |
| 15353 | /* 42297 */ // Label 979: @42297 |
| 15354 | /* 42297 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(42342), // Rule ID 1412 // |
| 15355 | /* 42302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15356 | /* 42305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 15357 | /* 42310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15358 | /* 42313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15359 | /* 42316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15360 | /* 42320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15361 | /* 42324 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4056:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 15362 | /* 42324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8), |
| 15363 | /* 42327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15364 | /* 42329 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15365 | /* 42331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15366 | /* 42334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15367 | /* 42340 */ GIR_RootConstrainSelectedInstOperands, |
| 15368 | /* 42341 */ // GIR_Coverage, 1412, |
| 15369 | /* 42341 */ GIR_EraseRootFromParent_Done, |
| 15370 | /* 42342 */ // Label 980: @42342 |
| 15371 | /* 42342 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(42387), // Rule ID 1413 // |
| 15372 | /* 42347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15373 | /* 42350 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 15374 | /* 42355 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15375 | /* 42358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15376 | /* 42361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15377 | /* 42365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15378 | /* 42369 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4056:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 15379 | /* 42369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16), |
| 15380 | /* 42372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15381 | /* 42374 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15382 | /* 42376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15383 | /* 42379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15384 | /* 42385 */ GIR_RootConstrainSelectedInstOperands, |
| 15385 | /* 42386 */ // GIR_Coverage, 1413, |
| 15386 | /* 42386 */ GIR_EraseRootFromParent_Done, |
| 15387 | /* 42387 */ // Label 981: @42387 |
| 15388 | /* 42387 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(42432), // Rule ID 1414 // |
| 15389 | /* 42392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15390 | /* 42395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 15391 | /* 42400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 15392 | /* 42403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15393 | /* 42406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15394 | /* 42410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15395 | /* 42414 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4056:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 15396 | /* 42414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32), |
| 15397 | /* 42417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15398 | /* 42419 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15399 | /* 42421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15400 | /* 42424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15401 | /* 42430 */ GIR_RootConstrainSelectedInstOperands, |
| 15402 | /* 42431 */ // GIR_Coverage, 1414, |
| 15403 | /* 42431 */ GIR_EraseRootFromParent_Done, |
| 15404 | /* 42432 */ // Label 982: @42432 |
| 15405 | /* 42432 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(42477), // Rule ID 1443 // |
| 15406 | /* 42437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15407 | /* 42440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 15408 | /* 42445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15409 | /* 42448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15410 | /* 42451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15411 | /* 42455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15412 | /* 42459 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4083:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 15413 | /* 42459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd), |
| 15414 | /* 42462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15415 | /* 42464 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15416 | /* 42466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15417 | /* 42469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15418 | /* 42475 */ GIR_RootConstrainSelectedInstOperands, |
| 15419 | /* 42476 */ // GIR_Coverage, 1443, |
| 15420 | /* 42476 */ GIR_EraseRootFromParent_Done, |
| 15421 | /* 42477 */ // Label 983: @42477 |
| 15422 | /* 42477 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(42522), // Rule ID 1444 // |
| 15423 | /* 42482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15424 | /* 42485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 15425 | /* 42490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15426 | /* 42493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15427 | /* 42496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15428 | /* 42500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15429 | /* 42504 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4083:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 15430 | /* 42504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq), |
| 15431 | /* 42507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15432 | /* 42509 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15433 | /* 42511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15434 | /* 42514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15435 | /* 42520 */ GIR_RootConstrainSelectedInstOperands, |
| 15436 | /* 42521 */ // GIR_Coverage, 1444, |
| 15437 | /* 42521 */ GIR_EraseRootFromParent_Done, |
| 15438 | /* 42522 */ // Label 984: @42522 |
| 15439 | /* 42522 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(42567), // Rule ID 1445 // |
| 15440 | /* 42527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15441 | /* 42530 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 15442 | /* 42535 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15443 | /* 42538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15444 | /* 42541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15445 | /* 42545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15446 | /* 42549 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4083:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 15447 | /* 42549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd), |
| 15448 | /* 42552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15449 | /* 42554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15450 | /* 42556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15451 | /* 42559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15452 | /* 42565 */ GIR_RootConstrainSelectedInstOperands, |
| 15453 | /* 42566 */ // GIR_Coverage, 1445, |
| 15454 | /* 42566 */ GIR_EraseRootFromParent_Done, |
| 15455 | /* 42567 */ // Label 985: @42567 |
| 15456 | /* 42567 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(42612), // Rule ID 1446 // |
| 15457 | /* 42572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15458 | /* 42575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 15459 | /* 42580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15460 | /* 42583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15461 | /* 42586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15462 | /* 42590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15463 | /* 42594 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4083:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 15464 | /* 42594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq), |
| 15465 | /* 42597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15466 | /* 42599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15467 | /* 42601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15468 | /* 42604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15469 | /* 42610 */ GIR_RootConstrainSelectedInstOperands, |
| 15470 | /* 42611 */ // GIR_Coverage, 1446, |
| 15471 | /* 42611 */ GIR_EraseRootFromParent_Done, |
| 15472 | /* 42612 */ // Label 986: @42612 |
| 15473 | /* 42612 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(42657), // Rule ID 1447 // |
| 15474 | /* 42617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15475 | /* 42620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 15476 | /* 42625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15477 | /* 42628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15478 | /* 42631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15479 | /* 42635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15480 | /* 42639 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4083:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 15481 | /* 42639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd), |
| 15482 | /* 42642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15483 | /* 42644 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15484 | /* 42646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15485 | /* 42649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15486 | /* 42655 */ GIR_RootConstrainSelectedInstOperands, |
| 15487 | /* 42656 */ // GIR_Coverage, 1447, |
| 15488 | /* 42656 */ GIR_EraseRootFromParent_Done, |
| 15489 | /* 42657 */ // Label 987: @42657 |
| 15490 | /* 42657 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(42702), // Rule ID 1448 // |
| 15491 | /* 42662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15492 | /* 42665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 15493 | /* 42670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15494 | /* 42673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15495 | /* 42676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15496 | /* 42680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15497 | /* 42684 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4083:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 15498 | /* 42684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq), |
| 15499 | /* 42687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15500 | /* 42689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15501 | /* 42691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15502 | /* 42694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15503 | /* 42700 */ GIR_RootConstrainSelectedInstOperands, |
| 15504 | /* 42701 */ // GIR_Coverage, 1448, |
| 15505 | /* 42701 */ GIR_EraseRootFromParent_Done, |
| 15506 | /* 42702 */ // Label 988: @42702 |
| 15507 | /* 42702 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(42747), // Rule ID 1453 // |
| 15508 | /* 42707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15509 | /* 42710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 15510 | /* 42715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15511 | /* 42718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15512 | /* 42721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15513 | /* 42725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15514 | /* 42729 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4090:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 15515 | /* 42729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd), |
| 15516 | /* 42732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15517 | /* 42734 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15518 | /* 42736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15519 | /* 42739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15520 | /* 42745 */ GIR_RootConstrainSelectedInstOperands, |
| 15521 | /* 42746 */ // GIR_Coverage, 1453, |
| 15522 | /* 42746 */ GIR_EraseRootFromParent_Done, |
| 15523 | /* 42747 */ // Label 989: @42747 |
| 15524 | /* 42747 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(42792), // Rule ID 1454 // |
| 15525 | /* 42752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15526 | /* 42755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 15527 | /* 42760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15528 | /* 42763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15529 | /* 42766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15530 | /* 42770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15531 | /* 42774 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4090:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 15532 | /* 42774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq), |
| 15533 | /* 42777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15534 | /* 42779 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15535 | /* 42781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15536 | /* 42784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15537 | /* 42790 */ GIR_RootConstrainSelectedInstOperands, |
| 15538 | /* 42791 */ // GIR_Coverage, 1454, |
| 15539 | /* 42791 */ GIR_EraseRootFromParent_Done, |
| 15540 | /* 42792 */ // Label 990: @42792 |
| 15541 | /* 42792 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(42837), // Rule ID 1455 // |
| 15542 | /* 42797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15543 | /* 42800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 15544 | /* 42805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15545 | /* 42808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15546 | /* 42811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15547 | /* 42815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15548 | /* 42819 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4090:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 15549 | /* 42819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd), |
| 15550 | /* 42822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15551 | /* 42824 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15552 | /* 42826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15553 | /* 42829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15554 | /* 42835 */ GIR_RootConstrainSelectedInstOperands, |
| 15555 | /* 42836 */ // GIR_Coverage, 1455, |
| 15556 | /* 42836 */ GIR_EraseRootFromParent_Done, |
| 15557 | /* 42837 */ // Label 991: @42837 |
| 15558 | /* 42837 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(42882), // Rule ID 1456 // |
| 15559 | /* 42842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15560 | /* 42845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 15561 | /* 42850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15562 | /* 42853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15563 | /* 42856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15564 | /* 42860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15565 | /* 42864 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4090:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 15566 | /* 42864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq), |
| 15567 | /* 42867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15568 | /* 42869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15569 | /* 42871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15570 | /* 42874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15571 | /* 42880 */ GIR_RootConstrainSelectedInstOperands, |
| 15572 | /* 42881 */ // GIR_Coverage, 1456, |
| 15573 | /* 42881 */ GIR_EraseRootFromParent_Done, |
| 15574 | /* 42882 */ // Label 992: @42882 |
| 15575 | /* 42882 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(42927), // Rule ID 1457 // |
| 15576 | /* 42887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15577 | /* 42890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 15578 | /* 42895 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15579 | /* 42898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15580 | /* 42901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15581 | /* 42905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15582 | /* 42909 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4090:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 15583 | /* 42909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd), |
| 15584 | /* 42912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15585 | /* 42914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15586 | /* 42916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15587 | /* 42919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15588 | /* 42925 */ GIR_RootConstrainSelectedInstOperands, |
| 15589 | /* 42926 */ // GIR_Coverage, 1457, |
| 15590 | /* 42926 */ GIR_EraseRootFromParent_Done, |
| 15591 | /* 42927 */ // Label 993: @42927 |
| 15592 | /* 42927 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(42972), // Rule ID 1458 // |
| 15593 | /* 42932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15594 | /* 42935 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 15595 | /* 42940 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15596 | /* 42943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15597 | /* 42946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15598 | /* 42950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15599 | /* 42954 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4090:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 15600 | /* 42954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq), |
| 15601 | /* 42957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15602 | /* 42959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15603 | /* 42961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15604 | /* 42964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15605 | /* 42970 */ GIR_RootConstrainSelectedInstOperands, |
| 15606 | /* 42971 */ // GIR_Coverage, 1458, |
| 15607 | /* 42971 */ GIR_EraseRootFromParent_Done, |
| 15608 | /* 42972 */ // Label 994: @42972 |
| 15609 | /* 42972 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(43017), // Rule ID 1679 // |
| 15610 | /* 42977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15611 | /* 42980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 15612 | /* 42985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 15613 | /* 42988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 15614 | /* 42991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15615 | /* 42995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15616 | /* 42999 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4061:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 15617 | /* 42999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8), |
| 15618 | /* 43002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15619 | /* 43004 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15620 | /* 43006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15621 | /* 43009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15622 | /* 43015 */ GIR_RootConstrainSelectedInstOperands, |
| 15623 | /* 43016 */ // GIR_Coverage, 1679, |
| 15624 | /* 43016 */ GIR_EraseRootFromParent_Done, |
| 15625 | /* 43017 */ // Label 995: @43017 |
| 15626 | /* 43017 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(43062), // Rule ID 1680 // |
| 15627 | /* 43022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15628 | /* 43025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 15629 | /* 43030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15630 | /* 43033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15631 | /* 43036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15632 | /* 43040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15633 | /* 43044 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4061:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 15634 | /* 43044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16), |
| 15635 | /* 43047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15636 | /* 43049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15637 | /* 43051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15638 | /* 43054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15639 | /* 43060 */ GIR_RootConstrainSelectedInstOperands, |
| 15640 | /* 43061 */ // GIR_Coverage, 1680, |
| 15641 | /* 43061 */ GIR_EraseRootFromParent_Done, |
| 15642 | /* 43062 */ // Label 996: @43062 |
| 15643 | /* 43062 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(43107), // Rule ID 1681 // |
| 15644 | /* 43067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15645 | /* 43070 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 15646 | /* 43075 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15647 | /* 43078 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15648 | /* 43081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15649 | /* 43085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15650 | /* 43089 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 15651 | /* 43089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32), |
| 15652 | /* 43092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15653 | /* 43094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15654 | /* 43096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15655 | /* 43099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15656 | /* 43105 */ GIR_RootConstrainSelectedInstOperands, |
| 15657 | /* 43106 */ // GIR_Coverage, 1681, |
| 15658 | /* 43106 */ GIR_EraseRootFromParent_Done, |
| 15659 | /* 43107 */ // Label 997: @43107 |
| 15660 | /* 43107 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(43152), // Rule ID 1682 // |
| 15661 | /* 43112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15662 | /* 43115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 15663 | /* 43120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15664 | /* 43123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15665 | /* 43126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15666 | /* 43130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15667 | /* 43134 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4061:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15668 | /* 43134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8), |
| 15669 | /* 43137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15670 | /* 43139 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15671 | /* 43141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15672 | /* 43144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15673 | /* 43150 */ GIR_RootConstrainSelectedInstOperands, |
| 15674 | /* 43151 */ // GIR_Coverage, 1682, |
| 15675 | /* 43151 */ GIR_EraseRootFromParent_Done, |
| 15676 | /* 43152 */ // Label 998: @43152 |
| 15677 | /* 43152 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(43197), // Rule ID 1683 // |
| 15678 | /* 43157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15679 | /* 43160 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 15680 | /* 43165 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15681 | /* 43168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15682 | /* 43171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15683 | /* 43175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15684 | /* 43179 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4061:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 15685 | /* 43179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16), |
| 15686 | /* 43182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15687 | /* 43184 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15688 | /* 43186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15689 | /* 43189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15690 | /* 43195 */ GIR_RootConstrainSelectedInstOperands, |
| 15691 | /* 43196 */ // GIR_Coverage, 1683, |
| 15692 | /* 43196 */ GIR_EraseRootFromParent_Done, |
| 15693 | /* 43197 */ // Label 999: @43197 |
| 15694 | /* 43197 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(43242), // Rule ID 1684 // |
| 15695 | /* 43202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15696 | /* 43205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 15697 | /* 43210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15698 | /* 43213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15699 | /* 43216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15700 | /* 43220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15701 | /* 43224 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4061:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 15702 | /* 43224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32), |
| 15703 | /* 43227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15704 | /* 43229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15705 | /* 43231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15706 | /* 43234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15707 | /* 43240 */ GIR_RootConstrainSelectedInstOperands, |
| 15708 | /* 43241 */ // GIR_Coverage, 1684, |
| 15709 | /* 43241 */ GIR_EraseRootFromParent_Done, |
| 15710 | /* 43242 */ // Label 1000: @43242 |
| 15711 | /* 43242 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(43287), // Rule ID 1695 // |
| 15712 | /* 43247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15713 | /* 43250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 15714 | /* 43255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 15715 | /* 43258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 15716 | /* 43261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15717 | /* 43265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15718 | /* 43269 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4067:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 15719 | /* 43269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8), |
| 15720 | /* 43272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15721 | /* 43274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15722 | /* 43276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15723 | /* 43279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15724 | /* 43285 */ GIR_RootConstrainSelectedInstOperands, |
| 15725 | /* 43286 */ // GIR_Coverage, 1695, |
| 15726 | /* 43286 */ GIR_EraseRootFromParent_Done, |
| 15727 | /* 43287 */ // Label 1001: @43287 |
| 15728 | /* 43287 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(43332), // Rule ID 1696 // |
| 15729 | /* 43292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15730 | /* 43295 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 15731 | /* 43300 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15732 | /* 43303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15733 | /* 43306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15734 | /* 43310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15735 | /* 43314 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 15736 | /* 43314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16), |
| 15737 | /* 43317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15738 | /* 43319 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15739 | /* 43321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15740 | /* 43324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15741 | /* 43330 */ GIR_RootConstrainSelectedInstOperands, |
| 15742 | /* 43331 */ // GIR_Coverage, 1696, |
| 15743 | /* 43331 */ GIR_EraseRootFromParent_Done, |
| 15744 | /* 43332 */ // Label 1002: @43332 |
| 15745 | /* 43332 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(43377), // Rule ID 1697 // |
| 15746 | /* 43337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15747 | /* 43340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 15748 | /* 43345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15749 | /* 43348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15750 | /* 43351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15751 | /* 43355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15752 | /* 43359 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 15753 | /* 43359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32), |
| 15754 | /* 43362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15755 | /* 43364 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15756 | /* 43366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15757 | /* 43369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15758 | /* 43375 */ GIR_RootConstrainSelectedInstOperands, |
| 15759 | /* 43376 */ // GIR_Coverage, 1697, |
| 15760 | /* 43376 */ GIR_EraseRootFromParent_Done, |
| 15761 | /* 43377 */ // Label 1003: @43377 |
| 15762 | /* 43377 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(43422), // Rule ID 1698 // |
| 15763 | /* 43382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15764 | /* 43385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 15765 | /* 43390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15766 | /* 43393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15767 | /* 43396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15768 | /* 43400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15769 | /* 43404 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4067:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15770 | /* 43404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8), |
| 15771 | /* 43407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15772 | /* 43409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15773 | /* 43411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15774 | /* 43414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15775 | /* 43420 */ GIR_RootConstrainSelectedInstOperands, |
| 15776 | /* 43421 */ // GIR_Coverage, 1698, |
| 15777 | /* 43421 */ GIR_EraseRootFromParent_Done, |
| 15778 | /* 43422 */ // Label 1004: @43422 |
| 15779 | /* 43422 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(43467), // Rule ID 1699 // |
| 15780 | /* 43427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15781 | /* 43430 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 15782 | /* 43435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15783 | /* 43438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15784 | /* 43441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15785 | /* 43445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15786 | /* 43449 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4067:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 15787 | /* 43449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16), |
| 15788 | /* 43452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15789 | /* 43454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15790 | /* 43456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15791 | /* 43459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15792 | /* 43465 */ GIR_RootConstrainSelectedInstOperands, |
| 15793 | /* 43466 */ // GIR_Coverage, 1699, |
| 15794 | /* 43466 */ GIR_EraseRootFromParent_Done, |
| 15795 | /* 43467 */ // Label 1005: @43467 |
| 15796 | /* 43467 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(43512), // Rule ID 1700 // |
| 15797 | /* 43472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15798 | /* 43475 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 15799 | /* 43480 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15800 | /* 43483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15801 | /* 43486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15802 | /* 43490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15803 | /* 43494 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 15804 | /* 43494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32), |
| 15805 | /* 43497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15806 | /* 43499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15807 | /* 43501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15808 | /* 43504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15809 | /* 43510 */ GIR_RootConstrainSelectedInstOperands, |
| 15810 | /* 43511 */ // GIR_Coverage, 1700, |
| 15811 | /* 43511 */ GIR_EraseRootFromParent_Done, |
| 15812 | /* 43512 */ // Label 1006: @43512 |
| 15813 | /* 43512 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(43557), // Rule ID 1750 // |
| 15814 | /* 43517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15815 | /* 43520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 15816 | /* 43525 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 15817 | /* 43528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15818 | /* 43531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15819 | /* 43535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15820 | /* 43539 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4064:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 15821 | /* 43539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8), |
| 15822 | /* 43542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15823 | /* 43544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15824 | /* 43546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15825 | /* 43549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15826 | /* 43555 */ GIR_RootConstrainSelectedInstOperands, |
| 15827 | /* 43556 */ // GIR_Coverage, 1750, |
| 15828 | /* 43556 */ GIR_EraseRootFromParent_Done, |
| 15829 | /* 43557 */ // Label 1007: @43557 |
| 15830 | /* 43557 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(43602), // Rule ID 1751 // |
| 15831 | /* 43562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15832 | /* 43565 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 15833 | /* 43570 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15834 | /* 43573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15835 | /* 43576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15836 | /* 43580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15837 | /* 43584 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4064:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 15838 | /* 43584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16), |
| 15839 | /* 43587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15840 | /* 43589 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15841 | /* 43591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15842 | /* 43594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15843 | /* 43600 */ GIR_RootConstrainSelectedInstOperands, |
| 15844 | /* 43601 */ // GIR_Coverage, 1751, |
| 15845 | /* 43601 */ GIR_EraseRootFromParent_Done, |
| 15846 | /* 43602 */ // Label 1008: @43602 |
| 15847 | /* 43602 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(43647), // Rule ID 1752 // |
| 15848 | /* 43607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15849 | /* 43610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 15850 | /* 43615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15851 | /* 43618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15852 | /* 43621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15853 | /* 43625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15854 | /* 43629 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4064:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 15855 | /* 43629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32), |
| 15856 | /* 43632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15857 | /* 43634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15858 | /* 43636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15859 | /* 43639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15860 | /* 43645 */ GIR_RootConstrainSelectedInstOperands, |
| 15861 | /* 43646 */ // GIR_Coverage, 1752, |
| 15862 | /* 43646 */ GIR_EraseRootFromParent_Done, |
| 15863 | /* 43647 */ // Label 1009: @43647 |
| 15864 | /* 43647 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(43692), // Rule ID 1753 // |
| 15865 | /* 43652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15866 | /* 43655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 15867 | /* 43660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 15868 | /* 43663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15869 | /* 43666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15870 | /* 43670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15871 | /* 43674 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4066:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 15872 | /* 43674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8), |
| 15873 | /* 43677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15874 | /* 43679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15875 | /* 43681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15876 | /* 43684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15877 | /* 43690 */ GIR_RootConstrainSelectedInstOperands, |
| 15878 | /* 43691 */ // GIR_Coverage, 1753, |
| 15879 | /* 43691 */ GIR_EraseRootFromParent_Done, |
| 15880 | /* 43692 */ // Label 1010: @43692 |
| 15881 | /* 43692 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(43737), // Rule ID 1754 // |
| 15882 | /* 43697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15883 | /* 43700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 15884 | /* 43705 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15885 | /* 43708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15886 | /* 43711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15887 | /* 43715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15888 | /* 43719 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4066:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 15889 | /* 43719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16), |
| 15890 | /* 43722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15891 | /* 43724 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15892 | /* 43726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15893 | /* 43729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15894 | /* 43735 */ GIR_RootConstrainSelectedInstOperands, |
| 15895 | /* 43736 */ // GIR_Coverage, 1754, |
| 15896 | /* 43736 */ GIR_EraseRootFromParent_Done, |
| 15897 | /* 43737 */ // Label 1011: @43737 |
| 15898 | /* 43737 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(43782), // Rule ID 1755 // |
| 15899 | /* 43742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15900 | /* 43745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 15901 | /* 43750 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15902 | /* 43753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15903 | /* 43756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15904 | /* 43760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15905 | /* 43764 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4066:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 15906 | /* 43764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32), |
| 15907 | /* 43767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15908 | /* 43769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15909 | /* 43771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15910 | /* 43774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15911 | /* 43780 */ GIR_RootConstrainSelectedInstOperands, |
| 15912 | /* 43781 */ // GIR_Coverage, 1755, |
| 15913 | /* 43781 */ GIR_EraseRootFromParent_Done, |
| 15914 | /* 43782 */ // Label 1012: @43782 |
| 15915 | /* 43782 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(43827), // Rule ID 1756 // |
| 15916 | /* 43787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15917 | /* 43790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 15918 | /* 43795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 15919 | /* 43798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15920 | /* 43801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15921 | /* 43805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15922 | /* 43809 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4065:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 15923 | /* 43809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8), |
| 15924 | /* 43812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15925 | /* 43814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15926 | /* 43816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15927 | /* 43819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15928 | /* 43825 */ GIR_RootConstrainSelectedInstOperands, |
| 15929 | /* 43826 */ // GIR_Coverage, 1756, |
| 15930 | /* 43826 */ GIR_EraseRootFromParent_Done, |
| 15931 | /* 43827 */ // Label 1013: @43827 |
| 15932 | /* 43827 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(43872), // Rule ID 1757 // |
| 15933 | /* 43832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15934 | /* 43835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 15935 | /* 43840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15936 | /* 43843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15937 | /* 43846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15938 | /* 43850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15939 | /* 43854 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4065:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 15940 | /* 43854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16), |
| 15941 | /* 43857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15942 | /* 43859 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15943 | /* 43861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15944 | /* 43864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15945 | /* 43870 */ GIR_RootConstrainSelectedInstOperands, |
| 15946 | /* 43871 */ // GIR_Coverage, 1757, |
| 15947 | /* 43871 */ GIR_EraseRootFromParent_Done, |
| 15948 | /* 43872 */ // Label 1014: @43872 |
| 15949 | /* 43872 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(43917), // Rule ID 1758 // |
| 15950 | /* 43877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15951 | /* 43880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 15952 | /* 43885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15953 | /* 43888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15954 | /* 43891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15955 | /* 43895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15956 | /* 43899 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4065:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 15957 | /* 43899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32), |
| 15958 | /* 43902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15959 | /* 43904 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15960 | /* 43906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15961 | /* 43909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15962 | /* 43915 */ GIR_RootConstrainSelectedInstOperands, |
| 15963 | /* 43916 */ // GIR_Coverage, 1758, |
| 15964 | /* 43916 */ GIR_EraseRootFromParent_Done, |
| 15965 | /* 43917 */ // Label 1015: @43917 |
| 15966 | /* 43917 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(43953), // Rule ID 1781 // |
| 15967 | /* 43922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 15968 | /* 43925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 15969 | /* 43930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15970 | /* 43933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15971 | /* 43936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15972 | /* 43940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15973 | /* 43944 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4009:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15974 | /* 43944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf), |
| 15975 | /* 43947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15976 | /* 43949 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15977 | /* 43951 */ GIR_RootConstrainSelectedInstOperands, |
| 15978 | /* 43952 */ // GIR_Coverage, 1781, |
| 15979 | /* 43952 */ GIR_EraseRootFromParent_Done, |
| 15980 | /* 43953 */ // Label 1016: @43953 |
| 15981 | /* 43953 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(43989), // Rule ID 1782 // |
| 15982 | /* 43958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 15983 | /* 43961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 15984 | /* 43966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15985 | /* 43969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15986 | /* 43972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15987 | /* 43976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15988 | /* 43980 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4009:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15989 | /* 43980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf), |
| 15990 | /* 43983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15991 | /* 43985 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15992 | /* 43987 */ GIR_RootConstrainSelectedInstOperands, |
| 15993 | /* 43988 */ // GIR_Coverage, 1782, |
| 15994 | /* 43988 */ GIR_EraseRootFromParent_Done, |
| 15995 | /* 43989 */ // Label 1017: @43989 |
| 15996 | /* 43989 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(44025), // Rule ID 1783 // |
| 15997 | /* 43994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 15998 | /* 43997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 15999 | /* 44002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16000 | /* 44005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16001 | /* 44008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16002 | /* 44012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16003 | /* 44016 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4010:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 16004 | /* 44016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf), |
| 16005 | /* 44019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16006 | /* 44021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16007 | /* 44023 */ GIR_RootConstrainSelectedInstOperands, |
| 16008 | /* 44024 */ // GIR_Coverage, 1783, |
| 16009 | /* 44024 */ GIR_EraseRootFromParent_Done, |
| 16010 | /* 44025 */ // Label 1018: @44025 |
| 16011 | /* 44025 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(44061), // Rule ID 1784 // |
| 16012 | /* 44030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16013 | /* 44033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 16014 | /* 44038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16015 | /* 44041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16016 | /* 44044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16017 | /* 44048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16018 | /* 44052 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4010:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 16019 | /* 44052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf), |
| 16020 | /* 44055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16021 | /* 44057 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16022 | /* 44059 */ GIR_RootConstrainSelectedInstOperands, |
| 16023 | /* 44060 */ // GIR_Coverage, 1784, |
| 16024 | /* 44060 */ GIR_EraseRootFromParent_Done, |
| 16025 | /* 44061 */ // Label 1019: @44061 |
| 16026 | /* 44061 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(44097), // Rule ID 1785 // |
| 16027 | /* 44066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16028 | /* 44069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 16029 | /* 44074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16030 | /* 44077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16031 | /* 44080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16032 | /* 44084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16033 | /* 44088 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4009:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16034 | /* 44088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh), |
| 16035 | /* 44091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16036 | /* 44093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16037 | /* 44095 */ GIR_RootConstrainSelectedInstOperands, |
| 16038 | /* 44096 */ // GIR_Coverage, 1785, |
| 16039 | /* 44096 */ GIR_EraseRootFromParent_Done, |
| 16040 | /* 44097 */ // Label 1020: @44097 |
| 16041 | /* 44097 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(44133), // Rule ID 1786 // |
| 16042 | /* 44102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16043 | /* 44105 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 16044 | /* 44110 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16045 | /* 44113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16046 | /* 44116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16047 | /* 44120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16048 | /* 44124 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4009:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16049 | /* 44124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh), |
| 16050 | /* 44127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16051 | /* 44129 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16052 | /* 44131 */ GIR_RootConstrainSelectedInstOperands, |
| 16053 | /* 44132 */ // GIR_Coverage, 1786, |
| 16054 | /* 44132 */ GIR_EraseRootFromParent_Done, |
| 16055 | /* 44133 */ // Label 1021: @44133 |
| 16056 | /* 44133 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(44169), // Rule ID 1787 // |
| 16057 | /* 44138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16058 | /* 44141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 16059 | /* 44146 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16060 | /* 44149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16061 | /* 44152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16062 | /* 44156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16063 | /* 44160 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4010:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16064 | /* 44160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh), |
| 16065 | /* 44163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16066 | /* 44165 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16067 | /* 44167 */ GIR_RootConstrainSelectedInstOperands, |
| 16068 | /* 44168 */ // GIR_Coverage, 1787, |
| 16069 | /* 44168 */ GIR_EraseRootFromParent_Done, |
| 16070 | /* 44169 */ // Label 1022: @44169 |
| 16071 | /* 44169 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(44205), // Rule ID 1788 // |
| 16072 | /* 44174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16073 | /* 44177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 16074 | /* 44182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16075 | /* 44185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16076 | /* 44188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16077 | /* 44192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16078 | /* 44196 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4010:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16079 | /* 44196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh), |
| 16080 | /* 44199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16081 | /* 44201 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16082 | /* 44203 */ GIR_RootConstrainSelectedInstOperands, |
| 16083 | /* 44204 */ // GIR_Coverage, 1788, |
| 16084 | /* 44204 */ GIR_EraseRootFromParent_Done, |
| 16085 | /* 44205 */ // Label 1023: @44205 |
| 16086 | /* 44205 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(44241), // Rule ID 1789 // |
| 16087 | /* 44210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16088 | /* 44213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 16089 | /* 44218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16090 | /* 44221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16091 | /* 44224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16092 | /* 44228 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16093 | /* 44232 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4021:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 16094 | /* 44232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf), |
| 16095 | /* 44235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16096 | /* 44237 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16097 | /* 44239 */ GIR_RootConstrainSelectedInstOperands, |
| 16098 | /* 44240 */ // GIR_Coverage, 1789, |
| 16099 | /* 44240 */ GIR_EraseRootFromParent_Done, |
| 16100 | /* 44241 */ // Label 1024: @44241 |
| 16101 | /* 44241 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(44277), // Rule ID 1790 // |
| 16102 | /* 44246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16103 | /* 44249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 16104 | /* 44254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16105 | /* 44257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16106 | /* 44260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16107 | /* 44264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16108 | /* 44268 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4021:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 16109 | /* 44268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf), |
| 16110 | /* 44271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16111 | /* 44273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16112 | /* 44275 */ GIR_RootConstrainSelectedInstOperands, |
| 16113 | /* 44276 */ // GIR_Coverage, 1790, |
| 16114 | /* 44276 */ GIR_EraseRootFromParent_Done, |
| 16115 | /* 44277 */ // Label 1025: @44277 |
| 16116 | /* 44277 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(44313), // Rule ID 1791 // |
| 16117 | /* 44282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16118 | /* 44285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 16119 | /* 44290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16120 | /* 44293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16121 | /* 44296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16122 | /* 44300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16123 | /* 44304 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4022:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 16124 | /* 44304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf), |
| 16125 | /* 44307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16126 | /* 44309 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16127 | /* 44311 */ GIR_RootConstrainSelectedInstOperands, |
| 16128 | /* 44312 */ // GIR_Coverage, 1791, |
| 16129 | /* 44312 */ GIR_EraseRootFromParent_Done, |
| 16130 | /* 44313 */ // Label 1026: @44313 |
| 16131 | /* 44313 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(44349), // Rule ID 1792 // |
| 16132 | /* 44318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16133 | /* 44321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 16134 | /* 44326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16135 | /* 44329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16136 | /* 44332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16137 | /* 44336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16138 | /* 44340 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4022:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 16139 | /* 44340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf), |
| 16140 | /* 44343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16141 | /* 44345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16142 | /* 44347 */ GIR_RootConstrainSelectedInstOperands, |
| 16143 | /* 44348 */ // GIR_Coverage, 1792, |
| 16144 | /* 44348 */ GIR_EraseRootFromParent_Done, |
| 16145 | /* 44349 */ // Label 1027: @44349 |
| 16146 | /* 44349 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(44385), // Rule ID 1793 // |
| 16147 | /* 44354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16148 | /* 44357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 16149 | /* 44362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16150 | /* 44365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16151 | /* 44368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16152 | /* 44372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16153 | /* 44376 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4021:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16154 | /* 44376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh), |
| 16155 | /* 44379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16156 | /* 44381 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16157 | /* 44383 */ GIR_RootConstrainSelectedInstOperands, |
| 16158 | /* 44384 */ // GIR_Coverage, 1793, |
| 16159 | /* 44384 */ GIR_EraseRootFromParent_Done, |
| 16160 | /* 44385 */ // Label 1028: @44385 |
| 16161 | /* 44385 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(44421), // Rule ID 1794 // |
| 16162 | /* 44390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16163 | /* 44393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 16164 | /* 44398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16165 | /* 44401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16166 | /* 44404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16167 | /* 44408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16168 | /* 44412 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4021:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16169 | /* 44412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh), |
| 16170 | /* 44415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16171 | /* 44417 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16172 | /* 44419 */ GIR_RootConstrainSelectedInstOperands, |
| 16173 | /* 44420 */ // GIR_Coverage, 1794, |
| 16174 | /* 44420 */ GIR_EraseRootFromParent_Done, |
| 16175 | /* 44421 */ // Label 1029: @44421 |
| 16176 | /* 44421 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(44457), // Rule ID 1795 // |
| 16177 | /* 44426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16178 | /* 44429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 16179 | /* 44434 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16180 | /* 44437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16181 | /* 44440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16182 | /* 44444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16183 | /* 44448 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4022:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16184 | /* 44448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh), |
| 16185 | /* 44451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16186 | /* 44453 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16187 | /* 44455 */ GIR_RootConstrainSelectedInstOperands, |
| 16188 | /* 44456 */ // GIR_Coverage, 1795, |
| 16189 | /* 44456 */ GIR_EraseRootFromParent_Done, |
| 16190 | /* 44457 */ // Label 1030: @44457 |
| 16191 | /* 44457 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(44493), // Rule ID 1796 // |
| 16192 | /* 44462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16193 | /* 44465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 16194 | /* 44470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16195 | /* 44473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16196 | /* 44476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16197 | /* 44480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16198 | /* 44484 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4022:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16199 | /* 44484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh), |
| 16200 | /* 44487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16201 | /* 44489 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16202 | /* 44491 */ GIR_RootConstrainSelectedInstOperands, |
| 16203 | /* 44492 */ // GIR_Coverage, 1796, |
| 16204 | /* 44492 */ GIR_EraseRootFromParent_Done, |
| 16205 | /* 44493 */ // Label 1031: @44493 |
| 16206 | /* 44493 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(44529), // Rule ID 1797 // |
| 16207 | /* 44498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16208 | /* 44501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 16209 | /* 44506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16210 | /* 44509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16211 | /* 44512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16212 | /* 44516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16213 | /* 44520 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4023:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 16214 | /* 44520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf), |
| 16215 | /* 44523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16216 | /* 44525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16217 | /* 44527 */ GIR_RootConstrainSelectedInstOperands, |
| 16218 | /* 44528 */ // GIR_Coverage, 1797, |
| 16219 | /* 44528 */ GIR_EraseRootFromParent_Done, |
| 16220 | /* 44529 */ // Label 1032: @44529 |
| 16221 | /* 44529 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(44565), // Rule ID 1798 // |
| 16222 | /* 44534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16223 | /* 44537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 16224 | /* 44542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16225 | /* 44545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16226 | /* 44548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16227 | /* 44552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16228 | /* 44556 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4023:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 16229 | /* 44556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf), |
| 16230 | /* 44559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16231 | /* 44561 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16232 | /* 44563 */ GIR_RootConstrainSelectedInstOperands, |
| 16233 | /* 44564 */ // GIR_Coverage, 1798, |
| 16234 | /* 44564 */ GIR_EraseRootFromParent_Done, |
| 16235 | /* 44565 */ // Label 1033: @44565 |
| 16236 | /* 44565 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(44601), // Rule ID 1799 // |
| 16237 | /* 44570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16238 | /* 44573 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 16239 | /* 44578 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16240 | /* 44581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16241 | /* 44584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16242 | /* 44588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16243 | /* 44592 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4024:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 16244 | /* 44592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf), |
| 16245 | /* 44595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16246 | /* 44597 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16247 | /* 44599 */ GIR_RootConstrainSelectedInstOperands, |
| 16248 | /* 44600 */ // GIR_Coverage, 1799, |
| 16249 | /* 44600 */ GIR_EraseRootFromParent_Done, |
| 16250 | /* 44601 */ // Label 1034: @44601 |
| 16251 | /* 44601 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(44637), // Rule ID 1800 // |
| 16252 | /* 44606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16253 | /* 44609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 16254 | /* 44614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16255 | /* 44617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16256 | /* 44620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16257 | /* 44624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16258 | /* 44628 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4024:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 16259 | /* 44628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf), |
| 16260 | /* 44631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16261 | /* 44633 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16262 | /* 44635 */ GIR_RootConstrainSelectedInstOperands, |
| 16263 | /* 44636 */ // GIR_Coverage, 1800, |
| 16264 | /* 44636 */ GIR_EraseRootFromParent_Done, |
| 16265 | /* 44637 */ // Label 1035: @44637 |
| 16266 | /* 44637 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(44673), // Rule ID 1801 // |
| 16267 | /* 44642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16268 | /* 44645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 16269 | /* 44650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16270 | /* 44653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16271 | /* 44656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16272 | /* 44660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16273 | /* 44664 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4023:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16274 | /* 44664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh), |
| 16275 | /* 44667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16276 | /* 44669 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16277 | /* 44671 */ GIR_RootConstrainSelectedInstOperands, |
| 16278 | /* 44672 */ // GIR_Coverage, 1801, |
| 16279 | /* 44672 */ GIR_EraseRootFromParent_Done, |
| 16280 | /* 44673 */ // Label 1036: @44673 |
| 16281 | /* 44673 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(44709), // Rule ID 1802 // |
| 16282 | /* 44678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16283 | /* 44681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 16284 | /* 44686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16285 | /* 44689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16286 | /* 44692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16287 | /* 44696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16288 | /* 44700 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4023:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16289 | /* 44700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh), |
| 16290 | /* 44703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16291 | /* 44705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16292 | /* 44707 */ GIR_RootConstrainSelectedInstOperands, |
| 16293 | /* 44708 */ // GIR_Coverage, 1802, |
| 16294 | /* 44708 */ GIR_EraseRootFromParent_Done, |
| 16295 | /* 44709 */ // Label 1037: @44709 |
| 16296 | /* 44709 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(44745), // Rule ID 1803 // |
| 16297 | /* 44714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16298 | /* 44717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 16299 | /* 44722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16300 | /* 44725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16301 | /* 44728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16302 | /* 44732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16303 | /* 44736 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4024:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16304 | /* 44736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh), |
| 16305 | /* 44739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16306 | /* 44741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16307 | /* 44743 */ GIR_RootConstrainSelectedInstOperands, |
| 16308 | /* 44744 */ // GIR_Coverage, 1803, |
| 16309 | /* 44744 */ GIR_EraseRootFromParent_Done, |
| 16310 | /* 44745 */ // Label 1038: @44745 |
| 16311 | /* 44745 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(44781), // Rule ID 1804 // |
| 16312 | /* 44750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16313 | /* 44753 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 16314 | /* 44758 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16315 | /* 44761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16316 | /* 44764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16317 | /* 44768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16318 | /* 44772 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4024:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16319 | /* 44772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh), |
| 16320 | /* 44775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16321 | /* 44777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16322 | /* 44779 */ GIR_RootConstrainSelectedInstOperands, |
| 16323 | /* 44780 */ // GIR_Coverage, 1804, |
| 16324 | /* 44780 */ GIR_EraseRootFromParent_Done, |
| 16325 | /* 44781 */ // Label 1039: @44781 |
| 16326 | /* 44781 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(44817), // Rule ID 1805 // |
| 16327 | /* 44786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16328 | /* 44789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 16329 | /* 44794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16330 | /* 44797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16331 | /* 44800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16332 | /* 44804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16333 | /* 44808 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4019:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 16334 | /* 44808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf), |
| 16335 | /* 44811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16336 | /* 44813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16337 | /* 44815 */ GIR_RootConstrainSelectedInstOperands, |
| 16338 | /* 44816 */ // GIR_Coverage, 1805, |
| 16339 | /* 44816 */ GIR_EraseRootFromParent_Done, |
| 16340 | /* 44817 */ // Label 1040: @44817 |
| 16341 | /* 44817 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(44853), // Rule ID 1806 // |
| 16342 | /* 44822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16343 | /* 44825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 16344 | /* 44830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16345 | /* 44833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16346 | /* 44836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16347 | /* 44840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16348 | /* 44844 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4019:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 16349 | /* 44844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf), |
| 16350 | /* 44847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16351 | /* 44849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16352 | /* 44851 */ GIR_RootConstrainSelectedInstOperands, |
| 16353 | /* 44852 */ // GIR_Coverage, 1806, |
| 16354 | /* 44852 */ GIR_EraseRootFromParent_Done, |
| 16355 | /* 44853 */ // Label 1041: @44853 |
| 16356 | /* 44853 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(44889), // Rule ID 1807 // |
| 16357 | /* 44858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16358 | /* 44861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 16359 | /* 44866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16360 | /* 44869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16361 | /* 44872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16362 | /* 44876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16363 | /* 44880 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4020:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 16364 | /* 44880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf), |
| 16365 | /* 44883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16366 | /* 44885 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16367 | /* 44887 */ GIR_RootConstrainSelectedInstOperands, |
| 16368 | /* 44888 */ // GIR_Coverage, 1807, |
| 16369 | /* 44888 */ GIR_EraseRootFromParent_Done, |
| 16370 | /* 44889 */ // Label 1042: @44889 |
| 16371 | /* 44889 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(44925), // Rule ID 1808 // |
| 16372 | /* 44894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 16373 | /* 44897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 16374 | /* 44902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16375 | /* 44905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16376 | /* 44908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16377 | /* 44912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16378 | /* 44916 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4020:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 16379 | /* 44916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf), |
| 16380 | /* 44919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16381 | /* 44921 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16382 | /* 44923 */ GIR_RootConstrainSelectedInstOperands, |
| 16383 | /* 44924 */ // GIR_Coverage, 1808, |
| 16384 | /* 44924 */ GIR_EraseRootFromParent_Done, |
| 16385 | /* 44925 */ // Label 1043: @44925 |
| 16386 | /* 44925 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(44961), // Rule ID 1809 // |
| 16387 | /* 44930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16388 | /* 44933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 16389 | /* 44938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16390 | /* 44941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16391 | /* 44944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16392 | /* 44948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16393 | /* 44952 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4019:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16394 | /* 44952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh), |
| 16395 | /* 44955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16396 | /* 44957 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16397 | /* 44959 */ GIR_RootConstrainSelectedInstOperands, |
| 16398 | /* 44960 */ // GIR_Coverage, 1809, |
| 16399 | /* 44960 */ GIR_EraseRootFromParent_Done, |
| 16400 | /* 44961 */ // Label 1044: @44961 |
| 16401 | /* 44961 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(44997), // Rule ID 1810 // |
| 16402 | /* 44966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16403 | /* 44969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 16404 | /* 44974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16405 | /* 44977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16406 | /* 44980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16407 | /* 44984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16408 | /* 44988 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4019:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16409 | /* 44988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh), |
| 16410 | /* 44991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16411 | /* 44993 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16412 | /* 44995 */ GIR_RootConstrainSelectedInstOperands, |
| 16413 | /* 44996 */ // GIR_Coverage, 1810, |
| 16414 | /* 44996 */ GIR_EraseRootFromParent_Done, |
| 16415 | /* 44997 */ // Label 1045: @44997 |
| 16416 | /* 44997 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(45033), // Rule ID 1811 // |
| 16417 | /* 45002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16418 | /* 45005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 16419 | /* 45010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16420 | /* 45013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16421 | /* 45016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16422 | /* 45020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16423 | /* 45024 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4020:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 16424 | /* 45024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh), |
| 16425 | /* 45027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16426 | /* 45029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16427 | /* 45031 */ GIR_RootConstrainSelectedInstOperands, |
| 16428 | /* 45032 */ // GIR_Coverage, 1811, |
| 16429 | /* 45032 */ GIR_EraseRootFromParent_Done, |
| 16430 | /* 45033 */ // Label 1046: @45033 |
| 16431 | /* 45033 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(45069), // Rule ID 1812 // |
| 16432 | /* 45038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 16433 | /* 45041 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 16434 | /* 45046 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16435 | /* 45049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16436 | /* 45052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16437 | /* 45056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16438 | /* 45060 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4020:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 16439 | /* 45060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh), |
| 16440 | /* 45063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16441 | /* 45065 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16442 | /* 45067 */ GIR_RootConstrainSelectedInstOperands, |
| 16443 | /* 45068 */ // GIR_Coverage, 1812, |
| 16444 | /* 45068 */ GIR_EraseRootFromParent_Done, |
| 16445 | /* 45069 */ // Label 1047: @45069 |
| 16446 | /* 45069 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(45114), // Rule ID 1829 // |
| 16447 | /* 45074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON), |
| 16448 | /* 45077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf), |
| 16449 | /* 45082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16450 | /* 45085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16451 | /* 45088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16452 | /* 45092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16453 | /* 45096 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4015:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm) |
| 16454 | /* 45096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 16455 | /* 45099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16456 | /* 45101 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16457 | /* 45103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16458 | /* 45106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16459 | /* 45112 */ GIR_RootConstrainSelectedInstOperands, |
| 16460 | /* 45113 */ // GIR_Coverage, 1829, |
| 16461 | /* 45113 */ GIR_EraseRootFromParent_Done, |
| 16462 | /* 45114 */ // Label 1048: @45114 |
| 16463 | /* 45114 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(45159), // Rule ID 1830 // |
| 16464 | /* 45119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON), |
| 16465 | /* 45122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp), |
| 16466 | /* 45127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16467 | /* 45130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16468 | /* 45133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16469 | /* 45137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16470 | /* 45141 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4018:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm) |
| 16471 | /* 45141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 16472 | /* 45144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16473 | /* 45146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16474 | /* 45148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16475 | /* 45151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16476 | /* 45157 */ GIR_RootConstrainSelectedInstOperands, |
| 16477 | /* 45158 */ // GIR_Coverage, 1830, |
| 16478 | /* 45158 */ GIR_EraseRootFromParent_Done, |
| 16479 | /* 45159 */ // Label 1049: @45159 |
| 16480 | /* 45159 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(45195), // Rule ID 1902 // |
| 16481 | /* 45164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 16482 | /* 45167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc), |
| 16483 | /* 45172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 16484 | /* 45175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 16485 | /* 45178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16486 | /* 45182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16487 | /* 45186 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3978:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 16488 | /* 45186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC), |
| 16489 | /* 45189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16490 | /* 45191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16491 | /* 45193 */ GIR_RootConstrainSelectedInstOperands, |
| 16492 | /* 45194 */ // GIR_Coverage, 1902, |
| 16493 | /* 45194 */ GIR_EraseRootFromParent_Done, |
| 16494 | /* 45195 */ // Label 1050: @45195 |
| 16495 | /* 45195 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(45231), // Rule ID 1903 // |
| 16496 | /* 45200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 16497 | /* 45203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc), |
| 16498 | /* 45208 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 16499 | /* 45211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 16500 | /* 45214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16501 | /* 45218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16502 | /* 45222 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3979:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 16503 | /* 45222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC), |
| 16504 | /* 45225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16505 | /* 45227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16506 | /* 45229 */ GIR_RootConstrainSelectedInstOperands, |
| 16507 | /* 45230 */ // GIR_Coverage, 1903, |
| 16508 | /* 45230 */ GIR_EraseRootFromParent_Done, |
| 16509 | /* 45231 */ // Label 1051: @45231 |
| 16510 | /* 45231 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(45279), // Rule ID 2036 // |
| 16511 | /* 45236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 16512 | /* 45239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 16513 | /* 45244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16514 | /* 45247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16515 | /* 45250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16516 | /* 45254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16517 | /* 45258 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 16518 | /* 45258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16), |
| 16519 | /* 45261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16520 | /* 45263 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 16521 | /* 45265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16522 | /* 45268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16523 | /* 45271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16524 | /* 45277 */ GIR_RootConstrainSelectedInstOperands, |
| 16525 | /* 45278 */ // GIR_Coverage, 2036, |
| 16526 | /* 45278 */ GIR_EraseRootFromParent_Done, |
| 16527 | /* 45279 */ // Label 1052: @45279 |
| 16528 | /* 45279 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(45327), // Rule ID 2284 // |
| 16529 | /* 45284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16530 | /* 45287 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 16531 | /* 45292 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16532 | /* 45295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16533 | /* 45298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16534 | /* 45302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16535 | /* 45306 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] }) |
| 16536 | /* 45306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16), |
| 16537 | /* 45309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16538 | /* 45311 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16539 | /* 45313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16540 | /* 45316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16541 | /* 45319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16542 | /* 45325 */ GIR_RootConstrainSelectedInstOperands, |
| 16543 | /* 45326 */ // GIR_Coverage, 2284, |
| 16544 | /* 45326 */ GIR_EraseRootFromParent_Done, |
| 16545 | /* 45327 */ // Label 1053: @45327 |
| 16546 | /* 45327 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(45393), // Rule ID 4348 // |
| 16547 | /* 45332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16548 | /* 45335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 16549 | /* 45340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16550 | /* 45343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16551 | /* 45346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16552 | /* 45350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16553 | /* 45354 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3938:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 16554 | /* 45354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16555 | /* 45357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16556 | /* 45361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16557 | /* 45366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 16558 | /* 45369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16559 | /* 45371 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16560 | /* 45373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16561 | /* 45376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16562 | /* 45382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16563 | /* 45388 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16564 | /* 45391 */ GIR_RootConstrainSelectedInstOperands, |
| 16565 | /* 45392 */ // GIR_Coverage, 4348, |
| 16566 | /* 45392 */ GIR_EraseRootFromParent_Done, |
| 16567 | /* 45393 */ // Label 1054: @45393 |
| 16568 | /* 45393 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(45459), // Rule ID 4352 // |
| 16569 | /* 45398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16570 | /* 45401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx), |
| 16571 | /* 45406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16572 | /* 45409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16573 | /* 45412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16574 | /* 45416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16575 | /* 45420 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 16576 | /* 45420 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16577 | /* 45423 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16578 | /* 45427 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16579 | /* 45432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 16580 | /* 45435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16581 | /* 45437 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16582 | /* 45439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16583 | /* 45442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16584 | /* 45448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16585 | /* 45454 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16586 | /* 45457 */ GIR_RootConstrainSelectedInstOperands, |
| 16587 | /* 45458 */ // GIR_Coverage, 4352, |
| 16588 | /* 45458 */ GIR_EraseRootFromParent_Done, |
| 16589 | /* 45459 */ // Label 1055: @45459 |
| 16590 | /* 45459 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(45525), // Rule ID 4356 // |
| 16591 | /* 45464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16592 | /* 45467 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta), |
| 16593 | /* 45472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16594 | /* 45475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16595 | /* 45478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16596 | /* 45482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16597 | /* 45486 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 16598 | /* 45486 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16599 | /* 45489 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16600 | /* 45493 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16601 | /* 45498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 16602 | /* 45501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16603 | /* 45503 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16604 | /* 45505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16605 | /* 45508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16606 | /* 45514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16607 | /* 45520 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16608 | /* 45523 */ GIR_RootConstrainSelectedInstOperands, |
| 16609 | /* 45524 */ // GIR_Coverage, 4356, |
| 16610 | /* 45524 */ GIR_EraseRootFromParent_Done, |
| 16611 | /* 45525 */ // Label 1056: @45525 |
| 16612 | /* 45525 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(45591), // Rule ID 4360 // |
| 16613 | /* 45530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16614 | /* 45533 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz), |
| 16615 | /* 45538 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16616 | /* 45541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16617 | /* 45544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16618 | /* 45548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16619 | /* 45552 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 16620 | /* 45552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16621 | /* 45555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16622 | /* 45559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16623 | /* 45564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 16624 | /* 45567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16625 | /* 45569 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16626 | /* 45571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16627 | /* 45574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16628 | /* 45580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16629 | /* 45586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16630 | /* 45589 */ GIR_RootConstrainSelectedInstOperands, |
| 16631 | /* 45590 */ // GIR_Coverage, 4360, |
| 16632 | /* 45590 */ GIR_EraseRootFromParent_Done, |
| 16633 | /* 45591 */ // Label 1057: @45591 |
| 16634 | /* 45591 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(45657), // Rule ID 4364 // |
| 16635 | /* 45596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16636 | /* 45599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm), |
| 16637 | /* 45604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16638 | /* 45607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16639 | /* 45610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16640 | /* 45614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16641 | /* 45618 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 16642 | /* 45618 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16643 | /* 45621 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16644 | /* 45625 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16645 | /* 45630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 16646 | /* 45633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16647 | /* 45635 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16648 | /* 45637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16649 | /* 45640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16650 | /* 45646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16651 | /* 45652 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16652 | /* 45655 */ GIR_RootConstrainSelectedInstOperands, |
| 16653 | /* 45656 */ // GIR_Coverage, 4364, |
| 16654 | /* 45656 */ GIR_EraseRootFromParent_Done, |
| 16655 | /* 45657 */ // Label 1058: @45657 |
| 16656 | /* 45657 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(45723), // Rule ID 4368 // |
| 16657 | /* 45662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16658 | /* 45665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp), |
| 16659 | /* 45670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16660 | /* 45673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16661 | /* 45676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16662 | /* 45680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16663 | /* 45684 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3940:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 16664 | /* 45684 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16665 | /* 45687 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16666 | /* 45691 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16667 | /* 45696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 16668 | /* 45699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16669 | /* 45701 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16670 | /* 45703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16671 | /* 45706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16672 | /* 45712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16673 | /* 45718 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16674 | /* 45721 */ GIR_RootConstrainSelectedInstOperands, |
| 16675 | /* 45722 */ // GIR_Coverage, 4368, |
| 16676 | /* 45722 */ GIR_EraseRootFromParent_Done, |
| 16677 | /* 45723 */ // Label 1059: @45723 |
| 16678 | /* 45723 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(45789), // Rule ID 4372 // |
| 16679 | /* 45728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16680 | /* 45731 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 16681 | /* 45736 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16682 | /* 45739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16683 | /* 45742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16684 | /* 45746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16685 | /* 45750 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3938:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 16686 | /* 45750 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16687 | /* 45753 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16688 | /* 45757 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16689 | /* 45762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 16690 | /* 45765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16691 | /* 45767 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16692 | /* 45769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16693 | /* 45772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16694 | /* 45778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16695 | /* 45784 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16696 | /* 45787 */ GIR_RootConstrainSelectedInstOperands, |
| 16697 | /* 45788 */ // GIR_Coverage, 4372, |
| 16698 | /* 45788 */ GIR_EraseRootFromParent_Done, |
| 16699 | /* 45789 */ // Label 1060: @45789 |
| 16700 | /* 45789 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(45855), // Rule ID 4376 // |
| 16701 | /* 45794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16702 | /* 45797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx), |
| 16703 | /* 45802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16704 | /* 45805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16705 | /* 45808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16706 | /* 45812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16707 | /* 45816 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 16708 | /* 45816 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16709 | /* 45819 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16710 | /* 45823 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16711 | /* 45828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 16712 | /* 45831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16713 | /* 45833 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16714 | /* 45835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16715 | /* 45838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16716 | /* 45844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16717 | /* 45850 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16718 | /* 45853 */ GIR_RootConstrainSelectedInstOperands, |
| 16719 | /* 45854 */ // GIR_Coverage, 4376, |
| 16720 | /* 45854 */ GIR_EraseRootFromParent_Done, |
| 16721 | /* 45855 */ // Label 1061: @45855 |
| 16722 | /* 45855 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(45921), // Rule ID 4380 // |
| 16723 | /* 45860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16724 | /* 45863 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta), |
| 16725 | /* 45868 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16726 | /* 45871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16727 | /* 45874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16728 | /* 45878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16729 | /* 45882 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 16730 | /* 45882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16731 | /* 45885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16732 | /* 45889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16733 | /* 45894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 16734 | /* 45897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16735 | /* 45899 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16736 | /* 45901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16737 | /* 45904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16738 | /* 45910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16739 | /* 45916 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16740 | /* 45919 */ GIR_RootConstrainSelectedInstOperands, |
| 16741 | /* 45920 */ // GIR_Coverage, 4380, |
| 16742 | /* 45920 */ GIR_EraseRootFromParent_Done, |
| 16743 | /* 45921 */ // Label 1062: @45921 |
| 16744 | /* 45921 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(45987), // Rule ID 4384 // |
| 16745 | /* 45926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16746 | /* 45929 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz), |
| 16747 | /* 45934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16748 | /* 45937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16749 | /* 45940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16750 | /* 45944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16751 | /* 45948 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 16752 | /* 45948 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16753 | /* 45951 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16754 | /* 45955 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16755 | /* 45960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 16756 | /* 45963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16757 | /* 45965 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16758 | /* 45967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16759 | /* 45970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16760 | /* 45976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16761 | /* 45982 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16762 | /* 45985 */ GIR_RootConstrainSelectedInstOperands, |
| 16763 | /* 45986 */ // GIR_Coverage, 4384, |
| 16764 | /* 45986 */ GIR_EraseRootFromParent_Done, |
| 16765 | /* 45987 */ // Label 1063: @45987 |
| 16766 | /* 45987 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(46053), // Rule ID 4388 // |
| 16767 | /* 45992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16768 | /* 45995 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm), |
| 16769 | /* 46000 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16770 | /* 46003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16771 | /* 46006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16772 | /* 46010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16773 | /* 46014 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 16774 | /* 46014 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16775 | /* 46017 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16776 | /* 46021 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16777 | /* 46026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 16778 | /* 46029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16779 | /* 46031 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16780 | /* 46033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16781 | /* 46036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16782 | /* 46042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16783 | /* 46048 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16784 | /* 46051 */ GIR_RootConstrainSelectedInstOperands, |
| 16785 | /* 46052 */ // GIR_Coverage, 4388, |
| 16786 | /* 46052 */ GIR_EraseRootFromParent_Done, |
| 16787 | /* 46053 */ // Label 1064: @46053 |
| 16788 | /* 46053 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(46119), // Rule ID 4392 // |
| 16789 | /* 46058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16790 | /* 46061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp), |
| 16791 | /* 46066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16792 | /* 46069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16793 | /* 46072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16794 | /* 46076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16795 | /* 46080 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3940:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 16796 | /* 46080 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16797 | /* 46083 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16798 | /* 46087 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16799 | /* 46092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 16800 | /* 46095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16801 | /* 46097 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 16802 | /* 46099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16803 | /* 46102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16804 | /* 46108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16805 | /* 46114 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16806 | /* 46117 */ GIR_RootConstrainSelectedInstOperands, |
| 16807 | /* 46118 */ // GIR_Coverage, 4392, |
| 16808 | /* 46118 */ GIR_EraseRootFromParent_Done, |
| 16809 | /* 46119 */ // Label 1065: @46119 |
| 16810 | /* 46119 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(46170), // Rule ID 5378 // |
| 16811 | /* 46124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 16812 | /* 46127 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8), |
| 16813 | /* 46132 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1, |
| 16814 | /* 46135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16815 | /* 46138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16816 | /* 46142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16817 | /* 46146 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3857:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn) |
| 16818 | /* 46146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8), |
| 16819 | /* 46149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16820 | /* 46151 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16821 | /* 46153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16822 | /* 46156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16823 | /* 46162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16824 | /* 46168 */ GIR_RootConstrainSelectedInstOperands, |
| 16825 | /* 46169 */ // GIR_Coverage, 5378, |
| 16826 | /* 46169 */ GIR_EraseRootFromParent_Done, |
| 16827 | /* 46170 */ // Label 1066: @46170 |
| 16828 | /* 46170 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(46221), // Rule ID 5380 // |
| 16829 | /* 46175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 16830 | /* 46178 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16), |
| 16831 | /* 46183 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 16832 | /* 46186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16833 | /* 46189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16834 | /* 46193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16835 | /* 46197 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3854:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn) |
| 16836 | /* 46197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16), |
| 16837 | /* 46200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16838 | /* 46202 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16839 | /* 46204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16840 | /* 46207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16841 | /* 46213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16842 | /* 46219 */ GIR_RootConstrainSelectedInstOperands, |
| 16843 | /* 46220 */ // GIR_Coverage, 5380, |
| 16844 | /* 46220 */ GIR_EraseRootFromParent_Done, |
| 16845 | /* 46221 */ // Label 1067: @46221 |
| 16846 | /* 46221 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(46272), // Rule ID 5382 // |
| 16847 | /* 46226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 16848 | /* 46229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32), |
| 16849 | /* 46234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 16850 | /* 46237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16851 | /* 46240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16852 | /* 46244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16853 | /* 46248 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3855:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn) |
| 16854 | /* 46248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32), |
| 16855 | /* 46251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16856 | /* 46253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16857 | /* 46255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16858 | /* 46258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16859 | /* 46264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16860 | /* 46270 */ GIR_RootConstrainSelectedInstOperands, |
| 16861 | /* 46271 */ // GIR_Coverage, 5382, |
| 16862 | /* 46271 */ GIR_EraseRootFromParent_Done, |
| 16863 | /* 46272 */ // Label 1068: @46272 |
| 16864 | /* 46272 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(46323), // Rule ID 5384 // |
| 16865 | /* 46277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 16866 | /* 46280 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64), |
| 16867 | /* 46285 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1, |
| 16868 | /* 46288 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16869 | /* 46291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16870 | /* 46295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16871 | /* 46299 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3856:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn) |
| 16872 | /* 46299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64), |
| 16873 | /* 46302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16874 | /* 46304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16875 | /* 46306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16876 | /* 46309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16877 | /* 46315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16878 | /* 46321 */ GIR_RootConstrainSelectedInstOperands, |
| 16879 | /* 46322 */ // GIR_Coverage, 5384, |
| 16880 | /* 46322 */ GIR_EraseRootFromParent_Done, |
| 16881 | /* 46323 */ // Label 1069: @46323 |
| 16882 | /* 46323 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(46369), // Rule ID 599 // |
| 16883 | /* 46328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 16884 | /* 46331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt), |
| 16885 | /* 46336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16886 | /* 46339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16887 | /* 46343 */ // MIs[0] Rn |
| 16888 | /* 46343 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16889 | /* 46347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16890 | /* 46351 */ // (intrinsic_wo_chain:{ *:[i32] } 3731:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16891 | /* 46351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT), |
| 16892 | /* 46354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16893 | /* 46356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16894 | /* 46358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16895 | /* 46361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16896 | /* 46367 */ GIR_RootConstrainSelectedInstOperands, |
| 16897 | /* 46368 */ // GIR_Coverage, 599, |
| 16898 | /* 46368 */ GIR_EraseRootFromParent_Done, |
| 16899 | /* 46369 */ // Label 1070: @46369 |
| 16900 | /* 46369 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(46415), // Rule ID 600 // |
| 16901 | /* 46374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 16902 | /* 46377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt), |
| 16903 | /* 46382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16904 | /* 46385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16905 | /* 46389 */ // MIs[0] Rn |
| 16906 | /* 46389 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16907 | /* 46393 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16908 | /* 46397 */ // (intrinsic_wo_chain:{ *:[i32] } 3734:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16909 | /* 46397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT), |
| 16910 | /* 46400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16911 | /* 46402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16912 | /* 46404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16913 | /* 46407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16914 | /* 46413 */ GIR_RootConstrainSelectedInstOperands, |
| 16915 | /* 46414 */ // GIR_Coverage, 600, |
| 16916 | /* 46414 */ GIR_EraseRootFromParent_Done, |
| 16917 | /* 46415 */ // Label 1071: @46415 |
| 16918 | /* 46415 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(46461), // Rule ID 601 // |
| 16919 | /* 46420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 16920 | /* 46423 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta), |
| 16921 | /* 46428 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16922 | /* 46431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16923 | /* 46435 */ // MIs[0] Rn |
| 16924 | /* 46435 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16925 | /* 46439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16926 | /* 46443 */ // (intrinsic_wo_chain:{ *:[i32] } 3732:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16927 | /* 46443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA), |
| 16928 | /* 46446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16929 | /* 46448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16930 | /* 46450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16931 | /* 46453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16932 | /* 46459 */ GIR_RootConstrainSelectedInstOperands, |
| 16933 | /* 46460 */ // GIR_Coverage, 601, |
| 16934 | /* 46460 */ GIR_EraseRootFromParent_Done, |
| 16935 | /* 46461 */ // Label 1072: @46461 |
| 16936 | /* 46461 */ GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(46507), // Rule ID 602 // |
| 16937 | /* 46466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 16938 | /* 46469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat), |
| 16939 | /* 46474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16940 | /* 46477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16941 | /* 46481 */ // MIs[0] Rn |
| 16942 | /* 46481 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16943 | /* 46485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16944 | /* 46489 */ // (intrinsic_wo_chain:{ *:[i32] } 3733:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16945 | /* 46489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT), |
| 16946 | /* 46492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16947 | /* 46494 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16948 | /* 46496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16949 | /* 46499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16950 | /* 46505 */ GIR_RootConstrainSelectedInstOperands, |
| 16951 | /* 46506 */ // GIR_Coverage, 602, |
| 16952 | /* 46506 */ GIR_EraseRootFromParent_Done, |
| 16953 | /* 46507 */ // Label 1073: @46507 |
| 16954 | /* 46507 */ GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(46661), // Rule ID 3067 // |
| 16955 | /* 46512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16956 | /* 46515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h), |
| 16957 | /* 46520 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16958 | /* 46523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16959 | /* 46526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16960 | /* 46530 */ // (intrinsic_wo_chain:{ *:[i32] } 3986:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] }) |
| 16961 | /* 46530 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 16962 | /* 46533 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16963 | /* 46537 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16964 | /* 46542 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 16965 | /* 46546 */ GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 16966 | /* 46551 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
| 16967 | /* 46554 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16968 | /* 46558 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16969 | /* 46563 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 16970 | /* 46565 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 16971 | /* 46568 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 16972 | /* 46572 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16973 | /* 46577 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 16974 | /* 46580 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 16975 | /* 46583 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 16976 | /* 46586 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 16977 | /* 46591 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 16978 | /* 46596 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 16979 | /* 46601 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 16980 | /* 46604 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H), |
| 16981 | /* 46608 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16982 | /* 46613 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 16983 | /* 46616 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16984 | /* 46618 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16985 | /* 46621 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16986 | /* 46625 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16987 | /* 46630 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 16988 | /* 46637 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 16989 | /* 46642 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID), |
| 16990 | /* 46647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16991 | /* 46650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16992 | /* 46652 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16993 | /* 46655 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 16994 | /* 46660 */ // GIR_Coverage, 3067, |
| 16995 | /* 46660 */ GIR_EraseRootFromParent_Done, |
| 16996 | /* 46661 */ // Label 1074: @46661 |
| 16997 | /* 46661 */ GIM_Reject, |
| 16998 | /* 46662 */ // Label 964: @46662 |
| 16999 | /* 46662 */ GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(69674), |
| 17000 | /* 46667 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 17001 | /* 46670 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(46727), // Rule ID 2302 // |
| 17002 | /* 46675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17003 | /* 46678 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 17004 | /* 46683 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17005 | /* 46686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17006 | /* 46689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17007 | /* 46692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17008 | /* 46696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17009 | /* 46700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17010 | /* 46704 */ // (intrinsic_wo_chain:{ *:[i32] } 4196:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 17011 | /* 46704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16), |
| 17012 | /* 46707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17013 | /* 46709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17014 | /* 46711 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17015 | /* 46713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17016 | /* 46716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17017 | /* 46719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17018 | /* 46725 */ GIR_RootConstrainSelectedInstOperands, |
| 17019 | /* 46726 */ // GIR_Coverage, 2302, |
| 17020 | /* 46726 */ GIR_EraseRootFromParent_Done, |
| 17021 | /* 46727 */ // Label 1076: @46727 |
| 17022 | /* 46727 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(46826), // Rule ID 2073 // |
| 17023 | /* 46732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 17024 | /* 46735 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 17025 | /* 46740 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17026 | /* 46743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17027 | /* 46746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17028 | /* 46749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17029 | /* 46753 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17030 | /* 46757 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 17031 | /* 46761 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 17032 | /* 46765 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17033 | /* 46769 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17034 | /* 46774 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17035 | /* 46778 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17036 | /* 46782 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17037 | /* 46786 */ // MIs[2] Operand 1 |
| 17038 | /* 46786 */ // No operand predicates |
| 17039 | /* 46786 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 17040 | /* 46790 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17041 | /* 46794 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17042 | /* 46798 */ // MIs[3] Operand 1 |
| 17043 | /* 46798 */ // No operand predicates |
| 17044 | /* 46798 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 17045 | /* 46800 */ // (intrinsic_wo_chain:{ *:[i32] } 4191:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 17046 | /* 46800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 17047 | /* 46803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17048 | /* 46805 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 17049 | /* 46808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 17050 | /* 46812 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 17051 | /* 46815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17052 | /* 46818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17053 | /* 46824 */ GIR_RootConstrainSelectedInstOperands, |
| 17054 | /* 46825 */ // GIR_Coverage, 2073, |
| 17055 | /* 46825 */ GIR_EraseRootFromParent_Done, |
| 17056 | /* 46826 */ // Label 1077: @46826 |
| 17057 | /* 46826 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(46925), // Rule ID 2339 // |
| 17058 | /* 46831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 17059 | /* 46834 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 17060 | /* 46839 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17061 | /* 46842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17062 | /* 46845 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17063 | /* 46848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17064 | /* 46852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17065 | /* 46856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 17066 | /* 46860 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 17067 | /* 46864 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17068 | /* 46868 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17069 | /* 46873 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17070 | /* 46877 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17071 | /* 46881 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17072 | /* 46885 */ // MIs[2] Operand 1 |
| 17073 | /* 46885 */ // No operand predicates |
| 17074 | /* 46885 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 17075 | /* 46889 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17076 | /* 46893 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17077 | /* 46897 */ // MIs[3] Operand 1 |
| 17078 | /* 46897 */ // No operand predicates |
| 17079 | /* 46897 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 17080 | /* 46899 */ // (intrinsic_wo_chain:{ *:[i32] } 4191:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 17081 | /* 46899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 17082 | /* 46902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17083 | /* 46904 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 17084 | /* 46907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 17085 | /* 46911 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 17086 | /* 46914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17087 | /* 46917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17088 | /* 46923 */ GIR_RootConstrainSelectedInstOperands, |
| 17089 | /* 46924 */ // GIR_Coverage, 2339, |
| 17090 | /* 46924 */ GIR_EraseRootFromParent_Done, |
| 17091 | /* 46925 */ // Label 1078: @46925 |
| 17092 | /* 46925 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(47009), // Rule ID 5944 // |
| 17093 | /* 46930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17094 | /* 46933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17095 | /* 46938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17096 | /* 46941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17097 | /* 46944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17098 | /* 46947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17099 | /* 46951 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17100 | /* 46955 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 17101 | /* 46959 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17102 | /* 46962 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17103 | /* 46967 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17104 | /* 46971 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17105 | /* 46976 */ // MIs[1] Rn |
| 17106 | /* 46976 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 17107 | /* 46981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17108 | /* 46985 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17109 | /* 46987 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 17110 | /* 46987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 17111 | /* 46990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17112 | /* 46992 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17113 | /* 46994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17114 | /* 46998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17115 | /* 47001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17116 | /* 47007 */ GIR_RootConstrainSelectedInstOperands, |
| 17117 | /* 47008 */ // GIR_Coverage, 5944, |
| 17118 | /* 47008 */ GIR_EraseRootFromParent_Done, |
| 17119 | /* 47009 */ // Label 1079: @47009 |
| 17120 | /* 47009 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(47093), // Rule ID 6267 // |
| 17121 | /* 47014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17122 | /* 47017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17123 | /* 47022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17124 | /* 47025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17125 | /* 47028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17126 | /* 47031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17127 | /* 47035 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17128 | /* 47039 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 17129 | /* 47043 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17130 | /* 47046 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17131 | /* 47051 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17132 | /* 47055 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17133 | /* 47060 */ // MIs[1] Rn |
| 17134 | /* 47060 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 17135 | /* 47065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17136 | /* 47069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17137 | /* 47071 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 17138 | /* 47071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 17139 | /* 47074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17140 | /* 47076 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17141 | /* 47078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17142 | /* 47082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17143 | /* 47085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17144 | /* 47091 */ GIR_RootConstrainSelectedInstOperands, |
| 17145 | /* 47092 */ // GIR_Coverage, 6267, |
| 17146 | /* 47092 */ GIR_EraseRootFromParent_Done, |
| 17147 | /* 47093 */ // Label 1080: @47093 |
| 17148 | /* 47093 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(47177), // Rule ID 108 // |
| 17149 | /* 47098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17150 | /* 47101 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17151 | /* 47106 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17152 | /* 47109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17153 | /* 47112 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17154 | /* 47115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17155 | /* 47119 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17156 | /* 47123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17157 | /* 47127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 17158 | /* 47131 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17159 | /* 47134 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17160 | /* 47139 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17161 | /* 47143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17162 | /* 47148 */ // MIs[1] Rn |
| 17163 | /* 47148 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 17164 | /* 47153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17165 | /* 47155 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 17166 | /* 47155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 17167 | /* 47158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17168 | /* 47160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17169 | /* 47162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17170 | /* 47166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17171 | /* 47169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17172 | /* 47175 */ GIR_RootConstrainSelectedInstOperands, |
| 17173 | /* 47176 */ // GIR_Coverage, 108, |
| 17174 | /* 47176 */ GIR_EraseRootFromParent_Done, |
| 17175 | /* 47177 */ // Label 1081: @47177 |
| 17176 | /* 47177 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(47261), // Rule ID 109 // |
| 17177 | /* 47182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17178 | /* 47185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 17179 | /* 47190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17180 | /* 47193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17181 | /* 47196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17182 | /* 47199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17183 | /* 47203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17184 | /* 47207 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17185 | /* 47211 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 17186 | /* 47215 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17187 | /* 47218 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17188 | /* 47223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17189 | /* 47227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17190 | /* 47232 */ // MIs[1] Rn |
| 17191 | /* 47232 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 17192 | /* 47237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17193 | /* 47239 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 17194 | /* 47239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 17195 | /* 47242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17196 | /* 47244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17197 | /* 47246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17198 | /* 47250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17199 | /* 47253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17200 | /* 47259 */ GIR_RootConstrainSelectedInstOperands, |
| 17201 | /* 47260 */ // GIR_Coverage, 109, |
| 17202 | /* 47260 */ GIR_EraseRootFromParent_Done, |
| 17203 | /* 47261 */ // Label 1082: @47261 |
| 17204 | /* 47261 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(47345), // Rule ID 2317 // |
| 17205 | /* 47266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17206 | /* 47269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17207 | /* 47274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17208 | /* 47277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17209 | /* 47280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17210 | /* 47283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17211 | /* 47287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17212 | /* 47291 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17213 | /* 47295 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 17214 | /* 47299 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17215 | /* 47302 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17216 | /* 47307 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17217 | /* 47311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17218 | /* 47316 */ // MIs[1] Rn |
| 17219 | /* 47316 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 17220 | /* 47321 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17221 | /* 47323 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 17222 | /* 47323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 17223 | /* 47326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17224 | /* 47328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17225 | /* 47330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17226 | /* 47334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17227 | /* 47337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17228 | /* 47343 */ GIR_RootConstrainSelectedInstOperands, |
| 17229 | /* 47344 */ // GIR_Coverage, 2317, |
| 17230 | /* 47344 */ GIR_EraseRootFromParent_Done, |
| 17231 | /* 47345 */ // Label 1083: @47345 |
| 17232 | /* 47345 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(47429), // Rule ID 2318 // |
| 17233 | /* 47350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17234 | /* 47353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 17235 | /* 47358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17236 | /* 47361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17237 | /* 47364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17238 | /* 47367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17239 | /* 47371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17240 | /* 47375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17241 | /* 47379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 17242 | /* 47383 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17243 | /* 47386 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17244 | /* 47391 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17245 | /* 47395 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17246 | /* 47400 */ // MIs[1] Rn |
| 17247 | /* 47400 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 17248 | /* 47405 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17249 | /* 47407 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 17250 | /* 47407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 17251 | /* 47410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17252 | /* 47412 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17253 | /* 47414 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17254 | /* 47418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17255 | /* 47421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17256 | /* 47427 */ GIR_RootConstrainSelectedInstOperands, |
| 17257 | /* 47428 */ // GIR_Coverage, 2318, |
| 17258 | /* 47428 */ GIR_EraseRootFromParent_Done, |
| 17259 | /* 47429 */ // Label 1084: @47429 |
| 17260 | /* 47429 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(47521), // Rule ID 4557 // |
| 17261 | /* 47434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 17262 | /* 47437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 17263 | /* 47442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17264 | /* 47445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17265 | /* 47448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17266 | /* 47451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17267 | /* 47455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17268 | /* 47459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17269 | /* 47463 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17270 | /* 47467 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17271 | /* 47472 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 17272 | /* 47476 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17273 | /* 47480 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17274 | /* 47484 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17275 | /* 47489 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17276 | /* 47491 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3894:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 17277 | /* 47491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 17278 | /* 47494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17279 | /* 47496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 17280 | /* 47500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 17281 | /* 47504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17282 | /* 47507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17283 | /* 47513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17284 | /* 47519 */ GIR_RootConstrainSelectedInstOperands, |
| 17285 | /* 47520 */ // GIR_Coverage, 4557, |
| 17286 | /* 47520 */ GIR_EraseRootFromParent_Done, |
| 17287 | /* 47521 */ // Label 1085: @47521 |
| 17288 | /* 47521 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(47613), // Rule ID 4560 // |
| 17289 | /* 47526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 17290 | /* 47529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 17291 | /* 47534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17292 | /* 47537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17293 | /* 47540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17294 | /* 47543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17295 | /* 47547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17296 | /* 47551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17297 | /* 47555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17298 | /* 47559 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17299 | /* 47564 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 17300 | /* 47568 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17301 | /* 47572 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17302 | /* 47576 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17303 | /* 47581 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17304 | /* 47583 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3894:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 17305 | /* 47583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 17306 | /* 47586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17307 | /* 47588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 17308 | /* 47592 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 17309 | /* 47596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17310 | /* 47599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17311 | /* 47605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17312 | /* 47611 */ GIR_RootConstrainSelectedInstOperands, |
| 17313 | /* 47612 */ // GIR_Coverage, 4560, |
| 17314 | /* 47612 */ GIR_EraseRootFromParent_Done, |
| 17315 | /* 47613 */ // Label 1086: @47613 |
| 17316 | /* 47613 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(47705), // Rule ID 4563 // |
| 17317 | /* 47618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 17318 | /* 47621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 17319 | /* 47626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17320 | /* 47629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17321 | /* 47632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17322 | /* 47635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17323 | /* 47639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17324 | /* 47643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17325 | /* 47647 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17326 | /* 47651 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17327 | /* 47656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 17328 | /* 47660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17329 | /* 47664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17330 | /* 47668 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17331 | /* 47673 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17332 | /* 47675 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3897:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 17333 | /* 47675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 17334 | /* 47678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17335 | /* 47680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 17336 | /* 47684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 17337 | /* 47688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17338 | /* 47691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17339 | /* 47697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17340 | /* 47703 */ GIR_RootConstrainSelectedInstOperands, |
| 17341 | /* 47704 */ // GIR_Coverage, 4563, |
| 17342 | /* 47704 */ GIR_EraseRootFromParent_Done, |
| 17343 | /* 47705 */ // Label 1087: @47705 |
| 17344 | /* 47705 */ GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(47797), // Rule ID 4566 // |
| 17345 | /* 47710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 17346 | /* 47713 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 17347 | /* 47718 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17348 | /* 47721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17349 | /* 47724 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17350 | /* 47727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17351 | /* 47731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17352 | /* 47735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17353 | /* 47739 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17354 | /* 47743 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17355 | /* 47748 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 17356 | /* 47752 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 17357 | /* 47756 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17358 | /* 47760 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17359 | /* 47765 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17360 | /* 47767 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3897:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 17361 | /* 47767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 17362 | /* 47770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17363 | /* 47772 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 17364 | /* 47776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 17365 | /* 47780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17366 | /* 47783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17367 | /* 47789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17368 | /* 47795 */ GIR_RootConstrainSelectedInstOperands, |
| 17369 | /* 47796 */ // GIR_Coverage, 4566, |
| 17370 | /* 47796 */ GIR_EraseRootFromParent_Done, |
| 17371 | /* 47797 */ // Label 1088: @47797 |
| 17372 | /* 47797 */ GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(47870), // Rule ID 4488 // |
| 17373 | /* 47802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17374 | /* 47805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 17375 | /* 47810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17376 | /* 47813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17377 | /* 47816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17378 | /* 47819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17379 | /* 47823 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17380 | /* 47827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17381 | /* 47831 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3867:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17382 | /* 47831 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17383 | /* 47834 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17384 | /* 47838 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17385 | /* 47843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a), |
| 17386 | /* 47846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17387 | /* 47848 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17388 | /* 47850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17389 | /* 47853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17390 | /* 47859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17391 | /* 47865 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17392 | /* 47868 */ GIR_RootConstrainSelectedInstOperands, |
| 17393 | /* 47869 */ // GIR_Coverage, 4488, |
| 17394 | /* 47869 */ GIR_EraseRootFromParent_Done, |
| 17395 | /* 47870 */ // Label 1089: @47870 |
| 17396 | /* 47870 */ GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(47943), // Rule ID 4490 // |
| 17397 | /* 47875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17398 | /* 47878 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 17399 | /* 47883 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17400 | /* 47886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17401 | /* 47889 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17402 | /* 47892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17403 | /* 47896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17404 | /* 47900 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17405 | /* 47904 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3871:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17406 | /* 47904 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17407 | /* 47907 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17408 | /* 47911 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17409 | /* 47916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n), |
| 17410 | /* 47919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17411 | /* 47921 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17412 | /* 47923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17413 | /* 47926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17414 | /* 47932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17415 | /* 47938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17416 | /* 47941 */ GIR_RootConstrainSelectedInstOperands, |
| 17417 | /* 47942 */ // GIR_Coverage, 4490, |
| 17418 | /* 47942 */ GIR_EraseRootFromParent_Done, |
| 17419 | /* 47943 */ // Label 1090: @47943 |
| 17420 | /* 47943 */ GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(48016), // Rule ID 4492 // |
| 17421 | /* 47948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17422 | /* 47951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 17423 | /* 47956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17424 | /* 47959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17425 | /* 47962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17426 | /* 47965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17427 | /* 47969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17428 | /* 47973 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17429 | /* 47977 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3873:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17430 | /* 47977 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17431 | /* 47980 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17432 | /* 47984 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17433 | /* 47989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p), |
| 17434 | /* 47992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17435 | /* 47994 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17436 | /* 47996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17437 | /* 47999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17438 | /* 48005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17439 | /* 48011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17440 | /* 48014 */ GIR_RootConstrainSelectedInstOperands, |
| 17441 | /* 48015 */ // GIR_Coverage, 4492, |
| 17442 | /* 48015 */ GIR_EraseRootFromParent_Done, |
| 17443 | /* 48016 */ // Label 1091: @48016 |
| 17444 | /* 48016 */ GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(48089), // Rule ID 4494 // |
| 17445 | /* 48021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17446 | /* 48024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 17447 | /* 48029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17448 | /* 48032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17449 | /* 48035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17450 | /* 48038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17451 | /* 48042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17452 | /* 48046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17453 | /* 48050 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17454 | /* 48050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17455 | /* 48053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17456 | /* 48057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17457 | /* 48062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m), |
| 17458 | /* 48065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17459 | /* 48067 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17460 | /* 48069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17461 | /* 48072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17462 | /* 48078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17463 | /* 48084 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17464 | /* 48087 */ GIR_RootConstrainSelectedInstOperands, |
| 17465 | /* 48088 */ // GIR_Coverage, 4494, |
| 17466 | /* 48088 */ GIR_EraseRootFromParent_Done, |
| 17467 | /* 48089 */ // Label 1092: @48089 |
| 17468 | /* 48089 */ GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(48162), // Rule ID 4496 // |
| 17469 | /* 48094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17470 | /* 48097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 17471 | /* 48102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17472 | /* 48105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17473 | /* 48108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17474 | /* 48111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17475 | /* 48115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17476 | /* 48119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17477 | /* 48123 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3867:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17478 | /* 48123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17479 | /* 48126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17480 | /* 48130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17481 | /* 48135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a), |
| 17482 | /* 48138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17483 | /* 48140 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17484 | /* 48142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17485 | /* 48145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17486 | /* 48151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17487 | /* 48157 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17488 | /* 48160 */ GIR_RootConstrainSelectedInstOperands, |
| 17489 | /* 48161 */ // GIR_Coverage, 4496, |
| 17490 | /* 48161 */ GIR_EraseRootFromParent_Done, |
| 17491 | /* 48162 */ // Label 1093: @48162 |
| 17492 | /* 48162 */ GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(48235), // Rule ID 4498 // |
| 17493 | /* 48167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17494 | /* 48170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 17495 | /* 48175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17496 | /* 48178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17497 | /* 48181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17498 | /* 48184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17499 | /* 48188 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17500 | /* 48192 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17501 | /* 48196 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3871:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17502 | /* 48196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17503 | /* 48199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17504 | /* 48203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17505 | /* 48208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n), |
| 17506 | /* 48211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17507 | /* 48213 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17508 | /* 48215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17509 | /* 48218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17510 | /* 48224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17511 | /* 48230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17512 | /* 48233 */ GIR_RootConstrainSelectedInstOperands, |
| 17513 | /* 48234 */ // GIR_Coverage, 4498, |
| 17514 | /* 48234 */ GIR_EraseRootFromParent_Done, |
| 17515 | /* 48235 */ // Label 1094: @48235 |
| 17516 | /* 48235 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(48308), // Rule ID 4500 // |
| 17517 | /* 48240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17518 | /* 48243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 17519 | /* 48248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17520 | /* 48251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17521 | /* 48254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17522 | /* 48257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17523 | /* 48261 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17524 | /* 48265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17525 | /* 48269 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3873:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17526 | /* 48269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17527 | /* 48272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17528 | /* 48276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17529 | /* 48281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p), |
| 17530 | /* 48284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17531 | /* 48286 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17532 | /* 48288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17533 | /* 48291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17534 | /* 48297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17535 | /* 48303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17536 | /* 48306 */ GIR_RootConstrainSelectedInstOperands, |
| 17537 | /* 48307 */ // GIR_Coverage, 4500, |
| 17538 | /* 48307 */ GIR_EraseRootFromParent_Done, |
| 17539 | /* 48308 */ // Label 1095: @48308 |
| 17540 | /* 48308 */ GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(48381), // Rule ID 4502 // |
| 17541 | /* 48313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17542 | /* 48316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 17543 | /* 48321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17544 | /* 48324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17545 | /* 48327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17546 | /* 48330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17547 | /* 48334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17548 | /* 48338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17549 | /* 48342 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 17550 | /* 48342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17551 | /* 48345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17552 | /* 48349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17553 | /* 48354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m), |
| 17554 | /* 48357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17555 | /* 48359 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17556 | /* 48361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17557 | /* 48364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17558 | /* 48370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17559 | /* 48376 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17560 | /* 48379 */ GIR_RootConstrainSelectedInstOperands, |
| 17561 | /* 48380 */ // GIR_Coverage, 4502, |
| 17562 | /* 48380 */ GIR_EraseRootFromParent_Done, |
| 17563 | /* 48381 */ // Label 1096: @48381 |
| 17564 | /* 48381 */ GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(48454), // Rule ID 4504 // |
| 17565 | /* 48386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17566 | /* 48389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 17567 | /* 48394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17568 | /* 48397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17569 | /* 48400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17570 | /* 48403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17571 | /* 48407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17572 | /* 48411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17573 | /* 48415 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3867:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17574 | /* 48415 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17575 | /* 48418 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17576 | /* 48422 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17577 | /* 48427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a), |
| 17578 | /* 48430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17579 | /* 48432 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17580 | /* 48434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17581 | /* 48437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17582 | /* 48443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17583 | /* 48449 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17584 | /* 48452 */ GIR_RootConstrainSelectedInstOperands, |
| 17585 | /* 48453 */ // GIR_Coverage, 4504, |
| 17586 | /* 48453 */ GIR_EraseRootFromParent_Done, |
| 17587 | /* 48454 */ // Label 1097: @48454 |
| 17588 | /* 48454 */ GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(48527), // Rule ID 4506 // |
| 17589 | /* 48459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17590 | /* 48462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 17591 | /* 48467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17592 | /* 48470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17593 | /* 48473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17594 | /* 48476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17595 | /* 48480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17596 | /* 48484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17597 | /* 48488 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3871:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17598 | /* 48488 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17599 | /* 48491 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17600 | /* 48495 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17601 | /* 48500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n), |
| 17602 | /* 48503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17603 | /* 48505 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17604 | /* 48507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17605 | /* 48510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17606 | /* 48516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17607 | /* 48522 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17608 | /* 48525 */ GIR_RootConstrainSelectedInstOperands, |
| 17609 | /* 48526 */ // GIR_Coverage, 4506, |
| 17610 | /* 48526 */ GIR_EraseRootFromParent_Done, |
| 17611 | /* 48527 */ // Label 1098: @48527 |
| 17612 | /* 48527 */ GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(48600), // Rule ID 4508 // |
| 17613 | /* 48532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17614 | /* 48535 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 17615 | /* 48540 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17616 | /* 48543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17617 | /* 48546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17618 | /* 48549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17619 | /* 48553 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17620 | /* 48557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17621 | /* 48561 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3873:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17622 | /* 48561 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17623 | /* 48564 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17624 | /* 48568 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17625 | /* 48573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p), |
| 17626 | /* 48576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17627 | /* 48578 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17628 | /* 48580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17629 | /* 48583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17630 | /* 48589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17631 | /* 48595 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17632 | /* 48598 */ GIR_RootConstrainSelectedInstOperands, |
| 17633 | /* 48599 */ // GIR_Coverage, 4508, |
| 17634 | /* 48599 */ GIR_EraseRootFromParent_Done, |
| 17635 | /* 48600 */ // Label 1099: @48600 |
| 17636 | /* 48600 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(48673), // Rule ID 4510 // |
| 17637 | /* 48605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17638 | /* 48608 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 17639 | /* 48613 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17640 | /* 48616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17641 | /* 48619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17642 | /* 48622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17643 | /* 48626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 17644 | /* 48630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17645 | /* 48634 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17646 | /* 48634 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17647 | /* 48637 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17648 | /* 48641 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17649 | /* 48646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m), |
| 17650 | /* 48649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17651 | /* 48651 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17652 | /* 48653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17653 | /* 48656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17654 | /* 48662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17655 | /* 48668 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17656 | /* 48671 */ GIR_RootConstrainSelectedInstOperands, |
| 17657 | /* 48672 */ // GIR_Coverage, 4510, |
| 17658 | /* 48672 */ GIR_EraseRootFromParent_Done, |
| 17659 | /* 48673 */ // Label 1100: @48673 |
| 17660 | /* 48673 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(48746), // Rule ID 4512 // |
| 17661 | /* 48678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17662 | /* 48681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 17663 | /* 48686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17664 | /* 48689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17665 | /* 48692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17666 | /* 48695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17667 | /* 48699 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17668 | /* 48703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17669 | /* 48707 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3867:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17670 | /* 48707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17671 | /* 48710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17672 | /* 48714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17673 | /* 48719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a), |
| 17674 | /* 48722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17675 | /* 48724 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17676 | /* 48726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17677 | /* 48729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17678 | /* 48735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17679 | /* 48741 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17680 | /* 48744 */ GIR_RootConstrainSelectedInstOperands, |
| 17681 | /* 48745 */ // GIR_Coverage, 4512, |
| 17682 | /* 48745 */ GIR_EraseRootFromParent_Done, |
| 17683 | /* 48746 */ // Label 1101: @48746 |
| 17684 | /* 48746 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(48819), // Rule ID 4514 // |
| 17685 | /* 48751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17686 | /* 48754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 17687 | /* 48759 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17688 | /* 48762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17689 | /* 48765 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17690 | /* 48768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17691 | /* 48772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17692 | /* 48776 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17693 | /* 48780 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3871:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17694 | /* 48780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17695 | /* 48783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17696 | /* 48787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17697 | /* 48792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n), |
| 17698 | /* 48795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17699 | /* 48797 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17700 | /* 48799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17701 | /* 48802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17702 | /* 48808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17703 | /* 48814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17704 | /* 48817 */ GIR_RootConstrainSelectedInstOperands, |
| 17705 | /* 48818 */ // GIR_Coverage, 4514, |
| 17706 | /* 48818 */ GIR_EraseRootFromParent_Done, |
| 17707 | /* 48819 */ // Label 1102: @48819 |
| 17708 | /* 48819 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(48892), // Rule ID 4516 // |
| 17709 | /* 48824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17710 | /* 48827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 17711 | /* 48832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17712 | /* 48835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17713 | /* 48838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17714 | /* 48841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17715 | /* 48845 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17716 | /* 48849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17717 | /* 48853 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3873:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17718 | /* 48853 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17719 | /* 48856 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17720 | /* 48860 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17721 | /* 48865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p), |
| 17722 | /* 48868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17723 | /* 48870 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17724 | /* 48872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17725 | /* 48875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17726 | /* 48881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17727 | /* 48887 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17728 | /* 48890 */ GIR_RootConstrainSelectedInstOperands, |
| 17729 | /* 48891 */ // GIR_Coverage, 4516, |
| 17730 | /* 48891 */ GIR_EraseRootFromParent_Done, |
| 17731 | /* 48892 */ // Label 1103: @48892 |
| 17732 | /* 48892 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(48965), // Rule ID 4518 // |
| 17733 | /* 48897 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17734 | /* 48900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 17735 | /* 48905 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17736 | /* 48908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17737 | /* 48911 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17738 | /* 48914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17739 | /* 48918 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 17740 | /* 48922 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17741 | /* 48926 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 17742 | /* 48926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17743 | /* 48929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17744 | /* 48933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17745 | /* 48938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m), |
| 17746 | /* 48941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17747 | /* 48943 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 17748 | /* 48945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17749 | /* 48948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17750 | /* 48954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17751 | /* 48960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17752 | /* 48963 */ GIR_RootConstrainSelectedInstOperands, |
| 17753 | /* 48964 */ // GIR_Coverage, 4518, |
| 17754 | /* 48964 */ GIR_EraseRootFromParent_Done, |
| 17755 | /* 48965 */ // Label 1104: @48965 |
| 17756 | /* 48965 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(49038), // Rule ID 4521 // |
| 17757 | /* 48970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17758 | /* 48973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp), |
| 17759 | /* 48978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17760 | /* 48981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17761 | /* 48984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17762 | /* 48987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17763 | /* 48991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17764 | /* 48995 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17765 | /* 48999 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3862:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 17766 | /* 48999 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17767 | /* 49002 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17768 | /* 49006 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17769 | /* 49011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 17770 | /* 49014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17771 | /* 49016 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17772 | /* 49018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17773 | /* 49021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17774 | /* 49027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17775 | /* 49033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17776 | /* 49036 */ GIR_RootConstrainSelectedInstOperands, |
| 17777 | /* 49037 */ // GIR_Coverage, 4521, |
| 17778 | /* 49037 */ GIR_EraseRootFromParent_Done, |
| 17779 | /* 49038 */ // Label 1105: @49038 |
| 17780 | /* 49038 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(49111), // Rule ID 4524 // |
| 17781 | /* 49043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17782 | /* 49046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp), |
| 17783 | /* 49051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17784 | /* 49054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17785 | /* 49057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17786 | /* 49060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17787 | /* 49064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17788 | /* 49068 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17789 | /* 49072 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3862:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 17790 | /* 49072 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17791 | /* 49075 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17792 | /* 49079 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17793 | /* 49084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 17794 | /* 49087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17795 | /* 49089 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17796 | /* 49091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17797 | /* 49094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17798 | /* 49100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17799 | /* 49106 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17800 | /* 49109 */ GIR_RootConstrainSelectedInstOperands, |
| 17801 | /* 49110 */ // GIR_Coverage, 4524, |
| 17802 | /* 49110 */ GIR_EraseRootFromParent_Done, |
| 17803 | /* 49111 */ // Label 1106: @49111 |
| 17804 | /* 49111 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(49184), // Rule ID 4527 // |
| 17805 | /* 49116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17806 | /* 49119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp), |
| 17807 | /* 49124 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17808 | /* 49127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17809 | /* 49130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17810 | /* 49133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17811 | /* 49137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17812 | /* 49141 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17813 | /* 49145 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3862:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 17814 | /* 49145 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17815 | /* 49148 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17816 | /* 49152 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17817 | /* 49157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 17818 | /* 49160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17819 | /* 49162 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17820 | /* 49164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17821 | /* 49167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17822 | /* 49173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17823 | /* 49179 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17824 | /* 49182 */ GIR_RootConstrainSelectedInstOperands, |
| 17825 | /* 49183 */ // GIR_Coverage, 4527, |
| 17826 | /* 49183 */ GIR_EraseRootFromParent_Done, |
| 17827 | /* 49184 */ // Label 1107: @49184 |
| 17828 | /* 49184 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(49257), // Rule ID 4530 // |
| 17829 | /* 49189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17830 | /* 49192 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp), |
| 17831 | /* 49197 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17832 | /* 49200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17833 | /* 49203 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17834 | /* 49206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17835 | /* 49210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17836 | /* 49214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17837 | /* 49218 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3862:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 17838 | /* 49218 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17839 | /* 49221 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17840 | /* 49225 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17841 | /* 49230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 17842 | /* 49233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17843 | /* 49235 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17844 | /* 49237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17845 | /* 49240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17846 | /* 49246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17847 | /* 49252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17848 | /* 49255 */ GIR_RootConstrainSelectedInstOperands, |
| 17849 | /* 49256 */ // GIR_Coverage, 4530, |
| 17850 | /* 49256 */ GIR_EraseRootFromParent_Done, |
| 17851 | /* 49257 */ // Label 1108: @49257 |
| 17852 | /* 49257 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(49330), // Rule ID 4533 // |
| 17853 | /* 49262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17854 | /* 49265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int), |
| 17855 | /* 49270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17856 | /* 49273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17857 | /* 49276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17858 | /* 49279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17859 | /* 49283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17860 | /* 49287 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17861 | /* 49291 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3860:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 17862 | /* 49291 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17863 | /* 49294 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17864 | /* 49298 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17865 | /* 49303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 17866 | /* 49306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17867 | /* 49308 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17868 | /* 49310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17869 | /* 49313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17870 | /* 49319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17871 | /* 49325 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17872 | /* 49328 */ GIR_RootConstrainSelectedInstOperands, |
| 17873 | /* 49329 */ // GIR_Coverage, 4533, |
| 17874 | /* 49329 */ GIR_EraseRootFromParent_Done, |
| 17875 | /* 49330 */ // Label 1109: @49330 |
| 17876 | /* 49330 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(49403), // Rule ID 4536 // |
| 17877 | /* 49335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17878 | /* 49338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int), |
| 17879 | /* 49343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17880 | /* 49346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17881 | /* 49349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17882 | /* 49352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17883 | /* 49356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17884 | /* 49360 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17885 | /* 49364 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3860:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 17886 | /* 49364 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17887 | /* 49367 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17888 | /* 49371 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17889 | /* 49376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 17890 | /* 49379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17891 | /* 49381 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17892 | /* 49383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17893 | /* 49386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17894 | /* 49392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17895 | /* 49398 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17896 | /* 49401 */ GIR_RootConstrainSelectedInstOperands, |
| 17897 | /* 49402 */ // GIR_Coverage, 4536, |
| 17898 | /* 49402 */ GIR_EraseRootFromParent_Done, |
| 17899 | /* 49403 */ // Label 1110: @49403 |
| 17900 | /* 49403 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(49476), // Rule ID 4539 // |
| 17901 | /* 49408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17902 | /* 49411 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int), |
| 17903 | /* 49416 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17904 | /* 49419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17905 | /* 49422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17906 | /* 49425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17907 | /* 49429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17908 | /* 49433 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17909 | /* 49437 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3860:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 17910 | /* 49437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17911 | /* 49440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17912 | /* 49444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17913 | /* 49449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 17914 | /* 49452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17915 | /* 49454 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17916 | /* 49456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17917 | /* 49459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17918 | /* 49465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17919 | /* 49471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17920 | /* 49474 */ GIR_RootConstrainSelectedInstOperands, |
| 17921 | /* 49475 */ // GIR_Coverage, 4539, |
| 17922 | /* 49475 */ GIR_EraseRootFromParent_Done, |
| 17923 | /* 49476 */ // Label 1111: @49476 |
| 17924 | /* 49476 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(49549), // Rule ID 4542 // |
| 17925 | /* 49481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17926 | /* 49484 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int), |
| 17927 | /* 49489 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17928 | /* 49492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17929 | /* 49495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17930 | /* 49498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17931 | /* 49502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17932 | /* 49506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17933 | /* 49510 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3860:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 17934 | /* 49510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17935 | /* 49513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17936 | /* 49517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17937 | /* 49522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 17938 | /* 49525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17939 | /* 49527 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17940 | /* 49529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17941 | /* 49532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17942 | /* 49538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17943 | /* 49544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17944 | /* 49547 */ GIR_RootConstrainSelectedInstOperands, |
| 17945 | /* 49548 */ // GIR_Coverage, 4542, |
| 17946 | /* 49548 */ GIR_EraseRootFromParent_Done, |
| 17947 | /* 49549 */ // Label 1112: @49549 |
| 17948 | /* 49549 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(49622), // Rule ID 5022 // |
| 17949 | /* 49554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17950 | /* 49557 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 17951 | /* 49562 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17952 | /* 49565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17953 | /* 49568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17954 | /* 49571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17955 | /* 49575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17956 | /* 49579 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17957 | /* 49583 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3865:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 17958 | /* 49583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17959 | /* 49586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17960 | /* 49590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17961 | /* 49595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh), |
| 17962 | /* 49598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17963 | /* 49600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 17964 | /* 49602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17965 | /* 49605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17966 | /* 49611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17967 | /* 49617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17968 | /* 49620 */ GIR_RootConstrainSelectedInstOperands, |
| 17969 | /* 49621 */ // GIR_Coverage, 5022, |
| 17970 | /* 49621 */ GIR_EraseRootFromParent_Done, |
| 17971 | /* 49622 */ // Label 1113: @49622 |
| 17972 | /* 49622 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(49695), // Rule ID 5028 // |
| 17973 | /* 49627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 17974 | /* 49630 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 17975 | /* 49635 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17976 | /* 49638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17977 | /* 49641 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17978 | /* 49644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17979 | /* 49648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17980 | /* 49652 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17981 | /* 49656 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3865:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 17982 | /* 49656 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17983 | /* 49659 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17984 | /* 49663 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17985 | /* 49668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th), |
| 17986 | /* 49671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17987 | /* 49673 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 17988 | /* 49675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17989 | /* 49678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17990 | /* 49684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17991 | /* 49690 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17992 | /* 49693 */ GIR_RootConstrainSelectedInstOperands, |
| 17993 | /* 49694 */ // GIR_Coverage, 5028, |
| 17994 | /* 49694 */ GIR_EraseRootFromParent_Done, |
| 17995 | /* 49695 */ // Label 1114: @49695 |
| 17996 | /* 49695 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(49763), // Rule ID 2066 // |
| 17997 | /* 49700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 17998 | /* 49703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 17999 | /* 49708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18000 | /* 49711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18001 | /* 49714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18002 | /* 49717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18003 | /* 49721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18004 | /* 49725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18005 | /* 49729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18006 | /* 49733 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 18007 | /* 49737 */ // MIs[1] Operand 1 |
| 18008 | /* 49737 */ // No operand predicates |
| 18009 | /* 49737 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18010 | /* 49739 */ // (intrinsic_wo_chain:{ *:[i32] } 4191:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 18011 | /* 49739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 18012 | /* 49742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18013 | /* 49744 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 18014 | /* 49747 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 18015 | /* 49749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18016 | /* 49752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18017 | /* 49755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18018 | /* 49761 */ GIR_RootConstrainSelectedInstOperands, |
| 18019 | /* 49762 */ // GIR_Coverage, 2066, |
| 18020 | /* 49762 */ GIR_EraseRootFromParent_Done, |
| 18021 | /* 49763 */ // Label 1115: @49763 |
| 18022 | /* 49763 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(49828), // Rule ID 2070 // |
| 18023 | /* 49768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 18024 | /* 49771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 18025 | /* 49776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18026 | /* 49779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18027 | /* 49782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18028 | /* 49785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18029 | /* 49789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18030 | /* 49793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18031 | /* 49797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18032 | /* 49801 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 18033 | /* 49805 */ // MIs[1] Operand 1 |
| 18034 | /* 49805 */ // No operand predicates |
| 18035 | /* 49805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18036 | /* 49807 */ // (intrinsic_wo_chain:{ *:[i32] } 4192:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a) |
| 18037 | /* 49807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16), |
| 18038 | /* 49810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18039 | /* 49812 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 18040 | /* 49815 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 18041 | /* 49817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18042 | /* 49820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18043 | /* 49826 */ GIR_RootConstrainSelectedInstOperands, |
| 18044 | /* 49827 */ // GIR_Coverage, 2070, |
| 18045 | /* 49827 */ GIR_EraseRootFromParent_Done, |
| 18046 | /* 49828 */ // Label 1116: @49828 |
| 18047 | /* 49828 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(49896), // Rule ID 2334 // |
| 18048 | /* 49833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 18049 | /* 49836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 18050 | /* 49841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18051 | /* 49844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18052 | /* 49847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18053 | /* 49850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18054 | /* 49854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18055 | /* 49858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18056 | /* 49862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18057 | /* 49866 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 18058 | /* 49870 */ // MIs[1] Operand 1 |
| 18059 | /* 49870 */ // No operand predicates |
| 18060 | /* 49870 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18061 | /* 49872 */ // (intrinsic_wo_chain:{ *:[i32] } 4191:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 18062 | /* 49872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 18063 | /* 49875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18064 | /* 49877 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 18065 | /* 49880 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 18066 | /* 49882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18067 | /* 49885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18068 | /* 49888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18069 | /* 49894 */ GIR_RootConstrainSelectedInstOperands, |
| 18070 | /* 49895 */ // GIR_Coverage, 2334, |
| 18071 | /* 49895 */ GIR_EraseRootFromParent_Done, |
| 18072 | /* 49896 */ // Label 1117: @49896 |
| 18073 | /* 49896 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(49961), // Rule ID 2336 // |
| 18074 | /* 49901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 18075 | /* 49904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 18076 | /* 49909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18077 | /* 49912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18078 | /* 49915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18079 | /* 49918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18080 | /* 49922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18081 | /* 49926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18082 | /* 49930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18083 | /* 49934 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 18084 | /* 49938 */ // MIs[1] Operand 1 |
| 18085 | /* 49938 */ // No operand predicates |
| 18086 | /* 49938 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18087 | /* 49940 */ // (intrinsic_wo_chain:{ *:[i32] } 4192:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a) |
| 18088 | /* 49940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16), |
| 18089 | /* 49943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18090 | /* 49945 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 18091 | /* 49948 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 18092 | /* 49950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18093 | /* 49953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18094 | /* 49959 */ GIR_RootConstrainSelectedInstOperands, |
| 18095 | /* 49960 */ // GIR_Coverage, 2336, |
| 18096 | /* 49960 */ GIR_EraseRootFromParent_Done, |
| 18097 | /* 49961 */ // Label 1118: @49961 |
| 18098 | /* 49961 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(50044), // Rule ID 4310 // |
| 18099 | /* 49966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 18100 | /* 49971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18101 | /* 49974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18102 | /* 49977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18103 | /* 49980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 18104 | /* 49984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 18105 | /* 49988 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18106 | /* 49992 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18107 | /* 49996 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 18108 | /* 50000 */ // MIs[1] Operand 1 |
| 18109 | /* 50000 */ // No operand predicates |
| 18110 | /* 50000 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18111 | /* 50002 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3929:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 18112 | /* 50002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 18113 | /* 50005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 18114 | /* 50009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 18115 | /* 50014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8), |
| 18116 | /* 50017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 18117 | /* 50019 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 18118 | /* 50021 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18119 | /* 50024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18120 | /* 50027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18121 | /* 50033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18122 | /* 50039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18123 | /* 50042 */ GIR_RootConstrainSelectedInstOperands, |
| 18124 | /* 50043 */ // GIR_Coverage, 4310, |
| 18125 | /* 50043 */ GIR_EraseRootFromParent_Done, |
| 18126 | /* 50044 */ // Label 1119: @50044 |
| 18127 | /* 50044 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(50127), // Rule ID 4312 // |
| 18128 | /* 50049 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 18129 | /* 50054 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18130 | /* 50057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18131 | /* 50060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18132 | /* 50063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 18133 | /* 50067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 18134 | /* 50071 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18135 | /* 50075 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18136 | /* 50079 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 18137 | /* 50083 */ // MIs[1] Operand 1 |
| 18138 | /* 50083 */ // No operand predicates |
| 18139 | /* 50083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18140 | /* 50085 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3929:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 18141 | /* 50085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 18142 | /* 50088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 18143 | /* 50092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 18144 | /* 50097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16), |
| 18145 | /* 50100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 18146 | /* 50102 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 18147 | /* 50104 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18148 | /* 50107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18149 | /* 50110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18150 | /* 50116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18151 | /* 50122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18152 | /* 50125 */ GIR_RootConstrainSelectedInstOperands, |
| 18153 | /* 50126 */ // GIR_Coverage, 4312, |
| 18154 | /* 50126 */ GIR_EraseRootFromParent_Done, |
| 18155 | /* 50127 */ // Label 1120: @50127 |
| 18156 | /* 50127 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(50210), // Rule ID 4314 // |
| 18157 | /* 50132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 18158 | /* 50137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18159 | /* 50140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18160 | /* 50143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18161 | /* 50146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 18162 | /* 50150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 18163 | /* 50154 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18164 | /* 50158 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18165 | /* 50162 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 18166 | /* 50166 */ // MIs[1] Operand 1 |
| 18167 | /* 50166 */ // No operand predicates |
| 18168 | /* 50166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18169 | /* 50168 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3929:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 18170 | /* 50168 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 18171 | /* 50171 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 18172 | /* 50175 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 18173 | /* 50180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32), |
| 18174 | /* 50183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 18175 | /* 50185 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 18176 | /* 50187 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18177 | /* 50190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18178 | /* 50193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18179 | /* 50199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18180 | /* 50205 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18181 | /* 50208 */ GIR_RootConstrainSelectedInstOperands, |
| 18182 | /* 50209 */ // GIR_Coverage, 4314, |
| 18183 | /* 50209 */ GIR_EraseRootFromParent_Done, |
| 18184 | /* 50210 */ // Label 1121: @50210 |
| 18185 | /* 50210 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(50271), // Rule ID 1813 // |
| 18186 | /* 50215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18187 | /* 50218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 18188 | /* 50223 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18189 | /* 50226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18190 | /* 50229 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18191 | /* 50232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18192 | /* 50236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18193 | /* 50240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18194 | /* 50244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18195 | /* 50248 */ // MIs[1] Operand 1 |
| 18196 | /* 50248 */ // No operand predicates |
| 18197 | /* 50248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18198 | /* 50250 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4013:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18199 | /* 50250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd), |
| 18200 | /* 50253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18201 | /* 50255 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18202 | /* 50257 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18203 | /* 50260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18204 | /* 50263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18205 | /* 50269 */ GIR_RootConstrainSelectedInstOperands, |
| 18206 | /* 50270 */ // GIR_Coverage, 1813, |
| 18207 | /* 50270 */ GIR_EraseRootFromParent_Done, |
| 18208 | /* 50271 */ // Label 1122: @50271 |
| 18209 | /* 50271 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(50332), // Rule ID 1814 // |
| 18210 | /* 50276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18211 | /* 50279 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 18212 | /* 50284 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18213 | /* 50287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18214 | /* 50290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18215 | /* 50293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18216 | /* 50297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18217 | /* 50301 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18218 | /* 50305 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18219 | /* 50309 */ // MIs[1] Operand 1 |
| 18220 | /* 50309 */ // No operand predicates |
| 18221 | /* 50309 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18222 | /* 50311 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4014:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18223 | /* 50311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud), |
| 18224 | /* 50314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18225 | /* 50316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18226 | /* 50318 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18227 | /* 50321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18228 | /* 50324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18229 | /* 50330 */ GIR_RootConstrainSelectedInstOperands, |
| 18230 | /* 50331 */ // GIR_Coverage, 1814, |
| 18231 | /* 50331 */ GIR_EraseRootFromParent_Done, |
| 18232 | /* 50332 */ // Label 1123: @50332 |
| 18233 | /* 50332 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(50393), // Rule ID 1815 // |
| 18234 | /* 50337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18235 | /* 50340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 18236 | /* 50345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18237 | /* 50348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18238 | /* 50351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18239 | /* 50354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18240 | /* 50358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18241 | /* 50362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18242 | /* 50366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18243 | /* 50370 */ // MIs[1] Operand 1 |
| 18244 | /* 50370 */ // No operand predicates |
| 18245 | /* 50370 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18246 | /* 50372 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18247 | /* 50372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd), |
| 18248 | /* 50375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18249 | /* 50377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18250 | /* 50379 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18251 | /* 50382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18252 | /* 50385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18253 | /* 50391 */ GIR_RootConstrainSelectedInstOperands, |
| 18254 | /* 50392 */ // GIR_Coverage, 1815, |
| 18255 | /* 50392 */ GIR_EraseRootFromParent_Done, |
| 18256 | /* 50393 */ // Label 1124: @50393 |
| 18257 | /* 50393 */ GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(50454), // Rule ID 1816 // |
| 18258 | /* 50398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18259 | /* 50401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 18260 | /* 50406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18261 | /* 50409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18262 | /* 50412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18263 | /* 50415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18264 | /* 50419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18265 | /* 50423 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18266 | /* 50427 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18267 | /* 50431 */ // MIs[1] Operand 1 |
| 18268 | /* 50431 */ // No operand predicates |
| 18269 | /* 50431 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18270 | /* 50433 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18271 | /* 50433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd), |
| 18272 | /* 50436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18273 | /* 50438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18274 | /* 50440 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18275 | /* 50443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18276 | /* 50446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18277 | /* 50452 */ GIR_RootConstrainSelectedInstOperands, |
| 18278 | /* 50453 */ // GIR_Coverage, 1816, |
| 18279 | /* 50453 */ GIR_EraseRootFromParent_Done, |
| 18280 | /* 50454 */ // Label 1125: @50454 |
| 18281 | /* 50454 */ GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(50515), // Rule ID 1817 // |
| 18282 | /* 50459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18283 | /* 50462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 18284 | /* 50467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18285 | /* 50470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18286 | /* 50473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18287 | /* 50476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18288 | /* 50480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18289 | /* 50484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18290 | /* 50488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18291 | /* 50492 */ // MIs[1] Operand 1 |
| 18292 | /* 50492 */ // No operand predicates |
| 18293 | /* 50492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18294 | /* 50494 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4013:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18295 | /* 50494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd), |
| 18296 | /* 50497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18297 | /* 50499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18298 | /* 50501 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18299 | /* 50504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18300 | /* 50507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18301 | /* 50513 */ GIR_RootConstrainSelectedInstOperands, |
| 18302 | /* 50514 */ // GIR_Coverage, 1817, |
| 18303 | /* 50514 */ GIR_EraseRootFromParent_Done, |
| 18304 | /* 50515 */ // Label 1126: @50515 |
| 18305 | /* 50515 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(50576), // Rule ID 1818 // |
| 18306 | /* 50520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18307 | /* 50523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 18308 | /* 50528 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18309 | /* 50531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18310 | /* 50534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18311 | /* 50537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18312 | /* 50541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18313 | /* 50545 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18314 | /* 50549 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18315 | /* 50553 */ // MIs[1] Operand 1 |
| 18316 | /* 50553 */ // No operand predicates |
| 18317 | /* 50553 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18318 | /* 50555 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4014:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18319 | /* 50555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud), |
| 18320 | /* 50558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18321 | /* 50560 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18322 | /* 50562 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18323 | /* 50565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18324 | /* 50568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18325 | /* 50574 */ GIR_RootConstrainSelectedInstOperands, |
| 18326 | /* 50575 */ // GIR_Coverage, 1818, |
| 18327 | /* 50575 */ GIR_EraseRootFromParent_Done, |
| 18328 | /* 50576 */ // Label 1127: @50576 |
| 18329 | /* 50576 */ GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(50637), // Rule ID 1819 // |
| 18330 | /* 50581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18331 | /* 50584 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 18332 | /* 50589 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18333 | /* 50592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18334 | /* 50595 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18335 | /* 50598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18336 | /* 50602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18337 | /* 50606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18338 | /* 50610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18339 | /* 50614 */ // MIs[1] Operand 1 |
| 18340 | /* 50614 */ // No operand predicates |
| 18341 | /* 50614 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18342 | /* 50616 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18343 | /* 50616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd), |
| 18344 | /* 50619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18345 | /* 50621 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18346 | /* 50623 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18347 | /* 50626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18348 | /* 50629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18349 | /* 50635 */ GIR_RootConstrainSelectedInstOperands, |
| 18350 | /* 50636 */ // GIR_Coverage, 1819, |
| 18351 | /* 50636 */ GIR_EraseRootFromParent_Done, |
| 18352 | /* 50637 */ // Label 1128: @50637 |
| 18353 | /* 50637 */ GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(50698), // Rule ID 1820 // |
| 18354 | /* 50642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18355 | /* 50645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 18356 | /* 50650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18357 | /* 50653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18358 | /* 50656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18359 | /* 50659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18360 | /* 50663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18361 | /* 50667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18362 | /* 50671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18363 | /* 50675 */ // MIs[1] Operand 1 |
| 18364 | /* 50675 */ // No operand predicates |
| 18365 | /* 50675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18366 | /* 50677 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18367 | /* 50677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd), |
| 18368 | /* 50680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18369 | /* 50682 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18370 | /* 50684 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18371 | /* 50687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18372 | /* 50690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18373 | /* 50696 */ GIR_RootConstrainSelectedInstOperands, |
| 18374 | /* 50697 */ // GIR_Coverage, 1820, |
| 18375 | /* 50697 */ GIR_EraseRootFromParent_Done, |
| 18376 | /* 50698 */ // Label 1129: @50698 |
| 18377 | /* 50698 */ GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(50759), // Rule ID 1821 // |
| 18378 | /* 50703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18379 | /* 50706 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 18380 | /* 50711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18381 | /* 50714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18382 | /* 50717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18383 | /* 50720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18384 | /* 50724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18385 | /* 50728 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18386 | /* 50732 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18387 | /* 50736 */ // MIs[1] Operand 1 |
| 18388 | /* 50736 */ // No operand predicates |
| 18389 | /* 50736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18390 | /* 50738 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4013:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18391 | /* 50738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq), |
| 18392 | /* 50741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18393 | /* 50743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18394 | /* 50745 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18395 | /* 50748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18396 | /* 50751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18397 | /* 50757 */ GIR_RootConstrainSelectedInstOperands, |
| 18398 | /* 50758 */ // GIR_Coverage, 1821, |
| 18399 | /* 50758 */ GIR_EraseRootFromParent_Done, |
| 18400 | /* 50759 */ // Label 1130: @50759 |
| 18401 | /* 50759 */ GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(50820), // Rule ID 1822 // |
| 18402 | /* 50764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18403 | /* 50767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 18404 | /* 50772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18405 | /* 50775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18406 | /* 50778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18407 | /* 50781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18408 | /* 50785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18409 | /* 50789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18410 | /* 50793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18411 | /* 50797 */ // MIs[1] Operand 1 |
| 18412 | /* 50797 */ // No operand predicates |
| 18413 | /* 50797 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18414 | /* 50799 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4014:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18415 | /* 50799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq), |
| 18416 | /* 50802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18417 | /* 50804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18418 | /* 50806 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18419 | /* 50809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18420 | /* 50812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18421 | /* 50818 */ GIR_RootConstrainSelectedInstOperands, |
| 18422 | /* 50819 */ // GIR_Coverage, 1822, |
| 18423 | /* 50819 */ GIR_EraseRootFromParent_Done, |
| 18424 | /* 50820 */ // Label 1131: @50820 |
| 18425 | /* 50820 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(50881), // Rule ID 1823 // |
| 18426 | /* 50825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18427 | /* 50828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 18428 | /* 50833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18429 | /* 50836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18430 | /* 50839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18431 | /* 50842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18432 | /* 50846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18433 | /* 50850 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18434 | /* 50854 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18435 | /* 50858 */ // MIs[1] Operand 1 |
| 18436 | /* 50858 */ // No operand predicates |
| 18437 | /* 50858 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18438 | /* 50860 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4016:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18439 | /* 50860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq), |
| 18440 | /* 50863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18441 | /* 50865 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18442 | /* 50867 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18443 | /* 50870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18444 | /* 50873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18445 | /* 50879 */ GIR_RootConstrainSelectedInstOperands, |
| 18446 | /* 50880 */ // GIR_Coverage, 1823, |
| 18447 | /* 50880 */ GIR_EraseRootFromParent_Done, |
| 18448 | /* 50881 */ // Label 1132: @50881 |
| 18449 | /* 50881 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(50942), // Rule ID 1824 // |
| 18450 | /* 50886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18451 | /* 50889 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 18452 | /* 50894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18453 | /* 50897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18454 | /* 50900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18455 | /* 50903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18456 | /* 50907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18457 | /* 50911 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18458 | /* 50915 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18459 | /* 50919 */ // MIs[1] Operand 1 |
| 18460 | /* 50919 */ // No operand predicates |
| 18461 | /* 50919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18462 | /* 50921 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4017:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18463 | /* 50921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq), |
| 18464 | /* 50924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18465 | /* 50926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18466 | /* 50928 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18467 | /* 50931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18468 | /* 50934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18469 | /* 50940 */ GIR_RootConstrainSelectedInstOperands, |
| 18470 | /* 50941 */ // GIR_Coverage, 1824, |
| 18471 | /* 50941 */ GIR_EraseRootFromParent_Done, |
| 18472 | /* 50942 */ // Label 1133: @50942 |
| 18473 | /* 50942 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(51003), // Rule ID 1825 // |
| 18474 | /* 50947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18475 | /* 50950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 18476 | /* 50955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18477 | /* 50958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18478 | /* 50961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18479 | /* 50964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18480 | /* 50968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18481 | /* 50972 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18482 | /* 50976 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18483 | /* 50980 */ // MIs[1] Operand 1 |
| 18484 | /* 50980 */ // No operand predicates |
| 18485 | /* 50980 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18486 | /* 50982 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4013:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18487 | /* 50982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq), |
| 18488 | /* 50985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18489 | /* 50987 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18490 | /* 50989 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18491 | /* 50992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18492 | /* 50995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18493 | /* 51001 */ GIR_RootConstrainSelectedInstOperands, |
| 18494 | /* 51002 */ // GIR_Coverage, 1825, |
| 18495 | /* 51002 */ GIR_EraseRootFromParent_Done, |
| 18496 | /* 51003 */ // Label 1134: @51003 |
| 18497 | /* 51003 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(51064), // Rule ID 1826 // |
| 18498 | /* 51008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18499 | /* 51011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 18500 | /* 51016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18501 | /* 51019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18502 | /* 51022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18503 | /* 51025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18504 | /* 51029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18505 | /* 51033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18506 | /* 51037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18507 | /* 51041 */ // MIs[1] Operand 1 |
| 18508 | /* 51041 */ // No operand predicates |
| 18509 | /* 51041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18510 | /* 51043 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4014:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18511 | /* 51043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq), |
| 18512 | /* 51046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18513 | /* 51048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18514 | /* 51050 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18515 | /* 51053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18516 | /* 51056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18517 | /* 51062 */ GIR_RootConstrainSelectedInstOperands, |
| 18518 | /* 51063 */ // GIR_Coverage, 1826, |
| 18519 | /* 51063 */ GIR_EraseRootFromParent_Done, |
| 18520 | /* 51064 */ // Label 1135: @51064 |
| 18521 | /* 51064 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(51125), // Rule ID 1827 // |
| 18522 | /* 51069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18523 | /* 51072 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 18524 | /* 51077 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18525 | /* 51080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18526 | /* 51083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18527 | /* 51086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18528 | /* 51090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18529 | /* 51094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18530 | /* 51098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18531 | /* 51102 */ // MIs[1] Operand 1 |
| 18532 | /* 51102 */ // No operand predicates |
| 18533 | /* 51102 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18534 | /* 51104 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4016:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18535 | /* 51104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq), |
| 18536 | /* 51107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18537 | /* 51109 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18538 | /* 51111 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18539 | /* 51114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18540 | /* 51117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18541 | /* 51123 */ GIR_RootConstrainSelectedInstOperands, |
| 18542 | /* 51124 */ // GIR_Coverage, 1827, |
| 18543 | /* 51124 */ GIR_EraseRootFromParent_Done, |
| 18544 | /* 51125 */ // Label 1136: @51125 |
| 18545 | /* 51125 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(51186), // Rule ID 1828 // |
| 18546 | /* 51130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18547 | /* 51133 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 18548 | /* 51138 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18549 | /* 51141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18550 | /* 51144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18551 | /* 51147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18552 | /* 51151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18553 | /* 51155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18554 | /* 51159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18555 | /* 51163 */ // MIs[1] Operand 1 |
| 18556 | /* 51163 */ // No operand predicates |
| 18557 | /* 51163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18558 | /* 51165 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4017:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 18559 | /* 51165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq), |
| 18560 | /* 51168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18561 | /* 51170 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 18562 | /* 51172 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 18563 | /* 51175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18564 | /* 51178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18565 | /* 51184 */ GIR_RootConstrainSelectedInstOperands, |
| 18566 | /* 51185 */ // GIR_Coverage, 1828, |
| 18567 | /* 51185 */ GIR_EraseRootFromParent_Done, |
| 18568 | /* 51186 */ // Label 1137: @51186 |
| 18569 | /* 51186 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(51247), // Rule ID 1910 // |
| 18570 | /* 51191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 18571 | /* 51194 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl), |
| 18572 | /* 51199 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18573 | /* 51202 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18574 | /* 51205 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18575 | /* 51208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18576 | /* 51212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18577 | /* 51216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18578 | /* 51220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18579 | /* 51224 */ // MIs[1] Operand 1 |
| 18580 | /* 51224 */ // No operand predicates |
| 18581 | /* 51224 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18582 | /* 51226 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 18583 | /* 51226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL), |
| 18584 | /* 51229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 18585 | /* 51231 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 18586 | /* 51233 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18587 | /* 51236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18588 | /* 51239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18589 | /* 51245 */ GIR_RootConstrainSelectedInstOperands, |
| 18590 | /* 51246 */ // GIR_Coverage, 1910, |
| 18591 | /* 51246 */ GIR_EraseRootFromParent_Done, |
| 18592 | /* 51247 */ // Label 1138: @51247 |
| 18593 | /* 51247 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(51308), // Rule ID 1911 // |
| 18594 | /* 51252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 18595 | /* 51255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr), |
| 18596 | /* 51260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18597 | /* 51263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18598 | /* 51266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18599 | /* 51269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18600 | /* 51273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18601 | /* 51277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18602 | /* 51281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18603 | /* 51285 */ // MIs[1] Operand 1 |
| 18604 | /* 51285 */ // No operand predicates |
| 18605 | /* 51285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18606 | /* 51287 */ // (intrinsic_wo_chain:{ *:[i32] } 3830:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 18607 | /* 51287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR), |
| 18608 | /* 51290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 18609 | /* 51292 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 18610 | /* 51294 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18611 | /* 51297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18612 | /* 51300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18613 | /* 51306 */ GIR_RootConstrainSelectedInstOperands, |
| 18614 | /* 51307 */ // GIR_Coverage, 1911, |
| 18615 | /* 51307 */ GIR_EraseRootFromParent_Done, |
| 18616 | /* 51308 */ // Label 1139: @51308 |
| 18617 | /* 51308 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(51369), // Rule ID 1912 // |
| 18618 | /* 51313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 18619 | /* 51316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl), |
| 18620 | /* 51321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18621 | /* 51324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18622 | /* 51327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18623 | /* 51330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18624 | /* 51334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18625 | /* 51338 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18626 | /* 51342 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18627 | /* 51346 */ // MIs[1] Operand 1 |
| 18628 | /* 51346 */ // No operand predicates |
| 18629 | /* 51346 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18630 | /* 51348 */ // (intrinsic_wo_chain:{ *:[i32] } 3835:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 18631 | /* 51348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL), |
| 18632 | /* 51351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 18633 | /* 51353 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 18634 | /* 51355 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18635 | /* 51358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18636 | /* 51361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18637 | /* 51367 */ GIR_RootConstrainSelectedInstOperands, |
| 18638 | /* 51368 */ // GIR_Coverage, 1912, |
| 18639 | /* 51368 */ GIR_EraseRootFromParent_Done, |
| 18640 | /* 51369 */ // Label 1140: @51369 |
| 18641 | /* 51369 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(51430), // Rule ID 1913 // |
| 18642 | /* 51374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 18643 | /* 51377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr), |
| 18644 | /* 51382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18645 | /* 51385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18646 | /* 51388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18647 | /* 51391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18648 | /* 51395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18649 | /* 51399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 18650 | /* 51403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18651 | /* 51407 */ // MIs[1] Operand 1 |
| 18652 | /* 51407 */ // No operand predicates |
| 18653 | /* 51407 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18654 | /* 51409 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 18655 | /* 51409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR), |
| 18656 | /* 51412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 18657 | /* 51414 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 18658 | /* 51416 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18659 | /* 51419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18660 | /* 51422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18661 | /* 51428 */ GIR_RootConstrainSelectedInstOperands, |
| 18662 | /* 51429 */ // GIR_Coverage, 1913, |
| 18663 | /* 51429 */ GIR_EraseRootFromParent_Done, |
| 18664 | /* 51430 */ // Label 1141: @51430 |
| 18665 | /* 51430 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(51484), // Rule ID 104 // |
| 18666 | /* 51435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18667 | /* 51438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 18668 | /* 51443 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18669 | /* 51446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18670 | /* 51449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18671 | /* 51452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18672 | /* 51456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18673 | /* 51460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18674 | /* 51464 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18675 | /* 51464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8), |
| 18676 | /* 51467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18677 | /* 51469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18678 | /* 51471 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18679 | /* 51473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18680 | /* 51476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18681 | /* 51482 */ GIR_RootConstrainSelectedInstOperands, |
| 18682 | /* 51483 */ // GIR_Coverage, 104, |
| 18683 | /* 51483 */ GIR_EraseRootFromParent_Done, |
| 18684 | /* 51484 */ // Label 1142: @51484 |
| 18685 | /* 51484 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(51538), // Rule ID 105 // |
| 18686 | /* 51489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18687 | /* 51492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 18688 | /* 51497 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18689 | /* 51500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18690 | /* 51503 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18691 | /* 51506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18692 | /* 51510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18693 | /* 51514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18694 | /* 51518 */ // (intrinsic_wo_chain:{ *:[i32] } 4115:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18695 | /* 51518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16), |
| 18696 | /* 51521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18697 | /* 51523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18698 | /* 51525 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18699 | /* 51527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18700 | /* 51530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18701 | /* 51536 */ GIR_RootConstrainSelectedInstOperands, |
| 18702 | /* 51537 */ // GIR_Coverage, 105, |
| 18703 | /* 51537 */ GIR_EraseRootFromParent_Done, |
| 18704 | /* 51538 */ // Label 1143: @51538 |
| 18705 | /* 51538 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(51592), // Rule ID 106 // |
| 18706 | /* 51543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18707 | /* 51546 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 18708 | /* 51551 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18709 | /* 51554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18710 | /* 51557 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18711 | /* 51560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18712 | /* 51564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18713 | /* 51568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18714 | /* 51572 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18715 | /* 51572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16), |
| 18716 | /* 51575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18717 | /* 51577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18718 | /* 51579 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18719 | /* 51581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18720 | /* 51584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18721 | /* 51590 */ GIR_RootConstrainSelectedInstOperands, |
| 18722 | /* 51591 */ // GIR_Coverage, 106, |
| 18723 | /* 51591 */ GIR_EraseRootFromParent_Done, |
| 18724 | /* 51592 */ // Label 1144: @51592 |
| 18725 | /* 51592 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(51646), // Rule ID 107 // |
| 18726 | /* 51597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18727 | /* 51600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 18728 | /* 51605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18729 | /* 51608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18730 | /* 51611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18731 | /* 51614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18732 | /* 51618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18733 | /* 51622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18734 | /* 51626 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18735 | /* 51626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8), |
| 18736 | /* 51629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18737 | /* 51631 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18738 | /* 51633 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18739 | /* 51635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18740 | /* 51638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18741 | /* 51644 */ GIR_RootConstrainSelectedInstOperands, |
| 18742 | /* 51645 */ // GIR_Coverage, 107, |
| 18743 | /* 51645 */ GIR_EraseRootFromParent_Done, |
| 18744 | /* 51646 */ // Label 1145: @51646 |
| 18745 | /* 51646 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(51700), // Rule ID 110 // |
| 18746 | /* 51651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18747 | /* 51654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 18748 | /* 51659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18749 | /* 51662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18750 | /* 51665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18751 | /* 51668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18752 | /* 51672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18753 | /* 51676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18754 | /* 51680 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 18755 | /* 51680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 18756 | /* 51683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18757 | /* 51685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 18758 | /* 51687 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 18759 | /* 51689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18760 | /* 51692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18761 | /* 51698 */ GIR_RootConstrainSelectedInstOperands, |
| 18762 | /* 51699 */ // GIR_Coverage, 110, |
| 18763 | /* 51699 */ GIR_EraseRootFromParent_Done, |
| 18764 | /* 51700 */ // Label 1146: @51700 |
| 18765 | /* 51700 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(51754), // Rule ID 111 // |
| 18766 | /* 51705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18767 | /* 51708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 18768 | /* 51713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18769 | /* 51716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18770 | /* 51719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18771 | /* 51722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18772 | /* 51726 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18773 | /* 51730 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18774 | /* 51734 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 18775 | /* 51734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 18776 | /* 51737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18777 | /* 51739 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 18778 | /* 51741 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 18779 | /* 51743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18780 | /* 51746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18781 | /* 51752 */ GIR_RootConstrainSelectedInstOperands, |
| 18782 | /* 51753 */ // GIR_Coverage, 111, |
| 18783 | /* 51753 */ GIR_EraseRootFromParent_Done, |
| 18784 | /* 51754 */ // Label 1147: @51754 |
| 18785 | /* 51754 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(51808), // Rule ID 112 // |
| 18786 | /* 51759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18787 | /* 51762 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 18788 | /* 51767 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18789 | /* 51770 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18790 | /* 51773 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18791 | /* 51776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18792 | /* 51780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18793 | /* 51784 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18794 | /* 51788 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18795 | /* 51788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16), |
| 18796 | /* 51791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18797 | /* 51793 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18798 | /* 51795 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18799 | /* 51797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18800 | /* 51800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18801 | /* 51806 */ GIR_RootConstrainSelectedInstOperands, |
| 18802 | /* 51807 */ // GIR_Coverage, 112, |
| 18803 | /* 51807 */ GIR_EraseRootFromParent_Done, |
| 18804 | /* 51808 */ // Label 1148: @51808 |
| 18805 | /* 51808 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(51862), // Rule ID 113 // |
| 18806 | /* 51813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18807 | /* 51816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 18808 | /* 51821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18809 | /* 51824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18810 | /* 51827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18811 | /* 51830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18812 | /* 51834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18813 | /* 51838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18814 | /* 51842 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18815 | /* 51842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8), |
| 18816 | /* 51845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18817 | /* 51847 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18818 | /* 51849 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18819 | /* 51851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18820 | /* 51854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18821 | /* 51860 */ GIR_RootConstrainSelectedInstOperands, |
| 18822 | /* 51861 */ // GIR_Coverage, 113, |
| 18823 | /* 51861 */ GIR_EraseRootFromParent_Done, |
| 18824 | /* 51862 */ // Label 1149: @51862 |
| 18825 | /* 51862 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(51916), // Rule ID 114 // |
| 18826 | /* 51867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18827 | /* 51870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 18828 | /* 51875 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18829 | /* 51878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18830 | /* 51881 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18831 | /* 51884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18832 | /* 51888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18833 | /* 51892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18834 | /* 51896 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18835 | /* 51896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16), |
| 18836 | /* 51899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18837 | /* 51901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18838 | /* 51903 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18839 | /* 51905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18840 | /* 51908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18841 | /* 51914 */ GIR_RootConstrainSelectedInstOperands, |
| 18842 | /* 51915 */ // GIR_Coverage, 114, |
| 18843 | /* 51915 */ GIR_EraseRootFromParent_Done, |
| 18844 | /* 51916 */ // Label 1150: @51916 |
| 18845 | /* 51916 */ GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(51970), // Rule ID 115 // |
| 18846 | /* 51921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18847 | /* 51924 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 18848 | /* 51929 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18849 | /* 51932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18850 | /* 51935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18851 | /* 51938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18852 | /* 51942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18853 | /* 51946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18854 | /* 51950 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18855 | /* 51950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8), |
| 18856 | /* 51953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18857 | /* 51955 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18858 | /* 51957 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18859 | /* 51959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18860 | /* 51962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18861 | /* 51968 */ GIR_RootConstrainSelectedInstOperands, |
| 18862 | /* 51969 */ // GIR_Coverage, 115, |
| 18863 | /* 51969 */ GIR_EraseRootFromParent_Done, |
| 18864 | /* 51970 */ // Label 1151: @51970 |
| 18865 | /* 51970 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(52024), // Rule ID 116 // |
| 18866 | /* 51975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18867 | /* 51978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 18868 | /* 51983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18869 | /* 51986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18870 | /* 51989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18871 | /* 51992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18872 | /* 51996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18873 | /* 52000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18874 | /* 52004 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18875 | /* 52004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX), |
| 18876 | /* 52007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18877 | /* 52009 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18878 | /* 52011 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18879 | /* 52013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18880 | /* 52016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18881 | /* 52022 */ GIR_RootConstrainSelectedInstOperands, |
| 18882 | /* 52023 */ // GIR_Coverage, 116, |
| 18883 | /* 52023 */ GIR_EraseRootFromParent_Done, |
| 18884 | /* 52024 */ // Label 1152: @52024 |
| 18885 | /* 52024 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(52078), // Rule ID 117 // |
| 18886 | /* 52029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18887 | /* 52032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 18888 | /* 52037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18889 | /* 52040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18890 | /* 52043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18891 | /* 52046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18892 | /* 52050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18893 | /* 52054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18894 | /* 52058 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18895 | /* 52058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX), |
| 18896 | /* 52061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18897 | /* 52063 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18898 | /* 52065 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18899 | /* 52067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18900 | /* 52070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18901 | /* 52076 */ GIR_RootConstrainSelectedInstOperands, |
| 18902 | /* 52077 */ // GIR_Coverage, 117, |
| 18903 | /* 52077 */ GIR_EraseRootFromParent_Done, |
| 18904 | /* 52078 */ // Label 1153: @52078 |
| 18905 | /* 52078 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(52132), // Rule ID 118 // |
| 18906 | /* 52083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18907 | /* 52086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 18908 | /* 52091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18909 | /* 52094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18910 | /* 52097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18911 | /* 52100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18912 | /* 52104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18913 | /* 52108 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18914 | /* 52112 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18915 | /* 52112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX), |
| 18916 | /* 52115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18917 | /* 52117 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18918 | /* 52119 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18919 | /* 52121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18920 | /* 52124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18921 | /* 52130 */ GIR_RootConstrainSelectedInstOperands, |
| 18922 | /* 52131 */ // GIR_Coverage, 118, |
| 18923 | /* 52131 */ GIR_EraseRootFromParent_Done, |
| 18924 | /* 52132 */ // Label 1154: @52132 |
| 18925 | /* 52132 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(52186), // Rule ID 119 // |
| 18926 | /* 52137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18927 | /* 52140 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 18928 | /* 52145 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18929 | /* 52148 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18930 | /* 52151 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18931 | /* 52154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18932 | /* 52158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18933 | /* 52162 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18934 | /* 52166 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18935 | /* 52166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX), |
| 18936 | /* 52169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18937 | /* 52171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18938 | /* 52173 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18939 | /* 52175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18940 | /* 52178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18941 | /* 52184 */ GIR_RootConstrainSelectedInstOperands, |
| 18942 | /* 52185 */ // GIR_Coverage, 119, |
| 18943 | /* 52185 */ GIR_EraseRootFromParent_Done, |
| 18944 | /* 52186 */ // Label 1155: @52186 |
| 18945 | /* 52186 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(52240), // Rule ID 132 // |
| 18946 | /* 52191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18947 | /* 52194 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 18948 | /* 52199 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18949 | /* 52202 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18950 | /* 52205 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18951 | /* 52208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18952 | /* 52212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18953 | /* 52216 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18954 | /* 52220 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18955 | /* 52220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX), |
| 18956 | /* 52223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18957 | /* 52225 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18958 | /* 52227 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18959 | /* 52229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18960 | /* 52232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18961 | /* 52238 */ GIR_RootConstrainSelectedInstOperands, |
| 18962 | /* 52239 */ // GIR_Coverage, 132, |
| 18963 | /* 52239 */ GIR_EraseRootFromParent_Done, |
| 18964 | /* 52240 */ // Label 1156: @52240 |
| 18965 | /* 52240 */ GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(52294), // Rule ID 133 // |
| 18966 | /* 52245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18967 | /* 52248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 18968 | /* 52253 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18969 | /* 52256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18970 | /* 52259 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18971 | /* 52262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18972 | /* 52266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18973 | /* 52270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18974 | /* 52274 */ // (intrinsic_wo_chain:{ *:[i32] } 4127:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18975 | /* 52274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16), |
| 18976 | /* 52277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18977 | /* 52279 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18978 | /* 52281 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18979 | /* 52283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18980 | /* 52286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18981 | /* 52292 */ GIR_RootConstrainSelectedInstOperands, |
| 18982 | /* 52293 */ // GIR_Coverage, 133, |
| 18983 | /* 52293 */ GIR_EraseRootFromParent_Done, |
| 18984 | /* 52294 */ // Label 1157: @52294 |
| 18985 | /* 52294 */ GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(52348), // Rule ID 134 // |
| 18986 | /* 52299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 18987 | /* 52302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 18988 | /* 52307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18989 | /* 52310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18990 | /* 52313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18991 | /* 52316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18992 | /* 52320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18993 | /* 52324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18994 | /* 52328 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18995 | /* 52328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8), |
| 18996 | /* 52331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18997 | /* 52333 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18998 | /* 52335 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18999 | /* 52337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19000 | /* 52340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19001 | /* 52346 */ GIR_RootConstrainSelectedInstOperands, |
| 19002 | /* 52347 */ // GIR_Coverage, 134, |
| 19003 | /* 52347 */ GIR_EraseRootFromParent_Done, |
| 19004 | /* 52348 */ // Label 1158: @52348 |
| 19005 | /* 52348 */ GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(52402), // Rule ID 135 // |
| 19006 | /* 52353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19007 | /* 52356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 19008 | /* 52361 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19009 | /* 52364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19010 | /* 52367 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19011 | /* 52370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19012 | /* 52374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19013 | /* 52378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19014 | /* 52382 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19015 | /* 52382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX), |
| 19016 | /* 52385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19017 | /* 52387 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19018 | /* 52389 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19019 | /* 52391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19020 | /* 52394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19021 | /* 52400 */ GIR_RootConstrainSelectedInstOperands, |
| 19022 | /* 52401 */ // GIR_Coverage, 135, |
| 19023 | /* 52401 */ GIR_EraseRootFromParent_Done, |
| 19024 | /* 52402 */ // Label 1159: @52402 |
| 19025 | /* 52402 */ GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(52456), // Rule ID 136 // |
| 19026 | /* 52407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19027 | /* 52410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 19028 | /* 52415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19029 | /* 52418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19030 | /* 52421 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19031 | /* 52424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19032 | /* 52428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19033 | /* 52432 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19034 | /* 52436 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19035 | /* 52436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16), |
| 19036 | /* 52439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19037 | /* 52441 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19038 | /* 52443 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19039 | /* 52445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19040 | /* 52448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19041 | /* 52454 */ GIR_RootConstrainSelectedInstOperands, |
| 19042 | /* 52455 */ // GIR_Coverage, 136, |
| 19043 | /* 52455 */ GIR_EraseRootFromParent_Done, |
| 19044 | /* 52456 */ // Label 1160: @52456 |
| 19045 | /* 52456 */ GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(52510), // Rule ID 137 // |
| 19046 | /* 52461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19047 | /* 52464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 19048 | /* 52469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19049 | /* 52472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19050 | /* 52475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19051 | /* 52478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19052 | /* 52482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19053 | /* 52486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19054 | /* 52490 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19055 | /* 52490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8), |
| 19056 | /* 52493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19057 | /* 52495 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19058 | /* 52497 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19059 | /* 52499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19060 | /* 52502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19061 | /* 52508 */ GIR_RootConstrainSelectedInstOperands, |
| 19062 | /* 52509 */ // GIR_Coverage, 137, |
| 19063 | /* 52509 */ GIR_EraseRootFromParent_Done, |
| 19064 | /* 52510 */ // Label 1161: @52510 |
| 19065 | /* 52510 */ GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(52564), // Rule ID 138 // |
| 19066 | /* 52515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19067 | /* 52518 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 19068 | /* 52523 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19069 | /* 52526 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19070 | /* 52529 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19071 | /* 52532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19072 | /* 52536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19073 | /* 52540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19074 | /* 52544 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19075 | /* 52544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX), |
| 19076 | /* 52547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19077 | /* 52549 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19078 | /* 52551 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19079 | /* 52553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19080 | /* 52556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19081 | /* 52562 */ GIR_RootConstrainSelectedInstOperands, |
| 19082 | /* 52563 */ // GIR_Coverage, 138, |
| 19083 | /* 52563 */ GIR_EraseRootFromParent_Done, |
| 19084 | /* 52564 */ // Label 1162: @52564 |
| 19085 | /* 52564 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(52618), // Rule ID 139 // |
| 19086 | /* 52569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19087 | /* 52572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 19088 | /* 52577 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19089 | /* 52580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19090 | /* 52583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19091 | /* 52586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19092 | /* 52590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19093 | /* 52594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19094 | /* 52598 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19095 | /* 52598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16), |
| 19096 | /* 52601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19097 | /* 52603 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19098 | /* 52605 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19099 | /* 52607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19100 | /* 52610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19101 | /* 52616 */ GIR_RootConstrainSelectedInstOperands, |
| 19102 | /* 52617 */ // GIR_Coverage, 139, |
| 19103 | /* 52617 */ GIR_EraseRootFromParent_Done, |
| 19104 | /* 52618 */ // Label 1163: @52618 |
| 19105 | /* 52618 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(52672), // Rule ID 140 // |
| 19106 | /* 52623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19107 | /* 52626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 19108 | /* 52631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19109 | /* 52634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19110 | /* 52637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19111 | /* 52640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19112 | /* 52644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19113 | /* 52648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19114 | /* 52652 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19115 | /* 52652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8), |
| 19116 | /* 52655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19117 | /* 52657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19118 | /* 52659 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19119 | /* 52661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19120 | /* 52664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19121 | /* 52670 */ GIR_RootConstrainSelectedInstOperands, |
| 19122 | /* 52671 */ // GIR_Coverage, 140, |
| 19123 | /* 52671 */ GIR_EraseRootFromParent_Done, |
| 19124 | /* 52672 */ // Label 1164: @52672 |
| 19125 | /* 52672 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(52726), // Rule ID 141 // |
| 19126 | /* 52677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19127 | /* 52680 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 19128 | /* 52685 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19129 | /* 52688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19130 | /* 52691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19131 | /* 52694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19132 | /* 52698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19133 | /* 52702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19134 | /* 52706 */ // (intrinsic_wo_chain:{ *:[i32] } 4179:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19135 | /* 52706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX), |
| 19136 | /* 52709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19137 | /* 52711 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19138 | /* 52713 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19139 | /* 52715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19140 | /* 52718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19141 | /* 52724 */ GIR_RootConstrainSelectedInstOperands, |
| 19142 | /* 52725 */ // GIR_Coverage, 141, |
| 19143 | /* 52725 */ GIR_EraseRootFromParent_Done, |
| 19144 | /* 52726 */ // Label 1165: @52726 |
| 19145 | /* 52726 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(52780), // Rule ID 142 // |
| 19146 | /* 52731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19147 | /* 52734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 19148 | /* 52739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19149 | /* 52742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19150 | /* 52745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19151 | /* 52748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19152 | /* 52752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19153 | /* 52756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19154 | /* 52760 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19155 | /* 52760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16), |
| 19156 | /* 52763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19157 | /* 52765 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19158 | /* 52767 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19159 | /* 52769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19160 | /* 52772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19161 | /* 52778 */ GIR_RootConstrainSelectedInstOperands, |
| 19162 | /* 52779 */ // GIR_Coverage, 142, |
| 19163 | /* 52779 */ GIR_EraseRootFromParent_Done, |
| 19164 | /* 52780 */ // Label 1166: @52780 |
| 19165 | /* 52780 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(52834), // Rule ID 143 // |
| 19166 | /* 52785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 19167 | /* 52788 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 19168 | /* 52793 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19169 | /* 52796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19170 | /* 52799 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19171 | /* 52802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19172 | /* 52806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19173 | /* 52810 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19174 | /* 52814 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19175 | /* 52814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8), |
| 19176 | /* 52817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19177 | /* 52819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19178 | /* 52821 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19179 | /* 52823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19180 | /* 52826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19181 | /* 52832 */ GIR_RootConstrainSelectedInstOperands, |
| 19182 | /* 52833 */ // GIR_Coverage, 143, |
| 19183 | /* 52833 */ GIR_EraseRootFromParent_Done, |
| 19184 | /* 52834 */ // Label 1167: @52834 |
| 19185 | /* 52834 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(52888), // Rule ID 144 // |
| 19186 | /* 52839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 19187 | /* 52842 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 19188 | /* 52847 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19189 | /* 52850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19190 | /* 52853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19191 | /* 52856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 19192 | /* 52860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 19193 | /* 52864 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 19194 | /* 52868 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 19195 | /* 52868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8), |
| 19196 | /* 52871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19197 | /* 52873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19198 | /* 52875 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19199 | /* 52877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19200 | /* 52880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19201 | /* 52886 */ GIR_RootConstrainSelectedInstOperands, |
| 19202 | /* 52887 */ // GIR_Coverage, 144, |
| 19203 | /* 52887 */ GIR_EraseRootFromParent_Done, |
| 19204 | /* 52888 */ // Label 1168: @52888 |
| 19205 | /* 52888 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(52933), // Rule ID 203 // |
| 19206 | /* 52893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 19207 | /* 52896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 19208 | /* 52901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19209 | /* 52904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19210 | /* 52907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19211 | /* 52910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19212 | /* 52914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19213 | /* 52918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19214 | /* 52922 */ // (intrinsic_wo_chain:{ *:[i32] } 3735:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19215 | /* 52922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B), |
| 19216 | /* 52925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19217 | /* 52927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19218 | /* 52929 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19219 | /* 52931 */ GIR_RootConstrainSelectedInstOperands, |
| 19220 | /* 52932 */ // GIR_Coverage, 203, |
| 19221 | /* 52932 */ GIR_EraseRootFromParent_Done, |
| 19222 | /* 52933 */ // Label 1169: @52933 |
| 19223 | /* 52933 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(52978), // Rule ID 204 // |
| 19224 | /* 52938 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 19225 | /* 52941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 19226 | /* 52946 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19227 | /* 52949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19228 | /* 52952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19229 | /* 52955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19230 | /* 52959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19231 | /* 52963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19232 | /* 52967 */ // (intrinsic_wo_chain:{ *:[i32] } 3736:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19233 | /* 52967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB), |
| 19234 | /* 52970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19235 | /* 52972 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19236 | /* 52974 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19237 | /* 52976 */ GIR_RootConstrainSelectedInstOperands, |
| 19238 | /* 52977 */ // GIR_Coverage, 204, |
| 19239 | /* 52977 */ GIR_EraseRootFromParent_Done, |
| 19240 | /* 52978 */ // Label 1170: @52978 |
| 19241 | /* 52978 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(53023), // Rule ID 205 // |
| 19242 | /* 52983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 19243 | /* 52986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 19244 | /* 52991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19245 | /* 52994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19246 | /* 52997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19247 | /* 53000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19248 | /* 53004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19249 | /* 53008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19250 | /* 53012 */ // (intrinsic_wo_chain:{ *:[i32] } 3739:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19251 | /* 53012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H), |
| 19252 | /* 53015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19253 | /* 53017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19254 | /* 53019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19255 | /* 53021 */ GIR_RootConstrainSelectedInstOperands, |
| 19256 | /* 53022 */ // GIR_Coverage, 205, |
| 19257 | /* 53022 */ GIR_EraseRootFromParent_Done, |
| 19258 | /* 53023 */ // Label 1171: @53023 |
| 19259 | /* 53023 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(53068), // Rule ID 206 // |
| 19260 | /* 53028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 19261 | /* 53031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 19262 | /* 53036 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19263 | /* 53039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19264 | /* 53042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19265 | /* 53045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19266 | /* 53049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19267 | /* 53053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19268 | /* 53057 */ // (intrinsic_wo_chain:{ *:[i32] } 3737:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19269 | /* 53057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH), |
| 19270 | /* 53060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19271 | /* 53062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19272 | /* 53064 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19273 | /* 53066 */ GIR_RootConstrainSelectedInstOperands, |
| 19274 | /* 53067 */ // GIR_Coverage, 206, |
| 19275 | /* 53067 */ GIR_EraseRootFromParent_Done, |
| 19276 | /* 53068 */ // Label 1172: @53068 |
| 19277 | /* 53068 */ GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(53113), // Rule ID 207 // |
| 19278 | /* 53073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 19279 | /* 53076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 19280 | /* 53081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19281 | /* 53084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19282 | /* 53087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19283 | /* 53090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19284 | /* 53094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19285 | /* 53098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19286 | /* 53102 */ // (intrinsic_wo_chain:{ *:[i32] } 3740:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19287 | /* 53102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W), |
| 19288 | /* 53105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19289 | /* 53107 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19290 | /* 53109 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19291 | /* 53111 */ GIR_RootConstrainSelectedInstOperands, |
| 19292 | /* 53112 */ // GIR_Coverage, 207, |
| 19293 | /* 53112 */ GIR_EraseRootFromParent_Done, |
| 19294 | /* 53113 */ // Label 1173: @53113 |
| 19295 | /* 53113 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(53158), // Rule ID 208 // |
| 19296 | /* 53118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 19297 | /* 53121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 19298 | /* 53126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19299 | /* 53129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19300 | /* 53132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19301 | /* 53135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19302 | /* 53139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19303 | /* 53143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 19304 | /* 53147 */ // (intrinsic_wo_chain:{ *:[i32] } 3738:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 19305 | /* 53147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW), |
| 19306 | /* 53150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19307 | /* 53152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19308 | /* 53154 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19309 | /* 53156 */ GIR_RootConstrainSelectedInstOperands, |
| 19310 | /* 53157 */ // GIR_Coverage, 208, |
| 19311 | /* 53157 */ GIR_EraseRootFromParent_Done, |
| 19312 | /* 53158 */ // Label 1174: @53158 |
| 19313 | /* 53158 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(53212), // Rule ID 431 // |
| 19314 | /* 53163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19315 | /* 53166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 19316 | /* 53171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19317 | /* 53174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19318 | /* 53177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19319 | /* 53180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19320 | /* 53184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19321 | /* 53188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19322 | /* 53192 */ // (intrinsic_wo_chain:{ *:[i32] } 4115:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19323 | /* 53192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16), |
| 19324 | /* 53195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19325 | /* 53197 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19326 | /* 53199 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19327 | /* 53201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19328 | /* 53204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19329 | /* 53210 */ GIR_RootConstrainSelectedInstOperands, |
| 19330 | /* 53211 */ // GIR_Coverage, 431, |
| 19331 | /* 53211 */ GIR_EraseRootFromParent_Done, |
| 19332 | /* 53212 */ // Label 1175: @53212 |
| 19333 | /* 53212 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(53266), // Rule ID 432 // |
| 19334 | /* 53217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19335 | /* 53220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 19336 | /* 53225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19337 | /* 53228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19338 | /* 53231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19339 | /* 53234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19340 | /* 53238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19341 | /* 53242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19342 | /* 53246 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19343 | /* 53246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8), |
| 19344 | /* 53249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19345 | /* 53251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19346 | /* 53253 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19347 | /* 53255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19348 | /* 53258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19349 | /* 53264 */ GIR_RootConstrainSelectedInstOperands, |
| 19350 | /* 53265 */ // GIR_Coverage, 432, |
| 19351 | /* 53265 */ GIR_EraseRootFromParent_Done, |
| 19352 | /* 53266 */ // Label 1176: @53266 |
| 19353 | /* 53266 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(53320), // Rule ID 433 // |
| 19354 | /* 53271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19355 | /* 53274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 19356 | /* 53279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19357 | /* 53282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19358 | /* 53285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19359 | /* 53288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19360 | /* 53292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19361 | /* 53296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19362 | /* 53300 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19363 | /* 53300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX), |
| 19364 | /* 53303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19365 | /* 53305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19366 | /* 53307 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19367 | /* 53309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19368 | /* 53312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19369 | /* 53318 */ GIR_RootConstrainSelectedInstOperands, |
| 19370 | /* 53319 */ // GIR_Coverage, 433, |
| 19371 | /* 53319 */ GIR_EraseRootFromParent_Done, |
| 19372 | /* 53320 */ // Label 1177: @53320 |
| 19373 | /* 53320 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(53374), // Rule ID 434 // |
| 19374 | /* 53325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19375 | /* 53328 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 19376 | /* 53333 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19377 | /* 53336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19378 | /* 53339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19379 | /* 53342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19380 | /* 53346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19381 | /* 53350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19382 | /* 53354 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19383 | /* 53354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8), |
| 19384 | /* 53357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19385 | /* 53359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19386 | /* 53361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19387 | /* 53363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19388 | /* 53366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19389 | /* 53372 */ GIR_RootConstrainSelectedInstOperands, |
| 19390 | /* 53373 */ // GIR_Coverage, 434, |
| 19391 | /* 53373 */ GIR_EraseRootFromParent_Done, |
| 19392 | /* 53374 */ // Label 1178: @53374 |
| 19393 | /* 53374 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(53428), // Rule ID 435 // |
| 19394 | /* 53379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19395 | /* 53382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 19396 | /* 53387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19397 | /* 53390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19398 | /* 53393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19399 | /* 53396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19400 | /* 53400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19401 | /* 53404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19402 | /* 53408 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19403 | /* 53408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX), |
| 19404 | /* 53411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19405 | /* 53413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19406 | /* 53415 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19407 | /* 53417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19408 | /* 53420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19409 | /* 53426 */ GIR_RootConstrainSelectedInstOperands, |
| 19410 | /* 53427 */ // GIR_Coverage, 435, |
| 19411 | /* 53427 */ GIR_EraseRootFromParent_Done, |
| 19412 | /* 53428 */ // Label 1179: @53428 |
| 19413 | /* 53428 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(53482), // Rule ID 436 // |
| 19414 | /* 53433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19415 | /* 53436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 19416 | /* 53441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19417 | /* 53444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19418 | /* 53447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19419 | /* 53450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19420 | /* 53454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19421 | /* 53458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19422 | /* 53462 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19423 | /* 53462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16), |
| 19424 | /* 53465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19425 | /* 53467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19426 | /* 53469 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19427 | /* 53471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19428 | /* 53474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19429 | /* 53480 */ GIR_RootConstrainSelectedInstOperands, |
| 19430 | /* 53481 */ // GIR_Coverage, 436, |
| 19431 | /* 53481 */ GIR_EraseRootFromParent_Done, |
| 19432 | /* 53482 */ // Label 1180: @53482 |
| 19433 | /* 53482 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(53536), // Rule ID 437 // |
| 19434 | /* 53487 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19435 | /* 53490 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 19436 | /* 53495 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19437 | /* 53498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19438 | /* 53501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19439 | /* 53504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19440 | /* 53508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19441 | /* 53512 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19442 | /* 53516 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19443 | /* 53516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8), |
| 19444 | /* 53519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19445 | /* 53521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19446 | /* 53523 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19447 | /* 53525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19448 | /* 53528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19449 | /* 53534 */ GIR_RootConstrainSelectedInstOperands, |
| 19450 | /* 53535 */ // GIR_Coverage, 437, |
| 19451 | /* 53535 */ GIR_EraseRootFromParent_Done, |
| 19452 | /* 53536 */ // Label 1181: @53536 |
| 19453 | /* 53536 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(53590), // Rule ID 438 // |
| 19454 | /* 53541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19455 | /* 53544 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 19456 | /* 53549 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19457 | /* 53552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19458 | /* 53555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19459 | /* 53558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19460 | /* 53562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19461 | /* 53566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19462 | /* 53570 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19463 | /* 53570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16), |
| 19464 | /* 53573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19465 | /* 53575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19466 | /* 53577 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19467 | /* 53579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19468 | /* 53582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19469 | /* 53588 */ GIR_RootConstrainSelectedInstOperands, |
| 19470 | /* 53589 */ // GIR_Coverage, 438, |
| 19471 | /* 53589 */ GIR_EraseRootFromParent_Done, |
| 19472 | /* 53590 */ // Label 1182: @53590 |
| 19473 | /* 53590 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(53644), // Rule ID 439 // |
| 19474 | /* 53595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19475 | /* 53598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 19476 | /* 53603 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19477 | /* 53606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19478 | /* 53609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19479 | /* 53612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19480 | /* 53616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19481 | /* 53620 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19482 | /* 53624 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19483 | /* 53624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8), |
| 19484 | /* 53627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19485 | /* 53629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19486 | /* 53631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19487 | /* 53633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19488 | /* 53636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19489 | /* 53642 */ GIR_RootConstrainSelectedInstOperands, |
| 19490 | /* 53643 */ // GIR_Coverage, 439, |
| 19491 | /* 53643 */ GIR_EraseRootFromParent_Done, |
| 19492 | /* 53644 */ // Label 1183: @53644 |
| 19493 | /* 53644 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(53698), // Rule ID 440 // |
| 19494 | /* 53649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19495 | /* 53652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 19496 | /* 53657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19497 | /* 53660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19498 | /* 53663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19499 | /* 53666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19500 | /* 53670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19501 | /* 53674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19502 | /* 53678 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19503 | /* 53678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX), |
| 19504 | /* 53681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19505 | /* 53683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19506 | /* 53685 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19507 | /* 53687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19508 | /* 53690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19509 | /* 53696 */ GIR_RootConstrainSelectedInstOperands, |
| 19510 | /* 53697 */ // GIR_Coverage, 440, |
| 19511 | /* 53697 */ GIR_EraseRootFromParent_Done, |
| 19512 | /* 53698 */ // Label 1184: @53698 |
| 19513 | /* 53698 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(53752), // Rule ID 441 // |
| 19514 | /* 53703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19515 | /* 53706 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 19516 | /* 53711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19517 | /* 53714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19518 | /* 53717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19519 | /* 53720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19520 | /* 53724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19521 | /* 53728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19522 | /* 53732 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19523 | /* 53732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX), |
| 19524 | /* 53735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19525 | /* 53737 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19526 | /* 53739 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19527 | /* 53741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19528 | /* 53744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19529 | /* 53750 */ GIR_RootConstrainSelectedInstOperands, |
| 19530 | /* 53751 */ // GIR_Coverage, 441, |
| 19531 | /* 53751 */ GIR_EraseRootFromParent_Done, |
| 19532 | /* 53752 */ // Label 1185: @53752 |
| 19533 | /* 53752 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(53806), // Rule ID 442 // |
| 19534 | /* 53757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19535 | /* 53760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 19536 | /* 53765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19537 | /* 53768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19538 | /* 53771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19539 | /* 53774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19540 | /* 53778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19541 | /* 53782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19542 | /* 53786 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19543 | /* 53786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16), |
| 19544 | /* 53789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19545 | /* 53791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19546 | /* 53793 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19547 | /* 53795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19548 | /* 53798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19549 | /* 53804 */ GIR_RootConstrainSelectedInstOperands, |
| 19550 | /* 53805 */ // GIR_Coverage, 442, |
| 19551 | /* 53805 */ GIR_EraseRootFromParent_Done, |
| 19552 | /* 53806 */ // Label 1186: @53806 |
| 19553 | /* 53806 */ GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(53860), // Rule ID 455 // |
| 19554 | /* 53811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19555 | /* 53814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 19556 | /* 53819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19557 | /* 53822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19558 | /* 53825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19559 | /* 53828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19560 | /* 53832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19561 | /* 53836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19562 | /* 53840 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19563 | /* 53840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX), |
| 19564 | /* 53843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19565 | /* 53845 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19566 | /* 53847 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19567 | /* 53849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19568 | /* 53852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19569 | /* 53858 */ GIR_RootConstrainSelectedInstOperands, |
| 19570 | /* 53859 */ // GIR_Coverage, 455, |
| 19571 | /* 53859 */ GIR_EraseRootFromParent_Done, |
| 19572 | /* 53860 */ // Label 1187: @53860 |
| 19573 | /* 53860 */ GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(53914), // Rule ID 456 // |
| 19574 | /* 53865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19575 | /* 53868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 19576 | /* 53873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19577 | /* 53876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19578 | /* 53879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19579 | /* 53882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19580 | /* 53886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19581 | /* 53890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19582 | /* 53894 */ // (intrinsic_wo_chain:{ *:[i32] } 4127:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19583 | /* 53894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16), |
| 19584 | /* 53897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19585 | /* 53899 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19586 | /* 53901 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19587 | /* 53903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19588 | /* 53906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19589 | /* 53912 */ GIR_RootConstrainSelectedInstOperands, |
| 19590 | /* 53913 */ // GIR_Coverage, 456, |
| 19591 | /* 53913 */ GIR_EraseRootFromParent_Done, |
| 19592 | /* 53914 */ // Label 1188: @53914 |
| 19593 | /* 53914 */ GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(53968), // Rule ID 457 // |
| 19594 | /* 53919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19595 | /* 53922 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 19596 | /* 53927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19597 | /* 53930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19598 | /* 53933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19599 | /* 53936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19600 | /* 53940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19601 | /* 53944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19602 | /* 53948 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19603 | /* 53948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8), |
| 19604 | /* 53951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19605 | /* 53953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19606 | /* 53955 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19607 | /* 53957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19608 | /* 53960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19609 | /* 53966 */ GIR_RootConstrainSelectedInstOperands, |
| 19610 | /* 53967 */ // GIR_Coverage, 457, |
| 19611 | /* 53967 */ GIR_EraseRootFromParent_Done, |
| 19612 | /* 53968 */ // Label 1189: @53968 |
| 19613 | /* 53968 */ GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(54022), // Rule ID 458 // |
| 19614 | /* 53973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19615 | /* 53976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 19616 | /* 53981 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19617 | /* 53984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19618 | /* 53987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19619 | /* 53990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19620 | /* 53994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19621 | /* 53998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19622 | /* 54002 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19623 | /* 54002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX), |
| 19624 | /* 54005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19625 | /* 54007 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19626 | /* 54009 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19627 | /* 54011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19628 | /* 54014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19629 | /* 54020 */ GIR_RootConstrainSelectedInstOperands, |
| 19630 | /* 54021 */ // GIR_Coverage, 458, |
| 19631 | /* 54021 */ GIR_EraseRootFromParent_Done, |
| 19632 | /* 54022 */ // Label 1190: @54022 |
| 19633 | /* 54022 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(54076), // Rule ID 459 // |
| 19634 | /* 54027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19635 | /* 54030 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 19636 | /* 54035 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19637 | /* 54038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19638 | /* 54041 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19639 | /* 54044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19640 | /* 54048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19641 | /* 54052 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19642 | /* 54056 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19643 | /* 54056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16), |
| 19644 | /* 54059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19645 | /* 54061 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19646 | /* 54063 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19647 | /* 54065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19648 | /* 54068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19649 | /* 54074 */ GIR_RootConstrainSelectedInstOperands, |
| 19650 | /* 54075 */ // GIR_Coverage, 459, |
| 19651 | /* 54075 */ GIR_EraseRootFromParent_Done, |
| 19652 | /* 54076 */ // Label 1191: @54076 |
| 19653 | /* 54076 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(54130), // Rule ID 460 // |
| 19654 | /* 54081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19655 | /* 54084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 19656 | /* 54089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19657 | /* 54092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19658 | /* 54095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19659 | /* 54098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19660 | /* 54102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19661 | /* 54106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19662 | /* 54110 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19663 | /* 54110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8), |
| 19664 | /* 54113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19665 | /* 54115 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19666 | /* 54117 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19667 | /* 54119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19668 | /* 54122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19669 | /* 54128 */ GIR_RootConstrainSelectedInstOperands, |
| 19670 | /* 54129 */ // GIR_Coverage, 460, |
| 19671 | /* 54129 */ GIR_EraseRootFromParent_Done, |
| 19672 | /* 54130 */ // Label 1192: @54130 |
| 19673 | /* 54130 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(54184), // Rule ID 461 // |
| 19674 | /* 54135 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19675 | /* 54138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 19676 | /* 54143 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19677 | /* 54146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19678 | /* 54149 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19679 | /* 54152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19680 | /* 54156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19681 | /* 54160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19682 | /* 54164 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19683 | /* 54164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX), |
| 19684 | /* 54167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19685 | /* 54169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19686 | /* 54171 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19687 | /* 54173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19688 | /* 54176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19689 | /* 54182 */ GIR_RootConstrainSelectedInstOperands, |
| 19690 | /* 54183 */ // GIR_Coverage, 461, |
| 19691 | /* 54183 */ GIR_EraseRootFromParent_Done, |
| 19692 | /* 54184 */ // Label 1193: @54184 |
| 19693 | /* 54184 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(54238), // Rule ID 462 // |
| 19694 | /* 54189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19695 | /* 54192 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 19696 | /* 54197 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19697 | /* 54200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19698 | /* 54203 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19699 | /* 54206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19700 | /* 54210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19701 | /* 54214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19702 | /* 54218 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19703 | /* 54218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16), |
| 19704 | /* 54221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19705 | /* 54223 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19706 | /* 54225 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19707 | /* 54227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19708 | /* 54230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19709 | /* 54236 */ GIR_RootConstrainSelectedInstOperands, |
| 19710 | /* 54237 */ // GIR_Coverage, 462, |
| 19711 | /* 54237 */ GIR_EraseRootFromParent_Done, |
| 19712 | /* 54238 */ // Label 1194: @54238 |
| 19713 | /* 54238 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(54292), // Rule ID 463 // |
| 19714 | /* 54243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19715 | /* 54246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 19716 | /* 54251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19717 | /* 54254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19718 | /* 54257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19719 | /* 54260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19720 | /* 54264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19721 | /* 54268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19722 | /* 54272 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19723 | /* 54272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8), |
| 19724 | /* 54275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19725 | /* 54277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19726 | /* 54279 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19727 | /* 54281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19728 | /* 54284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19729 | /* 54290 */ GIR_RootConstrainSelectedInstOperands, |
| 19730 | /* 54291 */ // GIR_Coverage, 463, |
| 19731 | /* 54291 */ GIR_EraseRootFromParent_Done, |
| 19732 | /* 54292 */ // Label 1195: @54292 |
| 19733 | /* 54292 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(54346), // Rule ID 464 // |
| 19734 | /* 54297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19735 | /* 54300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 19736 | /* 54305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19737 | /* 54308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19738 | /* 54311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19739 | /* 54314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19740 | /* 54318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19741 | /* 54322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19742 | /* 54326 */ // (intrinsic_wo_chain:{ *:[i32] } 4179:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19743 | /* 54326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX), |
| 19744 | /* 54329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19745 | /* 54331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19746 | /* 54333 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19747 | /* 54335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19748 | /* 54338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19749 | /* 54344 */ GIR_RootConstrainSelectedInstOperands, |
| 19750 | /* 54345 */ // GIR_Coverage, 464, |
| 19751 | /* 54345 */ GIR_EraseRootFromParent_Done, |
| 19752 | /* 54346 */ // Label 1196: @54346 |
| 19753 | /* 54346 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(54400), // Rule ID 465 // |
| 19754 | /* 54351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19755 | /* 54354 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 19756 | /* 54359 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19757 | /* 54362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19758 | /* 54365 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19759 | /* 54368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19760 | /* 54372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19761 | /* 54376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19762 | /* 54380 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19763 | /* 54380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16), |
| 19764 | /* 54383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19765 | /* 54385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19766 | /* 54387 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19767 | /* 54389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19768 | /* 54392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19769 | /* 54398 */ GIR_RootConstrainSelectedInstOperands, |
| 19770 | /* 54399 */ // GIR_Coverage, 465, |
| 19771 | /* 54399 */ GIR_EraseRootFromParent_Done, |
| 19772 | /* 54400 */ // Label 1197: @54400 |
| 19773 | /* 54400 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(54454), // Rule ID 466 // |
| 19774 | /* 54405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19775 | /* 54408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 19776 | /* 54413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19777 | /* 54416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19778 | /* 54419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19779 | /* 54422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19780 | /* 54426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19781 | /* 54430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19782 | /* 54434 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19783 | /* 54434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8), |
| 19784 | /* 54437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19785 | /* 54439 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19786 | /* 54441 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19787 | /* 54443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19788 | /* 54446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19789 | /* 54452 */ GIR_RootConstrainSelectedInstOperands, |
| 19790 | /* 54453 */ // GIR_Coverage, 466, |
| 19791 | /* 54453 */ GIR_EraseRootFromParent_Done, |
| 19792 | /* 54454 */ // Label 1198: @54454 |
| 19793 | /* 54454 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(54508), // Rule ID 467 // |
| 19794 | /* 54459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19795 | /* 54462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 19796 | /* 54467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19797 | /* 54470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19798 | /* 54473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19799 | /* 54476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19800 | /* 54480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19801 | /* 54484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19802 | /* 54488 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19803 | /* 54488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8), |
| 19804 | /* 54491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19805 | /* 54493 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19806 | /* 54495 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19807 | /* 54497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19808 | /* 54500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19809 | /* 54506 */ GIR_RootConstrainSelectedInstOperands, |
| 19810 | /* 54507 */ // GIR_Coverage, 467, |
| 19811 | /* 54507 */ GIR_EraseRootFromParent_Done, |
| 19812 | /* 54508 */ // Label 1199: @54508 |
| 19813 | /* 54508 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(54562), // Rule ID 523 // |
| 19814 | /* 54513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19815 | /* 54516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 19816 | /* 54521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19817 | /* 54524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19818 | /* 54527 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19819 | /* 54530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19820 | /* 54534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19821 | /* 54538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19822 | /* 54542 */ // (intrinsic_wo_chain:{ *:[i32] } 4147:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19823 | /* 54542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD), |
| 19824 | /* 54545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19825 | /* 54547 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19826 | /* 54549 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19827 | /* 54551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19828 | /* 54554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19829 | /* 54560 */ GIR_RootConstrainSelectedInstOperands, |
| 19830 | /* 54561 */ // GIR_Coverage, 523, |
| 19831 | /* 54561 */ GIR_EraseRootFromParent_Done, |
| 19832 | /* 54562 */ // Label 1200: @54562 |
| 19833 | /* 54562 */ GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(54616), // Rule ID 524 // |
| 19834 | /* 54567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19835 | /* 54570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 19836 | /* 54575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19837 | /* 54578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19838 | /* 54581 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19839 | /* 54584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19840 | /* 54588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19841 | /* 54592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19842 | /* 54596 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19843 | /* 54596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX), |
| 19844 | /* 54599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19845 | /* 54601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19846 | /* 54603 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19847 | /* 54605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19848 | /* 54608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19849 | /* 54614 */ GIR_RootConstrainSelectedInstOperands, |
| 19850 | /* 54615 */ // GIR_Coverage, 524, |
| 19851 | /* 54615 */ GIR_EraseRootFromParent_Done, |
| 19852 | /* 54616 */ // Label 1201: @54616 |
| 19853 | /* 54616 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(54670), // Rule ID 525 // |
| 19854 | /* 54621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19855 | /* 54624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 19856 | /* 54629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19857 | /* 54632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19858 | /* 54635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19859 | /* 54638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19860 | /* 54642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19861 | /* 54646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19862 | /* 54650 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19863 | /* 54650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD), |
| 19864 | /* 54653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19865 | /* 54655 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19866 | /* 54657 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19867 | /* 54659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19868 | /* 54662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19869 | /* 54668 */ GIR_RootConstrainSelectedInstOperands, |
| 19870 | /* 54669 */ // GIR_Coverage, 525, |
| 19871 | /* 54669 */ GIR_EraseRootFromParent_Done, |
| 19872 | /* 54670 */ // Label 1202: @54670 |
| 19873 | /* 54670 */ GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(54724), // Rule ID 526 // |
| 19874 | /* 54675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 19875 | /* 54678 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 19876 | /* 54683 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19877 | /* 54686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19878 | /* 54689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19879 | /* 54692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19880 | /* 54696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19881 | /* 54700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19882 | /* 54704 */ // (intrinsic_wo_chain:{ *:[i32] } 4156:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19883 | /* 54704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX), |
| 19884 | /* 54707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19885 | /* 54709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19886 | /* 54711 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19887 | /* 54713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19888 | /* 54716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19889 | /* 54722 */ GIR_RootConstrainSelectedInstOperands, |
| 19890 | /* 54723 */ // GIR_Coverage, 526, |
| 19891 | /* 54723 */ GIR_EraseRootFromParent_Done, |
| 19892 | /* 54724 */ // Label 1203: @54724 |
| 19893 | /* 54724 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(54769), // Rule ID 540 // |
| 19894 | /* 54729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 19895 | /* 54732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 19896 | /* 54737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19897 | /* 54740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19898 | /* 54743 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19899 | /* 54746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19900 | /* 54750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19901 | /* 54754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19902 | /* 54758 */ // (intrinsic_wo_chain:{ *:[i32] } 3735:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19903 | /* 54758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B), |
| 19904 | /* 54761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19905 | /* 54763 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19906 | /* 54765 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19907 | /* 54767 */ GIR_RootConstrainSelectedInstOperands, |
| 19908 | /* 54768 */ // GIR_Coverage, 540, |
| 19909 | /* 54768 */ GIR_EraseRootFromParent_Done, |
| 19910 | /* 54769 */ // Label 1204: @54769 |
| 19911 | /* 54769 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(54814), // Rule ID 541 // |
| 19912 | /* 54774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 19913 | /* 54777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 19914 | /* 54782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19915 | /* 54785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19916 | /* 54788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19917 | /* 54791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19918 | /* 54795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19919 | /* 54799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19920 | /* 54803 */ // (intrinsic_wo_chain:{ *:[i32] } 3736:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19921 | /* 54803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB), |
| 19922 | /* 54806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19923 | /* 54808 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19924 | /* 54810 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19925 | /* 54812 */ GIR_RootConstrainSelectedInstOperands, |
| 19926 | /* 54813 */ // GIR_Coverage, 541, |
| 19927 | /* 54813 */ GIR_EraseRootFromParent_Done, |
| 19928 | /* 54814 */ // Label 1205: @54814 |
| 19929 | /* 54814 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(54859), // Rule ID 542 // |
| 19930 | /* 54819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 19931 | /* 54822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 19932 | /* 54827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19933 | /* 54830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19934 | /* 54833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19935 | /* 54836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19936 | /* 54840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19937 | /* 54844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19938 | /* 54848 */ // (intrinsic_wo_chain:{ *:[i32] } 3739:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19939 | /* 54848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H), |
| 19940 | /* 54851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19941 | /* 54853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19942 | /* 54855 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19943 | /* 54857 */ GIR_RootConstrainSelectedInstOperands, |
| 19944 | /* 54858 */ // GIR_Coverage, 542, |
| 19945 | /* 54858 */ GIR_EraseRootFromParent_Done, |
| 19946 | /* 54859 */ // Label 1206: @54859 |
| 19947 | /* 54859 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(54904), // Rule ID 543 // |
| 19948 | /* 54864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 19949 | /* 54867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 19950 | /* 54872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19951 | /* 54875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19952 | /* 54878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19953 | /* 54881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19954 | /* 54885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19955 | /* 54889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19956 | /* 54893 */ // (intrinsic_wo_chain:{ *:[i32] } 3737:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19957 | /* 54893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH), |
| 19958 | /* 54896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19959 | /* 54898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19960 | /* 54900 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19961 | /* 54902 */ GIR_RootConstrainSelectedInstOperands, |
| 19962 | /* 54903 */ // GIR_Coverage, 543, |
| 19963 | /* 54903 */ GIR_EraseRootFromParent_Done, |
| 19964 | /* 54904 */ // Label 1207: @54904 |
| 19965 | /* 54904 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(54949), // Rule ID 544 // |
| 19966 | /* 54909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 19967 | /* 54912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 19968 | /* 54917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19969 | /* 54920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19970 | /* 54923 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19971 | /* 54926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19972 | /* 54930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19973 | /* 54934 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19974 | /* 54938 */ // (intrinsic_wo_chain:{ *:[i32] } 3740:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19975 | /* 54938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W), |
| 19976 | /* 54941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19977 | /* 54943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19978 | /* 54945 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19979 | /* 54947 */ GIR_RootConstrainSelectedInstOperands, |
| 19980 | /* 54948 */ // GIR_Coverage, 544, |
| 19981 | /* 54948 */ GIR_EraseRootFromParent_Done, |
| 19982 | /* 54949 */ // Label 1208: @54949 |
| 19983 | /* 54949 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(54994), // Rule ID 545 // |
| 19984 | /* 54954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 19985 | /* 54957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 19986 | /* 54962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19987 | /* 54965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19988 | /* 54968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19989 | /* 54971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19990 | /* 54975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19991 | /* 54979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19992 | /* 54983 */ // (intrinsic_wo_chain:{ *:[i32] } 3738:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19993 | /* 54983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW), |
| 19994 | /* 54986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19995 | /* 54988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19996 | /* 54990 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19997 | /* 54992 */ GIR_RootConstrainSelectedInstOperands, |
| 19998 | /* 54993 */ // GIR_Coverage, 545, |
| 19999 | /* 54993 */ GIR_EraseRootFromParent_Done, |
| 20000 | /* 54994 */ // Label 1209: @54994 |
| 20001 | /* 54994 */ GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(55048), // Rule ID 911 // |
| 20002 | /* 54999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20003 | /* 55002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 20004 | /* 55007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20005 | /* 55010 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20006 | /* 55013 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20007 | /* 55016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20008 | /* 55020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20009 | /* 55024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20010 | /* 55028 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4025:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20011 | /* 55028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16), |
| 20012 | /* 55031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20013 | /* 55033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20014 | /* 55035 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20015 | /* 55037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20016 | /* 55040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20017 | /* 55046 */ GIR_RootConstrainSelectedInstOperands, |
| 20018 | /* 55047 */ // GIR_Coverage, 911, |
| 20019 | /* 55047 */ GIR_EraseRootFromParent_Done, |
| 20020 | /* 55048 */ // Label 1210: @55048 |
| 20021 | /* 55048 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(55102), // Rule ID 912 // |
| 20022 | /* 55053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20023 | /* 55056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 20024 | /* 55061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20025 | /* 55064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20026 | /* 55067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20027 | /* 55070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20028 | /* 55074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20029 | /* 55078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20030 | /* 55082 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4025:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20031 | /* 55082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32), |
| 20032 | /* 55085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20033 | /* 55087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20034 | /* 55089 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20035 | /* 55091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20036 | /* 55094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20037 | /* 55100 */ GIR_RootConstrainSelectedInstOperands, |
| 20038 | /* 55101 */ // GIR_Coverage, 912, |
| 20039 | /* 55101 */ GIR_EraseRootFromParent_Done, |
| 20040 | /* 55102 */ // Label 1211: @55102 |
| 20041 | /* 55102 */ GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(55156), // Rule ID 913 // |
| 20042 | /* 55107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20043 | /* 55110 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 20044 | /* 55115 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20045 | /* 55118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20046 | /* 55121 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20047 | /* 55124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20048 | /* 55128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20049 | /* 55132 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20050 | /* 55136 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4025:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20051 | /* 55136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16), |
| 20052 | /* 55139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20053 | /* 55141 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20054 | /* 55143 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20055 | /* 55145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20056 | /* 55148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20057 | /* 55154 */ GIR_RootConstrainSelectedInstOperands, |
| 20058 | /* 55155 */ // GIR_Coverage, 913, |
| 20059 | /* 55155 */ GIR_EraseRootFromParent_Done, |
| 20060 | /* 55156 */ // Label 1212: @55156 |
| 20061 | /* 55156 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(55210), // Rule ID 914 // |
| 20062 | /* 55161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20063 | /* 55164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 20064 | /* 55169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20065 | /* 55172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20066 | /* 55175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20067 | /* 55178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20068 | /* 55182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20069 | /* 55186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20070 | /* 55190 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4025:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20071 | /* 55190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32), |
| 20072 | /* 55193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20073 | /* 55195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20074 | /* 55197 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20075 | /* 55199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20076 | /* 55202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20077 | /* 55208 */ GIR_RootConstrainSelectedInstOperands, |
| 20078 | /* 55209 */ // GIR_Coverage, 914, |
| 20079 | /* 55209 */ GIR_EraseRootFromParent_Done, |
| 20080 | /* 55210 */ // Label 1213: @55210 |
| 20081 | /* 55210 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(55264), // Rule ID 915 // |
| 20082 | /* 55215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20083 | /* 55218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 20084 | /* 55223 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20085 | /* 55226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20086 | /* 55229 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20087 | /* 55232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20088 | /* 55236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20089 | /* 55240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20090 | /* 55244 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4025:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20091 | /* 55244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8), |
| 20092 | /* 55247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20093 | /* 55249 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20094 | /* 55251 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20095 | /* 55253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20096 | /* 55256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20097 | /* 55262 */ GIR_RootConstrainSelectedInstOperands, |
| 20098 | /* 55263 */ // GIR_Coverage, 915, |
| 20099 | /* 55263 */ GIR_EraseRootFromParent_Done, |
| 20100 | /* 55264 */ // Label 1214: @55264 |
| 20101 | /* 55264 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(55318), // Rule ID 916 // |
| 20102 | /* 55269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20103 | /* 55272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 20104 | /* 55277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20105 | /* 55280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20106 | /* 55283 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20107 | /* 55286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20108 | /* 55290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20109 | /* 55294 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20110 | /* 55298 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4025:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20111 | /* 55298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8), |
| 20112 | /* 55301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20113 | /* 55303 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20114 | /* 55305 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20115 | /* 55307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20116 | /* 55310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20117 | /* 55316 */ GIR_RootConstrainSelectedInstOperands, |
| 20118 | /* 55317 */ // GIR_Coverage, 916, |
| 20119 | /* 55317 */ GIR_EraseRootFromParent_Done, |
| 20120 | /* 55318 */ // Label 1215: @55318 |
| 20121 | /* 55318 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(55372), // Rule ID 917 // |
| 20122 | /* 55323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20123 | /* 55326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 20124 | /* 55331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20125 | /* 55334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20126 | /* 55337 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20127 | /* 55340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20128 | /* 55344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20129 | /* 55348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20130 | /* 55352 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4026:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20131 | /* 55352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16), |
| 20132 | /* 55355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20133 | /* 55357 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20134 | /* 55359 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20135 | /* 55361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20136 | /* 55364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20137 | /* 55370 */ GIR_RootConstrainSelectedInstOperands, |
| 20138 | /* 55371 */ // GIR_Coverage, 917, |
| 20139 | /* 55371 */ GIR_EraseRootFromParent_Done, |
| 20140 | /* 55372 */ // Label 1216: @55372 |
| 20141 | /* 55372 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(55426), // Rule ID 918 // |
| 20142 | /* 55377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20143 | /* 55380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 20144 | /* 55385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20145 | /* 55388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20146 | /* 55391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20147 | /* 55394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20148 | /* 55398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20149 | /* 55402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20150 | /* 55406 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4026:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20151 | /* 55406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32), |
| 20152 | /* 55409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20153 | /* 55411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20154 | /* 55413 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20155 | /* 55415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20156 | /* 55418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20157 | /* 55424 */ GIR_RootConstrainSelectedInstOperands, |
| 20158 | /* 55425 */ // GIR_Coverage, 918, |
| 20159 | /* 55425 */ GIR_EraseRootFromParent_Done, |
| 20160 | /* 55426 */ // Label 1217: @55426 |
| 20161 | /* 55426 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(55480), // Rule ID 919 // |
| 20162 | /* 55431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20163 | /* 55434 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 20164 | /* 55439 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20165 | /* 55442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20166 | /* 55445 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20167 | /* 55448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20168 | /* 55452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20169 | /* 55456 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20170 | /* 55460 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4026:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20171 | /* 55460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16), |
| 20172 | /* 55463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20173 | /* 55465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20174 | /* 55467 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20175 | /* 55469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20176 | /* 55472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20177 | /* 55478 */ GIR_RootConstrainSelectedInstOperands, |
| 20178 | /* 55479 */ // GIR_Coverage, 919, |
| 20179 | /* 55479 */ GIR_EraseRootFromParent_Done, |
| 20180 | /* 55480 */ // Label 1218: @55480 |
| 20181 | /* 55480 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(55534), // Rule ID 920 // |
| 20182 | /* 55485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20183 | /* 55488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 20184 | /* 55493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20185 | /* 55496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20186 | /* 55499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20187 | /* 55502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20188 | /* 55506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20189 | /* 55510 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20190 | /* 55514 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4026:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20191 | /* 55514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32), |
| 20192 | /* 55517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20193 | /* 55519 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20194 | /* 55521 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20195 | /* 55523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20196 | /* 55526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20197 | /* 55532 */ GIR_RootConstrainSelectedInstOperands, |
| 20198 | /* 55533 */ // GIR_Coverage, 920, |
| 20199 | /* 55533 */ GIR_EraseRootFromParent_Done, |
| 20200 | /* 55534 */ // Label 1219: @55534 |
| 20201 | /* 55534 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(55588), // Rule ID 921 // |
| 20202 | /* 55539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20203 | /* 55542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 20204 | /* 55547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20205 | /* 55550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20206 | /* 55553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20207 | /* 55556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20208 | /* 55560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20209 | /* 55564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20210 | /* 55568 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4026:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20211 | /* 55568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8), |
| 20212 | /* 55571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20213 | /* 55573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20214 | /* 55575 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20215 | /* 55577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20216 | /* 55580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20217 | /* 55586 */ GIR_RootConstrainSelectedInstOperands, |
| 20218 | /* 55587 */ // GIR_Coverage, 921, |
| 20219 | /* 55587 */ GIR_EraseRootFromParent_Done, |
| 20220 | /* 55588 */ // Label 1220: @55588 |
| 20221 | /* 55588 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(55642), // Rule ID 922 // |
| 20222 | /* 55593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20223 | /* 55596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 20224 | /* 55601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20225 | /* 55604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20226 | /* 55607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20227 | /* 55610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20228 | /* 55614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20229 | /* 55618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20230 | /* 55622 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4026:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20231 | /* 55622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8), |
| 20232 | /* 55625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20233 | /* 55627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20234 | /* 55629 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20235 | /* 55631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20236 | /* 55634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20237 | /* 55640 */ GIR_RootConstrainSelectedInstOperands, |
| 20238 | /* 55641 */ // GIR_Coverage, 922, |
| 20239 | /* 55641 */ GIR_EraseRootFromParent_Done, |
| 20240 | /* 55642 */ // Label 1221: @55642 |
| 20241 | /* 55642 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(55696), // Rule ID 923 // |
| 20242 | /* 55647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20243 | /* 55650 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 20244 | /* 55655 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20245 | /* 55658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20246 | /* 55661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20247 | /* 55664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20248 | /* 55668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20249 | /* 55672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20250 | /* 55676 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4085:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20251 | /* 55676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16), |
| 20252 | /* 55679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20253 | /* 55681 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20254 | /* 55683 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20255 | /* 55685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20256 | /* 55688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20257 | /* 55694 */ GIR_RootConstrainSelectedInstOperands, |
| 20258 | /* 55695 */ // GIR_Coverage, 923, |
| 20259 | /* 55695 */ GIR_EraseRootFromParent_Done, |
| 20260 | /* 55696 */ // Label 1222: @55696 |
| 20261 | /* 55696 */ GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(55750), // Rule ID 924 // |
| 20262 | /* 55701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20263 | /* 55704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 20264 | /* 55709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20265 | /* 55712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20266 | /* 55715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20267 | /* 55718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20268 | /* 55722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20269 | /* 55726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20270 | /* 55730 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4085:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20271 | /* 55730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32), |
| 20272 | /* 55733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20273 | /* 55735 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20274 | /* 55737 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20275 | /* 55739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20276 | /* 55742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20277 | /* 55748 */ GIR_RootConstrainSelectedInstOperands, |
| 20278 | /* 55749 */ // GIR_Coverage, 924, |
| 20279 | /* 55749 */ GIR_EraseRootFromParent_Done, |
| 20280 | /* 55750 */ // Label 1223: @55750 |
| 20281 | /* 55750 */ GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(55804), // Rule ID 925 // |
| 20282 | /* 55755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20283 | /* 55758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 20284 | /* 55763 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20285 | /* 55766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20286 | /* 55769 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20287 | /* 55772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20288 | /* 55776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20289 | /* 55780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20290 | /* 55784 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4085:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20291 | /* 55784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16), |
| 20292 | /* 55787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20293 | /* 55789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20294 | /* 55791 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20295 | /* 55793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20296 | /* 55796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20297 | /* 55802 */ GIR_RootConstrainSelectedInstOperands, |
| 20298 | /* 55803 */ // GIR_Coverage, 925, |
| 20299 | /* 55803 */ GIR_EraseRootFromParent_Done, |
| 20300 | /* 55804 */ // Label 1224: @55804 |
| 20301 | /* 55804 */ GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(55858), // Rule ID 926 // |
| 20302 | /* 55809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20303 | /* 55812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 20304 | /* 55817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20305 | /* 55820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20306 | /* 55823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20307 | /* 55826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20308 | /* 55830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20309 | /* 55834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20310 | /* 55838 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4085:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20311 | /* 55838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32), |
| 20312 | /* 55841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20313 | /* 55843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20314 | /* 55845 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20315 | /* 55847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20316 | /* 55850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20317 | /* 55856 */ GIR_RootConstrainSelectedInstOperands, |
| 20318 | /* 55857 */ // GIR_Coverage, 926, |
| 20319 | /* 55857 */ GIR_EraseRootFromParent_Done, |
| 20320 | /* 55858 */ // Label 1225: @55858 |
| 20321 | /* 55858 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(55912), // Rule ID 927 // |
| 20322 | /* 55863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20323 | /* 55866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 20324 | /* 55871 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20325 | /* 55874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20326 | /* 55877 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20327 | /* 55880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20328 | /* 55884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20329 | /* 55888 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20330 | /* 55892 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4085:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20331 | /* 55892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8), |
| 20332 | /* 55895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20333 | /* 55897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20334 | /* 55899 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20335 | /* 55901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20336 | /* 55904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20337 | /* 55910 */ GIR_RootConstrainSelectedInstOperands, |
| 20338 | /* 55911 */ // GIR_Coverage, 927, |
| 20339 | /* 55911 */ GIR_EraseRootFromParent_Done, |
| 20340 | /* 55912 */ // Label 1226: @55912 |
| 20341 | /* 55912 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(55966), // Rule ID 928 // |
| 20342 | /* 55917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20343 | /* 55920 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 20344 | /* 55925 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20345 | /* 55928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20346 | /* 55931 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20347 | /* 55934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20348 | /* 55938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20349 | /* 55942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20350 | /* 55946 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4085:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20351 | /* 55946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8), |
| 20352 | /* 55949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20353 | /* 55951 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20354 | /* 55953 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20355 | /* 55955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20356 | /* 55958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20357 | /* 55964 */ GIR_RootConstrainSelectedInstOperands, |
| 20358 | /* 55965 */ // GIR_Coverage, 928, |
| 20359 | /* 55965 */ GIR_EraseRootFromParent_Done, |
| 20360 | /* 55966 */ // Label 1227: @55966 |
| 20361 | /* 55966 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(56020), // Rule ID 929 // |
| 20362 | /* 55971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20363 | /* 55974 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 20364 | /* 55979 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20365 | /* 55982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20366 | /* 55985 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20367 | /* 55988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20368 | /* 55992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20369 | /* 55996 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20370 | /* 56000 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4086:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20371 | /* 56000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16), |
| 20372 | /* 56003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20373 | /* 56005 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20374 | /* 56007 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20375 | /* 56009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20376 | /* 56012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20377 | /* 56018 */ GIR_RootConstrainSelectedInstOperands, |
| 20378 | /* 56019 */ // GIR_Coverage, 929, |
| 20379 | /* 56019 */ GIR_EraseRootFromParent_Done, |
| 20380 | /* 56020 */ // Label 1228: @56020 |
| 20381 | /* 56020 */ GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(56074), // Rule ID 930 // |
| 20382 | /* 56025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20383 | /* 56028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 20384 | /* 56033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20385 | /* 56036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20386 | /* 56039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20387 | /* 56042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20388 | /* 56046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20389 | /* 56050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20390 | /* 56054 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4086:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20391 | /* 56054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32), |
| 20392 | /* 56057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20393 | /* 56059 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20394 | /* 56061 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20395 | /* 56063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20396 | /* 56066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20397 | /* 56072 */ GIR_RootConstrainSelectedInstOperands, |
| 20398 | /* 56073 */ // GIR_Coverage, 930, |
| 20399 | /* 56073 */ GIR_EraseRootFromParent_Done, |
| 20400 | /* 56074 */ // Label 1229: @56074 |
| 20401 | /* 56074 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(56128), // Rule ID 931 // |
| 20402 | /* 56079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20403 | /* 56082 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 20404 | /* 56087 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20405 | /* 56090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20406 | /* 56093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20407 | /* 56096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20408 | /* 56100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20409 | /* 56104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20410 | /* 56108 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4086:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20411 | /* 56108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16), |
| 20412 | /* 56111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20413 | /* 56113 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20414 | /* 56115 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20415 | /* 56117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20416 | /* 56120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20417 | /* 56126 */ GIR_RootConstrainSelectedInstOperands, |
| 20418 | /* 56127 */ // GIR_Coverage, 931, |
| 20419 | /* 56127 */ GIR_EraseRootFromParent_Done, |
| 20420 | /* 56128 */ // Label 1230: @56128 |
| 20421 | /* 56128 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(56182), // Rule ID 932 // |
| 20422 | /* 56133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20423 | /* 56136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 20424 | /* 56141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20425 | /* 56144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20426 | /* 56147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20427 | /* 56150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20428 | /* 56154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20429 | /* 56158 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20430 | /* 56162 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4086:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20431 | /* 56162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32), |
| 20432 | /* 56165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20433 | /* 56167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20434 | /* 56169 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20435 | /* 56171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20436 | /* 56174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20437 | /* 56180 */ GIR_RootConstrainSelectedInstOperands, |
| 20438 | /* 56181 */ // GIR_Coverage, 932, |
| 20439 | /* 56181 */ GIR_EraseRootFromParent_Done, |
| 20440 | /* 56182 */ // Label 1231: @56182 |
| 20441 | /* 56182 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(56236), // Rule ID 933 // |
| 20442 | /* 56187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20443 | /* 56190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 20444 | /* 56195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20445 | /* 56198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20446 | /* 56201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20447 | /* 56204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20448 | /* 56208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20449 | /* 56212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20450 | /* 56216 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4086:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20451 | /* 56216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8), |
| 20452 | /* 56219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20453 | /* 56221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20454 | /* 56223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20455 | /* 56225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20456 | /* 56228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20457 | /* 56234 */ GIR_RootConstrainSelectedInstOperands, |
| 20458 | /* 56235 */ // GIR_Coverage, 933, |
| 20459 | /* 56235 */ GIR_EraseRootFromParent_Done, |
| 20460 | /* 56236 */ // Label 1232: @56236 |
| 20461 | /* 56236 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(56290), // Rule ID 934 // |
| 20462 | /* 56241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20463 | /* 56244 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 20464 | /* 56249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20465 | /* 56252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20466 | /* 56255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20467 | /* 56258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20468 | /* 56262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20469 | /* 56266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20470 | /* 56270 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4086:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20471 | /* 56270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8), |
| 20472 | /* 56273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20473 | /* 56275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20474 | /* 56277 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20475 | /* 56279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20476 | /* 56282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20477 | /* 56288 */ GIR_RootConstrainSelectedInstOperands, |
| 20478 | /* 56289 */ // GIR_Coverage, 934, |
| 20479 | /* 56289 */ GIR_EraseRootFromParent_Done, |
| 20480 | /* 56290 */ // Label 1233: @56290 |
| 20481 | /* 56290 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(56344), // Rule ID 951 // |
| 20482 | /* 56295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20483 | /* 56298 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 20484 | /* 56303 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20485 | /* 56306 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20486 | /* 56309 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20487 | /* 56312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20488 | /* 56316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20489 | /* 56320 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20490 | /* 56324 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4082:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20491 | /* 56324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8), |
| 20492 | /* 56327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20493 | /* 56329 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20494 | /* 56331 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20495 | /* 56333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20496 | /* 56336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20497 | /* 56342 */ GIR_RootConstrainSelectedInstOperands, |
| 20498 | /* 56343 */ // GIR_Coverage, 951, |
| 20499 | /* 56343 */ GIR_EraseRootFromParent_Done, |
| 20500 | /* 56344 */ // Label 1234: @56344 |
| 20501 | /* 56344 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(56398), // Rule ID 952 // |
| 20502 | /* 56349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20503 | /* 56352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 20504 | /* 56357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20505 | /* 56360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20506 | /* 56363 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20507 | /* 56366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20508 | /* 56370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20509 | /* 56374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20510 | /* 56378 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4082:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20511 | /* 56378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16), |
| 20512 | /* 56381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20513 | /* 56383 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20514 | /* 56385 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20515 | /* 56387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20516 | /* 56390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20517 | /* 56396 */ GIR_RootConstrainSelectedInstOperands, |
| 20518 | /* 56397 */ // GIR_Coverage, 952, |
| 20519 | /* 56397 */ GIR_EraseRootFromParent_Done, |
| 20520 | /* 56398 */ // Label 1235: @56398 |
| 20521 | /* 56398 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(56452), // Rule ID 953 // |
| 20522 | /* 56403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20523 | /* 56406 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 20524 | /* 56411 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20525 | /* 56414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20526 | /* 56417 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20527 | /* 56420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20528 | /* 56424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20529 | /* 56428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20530 | /* 56432 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4082:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 20531 | /* 56432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32), |
| 20532 | /* 56435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20533 | /* 56437 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20534 | /* 56439 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20535 | /* 56441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20536 | /* 56444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20537 | /* 56450 */ GIR_RootConstrainSelectedInstOperands, |
| 20538 | /* 56451 */ // GIR_Coverage, 953, |
| 20539 | /* 56451 */ GIR_EraseRootFromParent_Done, |
| 20540 | /* 56452 */ // Label 1236: @56452 |
| 20541 | /* 56452 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(56506), // Rule ID 960 // |
| 20542 | /* 56457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20543 | /* 56460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 20544 | /* 56465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20545 | /* 56468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20546 | /* 56471 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20547 | /* 56474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20548 | /* 56478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20549 | /* 56482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20550 | /* 56486 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4051:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20551 | /* 56486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd), |
| 20552 | /* 56489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20553 | /* 56491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20554 | /* 56493 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20555 | /* 56495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20556 | /* 56498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20557 | /* 56504 */ GIR_RootConstrainSelectedInstOperands, |
| 20558 | /* 56505 */ // GIR_Coverage, 960, |
| 20559 | /* 56505 */ GIR_EraseRootFromParent_Done, |
| 20560 | /* 56506 */ // Label 1237: @56506 |
| 20561 | /* 56506 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(56560), // Rule ID 961 // |
| 20562 | /* 56511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20563 | /* 56514 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 20564 | /* 56519 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20565 | /* 56522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20566 | /* 56525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20567 | /* 56528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20568 | /* 56532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20569 | /* 56536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20570 | /* 56540 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4051:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20571 | /* 56540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq), |
| 20572 | /* 56543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20573 | /* 56545 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20574 | /* 56547 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20575 | /* 56549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20576 | /* 56552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20577 | /* 56558 */ GIR_RootConstrainSelectedInstOperands, |
| 20578 | /* 56559 */ // GIR_Coverage, 961, |
| 20579 | /* 56559 */ GIR_EraseRootFromParent_Done, |
| 20580 | /* 56560 */ // Label 1238: @56560 |
| 20581 | /* 56560 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(56614), // Rule ID 974 // |
| 20582 | /* 56565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20583 | /* 56568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 20584 | /* 56573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20585 | /* 56576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20586 | /* 56579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20587 | /* 56582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20588 | /* 56586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20589 | /* 56590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20590 | /* 56594 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20591 | /* 56594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16), |
| 20592 | /* 56597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20593 | /* 56599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20594 | /* 56601 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20595 | /* 56603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20596 | /* 56606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20597 | /* 56612 */ GIR_RootConstrainSelectedInstOperands, |
| 20598 | /* 56613 */ // GIR_Coverage, 974, |
| 20599 | /* 56613 */ GIR_EraseRootFromParent_Done, |
| 20600 | /* 56614 */ // Label 1239: @56614 |
| 20601 | /* 56614 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(56668), // Rule ID 975 // |
| 20602 | /* 56619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20603 | /* 56622 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 20604 | /* 56627 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20605 | /* 56630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20606 | /* 56633 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20607 | /* 56636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20608 | /* 56640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20609 | /* 56644 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20610 | /* 56648 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20611 | /* 56648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32), |
| 20612 | /* 56651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20613 | /* 56653 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20614 | /* 56655 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20615 | /* 56657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20616 | /* 56660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20617 | /* 56666 */ GIR_RootConstrainSelectedInstOperands, |
| 20618 | /* 56667 */ // GIR_Coverage, 975, |
| 20619 | /* 56667 */ GIR_EraseRootFromParent_Done, |
| 20620 | /* 56668 */ // Label 1240: @56668 |
| 20621 | /* 56668 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(56722), // Rule ID 976 // |
| 20622 | /* 56673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20623 | /* 56676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 20624 | /* 56681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20625 | /* 56684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20626 | /* 56687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20627 | /* 56690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20628 | /* 56694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20629 | /* 56698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20630 | /* 56702 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4062:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20631 | /* 56702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16), |
| 20632 | /* 56705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20633 | /* 56707 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20634 | /* 56709 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20635 | /* 56711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20636 | /* 56714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20637 | /* 56720 */ GIR_RootConstrainSelectedInstOperands, |
| 20638 | /* 56721 */ // GIR_Coverage, 976, |
| 20639 | /* 56721 */ GIR_EraseRootFromParent_Done, |
| 20640 | /* 56722 */ // Label 1241: @56722 |
| 20641 | /* 56722 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(56776), // Rule ID 977 // |
| 20642 | /* 56727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20643 | /* 56730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 20644 | /* 56735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20645 | /* 56738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20646 | /* 56741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20647 | /* 56744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20648 | /* 56748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20649 | /* 56752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20650 | /* 56756 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4062:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20651 | /* 56756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32), |
| 20652 | /* 56759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20653 | /* 56761 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20654 | /* 56763 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20655 | /* 56765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20656 | /* 56768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20657 | /* 56774 */ GIR_RootConstrainSelectedInstOperands, |
| 20658 | /* 56775 */ // GIR_Coverage, 977, |
| 20659 | /* 56775 */ GIR_EraseRootFromParent_Done, |
| 20660 | /* 56776 */ // Label 1242: @56776 |
| 20661 | /* 56776 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(56830), // Rule ID 982 // |
| 20662 | /* 56781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20663 | /* 56784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 20664 | /* 56789 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20665 | /* 56792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20666 | /* 56795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20667 | /* 56798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20668 | /* 56802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20669 | /* 56806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20670 | /* 56810 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4070:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20671 | /* 56810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16), |
| 20672 | /* 56813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20673 | /* 56815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20674 | /* 56817 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20675 | /* 56819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20676 | /* 56822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20677 | /* 56828 */ GIR_RootConstrainSelectedInstOperands, |
| 20678 | /* 56829 */ // GIR_Coverage, 982, |
| 20679 | /* 56829 */ GIR_EraseRootFromParent_Done, |
| 20680 | /* 56830 */ // Label 1243: @56830 |
| 20681 | /* 56830 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(56884), // Rule ID 983 // |
| 20682 | /* 56835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20683 | /* 56838 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 20684 | /* 56843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20685 | /* 56846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20686 | /* 56849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20687 | /* 56852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20688 | /* 56856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20689 | /* 56860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20690 | /* 56864 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4070:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20691 | /* 56864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32), |
| 20692 | /* 56867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20693 | /* 56869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20694 | /* 56871 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20695 | /* 56873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20696 | /* 56876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20697 | /* 56882 */ GIR_RootConstrainSelectedInstOperands, |
| 20698 | /* 56883 */ // GIR_Coverage, 983, |
| 20699 | /* 56883 */ GIR_EraseRootFromParent_Done, |
| 20700 | /* 56884 */ // Label 1244: @56884 |
| 20701 | /* 56884 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(56938), // Rule ID 984 // |
| 20702 | /* 56889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20703 | /* 56892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 20704 | /* 56897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20705 | /* 56900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20706 | /* 56903 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20707 | /* 56906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20708 | /* 56910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20709 | /* 56914 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20710 | /* 56918 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4070:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20711 | /* 56918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16), |
| 20712 | /* 56921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20713 | /* 56923 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20714 | /* 56925 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20715 | /* 56927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20716 | /* 56930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20717 | /* 56936 */ GIR_RootConstrainSelectedInstOperands, |
| 20718 | /* 56937 */ // GIR_Coverage, 984, |
| 20719 | /* 56937 */ GIR_EraseRootFromParent_Done, |
| 20720 | /* 56938 */ // Label 1245: @56938 |
| 20721 | /* 56938 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(56992), // Rule ID 985 // |
| 20722 | /* 56943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20723 | /* 56946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 20724 | /* 56951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20725 | /* 56954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20726 | /* 56957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20727 | /* 56960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20728 | /* 56964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20729 | /* 56968 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20730 | /* 56972 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4070:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20731 | /* 56972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32), |
| 20732 | /* 56975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20733 | /* 56977 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20734 | /* 56979 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20735 | /* 56981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20736 | /* 56984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20737 | /* 56990 */ GIR_RootConstrainSelectedInstOperands, |
| 20738 | /* 56991 */ // GIR_Coverage, 985, |
| 20739 | /* 56991 */ GIR_EraseRootFromParent_Done, |
| 20740 | /* 56992 */ // Label 1246: @56992 |
| 20741 | /* 56992 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(57046), // Rule ID 996 // |
| 20742 | /* 56997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20743 | /* 57000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 20744 | /* 57005 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20745 | /* 57008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20746 | /* 57011 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20747 | /* 57014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20748 | /* 57018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20749 | /* 57022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20750 | /* 57026 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4048:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20751 | /* 57026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8), |
| 20752 | /* 57029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20753 | /* 57031 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20754 | /* 57033 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20755 | /* 57035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20756 | /* 57038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20757 | /* 57044 */ GIR_RootConstrainSelectedInstOperands, |
| 20758 | /* 57045 */ // GIR_Coverage, 996, |
| 20759 | /* 57045 */ GIR_EraseRootFromParent_Done, |
| 20760 | /* 57046 */ // Label 1247: @57046 |
| 20761 | /* 57046 */ GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(57091), // Rule ID 997 // |
| 20762 | /* 57051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 20763 | /* 57054 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 20764 | /* 57059 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20765 | /* 57062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20766 | /* 57065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20767 | /* 57068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20768 | /* 57072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20769 | /* 57076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20770 | /* 57080 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4048:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 20771 | /* 57080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64), |
| 20772 | /* 57083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20773 | /* 57085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20774 | /* 57087 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20775 | /* 57089 */ GIR_RootConstrainSelectedInstOperands, |
| 20776 | /* 57090 */ // GIR_Coverage, 997, |
| 20777 | /* 57090 */ GIR_EraseRootFromParent_Done, |
| 20778 | /* 57091 */ // Label 1248: @57091 |
| 20779 | /* 57091 */ GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(57145), // Rule ID 1002 // |
| 20780 | /* 57096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20781 | /* 57099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 20782 | /* 57104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20783 | /* 57107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20784 | /* 57110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20785 | /* 57113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20786 | /* 57117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20787 | /* 57121 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20788 | /* 57125 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20789 | /* 57125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32), |
| 20790 | /* 57128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20791 | /* 57130 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20792 | /* 57132 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20793 | /* 57134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20794 | /* 57137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20795 | /* 57143 */ GIR_RootConstrainSelectedInstOperands, |
| 20796 | /* 57144 */ // GIR_Coverage, 1002, |
| 20797 | /* 57144 */ GIR_EraseRootFromParent_Done, |
| 20798 | /* 57145 */ // Label 1249: @57145 |
| 20799 | /* 57145 */ GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(57199), // Rule ID 1003 // |
| 20800 | /* 57150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20801 | /* 57153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 20802 | /* 57158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20803 | /* 57161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20804 | /* 57164 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20805 | /* 57167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20806 | /* 57171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20807 | /* 57175 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20808 | /* 57179 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20809 | /* 57179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64), |
| 20810 | /* 57182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20811 | /* 57184 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20812 | /* 57186 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20813 | /* 57188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20814 | /* 57191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20815 | /* 57197 */ GIR_RootConstrainSelectedInstOperands, |
| 20816 | /* 57198 */ // GIR_Coverage, 1003, |
| 20817 | /* 57198 */ GIR_EraseRootFromParent_Done, |
| 20818 | /* 57199 */ // Label 1250: @57199 |
| 20819 | /* 57199 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(57253), // Rule ID 1157 // |
| 20820 | /* 57204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20821 | /* 57207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 20822 | /* 57212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20823 | /* 57215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20824 | /* 57218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20825 | /* 57221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20826 | /* 57225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20827 | /* 57229 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20828 | /* 57233 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4027:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20829 | /* 57233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16), |
| 20830 | /* 57236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20831 | /* 57238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20832 | /* 57240 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20833 | /* 57242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20834 | /* 57245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20835 | /* 57251 */ GIR_RootConstrainSelectedInstOperands, |
| 20836 | /* 57252 */ // GIR_Coverage, 1157, |
| 20837 | /* 57252 */ GIR_EraseRootFromParent_Done, |
| 20838 | /* 57253 */ // Label 1251: @57253 |
| 20839 | /* 57253 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(57307), // Rule ID 1158 // |
| 20840 | /* 57258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20841 | /* 57261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 20842 | /* 57266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20843 | /* 57269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20844 | /* 57272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20845 | /* 57275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20846 | /* 57279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20847 | /* 57283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20848 | /* 57287 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4027:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20849 | /* 57287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32), |
| 20850 | /* 57290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20851 | /* 57292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20852 | /* 57294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20853 | /* 57296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20854 | /* 57299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20855 | /* 57305 */ GIR_RootConstrainSelectedInstOperands, |
| 20856 | /* 57306 */ // GIR_Coverage, 1158, |
| 20857 | /* 57306 */ GIR_EraseRootFromParent_Done, |
| 20858 | /* 57307 */ // Label 1252: @57307 |
| 20859 | /* 57307 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(57361), // Rule ID 1159 // |
| 20860 | /* 57312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20861 | /* 57315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 20862 | /* 57320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20863 | /* 57323 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20864 | /* 57326 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20865 | /* 57329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20866 | /* 57333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20867 | /* 57337 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20868 | /* 57341 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4027:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20869 | /* 57341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16), |
| 20870 | /* 57344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20871 | /* 57346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20872 | /* 57348 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20873 | /* 57350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20874 | /* 57353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20875 | /* 57359 */ GIR_RootConstrainSelectedInstOperands, |
| 20876 | /* 57360 */ // GIR_Coverage, 1159, |
| 20877 | /* 57360 */ GIR_EraseRootFromParent_Done, |
| 20878 | /* 57361 */ // Label 1253: @57361 |
| 20879 | /* 57361 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(57415), // Rule ID 1160 // |
| 20880 | /* 57366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20881 | /* 57369 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 20882 | /* 57374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20883 | /* 57377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20884 | /* 57380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20885 | /* 57383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20886 | /* 57387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20887 | /* 57391 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20888 | /* 57395 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4027:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20889 | /* 57395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32), |
| 20890 | /* 57398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20891 | /* 57400 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20892 | /* 57402 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20893 | /* 57404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20894 | /* 57407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20895 | /* 57413 */ GIR_RootConstrainSelectedInstOperands, |
| 20896 | /* 57414 */ // GIR_Coverage, 1160, |
| 20897 | /* 57414 */ GIR_EraseRootFromParent_Done, |
| 20898 | /* 57415 */ // Label 1254: @57415 |
| 20899 | /* 57415 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(57469), // Rule ID 1161 // |
| 20900 | /* 57420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20901 | /* 57423 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 20902 | /* 57428 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20903 | /* 57431 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20904 | /* 57434 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20905 | /* 57437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20906 | /* 57441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20907 | /* 57445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20908 | /* 57449 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4027:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20909 | /* 57449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8), |
| 20910 | /* 57452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20911 | /* 57454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20912 | /* 57456 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20913 | /* 57458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20914 | /* 57461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20915 | /* 57467 */ GIR_RootConstrainSelectedInstOperands, |
| 20916 | /* 57468 */ // GIR_Coverage, 1161, |
| 20917 | /* 57468 */ GIR_EraseRootFromParent_Done, |
| 20918 | /* 57469 */ // Label 1255: @57469 |
| 20919 | /* 57469 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(57523), // Rule ID 1162 // |
| 20920 | /* 57474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20921 | /* 57477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 20922 | /* 57482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20923 | /* 57485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20924 | /* 57488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20925 | /* 57491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20926 | /* 57495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20927 | /* 57499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20928 | /* 57503 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4027:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20929 | /* 57503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8), |
| 20930 | /* 57506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20931 | /* 57508 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20932 | /* 57510 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20933 | /* 57512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20934 | /* 57515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20935 | /* 57521 */ GIR_RootConstrainSelectedInstOperands, |
| 20936 | /* 57522 */ // GIR_Coverage, 1162, |
| 20937 | /* 57522 */ GIR_EraseRootFromParent_Done, |
| 20938 | /* 57523 */ // Label 1256: @57523 |
| 20939 | /* 57523 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(57577), // Rule ID 1163 // |
| 20940 | /* 57528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20941 | /* 57531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 20942 | /* 57536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20943 | /* 57539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20944 | /* 57542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20945 | /* 57545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20946 | /* 57549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20947 | /* 57553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20948 | /* 57557 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4028:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20949 | /* 57557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16), |
| 20950 | /* 57560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20951 | /* 57562 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20952 | /* 57564 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20953 | /* 57566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20954 | /* 57569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20955 | /* 57575 */ GIR_RootConstrainSelectedInstOperands, |
| 20956 | /* 57576 */ // GIR_Coverage, 1163, |
| 20957 | /* 57576 */ GIR_EraseRootFromParent_Done, |
| 20958 | /* 57577 */ // Label 1257: @57577 |
| 20959 | /* 57577 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(57631), // Rule ID 1164 // |
| 20960 | /* 57582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20961 | /* 57585 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 20962 | /* 57590 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20963 | /* 57593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20964 | /* 57596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20965 | /* 57599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20966 | /* 57603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20967 | /* 57607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20968 | /* 57611 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4028:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20969 | /* 57611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32), |
| 20970 | /* 57614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20971 | /* 57616 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20972 | /* 57618 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20973 | /* 57620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20974 | /* 57623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20975 | /* 57629 */ GIR_RootConstrainSelectedInstOperands, |
| 20976 | /* 57630 */ // GIR_Coverage, 1164, |
| 20977 | /* 57630 */ GIR_EraseRootFromParent_Done, |
| 20978 | /* 57631 */ // Label 1258: @57631 |
| 20979 | /* 57631 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(57685), // Rule ID 1165 // |
| 20980 | /* 57636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20981 | /* 57639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 20982 | /* 57644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20983 | /* 57647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20984 | /* 57650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20985 | /* 57653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20986 | /* 57657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20987 | /* 57661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20988 | /* 57665 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4028:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20989 | /* 57665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16), |
| 20990 | /* 57668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20991 | /* 57670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20992 | /* 57672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20993 | /* 57674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20994 | /* 57677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20995 | /* 57683 */ GIR_RootConstrainSelectedInstOperands, |
| 20996 | /* 57684 */ // GIR_Coverage, 1165, |
| 20997 | /* 57684 */ GIR_EraseRootFromParent_Done, |
| 20998 | /* 57685 */ // Label 1259: @57685 |
| 20999 | /* 57685 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(57739), // Rule ID 1166 // |
| 21000 | /* 57690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21001 | /* 57693 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 21002 | /* 57698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21003 | /* 57701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21004 | /* 57704 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21005 | /* 57707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21006 | /* 57711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21007 | /* 57715 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21008 | /* 57719 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4028:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 21009 | /* 57719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32), |
| 21010 | /* 57722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21011 | /* 57724 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21012 | /* 57726 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21013 | /* 57728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21014 | /* 57731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21015 | /* 57737 */ GIR_RootConstrainSelectedInstOperands, |
| 21016 | /* 57738 */ // GIR_Coverage, 1166, |
| 21017 | /* 57738 */ GIR_EraseRootFromParent_Done, |
| 21018 | /* 57739 */ // Label 1260: @57739 |
| 21019 | /* 57739 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(57793), // Rule ID 1167 // |
| 21020 | /* 57744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21021 | /* 57747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 21022 | /* 57752 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21023 | /* 57755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21024 | /* 57758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21025 | /* 57761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21026 | /* 57765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21027 | /* 57769 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21028 | /* 57773 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4028:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21029 | /* 57773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8), |
| 21030 | /* 57776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21031 | /* 57778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21032 | /* 57780 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21033 | /* 57782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21034 | /* 57785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21035 | /* 57791 */ GIR_RootConstrainSelectedInstOperands, |
| 21036 | /* 57792 */ // GIR_Coverage, 1167, |
| 21037 | /* 57792 */ GIR_EraseRootFromParent_Done, |
| 21038 | /* 57793 */ // Label 1261: @57793 |
| 21039 | /* 57793 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(57847), // Rule ID 1168 // |
| 21040 | /* 57798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21041 | /* 57801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 21042 | /* 57806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21043 | /* 57809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21044 | /* 57812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21045 | /* 57815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21046 | /* 57819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21047 | /* 57823 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21048 | /* 57827 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4028:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 21049 | /* 57827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8), |
| 21050 | /* 57830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21051 | /* 57832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21052 | /* 57834 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21053 | /* 57836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21054 | /* 57839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21055 | /* 57845 */ GIR_RootConstrainSelectedInstOperands, |
| 21056 | /* 57846 */ // GIR_Coverage, 1168, |
| 21057 | /* 57846 */ GIR_EraseRootFromParent_Done, |
| 21058 | /* 57847 */ // Label 1262: @57847 |
| 21059 | /* 57847 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(57901), // Rule ID 1185 // |
| 21060 | /* 57852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21061 | /* 57855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 21062 | /* 57860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21063 | /* 57863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21064 | /* 57866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21065 | /* 57869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21066 | /* 57873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21067 | /* 57877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21068 | /* 57881 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4092:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 21069 | /* 57881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8), |
| 21070 | /* 57884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21071 | /* 57886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21072 | /* 57888 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21073 | /* 57890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21074 | /* 57893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21075 | /* 57899 */ GIR_RootConstrainSelectedInstOperands, |
| 21076 | /* 57900 */ // GIR_Coverage, 1185, |
| 21077 | /* 57900 */ GIR_EraseRootFromParent_Done, |
| 21078 | /* 57901 */ // Label 1263: @57901 |
| 21079 | /* 57901 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(57955), // Rule ID 1186 // |
| 21080 | /* 57906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21081 | /* 57909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 21082 | /* 57914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21083 | /* 57917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21084 | /* 57920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21085 | /* 57923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21086 | /* 57927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21087 | /* 57931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21088 | /* 57935 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4092:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 21089 | /* 57935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16), |
| 21090 | /* 57938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21091 | /* 57940 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21092 | /* 57942 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21093 | /* 57944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21094 | /* 57947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21095 | /* 57953 */ GIR_RootConstrainSelectedInstOperands, |
| 21096 | /* 57954 */ // GIR_Coverage, 1186, |
| 21097 | /* 57954 */ GIR_EraseRootFromParent_Done, |
| 21098 | /* 57955 */ // Label 1264: @57955 |
| 21099 | /* 57955 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(58009), // Rule ID 1187 // |
| 21100 | /* 57960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21101 | /* 57963 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 21102 | /* 57968 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21103 | /* 57971 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21104 | /* 57974 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21105 | /* 57977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21106 | /* 57981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21107 | /* 57985 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21108 | /* 57989 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4092:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 21109 | /* 57989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32), |
| 21110 | /* 57992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21111 | /* 57994 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21112 | /* 57996 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21113 | /* 57998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21114 | /* 58001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21115 | /* 58007 */ GIR_RootConstrainSelectedInstOperands, |
| 21116 | /* 58008 */ // GIR_Coverage, 1187, |
| 21117 | /* 58008 */ GIR_EraseRootFromParent_Done, |
| 21118 | /* 58009 */ // Label 1265: @58009 |
| 21119 | /* 58009 */ GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(58063), // Rule ID 1280 // |
| 21120 | /* 58014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21121 | /* 58017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 21122 | /* 58022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21123 | /* 58025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21124 | /* 58028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21125 | /* 58031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21126 | /* 58035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21127 | /* 58039 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21128 | /* 58043 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4003:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21129 | /* 58043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd), |
| 21130 | /* 58046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21131 | /* 58048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21132 | /* 58050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21133 | /* 58052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21134 | /* 58055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21135 | /* 58061 */ GIR_RootConstrainSelectedInstOperands, |
| 21136 | /* 58062 */ // GIR_Coverage, 1280, |
| 21137 | /* 58062 */ GIR_EraseRootFromParent_Done, |
| 21138 | /* 58063 */ // Label 1266: @58063 |
| 21139 | /* 58063 */ GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(58117), // Rule ID 1281 // |
| 21140 | /* 58068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21141 | /* 58071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 21142 | /* 58076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21143 | /* 58079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21144 | /* 58082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21145 | /* 58085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21146 | /* 58089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21147 | /* 58093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21148 | /* 58097 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4003:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 21149 | /* 58097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq), |
| 21150 | /* 58100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21151 | /* 58102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21152 | /* 58104 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21153 | /* 58106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21154 | /* 58109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21155 | /* 58115 */ GIR_RootConstrainSelectedInstOperands, |
| 21156 | /* 58116 */ // GIR_Coverage, 1281, |
| 21157 | /* 58116 */ GIR_EraseRootFromParent_Done, |
| 21158 | /* 58117 */ // Label 1267: @58117 |
| 21159 | /* 58117 */ GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(58171), // Rule ID 1282 // |
| 21160 | /* 58122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21161 | /* 58125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 21162 | /* 58130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21163 | /* 58133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21164 | /* 58136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21165 | /* 58139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21166 | /* 58143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21167 | /* 58147 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21168 | /* 58151 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4003:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21169 | /* 58151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd), |
| 21170 | /* 58154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21171 | /* 58156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21172 | /* 58158 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21173 | /* 58160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21174 | /* 58163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21175 | /* 58169 */ GIR_RootConstrainSelectedInstOperands, |
| 21176 | /* 58170 */ // GIR_Coverage, 1282, |
| 21177 | /* 58170 */ GIR_EraseRootFromParent_Done, |
| 21178 | /* 58171 */ // Label 1268: @58171 |
| 21179 | /* 58171 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(58225), // Rule ID 1283 // |
| 21180 | /* 58176 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21181 | /* 58179 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 21182 | /* 58184 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21183 | /* 58187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21184 | /* 58190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21185 | /* 58193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21186 | /* 58197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21187 | /* 58201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21188 | /* 58205 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4003:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 21189 | /* 58205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq), |
| 21190 | /* 58208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21191 | /* 58210 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21192 | /* 58212 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21193 | /* 58214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21194 | /* 58217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21195 | /* 58223 */ GIR_RootConstrainSelectedInstOperands, |
| 21196 | /* 58224 */ // GIR_Coverage, 1283, |
| 21197 | /* 58224 */ GIR_EraseRootFromParent_Done, |
| 21198 | /* 58225 */ // Label 1269: @58225 |
| 21199 | /* 58225 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(58279), // Rule ID 1284 // |
| 21200 | /* 58230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21201 | /* 58233 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 21202 | /* 58238 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21203 | /* 58241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21204 | /* 58244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21205 | /* 58247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21206 | /* 58251 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21207 | /* 58255 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21208 | /* 58259 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4004:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21209 | /* 58259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd), |
| 21210 | /* 58262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21211 | /* 58264 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21212 | /* 58266 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21213 | /* 58268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21214 | /* 58271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21215 | /* 58277 */ GIR_RootConstrainSelectedInstOperands, |
| 21216 | /* 58278 */ // GIR_Coverage, 1284, |
| 21217 | /* 58278 */ GIR_EraseRootFromParent_Done, |
| 21218 | /* 58279 */ // Label 1270: @58279 |
| 21219 | /* 58279 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(58333), // Rule ID 1285 // |
| 21220 | /* 58284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21221 | /* 58287 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 21222 | /* 58292 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21223 | /* 58295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21224 | /* 58298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21225 | /* 58301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21226 | /* 58305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21227 | /* 58309 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21228 | /* 58313 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4004:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 21229 | /* 58313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq), |
| 21230 | /* 58316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21231 | /* 58318 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21232 | /* 58320 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21233 | /* 58322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21234 | /* 58325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21235 | /* 58331 */ GIR_RootConstrainSelectedInstOperands, |
| 21236 | /* 58332 */ // GIR_Coverage, 1285, |
| 21237 | /* 58332 */ GIR_EraseRootFromParent_Done, |
| 21238 | /* 58333 */ // Label 1271: @58333 |
| 21239 | /* 58333 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(58387), // Rule ID 1286 // |
| 21240 | /* 58338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21241 | /* 58341 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 21242 | /* 58346 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21243 | /* 58349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21244 | /* 58352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21245 | /* 58355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21246 | /* 58359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21247 | /* 58363 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21248 | /* 58367 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4004:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21249 | /* 58367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd), |
| 21250 | /* 58370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21251 | /* 58372 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21252 | /* 58374 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21253 | /* 58376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21254 | /* 58379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21255 | /* 58385 */ GIR_RootConstrainSelectedInstOperands, |
| 21256 | /* 58386 */ // GIR_Coverage, 1286, |
| 21257 | /* 58386 */ GIR_EraseRootFromParent_Done, |
| 21258 | /* 58387 */ // Label 1272: @58387 |
| 21259 | /* 58387 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(58441), // Rule ID 1287 // |
| 21260 | /* 58392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21261 | /* 58395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 21262 | /* 58400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21263 | /* 58403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21264 | /* 58406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21265 | /* 58409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21266 | /* 58413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21267 | /* 58417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21268 | /* 58421 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4004:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 21269 | /* 58421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq), |
| 21270 | /* 58424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21271 | /* 58426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21272 | /* 58428 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21273 | /* 58430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21274 | /* 58433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21275 | /* 58439 */ GIR_RootConstrainSelectedInstOperands, |
| 21276 | /* 58440 */ // GIR_Coverage, 1287, |
| 21277 | /* 58440 */ GIR_EraseRootFromParent_Done, |
| 21278 | /* 58441 */ // Label 1273: @58441 |
| 21279 | /* 58441 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(58495), // Rule ID 1330 // |
| 21280 | /* 58446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21281 | /* 58449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 21282 | /* 58454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21283 | /* 58457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21284 | /* 58460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21285 | /* 58463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21286 | /* 58467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21287 | /* 58471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21288 | /* 58475 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4000:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21289 | /* 58475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd), |
| 21290 | /* 58478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21291 | /* 58480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21292 | /* 58482 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21293 | /* 58484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21294 | /* 58487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21295 | /* 58493 */ GIR_RootConstrainSelectedInstOperands, |
| 21296 | /* 58494 */ // GIR_Coverage, 1330, |
| 21297 | /* 58494 */ GIR_EraseRootFromParent_Done, |
| 21298 | /* 58495 */ // Label 1274: @58495 |
| 21299 | /* 58495 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(58549), // Rule ID 1331 // |
| 21300 | /* 58500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21301 | /* 58503 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 21302 | /* 58508 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21303 | /* 58511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21304 | /* 58514 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21305 | /* 58517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21306 | /* 58521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21307 | /* 58525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21308 | /* 58529 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4000:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 21309 | /* 58529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq), |
| 21310 | /* 58532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21311 | /* 58534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21312 | /* 58536 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21313 | /* 58538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21314 | /* 58541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21315 | /* 58547 */ GIR_RootConstrainSelectedInstOperands, |
| 21316 | /* 58548 */ // GIR_Coverage, 1331, |
| 21317 | /* 58548 */ GIR_EraseRootFromParent_Done, |
| 21318 | /* 58549 */ // Label 1275: @58549 |
| 21319 | /* 58549 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(58603), // Rule ID 1332 // |
| 21320 | /* 58554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21321 | /* 58557 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 21322 | /* 58562 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21323 | /* 58565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21324 | /* 58568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21325 | /* 58571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21326 | /* 58575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21327 | /* 58579 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21328 | /* 58583 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4000:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21329 | /* 58583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd), |
| 21330 | /* 58586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21331 | /* 58588 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21332 | /* 58590 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21333 | /* 58592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21334 | /* 58595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21335 | /* 58601 */ GIR_RootConstrainSelectedInstOperands, |
| 21336 | /* 58602 */ // GIR_Coverage, 1332, |
| 21337 | /* 58602 */ GIR_EraseRootFromParent_Done, |
| 21338 | /* 58603 */ // Label 1276: @58603 |
| 21339 | /* 58603 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(58657), // Rule ID 1333 // |
| 21340 | /* 58608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21341 | /* 58611 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 21342 | /* 58616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21343 | /* 58619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21344 | /* 58622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21345 | /* 58625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21346 | /* 58629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21347 | /* 58633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21348 | /* 58637 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4000:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 21349 | /* 58637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq), |
| 21350 | /* 58640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21351 | /* 58642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21352 | /* 58644 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21353 | /* 58646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21354 | /* 58649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21355 | /* 58655 */ GIR_RootConstrainSelectedInstOperands, |
| 21356 | /* 58656 */ // GIR_Coverage, 1333, |
| 21357 | /* 58656 */ GIR_EraseRootFromParent_Done, |
| 21358 | /* 58657 */ // Label 1277: @58657 |
| 21359 | /* 58657 */ GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(58711), // Rule ID 1398 // |
| 21360 | /* 58662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21361 | /* 58665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 21362 | /* 58670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21363 | /* 58673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21364 | /* 58676 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21365 | /* 58679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21366 | /* 58683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21367 | /* 58687 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21368 | /* 58691 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4054:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21369 | /* 58691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8), |
| 21370 | /* 58694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21371 | /* 58696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21372 | /* 58698 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21373 | /* 58700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21374 | /* 58703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21375 | /* 58709 */ GIR_RootConstrainSelectedInstOperands, |
| 21376 | /* 58710 */ // GIR_Coverage, 1398, |
| 21377 | /* 58710 */ GIR_EraseRootFromParent_Done, |
| 21378 | /* 58711 */ // Label 1278: @58711 |
| 21379 | /* 58711 */ GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(58765), // Rule ID 1399 // |
| 21380 | /* 58716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21381 | /* 58719 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 21382 | /* 58724 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21383 | /* 58727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21384 | /* 58730 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21385 | /* 58733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21386 | /* 58737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21387 | /* 58741 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21388 | /* 58745 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4054:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21389 | /* 58745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16), |
| 21390 | /* 58748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21391 | /* 58750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21392 | /* 58752 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21393 | /* 58754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21394 | /* 58757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21395 | /* 58763 */ GIR_RootConstrainSelectedInstOperands, |
| 21396 | /* 58764 */ // GIR_Coverage, 1399, |
| 21397 | /* 58764 */ GIR_EraseRootFromParent_Done, |
| 21398 | /* 58765 */ // Label 1279: @58765 |
| 21399 | /* 58765 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(58819), // Rule ID 1400 // |
| 21400 | /* 58770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21401 | /* 58773 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 21402 | /* 58778 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21403 | /* 58781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21404 | /* 58784 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21405 | /* 58787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21406 | /* 58791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21407 | /* 58795 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21408 | /* 58799 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4054:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21409 | /* 58799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32), |
| 21410 | /* 58802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21411 | /* 58804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21412 | /* 58806 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21413 | /* 58808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21414 | /* 58811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21415 | /* 58817 */ GIR_RootConstrainSelectedInstOperands, |
| 21416 | /* 58818 */ // GIR_Coverage, 1400, |
| 21417 | /* 58818 */ GIR_EraseRootFromParent_Done, |
| 21418 | /* 58819 */ // Label 1280: @58819 |
| 21419 | /* 58819 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(58873), // Rule ID 1401 // |
| 21420 | /* 58824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21421 | /* 58827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 21422 | /* 58832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21423 | /* 58835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21424 | /* 58838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21425 | /* 58841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21426 | /* 58845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21427 | /* 58849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21428 | /* 58853 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4054:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21429 | /* 58853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf), |
| 21430 | /* 58856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21431 | /* 58858 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21432 | /* 58860 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21433 | /* 58862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21434 | /* 58865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21435 | /* 58871 */ GIR_RootConstrainSelectedInstOperands, |
| 21436 | /* 58872 */ // GIR_Coverage, 1401, |
| 21437 | /* 58872 */ GIR_EraseRootFromParent_Done, |
| 21438 | /* 58873 */ // Label 1281: @58873 |
| 21439 | /* 58873 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(58927), // Rule ID 1402 // |
| 21440 | /* 58878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21441 | /* 58881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 21442 | /* 58886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21443 | /* 58889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21444 | /* 58892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21445 | /* 58895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21446 | /* 58899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21447 | /* 58903 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21448 | /* 58907 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4054:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21449 | /* 58907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh), |
| 21450 | /* 58910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21451 | /* 58912 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21452 | /* 58914 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21453 | /* 58916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21454 | /* 58919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21455 | /* 58925 */ GIR_RootConstrainSelectedInstOperands, |
| 21456 | /* 58926 */ // GIR_Coverage, 1402, |
| 21457 | /* 58926 */ GIR_EraseRootFromParent_Done, |
| 21458 | /* 58927 */ // Label 1282: @58927 |
| 21459 | /* 58927 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(58981), // Rule ID 1415 // |
| 21460 | /* 58932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21461 | /* 58935 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 21462 | /* 58940 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21463 | /* 58943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21464 | /* 58946 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21465 | /* 58949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21466 | /* 58953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21467 | /* 58957 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21468 | /* 58961 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 21469 | /* 58961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8), |
| 21470 | /* 58964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21471 | /* 58966 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21472 | /* 58968 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21473 | /* 58970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21474 | /* 58973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21475 | /* 58979 */ GIR_RootConstrainSelectedInstOperands, |
| 21476 | /* 58980 */ // GIR_Coverage, 1415, |
| 21477 | /* 58980 */ GIR_EraseRootFromParent_Done, |
| 21478 | /* 58981 */ // Label 1283: @58981 |
| 21479 | /* 58981 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(59035), // Rule ID 1416 // |
| 21480 | /* 58986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21481 | /* 58989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 21482 | /* 58994 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21483 | /* 58997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21484 | /* 59000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21485 | /* 59003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21486 | /* 59007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21487 | /* 59011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21488 | /* 59015 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4052:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 21489 | /* 59015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16), |
| 21490 | /* 59018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21491 | /* 59020 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21492 | /* 59022 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21493 | /* 59024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21494 | /* 59027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21495 | /* 59033 */ GIR_RootConstrainSelectedInstOperands, |
| 21496 | /* 59034 */ // GIR_Coverage, 1416, |
| 21497 | /* 59034 */ GIR_EraseRootFromParent_Done, |
| 21498 | /* 59035 */ // Label 1284: @59035 |
| 21499 | /* 59035 */ GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(59089), // Rule ID 1417 // |
| 21500 | /* 59040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21501 | /* 59043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 21502 | /* 59048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 21503 | /* 59051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21504 | /* 59054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21505 | /* 59057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21506 | /* 59061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21507 | /* 59065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21508 | /* 59069 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4052:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 21509 | /* 59069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32), |
| 21510 | /* 59072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21511 | /* 59074 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21512 | /* 59076 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21513 | /* 59078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21514 | /* 59081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21515 | /* 59087 */ GIR_RootConstrainSelectedInstOperands, |
| 21516 | /* 59088 */ // GIR_Coverage, 1417, |
| 21517 | /* 59088 */ GIR_EraseRootFromParent_Done, |
| 21518 | /* 59089 */ // Label 1285: @59089 |
| 21519 | /* 59089 */ GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(59143), // Rule ID 1418 // |
| 21520 | /* 59094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21521 | /* 59097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 21522 | /* 59102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21523 | /* 59105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21524 | /* 59108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21525 | /* 59111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21526 | /* 59115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21527 | /* 59119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21528 | /* 59123 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4052:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 21529 | /* 59123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8), |
| 21530 | /* 59126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21531 | /* 59128 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21532 | /* 59130 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21533 | /* 59132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21534 | /* 59135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21535 | /* 59141 */ GIR_RootConstrainSelectedInstOperands, |
| 21536 | /* 59142 */ // GIR_Coverage, 1418, |
| 21537 | /* 59142 */ GIR_EraseRootFromParent_Done, |
| 21538 | /* 59143 */ // Label 1286: @59143 |
| 21539 | /* 59143 */ GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(59197), // Rule ID 1419 // |
| 21540 | /* 59148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21541 | /* 59151 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 21542 | /* 59156 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21543 | /* 59159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21544 | /* 59162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21545 | /* 59165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21546 | /* 59169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21547 | /* 59173 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21548 | /* 59177 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4052:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 21549 | /* 59177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16), |
| 21550 | /* 59180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21551 | /* 59182 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21552 | /* 59184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21553 | /* 59186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21554 | /* 59189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21555 | /* 59195 */ GIR_RootConstrainSelectedInstOperands, |
| 21556 | /* 59196 */ // GIR_Coverage, 1419, |
| 21557 | /* 59196 */ GIR_EraseRootFromParent_Done, |
| 21558 | /* 59197 */ // Label 1287: @59197 |
| 21559 | /* 59197 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(59251), // Rule ID 1420 // |
| 21560 | /* 59202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21561 | /* 59205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 21562 | /* 59210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 21563 | /* 59213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21564 | /* 59216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21565 | /* 59219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21566 | /* 59223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21567 | /* 59227 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21568 | /* 59231 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4052:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 21569 | /* 59231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32), |
| 21570 | /* 59234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21571 | /* 59236 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21572 | /* 59238 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21573 | /* 59240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21574 | /* 59243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21575 | /* 59249 */ GIR_RootConstrainSelectedInstOperands, |
| 21576 | /* 59250 */ // GIR_Coverage, 1420, |
| 21577 | /* 59250 */ GIR_EraseRootFromParent_Done, |
| 21578 | /* 59251 */ // Label 1288: @59251 |
| 21579 | /* 59251 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(59305), // Rule ID 1421 // |
| 21580 | /* 59256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21581 | /* 59259 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 21582 | /* 59264 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21583 | /* 59267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21584 | /* 59270 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21585 | /* 59273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21586 | /* 59277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21587 | /* 59281 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21588 | /* 59285 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4053:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 21589 | /* 59285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8), |
| 21590 | /* 59288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21591 | /* 59290 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21592 | /* 59292 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21593 | /* 59294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21594 | /* 59297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21595 | /* 59303 */ GIR_RootConstrainSelectedInstOperands, |
| 21596 | /* 59304 */ // GIR_Coverage, 1421, |
| 21597 | /* 59304 */ GIR_EraseRootFromParent_Done, |
| 21598 | /* 59305 */ // Label 1289: @59305 |
| 21599 | /* 59305 */ GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(59359), // Rule ID 1422 // |
| 21600 | /* 59310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21601 | /* 59313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 21602 | /* 59318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21603 | /* 59321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21604 | /* 59324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21605 | /* 59327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21606 | /* 59331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21607 | /* 59335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21608 | /* 59339 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4053:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 21609 | /* 59339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16), |
| 21610 | /* 59342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21611 | /* 59344 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21612 | /* 59346 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21613 | /* 59348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21614 | /* 59351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21615 | /* 59357 */ GIR_RootConstrainSelectedInstOperands, |
| 21616 | /* 59358 */ // GIR_Coverage, 1422, |
| 21617 | /* 59358 */ GIR_EraseRootFromParent_Done, |
| 21618 | /* 59359 */ // Label 1290: @59359 |
| 21619 | /* 59359 */ GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(59413), // Rule ID 1423 // |
| 21620 | /* 59364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21621 | /* 59367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 21622 | /* 59372 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 21623 | /* 59375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21624 | /* 59378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21625 | /* 59381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21626 | /* 59385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21627 | /* 59389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21628 | /* 59393 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4053:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 21629 | /* 59393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32), |
| 21630 | /* 59396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21631 | /* 59398 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21632 | /* 59400 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21633 | /* 59402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21634 | /* 59405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21635 | /* 59411 */ GIR_RootConstrainSelectedInstOperands, |
| 21636 | /* 59412 */ // GIR_Coverage, 1423, |
| 21637 | /* 59412 */ GIR_EraseRootFromParent_Done, |
| 21638 | /* 59413 */ // Label 1291: @59413 |
| 21639 | /* 59413 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(59467), // Rule ID 1424 // |
| 21640 | /* 59418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21641 | /* 59421 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 21642 | /* 59426 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21643 | /* 59429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21644 | /* 59432 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21645 | /* 59435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21646 | /* 59439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21647 | /* 59443 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21648 | /* 59447 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4053:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 21649 | /* 59447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8), |
| 21650 | /* 59450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21651 | /* 59452 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21652 | /* 59454 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21653 | /* 59456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21654 | /* 59459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21655 | /* 59465 */ GIR_RootConstrainSelectedInstOperands, |
| 21656 | /* 59466 */ // GIR_Coverage, 1424, |
| 21657 | /* 59466 */ GIR_EraseRootFromParent_Done, |
| 21658 | /* 59467 */ // Label 1292: @59467 |
| 21659 | /* 59467 */ GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(59521), // Rule ID 1425 // |
| 21660 | /* 59472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21661 | /* 59475 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 21662 | /* 59480 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21663 | /* 59483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21664 | /* 59486 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21665 | /* 59489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21666 | /* 59493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21667 | /* 59497 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21668 | /* 59501 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4053:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 21669 | /* 59501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16), |
| 21670 | /* 59504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21671 | /* 59506 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21672 | /* 59508 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21673 | /* 59510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21674 | /* 59513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21675 | /* 59519 */ GIR_RootConstrainSelectedInstOperands, |
| 21676 | /* 59520 */ // GIR_Coverage, 1425, |
| 21677 | /* 59520 */ GIR_EraseRootFromParent_Done, |
| 21678 | /* 59521 */ // Label 1293: @59521 |
| 21679 | /* 59521 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(59575), // Rule ID 1426 // |
| 21680 | /* 59526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21681 | /* 59529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 21682 | /* 59534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 21683 | /* 59537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21684 | /* 59540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21685 | /* 59543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21686 | /* 59547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21687 | /* 59551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21688 | /* 59555 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4053:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 21689 | /* 59555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32), |
| 21690 | /* 59558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21691 | /* 59560 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 21692 | /* 59562 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21693 | /* 59564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21694 | /* 59567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21695 | /* 59573 */ GIR_RootConstrainSelectedInstOperands, |
| 21696 | /* 59574 */ // GIR_Coverage, 1426, |
| 21697 | /* 59574 */ GIR_EraseRootFromParent_Done, |
| 21698 | /* 59575 */ // Label 1294: @59575 |
| 21699 | /* 59575 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(59629), // Rule ID 1427 // |
| 21700 | /* 59580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21701 | /* 59583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 21702 | /* 59588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21703 | /* 59591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21704 | /* 59594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21705 | /* 59597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21706 | /* 59601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21707 | /* 59605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21708 | /* 59609 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4057:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21709 | /* 59609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8), |
| 21710 | /* 59612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21711 | /* 59614 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21712 | /* 59616 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21713 | /* 59618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21714 | /* 59621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21715 | /* 59627 */ GIR_RootConstrainSelectedInstOperands, |
| 21716 | /* 59628 */ // GIR_Coverage, 1427, |
| 21717 | /* 59628 */ GIR_EraseRootFromParent_Done, |
| 21718 | /* 59629 */ // Label 1295: @59629 |
| 21719 | /* 59629 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(59683), // Rule ID 1428 // |
| 21720 | /* 59634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21721 | /* 59637 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 21722 | /* 59642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21723 | /* 59645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21724 | /* 59648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21725 | /* 59651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21726 | /* 59655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21727 | /* 59659 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21728 | /* 59663 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21729 | /* 59663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16), |
| 21730 | /* 59666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21731 | /* 59668 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21732 | /* 59670 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21733 | /* 59672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21734 | /* 59675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21735 | /* 59681 */ GIR_RootConstrainSelectedInstOperands, |
| 21736 | /* 59682 */ // GIR_Coverage, 1428, |
| 21737 | /* 59682 */ GIR_EraseRootFromParent_Done, |
| 21738 | /* 59683 */ // Label 1296: @59683 |
| 21739 | /* 59683 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(59737), // Rule ID 1429 // |
| 21740 | /* 59688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21741 | /* 59691 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 21742 | /* 59696 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21743 | /* 59699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21744 | /* 59702 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21745 | /* 59705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21746 | /* 59709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21747 | /* 59713 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21748 | /* 59717 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21749 | /* 59717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32), |
| 21750 | /* 59720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21751 | /* 59722 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21752 | /* 59724 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21753 | /* 59726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21754 | /* 59729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21755 | /* 59735 */ GIR_RootConstrainSelectedInstOperands, |
| 21756 | /* 59736 */ // GIR_Coverage, 1429, |
| 21757 | /* 59736 */ GIR_EraseRootFromParent_Done, |
| 21758 | /* 59737 */ // Label 1297: @59737 |
| 21759 | /* 59737 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(59791), // Rule ID 1430 // |
| 21760 | /* 59742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21761 | /* 59745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 21762 | /* 59750 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21763 | /* 59753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21764 | /* 59756 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21765 | /* 59759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21766 | /* 59763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21767 | /* 59767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21768 | /* 59771 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4058:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21769 | /* 59771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8), |
| 21770 | /* 59774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21771 | /* 59776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21772 | /* 59778 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21773 | /* 59780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21774 | /* 59783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21775 | /* 59789 */ GIR_RootConstrainSelectedInstOperands, |
| 21776 | /* 59790 */ // GIR_Coverage, 1430, |
| 21777 | /* 59790 */ GIR_EraseRootFromParent_Done, |
| 21778 | /* 59791 */ // Label 1298: @59791 |
| 21779 | /* 59791 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(59845), // Rule ID 1431 // |
| 21780 | /* 59796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21781 | /* 59799 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 21782 | /* 59804 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21783 | /* 59807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21784 | /* 59810 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21785 | /* 59813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21786 | /* 59817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21787 | /* 59821 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21788 | /* 59825 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4058:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21789 | /* 59825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16), |
| 21790 | /* 59828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21791 | /* 59830 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21792 | /* 59832 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21793 | /* 59834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21794 | /* 59837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21795 | /* 59843 */ GIR_RootConstrainSelectedInstOperands, |
| 21796 | /* 59844 */ // GIR_Coverage, 1431, |
| 21797 | /* 59844 */ GIR_EraseRootFromParent_Done, |
| 21798 | /* 59845 */ // Label 1299: @59845 |
| 21799 | /* 59845 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(59899), // Rule ID 1432 // |
| 21800 | /* 59850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21801 | /* 59853 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 21802 | /* 59858 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21803 | /* 59861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21804 | /* 59864 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21805 | /* 59867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21806 | /* 59871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21807 | /* 59875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21808 | /* 59879 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4058:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21809 | /* 59879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32), |
| 21810 | /* 59882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21811 | /* 59884 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21812 | /* 59886 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21813 | /* 59888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21814 | /* 59891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21815 | /* 59897 */ GIR_RootConstrainSelectedInstOperands, |
| 21816 | /* 59898 */ // GIR_Coverage, 1432, |
| 21817 | /* 59898 */ GIR_EraseRootFromParent_Done, |
| 21818 | /* 59899 */ // Label 1300: @59899 |
| 21819 | /* 59899 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(59953), // Rule ID 1433 // |
| 21820 | /* 59904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21821 | /* 59907 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 21822 | /* 59912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21823 | /* 59915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21824 | /* 59918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21825 | /* 59921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21826 | /* 59925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21827 | /* 59929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21828 | /* 59933 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21829 | /* 59933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf), |
| 21830 | /* 59936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21831 | /* 59938 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21832 | /* 59940 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21833 | /* 59942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21834 | /* 59945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21835 | /* 59951 */ GIR_RootConstrainSelectedInstOperands, |
| 21836 | /* 59952 */ // GIR_Coverage, 1433, |
| 21837 | /* 59952 */ GIR_EraseRootFromParent_Done, |
| 21838 | /* 59953 */ // Label 1301: @59953 |
| 21839 | /* 59953 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(60007), // Rule ID 1434 // |
| 21840 | /* 59958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 21841 | /* 59961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 21842 | /* 59966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21843 | /* 59969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21844 | /* 59972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21845 | /* 59975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21846 | /* 59979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21847 | /* 59983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21848 | /* 59987 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21849 | /* 59987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh), |
| 21850 | /* 59990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21851 | /* 59992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21852 | /* 59994 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21853 | /* 59996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21854 | /* 59999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21855 | /* 60005 */ GIR_RootConstrainSelectedInstOperands, |
| 21856 | /* 60006 */ // GIR_Coverage, 1434, |
| 21857 | /* 60006 */ GIR_EraseRootFromParent_Done, |
| 21858 | /* 60007 */ // Label 1302: @60007 |
| 21859 | /* 60007 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(60061), // Rule ID 1435 // |
| 21860 | /* 60012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21861 | /* 60015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21862 | /* 60020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21863 | /* 60023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21864 | /* 60026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21865 | /* 60029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21866 | /* 60033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21867 | /* 60037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21868 | /* 60041 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4059:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21869 | /* 60041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8), |
| 21870 | /* 60044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21871 | /* 60046 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21872 | /* 60048 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21873 | /* 60050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21874 | /* 60053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21875 | /* 60059 */ GIR_RootConstrainSelectedInstOperands, |
| 21876 | /* 60060 */ // GIR_Coverage, 1435, |
| 21877 | /* 60060 */ GIR_EraseRootFromParent_Done, |
| 21878 | /* 60061 */ // Label 1303: @60061 |
| 21879 | /* 60061 */ GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(60115), // Rule ID 1436 // |
| 21880 | /* 60066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21881 | /* 60069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21882 | /* 60074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21883 | /* 60077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21884 | /* 60080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21885 | /* 60083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21886 | /* 60087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21887 | /* 60091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21888 | /* 60095 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4059:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21889 | /* 60095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16), |
| 21890 | /* 60098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21891 | /* 60100 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21892 | /* 60102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21893 | /* 60104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21894 | /* 60107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21895 | /* 60113 */ GIR_RootConstrainSelectedInstOperands, |
| 21896 | /* 60114 */ // GIR_Coverage, 1436, |
| 21897 | /* 60114 */ GIR_EraseRootFromParent_Done, |
| 21898 | /* 60115 */ // Label 1304: @60115 |
| 21899 | /* 60115 */ GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(60169), // Rule ID 1437 // |
| 21900 | /* 60120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21901 | /* 60123 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21902 | /* 60128 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21903 | /* 60131 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21904 | /* 60134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21905 | /* 60137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21906 | /* 60141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21907 | /* 60145 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21908 | /* 60149 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4059:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21909 | /* 60149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32), |
| 21910 | /* 60152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21911 | /* 60154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21912 | /* 60156 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21913 | /* 60158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21914 | /* 60161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21915 | /* 60167 */ GIR_RootConstrainSelectedInstOperands, |
| 21916 | /* 60168 */ // GIR_Coverage, 1437, |
| 21917 | /* 60168 */ GIR_EraseRootFromParent_Done, |
| 21918 | /* 60169 */ // Label 1305: @60169 |
| 21919 | /* 60169 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(60223), // Rule ID 1438 // |
| 21920 | /* 60174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21921 | /* 60177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 21922 | /* 60182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21923 | /* 60185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21924 | /* 60188 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21925 | /* 60191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21926 | /* 60195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21927 | /* 60199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21928 | /* 60203 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4060:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21929 | /* 60203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8), |
| 21930 | /* 60206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21931 | /* 60208 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21932 | /* 60210 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21933 | /* 60212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21934 | /* 60215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21935 | /* 60221 */ GIR_RootConstrainSelectedInstOperands, |
| 21936 | /* 60222 */ // GIR_Coverage, 1438, |
| 21937 | /* 60222 */ GIR_EraseRootFromParent_Done, |
| 21938 | /* 60223 */ // Label 1306: @60223 |
| 21939 | /* 60223 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(60277), // Rule ID 1439 // |
| 21940 | /* 60228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21941 | /* 60231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 21942 | /* 60236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21943 | /* 60239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21944 | /* 60242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21945 | /* 60245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21946 | /* 60249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21947 | /* 60253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21948 | /* 60257 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4060:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21949 | /* 60257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16), |
| 21950 | /* 60260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21951 | /* 60262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21952 | /* 60264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21953 | /* 60266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21954 | /* 60269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21955 | /* 60275 */ GIR_RootConstrainSelectedInstOperands, |
| 21956 | /* 60276 */ // GIR_Coverage, 1439, |
| 21957 | /* 60276 */ GIR_EraseRootFromParent_Done, |
| 21958 | /* 60277 */ // Label 1307: @60277 |
| 21959 | /* 60277 */ GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(60331), // Rule ID 1440 // |
| 21960 | /* 60282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21961 | /* 60285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 21962 | /* 60290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21963 | /* 60293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21964 | /* 60296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21965 | /* 60299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21966 | /* 60303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21967 | /* 60307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21968 | /* 60311 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4060:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21969 | /* 60311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32), |
| 21970 | /* 60314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21971 | /* 60316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21972 | /* 60318 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21973 | /* 60320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21974 | /* 60323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21975 | /* 60329 */ GIR_RootConstrainSelectedInstOperands, |
| 21976 | /* 60330 */ // GIR_Coverage, 1440, |
| 21977 | /* 60330 */ GIR_EraseRootFromParent_Done, |
| 21978 | /* 60331 */ // Label 1308: @60331 |
| 21979 | /* 60331 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(60385), // Rule ID 1441 // |
| 21980 | /* 60336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21981 | /* 60339 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21982 | /* 60344 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21983 | /* 60347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21984 | /* 60350 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21985 | /* 60353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21986 | /* 60357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21987 | /* 60361 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21988 | /* 60365 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4059:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21989 | /* 60365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf), |
| 21990 | /* 60368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21991 | /* 60370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21992 | /* 60372 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21993 | /* 60374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21994 | /* 60377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21995 | /* 60383 */ GIR_RootConstrainSelectedInstOperands, |
| 21996 | /* 60384 */ // GIR_Coverage, 1441, |
| 21997 | /* 60384 */ GIR_EraseRootFromParent_Done, |
| 21998 | /* 60385 */ // Label 1309: @60385 |
| 21999 | /* 60385 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(60439), // Rule ID 1442 // |
| 22000 | /* 60390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 22001 | /* 60393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 22002 | /* 60398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22003 | /* 60401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22004 | /* 60404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22005 | /* 60407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22006 | /* 60411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22007 | /* 60415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22008 | /* 60419 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4059:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 22009 | /* 60419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh), |
| 22010 | /* 60422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22011 | /* 60424 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22012 | /* 60426 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22013 | /* 60428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22014 | /* 60431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22015 | /* 60437 */ GIR_RootConstrainSelectedInstOperands, |
| 22016 | /* 60438 */ // GIR_Coverage, 1442, |
| 22017 | /* 60438 */ GIR_EraseRootFromParent_Done, |
| 22018 | /* 60439 */ // Label 1310: @60439 |
| 22019 | /* 60439 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(60493), // Rule ID 1449 // |
| 22020 | /* 60444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22021 | /* 60447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 22022 | /* 60452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22023 | /* 60455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22024 | /* 60458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22025 | /* 60461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22026 | /* 60465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22027 | /* 60469 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22028 | /* 60473 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4084:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 22029 | /* 60473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd), |
| 22030 | /* 60476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22031 | /* 60478 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22032 | /* 60480 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22033 | /* 60482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22034 | /* 60485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22035 | /* 60491 */ GIR_RootConstrainSelectedInstOperands, |
| 22036 | /* 60492 */ // GIR_Coverage, 1449, |
| 22037 | /* 60492 */ GIR_EraseRootFromParent_Done, |
| 22038 | /* 60493 */ // Label 1311: @60493 |
| 22039 | /* 60493 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(60547), // Rule ID 1450 // |
| 22040 | /* 60498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22041 | /* 60501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 22042 | /* 60506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22043 | /* 60509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22044 | /* 60512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22045 | /* 60515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22046 | /* 60519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22047 | /* 60523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22048 | /* 60527 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4084:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 22049 | /* 60527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq), |
| 22050 | /* 60530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22051 | /* 60532 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22052 | /* 60534 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22053 | /* 60536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22054 | /* 60539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22055 | /* 60545 */ GIR_RootConstrainSelectedInstOperands, |
| 22056 | /* 60546 */ // GIR_Coverage, 1450, |
| 22057 | /* 60546 */ GIR_EraseRootFromParent_Done, |
| 22058 | /* 60547 */ // Label 1312: @60547 |
| 22059 | /* 60547 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(60601), // Rule ID 1451 // |
| 22060 | /* 60552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 22061 | /* 60555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 22062 | /* 60560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22063 | /* 60563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22064 | /* 60566 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22065 | /* 60569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22066 | /* 60573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22067 | /* 60577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22068 | /* 60581 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4084:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 22069 | /* 60581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd), |
| 22070 | /* 60584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22071 | /* 60586 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22072 | /* 60588 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22073 | /* 60590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22074 | /* 60593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22075 | /* 60599 */ GIR_RootConstrainSelectedInstOperands, |
| 22076 | /* 60600 */ // GIR_Coverage, 1451, |
| 22077 | /* 60600 */ GIR_EraseRootFromParent_Done, |
| 22078 | /* 60601 */ // Label 1313: @60601 |
| 22079 | /* 60601 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(60655), // Rule ID 1452 // |
| 22080 | /* 60606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 22081 | /* 60609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 22082 | /* 60614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22083 | /* 60617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22084 | /* 60620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22085 | /* 60623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22086 | /* 60627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22087 | /* 60631 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22088 | /* 60635 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4084:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 22089 | /* 60635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq), |
| 22090 | /* 60638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22091 | /* 60640 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22092 | /* 60642 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22093 | /* 60644 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22094 | /* 60647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22095 | /* 60653 */ GIR_RootConstrainSelectedInstOperands, |
| 22096 | /* 60654 */ // GIR_Coverage, 1452, |
| 22097 | /* 60654 */ GIR_EraseRootFromParent_Done, |
| 22098 | /* 60655 */ // Label 1314: @60655 |
| 22099 | /* 60655 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(60709), // Rule ID 1459 // |
| 22100 | /* 60660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22101 | /* 60663 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 22102 | /* 60668 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22103 | /* 60671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22104 | /* 60674 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22105 | /* 60677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22106 | /* 60681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22107 | /* 60685 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22108 | /* 60689 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4091:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 22109 | /* 60689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd), |
| 22110 | /* 60692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22111 | /* 60694 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22112 | /* 60696 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22113 | /* 60698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22114 | /* 60701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22115 | /* 60707 */ GIR_RootConstrainSelectedInstOperands, |
| 22116 | /* 60708 */ // GIR_Coverage, 1459, |
| 22117 | /* 60708 */ GIR_EraseRootFromParent_Done, |
| 22118 | /* 60709 */ // Label 1315: @60709 |
| 22119 | /* 60709 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(60763), // Rule ID 1460 // |
| 22120 | /* 60714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22121 | /* 60717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 22122 | /* 60722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22123 | /* 60725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22124 | /* 60728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22125 | /* 60731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22126 | /* 60735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22127 | /* 60739 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22128 | /* 60743 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4091:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 22129 | /* 60743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq), |
| 22130 | /* 60746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22131 | /* 60748 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22132 | /* 60750 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22133 | /* 60752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22134 | /* 60755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22135 | /* 60761 */ GIR_RootConstrainSelectedInstOperands, |
| 22136 | /* 60762 */ // GIR_Coverage, 1460, |
| 22137 | /* 60762 */ GIR_EraseRootFromParent_Done, |
| 22138 | /* 60763 */ // Label 1316: @60763 |
| 22139 | /* 60763 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(60817), // Rule ID 1461 // |
| 22140 | /* 60768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 22141 | /* 60771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 22142 | /* 60776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22143 | /* 60779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22144 | /* 60782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22145 | /* 60785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22146 | /* 60789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22147 | /* 60793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22148 | /* 60797 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4091:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 22149 | /* 60797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd), |
| 22150 | /* 60800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22151 | /* 60802 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22152 | /* 60804 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22153 | /* 60806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22154 | /* 60809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22155 | /* 60815 */ GIR_RootConstrainSelectedInstOperands, |
| 22156 | /* 60816 */ // GIR_Coverage, 1461, |
| 22157 | /* 60816 */ GIR_EraseRootFromParent_Done, |
| 22158 | /* 60817 */ // Label 1317: @60817 |
| 22159 | /* 60817 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(60871), // Rule ID 1462 // |
| 22160 | /* 60822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 22161 | /* 60825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 22162 | /* 60830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22163 | /* 60833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22164 | /* 60836 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22165 | /* 60839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22166 | /* 60843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22167 | /* 60847 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22168 | /* 60851 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4091:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 22169 | /* 60851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq), |
| 22170 | /* 60854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22171 | /* 60856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 22172 | /* 60858 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22173 | /* 60860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22174 | /* 60863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22175 | /* 60869 */ GIR_RootConstrainSelectedInstOperands, |
| 22176 | /* 60870 */ // GIR_Coverage, 1462, |
| 22177 | /* 60870 */ GIR_EraseRootFromParent_Done, |
| 22178 | /* 60871 */ // Label 1318: @60871 |
| 22179 | /* 60871 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(60925), // Rule ID 1463 // |
| 22180 | /* 60876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22181 | /* 60879 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22182 | /* 60884 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22183 | /* 60887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22184 | /* 60890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22185 | /* 60893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22186 | /* 60897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22187 | /* 60901 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22188 | /* 60905 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4094:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22189 | /* 60905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16), |
| 22190 | /* 60908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22191 | /* 60910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22192 | /* 60912 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22193 | /* 60914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22194 | /* 60917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22195 | /* 60923 */ GIR_RootConstrainSelectedInstOperands, |
| 22196 | /* 60924 */ // GIR_Coverage, 1463, |
| 22197 | /* 60924 */ GIR_EraseRootFromParent_Done, |
| 22198 | /* 60925 */ // Label 1319: @60925 |
| 22199 | /* 60925 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(60979), // Rule ID 1464 // |
| 22200 | /* 60930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22201 | /* 60933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22202 | /* 60938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22203 | /* 60941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22204 | /* 60944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22205 | /* 60947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22206 | /* 60951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22207 | /* 60955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22208 | /* 60959 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4094:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22209 | /* 60959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32), |
| 22210 | /* 60962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22211 | /* 60964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22212 | /* 60966 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22213 | /* 60968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22214 | /* 60971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22215 | /* 60977 */ GIR_RootConstrainSelectedInstOperands, |
| 22216 | /* 60978 */ // GIR_Coverage, 1464, |
| 22217 | /* 60978 */ GIR_EraseRootFromParent_Done, |
| 22218 | /* 60979 */ // Label 1320: @60979 |
| 22219 | /* 60979 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(61033), // Rule ID 1465 // |
| 22220 | /* 60984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22221 | /* 60987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22222 | /* 60992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22223 | /* 60995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22224 | /* 60998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22225 | /* 61001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22226 | /* 61005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22227 | /* 61009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22228 | /* 61013 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4094:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22229 | /* 61013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16), |
| 22230 | /* 61016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22231 | /* 61018 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22232 | /* 61020 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22233 | /* 61022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22234 | /* 61025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22235 | /* 61031 */ GIR_RootConstrainSelectedInstOperands, |
| 22236 | /* 61032 */ // GIR_Coverage, 1465, |
| 22237 | /* 61032 */ GIR_EraseRootFromParent_Done, |
| 22238 | /* 61033 */ // Label 1321: @61033 |
| 22239 | /* 61033 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(61087), // Rule ID 1466 // |
| 22240 | /* 61038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22241 | /* 61041 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22242 | /* 61046 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22243 | /* 61049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22244 | /* 61052 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22245 | /* 61055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22246 | /* 61059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22247 | /* 61063 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22248 | /* 61067 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4094:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22249 | /* 61067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32), |
| 22250 | /* 61070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22251 | /* 61072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22252 | /* 61074 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22253 | /* 61076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22254 | /* 61079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22255 | /* 61085 */ GIR_RootConstrainSelectedInstOperands, |
| 22256 | /* 61086 */ // GIR_Coverage, 1466, |
| 22257 | /* 61086 */ GIR_EraseRootFromParent_Done, |
| 22258 | /* 61087 */ // Label 1322: @61087 |
| 22259 | /* 61087 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(61141), // Rule ID 1467 // |
| 22260 | /* 61092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22261 | /* 61095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22262 | /* 61100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 22263 | /* 61103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22264 | /* 61106 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22265 | /* 61109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22266 | /* 61113 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22267 | /* 61117 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22268 | /* 61121 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4094:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22269 | /* 61121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8), |
| 22270 | /* 61124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22271 | /* 61126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22272 | /* 61128 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22273 | /* 61130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22274 | /* 61133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22275 | /* 61139 */ GIR_RootConstrainSelectedInstOperands, |
| 22276 | /* 61140 */ // GIR_Coverage, 1467, |
| 22277 | /* 61140 */ GIR_EraseRootFromParent_Done, |
| 22278 | /* 61141 */ // Label 1323: @61141 |
| 22279 | /* 61141 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(61195), // Rule ID 1468 // |
| 22280 | /* 61146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22281 | /* 61149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22282 | /* 61154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22283 | /* 61157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22284 | /* 61160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22285 | /* 61163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22286 | /* 61167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22287 | /* 61171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22288 | /* 61175 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4094:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22289 | /* 61175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8), |
| 22290 | /* 61178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22291 | /* 61180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22292 | /* 61182 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22293 | /* 61184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22294 | /* 61187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22295 | /* 61193 */ GIR_RootConstrainSelectedInstOperands, |
| 22296 | /* 61194 */ // GIR_Coverage, 1468, |
| 22297 | /* 61194 */ GIR_EraseRootFromParent_Done, |
| 22298 | /* 61195 */ // Label 1324: @61195 |
| 22299 | /* 61195 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(61249), // Rule ID 1469 // |
| 22300 | /* 61200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22301 | /* 61203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22302 | /* 61208 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 22303 | /* 61211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22304 | /* 61214 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22305 | /* 61217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22306 | /* 61221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22307 | /* 61225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22308 | /* 61229 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4094:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22309 | /* 61229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64), |
| 22310 | /* 61232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22311 | /* 61234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22312 | /* 61236 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22313 | /* 61238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22314 | /* 61241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22315 | /* 61247 */ GIR_RootConstrainSelectedInstOperands, |
| 22316 | /* 61248 */ // GIR_Coverage, 1469, |
| 22317 | /* 61248 */ GIR_EraseRootFromParent_Done, |
| 22318 | /* 61249 */ // Label 1325: @61249 |
| 22319 | /* 61249 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(61303), // Rule ID 1470 // |
| 22320 | /* 61254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22321 | /* 61257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 22322 | /* 61262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 22323 | /* 61265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22324 | /* 61268 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22325 | /* 61271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22326 | /* 61275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22327 | /* 61279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22328 | /* 61283 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4094:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22329 | /* 61283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64), |
| 22330 | /* 61286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22331 | /* 61288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22332 | /* 61290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22333 | /* 61292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22334 | /* 61295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22335 | /* 61301 */ GIR_RootConstrainSelectedInstOperands, |
| 22336 | /* 61302 */ // GIR_Coverage, 1470, |
| 22337 | /* 61302 */ GIR_EraseRootFromParent_Done, |
| 22338 | /* 61303 */ // Label 1326: @61303 |
| 22339 | /* 61303 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(61357), // Rule ID 1471 // |
| 22340 | /* 61308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22341 | /* 61311 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22342 | /* 61316 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22343 | /* 61319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22344 | /* 61322 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22345 | /* 61325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22346 | /* 61329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22347 | /* 61333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22348 | /* 61337 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4095:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22349 | /* 61337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16), |
| 22350 | /* 61340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22351 | /* 61342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22352 | /* 61344 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22353 | /* 61346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22354 | /* 61349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22355 | /* 61355 */ GIR_RootConstrainSelectedInstOperands, |
| 22356 | /* 61356 */ // GIR_Coverage, 1471, |
| 22357 | /* 61356 */ GIR_EraseRootFromParent_Done, |
| 22358 | /* 61357 */ // Label 1327: @61357 |
| 22359 | /* 61357 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(61411), // Rule ID 1472 // |
| 22360 | /* 61362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22361 | /* 61365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22362 | /* 61370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22363 | /* 61373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22364 | /* 61376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22365 | /* 61379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22366 | /* 61383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22367 | /* 61387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22368 | /* 61391 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4095:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22369 | /* 61391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32), |
| 22370 | /* 61394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22371 | /* 61396 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22372 | /* 61398 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22373 | /* 61400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22374 | /* 61403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22375 | /* 61409 */ GIR_RootConstrainSelectedInstOperands, |
| 22376 | /* 61410 */ // GIR_Coverage, 1472, |
| 22377 | /* 61410 */ GIR_EraseRootFromParent_Done, |
| 22378 | /* 61411 */ // Label 1328: @61411 |
| 22379 | /* 61411 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(61465), // Rule ID 1473 // |
| 22380 | /* 61416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22381 | /* 61419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22382 | /* 61424 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22383 | /* 61427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22384 | /* 61430 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22385 | /* 61433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22386 | /* 61437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22387 | /* 61441 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22388 | /* 61445 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4095:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22389 | /* 61445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16), |
| 22390 | /* 61448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22391 | /* 61450 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22392 | /* 61452 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22393 | /* 61454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22394 | /* 61457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22395 | /* 61463 */ GIR_RootConstrainSelectedInstOperands, |
| 22396 | /* 61464 */ // GIR_Coverage, 1473, |
| 22397 | /* 61464 */ GIR_EraseRootFromParent_Done, |
| 22398 | /* 61465 */ // Label 1329: @61465 |
| 22399 | /* 61465 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(61519), // Rule ID 1474 // |
| 22400 | /* 61470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22401 | /* 61473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22402 | /* 61478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22403 | /* 61481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22404 | /* 61484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22405 | /* 61487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22406 | /* 61491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22407 | /* 61495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22408 | /* 61499 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4095:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22409 | /* 61499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32), |
| 22410 | /* 61502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22411 | /* 61504 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22412 | /* 61506 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22413 | /* 61508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22414 | /* 61511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22415 | /* 61517 */ GIR_RootConstrainSelectedInstOperands, |
| 22416 | /* 61518 */ // GIR_Coverage, 1474, |
| 22417 | /* 61518 */ GIR_EraseRootFromParent_Done, |
| 22418 | /* 61519 */ // Label 1330: @61519 |
| 22419 | /* 61519 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(61573), // Rule ID 1475 // |
| 22420 | /* 61524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22421 | /* 61527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22422 | /* 61532 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 22423 | /* 61535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22424 | /* 61538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22425 | /* 61541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22426 | /* 61545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22427 | /* 61549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22428 | /* 61553 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4095:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22429 | /* 61553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8), |
| 22430 | /* 61556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22431 | /* 61558 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22432 | /* 61560 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22433 | /* 61562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22434 | /* 61565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22435 | /* 61571 */ GIR_RootConstrainSelectedInstOperands, |
| 22436 | /* 61572 */ // GIR_Coverage, 1475, |
| 22437 | /* 61572 */ GIR_EraseRootFromParent_Done, |
| 22438 | /* 61573 */ // Label 1331: @61573 |
| 22439 | /* 61573 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(61627), // Rule ID 1476 // |
| 22440 | /* 61578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22441 | /* 61581 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22442 | /* 61586 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22443 | /* 61589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22444 | /* 61592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22445 | /* 61595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22446 | /* 61599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22447 | /* 61603 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22448 | /* 61607 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4095:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22449 | /* 61607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8), |
| 22450 | /* 61610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22451 | /* 61612 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22452 | /* 61614 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22453 | /* 61616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22454 | /* 61619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22455 | /* 61625 */ GIR_RootConstrainSelectedInstOperands, |
| 22456 | /* 61626 */ // GIR_Coverage, 1476, |
| 22457 | /* 61626 */ GIR_EraseRootFromParent_Done, |
| 22458 | /* 61627 */ // Label 1332: @61627 |
| 22459 | /* 61627 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(61681), // Rule ID 1477 // |
| 22460 | /* 61632 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22461 | /* 61635 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22462 | /* 61640 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 22463 | /* 61643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22464 | /* 61646 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22465 | /* 61649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22466 | /* 61653 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22467 | /* 61657 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22468 | /* 61661 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4095:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22469 | /* 61661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64), |
| 22470 | /* 61664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22471 | /* 61666 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22472 | /* 61668 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22473 | /* 61670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22474 | /* 61673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22475 | /* 61679 */ GIR_RootConstrainSelectedInstOperands, |
| 22476 | /* 61680 */ // GIR_Coverage, 1477, |
| 22477 | /* 61680 */ GIR_EraseRootFromParent_Done, |
| 22478 | /* 61681 */ // Label 1333: @61681 |
| 22479 | /* 61681 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(61735), // Rule ID 1478 // |
| 22480 | /* 61686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22481 | /* 61689 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 22482 | /* 61694 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 22483 | /* 61697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22484 | /* 61700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22485 | /* 61703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22486 | /* 61707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22487 | /* 61711 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22488 | /* 61715 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4095:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22489 | /* 61715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64), |
| 22490 | /* 61718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22491 | /* 61720 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22492 | /* 61722 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22493 | /* 61724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22494 | /* 61727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22495 | /* 61733 */ GIR_RootConstrainSelectedInstOperands, |
| 22496 | /* 61734 */ // GIR_Coverage, 1478, |
| 22497 | /* 61734 */ GIR_EraseRootFromParent_Done, |
| 22498 | /* 61735 */ // Label 1334: @61735 |
| 22499 | /* 61735 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(61789), // Rule ID 1512 // |
| 22500 | /* 61740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22501 | /* 61743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22502 | /* 61748 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22503 | /* 61751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22504 | /* 61754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22505 | /* 61757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22506 | /* 61761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22507 | /* 61765 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22508 | /* 61769 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4088:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22509 | /* 61769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16), |
| 22510 | /* 61772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22511 | /* 61774 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22512 | /* 61776 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22513 | /* 61778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22514 | /* 61781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22515 | /* 61787 */ GIR_RootConstrainSelectedInstOperands, |
| 22516 | /* 61788 */ // GIR_Coverage, 1512, |
| 22517 | /* 61788 */ GIR_EraseRootFromParent_Done, |
| 22518 | /* 61789 */ // Label 1335: @61789 |
| 22519 | /* 61789 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(61843), // Rule ID 1513 // |
| 22520 | /* 61794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22521 | /* 61797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22522 | /* 61802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22523 | /* 61805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22524 | /* 61808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22525 | /* 61811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22526 | /* 61815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22527 | /* 61819 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22528 | /* 61823 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4088:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22529 | /* 61823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32), |
| 22530 | /* 61826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22531 | /* 61828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22532 | /* 61830 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22533 | /* 61832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22534 | /* 61835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22535 | /* 61841 */ GIR_RootConstrainSelectedInstOperands, |
| 22536 | /* 61842 */ // GIR_Coverage, 1513, |
| 22537 | /* 61842 */ GIR_EraseRootFromParent_Done, |
| 22538 | /* 61843 */ // Label 1336: @61843 |
| 22539 | /* 61843 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(61897), // Rule ID 1514 // |
| 22540 | /* 61848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22541 | /* 61851 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22542 | /* 61856 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22543 | /* 61859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22544 | /* 61862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22545 | /* 61865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22546 | /* 61869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22547 | /* 61873 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22548 | /* 61877 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4088:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22549 | /* 61877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16), |
| 22550 | /* 61880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22551 | /* 61882 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22552 | /* 61884 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22553 | /* 61886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22554 | /* 61889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22555 | /* 61895 */ GIR_RootConstrainSelectedInstOperands, |
| 22556 | /* 61896 */ // GIR_Coverage, 1514, |
| 22557 | /* 61896 */ GIR_EraseRootFromParent_Done, |
| 22558 | /* 61897 */ // Label 1337: @61897 |
| 22559 | /* 61897 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(61951), // Rule ID 1515 // |
| 22560 | /* 61902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22561 | /* 61905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22562 | /* 61910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22563 | /* 61913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22564 | /* 61916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22565 | /* 61919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22566 | /* 61923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22567 | /* 61927 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22568 | /* 61931 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4088:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22569 | /* 61931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32), |
| 22570 | /* 61934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22571 | /* 61936 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22572 | /* 61938 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22573 | /* 61940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22574 | /* 61943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22575 | /* 61949 */ GIR_RootConstrainSelectedInstOperands, |
| 22576 | /* 61950 */ // GIR_Coverage, 1515, |
| 22577 | /* 61950 */ GIR_EraseRootFromParent_Done, |
| 22578 | /* 61951 */ // Label 1338: @61951 |
| 22579 | /* 61951 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(62005), // Rule ID 1516 // |
| 22580 | /* 61956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22581 | /* 61959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22582 | /* 61964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 22583 | /* 61967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22584 | /* 61970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22585 | /* 61973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22586 | /* 61977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22587 | /* 61981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22588 | /* 61985 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4088:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22589 | /* 61985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8), |
| 22590 | /* 61988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22591 | /* 61990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22592 | /* 61992 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22593 | /* 61994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22594 | /* 61997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22595 | /* 62003 */ GIR_RootConstrainSelectedInstOperands, |
| 22596 | /* 62004 */ // GIR_Coverage, 1516, |
| 22597 | /* 62004 */ GIR_EraseRootFromParent_Done, |
| 22598 | /* 62005 */ // Label 1339: @62005 |
| 22599 | /* 62005 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(62059), // Rule ID 1517 // |
| 22600 | /* 62010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22601 | /* 62013 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22602 | /* 62018 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22603 | /* 62021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22604 | /* 62024 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22605 | /* 62027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22606 | /* 62031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22607 | /* 62035 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22608 | /* 62039 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4088:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22609 | /* 62039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8), |
| 22610 | /* 62042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22611 | /* 62044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22612 | /* 62046 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22613 | /* 62048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22614 | /* 62051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22615 | /* 62057 */ GIR_RootConstrainSelectedInstOperands, |
| 22616 | /* 62058 */ // GIR_Coverage, 1517, |
| 22617 | /* 62058 */ GIR_EraseRootFromParent_Done, |
| 22618 | /* 62059 */ // Label 1340: @62059 |
| 22619 | /* 62059 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(62113), // Rule ID 1518 // |
| 22620 | /* 62064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22621 | /* 62067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22622 | /* 62072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 22623 | /* 62075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22624 | /* 62078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22625 | /* 62081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22626 | /* 62085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22627 | /* 62089 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22628 | /* 62093 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4088:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22629 | /* 62093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64), |
| 22630 | /* 62096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22631 | /* 62098 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22632 | /* 62100 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22633 | /* 62102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22634 | /* 62105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22635 | /* 62111 */ GIR_RootConstrainSelectedInstOperands, |
| 22636 | /* 62112 */ // GIR_Coverage, 1518, |
| 22637 | /* 62112 */ GIR_EraseRootFromParent_Done, |
| 22638 | /* 62113 */ // Label 1341: @62113 |
| 22639 | /* 62113 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(62167), // Rule ID 1519 // |
| 22640 | /* 62118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22641 | /* 62121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 22642 | /* 62126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 22643 | /* 62129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22644 | /* 62132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22645 | /* 62135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22646 | /* 62139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22647 | /* 62143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22648 | /* 62147 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4088:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22649 | /* 62147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64), |
| 22650 | /* 62150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22651 | /* 62152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22652 | /* 62154 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22653 | /* 62156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22654 | /* 62159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22655 | /* 62165 */ GIR_RootConstrainSelectedInstOperands, |
| 22656 | /* 62166 */ // GIR_Coverage, 1519, |
| 22657 | /* 62166 */ GIR_EraseRootFromParent_Done, |
| 22658 | /* 62167 */ // Label 1342: @62167 |
| 22659 | /* 62167 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(62221), // Rule ID 1520 // |
| 22660 | /* 62172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22661 | /* 62175 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22662 | /* 62180 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22663 | /* 62183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22664 | /* 62186 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22665 | /* 62189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22666 | /* 62193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22667 | /* 62197 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22668 | /* 62201 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4089:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22669 | /* 62201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16), |
| 22670 | /* 62204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22671 | /* 62206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22672 | /* 62208 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22673 | /* 62210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22674 | /* 62213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22675 | /* 62219 */ GIR_RootConstrainSelectedInstOperands, |
| 22676 | /* 62220 */ // GIR_Coverage, 1520, |
| 22677 | /* 62220 */ GIR_EraseRootFromParent_Done, |
| 22678 | /* 62221 */ // Label 1343: @62221 |
| 22679 | /* 62221 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(62275), // Rule ID 1521 // |
| 22680 | /* 62226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22681 | /* 62229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22682 | /* 62234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22683 | /* 62237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22684 | /* 62240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22685 | /* 62243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22686 | /* 62247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22687 | /* 62251 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22688 | /* 62255 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4089:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22689 | /* 62255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32), |
| 22690 | /* 62258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22691 | /* 62260 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22692 | /* 62262 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22693 | /* 62264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22694 | /* 62267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22695 | /* 62273 */ GIR_RootConstrainSelectedInstOperands, |
| 22696 | /* 62274 */ // GIR_Coverage, 1521, |
| 22697 | /* 62274 */ GIR_EraseRootFromParent_Done, |
| 22698 | /* 62275 */ // Label 1344: @62275 |
| 22699 | /* 62275 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(62329), // Rule ID 1522 // |
| 22700 | /* 62280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22701 | /* 62283 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22702 | /* 62288 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22703 | /* 62291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22704 | /* 62294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22705 | /* 62297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22706 | /* 62301 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22707 | /* 62305 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22708 | /* 62309 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4089:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22709 | /* 62309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16), |
| 22710 | /* 62312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22711 | /* 62314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22712 | /* 62316 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22713 | /* 62318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22714 | /* 62321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22715 | /* 62327 */ GIR_RootConstrainSelectedInstOperands, |
| 22716 | /* 62328 */ // GIR_Coverage, 1522, |
| 22717 | /* 62328 */ GIR_EraseRootFromParent_Done, |
| 22718 | /* 62329 */ // Label 1345: @62329 |
| 22719 | /* 62329 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(62383), // Rule ID 1523 // |
| 22720 | /* 62334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22721 | /* 62337 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22722 | /* 62342 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22723 | /* 62345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22724 | /* 62348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22725 | /* 62351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22726 | /* 62355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22727 | /* 62359 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22728 | /* 62363 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4089:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22729 | /* 62363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32), |
| 22730 | /* 62366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22731 | /* 62368 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22732 | /* 62370 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22733 | /* 62372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22734 | /* 62375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22735 | /* 62381 */ GIR_RootConstrainSelectedInstOperands, |
| 22736 | /* 62382 */ // GIR_Coverage, 1523, |
| 22737 | /* 62382 */ GIR_EraseRootFromParent_Done, |
| 22738 | /* 62383 */ // Label 1346: @62383 |
| 22739 | /* 62383 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(62437), // Rule ID 1524 // |
| 22740 | /* 62388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22741 | /* 62391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22742 | /* 62396 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 22743 | /* 62399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22744 | /* 62402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22745 | /* 62405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22746 | /* 62409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22747 | /* 62413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22748 | /* 62417 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4089:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22749 | /* 62417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8), |
| 22750 | /* 62420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22751 | /* 62422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22752 | /* 62424 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22753 | /* 62426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22754 | /* 62429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22755 | /* 62435 */ GIR_RootConstrainSelectedInstOperands, |
| 22756 | /* 62436 */ // GIR_Coverage, 1524, |
| 22757 | /* 62436 */ GIR_EraseRootFromParent_Done, |
| 22758 | /* 62437 */ // Label 1347: @62437 |
| 22759 | /* 62437 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(62491), // Rule ID 1525 // |
| 22760 | /* 62442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22761 | /* 62445 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22762 | /* 62450 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22763 | /* 62453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22764 | /* 62456 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22765 | /* 62459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22766 | /* 62463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22767 | /* 62467 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22768 | /* 62471 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4089:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22769 | /* 62471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8), |
| 22770 | /* 62474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22771 | /* 62476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22772 | /* 62478 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22773 | /* 62480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22774 | /* 62483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22775 | /* 62489 */ GIR_RootConstrainSelectedInstOperands, |
| 22776 | /* 62490 */ // GIR_Coverage, 1525, |
| 22777 | /* 62490 */ GIR_EraseRootFromParent_Done, |
| 22778 | /* 62491 */ // Label 1348: @62491 |
| 22779 | /* 62491 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(62545), // Rule ID 1526 // |
| 22780 | /* 62496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22781 | /* 62499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22782 | /* 62504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 22783 | /* 62507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22784 | /* 62510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22785 | /* 62513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22786 | /* 62517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22787 | /* 62521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22788 | /* 62525 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4089:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22789 | /* 62525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64), |
| 22790 | /* 62528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22791 | /* 62530 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22792 | /* 62532 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22793 | /* 62534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22794 | /* 62537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22795 | /* 62543 */ GIR_RootConstrainSelectedInstOperands, |
| 22796 | /* 62544 */ // GIR_Coverage, 1526, |
| 22797 | /* 62544 */ GIR_EraseRootFromParent_Done, |
| 22798 | /* 62545 */ // Label 1349: @62545 |
| 22799 | /* 62545 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(62599), // Rule ID 1527 // |
| 22800 | /* 62550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22801 | /* 62553 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 22802 | /* 62558 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 22803 | /* 62561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22804 | /* 62564 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22805 | /* 62567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22806 | /* 62571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22807 | /* 62575 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22808 | /* 62579 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4089:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22809 | /* 62579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64), |
| 22810 | /* 62582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22811 | /* 62584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22812 | /* 62586 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22813 | /* 62588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22814 | /* 62591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22815 | /* 62597 */ GIR_RootConstrainSelectedInstOperands, |
| 22816 | /* 62598 */ // GIR_Coverage, 1527, |
| 22817 | /* 62598 */ GIR_EraseRootFromParent_Done, |
| 22818 | /* 62599 */ // Label 1350: @62599 |
| 22819 | /* 62599 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(62653), // Rule ID 1547 // |
| 22820 | /* 62604 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22821 | /* 62607 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22822 | /* 62612 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22823 | /* 62615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22824 | /* 62618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22825 | /* 62621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22826 | /* 62625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22827 | /* 62629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22828 | /* 62633 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4079:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22829 | /* 62633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16), |
| 22830 | /* 62636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22831 | /* 62638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22832 | /* 62640 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22833 | /* 62642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22834 | /* 62645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22835 | /* 62651 */ GIR_RootConstrainSelectedInstOperands, |
| 22836 | /* 62652 */ // GIR_Coverage, 1547, |
| 22837 | /* 62652 */ GIR_EraseRootFromParent_Done, |
| 22838 | /* 62653 */ // Label 1351: @62653 |
| 22839 | /* 62653 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(62707), // Rule ID 1548 // |
| 22840 | /* 62658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22841 | /* 62661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22842 | /* 62666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22843 | /* 62669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22844 | /* 62672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22845 | /* 62675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22846 | /* 62679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22847 | /* 62683 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22848 | /* 62687 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4079:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22849 | /* 62687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32), |
| 22850 | /* 62690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22851 | /* 62692 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22852 | /* 62694 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22853 | /* 62696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22854 | /* 62699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22855 | /* 62705 */ GIR_RootConstrainSelectedInstOperands, |
| 22856 | /* 62706 */ // GIR_Coverage, 1548, |
| 22857 | /* 62706 */ GIR_EraseRootFromParent_Done, |
| 22858 | /* 62707 */ // Label 1352: @62707 |
| 22859 | /* 62707 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(62761), // Rule ID 1549 // |
| 22860 | /* 62712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22861 | /* 62715 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22862 | /* 62720 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22863 | /* 62723 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22864 | /* 62726 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22865 | /* 62729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22866 | /* 62733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22867 | /* 62737 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22868 | /* 62741 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4079:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22869 | /* 62741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16), |
| 22870 | /* 62744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22871 | /* 62746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22872 | /* 62748 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22873 | /* 62750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22874 | /* 62753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22875 | /* 62759 */ GIR_RootConstrainSelectedInstOperands, |
| 22876 | /* 62760 */ // GIR_Coverage, 1549, |
| 22877 | /* 62760 */ GIR_EraseRootFromParent_Done, |
| 22878 | /* 62761 */ // Label 1353: @62761 |
| 22879 | /* 62761 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(62815), // Rule ID 1550 // |
| 22880 | /* 62766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22881 | /* 62769 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22882 | /* 62774 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22883 | /* 62777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22884 | /* 62780 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22885 | /* 62783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22886 | /* 62787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22887 | /* 62791 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22888 | /* 62795 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4079:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22889 | /* 62795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32), |
| 22890 | /* 62798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22891 | /* 62800 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22892 | /* 62802 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22893 | /* 62804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22894 | /* 62807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22895 | /* 62813 */ GIR_RootConstrainSelectedInstOperands, |
| 22896 | /* 62814 */ // GIR_Coverage, 1550, |
| 22897 | /* 62814 */ GIR_EraseRootFromParent_Done, |
| 22898 | /* 62815 */ // Label 1354: @62815 |
| 22899 | /* 62815 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(62869), // Rule ID 1551 // |
| 22900 | /* 62820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22901 | /* 62823 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22902 | /* 62828 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 22903 | /* 62831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22904 | /* 62834 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22905 | /* 62837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22906 | /* 62841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22907 | /* 62845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22908 | /* 62849 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4079:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22909 | /* 62849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8), |
| 22910 | /* 62852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22911 | /* 62854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22912 | /* 62856 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22913 | /* 62858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22914 | /* 62861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22915 | /* 62867 */ GIR_RootConstrainSelectedInstOperands, |
| 22916 | /* 62868 */ // GIR_Coverage, 1551, |
| 22917 | /* 62868 */ GIR_EraseRootFromParent_Done, |
| 22918 | /* 62869 */ // Label 1355: @62869 |
| 22919 | /* 62869 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(62923), // Rule ID 1552 // |
| 22920 | /* 62874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22921 | /* 62877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22922 | /* 62882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22923 | /* 62885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22924 | /* 62888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22925 | /* 62891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22926 | /* 62895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22927 | /* 62899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22928 | /* 62903 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4079:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22929 | /* 62903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8), |
| 22930 | /* 62906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22931 | /* 62908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22932 | /* 62910 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22933 | /* 62912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22934 | /* 62915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22935 | /* 62921 */ GIR_RootConstrainSelectedInstOperands, |
| 22936 | /* 62922 */ // GIR_Coverage, 1552, |
| 22937 | /* 62922 */ GIR_EraseRootFromParent_Done, |
| 22938 | /* 62923 */ // Label 1356: @62923 |
| 22939 | /* 62923 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(62977), // Rule ID 1553 // |
| 22940 | /* 62928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22941 | /* 62931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22942 | /* 62936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 22943 | /* 62939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22944 | /* 62942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22945 | /* 62945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22946 | /* 62949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22947 | /* 62953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22948 | /* 62957 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4079:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22949 | /* 62957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64), |
| 22950 | /* 62960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22951 | /* 62962 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22952 | /* 62964 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22953 | /* 62966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22954 | /* 62969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22955 | /* 62975 */ GIR_RootConstrainSelectedInstOperands, |
| 22956 | /* 62976 */ // GIR_Coverage, 1553, |
| 22957 | /* 62976 */ GIR_EraseRootFromParent_Done, |
| 22958 | /* 62977 */ // Label 1357: @62977 |
| 22959 | /* 62977 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(63031), // Rule ID 1554 // |
| 22960 | /* 62982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22961 | /* 62985 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22962 | /* 62990 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 22963 | /* 62993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22964 | /* 62996 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22965 | /* 62999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22966 | /* 63003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22967 | /* 63007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22968 | /* 63011 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4079:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22969 | /* 63011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64), |
| 22970 | /* 63014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22971 | /* 63016 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22972 | /* 63018 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22973 | /* 63020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22974 | /* 63023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22975 | /* 63029 */ GIR_RootConstrainSelectedInstOperands, |
| 22976 | /* 63030 */ // GIR_Coverage, 1554, |
| 22977 | /* 63030 */ GIR_EraseRootFromParent_Done, |
| 22978 | /* 63031 */ // Label 1358: @63031 |
| 22979 | /* 63031 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(63085), // Rule ID 1555 // |
| 22980 | /* 63036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 22981 | /* 63039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 22982 | /* 63044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22983 | /* 63047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22984 | /* 63050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22985 | /* 63053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22986 | /* 63057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22987 | /* 63061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22988 | /* 63065 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4081:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22989 | /* 63065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16), |
| 22990 | /* 63068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22991 | /* 63070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22992 | /* 63072 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22993 | /* 63074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22994 | /* 63077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22995 | /* 63083 */ GIR_RootConstrainSelectedInstOperands, |
| 22996 | /* 63084 */ // GIR_Coverage, 1555, |
| 22997 | /* 63084 */ GIR_EraseRootFromParent_Done, |
| 22998 | /* 63085 */ // Label 1359: @63085 |
| 22999 | /* 63085 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(63139), // Rule ID 1556 // |
| 23000 | /* 63090 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23001 | /* 63093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 23002 | /* 63098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 23003 | /* 63101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 23004 | /* 63104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 23005 | /* 63107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23006 | /* 63111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23007 | /* 63115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23008 | /* 63119 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4081:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 23009 | /* 63119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32), |
| 23010 | /* 63122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23011 | /* 63124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23012 | /* 63126 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23013 | /* 63128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23014 | /* 63131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23015 | /* 63137 */ GIR_RootConstrainSelectedInstOperands, |
| 23016 | /* 63138 */ // GIR_Coverage, 1556, |
| 23017 | /* 63138 */ GIR_EraseRootFromParent_Done, |
| 23018 | /* 63139 */ // Label 1360: @63139 |
| 23019 | /* 63139 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(63193), // Rule ID 1557 // |
| 23020 | /* 63144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23021 | /* 63147 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 23022 | /* 63152 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23023 | /* 63155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23024 | /* 63158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23025 | /* 63161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23026 | /* 63165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23027 | /* 63169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23028 | /* 63173 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4081:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 23029 | /* 63173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16), |
| 23030 | /* 63176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23031 | /* 63178 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23032 | /* 63180 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23033 | /* 63182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23034 | /* 63185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23035 | /* 63191 */ GIR_RootConstrainSelectedInstOperands, |
| 23036 | /* 63192 */ // GIR_Coverage, 1557, |
| 23037 | /* 63192 */ GIR_EraseRootFromParent_Done, |
| 23038 | /* 63193 */ // Label 1361: @63193 |
| 23039 | /* 63193 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(63247), // Rule ID 1558 // |
| 23040 | /* 63198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23041 | /* 63201 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 23042 | /* 63206 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23043 | /* 63209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23044 | /* 63212 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23045 | /* 63215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23046 | /* 63219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23047 | /* 63223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23048 | /* 63227 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4081:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 23049 | /* 63227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32), |
| 23050 | /* 63230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23051 | /* 63232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23052 | /* 63234 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23053 | /* 63236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23054 | /* 63239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23055 | /* 63245 */ GIR_RootConstrainSelectedInstOperands, |
| 23056 | /* 63246 */ // GIR_Coverage, 1558, |
| 23057 | /* 63246 */ GIR_EraseRootFromParent_Done, |
| 23058 | /* 63247 */ // Label 1362: @63247 |
| 23059 | /* 63247 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(63301), // Rule ID 1559 // |
| 23060 | /* 63252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23061 | /* 63255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 23062 | /* 63260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 23063 | /* 63263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 23064 | /* 63266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 23065 | /* 63269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23066 | /* 63273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23067 | /* 63277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23068 | /* 63281 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4081:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 23069 | /* 63281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8), |
| 23070 | /* 63284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23071 | /* 63286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23072 | /* 63288 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23073 | /* 63290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23074 | /* 63293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23075 | /* 63299 */ GIR_RootConstrainSelectedInstOperands, |
| 23076 | /* 63300 */ // GIR_Coverage, 1559, |
| 23077 | /* 63300 */ GIR_EraseRootFromParent_Done, |
| 23078 | /* 63301 */ // Label 1363: @63301 |
| 23079 | /* 63301 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(63355), // Rule ID 1560 // |
| 23080 | /* 63306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23081 | /* 63309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 23082 | /* 63314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23083 | /* 63317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23084 | /* 63320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23085 | /* 63323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23086 | /* 63327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23087 | /* 63331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23088 | /* 63335 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4081:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 23089 | /* 63335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8), |
| 23090 | /* 63338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23091 | /* 63340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23092 | /* 63342 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23093 | /* 63344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23094 | /* 63347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23095 | /* 63353 */ GIR_RootConstrainSelectedInstOperands, |
| 23096 | /* 63354 */ // GIR_Coverage, 1560, |
| 23097 | /* 63354 */ GIR_EraseRootFromParent_Done, |
| 23098 | /* 63355 */ // Label 1364: @63355 |
| 23099 | /* 63355 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(63409), // Rule ID 1561 // |
| 23100 | /* 63360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23101 | /* 63363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 23102 | /* 63368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 23103 | /* 63371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 23104 | /* 63374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 23105 | /* 63377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23106 | /* 63381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23107 | /* 63385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23108 | /* 63389 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4081:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 23109 | /* 63389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64), |
| 23110 | /* 63392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23111 | /* 63394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23112 | /* 63396 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23113 | /* 63398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23114 | /* 63401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23115 | /* 63407 */ GIR_RootConstrainSelectedInstOperands, |
| 23116 | /* 63408 */ // GIR_Coverage, 1561, |
| 23117 | /* 63408 */ GIR_EraseRootFromParent_Done, |
| 23118 | /* 63409 */ // Label 1365: @63409 |
| 23119 | /* 63409 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(63463), // Rule ID 1562 // |
| 23120 | /* 63414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23121 | /* 63417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 23122 | /* 63422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 23123 | /* 63425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 23124 | /* 63428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 23125 | /* 63431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23126 | /* 63435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23127 | /* 63439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23128 | /* 63443 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4081:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 23129 | /* 63443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64), |
| 23130 | /* 63446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23131 | /* 63448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23132 | /* 63450 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23133 | /* 63452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23134 | /* 63455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23135 | /* 63461 */ GIR_RootConstrainSelectedInstOperands, |
| 23136 | /* 63462 */ // GIR_Coverage, 1562, |
| 23137 | /* 63462 */ GIR_EraseRootFromParent_Done, |
| 23138 | /* 63463 */ // Label 1366: @63463 |
| 23139 | /* 63463 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(63517), // Rule ID 1596 // |
| 23140 | /* 63468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23141 | /* 63471 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23142 | /* 63476 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 23143 | /* 63479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 23144 | /* 63482 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 23145 | /* 63485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23146 | /* 63489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23147 | /* 63493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23148 | /* 63497 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4074:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 23149 | /* 63497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16), |
| 23150 | /* 63500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23151 | /* 63502 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23152 | /* 63504 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23153 | /* 63506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23154 | /* 63509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23155 | /* 63515 */ GIR_RootConstrainSelectedInstOperands, |
| 23156 | /* 63516 */ // GIR_Coverage, 1596, |
| 23157 | /* 63516 */ GIR_EraseRootFromParent_Done, |
| 23158 | /* 63517 */ // Label 1367: @63517 |
| 23159 | /* 63517 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(63571), // Rule ID 1597 // |
| 23160 | /* 63522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23161 | /* 63525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23162 | /* 63530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 23163 | /* 63533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 23164 | /* 63536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 23165 | /* 63539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23166 | /* 63543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23167 | /* 63547 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23168 | /* 63551 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4074:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 23169 | /* 63551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32), |
| 23170 | /* 63554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23171 | /* 63556 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23172 | /* 63558 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23173 | /* 63560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23174 | /* 63563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23175 | /* 63569 */ GIR_RootConstrainSelectedInstOperands, |
| 23176 | /* 63570 */ // GIR_Coverage, 1597, |
| 23177 | /* 63570 */ GIR_EraseRootFromParent_Done, |
| 23178 | /* 63571 */ // Label 1368: @63571 |
| 23179 | /* 63571 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(63625), // Rule ID 1598 // |
| 23180 | /* 63576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23181 | /* 63579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23182 | /* 63584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23183 | /* 63587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23184 | /* 63590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23185 | /* 63593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23186 | /* 63597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23187 | /* 63601 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23188 | /* 63605 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4074:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 23189 | /* 63605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16), |
| 23190 | /* 63608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23191 | /* 63610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23192 | /* 63612 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23193 | /* 63614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23194 | /* 63617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23195 | /* 63623 */ GIR_RootConstrainSelectedInstOperands, |
| 23196 | /* 63624 */ // GIR_Coverage, 1598, |
| 23197 | /* 63624 */ GIR_EraseRootFromParent_Done, |
| 23198 | /* 63625 */ // Label 1369: @63625 |
| 23199 | /* 63625 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(63679), // Rule ID 1599 // |
| 23200 | /* 63630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23201 | /* 63633 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23202 | /* 63638 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23203 | /* 63641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23204 | /* 63644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23205 | /* 63647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23206 | /* 63651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23207 | /* 63655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23208 | /* 63659 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4074:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 23209 | /* 63659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32), |
| 23210 | /* 63662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23211 | /* 63664 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23212 | /* 63666 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23213 | /* 63668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23214 | /* 63671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23215 | /* 63677 */ GIR_RootConstrainSelectedInstOperands, |
| 23216 | /* 63678 */ // GIR_Coverage, 1599, |
| 23217 | /* 63678 */ GIR_EraseRootFromParent_Done, |
| 23218 | /* 63679 */ // Label 1370: @63679 |
| 23219 | /* 63679 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(63733), // Rule ID 1600 // |
| 23220 | /* 63684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23221 | /* 63687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23222 | /* 63692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 23223 | /* 63695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 23224 | /* 63698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 23225 | /* 63701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23226 | /* 63705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23227 | /* 63709 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23228 | /* 63713 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4074:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 23229 | /* 63713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8), |
| 23230 | /* 63716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23231 | /* 63718 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23232 | /* 63720 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23233 | /* 63722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23234 | /* 63725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23235 | /* 63731 */ GIR_RootConstrainSelectedInstOperands, |
| 23236 | /* 63732 */ // GIR_Coverage, 1600, |
| 23237 | /* 63732 */ GIR_EraseRootFromParent_Done, |
| 23238 | /* 63733 */ // Label 1371: @63733 |
| 23239 | /* 63733 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(63787), // Rule ID 1601 // |
| 23240 | /* 63738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23241 | /* 63741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23242 | /* 63746 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23243 | /* 63749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23244 | /* 63752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23245 | /* 63755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23246 | /* 63759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23247 | /* 63763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23248 | /* 63767 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4074:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 23249 | /* 63767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8), |
| 23250 | /* 63770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23251 | /* 63772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23252 | /* 63774 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23253 | /* 63776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23254 | /* 63779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23255 | /* 63785 */ GIR_RootConstrainSelectedInstOperands, |
| 23256 | /* 63786 */ // GIR_Coverage, 1601, |
| 23257 | /* 63786 */ GIR_EraseRootFromParent_Done, |
| 23258 | /* 63787 */ // Label 1372: @63787 |
| 23259 | /* 63787 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(63841), // Rule ID 1602 // |
| 23260 | /* 63792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23261 | /* 63795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23262 | /* 63800 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 23263 | /* 63803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 23264 | /* 63806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 23265 | /* 63809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23266 | /* 63813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23267 | /* 63817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23268 | /* 63821 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4074:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 23269 | /* 63821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64), |
| 23270 | /* 63824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23271 | /* 63826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23272 | /* 63828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23273 | /* 63830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23274 | /* 63833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23275 | /* 63839 */ GIR_RootConstrainSelectedInstOperands, |
| 23276 | /* 63840 */ // GIR_Coverage, 1602, |
| 23277 | /* 63840 */ GIR_EraseRootFromParent_Done, |
| 23278 | /* 63841 */ // Label 1373: @63841 |
| 23279 | /* 63841 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(63895), // Rule ID 1603 // |
| 23280 | /* 63846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23281 | /* 63849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 23282 | /* 63854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 23283 | /* 63857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 23284 | /* 63860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 23285 | /* 63863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23286 | /* 63867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23287 | /* 63871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23288 | /* 63875 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4074:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 23289 | /* 63875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64), |
| 23290 | /* 63878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23291 | /* 63880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23292 | /* 63882 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23293 | /* 63884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23294 | /* 63887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23295 | /* 63893 */ GIR_RootConstrainSelectedInstOperands, |
| 23296 | /* 63894 */ // GIR_Coverage, 1603, |
| 23297 | /* 63894 */ GIR_EraseRootFromParent_Done, |
| 23298 | /* 63895 */ // Label 1374: @63895 |
| 23299 | /* 63895 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(63949), // Rule ID 1604 // |
| 23300 | /* 63900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23301 | /* 63903 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23302 | /* 63908 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 23303 | /* 63911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 23304 | /* 63914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 23305 | /* 63917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23306 | /* 63921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23307 | /* 63925 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23308 | /* 63929 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4075:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 23309 | /* 63929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16), |
| 23310 | /* 63932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23311 | /* 63934 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23312 | /* 63936 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23313 | /* 63938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23314 | /* 63941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23315 | /* 63947 */ GIR_RootConstrainSelectedInstOperands, |
| 23316 | /* 63948 */ // GIR_Coverage, 1604, |
| 23317 | /* 63948 */ GIR_EraseRootFromParent_Done, |
| 23318 | /* 63949 */ // Label 1375: @63949 |
| 23319 | /* 63949 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(64003), // Rule ID 1605 // |
| 23320 | /* 63954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23321 | /* 63957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23322 | /* 63962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 23323 | /* 63965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 23324 | /* 63968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 23325 | /* 63971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23326 | /* 63975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23327 | /* 63979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23328 | /* 63983 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4075:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 23329 | /* 63983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32), |
| 23330 | /* 63986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23331 | /* 63988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23332 | /* 63990 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23333 | /* 63992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23334 | /* 63995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23335 | /* 64001 */ GIR_RootConstrainSelectedInstOperands, |
| 23336 | /* 64002 */ // GIR_Coverage, 1605, |
| 23337 | /* 64002 */ GIR_EraseRootFromParent_Done, |
| 23338 | /* 64003 */ // Label 1376: @64003 |
| 23339 | /* 64003 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(64057), // Rule ID 1606 // |
| 23340 | /* 64008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23341 | /* 64011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23342 | /* 64016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23343 | /* 64019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23344 | /* 64022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23345 | /* 64025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23346 | /* 64029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23347 | /* 64033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23348 | /* 64037 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4075:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 23349 | /* 64037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16), |
| 23350 | /* 64040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23351 | /* 64042 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23352 | /* 64044 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23353 | /* 64046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23354 | /* 64049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23355 | /* 64055 */ GIR_RootConstrainSelectedInstOperands, |
| 23356 | /* 64056 */ // GIR_Coverage, 1606, |
| 23357 | /* 64056 */ GIR_EraseRootFromParent_Done, |
| 23358 | /* 64057 */ // Label 1377: @64057 |
| 23359 | /* 64057 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(64111), // Rule ID 1607 // |
| 23360 | /* 64062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23361 | /* 64065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23362 | /* 64070 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23363 | /* 64073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23364 | /* 64076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23365 | /* 64079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23366 | /* 64083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23367 | /* 64087 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23368 | /* 64091 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4075:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 23369 | /* 64091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32), |
| 23370 | /* 64094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23371 | /* 64096 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23372 | /* 64098 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23373 | /* 64100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23374 | /* 64103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23375 | /* 64109 */ GIR_RootConstrainSelectedInstOperands, |
| 23376 | /* 64110 */ // GIR_Coverage, 1607, |
| 23377 | /* 64110 */ GIR_EraseRootFromParent_Done, |
| 23378 | /* 64111 */ // Label 1378: @64111 |
| 23379 | /* 64111 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(64165), // Rule ID 1608 // |
| 23380 | /* 64116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23381 | /* 64119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23382 | /* 64124 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 23383 | /* 64127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 23384 | /* 64130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 23385 | /* 64133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23386 | /* 64137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23387 | /* 64141 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23388 | /* 64145 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4075:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 23389 | /* 64145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8), |
| 23390 | /* 64148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23391 | /* 64150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23392 | /* 64152 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23393 | /* 64154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23394 | /* 64157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23395 | /* 64163 */ GIR_RootConstrainSelectedInstOperands, |
| 23396 | /* 64164 */ // GIR_Coverage, 1608, |
| 23397 | /* 64164 */ GIR_EraseRootFromParent_Done, |
| 23398 | /* 64165 */ // Label 1379: @64165 |
| 23399 | /* 64165 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(64219), // Rule ID 1609 // |
| 23400 | /* 64170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23401 | /* 64173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23402 | /* 64178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23403 | /* 64181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23404 | /* 64184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23405 | /* 64187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23406 | /* 64191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23407 | /* 64195 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23408 | /* 64199 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4075:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 23409 | /* 64199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8), |
| 23410 | /* 64202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23411 | /* 64204 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23412 | /* 64206 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23413 | /* 64208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23414 | /* 64211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23415 | /* 64217 */ GIR_RootConstrainSelectedInstOperands, |
| 23416 | /* 64218 */ // GIR_Coverage, 1609, |
| 23417 | /* 64218 */ GIR_EraseRootFromParent_Done, |
| 23418 | /* 64219 */ // Label 1380: @64219 |
| 23419 | /* 64219 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(64273), // Rule ID 1610 // |
| 23420 | /* 64224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23421 | /* 64227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23422 | /* 64232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 23423 | /* 64235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 23424 | /* 64238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 23425 | /* 64241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23426 | /* 64245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23427 | /* 64249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23428 | /* 64253 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4075:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 23429 | /* 64253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64), |
| 23430 | /* 64256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23431 | /* 64258 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23432 | /* 64260 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23433 | /* 64262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23434 | /* 64265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23435 | /* 64271 */ GIR_RootConstrainSelectedInstOperands, |
| 23436 | /* 64272 */ // GIR_Coverage, 1610, |
| 23437 | /* 64272 */ GIR_EraseRootFromParent_Done, |
| 23438 | /* 64273 */ // Label 1381: @64273 |
| 23439 | /* 64273 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(64327), // Rule ID 1611 // |
| 23440 | /* 64278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 23441 | /* 64281 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 23442 | /* 64286 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 23443 | /* 64289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 23444 | /* 64292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 23445 | /* 64295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23446 | /* 64299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23447 | /* 64303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23448 | /* 64307 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4075:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 23449 | /* 64307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64), |
| 23450 | /* 64310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23451 | /* 64312 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 23452 | /* 64314 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 23453 | /* 64316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23454 | /* 64319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23455 | /* 64325 */ GIR_RootConstrainSelectedInstOperands, |
| 23456 | /* 64326 */ // GIR_Coverage, 1611, |
| 23457 | /* 64326 */ GIR_EraseRootFromParent_Done, |
| 23458 | /* 64327 */ // Label 1382: @64327 |
| 23459 | /* 64327 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(64372), // Rule ID 1900 // |
| 23460 | /* 64332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 23461 | /* 64335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd), |
| 23462 | /* 64340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23463 | /* 64343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23464 | /* 64346 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23465 | /* 64349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23466 | /* 64353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23467 | /* 64357 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23468 | /* 64361 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3976:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 23469 | /* 64361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD), |
| 23470 | /* 64364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23471 | /* 64366 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23472 | /* 64368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 23473 | /* 64370 */ GIR_RootConstrainSelectedInstOperands, |
| 23474 | /* 64371 */ // GIR_Coverage, 1900, |
| 23475 | /* 64371 */ GIR_EraseRootFromParent_Done, |
| 23476 | /* 64372 */ // Label 1383: @64372 |
| 23477 | /* 64372 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(64417), // Rule ID 1901 // |
| 23478 | /* 64377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 23479 | /* 64380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese), |
| 23480 | /* 64385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23481 | /* 64388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23482 | /* 64391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23483 | /* 64394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23484 | /* 64398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23485 | /* 64402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23486 | /* 64406 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3977:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 23487 | /* 64406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE), |
| 23488 | /* 64409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23489 | /* 64411 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23490 | /* 64413 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 23491 | /* 64415 */ GIR_RootConstrainSelectedInstOperands, |
| 23492 | /* 64416 */ // GIR_Coverage, 1901, |
| 23493 | /* 64416 */ GIR_EraseRootFromParent_Done, |
| 23494 | /* 64417 */ // Label 1384: @64417 |
| 23495 | /* 64417 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(64462), // Rule ID 1904 // |
| 23496 | /* 64422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 23497 | /* 64425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1), |
| 23498 | /* 64430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23499 | /* 64433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23500 | /* 64436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23501 | /* 64439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23502 | /* 64443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23503 | /* 64447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23504 | /* 64451 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3990:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 23505 | /* 64451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1), |
| 23506 | /* 64454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23507 | /* 64456 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23508 | /* 64458 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 23509 | /* 64460 */ GIR_RootConstrainSelectedInstOperands, |
| 23510 | /* 64461 */ // GIR_Coverage, 1904, |
| 23511 | /* 64461 */ GIR_EraseRootFromParent_Done, |
| 23512 | /* 64462 */ // Label 1385: @64462 |
| 23513 | /* 64462 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(64507), // Rule ID 1905 // |
| 23514 | /* 64467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 23515 | /* 64470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0), |
| 23516 | /* 64475 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23517 | /* 64478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23518 | /* 64481 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23519 | /* 64484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23520 | /* 64488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23521 | /* 64492 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23522 | /* 64496 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 23523 | /* 64496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0), |
| 23524 | /* 64499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23525 | /* 64501 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23526 | /* 64503 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 23527 | /* 64505 */ GIR_RootConstrainSelectedInstOperands, |
| 23528 | /* 64506 */ // GIR_Coverage, 1905, |
| 23529 | /* 64506 */ GIR_EraseRootFromParent_Done, |
| 23530 | /* 64507 */ // Label 1386: @64507 |
| 23531 | /* 64507 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(64561), // Rule ID 1914 // |
| 23532 | /* 64512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 23533 | /* 64515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr), |
| 23534 | /* 64520 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23535 | /* 64523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23536 | /* 64526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23537 | /* 64529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23538 | /* 64533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23539 | /* 64537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23540 | /* 64541 */ // (intrinsic_wo_chain:{ *:[i32] } 3826:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 23541 | /* 64541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR), |
| 23542 | /* 64544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23543 | /* 64546 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 23544 | /* 64548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23545 | /* 64550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23546 | /* 64553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23547 | /* 64559 */ GIR_RootConstrainSelectedInstOperands, |
| 23548 | /* 64560 */ // GIR_Coverage, 1914, |
| 23549 | /* 64560 */ GIR_EraseRootFromParent_Done, |
| 23550 | /* 64561 */ // Label 1387: @64561 |
| 23551 | /* 64561 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(64615), // Rule ID 1915 // |
| 23552 | /* 64566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 23553 | /* 64569 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl), |
| 23554 | /* 64574 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23555 | /* 64577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23556 | /* 64580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23557 | /* 64583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23558 | /* 64587 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23559 | /* 64591 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23560 | /* 64595 */ // (intrinsic_wo_chain:{ *:[i32] } 3833:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 23561 | /* 64595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL), |
| 23562 | /* 64598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23563 | /* 64600 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 23564 | /* 64602 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23565 | /* 64604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23566 | /* 64607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23567 | /* 64613 */ GIR_RootConstrainSelectedInstOperands, |
| 23568 | /* 64614 */ // GIR_Coverage, 1915, |
| 23569 | /* 64614 */ GIR_EraseRootFromParent_Done, |
| 23570 | /* 64615 */ // Label 1388: @64615 |
| 23571 | /* 64615 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(64672), // Rule ID 2038 // |
| 23572 | /* 64620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 23573 | /* 64623 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 23574 | /* 64628 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23575 | /* 64631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23576 | /* 64634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23577 | /* 64637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23578 | /* 64641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23579 | /* 64645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23580 | /* 64649 */ // (intrinsic_wo_chain:{ *:[i32] } 4171:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 23581 | /* 64649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16), |
| 23582 | /* 64652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23583 | /* 64654 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 23584 | /* 64656 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 23585 | /* 64658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23586 | /* 64661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23587 | /* 64664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23588 | /* 64670 */ GIR_RootConstrainSelectedInstOperands, |
| 23589 | /* 64671 */ // GIR_Coverage, 2038, |
| 23590 | /* 64671 */ GIR_EraseRootFromParent_Done, |
| 23591 | /* 64672 */ // Label 1389: @64672 |
| 23592 | /* 64672 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(64729), // Rule ID 2045 // |
| 23593 | /* 64677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 23594 | /* 64680 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 23595 | /* 64685 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23596 | /* 64688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23597 | /* 64691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23598 | /* 64694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23599 | /* 64698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23600 | /* 64702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23601 | /* 64706 */ // (intrinsic_wo_chain:{ *:[i32] } 4196:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 23602 | /* 64706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16), |
| 23603 | /* 64709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23604 | /* 64711 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 23605 | /* 64713 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 23606 | /* 64715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23607 | /* 64718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23608 | /* 64721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23609 | /* 64727 */ GIR_RootConstrainSelectedInstOperands, |
| 23610 | /* 64728 */ // GIR_Coverage, 2045, |
| 23611 | /* 64728 */ GIR_EraseRootFromParent_Done, |
| 23612 | /* 64729 */ // Label 1390: @64729 |
| 23613 | /* 64729 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(64783), // Rule ID 2092 // |
| 23614 | /* 64734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 23615 | /* 64737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 23616 | /* 64742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23617 | /* 64745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23618 | /* 64748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23619 | /* 64751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23620 | /* 64755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23621 | /* 64759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23622 | /* 64763 */ // (intrinsic_wo_chain:{ *:[i32] } 4147:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 23623 | /* 64763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD), |
| 23624 | /* 64766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23625 | /* 64768 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23626 | /* 64770 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23627 | /* 64772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23628 | /* 64775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23629 | /* 64781 */ GIR_RootConstrainSelectedInstOperands, |
| 23630 | /* 64782 */ // GIR_Coverage, 2092, |
| 23631 | /* 64782 */ GIR_EraseRootFromParent_Done, |
| 23632 | /* 64783 */ // Label 1391: @64783 |
| 23633 | /* 64783 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(64837), // Rule ID 2093 // |
| 23634 | /* 64788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 23635 | /* 64791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 23636 | /* 64796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23637 | /* 64799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23638 | /* 64802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23639 | /* 64805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23640 | /* 64809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23641 | /* 64813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23642 | /* 64817 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 23643 | /* 64817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX), |
| 23644 | /* 64820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23645 | /* 64822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23646 | /* 64824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23647 | /* 64826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23648 | /* 64829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23649 | /* 64835 */ GIR_RootConstrainSelectedInstOperands, |
| 23650 | /* 64836 */ // GIR_Coverage, 2093, |
| 23651 | /* 64836 */ GIR_EraseRootFromParent_Done, |
| 23652 | /* 64837 */ // Label 1392: @64837 |
| 23653 | /* 64837 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(64891), // Rule ID 2094 // |
| 23654 | /* 64842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 23655 | /* 64845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 23656 | /* 64850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23657 | /* 64853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23658 | /* 64856 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23659 | /* 64859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23660 | /* 64863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23661 | /* 64867 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23662 | /* 64871 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 23663 | /* 64871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD), |
| 23664 | /* 64874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23665 | /* 64876 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23666 | /* 64878 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23667 | /* 64880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23668 | /* 64883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23669 | /* 64889 */ GIR_RootConstrainSelectedInstOperands, |
| 23670 | /* 64890 */ // GIR_Coverage, 2094, |
| 23671 | /* 64890 */ GIR_EraseRootFromParent_Done, |
| 23672 | /* 64891 */ // Label 1393: @64891 |
| 23673 | /* 64891 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(64945), // Rule ID 2095 // |
| 23674 | /* 64896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 23675 | /* 64899 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 23676 | /* 64904 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23677 | /* 64907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23678 | /* 64910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23679 | /* 64913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23680 | /* 64917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23681 | /* 64921 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 23682 | /* 64925 */ // (intrinsic_wo_chain:{ *:[i32] } 4156:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 23683 | /* 64925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX), |
| 23684 | /* 64928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23685 | /* 64930 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23686 | /* 64932 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23687 | /* 64934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23688 | /* 64937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23689 | /* 64943 */ GIR_RootConstrainSelectedInstOperands, |
| 23690 | /* 64944 */ // GIR_Coverage, 2095, |
| 23691 | /* 64944 */ GIR_EraseRootFromParent_Done, |
| 23692 | /* 64945 */ // Label 1394: @64945 |
| 23693 | /* 64945 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(64999), // Rule ID 2169 // |
| 23694 | /* 64950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 23695 | /* 64953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 23696 | /* 64958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23697 | /* 64961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23698 | /* 64964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23699 | /* 64967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23700 | /* 64971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23701 | /* 64975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23702 | /* 64979 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23703 | /* 64979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 23704 | /* 64982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23705 | /* 64984 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23706 | /* 64986 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23707 | /* 64988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23708 | /* 64991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23709 | /* 64997 */ GIR_RootConstrainSelectedInstOperands, |
| 23710 | /* 64998 */ // GIR_Coverage, 2169, |
| 23711 | /* 64998 */ GIR_EraseRootFromParent_Done, |
| 23712 | /* 64999 */ // Label 1395: @64999 |
| 23713 | /* 64999 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(65053), // Rule ID 2170 // |
| 23714 | /* 65004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 23715 | /* 65007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 23716 | /* 65012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23717 | /* 65015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23718 | /* 65018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23719 | /* 65021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23720 | /* 65025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23721 | /* 65029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23722 | /* 65033 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23723 | /* 65033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 23724 | /* 65036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23725 | /* 65038 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23726 | /* 65040 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23727 | /* 65042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23728 | /* 65045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23729 | /* 65051 */ GIR_RootConstrainSelectedInstOperands, |
| 23730 | /* 65052 */ // GIR_Coverage, 2170, |
| 23731 | /* 65052 */ GIR_EraseRootFromParent_Done, |
| 23732 | /* 65053 */ // Label 1396: @65053 |
| 23733 | /* 65053 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(65107), // Rule ID 2171 // |
| 23734 | /* 65058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 23735 | /* 65061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 23736 | /* 65066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23737 | /* 65069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23738 | /* 65072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23739 | /* 65075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23740 | /* 65079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23741 | /* 65083 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23742 | /* 65087 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23743 | /* 65087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 23744 | /* 65090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23745 | /* 65092 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23746 | /* 65094 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23747 | /* 65096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23748 | /* 65099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23749 | /* 65105 */ GIR_RootConstrainSelectedInstOperands, |
| 23750 | /* 65106 */ // GIR_Coverage, 2171, |
| 23751 | /* 65106 */ GIR_EraseRootFromParent_Done, |
| 23752 | /* 65107 */ // Label 1397: @65107 |
| 23753 | /* 65107 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(65161), // Rule ID 2172 // |
| 23754 | /* 65112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 23755 | /* 65115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 23756 | /* 65120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23757 | /* 65123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23758 | /* 65126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23759 | /* 65129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23760 | /* 65133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23761 | /* 65137 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23762 | /* 65141 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23763 | /* 65141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 23764 | /* 65144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23765 | /* 65146 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23766 | /* 65148 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23767 | /* 65150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23768 | /* 65153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23769 | /* 65159 */ GIR_RootConstrainSelectedInstOperands, |
| 23770 | /* 65160 */ // GIR_Coverage, 2172, |
| 23771 | /* 65160 */ GIR_EraseRootFromParent_Done, |
| 23772 | /* 65161 */ // Label 1398: @65161 |
| 23773 | /* 65161 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(65215), // Rule ID 2173 // |
| 23774 | /* 65166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 23775 | /* 65169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 23776 | /* 65174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23777 | /* 65177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23778 | /* 65180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23779 | /* 65183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23780 | /* 65187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23781 | /* 65191 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23782 | /* 65195 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23783 | /* 65195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB), |
| 23784 | /* 65198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23785 | /* 65200 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23786 | /* 65202 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23787 | /* 65204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23788 | /* 65207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23789 | /* 65213 */ GIR_RootConstrainSelectedInstOperands, |
| 23790 | /* 65214 */ // GIR_Coverage, 2173, |
| 23791 | /* 65214 */ GIR_EraseRootFromParent_Done, |
| 23792 | /* 65215 */ // Label 1399: @65215 |
| 23793 | /* 65215 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(65269), // Rule ID 2174 // |
| 23794 | /* 65220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 23795 | /* 65223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 23796 | /* 65228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23797 | /* 65231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23798 | /* 65234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23799 | /* 65237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23800 | /* 65241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23801 | /* 65245 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23802 | /* 65249 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23803 | /* 65249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT), |
| 23804 | /* 65252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23805 | /* 65254 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23806 | /* 65256 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23807 | /* 65258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23808 | /* 65261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23809 | /* 65267 */ GIR_RootConstrainSelectedInstOperands, |
| 23810 | /* 65268 */ // GIR_Coverage, 2174, |
| 23811 | /* 65268 */ GIR_EraseRootFromParent_Done, |
| 23812 | /* 65269 */ // Label 1400: @65269 |
| 23813 | /* 65269 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(65326), // Rule ID 2285 // |
| 23814 | /* 65274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23815 | /* 65277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 23816 | /* 65282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23817 | /* 65285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23818 | /* 65288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23819 | /* 65291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23820 | /* 65295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23821 | /* 65299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23822 | /* 65303 */ // (intrinsic_wo_chain:{ *:[i32] } 4171:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 23823 | /* 65303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16), |
| 23824 | /* 65306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23825 | /* 65308 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23826 | /* 65310 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23827 | /* 65312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23828 | /* 65315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23829 | /* 65318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23830 | /* 65324 */ GIR_RootConstrainSelectedInstOperands, |
| 23831 | /* 65325 */ // GIR_Coverage, 2285, |
| 23832 | /* 65325 */ GIR_EraseRootFromParent_Done, |
| 23833 | /* 65326 */ // Label 1401: @65326 |
| 23834 | /* 65326 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(65380), // Rule ID 2315 // |
| 23835 | /* 65331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23836 | /* 65334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 23837 | /* 65339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23838 | /* 65342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23839 | /* 65345 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23840 | /* 65348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23841 | /* 65352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23842 | /* 65356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23843 | /* 65360 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 23844 | /* 65360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 23845 | /* 65363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23846 | /* 65365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 23847 | /* 65367 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 23848 | /* 65369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23849 | /* 65372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23850 | /* 65378 */ GIR_RootConstrainSelectedInstOperands, |
| 23851 | /* 65379 */ // GIR_Coverage, 2315, |
| 23852 | /* 65379 */ GIR_EraseRootFromParent_Done, |
| 23853 | /* 65380 */ // Label 1402: @65380 |
| 23854 | /* 65380 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(65434), // Rule ID 2316 // |
| 23855 | /* 65385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23856 | /* 65388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 23857 | /* 65393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23858 | /* 65396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23859 | /* 65399 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23860 | /* 65402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23861 | /* 65406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23862 | /* 65410 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23863 | /* 65414 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 23864 | /* 65414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 23865 | /* 65417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23866 | /* 65419 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 23867 | /* 65421 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 23868 | /* 65423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23869 | /* 65426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23870 | /* 65432 */ GIR_RootConstrainSelectedInstOperands, |
| 23871 | /* 65433 */ // GIR_Coverage, 2316, |
| 23872 | /* 65433 */ GIR_EraseRootFromParent_Done, |
| 23873 | /* 65434 */ // Label 1403: @65434 |
| 23874 | /* 65434 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(65488), // Rule ID 2356 // |
| 23875 | /* 65439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23876 | /* 65442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 23877 | /* 65447 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23878 | /* 65450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23879 | /* 65453 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23880 | /* 65456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23881 | /* 65460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23882 | /* 65464 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23883 | /* 65468 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23884 | /* 65468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 23885 | /* 65471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23886 | /* 65473 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23887 | /* 65475 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23888 | /* 65477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23889 | /* 65480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23890 | /* 65486 */ GIR_RootConstrainSelectedInstOperands, |
| 23891 | /* 65487 */ // GIR_Coverage, 2356, |
| 23892 | /* 65487 */ GIR_EraseRootFromParent_Done, |
| 23893 | /* 65488 */ // Label 1404: @65488 |
| 23894 | /* 65488 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(65542), // Rule ID 2357 // |
| 23895 | /* 65493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23896 | /* 65496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 23897 | /* 65501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23898 | /* 65504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23899 | /* 65507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23900 | /* 65510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23901 | /* 65514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23902 | /* 65518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23903 | /* 65522 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23904 | /* 65522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 23905 | /* 65525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23906 | /* 65527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23907 | /* 65529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23908 | /* 65531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23909 | /* 65534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23910 | /* 65540 */ GIR_RootConstrainSelectedInstOperands, |
| 23911 | /* 65541 */ // GIR_Coverage, 2357, |
| 23912 | /* 65541 */ GIR_EraseRootFromParent_Done, |
| 23913 | /* 65542 */ // Label 1405: @65542 |
| 23914 | /* 65542 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(65596), // Rule ID 2358 // |
| 23915 | /* 65547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23916 | /* 65550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 23917 | /* 65555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23918 | /* 65558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23919 | /* 65561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23920 | /* 65564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23921 | /* 65568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23922 | /* 65572 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23923 | /* 65576 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23924 | /* 65576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 23925 | /* 65579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23926 | /* 65581 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23927 | /* 65583 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23928 | /* 65585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23929 | /* 65588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23930 | /* 65594 */ GIR_RootConstrainSelectedInstOperands, |
| 23931 | /* 65595 */ // GIR_Coverage, 2358, |
| 23932 | /* 65595 */ GIR_EraseRootFromParent_Done, |
| 23933 | /* 65596 */ // Label 1406: @65596 |
| 23934 | /* 65596 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(65650), // Rule ID 2359 // |
| 23935 | /* 65601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23936 | /* 65604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 23937 | /* 65609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23938 | /* 65612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23939 | /* 65615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23940 | /* 65618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23941 | /* 65622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23942 | /* 65626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23943 | /* 65630 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23944 | /* 65630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 23945 | /* 65633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23946 | /* 65635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23947 | /* 65637 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23948 | /* 65639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23949 | /* 65642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23950 | /* 65648 */ GIR_RootConstrainSelectedInstOperands, |
| 23951 | /* 65649 */ // GIR_Coverage, 2359, |
| 23952 | /* 65649 */ GIR_EraseRootFromParent_Done, |
| 23953 | /* 65650 */ // Label 1407: @65650 |
| 23954 | /* 65650 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(65704), // Rule ID 2360 // |
| 23955 | /* 65655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23956 | /* 65658 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 23957 | /* 65663 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23958 | /* 65666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23959 | /* 65669 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23960 | /* 65672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23961 | /* 65676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23962 | /* 65680 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23963 | /* 65684 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23964 | /* 65684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB), |
| 23965 | /* 65687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23966 | /* 65689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23967 | /* 65691 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23968 | /* 65693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23969 | /* 65696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23970 | /* 65702 */ GIR_RootConstrainSelectedInstOperands, |
| 23971 | /* 65703 */ // GIR_Coverage, 2360, |
| 23972 | /* 65703 */ GIR_EraseRootFromParent_Done, |
| 23973 | /* 65704 */ // Label 1408: @65704 |
| 23974 | /* 65704 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(65758), // Rule ID 2361 // |
| 23975 | /* 65709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 23976 | /* 65712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 23977 | /* 65717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23978 | /* 65720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23979 | /* 65723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23980 | /* 65726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23981 | /* 65730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23982 | /* 65734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23983 | /* 65738 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23984 | /* 65738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT), |
| 23985 | /* 65741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23986 | /* 65743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23987 | /* 65745 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23988 | /* 65747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23989 | /* 65750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23990 | /* 65756 */ GIR_RootConstrainSelectedInstOperands, |
| 23991 | /* 65757 */ // GIR_Coverage, 2361, |
| 23992 | /* 65757 */ GIR_EraseRootFromParent_Done, |
| 23993 | /* 65758 */ // Label 1409: @65758 |
| 23994 | /* 65758 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(65806), // Rule ID 2887 // |
| 23995 | /* 65763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 23996 | /* 65766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23997 | /* 65771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 23998 | /* 65774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 23999 | /* 65777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 24000 | /* 65780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24001 | /* 65784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24002 | /* 65788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24003 | /* 65792 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4007:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) |
| 24004 | /* 65792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 24005 | /* 65795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24006 | /* 65797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24007 | /* 65799 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24008 | /* 65801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24009 | /* 65804 */ GIR_RootConstrainSelectedInstOperands, |
| 24010 | /* 65805 */ // GIR_Coverage, 2887, |
| 24011 | /* 65805 */ GIR_EraseRootFromParent_Done, |
| 24012 | /* 65806 */ // Label 1410: @65806 |
| 24013 | /* 65806 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(65854), // Rule ID 2888 // |
| 24014 | /* 65811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 24015 | /* 65814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 24016 | /* 65819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 24017 | /* 65822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 24018 | /* 65825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 24019 | /* 65828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24020 | /* 65832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24021 | /* 65836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24022 | /* 65840 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4006:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) |
| 24023 | /* 65840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 24024 | /* 65843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24025 | /* 65845 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24026 | /* 65847 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24027 | /* 65849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24028 | /* 65852 */ GIR_RootConstrainSelectedInstOperands, |
| 24029 | /* 65853 */ // GIR_Coverage, 2888, |
| 24030 | /* 65853 */ GIR_EraseRootFromParent_Done, |
| 24031 | /* 65854 */ // Label 1411: @65854 |
| 24032 | /* 65854 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(65902), // Rule ID 2889 // |
| 24033 | /* 65859 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 24034 | /* 65862 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 24035 | /* 65867 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24036 | /* 65870 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24037 | /* 65873 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24038 | /* 65876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24039 | /* 65880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24040 | /* 65884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24041 | /* 65888 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4007:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) |
| 24042 | /* 65888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 24043 | /* 65891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24044 | /* 65893 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24045 | /* 65895 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24046 | /* 65897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24047 | /* 65900 */ GIR_RootConstrainSelectedInstOperands, |
| 24048 | /* 65901 */ // GIR_Coverage, 2889, |
| 24049 | /* 65901 */ GIR_EraseRootFromParent_Done, |
| 24050 | /* 65902 */ // Label 1412: @65902 |
| 24051 | /* 65902 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(65950), // Rule ID 2890 // |
| 24052 | /* 65907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 24053 | /* 65910 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 24054 | /* 65915 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24055 | /* 65918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24056 | /* 65921 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24057 | /* 65924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24058 | /* 65928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24059 | /* 65932 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24060 | /* 65936 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4006:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) |
| 24061 | /* 65936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 24062 | /* 65939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24063 | /* 65941 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24064 | /* 65943 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24065 | /* 65945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24066 | /* 65948 */ GIR_RootConstrainSelectedInstOperands, |
| 24067 | /* 65949 */ // GIR_Coverage, 2890, |
| 24068 | /* 65949 */ GIR_EraseRootFromParent_Done, |
| 24069 | /* 65950 */ // Label 1413: @65950 |
| 24070 | /* 65950 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(65998), // Rule ID 2891 // |
| 24071 | /* 65955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 24072 | /* 65958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 24073 | /* 65963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 24074 | /* 65966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 24075 | /* 65969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 24076 | /* 65972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24077 | /* 65976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24078 | /* 65980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24079 | /* 65984 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4007:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) |
| 24080 | /* 65984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 24081 | /* 65987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24082 | /* 65989 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24083 | /* 65991 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24084 | /* 65993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24085 | /* 65996 */ GIR_RootConstrainSelectedInstOperands, |
| 24086 | /* 65997 */ // GIR_Coverage, 2891, |
| 24087 | /* 65997 */ GIR_EraseRootFromParent_Done, |
| 24088 | /* 65998 */ // Label 1414: @65998 |
| 24089 | /* 65998 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(66046), // Rule ID 2892 // |
| 24090 | /* 66003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 24091 | /* 66006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 24092 | /* 66011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 24093 | /* 66014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 24094 | /* 66017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 24095 | /* 66020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24096 | /* 66024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24097 | /* 66028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24098 | /* 66032 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4006:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) |
| 24099 | /* 66032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 24100 | /* 66035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24101 | /* 66037 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24102 | /* 66039 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24103 | /* 66041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24104 | /* 66044 */ GIR_RootConstrainSelectedInstOperands, |
| 24105 | /* 66045 */ // GIR_Coverage, 2892, |
| 24106 | /* 66045 */ GIR_EraseRootFromParent_Done, |
| 24107 | /* 66046 */ // Label 1415: @66046 |
| 24108 | /* 66046 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(66094), // Rule ID 2893 // |
| 24109 | /* 66051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 24110 | /* 66054 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 24111 | /* 66059 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24112 | /* 66062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24113 | /* 66065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24114 | /* 66068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24115 | /* 66072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24116 | /* 66076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24117 | /* 66080 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4007:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) |
| 24118 | /* 66080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 24119 | /* 66083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24120 | /* 66085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24121 | /* 66087 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24122 | /* 66089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24123 | /* 66092 */ GIR_RootConstrainSelectedInstOperands, |
| 24124 | /* 66093 */ // GIR_Coverage, 2893, |
| 24125 | /* 66093 */ GIR_EraseRootFromParent_Done, |
| 24126 | /* 66094 */ // Label 1416: @66094 |
| 24127 | /* 66094 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(66142), // Rule ID 2894 // |
| 24128 | /* 66099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 24129 | /* 66102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 24130 | /* 66107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24131 | /* 66110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24132 | /* 66113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24133 | /* 66116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24134 | /* 66120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24135 | /* 66124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24136 | /* 66128 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4006:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) |
| 24137 | /* 66128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 24138 | /* 66131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24139 | /* 66133 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24140 | /* 66135 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24141 | /* 66137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24142 | /* 66140 */ GIR_RootConstrainSelectedInstOperands, |
| 24143 | /* 66141 */ // GIR_Coverage, 2894, |
| 24144 | /* 66141 */ GIR_EraseRootFromParent_Done, |
| 24145 | /* 66142 */ // Label 1417: @66142 |
| 24146 | /* 66142 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(66217), // Rule ID 3405 // |
| 24147 | /* 66147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24148 | /* 66150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 24149 | /* 66155 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24150 | /* 66158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24151 | /* 66161 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24152 | /* 66164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24153 | /* 66168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24154 | /* 66172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24155 | /* 66176 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3894:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24156 | /* 66176 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24157 | /* 66179 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24158 | /* 66183 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24159 | /* 66188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 24160 | /* 66191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24161 | /* 66193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24162 | /* 66195 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24163 | /* 66197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24164 | /* 66200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24165 | /* 66206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24166 | /* 66212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24167 | /* 66215 */ GIR_RootConstrainSelectedInstOperands, |
| 24168 | /* 66216 */ // GIR_Coverage, 3405, |
| 24169 | /* 66216 */ GIR_EraseRootFromParent_Done, |
| 24170 | /* 66217 */ // Label 1418: @66217 |
| 24171 | /* 66217 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(66322), // Rule ID 3481 // |
| 24172 | /* 66222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24173 | /* 66225 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 24174 | /* 66230 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24175 | /* 66233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24176 | /* 66236 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24177 | /* 66239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24178 | /* 66243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24179 | /* 66247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24180 | /* 66251 */ // (intrinsic_wo_chain:{ *:[f32] } 3802:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 24181 | /* 66251 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24182 | /* 66254 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24183 | /* 66258 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24184 | /* 66263 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24185 | /* 66267 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24186 | /* 66272 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24187 | /* 66275 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32), |
| 24188 | /* 66279 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24189 | /* 66284 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24190 | /* 66287 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24191 | /* 66291 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24192 | /* 66294 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24193 | /* 66300 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24194 | /* 66306 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24195 | /* 66308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24196 | /* 66311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24197 | /* 66313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24198 | /* 66316 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 24199 | /* 66321 */ // GIR_Coverage, 3481, |
| 24200 | /* 66321 */ GIR_EraseRootFromParent_Done, |
| 24201 | /* 66322 */ // Label 1419: @66322 |
| 24202 | /* 66322 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(66427), // Rule ID 3483 // |
| 24203 | /* 66327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24204 | /* 66330 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 24205 | /* 66335 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 24206 | /* 66338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 24207 | /* 66341 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24208 | /* 66344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24209 | /* 66348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24210 | /* 66352 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24211 | /* 66356 */ // (intrinsic_wo_chain:{ *:[f16] } 3802:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 24212 | /* 66356 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24213 | /* 66359 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24214 | /* 66363 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24215 | /* 66368 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24216 | /* 66372 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24217 | /* 66377 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24218 | /* 66380 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16), |
| 24219 | /* 66384 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24220 | /* 66389 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24221 | /* 66392 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24222 | /* 66396 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24223 | /* 66399 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24224 | /* 66405 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24225 | /* 66411 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24226 | /* 66413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24227 | /* 66416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24228 | /* 66418 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24229 | /* 66421 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 24230 | /* 66426 */ // GIR_Coverage, 3483, |
| 24231 | /* 66426 */ GIR_EraseRootFromParent_Done, |
| 24232 | /* 66427 */ // Label 1420: @66427 |
| 24233 | /* 66427 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(66532), // Rule ID 3485 // |
| 24234 | /* 66432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24235 | /* 66435 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 24236 | /* 66440 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24237 | /* 66443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24238 | /* 66446 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24239 | /* 66449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24240 | /* 66453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24241 | /* 66457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24242 | /* 66461 */ // (intrinsic_wo_chain:{ *:[f32] } 3793:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 24243 | /* 66461 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24244 | /* 66464 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24245 | /* 66468 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24246 | /* 66473 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24247 | /* 66477 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24248 | /* 66482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24249 | /* 66485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32), |
| 24250 | /* 66489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24251 | /* 66494 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24252 | /* 66497 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24253 | /* 66501 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24254 | /* 66504 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24255 | /* 66510 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24256 | /* 66516 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24257 | /* 66518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24258 | /* 66521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24259 | /* 66523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24260 | /* 66526 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 24261 | /* 66531 */ // GIR_Coverage, 3485, |
| 24262 | /* 66531 */ GIR_EraseRootFromParent_Done, |
| 24263 | /* 66532 */ // Label 1421: @66532 |
| 24264 | /* 66532 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(66637), // Rule ID 3487 // |
| 24265 | /* 66537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24266 | /* 66540 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 24267 | /* 66545 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 24268 | /* 66548 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 24269 | /* 66551 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24270 | /* 66554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24271 | /* 66558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24272 | /* 66562 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24273 | /* 66566 */ // (intrinsic_wo_chain:{ *:[f16] } 3793:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 24274 | /* 66566 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24275 | /* 66569 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24276 | /* 66573 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24277 | /* 66578 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24278 | /* 66582 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24279 | /* 66587 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24280 | /* 66590 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16), |
| 24281 | /* 66594 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24282 | /* 66599 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24283 | /* 66602 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24284 | /* 66606 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24285 | /* 66609 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24286 | /* 66615 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24287 | /* 66621 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24288 | /* 66623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24289 | /* 66626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24290 | /* 66628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24291 | /* 66631 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 24292 | /* 66636 */ // GIR_Coverage, 3487, |
| 24293 | /* 66636 */ GIR_EraseRootFromParent_Done, |
| 24294 | /* 66637 */ // Label 1422: @66637 |
| 24295 | /* 66637 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(66742), // Rule ID 3489 // |
| 24296 | /* 66642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24297 | /* 66645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 24298 | /* 66650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24299 | /* 66653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24300 | /* 66656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24301 | /* 66659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24302 | /* 66663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24303 | /* 66667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24304 | /* 66671 */ // (intrinsic_wo_chain:{ *:[f32] } 3800:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 24305 | /* 66671 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24306 | /* 66674 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24307 | /* 66678 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24308 | /* 66683 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24309 | /* 66687 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24310 | /* 66692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24311 | /* 66695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32), |
| 24312 | /* 66699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24313 | /* 66704 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24314 | /* 66707 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24315 | /* 66711 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24316 | /* 66714 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24317 | /* 66720 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24318 | /* 66726 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24319 | /* 66728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24320 | /* 66731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24321 | /* 66733 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24322 | /* 66736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 24323 | /* 66741 */ // GIR_Coverage, 3489, |
| 24324 | /* 66741 */ GIR_EraseRootFromParent_Done, |
| 24325 | /* 66742 */ // Label 1423: @66742 |
| 24326 | /* 66742 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(66847), // Rule ID 3491 // |
| 24327 | /* 66747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24328 | /* 66750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 24329 | /* 66755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 24330 | /* 66758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 24331 | /* 66761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24332 | /* 66764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24333 | /* 66768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24334 | /* 66772 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24335 | /* 66776 */ // (intrinsic_wo_chain:{ *:[f16] } 3800:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 24336 | /* 66776 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24337 | /* 66779 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24338 | /* 66783 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24339 | /* 66788 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24340 | /* 66792 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24341 | /* 66797 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24342 | /* 66800 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16), |
| 24343 | /* 66804 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24344 | /* 66809 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24345 | /* 66812 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24346 | /* 66816 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24347 | /* 66819 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24348 | /* 66825 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24349 | /* 66831 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24350 | /* 66833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24351 | /* 66836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24352 | /* 66838 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24353 | /* 66841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 24354 | /* 66846 */ // GIR_Coverage, 3491, |
| 24355 | /* 66846 */ GIR_EraseRootFromParent_Done, |
| 24356 | /* 66847 */ // Label 1424: @66847 |
| 24357 | /* 66847 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(66952), // Rule ID 3493 // |
| 24358 | /* 66852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24359 | /* 66855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 24360 | /* 66860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24361 | /* 66863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24362 | /* 66866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24363 | /* 66869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24364 | /* 66873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 24365 | /* 66877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24366 | /* 66881 */ // (intrinsic_wo_chain:{ *:[f32] } 3791:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 24367 | /* 66881 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24368 | /* 66884 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24369 | /* 66888 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24370 | /* 66893 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24371 | /* 66897 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24372 | /* 66902 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24373 | /* 66905 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32), |
| 24374 | /* 66909 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24375 | /* 66914 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24376 | /* 66917 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24377 | /* 66921 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24378 | /* 66924 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24379 | /* 66930 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24380 | /* 66936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24381 | /* 66938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24382 | /* 66941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24383 | /* 66943 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24384 | /* 66946 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 24385 | /* 66951 */ // GIR_Coverage, 3493, |
| 24386 | /* 66951 */ GIR_EraseRootFromParent_Done, |
| 24387 | /* 66952 */ // Label 1425: @66952 |
| 24388 | /* 66952 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(67057), // Rule ID 3495 // |
| 24389 | /* 66957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24390 | /* 66960 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 24391 | /* 66965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 24392 | /* 66968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 24393 | /* 66971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24394 | /* 66974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24395 | /* 66978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 24396 | /* 66982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24397 | /* 66986 */ // (intrinsic_wo_chain:{ *:[f16] } 3791:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 24398 | /* 66986 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24399 | /* 66989 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24400 | /* 66993 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24401 | /* 66998 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 24402 | /* 67002 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 24403 | /* 67007 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24404 | /* 67010 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16), |
| 24405 | /* 67014 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24406 | /* 67019 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24407 | /* 67022 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 24408 | /* 67026 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24409 | /* 67029 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24410 | /* 67035 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24411 | /* 67041 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24412 | /* 67043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24413 | /* 67046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24414 | /* 67048 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24415 | /* 67051 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 24416 | /* 67056 */ // GIR_Coverage, 3495, |
| 24417 | /* 67056 */ GIR_EraseRootFromParent_Done, |
| 24418 | /* 67057 */ // Label 1426: @67057 |
| 24419 | /* 67057 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(67117), // Rule ID 3545 // |
| 24420 | /* 67062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24421 | /* 67065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 24422 | /* 67070 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24423 | /* 67073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24424 | /* 67076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24425 | /* 67079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24426 | /* 67083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24427 | /* 67087 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24428 | /* 67091 */ // (intrinsic_wo_chain:{ *:[i32] } 3798:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 24429 | /* 67091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8), |
| 24430 | /* 67094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 24431 | /* 67096 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 24432 | /* 67098 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 24433 | /* 67100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24434 | /* 67103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24435 | /* 67109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24436 | /* 67115 */ GIR_RootConstrainSelectedInstOperands, |
| 24437 | /* 67116 */ // GIR_Coverage, 3545, |
| 24438 | /* 67116 */ GIR_EraseRootFromParent_Done, |
| 24439 | /* 67117 */ // Label 1427: @67117 |
| 24440 | /* 67117 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(67177), // Rule ID 3547 // |
| 24441 | /* 67122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24442 | /* 67125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 24443 | /* 67130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24444 | /* 67133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24445 | /* 67136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24446 | /* 67139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24447 | /* 67143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24448 | /* 67147 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24449 | /* 67151 */ // (intrinsic_wo_chain:{ *:[i32] } 3798:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 24450 | /* 67151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16), |
| 24451 | /* 67154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 24452 | /* 67156 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 24453 | /* 67158 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 24454 | /* 67160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24455 | /* 67163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24456 | /* 67169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24457 | /* 67175 */ GIR_RootConstrainSelectedInstOperands, |
| 24458 | /* 67176 */ // GIR_Coverage, 3547, |
| 24459 | /* 67176 */ GIR_EraseRootFromParent_Done, |
| 24460 | /* 67177 */ // Label 1428: @67177 |
| 24461 | /* 67177 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(67237), // Rule ID 3549 // |
| 24462 | /* 67182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24463 | /* 67185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 24464 | /* 67190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24465 | /* 67193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24466 | /* 67196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24467 | /* 67199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24468 | /* 67203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24469 | /* 67207 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24470 | /* 67211 */ // (intrinsic_wo_chain:{ *:[i32] } 3798:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 24471 | /* 67211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32), |
| 24472 | /* 67214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 24473 | /* 67216 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 24474 | /* 67218 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 24475 | /* 67220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24476 | /* 67223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24477 | /* 67229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24478 | /* 67235 */ GIR_RootConstrainSelectedInstOperands, |
| 24479 | /* 67236 */ // GIR_Coverage, 3549, |
| 24480 | /* 67236 */ GIR_EraseRootFromParent_Done, |
| 24481 | /* 67237 */ // Label 1429: @67237 |
| 24482 | /* 67237 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(67297), // Rule ID 3551 // |
| 24483 | /* 67242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24484 | /* 67245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 24485 | /* 67250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24486 | /* 67253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24487 | /* 67256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24488 | /* 67259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24489 | /* 67263 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24490 | /* 67267 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24491 | /* 67271 */ // (intrinsic_wo_chain:{ *:[i32] } 3789:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 24492 | /* 67271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8), |
| 24493 | /* 67274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 24494 | /* 67276 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 24495 | /* 67278 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 24496 | /* 67280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24497 | /* 67283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24498 | /* 67289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24499 | /* 67295 */ GIR_RootConstrainSelectedInstOperands, |
| 24500 | /* 67296 */ // GIR_Coverage, 3551, |
| 24501 | /* 67296 */ GIR_EraseRootFromParent_Done, |
| 24502 | /* 67297 */ // Label 1430: @67297 |
| 24503 | /* 67297 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(67357), // Rule ID 3553 // |
| 24504 | /* 67302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24505 | /* 67305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 24506 | /* 67310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24507 | /* 67313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24508 | /* 67316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24509 | /* 67319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24510 | /* 67323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24511 | /* 67327 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24512 | /* 67331 */ // (intrinsic_wo_chain:{ *:[i32] } 3789:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 24513 | /* 67331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16), |
| 24514 | /* 67334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 24515 | /* 67336 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 24516 | /* 67338 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 24517 | /* 67340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24518 | /* 67343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24519 | /* 67349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24520 | /* 67355 */ GIR_RootConstrainSelectedInstOperands, |
| 24521 | /* 67356 */ // GIR_Coverage, 3553, |
| 24522 | /* 67356 */ GIR_EraseRootFromParent_Done, |
| 24523 | /* 67357 */ // Label 1431: @67357 |
| 24524 | /* 67357 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(67417), // Rule ID 3555 // |
| 24525 | /* 67362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24526 | /* 67365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 24527 | /* 67370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24528 | /* 67373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24529 | /* 67376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24530 | /* 67379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24531 | /* 67383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24532 | /* 67387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24533 | /* 67391 */ // (intrinsic_wo_chain:{ *:[i32] } 3789:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 24534 | /* 67391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32), |
| 24535 | /* 67394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 24536 | /* 67396 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 24537 | /* 67398 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 24538 | /* 67400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24539 | /* 67403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24540 | /* 67409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24541 | /* 67415 */ GIR_RootConstrainSelectedInstOperands, |
| 24542 | /* 67416 */ // GIR_Coverage, 3555, |
| 24543 | /* 67416 */ GIR_EraseRootFromParent_Done, |
| 24544 | /* 67417 */ // Label 1432: @67417 |
| 24545 | /* 67417 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(67492), // Rule ID 3662 // |
| 24546 | /* 67422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24547 | /* 67425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 24548 | /* 67430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24549 | /* 67433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24550 | /* 67436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24551 | /* 67439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24552 | /* 67443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24553 | /* 67447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24554 | /* 67451 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3894:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24555 | /* 67451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24556 | /* 67454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24557 | /* 67458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24558 | /* 67463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 24559 | /* 67466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24560 | /* 67468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24561 | /* 67470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24562 | /* 67472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24563 | /* 67475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24564 | /* 67481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24565 | /* 67487 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24566 | /* 67490 */ GIR_RootConstrainSelectedInstOperands, |
| 24567 | /* 67491 */ // GIR_Coverage, 3662, |
| 24568 | /* 67491 */ GIR_EraseRootFromParent_Done, |
| 24569 | /* 67492 */ // Label 1433: @67492 |
| 24570 | /* 67492 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(67567), // Rule ID 3667 // |
| 24571 | /* 67497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24572 | /* 67500 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 24573 | /* 67505 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24574 | /* 67508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24575 | /* 67511 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24576 | /* 67514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24577 | /* 67518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24578 | /* 67522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24579 | /* 67526 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3897:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24580 | /* 67526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24581 | /* 67529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24582 | /* 67533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24583 | /* 67538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 24584 | /* 67541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24585 | /* 67543 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24586 | /* 67545 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24587 | /* 67547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24588 | /* 67550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24589 | /* 67556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24590 | /* 67562 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24591 | /* 67565 */ GIR_RootConstrainSelectedInstOperands, |
| 24592 | /* 67566 */ // GIR_Coverage, 3667, |
| 24593 | /* 67566 */ GIR_EraseRootFromParent_Done, |
| 24594 | /* 67567 */ // Label 1434: @67567 |
| 24595 | /* 67567 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(67642), // Rule ID 3672 // |
| 24596 | /* 67572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24597 | /* 67575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 24598 | /* 67580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24599 | /* 67583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24600 | /* 67586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24601 | /* 67589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24602 | /* 67593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24603 | /* 67597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24604 | /* 67601 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3897:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24605 | /* 67601 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24606 | /* 67604 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24607 | /* 67608 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24608 | /* 67613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 24609 | /* 67616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24610 | /* 67618 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24611 | /* 67620 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24612 | /* 67622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24613 | /* 67625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24614 | /* 67631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24615 | /* 67637 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24616 | /* 67640 */ GIR_RootConstrainSelectedInstOperands, |
| 24617 | /* 67641 */ // GIR_Coverage, 3672, |
| 24618 | /* 67641 */ GIR_EraseRootFromParent_Done, |
| 24619 | /* 67642 */ // Label 1435: @67642 |
| 24620 | /* 67642 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(67717), // Rule ID 3852 // |
| 24621 | /* 67647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24622 | /* 67650 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 24623 | /* 67655 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24624 | /* 67658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24625 | /* 67661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24626 | /* 67664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24627 | /* 67668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24628 | /* 67672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24629 | /* 67676 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3917:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24630 | /* 67676 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24631 | /* 67679 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24632 | /* 67683 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24633 | /* 67688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8), |
| 24634 | /* 67691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24635 | /* 67693 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24636 | /* 67695 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24637 | /* 67697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24638 | /* 67700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24639 | /* 67706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24640 | /* 67712 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24641 | /* 67715 */ GIR_RootConstrainSelectedInstOperands, |
| 24642 | /* 67716 */ // GIR_Coverage, 3852, |
| 24643 | /* 67716 */ GIR_EraseRootFromParent_Done, |
| 24644 | /* 67717 */ // Label 1436: @67717 |
| 24645 | /* 67717 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(67792), // Rule ID 3859 // |
| 24646 | /* 67722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24647 | /* 67725 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 24648 | /* 67730 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24649 | /* 67733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24650 | /* 67736 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24651 | /* 67739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24652 | /* 67743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24653 | /* 67747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24654 | /* 67751 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3917:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24655 | /* 67751 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24656 | /* 67754 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24657 | /* 67758 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24658 | /* 67763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16), |
| 24659 | /* 67766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24660 | /* 67768 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24661 | /* 67770 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24662 | /* 67772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24663 | /* 67775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24664 | /* 67781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24665 | /* 67787 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24666 | /* 67790 */ GIR_RootConstrainSelectedInstOperands, |
| 24667 | /* 67791 */ // GIR_Coverage, 3859, |
| 24668 | /* 67791 */ GIR_EraseRootFromParent_Done, |
| 24669 | /* 67792 */ // Label 1437: @67792 |
| 24670 | /* 67792 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(67867), // Rule ID 3863 // |
| 24671 | /* 67797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24672 | /* 67800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 24673 | /* 67805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24674 | /* 67808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24675 | /* 67811 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24676 | /* 67814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24677 | /* 67818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24678 | /* 67822 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24679 | /* 67826 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3917:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24680 | /* 67826 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24681 | /* 67829 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24682 | /* 67833 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24683 | /* 67838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32), |
| 24684 | /* 67841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24685 | /* 67843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24686 | /* 67845 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24687 | /* 67847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24688 | /* 67850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24689 | /* 67856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24690 | /* 67862 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24691 | /* 67865 */ GIR_RootConstrainSelectedInstOperands, |
| 24692 | /* 67866 */ // GIR_Coverage, 3863, |
| 24693 | /* 67866 */ GIR_EraseRootFromParent_Done, |
| 24694 | /* 67867 */ // Label 1438: @67867 |
| 24695 | /* 67867 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(67942), // Rule ID 3865 // |
| 24696 | /* 67872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24697 | /* 67875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 24698 | /* 67880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24699 | /* 67883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24700 | /* 67886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24701 | /* 67889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24702 | /* 67893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24703 | /* 67897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24704 | /* 67901 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3926:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24705 | /* 67901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24706 | /* 67904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24707 | /* 67908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24708 | /* 67913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8), |
| 24709 | /* 67916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24710 | /* 67918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24711 | /* 67920 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24712 | /* 67922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24713 | /* 67925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24714 | /* 67931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24715 | /* 67937 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24716 | /* 67940 */ GIR_RootConstrainSelectedInstOperands, |
| 24717 | /* 67941 */ // GIR_Coverage, 3865, |
| 24718 | /* 67941 */ GIR_EraseRootFromParent_Done, |
| 24719 | /* 67942 */ // Label 1439: @67942 |
| 24720 | /* 67942 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(68017), // Rule ID 3867 // |
| 24721 | /* 67947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24722 | /* 67950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 24723 | /* 67955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24724 | /* 67958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24725 | /* 67961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24726 | /* 67964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24727 | /* 67968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24728 | /* 67972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24729 | /* 67976 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3926:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24730 | /* 67976 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24731 | /* 67979 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24732 | /* 67983 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24733 | /* 67988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16), |
| 24734 | /* 67991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24735 | /* 67993 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24736 | /* 67995 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24737 | /* 67997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24738 | /* 68000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24739 | /* 68006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24740 | /* 68012 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24741 | /* 68015 */ GIR_RootConstrainSelectedInstOperands, |
| 24742 | /* 68016 */ // GIR_Coverage, 3867, |
| 24743 | /* 68016 */ GIR_EraseRootFromParent_Done, |
| 24744 | /* 68017 */ // Label 1440: @68017 |
| 24745 | /* 68017 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(68092), // Rule ID 3869 // |
| 24746 | /* 68022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24747 | /* 68025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 24748 | /* 68030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24749 | /* 68033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24750 | /* 68036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24751 | /* 68039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24752 | /* 68043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24753 | /* 68047 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24754 | /* 68051 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3926:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24755 | /* 68051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24756 | /* 68054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24757 | /* 68058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24758 | /* 68063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32), |
| 24759 | /* 68066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24760 | /* 68068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24761 | /* 68070 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24762 | /* 68072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24763 | /* 68075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24764 | /* 68081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24765 | /* 68087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24766 | /* 68090 */ GIR_RootConstrainSelectedInstOperands, |
| 24767 | /* 68091 */ // GIR_Coverage, 3869, |
| 24768 | /* 68091 */ GIR_EraseRootFromParent_Done, |
| 24769 | /* 68092 */ // Label 1441: @68092 |
| 24770 | /* 68092 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(68167), // Rule ID 4395 // |
| 24771 | /* 68097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24772 | /* 68100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul), |
| 24773 | /* 68105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24774 | /* 68108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24775 | /* 68111 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24776 | /* 68114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24777 | /* 68118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24778 | /* 68122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24779 | /* 68126 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24780 | /* 68126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24781 | /* 68129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24782 | /* 68133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24783 | /* 68138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 24784 | /* 68141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24785 | /* 68143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24786 | /* 68145 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24787 | /* 68147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24788 | /* 68150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24789 | /* 68156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24790 | /* 68162 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24791 | /* 68165 */ GIR_RootConstrainSelectedInstOperands, |
| 24792 | /* 68166 */ // GIR_Coverage, 4395, |
| 24793 | /* 68166 */ GIR_EraseRootFromParent_Done, |
| 24794 | /* 68167 */ // Label 1442: @68167 |
| 24795 | /* 68167 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(68242), // Rule ID 4402 // |
| 24796 | /* 68172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24797 | /* 68175 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul), |
| 24798 | /* 68180 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24799 | /* 68183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24800 | /* 68186 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24801 | /* 68189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24802 | /* 68193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24803 | /* 68197 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24804 | /* 68201 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24805 | /* 68201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24806 | /* 68204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24807 | /* 68208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24808 | /* 68213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 24809 | /* 68216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24810 | /* 68218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24811 | /* 68220 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24812 | /* 68222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24813 | /* 68225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24814 | /* 68231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24815 | /* 68237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24816 | /* 68240 */ GIR_RootConstrainSelectedInstOperands, |
| 24817 | /* 68241 */ // GIR_Coverage, 4402, |
| 24818 | /* 68241 */ GIR_EraseRootFromParent_Done, |
| 24819 | /* 68242 */ // Label 1443: @68242 |
| 24820 | /* 68242 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(68317), // Rule ID 4435 // |
| 24821 | /* 68247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24822 | /* 68250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd), |
| 24823 | /* 68255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24824 | /* 68258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24825 | /* 68261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24826 | /* 68264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24827 | /* 68268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24828 | /* 68272 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24829 | /* 68276 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3844:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24830 | /* 68276 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24831 | /* 68279 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24832 | /* 68283 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24833 | /* 68288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 24834 | /* 68291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24835 | /* 68293 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24836 | /* 68295 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24837 | /* 68297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24838 | /* 68300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24839 | /* 68306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24840 | /* 68312 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24841 | /* 68315 */ GIR_RootConstrainSelectedInstOperands, |
| 24842 | /* 68316 */ // GIR_Coverage, 4435, |
| 24843 | /* 68316 */ GIR_EraseRootFromParent_Done, |
| 24844 | /* 68317 */ // Label 1444: @68317 |
| 24845 | /* 68317 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(68392), // Rule ID 4442 // |
| 24846 | /* 68322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24847 | /* 68325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd), |
| 24848 | /* 68330 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24849 | /* 68333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24850 | /* 68336 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24851 | /* 68339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24852 | /* 68343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24853 | /* 68347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24854 | /* 68351 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3844:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24855 | /* 68351 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24856 | /* 68354 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24857 | /* 68358 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24858 | /* 68363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 24859 | /* 68366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24860 | /* 68368 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24861 | /* 68370 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24862 | /* 68372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24863 | /* 68375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24864 | /* 68381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24865 | /* 68387 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24866 | /* 68390 */ GIR_RootConstrainSelectedInstOperands, |
| 24867 | /* 68391 */ // GIR_Coverage, 4442, |
| 24868 | /* 68391 */ GIR_EraseRootFromParent_Done, |
| 24869 | /* 68392 */ // Label 1445: @68392 |
| 24870 | /* 68392 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(68467), // Rule ID 4449 // |
| 24871 | /* 68397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24872 | /* 68400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub), |
| 24873 | /* 68405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24874 | /* 68408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24875 | /* 68411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24876 | /* 68414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24877 | /* 68418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24878 | /* 68422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24879 | /* 68426 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3975:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24880 | /* 68426 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24881 | /* 68429 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24882 | /* 68433 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24883 | /* 68438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 24884 | /* 68441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24885 | /* 68443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24886 | /* 68445 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24887 | /* 68447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24888 | /* 68450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24889 | /* 68456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24890 | /* 68462 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24891 | /* 68465 */ GIR_RootConstrainSelectedInstOperands, |
| 24892 | /* 68466 */ // GIR_Coverage, 4449, |
| 24893 | /* 68466 */ GIR_EraseRootFromParent_Done, |
| 24894 | /* 68467 */ // Label 1446: @68467 |
| 24895 | /* 68467 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(68542), // Rule ID 4456 // |
| 24896 | /* 68472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24897 | /* 68475 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub), |
| 24898 | /* 68480 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24899 | /* 68483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24900 | /* 68486 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24901 | /* 68489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24902 | /* 68493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24903 | /* 68497 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24904 | /* 68501 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3975:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24905 | /* 68501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24906 | /* 68504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24907 | /* 68508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24908 | /* 68513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 24909 | /* 68516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24910 | /* 68518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24911 | /* 68520 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24912 | /* 68522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24913 | /* 68525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24914 | /* 68531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24915 | /* 68537 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24916 | /* 68540 */ GIR_RootConstrainSelectedInstOperands, |
| 24917 | /* 68541 */ // GIR_Coverage, 4456, |
| 24918 | /* 68541 */ GIR_EraseRootFromParent_Done, |
| 24919 | /* 68542 */ // Label 1447: @68542 |
| 24920 | /* 68542 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(68605), // Rule ID 4580 // |
| 24921 | /* 68547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24922 | /* 68550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq), |
| 24923 | /* 68555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 24924 | /* 68558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24925 | /* 68561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24926 | /* 68564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24927 | /* 68568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24928 | /* 68572 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24929 | /* 68576 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3776:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 0:{ *:[i32] }) |
| 24930 | /* 68576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24931 | /* 68579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24932 | /* 68581 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24933 | /* 68583 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24934 | /* 68585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24935 | /* 68588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24936 | /* 68591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24937 | /* 68597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24938 | /* 68603 */ GIR_RootConstrainSelectedInstOperands, |
| 24939 | /* 68604 */ // GIR_Coverage, 4580, |
| 24940 | /* 68604 */ GIR_EraseRootFromParent_Done, |
| 24941 | /* 68605 */ // Label 1448: @68605 |
| 24942 | /* 68605 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(68668), // Rule ID 4582 // |
| 24943 | /* 68610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24944 | /* 68613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq), |
| 24945 | /* 68618 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 24946 | /* 68621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24947 | /* 68624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24948 | /* 68627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24949 | /* 68631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24950 | /* 68635 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24951 | /* 68639 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3776:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 0:{ *:[i32] }) |
| 24952 | /* 68639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24953 | /* 68642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24954 | /* 68644 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24955 | /* 68646 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24956 | /* 68648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24957 | /* 68651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24958 | /* 68654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24959 | /* 68660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24960 | /* 68666 */ GIR_RootConstrainSelectedInstOperands, |
| 24961 | /* 68667 */ // GIR_Coverage, 4582, |
| 24962 | /* 68667 */ GIR_EraseRootFromParent_Done, |
| 24963 | /* 68668 */ // Label 1449: @68668 |
| 24964 | /* 68668 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(68731), // Rule ID 4669 // |
| 24965 | /* 68673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24966 | /* 68676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne), |
| 24967 | /* 68681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 24968 | /* 68684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24969 | /* 68687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24970 | /* 68690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24971 | /* 68694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24972 | /* 68698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24973 | /* 68702 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3781:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 1:{ *:[i32] }) |
| 24974 | /* 68702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24975 | /* 68705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24976 | /* 68707 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24977 | /* 68709 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24978 | /* 68711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24979 | /* 68714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24980 | /* 68717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24981 | /* 68723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24982 | /* 68729 */ GIR_RootConstrainSelectedInstOperands, |
| 24983 | /* 68730 */ // GIR_Coverage, 4669, |
| 24984 | /* 68730 */ GIR_EraseRootFromParent_Done, |
| 24985 | /* 68731 */ // Label 1450: @68731 |
| 24986 | /* 68731 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(68794), // Rule ID 4671 // |
| 24987 | /* 68736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24988 | /* 68739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne), |
| 24989 | /* 68744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 24990 | /* 68747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24991 | /* 68750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24992 | /* 68753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24993 | /* 68757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24994 | /* 68761 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24995 | /* 68765 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3781:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 1:{ *:[i32] }) |
| 24996 | /* 68765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24997 | /* 68768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24998 | /* 68770 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24999 | /* 68772 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25000 | /* 68774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 25001 | /* 68777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25002 | /* 68780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25003 | /* 68786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25004 | /* 68792 */ GIR_RootConstrainSelectedInstOperands, |
| 25005 | /* 68793 */ // GIR_Coverage, 4671, |
| 25006 | /* 68793 */ GIR_EraseRootFromParent_Done, |
| 25007 | /* 68794 */ // Label 1451: @68794 |
| 25008 | /* 68794 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(68857), // Rule ID 4685 // |
| 25009 | /* 68799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25010 | /* 68802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge), |
| 25011 | /* 68807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 25012 | /* 68810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25013 | /* 68813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25014 | /* 68816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25015 | /* 68820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25016 | /* 68824 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25017 | /* 68828 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3777:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 10:{ *:[i32] }) |
| 25018 | /* 68828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 25019 | /* 68831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25020 | /* 68833 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25021 | /* 68835 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25022 | /* 68837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10, |
| 25023 | /* 68840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25024 | /* 68843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25025 | /* 68849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25026 | /* 68855 */ GIR_RootConstrainSelectedInstOperands, |
| 25027 | /* 68856 */ // GIR_Coverage, 4685, |
| 25028 | /* 68856 */ GIR_EraseRootFromParent_Done, |
| 25029 | /* 68857 */ // Label 1452: @68857 |
| 25030 | /* 68857 */ GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(68920), // Rule ID 4687 // |
| 25031 | /* 68862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25032 | /* 68865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge), |
| 25033 | /* 68870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 25034 | /* 68873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25035 | /* 68876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25036 | /* 68879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25037 | /* 68883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25038 | /* 68887 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25039 | /* 68891 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3777:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 10:{ *:[i32] }) |
| 25040 | /* 68891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 25041 | /* 68894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25042 | /* 68896 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25043 | /* 68898 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25044 | /* 68900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10, |
| 25045 | /* 68903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25046 | /* 68906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25047 | /* 68912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25048 | /* 68918 */ GIR_RootConstrainSelectedInstOperands, |
| 25049 | /* 68919 */ // GIR_Coverage, 4687, |
| 25050 | /* 68919 */ GIR_EraseRootFromParent_Done, |
| 25051 | /* 68920 */ // Label 1453: @68920 |
| 25052 | /* 68920 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(68983), // Rule ID 4701 // |
| 25053 | /* 68925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25054 | /* 68928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt), |
| 25055 | /* 68933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 25056 | /* 68936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25057 | /* 68939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25058 | /* 68942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25059 | /* 68946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25060 | /* 68950 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25061 | /* 68954 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3780:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 11:{ *:[i32] }) |
| 25062 | /* 68954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 25063 | /* 68957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25064 | /* 68959 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25065 | /* 68961 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25066 | /* 68963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 25067 | /* 68966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25068 | /* 68969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25069 | /* 68975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25070 | /* 68981 */ GIR_RootConstrainSelectedInstOperands, |
| 25071 | /* 68982 */ // GIR_Coverage, 4701, |
| 25072 | /* 68982 */ GIR_EraseRootFromParent_Done, |
| 25073 | /* 68983 */ // Label 1454: @68983 |
| 25074 | /* 68983 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(69046), // Rule ID 4703 // |
| 25075 | /* 68988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25076 | /* 68991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt), |
| 25077 | /* 68996 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 25078 | /* 68999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25079 | /* 69002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25080 | /* 69005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25081 | /* 69009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25082 | /* 69013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25083 | /* 69017 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3780:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 11:{ *:[i32] }) |
| 25084 | /* 69017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 25085 | /* 69020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25086 | /* 69022 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25087 | /* 69024 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25088 | /* 69026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 25089 | /* 69029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25090 | /* 69032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25091 | /* 69038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25092 | /* 69044 */ GIR_RootConstrainSelectedInstOperands, |
| 25093 | /* 69045 */ // GIR_Coverage, 4703, |
| 25094 | /* 69045 */ GIR_EraseRootFromParent_Done, |
| 25095 | /* 69046 */ // Label 1455: @69046 |
| 25096 | /* 69046 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(69109), // Rule ID 4717 // |
| 25097 | /* 69051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25098 | /* 69054 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt), |
| 25099 | /* 69059 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 25100 | /* 69062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25101 | /* 69065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25102 | /* 69068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25103 | /* 69072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25104 | /* 69076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25105 | /* 69080 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3778:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 12:{ *:[i32] }) |
| 25106 | /* 69080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 25107 | /* 69083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25108 | /* 69085 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25109 | /* 69087 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25110 | /* 69089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12, |
| 25111 | /* 69092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25112 | /* 69095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25113 | /* 69101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25114 | /* 69107 */ GIR_RootConstrainSelectedInstOperands, |
| 25115 | /* 69108 */ // GIR_Coverage, 4717, |
| 25116 | /* 69108 */ GIR_EraseRootFromParent_Done, |
| 25117 | /* 69109 */ // Label 1456: @69109 |
| 25118 | /* 69109 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(69172), // Rule ID 4719 // |
| 25119 | /* 69114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25120 | /* 69117 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt), |
| 25121 | /* 69122 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 25122 | /* 69125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25123 | /* 69128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25124 | /* 69131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25125 | /* 69135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25126 | /* 69139 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25127 | /* 69143 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3778:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 12:{ *:[i32] }) |
| 25128 | /* 69143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 25129 | /* 69146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25130 | /* 69148 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25131 | /* 69150 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25132 | /* 69152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12, |
| 25133 | /* 69155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25134 | /* 69158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25135 | /* 69164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25136 | /* 69170 */ GIR_RootConstrainSelectedInstOperands, |
| 25137 | /* 69171 */ // GIR_Coverage, 4719, |
| 25138 | /* 69171 */ GIR_EraseRootFromParent_Done, |
| 25139 | /* 69172 */ // Label 1457: @69172 |
| 25140 | /* 69172 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(69235), // Rule ID 4733 // |
| 25141 | /* 69177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25142 | /* 69180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le), |
| 25143 | /* 69185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 25144 | /* 69188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25145 | /* 69191 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25146 | /* 69194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25147 | /* 69198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25148 | /* 69202 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25149 | /* 69206 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3779:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 13:{ *:[i32] }) |
| 25150 | /* 69206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 25151 | /* 69209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25152 | /* 69211 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25153 | /* 69213 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25154 | /* 69215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13, |
| 25155 | /* 69218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25156 | /* 69221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25157 | /* 69227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25158 | /* 69233 */ GIR_RootConstrainSelectedInstOperands, |
| 25159 | /* 69234 */ // GIR_Coverage, 4733, |
| 25160 | /* 69234 */ GIR_EraseRootFromParent_Done, |
| 25161 | /* 69235 */ // Label 1458: @69235 |
| 25162 | /* 69235 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(69298), // Rule ID 4735 // |
| 25163 | /* 69240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25164 | /* 69243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le), |
| 25165 | /* 69248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 25166 | /* 69251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25167 | /* 69254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25168 | /* 69257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 25169 | /* 69261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25170 | /* 69265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25171 | /* 69269 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3779:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 13:{ *:[i32] }) |
| 25172 | /* 69269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 25173 | /* 69272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 25174 | /* 69274 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25175 | /* 69276 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25176 | /* 69278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13, |
| 25177 | /* 69281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25178 | /* 69284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25179 | /* 69290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25180 | /* 69296 */ GIR_RootConstrainSelectedInstOperands, |
| 25181 | /* 69297 */ // GIR_Coverage, 4735, |
| 25182 | /* 69297 */ GIR_EraseRootFromParent_Done, |
| 25183 | /* 69298 */ // Label 1459: @69298 |
| 25184 | /* 69298 */ GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(69373), // Rule ID 5257 // |
| 25185 | /* 69303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25186 | /* 69306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 25187 | /* 69311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25188 | /* 69314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25189 | /* 69317 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25190 | /* 69320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25191 | /* 69324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25192 | /* 69328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25193 | /* 69332 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3845:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 25194 | /* 69332 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25195 | /* 69335 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25196 | /* 69339 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25197 | /* 69344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 25198 | /* 69347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25199 | /* 69349 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 25200 | /* 69351 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25201 | /* 69353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25202 | /* 69356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25203 | /* 69362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25204 | /* 69368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25205 | /* 69371 */ GIR_RootConstrainSelectedInstOperands, |
| 25206 | /* 69372 */ // GIR_Coverage, 5257, |
| 25207 | /* 69372 */ GIR_EraseRootFromParent_Done, |
| 25208 | /* 69373 */ // Label 1460: @69373 |
| 25209 | /* 69373 */ GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(69448), // Rule ID 5262 // |
| 25210 | /* 69378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25211 | /* 69381 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 25212 | /* 69386 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25213 | /* 69389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25214 | /* 69392 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25215 | /* 69395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25216 | /* 69399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25217 | /* 69403 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25218 | /* 69407 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 25219 | /* 69407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25220 | /* 69410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25221 | /* 69414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25222 | /* 69419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 25223 | /* 69422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25224 | /* 69424 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 25225 | /* 69426 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25226 | /* 69428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25227 | /* 69431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25228 | /* 69437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25229 | /* 69443 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25230 | /* 69446 */ GIR_RootConstrainSelectedInstOperands, |
| 25231 | /* 69447 */ // GIR_Coverage, 5262, |
| 25232 | /* 69447 */ GIR_EraseRootFromParent_Done, |
| 25233 | /* 69448 */ // Label 1461: @69448 |
| 25234 | /* 69448 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(69523), // Rule ID 5264 // |
| 25235 | /* 69453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25236 | /* 69456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 25237 | /* 69461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25238 | /* 69464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25239 | /* 69467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25240 | /* 69470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25241 | /* 69474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25242 | /* 69478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25243 | /* 69482 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 25244 | /* 69482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25245 | /* 69485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25246 | /* 69489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25247 | /* 69494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 25248 | /* 69497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25249 | /* 69499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 25250 | /* 69501 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25251 | /* 69503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25252 | /* 69506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25253 | /* 69512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25254 | /* 69518 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25255 | /* 69521 */ GIR_RootConstrainSelectedInstOperands, |
| 25256 | /* 69522 */ // GIR_Coverage, 5264, |
| 25257 | /* 69522 */ GIR_EraseRootFromParent_Done, |
| 25258 | /* 69523 */ // Label 1462: @69523 |
| 25259 | /* 69523 */ GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(69598), // Rule ID 5266 // |
| 25260 | /* 69528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25261 | /* 69531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 25262 | /* 69536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25263 | /* 69539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25264 | /* 69542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25265 | /* 69545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25266 | /* 69549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25267 | /* 69553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25268 | /* 69557 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3845:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 25269 | /* 69557 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25270 | /* 69560 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25271 | /* 69564 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25272 | /* 69569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 25273 | /* 69572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25274 | /* 69574 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 25275 | /* 69576 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25276 | /* 69578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25277 | /* 69581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25278 | /* 69587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25279 | /* 69593 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25280 | /* 69596 */ GIR_RootConstrainSelectedInstOperands, |
| 25281 | /* 69597 */ // GIR_Coverage, 5266, |
| 25282 | /* 69597 */ GIR_EraseRootFromParent_Done, |
| 25283 | /* 69598 */ // Label 1463: @69598 |
| 25284 | /* 69598 */ GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(69673), // Rule ID 5268 // |
| 25285 | /* 69603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25286 | /* 69606 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 25287 | /* 69611 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25288 | /* 69614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25289 | /* 69617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25290 | /* 69620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25291 | /* 69624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25292 | /* 69628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25293 | /* 69632 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3845:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 25294 | /* 69632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25295 | /* 69635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25296 | /* 69639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25297 | /* 69644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 25298 | /* 69647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25299 | /* 69649 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 25300 | /* 69651 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25301 | /* 69653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25302 | /* 69656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25303 | /* 69662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25304 | /* 69668 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25305 | /* 69671 */ GIR_RootConstrainSelectedInstOperands, |
| 25306 | /* 69672 */ // GIR_Coverage, 5268, |
| 25307 | /* 69672 */ GIR_EraseRootFromParent_Done, |
| 25308 | /* 69673 */ // Label 1464: @69673 |
| 25309 | /* 69673 */ GIM_Reject, |
| 25310 | /* 69674 */ // Label 1075: @69674 |
| 25311 | /* 69674 */ GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(81136), |
| 25312 | /* 69679 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 25313 | /* 69682 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(69772), // Rule ID 4298 // |
| 25314 | /* 69687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 25315 | /* 69692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25316 | /* 69695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25317 | /* 69698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25318 | /* 69701 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25319 | /* 69704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25320 | /* 69708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25321 | /* 69712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25322 | /* 69716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25323 | /* 69720 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 25324 | /* 69724 */ // MIs[1] Operand 1 |
| 25325 | /* 69724 */ // No operand predicates |
| 25326 | /* 69724 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25327 | /* 69728 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25328 | /* 69730 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3927:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 25329 | /* 69730 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25330 | /* 69733 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25331 | /* 69737 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25332 | /* 69742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8), |
| 25333 | /* 69745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25334 | /* 69747 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25335 | /* 69749 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25336 | /* 69752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25337 | /* 69755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25338 | /* 69761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25339 | /* 69767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25340 | /* 69770 */ GIR_RootConstrainSelectedInstOperands, |
| 25341 | /* 69771 */ // GIR_Coverage, 4298, |
| 25342 | /* 69771 */ GIR_EraseRootFromParent_Done, |
| 25343 | /* 69772 */ // Label 1466: @69772 |
| 25344 | /* 69772 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(69862), // Rule ID 4300 // |
| 25345 | /* 69777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 25346 | /* 69782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25347 | /* 69785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25348 | /* 69788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25349 | /* 69791 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25350 | /* 69794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25351 | /* 69798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25352 | /* 69802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25353 | /* 69806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25354 | /* 69810 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 25355 | /* 69814 */ // MIs[1] Operand 1 |
| 25356 | /* 69814 */ // No operand predicates |
| 25357 | /* 69814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25358 | /* 69818 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25359 | /* 69820 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3927:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 25360 | /* 69820 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25361 | /* 69823 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25362 | /* 69827 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25363 | /* 69832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8), |
| 25364 | /* 69835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25365 | /* 69837 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25366 | /* 69839 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25367 | /* 69842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25368 | /* 69845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25369 | /* 69851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25370 | /* 69857 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25371 | /* 69860 */ GIR_RootConstrainSelectedInstOperands, |
| 25372 | /* 69861 */ // GIR_Coverage, 4300, |
| 25373 | /* 69861 */ GIR_EraseRootFromParent_Done, |
| 25374 | /* 69862 */ // Label 1467: @69862 |
| 25375 | /* 69862 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(69952), // Rule ID 4302 // |
| 25376 | /* 69867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 25377 | /* 69872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25378 | /* 69875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25379 | /* 69878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25380 | /* 69881 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25381 | /* 69884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25382 | /* 69888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25383 | /* 69892 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25384 | /* 69896 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25385 | /* 69900 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 25386 | /* 69904 */ // MIs[1] Operand 1 |
| 25387 | /* 69904 */ // No operand predicates |
| 25388 | /* 69904 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25389 | /* 69908 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25390 | /* 69910 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3927:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 25391 | /* 69910 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25392 | /* 69913 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25393 | /* 69917 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25394 | /* 69922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16), |
| 25395 | /* 69925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25396 | /* 69927 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25397 | /* 69929 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25398 | /* 69932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25399 | /* 69935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25400 | /* 69941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25401 | /* 69947 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25402 | /* 69950 */ GIR_RootConstrainSelectedInstOperands, |
| 25403 | /* 69951 */ // GIR_Coverage, 4302, |
| 25404 | /* 69951 */ GIR_EraseRootFromParent_Done, |
| 25405 | /* 69952 */ // Label 1468: @69952 |
| 25406 | /* 69952 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(70042), // Rule ID 4304 // |
| 25407 | /* 69957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 25408 | /* 69962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25409 | /* 69965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25410 | /* 69968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25411 | /* 69971 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25412 | /* 69974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25413 | /* 69978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25414 | /* 69982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25415 | /* 69986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25416 | /* 69990 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 25417 | /* 69994 */ // MIs[1] Operand 1 |
| 25418 | /* 69994 */ // No operand predicates |
| 25419 | /* 69994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25420 | /* 69998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25421 | /* 70000 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3927:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 25422 | /* 70000 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25423 | /* 70003 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25424 | /* 70007 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25425 | /* 70012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16), |
| 25426 | /* 70015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25427 | /* 70017 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25428 | /* 70019 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25429 | /* 70022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25430 | /* 70025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25431 | /* 70031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25432 | /* 70037 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25433 | /* 70040 */ GIR_RootConstrainSelectedInstOperands, |
| 25434 | /* 70041 */ // GIR_Coverage, 4304, |
| 25435 | /* 70041 */ GIR_EraseRootFromParent_Done, |
| 25436 | /* 70042 */ // Label 1469: @70042 |
| 25437 | /* 70042 */ GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(70132), // Rule ID 4306 // |
| 25438 | /* 70047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 25439 | /* 70052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25440 | /* 70055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25441 | /* 70058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25442 | /* 70061 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25443 | /* 70064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25444 | /* 70068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25445 | /* 70072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25446 | /* 70076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25447 | /* 70080 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 25448 | /* 70084 */ // MIs[1] Operand 1 |
| 25449 | /* 70084 */ // No operand predicates |
| 25450 | /* 70084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25451 | /* 70088 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25452 | /* 70090 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3927:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 25453 | /* 70090 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25454 | /* 70093 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25455 | /* 70097 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25456 | /* 70102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32), |
| 25457 | /* 70105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25458 | /* 70107 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25459 | /* 70109 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25460 | /* 70112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25461 | /* 70115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25462 | /* 70121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25463 | /* 70127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25464 | /* 70130 */ GIR_RootConstrainSelectedInstOperands, |
| 25465 | /* 70131 */ // GIR_Coverage, 4306, |
| 25466 | /* 70131 */ GIR_EraseRootFromParent_Done, |
| 25467 | /* 70132 */ // Label 1470: @70132 |
| 25468 | /* 70132 */ GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(70222), // Rule ID 4308 // |
| 25469 | /* 70137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 25470 | /* 70142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25471 | /* 70145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25472 | /* 70148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25473 | /* 70151 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25474 | /* 70154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25475 | /* 70158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25476 | /* 70162 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25477 | /* 70166 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25478 | /* 70170 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 25479 | /* 70174 */ // MIs[1] Operand 1 |
| 25480 | /* 70174 */ // No operand predicates |
| 25481 | /* 70174 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25482 | /* 70178 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25483 | /* 70180 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3927:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 25484 | /* 70180 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25485 | /* 70183 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25486 | /* 70187 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25487 | /* 70192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32), |
| 25488 | /* 70195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25489 | /* 70197 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25490 | /* 70199 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25491 | /* 70202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25492 | /* 70205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25493 | /* 70211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25494 | /* 70217 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25495 | /* 70220 */ GIR_RootConstrainSelectedInstOperands, |
| 25496 | /* 70221 */ // GIR_Coverage, 4308, |
| 25497 | /* 70221 */ GIR_EraseRootFromParent_Done, |
| 25498 | /* 70222 */ // Label 1471: @70222 |
| 25499 | /* 70222 */ GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(70312), // Rule ID 4316 // |
| 25500 | /* 70227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 25501 | /* 70232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25502 | /* 70235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25503 | /* 70238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25504 | /* 70241 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25505 | /* 70244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25506 | /* 70248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25507 | /* 70252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25508 | /* 70256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25509 | /* 70260 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 25510 | /* 70264 */ // MIs[1] Operand 1 |
| 25511 | /* 70264 */ // No operand predicates |
| 25512 | /* 70264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25513 | /* 70268 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25514 | /* 70270 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3949:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 25515 | /* 70270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25516 | /* 70273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25517 | /* 70277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25518 | /* 70282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8), |
| 25519 | /* 70285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25520 | /* 70287 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25521 | /* 70289 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25522 | /* 70292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25523 | /* 70295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25524 | /* 70301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25525 | /* 70307 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25526 | /* 70310 */ GIR_RootConstrainSelectedInstOperands, |
| 25527 | /* 70311 */ // GIR_Coverage, 4316, |
| 25528 | /* 70311 */ GIR_EraseRootFromParent_Done, |
| 25529 | /* 70312 */ // Label 1472: @70312 |
| 25530 | /* 70312 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(70402), // Rule ID 4318 // |
| 25531 | /* 70317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 25532 | /* 70322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25533 | /* 70325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25534 | /* 70328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25535 | /* 70331 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25536 | /* 70334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25537 | /* 70338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25538 | /* 70342 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25539 | /* 70346 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25540 | /* 70350 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 25541 | /* 70354 */ // MIs[1] Operand 1 |
| 25542 | /* 70354 */ // No operand predicates |
| 25543 | /* 70354 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25544 | /* 70358 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25545 | /* 70360 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3949:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 25546 | /* 70360 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25547 | /* 70363 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25548 | /* 70367 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25549 | /* 70372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8), |
| 25550 | /* 70375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25551 | /* 70377 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25552 | /* 70379 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25553 | /* 70382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25554 | /* 70385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25555 | /* 70391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25556 | /* 70397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25557 | /* 70400 */ GIR_RootConstrainSelectedInstOperands, |
| 25558 | /* 70401 */ // GIR_Coverage, 4318, |
| 25559 | /* 70401 */ GIR_EraseRootFromParent_Done, |
| 25560 | /* 70402 */ // Label 1473: @70402 |
| 25561 | /* 70402 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(70492), // Rule ID 4320 // |
| 25562 | /* 70407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 25563 | /* 70412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25564 | /* 70415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25565 | /* 70418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25566 | /* 70421 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25567 | /* 70424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25568 | /* 70428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25569 | /* 70432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25570 | /* 70436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25571 | /* 70440 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 25572 | /* 70444 */ // MIs[1] Operand 1 |
| 25573 | /* 70444 */ // No operand predicates |
| 25574 | /* 70444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25575 | /* 70448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25576 | /* 70450 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3949:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 25577 | /* 70450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25578 | /* 70453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25579 | /* 70457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25580 | /* 70462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16), |
| 25581 | /* 70465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25582 | /* 70467 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25583 | /* 70469 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25584 | /* 70472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25585 | /* 70475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25586 | /* 70481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25587 | /* 70487 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25588 | /* 70490 */ GIR_RootConstrainSelectedInstOperands, |
| 25589 | /* 70491 */ // GIR_Coverage, 4320, |
| 25590 | /* 70491 */ GIR_EraseRootFromParent_Done, |
| 25591 | /* 70492 */ // Label 1474: @70492 |
| 25592 | /* 70492 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(70582), // Rule ID 4322 // |
| 25593 | /* 70497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 25594 | /* 70502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25595 | /* 70505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25596 | /* 70508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25597 | /* 70511 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25598 | /* 70514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25599 | /* 70518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25600 | /* 70522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25601 | /* 70526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25602 | /* 70530 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 25603 | /* 70534 */ // MIs[1] Operand 1 |
| 25604 | /* 70534 */ // No operand predicates |
| 25605 | /* 70534 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25606 | /* 70538 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25607 | /* 70540 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3949:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 25608 | /* 70540 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25609 | /* 70543 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25610 | /* 70547 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25611 | /* 70552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16), |
| 25612 | /* 70555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25613 | /* 70557 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25614 | /* 70559 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25615 | /* 70562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25616 | /* 70565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25617 | /* 70571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25618 | /* 70577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25619 | /* 70580 */ GIR_RootConstrainSelectedInstOperands, |
| 25620 | /* 70581 */ // GIR_Coverage, 4322, |
| 25621 | /* 70581 */ GIR_EraseRootFromParent_Done, |
| 25622 | /* 70582 */ // Label 1475: @70582 |
| 25623 | /* 70582 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(70672), // Rule ID 4324 // |
| 25624 | /* 70587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 25625 | /* 70592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25626 | /* 70595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25627 | /* 70598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25628 | /* 70601 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25629 | /* 70604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25630 | /* 70608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25631 | /* 70612 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25632 | /* 70616 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25633 | /* 70620 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 25634 | /* 70624 */ // MIs[1] Operand 1 |
| 25635 | /* 70624 */ // No operand predicates |
| 25636 | /* 70624 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25637 | /* 70628 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25638 | /* 70630 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3949:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 25639 | /* 70630 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25640 | /* 70633 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25641 | /* 70637 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25642 | /* 70642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32), |
| 25643 | /* 70645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25644 | /* 70647 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25645 | /* 70649 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25646 | /* 70652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25647 | /* 70655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25648 | /* 70661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25649 | /* 70667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25650 | /* 70670 */ GIR_RootConstrainSelectedInstOperands, |
| 25651 | /* 70671 */ // GIR_Coverage, 4324, |
| 25652 | /* 70671 */ GIR_EraseRootFromParent_Done, |
| 25653 | /* 70672 */ // Label 1476: @70672 |
| 25654 | /* 70672 */ GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(70762), // Rule ID 4326 // |
| 25655 | /* 70677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 25656 | /* 70682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25657 | /* 70685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25658 | /* 70688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25659 | /* 70691 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25660 | /* 70694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25661 | /* 70698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25662 | /* 70702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 25663 | /* 70706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25664 | /* 70710 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 25665 | /* 70714 */ // MIs[1] Operand 1 |
| 25666 | /* 70714 */ // No operand predicates |
| 25667 | /* 70714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25668 | /* 70718 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25669 | /* 70720 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3949:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 25670 | /* 70720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25671 | /* 70723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25672 | /* 70727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25673 | /* 70732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32), |
| 25674 | /* 70735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25675 | /* 70737 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25676 | /* 70739 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25677 | /* 70742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25678 | /* 70745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25679 | /* 70751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25680 | /* 70757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25681 | /* 70760 */ GIR_RootConstrainSelectedInstOperands, |
| 25682 | /* 70761 */ // GIR_Coverage, 4326, |
| 25683 | /* 70761 */ GIR_EraseRootFromParent_Done, |
| 25684 | /* 70762 */ // Label 1477: @70762 |
| 25685 | /* 70762 */ GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(70851), // Rule ID 4472 // |
| 25686 | /* 70767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25687 | /* 70770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25688 | /* 70775 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25689 | /* 70778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25690 | /* 70781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25691 | /* 70784 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25692 | /* 70787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25693 | /* 70791 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 25694 | /* 70795 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25695 | /* 70799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25696 | /* 70803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25697 | /* 70807 */ // MIs[1] Operand 1 |
| 25698 | /* 70807 */ // No operand predicates |
| 25699 | /* 70807 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25700 | /* 70809 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3858:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25701 | /* 70809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25702 | /* 70812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25703 | /* 70816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25704 | /* 70821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix), |
| 25705 | /* 70824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25706 | /* 70826 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25707 | /* 70828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25708 | /* 70831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25709 | /* 70834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25710 | /* 70840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25711 | /* 70846 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25712 | /* 70849 */ GIR_RootConstrainSelectedInstOperands, |
| 25713 | /* 70850 */ // GIR_Coverage, 4472, |
| 25714 | /* 70850 */ GIR_EraseRootFromParent_Done, |
| 25715 | /* 70851 */ // Label 1478: @70851 |
| 25716 | /* 70851 */ GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(70940), // Rule ID 4474 // |
| 25717 | /* 70856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25718 | /* 70859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25719 | /* 70864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25720 | /* 70867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25721 | /* 70870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25722 | /* 70873 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25723 | /* 70876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25724 | /* 70880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 25725 | /* 70884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25726 | /* 70888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25727 | /* 70892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25728 | /* 70896 */ // MIs[1] Operand 1 |
| 25729 | /* 70896 */ // No operand predicates |
| 25730 | /* 70896 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25731 | /* 70898 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3858:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25732 | /* 70898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25733 | /* 70901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25734 | /* 70905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25735 | /* 70910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix), |
| 25736 | /* 70913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25737 | /* 70915 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25738 | /* 70917 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25739 | /* 70920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25740 | /* 70923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25741 | /* 70929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25742 | /* 70935 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25743 | /* 70938 */ GIR_RootConstrainSelectedInstOperands, |
| 25744 | /* 70939 */ // GIR_Coverage, 4474, |
| 25745 | /* 70939 */ GIR_EraseRootFromParent_Done, |
| 25746 | /* 70940 */ // Label 1479: @70940 |
| 25747 | /* 70940 */ GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(71029), // Rule ID 4476 // |
| 25748 | /* 70945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25749 | /* 70948 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25750 | /* 70953 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25751 | /* 70956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25752 | /* 70959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25753 | /* 70962 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25754 | /* 70965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25755 | /* 70969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25756 | /* 70973 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25757 | /* 70977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25758 | /* 70981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25759 | /* 70985 */ // MIs[1] Operand 1 |
| 25760 | /* 70985 */ // No operand predicates |
| 25761 | /* 70985 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25762 | /* 70987 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3858:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25763 | /* 70987 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25764 | /* 70990 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25765 | /* 70994 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25766 | /* 70999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix), |
| 25767 | /* 71002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25768 | /* 71004 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25769 | /* 71006 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25770 | /* 71009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25771 | /* 71012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25772 | /* 71018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25773 | /* 71024 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25774 | /* 71027 */ GIR_RootConstrainSelectedInstOperands, |
| 25775 | /* 71028 */ // GIR_Coverage, 4476, |
| 25776 | /* 71028 */ GIR_EraseRootFromParent_Done, |
| 25777 | /* 71029 */ // Label 1480: @71029 |
| 25778 | /* 71029 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(71118), // Rule ID 4478 // |
| 25779 | /* 71034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25780 | /* 71037 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25781 | /* 71042 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25782 | /* 71045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25783 | /* 71048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25784 | /* 71051 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25785 | /* 71054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25786 | /* 71058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25787 | /* 71062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25788 | /* 71066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25789 | /* 71070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25790 | /* 71074 */ // MIs[1] Operand 1 |
| 25791 | /* 71074 */ // No operand predicates |
| 25792 | /* 71074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25793 | /* 71076 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3858:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25794 | /* 71076 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25795 | /* 71079 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25796 | /* 71083 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25797 | /* 71088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix), |
| 25798 | /* 71091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25799 | /* 71093 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25800 | /* 71095 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25801 | /* 71098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25802 | /* 71101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25803 | /* 71107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25804 | /* 71113 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25805 | /* 71116 */ GIR_RootConstrainSelectedInstOperands, |
| 25806 | /* 71117 */ // GIR_Coverage, 4478, |
| 25807 | /* 71117 */ GIR_EraseRootFromParent_Done, |
| 25808 | /* 71118 */ // Label 1481: @71118 |
| 25809 | /* 71118 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(71207), // Rule ID 4480 // |
| 25810 | /* 71123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25811 | /* 71126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25812 | /* 71131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25813 | /* 71134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25814 | /* 71137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25815 | /* 71140 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25816 | /* 71143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25817 | /* 71147 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 25818 | /* 71151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25819 | /* 71155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25820 | /* 71159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25821 | /* 71163 */ // MIs[1] Operand 1 |
| 25822 | /* 71163 */ // No operand predicates |
| 25823 | /* 71163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25824 | /* 71165 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3858:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25825 | /* 71165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25826 | /* 71168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25827 | /* 71172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25828 | /* 71177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix), |
| 25829 | /* 71180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25830 | /* 71182 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25831 | /* 71184 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25832 | /* 71187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25833 | /* 71190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25834 | /* 71196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25835 | /* 71202 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25836 | /* 71205 */ GIR_RootConstrainSelectedInstOperands, |
| 25837 | /* 71206 */ // GIR_Coverage, 4480, |
| 25838 | /* 71206 */ GIR_EraseRootFromParent_Done, |
| 25839 | /* 71207 */ // Label 1482: @71207 |
| 25840 | /* 71207 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(71296), // Rule ID 4482 // |
| 25841 | /* 71212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25842 | /* 71215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25843 | /* 71220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25844 | /* 71223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25845 | /* 71226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25846 | /* 71229 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25847 | /* 71232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25848 | /* 71236 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 25849 | /* 71240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25850 | /* 71244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25851 | /* 71248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25852 | /* 71252 */ // MIs[1] Operand 1 |
| 25853 | /* 71252 */ // No operand predicates |
| 25854 | /* 71252 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25855 | /* 71254 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3858:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25856 | /* 71254 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25857 | /* 71257 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25858 | /* 71261 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25859 | /* 71266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix), |
| 25860 | /* 71269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25861 | /* 71271 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25862 | /* 71273 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25863 | /* 71276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25864 | /* 71279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25865 | /* 71285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25866 | /* 71291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25867 | /* 71294 */ GIR_RootConstrainSelectedInstOperands, |
| 25868 | /* 71295 */ // GIR_Coverage, 4482, |
| 25869 | /* 71295 */ GIR_EraseRootFromParent_Done, |
| 25870 | /* 71296 */ // Label 1483: @71296 |
| 25871 | /* 71296 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(71385), // Rule ID 4484 // |
| 25872 | /* 71301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25873 | /* 71304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25874 | /* 71309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25875 | /* 71312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25876 | /* 71315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25877 | /* 71318 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25878 | /* 71321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25879 | /* 71325 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25880 | /* 71329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25881 | /* 71333 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25882 | /* 71337 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25883 | /* 71341 */ // MIs[1] Operand 1 |
| 25884 | /* 71341 */ // No operand predicates |
| 25885 | /* 71341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25886 | /* 71343 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3858:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25887 | /* 71343 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25888 | /* 71346 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25889 | /* 71350 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25890 | /* 71355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix), |
| 25891 | /* 71358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25892 | /* 71360 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25893 | /* 71362 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25894 | /* 71365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25895 | /* 71368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25896 | /* 71374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25897 | /* 71380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25898 | /* 71383 */ GIR_RootConstrainSelectedInstOperands, |
| 25899 | /* 71384 */ // GIR_Coverage, 4484, |
| 25900 | /* 71384 */ GIR_EraseRootFromParent_Done, |
| 25901 | /* 71385 */ // Label 1484: @71385 |
| 25902 | /* 71385 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(71474), // Rule ID 4486 // |
| 25903 | /* 71390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25904 | /* 71393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 25905 | /* 71398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25906 | /* 71401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25907 | /* 71404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25908 | /* 71407 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25909 | /* 71410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25910 | /* 71414 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25911 | /* 71418 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25912 | /* 71422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25913 | /* 71426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25914 | /* 71430 */ // MIs[1] Operand 1 |
| 25915 | /* 71430 */ // No operand predicates |
| 25916 | /* 71430 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25917 | /* 71432 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3858:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25918 | /* 71432 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25919 | /* 71435 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25920 | /* 71439 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25921 | /* 71444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix), |
| 25922 | /* 71447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25923 | /* 71449 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25924 | /* 71451 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25925 | /* 71454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25926 | /* 71457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25927 | /* 71463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25928 | /* 71469 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25929 | /* 71472 */ GIR_RootConstrainSelectedInstOperands, |
| 25930 | /* 71473 */ // GIR_Coverage, 4486, |
| 25931 | /* 71473 */ GIR_EraseRootFromParent_Done, |
| 25932 | /* 71474 */ // Label 1485: @71474 |
| 25933 | /* 71474 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(71541), // Rule ID 3497 // |
| 25934 | /* 71479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25935 | /* 71482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 25936 | /* 71487 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25937 | /* 71490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25938 | /* 71493 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25939 | /* 71496 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25940 | /* 71499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25941 | /* 71503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25942 | /* 71507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25943 | /* 71511 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25944 | /* 71515 */ // (intrinsic_wo_chain:{ *:[i32] } 3804:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25945 | /* 71515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 25946 | /* 71518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25947 | /* 71520 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25948 | /* 71522 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25949 | /* 71524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25950 | /* 71527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25951 | /* 71533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25952 | /* 71539 */ GIR_RootConstrainSelectedInstOperands, |
| 25953 | /* 71540 */ // GIR_Coverage, 3497, |
| 25954 | /* 71540 */ GIR_EraseRootFromParent_Done, |
| 25955 | /* 71541 */ // Label 1486: @71541 |
| 25956 | /* 71541 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(71608), // Rule ID 3499 // |
| 25957 | /* 71546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25958 | /* 71549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 25959 | /* 71554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25960 | /* 71557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25961 | /* 71560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25962 | /* 71563 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25963 | /* 71566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25964 | /* 71570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25965 | /* 71574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25966 | /* 71578 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25967 | /* 71582 */ // (intrinsic_wo_chain:{ *:[i32] } 3804:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25968 | /* 71582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 25969 | /* 71585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25970 | /* 71587 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25971 | /* 71589 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25972 | /* 71591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25973 | /* 71594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25974 | /* 71600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25975 | /* 71606 */ GIR_RootConstrainSelectedInstOperands, |
| 25976 | /* 71607 */ // GIR_Coverage, 3499, |
| 25977 | /* 71607 */ GIR_EraseRootFromParent_Done, |
| 25978 | /* 71608 */ // Label 1487: @71608 |
| 25979 | /* 71608 */ GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(71675), // Rule ID 3501 // |
| 25980 | /* 71613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25981 | /* 71616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 25982 | /* 71621 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25983 | /* 71624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25984 | /* 71627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25985 | /* 71630 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25986 | /* 71633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25987 | /* 71637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25988 | /* 71641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25989 | /* 71645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25990 | /* 71649 */ // (intrinsic_wo_chain:{ *:[i32] } 3804:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25991 | /* 71649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 25992 | /* 71652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25993 | /* 71654 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25994 | /* 71656 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25995 | /* 71658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25996 | /* 71661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25997 | /* 71667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25998 | /* 71673 */ GIR_RootConstrainSelectedInstOperands, |
| 25999 | /* 71674 */ // GIR_Coverage, 3501, |
| 26000 | /* 71674 */ GIR_EraseRootFromParent_Done, |
| 26001 | /* 71675 */ // Label 1488: @71675 |
| 26002 | /* 71675 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(71742), // Rule ID 3503 // |
| 26003 | /* 71680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26004 | /* 71683 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 26005 | /* 71688 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26006 | /* 71691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26007 | /* 71694 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26008 | /* 71697 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26009 | /* 71700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26010 | /* 71704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26011 | /* 71708 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26012 | /* 71712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26013 | /* 71716 */ // (intrinsic_wo_chain:{ *:[i32] } 3804:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 26014 | /* 71716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 26015 | /* 71719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26016 | /* 71721 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26017 | /* 71723 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26018 | /* 71725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26019 | /* 71728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26020 | /* 71734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26021 | /* 71740 */ GIR_RootConstrainSelectedInstOperands, |
| 26022 | /* 71741 */ // GIR_Coverage, 3503, |
| 26023 | /* 71741 */ GIR_EraseRootFromParent_Done, |
| 26024 | /* 71742 */ // Label 1489: @71742 |
| 26025 | /* 71742 */ GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(71809), // Rule ID 3505 // |
| 26026 | /* 71747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26027 | /* 71750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 26028 | /* 71755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26029 | /* 71758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26030 | /* 71761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26031 | /* 71764 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26032 | /* 71767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26033 | /* 71771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26034 | /* 71775 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26035 | /* 71779 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26036 | /* 71783 */ // (intrinsic_wo_chain:{ *:[i32] } 3804:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 26037 | /* 71783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 26038 | /* 71786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26039 | /* 71788 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26040 | /* 71790 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26041 | /* 71792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26042 | /* 71795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26043 | /* 71801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26044 | /* 71807 */ GIR_RootConstrainSelectedInstOperands, |
| 26045 | /* 71808 */ // GIR_Coverage, 3505, |
| 26046 | /* 71808 */ GIR_EraseRootFromParent_Done, |
| 26047 | /* 71809 */ // Label 1490: @71809 |
| 26048 | /* 71809 */ GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(71876), // Rule ID 3507 // |
| 26049 | /* 71814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26050 | /* 71817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 26051 | /* 71822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26052 | /* 71825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26053 | /* 71828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26054 | /* 71831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26055 | /* 71834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26056 | /* 71838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26057 | /* 71842 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26058 | /* 71846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26059 | /* 71850 */ // (intrinsic_wo_chain:{ *:[i32] } 3804:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 26060 | /* 71850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 26061 | /* 71853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26062 | /* 71855 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26063 | /* 71857 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26064 | /* 71859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26065 | /* 71862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26066 | /* 71868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26067 | /* 71874 */ GIR_RootConstrainSelectedInstOperands, |
| 26068 | /* 71875 */ // GIR_Coverage, 3507, |
| 26069 | /* 71875 */ GIR_EraseRootFromParent_Done, |
| 26070 | /* 71876 */ // Label 1491: @71876 |
| 26071 | /* 71876 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(71943), // Rule ID 3509 // |
| 26072 | /* 71881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26073 | /* 71884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 26074 | /* 71889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26075 | /* 71892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26076 | /* 71895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26077 | /* 71898 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26078 | /* 71901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26079 | /* 71905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26080 | /* 71909 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26081 | /* 71913 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26082 | /* 71917 */ // (intrinsic_wo_chain:{ *:[i32] } 3795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 26083 | /* 71917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 26084 | /* 71920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26085 | /* 71922 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26086 | /* 71924 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26087 | /* 71926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26088 | /* 71929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26089 | /* 71935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26090 | /* 71941 */ GIR_RootConstrainSelectedInstOperands, |
| 26091 | /* 71942 */ // GIR_Coverage, 3509, |
| 26092 | /* 71942 */ GIR_EraseRootFromParent_Done, |
| 26093 | /* 71943 */ // Label 1492: @71943 |
| 26094 | /* 71943 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(72010), // Rule ID 3511 // |
| 26095 | /* 71948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26096 | /* 71951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 26097 | /* 71956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26098 | /* 71959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26099 | /* 71962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26100 | /* 71965 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26101 | /* 71968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26102 | /* 71972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26103 | /* 71976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26104 | /* 71980 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26105 | /* 71984 */ // (intrinsic_wo_chain:{ *:[i32] } 3795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 26106 | /* 71984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 26107 | /* 71987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26108 | /* 71989 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26109 | /* 71991 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26110 | /* 71993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26111 | /* 71996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26112 | /* 72002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26113 | /* 72008 */ GIR_RootConstrainSelectedInstOperands, |
| 26114 | /* 72009 */ // GIR_Coverage, 3511, |
| 26115 | /* 72009 */ GIR_EraseRootFromParent_Done, |
| 26116 | /* 72010 */ // Label 1493: @72010 |
| 26117 | /* 72010 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(72077), // Rule ID 3513 // |
| 26118 | /* 72015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26119 | /* 72018 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 26120 | /* 72023 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26121 | /* 72026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26122 | /* 72029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26123 | /* 72032 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26124 | /* 72035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26125 | /* 72039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26126 | /* 72043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26127 | /* 72047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26128 | /* 72051 */ // (intrinsic_wo_chain:{ *:[i32] } 3795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 26129 | /* 72051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 26130 | /* 72054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26131 | /* 72056 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26132 | /* 72058 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26133 | /* 72060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26134 | /* 72063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26135 | /* 72069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26136 | /* 72075 */ GIR_RootConstrainSelectedInstOperands, |
| 26137 | /* 72076 */ // GIR_Coverage, 3513, |
| 26138 | /* 72076 */ GIR_EraseRootFromParent_Done, |
| 26139 | /* 72077 */ // Label 1494: @72077 |
| 26140 | /* 72077 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(72144), // Rule ID 3515 // |
| 26141 | /* 72082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26142 | /* 72085 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 26143 | /* 72090 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26144 | /* 72093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26145 | /* 72096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26146 | /* 72099 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26147 | /* 72102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26148 | /* 72106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26149 | /* 72110 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26150 | /* 72114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26151 | /* 72118 */ // (intrinsic_wo_chain:{ *:[i32] } 3795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 26152 | /* 72118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 26153 | /* 72121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26154 | /* 72123 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26155 | /* 72125 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26156 | /* 72127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26157 | /* 72130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26158 | /* 72136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26159 | /* 72142 */ GIR_RootConstrainSelectedInstOperands, |
| 26160 | /* 72143 */ // GIR_Coverage, 3515, |
| 26161 | /* 72143 */ GIR_EraseRootFromParent_Done, |
| 26162 | /* 72144 */ // Label 1495: @72144 |
| 26163 | /* 72144 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(72211), // Rule ID 3517 // |
| 26164 | /* 72149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26165 | /* 72152 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 26166 | /* 72157 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26167 | /* 72160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26168 | /* 72163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26169 | /* 72166 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26170 | /* 72169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26171 | /* 72173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26172 | /* 72177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26173 | /* 72181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26174 | /* 72185 */ // (intrinsic_wo_chain:{ *:[i32] } 3795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 26175 | /* 72185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 26176 | /* 72188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26177 | /* 72190 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26178 | /* 72192 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26179 | /* 72194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26180 | /* 72197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26181 | /* 72203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26182 | /* 72209 */ GIR_RootConstrainSelectedInstOperands, |
| 26183 | /* 72210 */ // GIR_Coverage, 3517, |
| 26184 | /* 72210 */ GIR_EraseRootFromParent_Done, |
| 26185 | /* 72211 */ // Label 1496: @72211 |
| 26186 | /* 72211 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(72278), // Rule ID 3519 // |
| 26187 | /* 72216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26188 | /* 72219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 26189 | /* 72224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26190 | /* 72227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26191 | /* 72230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26192 | /* 72233 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26193 | /* 72236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26194 | /* 72240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26195 | /* 72244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26196 | /* 72248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26197 | /* 72252 */ // (intrinsic_wo_chain:{ *:[i32] } 3795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 26198 | /* 72252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 26199 | /* 72255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 26200 | /* 72257 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 26201 | /* 72259 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 26202 | /* 72261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26203 | /* 72264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26204 | /* 72270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26205 | /* 72276 */ GIR_RootConstrainSelectedInstOperands, |
| 26206 | /* 72277 */ // GIR_Coverage, 3519, |
| 26207 | /* 72277 */ GIR_EraseRootFromParent_Done, |
| 26208 | /* 72278 */ // Label 1497: @72278 |
| 26209 | /* 72278 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(72360), // Rule ID 3930 // |
| 26210 | /* 72283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26211 | /* 72286 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26212 | /* 72291 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26213 | /* 72294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26214 | /* 72297 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26215 | /* 72300 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26216 | /* 72303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26217 | /* 72307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26218 | /* 72311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26219 | /* 72315 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26220 | /* 72319 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3841:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26221 | /* 72319 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26222 | /* 72322 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26223 | /* 72326 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26224 | /* 72331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 26225 | /* 72334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26226 | /* 72336 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26227 | /* 72338 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26228 | /* 72340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26229 | /* 72343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26230 | /* 72349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26231 | /* 72355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26232 | /* 72358 */ GIR_RootConstrainSelectedInstOperands, |
| 26233 | /* 72359 */ // GIR_Coverage, 3930, |
| 26234 | /* 72359 */ GIR_EraseRootFromParent_Done, |
| 26235 | /* 72360 */ // Label 1498: @72360 |
| 26236 | /* 72360 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(72442), // Rule ID 3937 // |
| 26237 | /* 72365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26238 | /* 72368 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26239 | /* 72373 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26240 | /* 72376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26241 | /* 72379 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26242 | /* 72382 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26243 | /* 72385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26244 | /* 72389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26245 | /* 72393 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26246 | /* 72397 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26247 | /* 72401 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3841:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26248 | /* 72401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26249 | /* 72404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26250 | /* 72408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26251 | /* 72413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 26252 | /* 72416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26253 | /* 72418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26254 | /* 72420 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26255 | /* 72422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26256 | /* 72425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26257 | /* 72431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26258 | /* 72437 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26259 | /* 72440 */ GIR_RootConstrainSelectedInstOperands, |
| 26260 | /* 72441 */ // GIR_Coverage, 3937, |
| 26261 | /* 72441 */ GIR_EraseRootFromParent_Done, |
| 26262 | /* 72442 */ // Label 1499: @72442 |
| 26263 | /* 72442 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(72524), // Rule ID 3941 // |
| 26264 | /* 72447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26265 | /* 72450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26266 | /* 72455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26267 | /* 72458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26268 | /* 72461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26269 | /* 72464 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26270 | /* 72467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26271 | /* 72471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26272 | /* 72475 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26273 | /* 72479 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26274 | /* 72483 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3841:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26275 | /* 72483 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26276 | /* 72486 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26277 | /* 72490 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26278 | /* 72495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 26279 | /* 72498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26280 | /* 72500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26281 | /* 72502 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26282 | /* 72504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26283 | /* 72507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26284 | /* 72513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26285 | /* 72519 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26286 | /* 72522 */ GIR_RootConstrainSelectedInstOperands, |
| 26287 | /* 72523 */ // GIR_Coverage, 3941, |
| 26288 | /* 72523 */ GIR_EraseRootFromParent_Done, |
| 26289 | /* 72524 */ // Label 1500: @72524 |
| 26290 | /* 72524 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(72606), // Rule ID 3945 // |
| 26291 | /* 72529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26292 | /* 72532 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26293 | /* 72537 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26294 | /* 72540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26295 | /* 72543 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26296 | /* 72546 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26297 | /* 72549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26298 | /* 72553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26299 | /* 72557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26300 | /* 72561 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26301 | /* 72565 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3841:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26302 | /* 72565 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26303 | /* 72568 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26304 | /* 72572 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26305 | /* 72577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 26306 | /* 72580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26307 | /* 72582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26308 | /* 72584 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26309 | /* 72586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26310 | /* 72589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26311 | /* 72595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26312 | /* 72601 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26313 | /* 72604 */ GIR_RootConstrainSelectedInstOperands, |
| 26314 | /* 72605 */ // GIR_Coverage, 3945, |
| 26315 | /* 72605 */ GIR_EraseRootFromParent_Done, |
| 26316 | /* 72606 */ // Label 1501: @72606 |
| 26317 | /* 72606 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(72688), // Rule ID 3949 // |
| 26318 | /* 72611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26319 | /* 72614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26320 | /* 72619 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26321 | /* 72622 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26322 | /* 72625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26323 | /* 72628 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26324 | /* 72631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26325 | /* 72635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26326 | /* 72639 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26327 | /* 72643 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26328 | /* 72647 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3841:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26329 | /* 72647 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26330 | /* 72650 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26331 | /* 72654 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26332 | /* 72659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 26333 | /* 72662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26334 | /* 72664 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26335 | /* 72666 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26336 | /* 72668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26337 | /* 72671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26338 | /* 72677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26339 | /* 72683 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26340 | /* 72686 */ GIR_RootConstrainSelectedInstOperands, |
| 26341 | /* 72687 */ // GIR_Coverage, 3949, |
| 26342 | /* 72687 */ GIR_EraseRootFromParent_Done, |
| 26343 | /* 72688 */ // Label 1502: @72688 |
| 26344 | /* 72688 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(72770), // Rule ID 3953 // |
| 26345 | /* 72693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26346 | /* 72696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26347 | /* 72701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26348 | /* 72704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26349 | /* 72707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26350 | /* 72710 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26351 | /* 72713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26352 | /* 72717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26353 | /* 72721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26354 | /* 72725 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26355 | /* 72729 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3841:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26356 | /* 72729 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26357 | /* 72732 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26358 | /* 72736 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26359 | /* 72741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 26360 | /* 72744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26361 | /* 72746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26362 | /* 72748 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26363 | /* 72750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26364 | /* 72753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26365 | /* 72759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26366 | /* 72765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26367 | /* 72768 */ GIR_RootConstrainSelectedInstOperands, |
| 26368 | /* 72769 */ // GIR_Coverage, 3953, |
| 26369 | /* 72769 */ GIR_EraseRootFromParent_Done, |
| 26370 | /* 72770 */ // Label 1503: @72770 |
| 26371 | /* 72770 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(72852), // Rule ID 3954 // |
| 26372 | /* 72775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26373 | /* 72778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 26374 | /* 72783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26375 | /* 72786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26376 | /* 72789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26377 | /* 72792 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26378 | /* 72795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26379 | /* 72799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26380 | /* 72803 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26381 | /* 72807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26382 | /* 72811 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26383 | /* 72811 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26384 | /* 72814 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26385 | /* 72818 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26386 | /* 72823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 26387 | /* 72826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26388 | /* 72828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26389 | /* 72830 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26390 | /* 72832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26391 | /* 72835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26392 | /* 72841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26393 | /* 72847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26394 | /* 72850 */ GIR_RootConstrainSelectedInstOperands, |
| 26395 | /* 72851 */ // GIR_Coverage, 3954, |
| 26396 | /* 72851 */ GIR_EraseRootFromParent_Done, |
| 26397 | /* 72852 */ // Label 1504: @72852 |
| 26398 | /* 72852 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(72934), // Rule ID 3961 // |
| 26399 | /* 72857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26400 | /* 72860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 26401 | /* 72865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26402 | /* 72868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26403 | /* 72871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26404 | /* 72874 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26405 | /* 72877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26406 | /* 72881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26407 | /* 72885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26408 | /* 72889 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26409 | /* 72893 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26410 | /* 72893 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26411 | /* 72896 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26412 | /* 72900 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26413 | /* 72905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 26414 | /* 72908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26415 | /* 72910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26416 | /* 72912 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26417 | /* 72914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26418 | /* 72917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26419 | /* 72923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26420 | /* 72929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26421 | /* 72932 */ GIR_RootConstrainSelectedInstOperands, |
| 26422 | /* 72933 */ // GIR_Coverage, 3961, |
| 26423 | /* 72933 */ GIR_EraseRootFromParent_Done, |
| 26424 | /* 72934 */ // Label 1505: @72934 |
| 26425 | /* 72934 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(73016), // Rule ID 3965 // |
| 26426 | /* 72939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26427 | /* 72942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 26428 | /* 72947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26429 | /* 72950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26430 | /* 72953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26431 | /* 72956 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26432 | /* 72959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26433 | /* 72963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26434 | /* 72967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26435 | /* 72971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26436 | /* 72975 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26437 | /* 72975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26438 | /* 72978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26439 | /* 72982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26440 | /* 72987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 26441 | /* 72990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26442 | /* 72992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26443 | /* 72994 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26444 | /* 72996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26445 | /* 72999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26446 | /* 73005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26447 | /* 73011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26448 | /* 73014 */ GIR_RootConstrainSelectedInstOperands, |
| 26449 | /* 73015 */ // GIR_Coverage, 3965, |
| 26450 | /* 73015 */ GIR_EraseRootFromParent_Done, |
| 26451 | /* 73016 */ // Label 1506: @73016 |
| 26452 | /* 73016 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(73098), // Rule ID 3969 // |
| 26453 | /* 73021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26454 | /* 73024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 26455 | /* 73029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26456 | /* 73032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26457 | /* 73035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26458 | /* 73038 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26459 | /* 73041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26460 | /* 73045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26461 | /* 73049 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26462 | /* 73053 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26463 | /* 73057 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26464 | /* 73057 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26465 | /* 73060 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26466 | /* 73064 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26467 | /* 73069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 26468 | /* 73072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26469 | /* 73074 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26470 | /* 73076 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26471 | /* 73078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26472 | /* 73081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26473 | /* 73087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26474 | /* 73093 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26475 | /* 73096 */ GIR_RootConstrainSelectedInstOperands, |
| 26476 | /* 73097 */ // GIR_Coverage, 3969, |
| 26477 | /* 73097 */ GIR_EraseRootFromParent_Done, |
| 26478 | /* 73098 */ // Label 1507: @73098 |
| 26479 | /* 73098 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(73180), // Rule ID 3973 // |
| 26480 | /* 73103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26481 | /* 73106 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 26482 | /* 73111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26483 | /* 73114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26484 | /* 73117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26485 | /* 73120 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26486 | /* 73123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26487 | /* 73127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26488 | /* 73131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26489 | /* 73135 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26490 | /* 73139 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26491 | /* 73139 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26492 | /* 73142 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26493 | /* 73146 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26494 | /* 73151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 26495 | /* 73154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26496 | /* 73156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26497 | /* 73158 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26498 | /* 73160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26499 | /* 73163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26500 | /* 73169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26501 | /* 73175 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26502 | /* 73178 */ GIR_RootConstrainSelectedInstOperands, |
| 26503 | /* 73179 */ // GIR_Coverage, 3973, |
| 26504 | /* 73179 */ GIR_EraseRootFromParent_Done, |
| 26505 | /* 73180 */ // Label 1508: @73180 |
| 26506 | /* 73180 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(73262), // Rule ID 3977 // |
| 26507 | /* 73185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26508 | /* 73188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 26509 | /* 73193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26510 | /* 73196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26511 | /* 73199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26512 | /* 73202 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26513 | /* 73205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26514 | /* 73209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26515 | /* 73213 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26516 | /* 73217 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26517 | /* 73221 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26518 | /* 73221 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26519 | /* 73224 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26520 | /* 73228 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26521 | /* 73233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 26522 | /* 73236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26523 | /* 73238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26524 | /* 73240 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26525 | /* 73242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26526 | /* 73245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26527 | /* 73251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26528 | /* 73257 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26529 | /* 73260 */ GIR_RootConstrainSelectedInstOperands, |
| 26530 | /* 73261 */ // GIR_Coverage, 3977, |
| 26531 | /* 73261 */ GIR_EraseRootFromParent_Done, |
| 26532 | /* 73262 */ // Label 1509: @73262 |
| 26533 | /* 73262 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(73344), // Rule ID 3978 // |
| 26534 | /* 73267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26535 | /* 73270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 26536 | /* 73275 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26537 | /* 73278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26538 | /* 73281 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26539 | /* 73284 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26540 | /* 73287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26541 | /* 73291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26542 | /* 73295 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26543 | /* 73299 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26544 | /* 73303 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3879:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26545 | /* 73303 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26546 | /* 73306 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26547 | /* 73310 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26548 | /* 73315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 26549 | /* 73318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26550 | /* 73320 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26551 | /* 73322 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26552 | /* 73324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26553 | /* 73327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26554 | /* 73333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26555 | /* 73339 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26556 | /* 73342 */ GIR_RootConstrainSelectedInstOperands, |
| 26557 | /* 73343 */ // GIR_Coverage, 3978, |
| 26558 | /* 73343 */ GIR_EraseRootFromParent_Done, |
| 26559 | /* 73344 */ // Label 1510: @73344 |
| 26560 | /* 73344 */ GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(73426), // Rule ID 3985 // |
| 26561 | /* 73349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26562 | /* 73352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 26563 | /* 73357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26564 | /* 73360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26565 | /* 73363 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26566 | /* 73366 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26567 | /* 73369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26568 | /* 73373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26569 | /* 73377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26570 | /* 73381 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26571 | /* 73385 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3879:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26572 | /* 73385 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26573 | /* 73388 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26574 | /* 73392 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26575 | /* 73397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 26576 | /* 73400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26577 | /* 73402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26578 | /* 73404 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26579 | /* 73406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26580 | /* 73409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26581 | /* 73415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26582 | /* 73421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26583 | /* 73424 */ GIR_RootConstrainSelectedInstOperands, |
| 26584 | /* 73425 */ // GIR_Coverage, 3985, |
| 26585 | /* 73425 */ GIR_EraseRootFromParent_Done, |
| 26586 | /* 73426 */ // Label 1511: @73426 |
| 26587 | /* 73426 */ GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(73508), // Rule ID 3989 // |
| 26588 | /* 73431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26589 | /* 73434 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 26590 | /* 73439 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26591 | /* 73442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26592 | /* 73445 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26593 | /* 73448 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26594 | /* 73451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26595 | /* 73455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26596 | /* 73459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26597 | /* 73463 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26598 | /* 73467 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3879:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26599 | /* 73467 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26600 | /* 73470 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26601 | /* 73474 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26602 | /* 73479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 26603 | /* 73482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26604 | /* 73484 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26605 | /* 73486 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26606 | /* 73488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26607 | /* 73491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26608 | /* 73497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26609 | /* 73503 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26610 | /* 73506 */ GIR_RootConstrainSelectedInstOperands, |
| 26611 | /* 73507 */ // GIR_Coverage, 3989, |
| 26612 | /* 73507 */ GIR_EraseRootFromParent_Done, |
| 26613 | /* 73508 */ // Label 1512: @73508 |
| 26614 | /* 73508 */ GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(73590), // Rule ID 3993 // |
| 26615 | /* 73513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26616 | /* 73516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 26617 | /* 73521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26618 | /* 73524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26619 | /* 73527 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26620 | /* 73530 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26621 | /* 73533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26622 | /* 73537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26623 | /* 73541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26624 | /* 73545 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26625 | /* 73549 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3879:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26626 | /* 73549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26627 | /* 73552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26628 | /* 73556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26629 | /* 73561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 26630 | /* 73564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26631 | /* 73566 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26632 | /* 73568 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26633 | /* 73570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26634 | /* 73573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26635 | /* 73579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26636 | /* 73585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26637 | /* 73588 */ GIR_RootConstrainSelectedInstOperands, |
| 26638 | /* 73589 */ // GIR_Coverage, 3993, |
| 26639 | /* 73589 */ GIR_EraseRootFromParent_Done, |
| 26640 | /* 73590 */ // Label 1513: @73590 |
| 26641 | /* 73590 */ GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(73672), // Rule ID 3997 // |
| 26642 | /* 73595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26643 | /* 73598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 26644 | /* 73603 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26645 | /* 73606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26646 | /* 73609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26647 | /* 73612 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26648 | /* 73615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26649 | /* 73619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26650 | /* 73623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26651 | /* 73627 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26652 | /* 73631 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3879:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26653 | /* 73631 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26654 | /* 73634 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26655 | /* 73638 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26656 | /* 73643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 26657 | /* 73646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26658 | /* 73648 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26659 | /* 73650 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26660 | /* 73652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26661 | /* 73655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26662 | /* 73661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26663 | /* 73667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26664 | /* 73670 */ GIR_RootConstrainSelectedInstOperands, |
| 26665 | /* 73671 */ // GIR_Coverage, 3997, |
| 26666 | /* 73671 */ GIR_EraseRootFromParent_Done, |
| 26667 | /* 73672 */ // Label 1514: @73672 |
| 26668 | /* 73672 */ GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(73754), // Rule ID 4001 // |
| 26669 | /* 73677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26670 | /* 73680 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 26671 | /* 73685 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26672 | /* 73688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26673 | /* 73691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26674 | /* 73694 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26675 | /* 73697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26676 | /* 73701 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26677 | /* 73705 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26678 | /* 73709 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26679 | /* 73713 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3879:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26680 | /* 73713 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26681 | /* 73716 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26682 | /* 73720 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26683 | /* 73725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 26684 | /* 73728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26685 | /* 73730 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26686 | /* 73732 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26687 | /* 73734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26688 | /* 73737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26689 | /* 73743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26690 | /* 73749 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26691 | /* 73752 */ GIR_RootConstrainSelectedInstOperands, |
| 26692 | /* 73753 */ // GIR_Coverage, 4001, |
| 26693 | /* 73753 */ GIR_EraseRootFromParent_Done, |
| 26694 | /* 73754 */ // Label 1515: @73754 |
| 26695 | /* 73754 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(73836), // Rule ID 4002 // |
| 26696 | /* 73759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26697 | /* 73762 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 26698 | /* 73767 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26699 | /* 73770 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26700 | /* 73773 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26701 | /* 73776 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26702 | /* 73779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26703 | /* 73783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26704 | /* 73787 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26705 | /* 73791 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26706 | /* 73795 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3880:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26707 | /* 73795 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26708 | /* 73798 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26709 | /* 73802 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26710 | /* 73807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8), |
| 26711 | /* 73810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26712 | /* 73812 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26713 | /* 73814 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26714 | /* 73816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26715 | /* 73819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26716 | /* 73825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26717 | /* 73831 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26718 | /* 73834 */ GIR_RootConstrainSelectedInstOperands, |
| 26719 | /* 73835 */ // GIR_Coverage, 4002, |
| 26720 | /* 73835 */ GIR_EraseRootFromParent_Done, |
| 26721 | /* 73836 */ // Label 1516: @73836 |
| 26722 | /* 73836 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(73918), // Rule ID 4005 // |
| 26723 | /* 73841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26724 | /* 73844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 26725 | /* 73849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26726 | /* 73852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26727 | /* 73855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26728 | /* 73858 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26729 | /* 73861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26730 | /* 73865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26731 | /* 73869 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26732 | /* 73873 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26733 | /* 73877 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26734 | /* 73877 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26735 | /* 73880 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26736 | /* 73884 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26737 | /* 73889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16), |
| 26738 | /* 73892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26739 | /* 73894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26740 | /* 73896 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26741 | /* 73898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26742 | /* 73901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26743 | /* 73907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26744 | /* 73913 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26745 | /* 73916 */ GIR_RootConstrainSelectedInstOperands, |
| 26746 | /* 73917 */ // GIR_Coverage, 4005, |
| 26747 | /* 73917 */ GIR_EraseRootFromParent_Done, |
| 26748 | /* 73918 */ // Label 1517: @73918 |
| 26749 | /* 73918 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(74000), // Rule ID 4008 // |
| 26750 | /* 73923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26751 | /* 73926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 26752 | /* 73931 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26753 | /* 73934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26754 | /* 73937 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26755 | /* 73940 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26756 | /* 73943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26757 | /* 73947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26758 | /* 73951 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26759 | /* 73955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26760 | /* 73959 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26761 | /* 73959 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26762 | /* 73962 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26763 | /* 73966 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26764 | /* 73971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32), |
| 26765 | /* 73974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26766 | /* 73976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26767 | /* 73978 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26768 | /* 73980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26769 | /* 73983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26770 | /* 73989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26771 | /* 73995 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26772 | /* 73998 */ GIR_RootConstrainSelectedInstOperands, |
| 26773 | /* 73999 */ // GIR_Coverage, 4008, |
| 26774 | /* 73999 */ GIR_EraseRootFromParent_Done, |
| 26775 | /* 74000 */ // Label 1518: @74000 |
| 26776 | /* 74000 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(74082), // Rule ID 4011 // |
| 26777 | /* 74005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26778 | /* 74008 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 26779 | /* 74013 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26780 | /* 74016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26781 | /* 74019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26782 | /* 74022 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26783 | /* 74025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26784 | /* 74029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26785 | /* 74033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26786 | /* 74037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26787 | /* 74041 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3880:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26788 | /* 74041 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26789 | /* 74044 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26790 | /* 74048 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26791 | /* 74053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8), |
| 26792 | /* 74056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26793 | /* 74058 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26794 | /* 74060 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26795 | /* 74062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26796 | /* 74065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26797 | /* 74071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26798 | /* 74077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26799 | /* 74080 */ GIR_RootConstrainSelectedInstOperands, |
| 26800 | /* 74081 */ // GIR_Coverage, 4011, |
| 26801 | /* 74081 */ GIR_EraseRootFromParent_Done, |
| 26802 | /* 74082 */ // Label 1519: @74082 |
| 26803 | /* 74082 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(74164), // Rule ID 4014 // |
| 26804 | /* 74087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26805 | /* 74090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 26806 | /* 74095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26807 | /* 74098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26808 | /* 74101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26809 | /* 74104 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26810 | /* 74107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26811 | /* 74111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26812 | /* 74115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26813 | /* 74119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26814 | /* 74123 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26815 | /* 74123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26816 | /* 74126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26817 | /* 74130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26818 | /* 74135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16), |
| 26819 | /* 74138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26820 | /* 74140 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26821 | /* 74142 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26822 | /* 74144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26823 | /* 74147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26824 | /* 74153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26825 | /* 74159 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26826 | /* 74162 */ GIR_RootConstrainSelectedInstOperands, |
| 26827 | /* 74163 */ // GIR_Coverage, 4014, |
| 26828 | /* 74163 */ GIR_EraseRootFromParent_Done, |
| 26829 | /* 74164 */ // Label 1520: @74164 |
| 26830 | /* 74164 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(74246), // Rule ID 4017 // |
| 26831 | /* 74169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26832 | /* 74172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 26833 | /* 74177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26834 | /* 74180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26835 | /* 74183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26836 | /* 74186 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26837 | /* 74189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26838 | /* 74193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26839 | /* 74197 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26840 | /* 74201 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26841 | /* 74205 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26842 | /* 74205 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26843 | /* 74208 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26844 | /* 74212 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26845 | /* 74217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32), |
| 26846 | /* 74220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26847 | /* 74222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26848 | /* 74224 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26849 | /* 74226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26850 | /* 74229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26851 | /* 74235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26852 | /* 74241 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26853 | /* 74244 */ GIR_RootConstrainSelectedInstOperands, |
| 26854 | /* 74245 */ // GIR_Coverage, 4017, |
| 26855 | /* 74245 */ GIR_EraseRootFromParent_Done, |
| 26856 | /* 74246 */ // Label 1521: @74246 |
| 26857 | /* 74246 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(74328), // Rule ID 4466 // |
| 26858 | /* 74251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 26859 | /* 74254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26860 | /* 74259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26861 | /* 74262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26862 | /* 74265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26863 | /* 74268 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26864 | /* 74271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26865 | /* 74275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26866 | /* 74279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26867 | /* 74283 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26868 | /* 74287 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3841:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 26869 | /* 74287 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26870 | /* 74290 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26871 | /* 74294 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26872 | /* 74299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 26873 | /* 74302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26874 | /* 74304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26875 | /* 74306 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26876 | /* 74308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26877 | /* 74311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26878 | /* 74317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26879 | /* 74323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26880 | /* 74326 */ GIR_RootConstrainSelectedInstOperands, |
| 26881 | /* 74327 */ // GIR_Coverage, 4466, |
| 26882 | /* 74327 */ GIR_EraseRootFromParent_Done, |
| 26883 | /* 74328 */ // Label 1522: @74328 |
| 26884 | /* 74328 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(74410), // Rule ID 4468 // |
| 26885 | /* 74333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 26886 | /* 74336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26887 | /* 74341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26888 | /* 74344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26889 | /* 74347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26890 | /* 74350 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26891 | /* 74353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26892 | /* 74357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26893 | /* 74361 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26894 | /* 74365 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26895 | /* 74369 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3841:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 26896 | /* 74369 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26897 | /* 74372 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26898 | /* 74376 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26899 | /* 74381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 26900 | /* 74384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26901 | /* 74386 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26902 | /* 74388 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26903 | /* 74390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26904 | /* 74393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26905 | /* 74399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26906 | /* 74405 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26907 | /* 74408 */ GIR_RootConstrainSelectedInstOperands, |
| 26908 | /* 74409 */ // GIR_Coverage, 4468, |
| 26909 | /* 74409 */ GIR_EraseRootFromParent_Done, |
| 26910 | /* 74410 */ // Label 1523: @74410 |
| 26911 | /* 74410 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(74492), // Rule ID 4901 // |
| 26912 | /* 74415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26913 | /* 74418 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 26914 | /* 74423 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26915 | /* 74426 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26916 | /* 74429 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26917 | /* 74432 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26918 | /* 74435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26919 | /* 74439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26920 | /* 74443 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26921 | /* 74447 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26922 | /* 74451 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3910:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26923 | /* 74451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26924 | /* 74454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26925 | /* 74458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26926 | /* 74463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8), |
| 26927 | /* 74466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26928 | /* 74468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26929 | /* 74470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26930 | /* 74472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26931 | /* 74475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26932 | /* 74481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26933 | /* 74487 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26934 | /* 74490 */ GIR_RootConstrainSelectedInstOperands, |
| 26935 | /* 74491 */ // GIR_Coverage, 4901, |
| 26936 | /* 74491 */ GIR_EraseRootFromParent_Done, |
| 26937 | /* 74492 */ // Label 1524: @74492 |
| 26938 | /* 74492 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(74574), // Rule ID 4903 // |
| 26939 | /* 74497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26940 | /* 74500 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 26941 | /* 74505 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26942 | /* 74508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26943 | /* 74511 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26944 | /* 74514 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26945 | /* 74517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26946 | /* 74521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26947 | /* 74525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26948 | /* 74529 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26949 | /* 74533 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3910:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26950 | /* 74533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26951 | /* 74536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26952 | /* 74540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26953 | /* 74545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8), |
| 26954 | /* 74548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26955 | /* 74550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26956 | /* 74552 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26957 | /* 74554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26958 | /* 74557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26959 | /* 74563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26960 | /* 74569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26961 | /* 74572 */ GIR_RootConstrainSelectedInstOperands, |
| 26962 | /* 74573 */ // GIR_Coverage, 4903, |
| 26963 | /* 74573 */ GIR_EraseRootFromParent_Done, |
| 26964 | /* 74574 */ // Label 1525: @74574 |
| 26965 | /* 74574 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(74656), // Rule ID 4905 // |
| 26966 | /* 74579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26967 | /* 74582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 26968 | /* 74587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26969 | /* 74590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26970 | /* 74593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26971 | /* 74596 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26972 | /* 74599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26973 | /* 74603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26974 | /* 74607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26975 | /* 74611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26976 | /* 74615 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3910:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26977 | /* 74615 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26978 | /* 74618 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26979 | /* 74622 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26980 | /* 74627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16), |
| 26981 | /* 74630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26982 | /* 74632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26983 | /* 74634 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26984 | /* 74636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26985 | /* 74639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26986 | /* 74645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26987 | /* 74651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26988 | /* 74654 */ GIR_RootConstrainSelectedInstOperands, |
| 26989 | /* 74655 */ // GIR_Coverage, 4905, |
| 26990 | /* 74655 */ GIR_EraseRootFromParent_Done, |
| 26991 | /* 74656 */ // Label 1526: @74656 |
| 26992 | /* 74656 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(74738), // Rule ID 4907 // |
| 26993 | /* 74661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26994 | /* 74664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 26995 | /* 74669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26996 | /* 74672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26997 | /* 74675 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26998 | /* 74678 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26999 | /* 74681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27000 | /* 74685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27001 | /* 74689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27002 | /* 74693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27003 | /* 74697 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3910:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27004 | /* 74697 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27005 | /* 74700 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27006 | /* 74704 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27007 | /* 74709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16), |
| 27008 | /* 74712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27009 | /* 74714 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27010 | /* 74716 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27011 | /* 74718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27012 | /* 74721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27013 | /* 74727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27014 | /* 74733 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27015 | /* 74736 */ GIR_RootConstrainSelectedInstOperands, |
| 27016 | /* 74737 */ // GIR_Coverage, 4907, |
| 27017 | /* 74737 */ GIR_EraseRootFromParent_Done, |
| 27018 | /* 74738 */ // Label 1527: @74738 |
| 27019 | /* 74738 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(74820), // Rule ID 4934 // |
| 27020 | /* 74743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27021 | /* 74746 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 27022 | /* 74751 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27023 | /* 74754 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27024 | /* 74757 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27025 | /* 74760 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27026 | /* 74763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27027 | /* 74767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27028 | /* 74771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27029 | /* 74775 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27030 | /* 74779 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3908:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 27031 | /* 74779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27032 | /* 74782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27033 | /* 74786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27034 | /* 74791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 27035 | /* 74794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27036 | /* 74796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27037 | /* 74798 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27038 | /* 74800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27039 | /* 74803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27040 | /* 74809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27041 | /* 74815 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27042 | /* 74818 */ GIR_RootConstrainSelectedInstOperands, |
| 27043 | /* 74819 */ // GIR_Coverage, 4934, |
| 27044 | /* 74819 */ GIR_EraseRootFromParent_Done, |
| 27045 | /* 74820 */ // Label 1528: @74820 |
| 27046 | /* 74820 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(74902), // Rule ID 4941 // |
| 27047 | /* 74825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27048 | /* 74828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 27049 | /* 74833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27050 | /* 74836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27051 | /* 74839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27052 | /* 74842 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27053 | /* 74845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27054 | /* 74849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27055 | /* 74853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27056 | /* 74857 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27057 | /* 74861 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3908:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27058 | /* 74861 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27059 | /* 74864 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27060 | /* 74868 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27061 | /* 74873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 27062 | /* 74876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27063 | /* 74878 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27064 | /* 74880 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27065 | /* 74882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27066 | /* 74885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27067 | /* 74891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27068 | /* 74897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27069 | /* 74900 */ GIR_RootConstrainSelectedInstOperands, |
| 27070 | /* 74901 */ // GIR_Coverage, 4941, |
| 27071 | /* 74901 */ GIR_EraseRootFromParent_Done, |
| 27072 | /* 74902 */ // Label 1529: @74902 |
| 27073 | /* 74902 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(74984), // Rule ID 4945 // |
| 27074 | /* 74907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27075 | /* 74910 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 27076 | /* 74915 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27077 | /* 74918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27078 | /* 74921 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27079 | /* 74924 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27080 | /* 74927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27081 | /* 74931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27082 | /* 74935 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27083 | /* 74939 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27084 | /* 74943 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3908:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27085 | /* 74943 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27086 | /* 74946 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27087 | /* 74950 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27088 | /* 74955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 27089 | /* 74958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27090 | /* 74960 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27091 | /* 74962 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27092 | /* 74964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27093 | /* 74967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27094 | /* 74973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27095 | /* 74979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27096 | /* 74982 */ GIR_RootConstrainSelectedInstOperands, |
| 27097 | /* 74983 */ // GIR_Coverage, 4945, |
| 27098 | /* 74983 */ GIR_EraseRootFromParent_Done, |
| 27099 | /* 74984 */ // Label 1530: @74984 |
| 27100 | /* 74984 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(75066), // Rule ID 4949 // |
| 27101 | /* 74989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27102 | /* 74992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 27103 | /* 74997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27104 | /* 75000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27105 | /* 75003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27106 | /* 75006 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27107 | /* 75009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27108 | /* 75013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27109 | /* 75017 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27110 | /* 75021 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27111 | /* 75025 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3908:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 27112 | /* 75025 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27113 | /* 75028 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27114 | /* 75032 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27115 | /* 75037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 27116 | /* 75040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27117 | /* 75042 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27118 | /* 75044 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27119 | /* 75046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27120 | /* 75049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27121 | /* 75055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27122 | /* 75061 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27123 | /* 75064 */ GIR_RootConstrainSelectedInstOperands, |
| 27124 | /* 75065 */ // GIR_Coverage, 4949, |
| 27125 | /* 75065 */ GIR_EraseRootFromParent_Done, |
| 27126 | /* 75066 */ // Label 1531: @75066 |
| 27127 | /* 75066 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(75148), // Rule ID 4953 // |
| 27128 | /* 75071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27129 | /* 75074 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 27130 | /* 75079 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27131 | /* 75082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27132 | /* 75085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27133 | /* 75088 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27134 | /* 75091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27135 | /* 75095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27136 | /* 75099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27137 | /* 75103 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27138 | /* 75107 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3908:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27139 | /* 75107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27140 | /* 75110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27141 | /* 75114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27142 | /* 75119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 27143 | /* 75122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27144 | /* 75124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27145 | /* 75126 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27146 | /* 75128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27147 | /* 75131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27148 | /* 75137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27149 | /* 75143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27150 | /* 75146 */ GIR_RootConstrainSelectedInstOperands, |
| 27151 | /* 75147 */ // GIR_Coverage, 4953, |
| 27152 | /* 75147 */ GIR_EraseRootFromParent_Done, |
| 27153 | /* 75148 */ // Label 1532: @75148 |
| 27154 | /* 75148 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(75230), // Rule ID 4957 // |
| 27155 | /* 75153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27156 | /* 75156 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 27157 | /* 75161 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27158 | /* 75164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27159 | /* 75167 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27160 | /* 75170 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27161 | /* 75173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27162 | /* 75177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27163 | /* 75181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27164 | /* 75185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27165 | /* 75189 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3908:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27166 | /* 75189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27167 | /* 75192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27168 | /* 75196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27169 | /* 75201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 27170 | /* 75204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27171 | /* 75206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27172 | /* 75208 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27173 | /* 75210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27174 | /* 75213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27175 | /* 75219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27176 | /* 75225 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27177 | /* 75228 */ GIR_RootConstrainSelectedInstOperands, |
| 27178 | /* 75229 */ // GIR_Coverage, 4957, |
| 27179 | /* 75229 */ GIR_EraseRootFromParent_Done, |
| 27180 | /* 75230 */ // Label 1533: @75230 |
| 27181 | /* 75230 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(75312), // Rule ID 4958 // |
| 27182 | /* 75235 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27183 | /* 75238 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 27184 | /* 75243 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27185 | /* 75246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27186 | /* 75249 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27187 | /* 75252 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27188 | /* 75255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27189 | /* 75259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27190 | /* 75263 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27191 | /* 75267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27192 | /* 75271 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3948:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 27193 | /* 75271 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27194 | /* 75274 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27195 | /* 75278 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27196 | /* 75283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8), |
| 27197 | /* 75286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27198 | /* 75288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27199 | /* 75290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27200 | /* 75292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27201 | /* 75295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27202 | /* 75301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27203 | /* 75307 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27204 | /* 75310 */ GIR_RootConstrainSelectedInstOperands, |
| 27205 | /* 75311 */ // GIR_Coverage, 4958, |
| 27206 | /* 75311 */ GIR_EraseRootFromParent_Done, |
| 27207 | /* 75312 */ // Label 1534: @75312 |
| 27208 | /* 75312 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(75394), // Rule ID 4960 // |
| 27209 | /* 75317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27210 | /* 75320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 27211 | /* 75325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27212 | /* 75328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27213 | /* 75331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27214 | /* 75334 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27215 | /* 75337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27216 | /* 75341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27217 | /* 75345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27218 | /* 75349 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27219 | /* 75353 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3948:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27220 | /* 75353 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27221 | /* 75356 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27222 | /* 75360 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27223 | /* 75365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16), |
| 27224 | /* 75368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27225 | /* 75370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27226 | /* 75372 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27227 | /* 75374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27228 | /* 75377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27229 | /* 75383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27230 | /* 75389 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27231 | /* 75392 */ GIR_RootConstrainSelectedInstOperands, |
| 27232 | /* 75393 */ // GIR_Coverage, 4960, |
| 27233 | /* 75393 */ GIR_EraseRootFromParent_Done, |
| 27234 | /* 75394 */ // Label 1535: @75394 |
| 27235 | /* 75394 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(75476), // Rule ID 4962 // |
| 27236 | /* 75399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27237 | /* 75402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 27238 | /* 75407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27239 | /* 75410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27240 | /* 75413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27241 | /* 75416 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27242 | /* 75419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27243 | /* 75423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27244 | /* 75427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27245 | /* 75431 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27246 | /* 75435 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3948:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27247 | /* 75435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27248 | /* 75438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27249 | /* 75442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27250 | /* 75447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32), |
| 27251 | /* 75450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27252 | /* 75452 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27253 | /* 75454 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27254 | /* 75456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27255 | /* 75459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27256 | /* 75465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27257 | /* 75471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27258 | /* 75474 */ GIR_RootConstrainSelectedInstOperands, |
| 27259 | /* 75475 */ // GIR_Coverage, 4962, |
| 27260 | /* 75475 */ GIR_EraseRootFromParent_Done, |
| 27261 | /* 75476 */ // Label 1536: @75476 |
| 27262 | /* 75476 */ GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(75558), // Rule ID 4964 // |
| 27263 | /* 75481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27264 | /* 75484 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 27265 | /* 75489 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27266 | /* 75492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27267 | /* 75495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27268 | /* 75498 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27269 | /* 75501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27270 | /* 75505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27271 | /* 75509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27272 | /* 75513 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27273 | /* 75517 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3948:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 27274 | /* 75517 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27275 | /* 75520 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27276 | /* 75524 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27277 | /* 75529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8), |
| 27278 | /* 75532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27279 | /* 75534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27280 | /* 75536 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27281 | /* 75538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27282 | /* 75541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27283 | /* 75547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27284 | /* 75553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27285 | /* 75556 */ GIR_RootConstrainSelectedInstOperands, |
| 27286 | /* 75557 */ // GIR_Coverage, 4964, |
| 27287 | /* 75557 */ GIR_EraseRootFromParent_Done, |
| 27288 | /* 75558 */ // Label 1537: @75558 |
| 27289 | /* 75558 */ GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(75640), // Rule ID 4966 // |
| 27290 | /* 75563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27291 | /* 75566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 27292 | /* 75571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27293 | /* 75574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27294 | /* 75577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27295 | /* 75580 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27296 | /* 75583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27297 | /* 75587 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27298 | /* 75591 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27299 | /* 75595 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27300 | /* 75599 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3948:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27301 | /* 75599 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27302 | /* 75602 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27303 | /* 75606 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27304 | /* 75611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16), |
| 27305 | /* 75614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27306 | /* 75616 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27307 | /* 75618 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27308 | /* 75620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27309 | /* 75623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27310 | /* 75629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27311 | /* 75635 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27312 | /* 75638 */ GIR_RootConstrainSelectedInstOperands, |
| 27313 | /* 75639 */ // GIR_Coverage, 4966, |
| 27314 | /* 75639 */ GIR_EraseRootFromParent_Done, |
| 27315 | /* 75640 */ // Label 1538: @75640 |
| 27316 | /* 75640 */ GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(75722), // Rule ID 4968 // |
| 27317 | /* 75645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27318 | /* 75648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 27319 | /* 75653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27320 | /* 75656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27321 | /* 75659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27322 | /* 75662 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27323 | /* 75665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27324 | /* 75669 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27325 | /* 75673 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27326 | /* 75677 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27327 | /* 75681 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3948:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27328 | /* 75681 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27329 | /* 75684 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27330 | /* 75688 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27331 | /* 75693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32), |
| 27332 | /* 75696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27333 | /* 75698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27334 | /* 75700 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27335 | /* 75702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27336 | /* 75705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27337 | /* 75711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27338 | /* 75717 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27339 | /* 75720 */ GIR_RootConstrainSelectedInstOperands, |
| 27340 | /* 75721 */ // GIR_Coverage, 4968, |
| 27341 | /* 75721 */ GIR_EraseRootFromParent_Done, |
| 27342 | /* 75722 */ // Label 1539: @75722 |
| 27343 | /* 75722 */ GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(75789), // Rule ID 5019 // |
| 27344 | /* 75727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27345 | /* 75730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 27346 | /* 75735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27347 | /* 75738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27348 | /* 75741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27349 | /* 75744 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27350 | /* 75747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27351 | /* 75751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27352 | /* 75755 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27353 | /* 75759 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27354 | /* 75763 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3863:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 27355 | /* 75763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh), |
| 27356 | /* 75766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27357 | /* 75768 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 27358 | /* 75770 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27359 | /* 75772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27360 | /* 75775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27361 | /* 75781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27362 | /* 75787 */ GIR_RootConstrainSelectedInstOperands, |
| 27363 | /* 75788 */ // GIR_Coverage, 5019, |
| 27364 | /* 75788 */ GIR_EraseRootFromParent_Done, |
| 27365 | /* 75789 */ // Label 1540: @75789 |
| 27366 | /* 75789 */ GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(75856), // Rule ID 5025 // |
| 27367 | /* 75794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27368 | /* 75797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 27369 | /* 75802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27370 | /* 75805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27371 | /* 75808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27372 | /* 75811 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27373 | /* 75814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27374 | /* 75818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27375 | /* 75822 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27376 | /* 75826 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27377 | /* 75830 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3863:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 27378 | /* 75830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th), |
| 27379 | /* 75833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27380 | /* 75835 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 27381 | /* 75837 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27382 | /* 75839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27383 | /* 75842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27384 | /* 75848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27385 | /* 75854 */ GIR_RootConstrainSelectedInstOperands, |
| 27386 | /* 75855 */ // GIR_Coverage, 5025, |
| 27387 | /* 75855 */ GIR_EraseRootFromParent_Done, |
| 27388 | /* 75856 */ // Label 1541: @75856 |
| 27389 | /* 75856 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(75938), // Rule ID 5043 // |
| 27390 | /* 75861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27391 | /* 75864 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 27392 | /* 75869 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27393 | /* 75872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27394 | /* 75875 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27395 | /* 75878 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27396 | /* 75881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27397 | /* 75885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27398 | /* 75889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27399 | /* 75893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27400 | /* 75897 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27401 | /* 75897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27402 | /* 75900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27403 | /* 75904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27404 | /* 75909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh), |
| 27405 | /* 75912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27406 | /* 75914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27407 | /* 75916 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27408 | /* 75918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27409 | /* 75921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27410 | /* 75927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27411 | /* 75933 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27412 | /* 75936 */ GIR_RootConstrainSelectedInstOperands, |
| 27413 | /* 75937 */ // GIR_Coverage, 5043, |
| 27414 | /* 75937 */ GIR_EraseRootFromParent_Done, |
| 27415 | /* 75938 */ // Label 1542: @75938 |
| 27416 | /* 75938 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(76020), // Rule ID 5045 // |
| 27417 | /* 75943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27418 | /* 75946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 27419 | /* 75951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27420 | /* 75954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27421 | /* 75957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27422 | /* 75960 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27423 | /* 75963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27424 | /* 75967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27425 | /* 75971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27426 | /* 75975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27427 | /* 75979 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27428 | /* 75979 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27429 | /* 75982 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27430 | /* 75986 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27431 | /* 75991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th), |
| 27432 | /* 75994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27433 | /* 75996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27434 | /* 75998 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27435 | /* 76000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27436 | /* 76003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27437 | /* 76009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27438 | /* 76015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27439 | /* 76018 */ GIR_RootConstrainSelectedInstOperands, |
| 27440 | /* 76019 */ // GIR_Coverage, 5045, |
| 27441 | /* 76019 */ GIR_EraseRootFromParent_Done, |
| 27442 | /* 76020 */ // Label 1543: @76020 |
| 27443 | /* 76020 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(76102), // Rule ID 5047 // |
| 27444 | /* 76025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27445 | /* 76028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 27446 | /* 76033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 27447 | /* 76036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27448 | /* 76039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27449 | /* 76042 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27450 | /* 76045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27451 | /* 76049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27452 | /* 76053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27453 | /* 76057 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27454 | /* 76061 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3918:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27455 | /* 76061 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27456 | /* 76064 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27457 | /* 76068 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27458 | /* 76073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh), |
| 27459 | /* 76076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27460 | /* 76078 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27461 | /* 76080 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27462 | /* 76082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27463 | /* 76085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27464 | /* 76091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27465 | /* 76097 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27466 | /* 76100 */ GIR_RootConstrainSelectedInstOperands, |
| 27467 | /* 76101 */ // GIR_Coverage, 5047, |
| 27468 | /* 76101 */ GIR_EraseRootFromParent_Done, |
| 27469 | /* 76102 */ // Label 1544: @76102 |
| 27470 | /* 76102 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(76184), // Rule ID 5049 // |
| 27471 | /* 76107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27472 | /* 76110 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 27473 | /* 76115 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 27474 | /* 76118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27475 | /* 76121 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27476 | /* 76124 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27477 | /* 76127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27478 | /* 76131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27479 | /* 76135 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27480 | /* 76139 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27481 | /* 76143 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3918:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27482 | /* 76143 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27483 | /* 76146 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27484 | /* 76150 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27485 | /* 76155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th), |
| 27486 | /* 76158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27487 | /* 76160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27488 | /* 76162 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27489 | /* 76164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27490 | /* 76167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27491 | /* 76173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27492 | /* 76179 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27493 | /* 76182 */ GIR_RootConstrainSelectedInstOperands, |
| 27494 | /* 76183 */ // GIR_Coverage, 5049, |
| 27495 | /* 76183 */ GIR_EraseRootFromParent_Done, |
| 27496 | /* 76184 */ // Label 1545: @76184 |
| 27497 | /* 76184 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(76261), // Rule ID 4286 // |
| 27498 | /* 76189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 27499 | /* 76194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27500 | /* 76197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27501 | /* 76200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27502 | /* 76203 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27503 | /* 76206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27504 | /* 76210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27505 | /* 76214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27506 | /* 76218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 27507 | /* 76222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27508 | /* 76226 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 27509 | /* 76230 */ // MIs[1] Operand 1 |
| 27510 | /* 76230 */ // No operand predicates |
| 27511 | /* 76230 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27512 | /* 76232 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3963:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 27513 | /* 76232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm8), |
| 27514 | /* 76235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27515 | /* 76237 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 27516 | /* 76239 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27517 | /* 76241 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 27518 | /* 76244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27519 | /* 76247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27520 | /* 76253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27521 | /* 76259 */ GIR_RootConstrainSelectedInstOperands, |
| 27522 | /* 76260 */ // GIR_Coverage, 4286, |
| 27523 | /* 76260 */ GIR_EraseRootFromParent_Done, |
| 27524 | /* 76261 */ // Label 1546: @76261 |
| 27525 | /* 76261 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(76338), // Rule ID 4288 // |
| 27526 | /* 76266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 27527 | /* 76271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27528 | /* 76274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27529 | /* 76277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27530 | /* 76280 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27531 | /* 76283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27532 | /* 76287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27533 | /* 76291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27534 | /* 76295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 27535 | /* 76299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27536 | /* 76303 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 27537 | /* 76307 */ // MIs[1] Operand 1 |
| 27538 | /* 76307 */ // No operand predicates |
| 27539 | /* 76307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27540 | /* 76309 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3963:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 27541 | /* 76309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm16), |
| 27542 | /* 76312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27543 | /* 76314 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 27544 | /* 76316 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27545 | /* 76318 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 27546 | /* 76321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27547 | /* 76324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27548 | /* 76330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27549 | /* 76336 */ GIR_RootConstrainSelectedInstOperands, |
| 27550 | /* 76337 */ // GIR_Coverage, 4288, |
| 27551 | /* 76337 */ GIR_EraseRootFromParent_Done, |
| 27552 | /* 76338 */ // Label 1547: @76338 |
| 27553 | /* 76338 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(76415), // Rule ID 4290 // |
| 27554 | /* 76343 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 27555 | /* 76348 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27556 | /* 76351 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27557 | /* 76354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27558 | /* 76357 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27559 | /* 76360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27560 | /* 76364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27561 | /* 76368 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27562 | /* 76372 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 27563 | /* 76376 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27564 | /* 76380 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 27565 | /* 76384 */ // MIs[1] Operand 1 |
| 27566 | /* 76384 */ // No operand predicates |
| 27567 | /* 76384 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27568 | /* 76386 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 27569 | /* 76386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm32), |
| 27570 | /* 76389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27571 | /* 76391 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 27572 | /* 76393 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27573 | /* 76395 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 27574 | /* 76398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27575 | /* 76401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27576 | /* 76407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27577 | /* 76413 */ GIR_RootConstrainSelectedInstOperands, |
| 27578 | /* 76414 */ // GIR_Coverage, 4290, |
| 27579 | /* 76414 */ GIR_EraseRootFromParent_Done, |
| 27580 | /* 76415 */ // Label 1548: @76415 |
| 27581 | /* 76415 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(76492), // Rule ID 4292 // |
| 27582 | /* 76420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 27583 | /* 76425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27584 | /* 76428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27585 | /* 76431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27586 | /* 76434 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27587 | /* 76437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27588 | /* 76441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27589 | /* 76445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27590 | /* 76449 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 27591 | /* 76453 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27592 | /* 76457 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 27593 | /* 76461 */ // MIs[1] Operand 1 |
| 27594 | /* 76461 */ // No operand predicates |
| 27595 | /* 76461 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27596 | /* 76463 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) => (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 27597 | /* 76463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm8), |
| 27598 | /* 76466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27599 | /* 76468 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 27600 | /* 76470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27601 | /* 76472 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 27602 | /* 76475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27603 | /* 76478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27604 | /* 76484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27605 | /* 76490 */ GIR_RootConstrainSelectedInstOperands, |
| 27606 | /* 76491 */ // GIR_Coverage, 4292, |
| 27607 | /* 76491 */ GIR_EraseRootFromParent_Done, |
| 27608 | /* 76492 */ // Label 1549: @76492 |
| 27609 | /* 76492 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(76569), // Rule ID 4294 // |
| 27610 | /* 76497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 27611 | /* 76502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27612 | /* 76505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27613 | /* 76508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27614 | /* 76511 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27615 | /* 76514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27616 | /* 76518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27617 | /* 76522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27618 | /* 76526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 27619 | /* 76530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27620 | /* 76534 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 27621 | /* 76538 */ // MIs[1] Operand 1 |
| 27622 | /* 76538 */ // No operand predicates |
| 27623 | /* 76538 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27624 | /* 76540 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) => (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 27625 | /* 76540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm16), |
| 27626 | /* 76543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27627 | /* 76545 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 27628 | /* 76547 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27629 | /* 76549 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 27630 | /* 76552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27631 | /* 76555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27632 | /* 76561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27633 | /* 76567 */ GIR_RootConstrainSelectedInstOperands, |
| 27634 | /* 76568 */ // GIR_Coverage, 4294, |
| 27635 | /* 76568 */ GIR_EraseRootFromParent_Done, |
| 27636 | /* 76569 */ // Label 1550: @76569 |
| 27637 | /* 76569 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(76646), // Rule ID 4296 // |
| 27638 | /* 76574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 27639 | /* 76579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27640 | /* 76582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27641 | /* 76585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27642 | /* 76588 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27643 | /* 76591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27644 | /* 76595 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27645 | /* 76599 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27646 | /* 76603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 27647 | /* 76607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27648 | /* 76611 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 27649 | /* 76615 */ // MIs[1] Operand 1 |
| 27650 | /* 76615 */ // No operand predicates |
| 27651 | /* 76615 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27652 | /* 76617 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3965:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) => (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 27653 | /* 76617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm32), |
| 27654 | /* 76620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27655 | /* 76622 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 27656 | /* 76624 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 27657 | /* 76626 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 27658 | /* 76629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27659 | /* 76632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27660 | /* 76638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27661 | /* 76644 */ GIR_RootConstrainSelectedInstOperands, |
| 27662 | /* 76645 */ // GIR_Coverage, 4296, |
| 27663 | /* 76645 */ GIR_EraseRootFromParent_Done, |
| 27664 | /* 76646 */ // Label 1551: @76646 |
| 27665 | /* 76646 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(76732), // Rule ID 4415 // |
| 27666 | /* 76651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27667 | /* 76654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 27668 | /* 76659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27669 | /* 76662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27670 | /* 76665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27671 | /* 76668 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27672 | /* 76671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27673 | /* 76675 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27674 | /* 76679 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 27675 | /* 76683 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 27676 | /* 76687 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27677 | /* 76692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27678 | /* 76696 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27679 | /* 76700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27680 | /* 76702 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3783:{ *:[iPTR] }, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 27681 | /* 76702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 27682 | /* 76705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27683 | /* 76707 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27684 | /* 76709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 27685 | /* 76713 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 27686 | /* 76715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27687 | /* 76718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27688 | /* 76724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27689 | /* 76730 */ GIR_RootConstrainSelectedInstOperands, |
| 27690 | /* 76731 */ // GIR_Coverage, 4415, |
| 27691 | /* 76731 */ GIR_EraseRootFromParent_Done, |
| 27692 | /* 76732 */ // Label 1552: @76732 |
| 27693 | /* 76732 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(76818), // Rule ID 4429 // |
| 27694 | /* 76737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27695 | /* 76740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 27696 | /* 76745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27697 | /* 76748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27698 | /* 76751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27699 | /* 76754 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27700 | /* 76757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27701 | /* 76761 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27702 | /* 76765 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 27703 | /* 76769 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 27704 | /* 76773 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27705 | /* 76778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27706 | /* 76782 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27707 | /* 76786 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27708 | /* 76788 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3783:{ *:[iPTR] }, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 27709 | /* 76788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 27710 | /* 76791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27711 | /* 76793 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27712 | /* 76795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 27713 | /* 76799 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 27714 | /* 76801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27715 | /* 76804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27716 | /* 76810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27717 | /* 76816 */ GIR_RootConstrainSelectedInstOperands, |
| 27718 | /* 76817 */ // GIR_Coverage, 4429, |
| 27719 | /* 76817 */ GIR_EraseRootFromParent_Done, |
| 27720 | /* 76818 */ // Label 1553: @76818 |
| 27721 | /* 76818 */ GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(76909), // Rule ID 4873 // |
| 27722 | /* 76823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27723 | /* 76826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 27724 | /* 76831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27725 | /* 76834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27726 | /* 76837 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27727 | /* 76840 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27728 | /* 76843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27729 | /* 76847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27730 | /* 76851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27731 | /* 76855 */ // MIs[1] Operand 1 |
| 27732 | /* 76855 */ // No operand predicates |
| 27733 | /* 76855 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27734 | /* 76859 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27735 | /* 76863 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27736 | /* 76865 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3852:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27737 | /* 76865 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27738 | /* 76868 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27739 | /* 76872 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27740 | /* 76877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16), |
| 27741 | /* 76880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27742 | /* 76882 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27743 | /* 76884 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 27744 | /* 76886 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27745 | /* 76889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27746 | /* 76892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27747 | /* 76898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27748 | /* 76904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27749 | /* 76907 */ GIR_RootConstrainSelectedInstOperands, |
| 27750 | /* 76908 */ // GIR_Coverage, 4873, |
| 27751 | /* 76908 */ GIR_EraseRootFromParent_Done, |
| 27752 | /* 76909 */ // Label 1554: @76909 |
| 27753 | /* 76909 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(77000), // Rule ID 4875 // |
| 27754 | /* 76914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27755 | /* 76917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 27756 | /* 76922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27757 | /* 76925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27758 | /* 76928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27759 | /* 76931 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27760 | /* 76934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27761 | /* 76938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27762 | /* 76942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27763 | /* 76946 */ // MIs[1] Operand 1 |
| 27764 | /* 76946 */ // No operand predicates |
| 27765 | /* 76946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27766 | /* 76950 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27767 | /* 76954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27768 | /* 76956 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3852:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27769 | /* 76956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27770 | /* 76959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27771 | /* 76963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 27772 | /* 76968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32), |
| 27773 | /* 76971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27774 | /* 76973 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27775 | /* 76975 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 27776 | /* 76977 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27777 | /* 76980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27778 | /* 76983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27779 | /* 76989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27780 | /* 76995 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27781 | /* 76998 */ GIR_RootConstrainSelectedInstOperands, |
| 27782 | /* 76999 */ // GIR_Coverage, 4875, |
| 27783 | /* 76999 */ GIR_EraseRootFromParent_Done, |
| 27784 | /* 77000 */ // Label 1555: @77000 |
| 27785 | /* 77000 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(77086), // Rule ID 4416 // |
| 27786 | /* 77005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27787 | /* 77008 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 27788 | /* 77013 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27789 | /* 77016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27790 | /* 77019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27791 | /* 77022 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27792 | /* 77025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27793 | /* 77029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27794 | /* 77033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27795 | /* 77037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 27796 | /* 77041 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 27797 | /* 77045 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27798 | /* 77050 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27799 | /* 77054 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27800 | /* 77056 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3783:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 27801 | /* 77056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 27802 | /* 77059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27803 | /* 77061 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27804 | /* 77063 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 27805 | /* 77065 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2 |
| 27806 | /* 77069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27807 | /* 77072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27808 | /* 77078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27809 | /* 77084 */ GIR_RootConstrainSelectedInstOperands, |
| 27810 | /* 77085 */ // GIR_Coverage, 4416, |
| 27811 | /* 77085 */ GIR_EraseRootFromParent_Done, |
| 27812 | /* 77086 */ // Label 1556: @77086 |
| 27813 | /* 77086 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(77172), // Rule ID 4430 // |
| 27814 | /* 77091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27815 | /* 77094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 27816 | /* 77099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27817 | /* 77102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27818 | /* 77105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27819 | /* 77108 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27820 | /* 77111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27821 | /* 77115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27822 | /* 77119 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27823 | /* 77123 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 27824 | /* 77127 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 27825 | /* 77131 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27826 | /* 77136 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27827 | /* 77140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27828 | /* 77142 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3783:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 27829 | /* 77142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 27830 | /* 77145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27831 | /* 77147 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27832 | /* 77149 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 27833 | /* 77151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2 |
| 27834 | /* 77155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27835 | /* 77158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27836 | /* 77164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27837 | /* 77170 */ GIR_RootConstrainSelectedInstOperands, |
| 27838 | /* 77171 */ // GIR_Coverage, 4430, |
| 27839 | /* 77171 */ GIR_EraseRootFromParent_Done, |
| 27840 | /* 77172 */ // Label 1557: @77172 |
| 27841 | /* 77172 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(77235), // Rule ID 145 // |
| 27842 | /* 77177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 27843 | /* 77180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 27844 | /* 77185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27845 | /* 77188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27846 | /* 77191 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27847 | /* 77194 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27848 | /* 77197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27849 | /* 77201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27850 | /* 77205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27851 | /* 77209 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27852 | /* 77213 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 27853 | /* 77213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8), |
| 27854 | /* 77216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27855 | /* 77218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27856 | /* 77220 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27857 | /* 77222 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27858 | /* 77224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27859 | /* 77227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27860 | /* 77233 */ GIR_RootConstrainSelectedInstOperands, |
| 27861 | /* 77234 */ // GIR_Coverage, 145, |
| 27862 | /* 77234 */ GIR_EraseRootFromParent_Done, |
| 27863 | /* 77235 */ // Label 1558: @77235 |
| 27864 | /* 77235 */ GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(77298), // Rule ID 468 // |
| 27865 | /* 77240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 27866 | /* 77243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 27867 | /* 77248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27868 | /* 77251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27869 | /* 77254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27870 | /* 77257 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27871 | /* 77260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27872 | /* 77264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27873 | /* 77268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27874 | /* 77272 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27875 | /* 77276 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 27876 | /* 77276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8), |
| 27877 | /* 77279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27878 | /* 77281 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27879 | /* 77283 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27880 | /* 77285 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27881 | /* 77287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27882 | /* 77290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27883 | /* 77296 */ GIR_RootConstrainSelectedInstOperands, |
| 27884 | /* 77297 */ // GIR_Coverage, 468, |
| 27885 | /* 77297 */ GIR_EraseRootFromParent_Done, |
| 27886 | /* 77298 */ // Label 1559: @77298 |
| 27887 | /* 77298 */ GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(77361), // Rule ID 527 // |
| 27888 | /* 77303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 27889 | /* 77306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 27890 | /* 77311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27891 | /* 77314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27892 | /* 77317 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27893 | /* 77320 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27894 | /* 77323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27895 | /* 77327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27896 | /* 77331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27897 | /* 77335 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27898 | /* 77339 */ // (intrinsic_wo_chain:{ *:[i32] } 4135:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 27899 | /* 77339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD), |
| 27900 | /* 77342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27901 | /* 77344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27902 | /* 77346 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27903 | /* 77348 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27904 | /* 77350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27905 | /* 77353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27906 | /* 77359 */ GIR_RootConstrainSelectedInstOperands, |
| 27907 | /* 77360 */ // GIR_Coverage, 527, |
| 27908 | /* 77360 */ GIR_EraseRootFromParent_Done, |
| 27909 | /* 77361 */ // Label 1560: @77361 |
| 27910 | /* 77361 */ GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(77424), // Rule ID 528 // |
| 27911 | /* 77366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 27912 | /* 77369 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 27913 | /* 77374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27914 | /* 77377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27915 | /* 77380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27916 | /* 77383 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27917 | /* 77386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27918 | /* 77390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27919 | /* 77394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27920 | /* 77398 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27921 | /* 77402 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 27922 | /* 77402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX), |
| 27923 | /* 77405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27924 | /* 77407 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27925 | /* 77409 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27926 | /* 77411 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27927 | /* 77413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27928 | /* 77416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27929 | /* 77422 */ GIR_RootConstrainSelectedInstOperands, |
| 27930 | /* 77423 */ // GIR_Coverage, 528, |
| 27931 | /* 77423 */ GIR_EraseRootFromParent_Done, |
| 27932 | /* 77424 */ // Label 1561: @77424 |
| 27933 | /* 77424 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(77487), // Rule ID 529 // |
| 27934 | /* 77429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 27935 | /* 77432 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 27936 | /* 77437 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27937 | /* 77440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27938 | /* 77443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27939 | /* 77446 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27940 | /* 77449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27941 | /* 77453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27942 | /* 77457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27943 | /* 77461 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27944 | /* 77465 */ // (intrinsic_wo_chain:{ *:[i32] } 4143:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 27945 | /* 77465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD), |
| 27946 | /* 77468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27947 | /* 77470 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27948 | /* 77472 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27949 | /* 77474 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27950 | /* 77476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27951 | /* 77479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27952 | /* 77485 */ GIR_RootConstrainSelectedInstOperands, |
| 27953 | /* 77486 */ // GIR_Coverage, 529, |
| 27954 | /* 77486 */ GIR_EraseRootFromParent_Done, |
| 27955 | /* 77487 */ // Label 1562: @77487 |
| 27956 | /* 77487 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(77550), // Rule ID 530 // |
| 27957 | /* 77492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 27958 | /* 77495 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 27959 | /* 77500 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27960 | /* 77503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27961 | /* 77506 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27962 | /* 77509 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27963 | /* 77512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27964 | /* 77516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27965 | /* 77520 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27966 | /* 77524 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27967 | /* 77528 */ // (intrinsic_wo_chain:{ *:[i32] } 4144:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 27968 | /* 77528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX), |
| 27969 | /* 77531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27970 | /* 77533 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27971 | /* 77535 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27972 | /* 77537 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27973 | /* 77539 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27974 | /* 77542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27975 | /* 77548 */ GIR_RootConstrainSelectedInstOperands, |
| 27976 | /* 77549 */ // GIR_Coverage, 530, |
| 27977 | /* 77549 */ GIR_EraseRootFromParent_Done, |
| 27978 | /* 77550 */ // Label 1563: @77550 |
| 27979 | /* 77550 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(77604), // Rule ID 1112 // |
| 27980 | /* 77555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 27981 | /* 77558 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 27982 | /* 77563 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 27983 | /* 77566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27984 | /* 77569 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27985 | /* 77572 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27986 | /* 77575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27987 | /* 77579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27988 | /* 77583 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27989 | /* 77587 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27990 | /* 77591 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3996:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 27991 | /* 77591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD), |
| 27992 | /* 77594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27993 | /* 77596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27994 | /* 77598 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27995 | /* 77600 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27996 | /* 77602 */ GIR_RootConstrainSelectedInstOperands, |
| 27997 | /* 77603 */ // GIR_Coverage, 1112, |
| 27998 | /* 77603 */ GIR_EraseRootFromParent_Done, |
| 27999 | /* 77604 */ // Label 1564: @77604 |
| 28000 | /* 77604 */ GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(77658), // Rule ID 1113 // |
| 28001 | /* 77609 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 28002 | /* 77612 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 28003 | /* 77617 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 28004 | /* 77620 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 28005 | /* 77623 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 28006 | /* 77626 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 28007 | /* 77629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28008 | /* 77633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28009 | /* 77637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28010 | /* 77641 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28011 | /* 77645 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3984:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 28012 | /* 77645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD), |
| 28013 | /* 77648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28014 | /* 77650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28015 | /* 77652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28016 | /* 77654 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28017 | /* 77656 */ GIR_RootConstrainSelectedInstOperands, |
| 28018 | /* 77657 */ // GIR_Coverage, 1113, |
| 28019 | /* 77657 */ GIR_EraseRootFromParent_Done, |
| 28020 | /* 77658 */ // Label 1565: @77658 |
| 28021 | /* 77658 */ GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(77712), // Rule ID 1114 // |
| 28022 | /* 77663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 28023 | /* 77666 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 28024 | /* 77671 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28025 | /* 77674 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28026 | /* 77677 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28027 | /* 77680 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28028 | /* 77683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28029 | /* 77687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28030 | /* 77691 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28031 | /* 77695 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28032 | /* 77699 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3996:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 28033 | /* 77699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ), |
| 28034 | /* 77702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28035 | /* 77704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28036 | /* 77706 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28037 | /* 77708 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28038 | /* 77710 */ GIR_RootConstrainSelectedInstOperands, |
| 28039 | /* 77711 */ // GIR_Coverage, 1114, |
| 28040 | /* 77711 */ GIR_EraseRootFromParent_Done, |
| 28041 | /* 77712 */ // Label 1566: @77712 |
| 28042 | /* 77712 */ GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(77766), // Rule ID 1115 // |
| 28043 | /* 77717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 28044 | /* 77720 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 28045 | /* 77725 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28046 | /* 77728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28047 | /* 77731 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28048 | /* 77734 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28049 | /* 77737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28050 | /* 77741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28051 | /* 77745 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28052 | /* 77749 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28053 | /* 77753 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3984:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 28054 | /* 77753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ), |
| 28055 | /* 77756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28056 | /* 77758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28057 | /* 77760 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28058 | /* 77762 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28059 | /* 77764 */ GIR_RootConstrainSelectedInstOperands, |
| 28060 | /* 77765 */ // GIR_Coverage, 1115, |
| 28061 | /* 77765 */ GIR_EraseRootFromParent_Done, |
| 28062 | /* 77766 */ // Label 1567: @77766 |
| 28063 | /* 77766 */ GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(77820), // Rule ID 1116 // |
| 28064 | /* 77771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 28065 | /* 77774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla), |
| 28066 | /* 77779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28067 | /* 77782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28068 | /* 77785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28069 | /* 77788 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28070 | /* 77791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28071 | /* 77795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28072 | /* 77799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28073 | /* 77803 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28074 | /* 77807 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3995:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 28075 | /* 77807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA), |
| 28076 | /* 77810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28077 | /* 77812 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28078 | /* 77814 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28079 | /* 77816 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28080 | /* 77818 */ GIR_RootConstrainSelectedInstOperands, |
| 28081 | /* 77819 */ // GIR_Coverage, 1116, |
| 28082 | /* 77819 */ GIR_EraseRootFromParent_Done, |
| 28083 | /* 77820 */ // Label 1568: @77820 |
| 28084 | /* 77820 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(77874), // Rule ID 1117 // |
| 28085 | /* 77825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 28086 | /* 77828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla), |
| 28087 | /* 77833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28088 | /* 77836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28089 | /* 77839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28090 | /* 77842 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28091 | /* 77845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28092 | /* 77849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28093 | /* 77853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28094 | /* 77857 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28095 | /* 77861 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3997:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 28096 | /* 77861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA), |
| 28097 | /* 77864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28098 | /* 77866 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28099 | /* 77868 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28100 | /* 77870 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28101 | /* 77872 */ GIR_RootConstrainSelectedInstOperands, |
| 28102 | /* 77873 */ // GIR_Coverage, 1117, |
| 28103 | /* 77873 */ GIR_EraseRootFromParent_Done, |
| 28104 | /* 77874 */ // Label 1569: @77874 |
| 28105 | /* 77874 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(77928), // Rule ID 1118 // |
| 28106 | /* 77879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 28107 | /* 77882 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla), |
| 28108 | /* 77887 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28109 | /* 77890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28110 | /* 77893 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28111 | /* 77896 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28112 | /* 77899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28113 | /* 77903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28114 | /* 77907 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28115 | /* 77911 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28116 | /* 77915 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3999:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 28117 | /* 77915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA), |
| 28118 | /* 77918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28119 | /* 77920 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28120 | /* 77922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28121 | /* 77924 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28122 | /* 77926 */ GIR_RootConstrainSelectedInstOperands, |
| 28123 | /* 77927 */ // GIR_Coverage, 1118, |
| 28124 | /* 77927 */ GIR_EraseRootFromParent_Done, |
| 28125 | /* 77928 */ // Label 1570: @77928 |
| 28126 | /* 77928 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(77982), // Rule ID 1119 // |
| 28127 | /* 77933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 28128 | /* 77936 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 28129 | /* 77941 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 28130 | /* 77944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 28131 | /* 77947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 28132 | /* 77950 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 28133 | /* 77953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28134 | /* 77957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28135 | /* 77961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28136 | /* 77965 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28137 | /* 77969 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3998:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 28138 | /* 77969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD), |
| 28139 | /* 77972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28140 | /* 77974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28141 | /* 77976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28142 | /* 77978 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28143 | /* 77980 */ GIR_RootConstrainSelectedInstOperands, |
| 28144 | /* 77981 */ // GIR_Coverage, 1119, |
| 28145 | /* 77981 */ GIR_EraseRootFromParent_Done, |
| 28146 | /* 77982 */ // Label 1571: @77982 |
| 28147 | /* 77982 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(78036), // Rule ID 1120 // |
| 28148 | /* 77987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 28149 | /* 77990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 28150 | /* 77995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28151 | /* 77998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28152 | /* 78001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28153 | /* 78004 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28154 | /* 78007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28155 | /* 78011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28156 | /* 78015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28157 | /* 78019 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28158 | /* 78023 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3998:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 28159 | /* 78023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ), |
| 28160 | /* 78026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28161 | /* 78028 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 28162 | /* 78030 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28163 | /* 78032 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28164 | /* 78034 */ GIR_RootConstrainSelectedInstOperands, |
| 28165 | /* 78035 */ // GIR_Coverage, 1120, |
| 28166 | /* 78035 */ GIR_EraseRootFromParent_Done, |
| 28167 | /* 78036 */ // Label 1572: @78036 |
| 28168 | /* 78036 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(78099), // Rule ID 1851 // |
| 28169 | /* 78041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 28170 | /* 78044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1), |
| 28171 | /* 78049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 28172 | /* 78052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 28173 | /* 78055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 28174 | /* 78058 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 28175 | /* 78061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28176 | /* 78065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28177 | /* 78069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28178 | /* 78073 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28179 | /* 78077 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4110:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 28180 | /* 78077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1), |
| 28181 | /* 78080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28182 | /* 78082 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 28183 | /* 78084 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28184 | /* 78086 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28185 | /* 78088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28186 | /* 78091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28187 | /* 78097 */ GIR_RootConstrainSelectedInstOperands, |
| 28188 | /* 78098 */ // GIR_Coverage, 1851, |
| 28189 | /* 78098 */ GIR_EraseRootFromParent_Done, |
| 28190 | /* 78099 */ // Label 1573: @78099 |
| 28191 | /* 78099 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(78153), // Rule ID 1906 // |
| 28192 | /* 78104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 28193 | /* 78107 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0), |
| 28194 | /* 78112 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28195 | /* 78115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28196 | /* 78118 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28197 | /* 78121 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28198 | /* 78124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28199 | /* 78128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28200 | /* 78132 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28201 | /* 78136 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28202 | /* 78140 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 28203 | /* 78140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0), |
| 28204 | /* 78143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28205 | /* 78145 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28206 | /* 78147 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28207 | /* 78149 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28208 | /* 78151 */ GIR_RootConstrainSelectedInstOperands, |
| 28209 | /* 78152 */ // GIR_Coverage, 1906, |
| 28210 | /* 78152 */ GIR_EraseRootFromParent_Done, |
| 28211 | /* 78153 */ // Label 1574: @78153 |
| 28212 | /* 78153 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(78207), // Rule ID 1907 // |
| 28213 | /* 78158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 28214 | /* 78161 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h), |
| 28215 | /* 78166 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28216 | /* 78169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28217 | /* 78172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28218 | /* 78175 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28219 | /* 78178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28220 | /* 78182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28221 | /* 78186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28222 | /* 78190 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28223 | /* 78194 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3991:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 28224 | /* 78194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H), |
| 28225 | /* 78197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28226 | /* 78199 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28227 | /* 78201 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28228 | /* 78203 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28229 | /* 78205 */ GIR_RootConstrainSelectedInstOperands, |
| 28230 | /* 78206 */ // GIR_Coverage, 1907, |
| 28231 | /* 78206 */ GIR_EraseRootFromParent_Done, |
| 28232 | /* 78207 */ // Label 1575: @78207 |
| 28233 | /* 78207 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(78261), // Rule ID 1908 // |
| 28234 | /* 78212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 28235 | /* 78215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2), |
| 28236 | /* 78220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28237 | /* 78223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28238 | /* 78226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28239 | /* 78229 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28240 | /* 78232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28241 | /* 78236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28242 | /* 78240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28243 | /* 78244 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28244 | /* 78248 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3992:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 28245 | /* 78248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2), |
| 28246 | /* 78251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28247 | /* 78253 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28248 | /* 78255 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28249 | /* 78257 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28250 | /* 78259 */ GIR_RootConstrainSelectedInstOperands, |
| 28251 | /* 78260 */ // GIR_Coverage, 1908, |
| 28252 | /* 78260 */ GIR_EraseRootFromParent_Done, |
| 28253 | /* 78261 */ // Label 1576: @78261 |
| 28254 | /* 78261 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(78315), // Rule ID 1909 // |
| 28255 | /* 78266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 28256 | /* 78269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1), |
| 28257 | /* 78274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28258 | /* 78277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28259 | /* 78280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28260 | /* 78283 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28261 | /* 78286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28262 | /* 78290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28263 | /* 78294 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28264 | /* 78298 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28265 | /* 78302 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3994:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 28266 | /* 78302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1), |
| 28267 | /* 78305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28268 | /* 78307 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28269 | /* 78309 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28270 | /* 78311 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28271 | /* 78313 */ GIR_RootConstrainSelectedInstOperands, |
| 28272 | /* 78314 */ // GIR_Coverage, 1909, |
| 28273 | /* 78314 */ GIR_EraseRootFromParent_Done, |
| 28274 | /* 78315 */ // Label 1577: @78315 |
| 28275 | /* 78315 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(78378), // Rule ID 2084 // |
| 28276 | /* 78320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 28277 | /* 78323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 28278 | /* 78328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28279 | /* 78331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28280 | /* 78334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28281 | /* 78337 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28282 | /* 78340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28283 | /* 78344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28284 | /* 78348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28285 | /* 78352 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28286 | /* 78356 */ // (intrinsic_wo_chain:{ *:[i32] } 4135:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 28287 | /* 78356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD), |
| 28288 | /* 78359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28289 | /* 78361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 28290 | /* 78363 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 28291 | /* 78365 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 28292 | /* 78367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28293 | /* 78370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28294 | /* 78376 */ GIR_RootConstrainSelectedInstOperands, |
| 28295 | /* 78377 */ // GIR_Coverage, 2084, |
| 28296 | /* 78377 */ GIR_EraseRootFromParent_Done, |
| 28297 | /* 78378 */ // Label 1578: @78378 |
| 28298 | /* 78378 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(78441), // Rule ID 2085 // |
| 28299 | /* 78383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 28300 | /* 78386 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 28301 | /* 78391 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28302 | /* 78394 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28303 | /* 78397 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28304 | /* 78400 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28305 | /* 78403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28306 | /* 78407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28307 | /* 78411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28308 | /* 78415 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28309 | /* 78419 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 28310 | /* 78419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX), |
| 28311 | /* 78422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28312 | /* 78424 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 28313 | /* 78426 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 28314 | /* 78428 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 28315 | /* 78430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28316 | /* 78433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28317 | /* 78439 */ GIR_RootConstrainSelectedInstOperands, |
| 28318 | /* 78440 */ // GIR_Coverage, 2085, |
| 28319 | /* 78440 */ GIR_EraseRootFromParent_Done, |
| 28320 | /* 78441 */ // Label 1579: @78441 |
| 28321 | /* 78441 */ GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(78504), // Rule ID 2086 // |
| 28322 | /* 78446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 28323 | /* 78449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 28324 | /* 78454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28325 | /* 78457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28326 | /* 78460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28327 | /* 78463 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28328 | /* 78466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28329 | /* 78470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28330 | /* 78474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28331 | /* 78478 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28332 | /* 78482 */ // (intrinsic_wo_chain:{ *:[i32] } 4143:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 28333 | /* 78482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD), |
| 28334 | /* 78485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28335 | /* 78487 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 28336 | /* 78489 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 28337 | /* 78491 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 28338 | /* 78493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28339 | /* 78496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28340 | /* 78502 */ GIR_RootConstrainSelectedInstOperands, |
| 28341 | /* 78503 */ // GIR_Coverage, 2086, |
| 28342 | /* 78503 */ GIR_EraseRootFromParent_Done, |
| 28343 | /* 78504 */ // Label 1580: @78504 |
| 28344 | /* 78504 */ GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(78567), // Rule ID 2087 // |
| 28345 | /* 78509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 28346 | /* 78512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 28347 | /* 78517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28348 | /* 78520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28349 | /* 78523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28350 | /* 78526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28351 | /* 78529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28352 | /* 78533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28353 | /* 78537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28354 | /* 78541 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28355 | /* 78545 */ // (intrinsic_wo_chain:{ *:[i32] } 4144:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 28356 | /* 78545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX), |
| 28357 | /* 78548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28358 | /* 78550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 28359 | /* 78552 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 28360 | /* 78554 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 28361 | /* 78556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28362 | /* 78559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28363 | /* 78565 */ GIR_RootConstrainSelectedInstOperands, |
| 28364 | /* 78566 */ // GIR_Coverage, 2087, |
| 28365 | /* 78566 */ GIR_EraseRootFromParent_Done, |
| 28366 | /* 78567 */ // Label 1581: @78567 |
| 28367 | /* 78567 */ GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(78630), // Rule ID 2175 // |
| 28368 | /* 78572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 28369 | /* 78575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 28370 | /* 78580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28371 | /* 78583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28372 | /* 78586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28373 | /* 78589 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28374 | /* 78592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28375 | /* 78596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28376 | /* 78600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28377 | /* 78604 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28378 | /* 78608 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28379 | /* 78608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 28380 | /* 78611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28381 | /* 78613 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28382 | /* 78615 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28383 | /* 78617 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28384 | /* 78619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28385 | /* 78622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28386 | /* 78628 */ GIR_RootConstrainSelectedInstOperands, |
| 28387 | /* 78629 */ // GIR_Coverage, 2175, |
| 28388 | /* 78629 */ GIR_EraseRootFromParent_Done, |
| 28389 | /* 78630 */ // Label 1582: @78630 |
| 28390 | /* 78630 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(78693), // Rule ID 2176 // |
| 28391 | /* 78635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 28392 | /* 78638 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 28393 | /* 78643 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28394 | /* 78646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28395 | /* 78649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28396 | /* 78652 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28397 | /* 78655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28398 | /* 78659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28399 | /* 78663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28400 | /* 78667 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28401 | /* 78671 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28402 | /* 78671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 28403 | /* 78674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28404 | /* 78676 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28405 | /* 78678 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28406 | /* 78680 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28407 | /* 78682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28408 | /* 78685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28409 | /* 78691 */ GIR_RootConstrainSelectedInstOperands, |
| 28410 | /* 78692 */ // GIR_Coverage, 2176, |
| 28411 | /* 78692 */ GIR_EraseRootFromParent_Done, |
| 28412 | /* 78693 */ // Label 1583: @78693 |
| 28413 | /* 78693 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(78756), // Rule ID 2177 // |
| 28414 | /* 78698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 28415 | /* 78701 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 28416 | /* 78706 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28417 | /* 78709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28418 | /* 78712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28419 | /* 78715 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28420 | /* 78718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28421 | /* 78722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28422 | /* 78726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28423 | /* 78730 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28424 | /* 78734 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28425 | /* 78734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 28426 | /* 78737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28427 | /* 78739 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28428 | /* 78741 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28429 | /* 78743 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28430 | /* 78745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28431 | /* 78748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28432 | /* 78754 */ GIR_RootConstrainSelectedInstOperands, |
| 28433 | /* 78755 */ // GIR_Coverage, 2177, |
| 28434 | /* 78755 */ GIR_EraseRootFromParent_Done, |
| 28435 | /* 78756 */ // Label 1584: @78756 |
| 28436 | /* 78756 */ GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(78819), // Rule ID 2178 // |
| 28437 | /* 78761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 28438 | /* 78764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 28439 | /* 78769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28440 | /* 78772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28441 | /* 78775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28442 | /* 78778 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28443 | /* 78781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28444 | /* 78785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28445 | /* 78789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28446 | /* 78793 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28447 | /* 78797 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28448 | /* 78797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 28449 | /* 78800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28450 | /* 78802 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28451 | /* 78804 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28452 | /* 78806 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28453 | /* 78808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28454 | /* 78811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28455 | /* 78817 */ GIR_RootConstrainSelectedInstOperands, |
| 28456 | /* 78818 */ // GIR_Coverage, 2178, |
| 28457 | /* 78818 */ GIR_EraseRootFromParent_Done, |
| 28458 | /* 78819 */ // Label 1585: @78819 |
| 28459 | /* 78819 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(78882), // Rule ID 2179 // |
| 28460 | /* 78824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 28461 | /* 78827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 28462 | /* 78832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28463 | /* 78835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28464 | /* 78838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28465 | /* 78841 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28466 | /* 78844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28467 | /* 78848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28468 | /* 78852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28469 | /* 78856 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28470 | /* 78860 */ // (intrinsic_wo_chain:{ *:[i32] } 4141:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28471 | /* 78860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB), |
| 28472 | /* 78863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28473 | /* 78865 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28474 | /* 78867 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28475 | /* 78869 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28476 | /* 78871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28477 | /* 78874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28478 | /* 78880 */ GIR_RootConstrainSelectedInstOperands, |
| 28479 | /* 78881 */ // GIR_Coverage, 2179, |
| 28480 | /* 78881 */ GIR_EraseRootFromParent_Done, |
| 28481 | /* 78882 */ // Label 1586: @78882 |
| 28482 | /* 78882 */ GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(78945), // Rule ID 2180 // |
| 28483 | /* 78887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 28484 | /* 78890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 28485 | /* 78895 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28486 | /* 78898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28487 | /* 78901 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28488 | /* 78904 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28489 | /* 78907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 28490 | /* 78911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28491 | /* 78915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28492 | /* 78919 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28493 | /* 78923 */ // (intrinsic_wo_chain:{ *:[i32] } 4142:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28494 | /* 78923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT), |
| 28495 | /* 78926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28496 | /* 78928 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28497 | /* 78930 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28498 | /* 78932 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28499 | /* 78934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28500 | /* 78937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28501 | /* 78943 */ GIR_RootConstrainSelectedInstOperands, |
| 28502 | /* 78944 */ // GIR_Coverage, 2180, |
| 28503 | /* 78944 */ GIR_EraseRootFromParent_Done, |
| 28504 | /* 78945 */ // Label 1587: @78945 |
| 28505 | /* 78945 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(79008), // Rule ID 2366 // |
| 28506 | /* 78950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 28507 | /* 78953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 28508 | /* 78958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28509 | /* 78961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28510 | /* 78964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28511 | /* 78967 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28512 | /* 78970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28513 | /* 78974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28514 | /* 78978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28515 | /* 78982 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28516 | /* 78986 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28517 | /* 78986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 28518 | /* 78989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28519 | /* 78991 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28520 | /* 78993 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28521 | /* 78995 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28522 | /* 78997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28523 | /* 79000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28524 | /* 79006 */ GIR_RootConstrainSelectedInstOperands, |
| 28525 | /* 79007 */ // GIR_Coverage, 2366, |
| 28526 | /* 79007 */ GIR_EraseRootFromParent_Done, |
| 28527 | /* 79008 */ // Label 1588: @79008 |
| 28528 | /* 79008 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(79071), // Rule ID 2367 // |
| 28529 | /* 79013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 28530 | /* 79016 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 28531 | /* 79021 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28532 | /* 79024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28533 | /* 79027 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28534 | /* 79030 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28535 | /* 79033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28536 | /* 79037 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28537 | /* 79041 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28538 | /* 79045 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28539 | /* 79049 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28540 | /* 79049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 28541 | /* 79052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28542 | /* 79054 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28543 | /* 79056 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28544 | /* 79058 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28545 | /* 79060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28546 | /* 79063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28547 | /* 79069 */ GIR_RootConstrainSelectedInstOperands, |
| 28548 | /* 79070 */ // GIR_Coverage, 2367, |
| 28549 | /* 79070 */ GIR_EraseRootFromParent_Done, |
| 28550 | /* 79071 */ // Label 1589: @79071 |
| 28551 | /* 79071 */ GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(79134), // Rule ID 2368 // |
| 28552 | /* 79076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 28553 | /* 79079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 28554 | /* 79084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28555 | /* 79087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28556 | /* 79090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28557 | /* 79093 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28558 | /* 79096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28559 | /* 79100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28560 | /* 79104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28561 | /* 79108 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28562 | /* 79112 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28563 | /* 79112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 28564 | /* 79115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28565 | /* 79117 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28566 | /* 79119 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28567 | /* 79121 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28568 | /* 79123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28569 | /* 79126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28570 | /* 79132 */ GIR_RootConstrainSelectedInstOperands, |
| 28571 | /* 79133 */ // GIR_Coverage, 2368, |
| 28572 | /* 79133 */ GIR_EraseRootFromParent_Done, |
| 28573 | /* 79134 */ // Label 1590: @79134 |
| 28574 | /* 79134 */ GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(79197), // Rule ID 2369 // |
| 28575 | /* 79139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 28576 | /* 79142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 28577 | /* 79147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28578 | /* 79150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28579 | /* 79153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28580 | /* 79156 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28581 | /* 79159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28582 | /* 79163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28583 | /* 79167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28584 | /* 79171 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28585 | /* 79175 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28586 | /* 79175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 28587 | /* 79178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28588 | /* 79180 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28589 | /* 79182 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28590 | /* 79184 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28591 | /* 79186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28592 | /* 79189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28593 | /* 79195 */ GIR_RootConstrainSelectedInstOperands, |
| 28594 | /* 79196 */ // GIR_Coverage, 2369, |
| 28595 | /* 79196 */ GIR_EraseRootFromParent_Done, |
| 28596 | /* 79197 */ // Label 1591: @79197 |
| 28597 | /* 79197 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(79260), // Rule ID 2370 // |
| 28598 | /* 79202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 28599 | /* 79205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 28600 | /* 79210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28601 | /* 79213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28602 | /* 79216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28603 | /* 79219 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28604 | /* 79222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28605 | /* 79226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28606 | /* 79230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28607 | /* 79234 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28608 | /* 79238 */ // (intrinsic_wo_chain:{ *:[i32] } 4141:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28609 | /* 79238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB), |
| 28610 | /* 79241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28611 | /* 79243 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28612 | /* 79245 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28613 | /* 79247 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28614 | /* 79249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28615 | /* 79252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28616 | /* 79258 */ GIR_RootConstrainSelectedInstOperands, |
| 28617 | /* 79259 */ // GIR_Coverage, 2370, |
| 28618 | /* 79259 */ GIR_EraseRootFromParent_Done, |
| 28619 | /* 79260 */ // Label 1592: @79260 |
| 28620 | /* 79260 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(79323), // Rule ID 2371 // |
| 28621 | /* 79265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 28622 | /* 79268 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 28623 | /* 79273 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28624 | /* 79276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28625 | /* 79279 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28626 | /* 79282 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28627 | /* 79285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28628 | /* 79289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28629 | /* 79293 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28630 | /* 79297 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 28631 | /* 79301 */ // (intrinsic_wo_chain:{ *:[i32] } 4142:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 28632 | /* 79301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT), |
| 28633 | /* 79304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 28634 | /* 79306 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 28635 | /* 79308 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 28636 | /* 79310 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 28637 | /* 79312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28638 | /* 79315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28639 | /* 79321 */ GIR_RootConstrainSelectedInstOperands, |
| 28640 | /* 79322 */ // GIR_Coverage, 2371, |
| 28641 | /* 79322 */ GIR_EraseRootFromParent_Done, |
| 28642 | /* 79323 */ // Label 1593: @79323 |
| 28643 | /* 79323 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(79386), // Rule ID 2841 // |
| 28644 | /* 79328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28645 | /* 79331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 28646 | /* 79336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 28647 | /* 79339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 28648 | /* 79342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 28649 | /* 79345 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 28650 | /* 79348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28651 | /* 79352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28652 | /* 79356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28653 | /* 79360 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28654 | /* 79364 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4068:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 28655 | /* 79364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16), |
| 28656 | /* 79367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28657 | /* 79369 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28658 | /* 79371 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28659 | /* 79373 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28660 | /* 79375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28661 | /* 79378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28662 | /* 79384 */ GIR_RootConstrainSelectedInstOperands, |
| 28663 | /* 79385 */ // GIR_Coverage, 2841, |
| 28664 | /* 79385 */ GIR_EraseRootFromParent_Done, |
| 28665 | /* 79386 */ // Label 1594: @79386 |
| 28666 | /* 79386 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(79449), // Rule ID 2842 // |
| 28667 | /* 79391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28668 | /* 79394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 28669 | /* 79399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 28670 | /* 79402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 28671 | /* 79405 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 28672 | /* 79408 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 28673 | /* 79411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28674 | /* 79415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28675 | /* 79419 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28676 | /* 79423 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28677 | /* 79427 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4068:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 28678 | /* 79427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32), |
| 28679 | /* 79430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28680 | /* 79432 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28681 | /* 79434 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28682 | /* 79436 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28683 | /* 79438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28684 | /* 79441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28685 | /* 79447 */ GIR_RootConstrainSelectedInstOperands, |
| 28686 | /* 79448 */ // GIR_Coverage, 2842, |
| 28687 | /* 79448 */ GIR_EraseRootFromParent_Done, |
| 28688 | /* 79449 */ // Label 1595: @79449 |
| 28689 | /* 79449 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(79512), // Rule ID 2843 // |
| 28690 | /* 79454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28691 | /* 79457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 28692 | /* 79462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28693 | /* 79465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28694 | /* 79468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28695 | /* 79471 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 28696 | /* 79474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28697 | /* 79478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28698 | /* 79482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28699 | /* 79486 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28700 | /* 79490 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4068:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 28701 | /* 79490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16), |
| 28702 | /* 79493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28703 | /* 79495 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28704 | /* 79497 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28705 | /* 79499 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28706 | /* 79501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28707 | /* 79504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28708 | /* 79510 */ GIR_RootConstrainSelectedInstOperands, |
| 28709 | /* 79511 */ // GIR_Coverage, 2843, |
| 28710 | /* 79511 */ GIR_EraseRootFromParent_Done, |
| 28711 | /* 79512 */ // Label 1596: @79512 |
| 28712 | /* 79512 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(79575), // Rule ID 2844 // |
| 28713 | /* 79517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28714 | /* 79520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 28715 | /* 79525 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28716 | /* 79528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28717 | /* 79531 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28718 | /* 79534 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28719 | /* 79537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28720 | /* 79541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28721 | /* 79545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28722 | /* 79549 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28723 | /* 79553 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4068:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 28724 | /* 79553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32), |
| 28725 | /* 79556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28726 | /* 79558 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28727 | /* 79560 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28728 | /* 79562 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28729 | /* 79564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28730 | /* 79567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28731 | /* 79573 */ GIR_RootConstrainSelectedInstOperands, |
| 28732 | /* 79574 */ // GIR_Coverage, 2844, |
| 28733 | /* 79574 */ GIR_EraseRootFromParent_Done, |
| 28734 | /* 79575 */ // Label 1597: @79575 |
| 28735 | /* 79575 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(79638), // Rule ID 2849 // |
| 28736 | /* 79580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28737 | /* 79583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 28738 | /* 79588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 28739 | /* 79591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 28740 | /* 79594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 28741 | /* 79597 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 28742 | /* 79600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28743 | /* 79604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28744 | /* 79608 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28745 | /* 79612 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28746 | /* 79616 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4069:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 28747 | /* 79616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16), |
| 28748 | /* 79619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28749 | /* 79621 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28750 | /* 79623 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28751 | /* 79625 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28752 | /* 79627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28753 | /* 79630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28754 | /* 79636 */ GIR_RootConstrainSelectedInstOperands, |
| 28755 | /* 79637 */ // GIR_Coverage, 2849, |
| 28756 | /* 79637 */ GIR_EraseRootFromParent_Done, |
| 28757 | /* 79638 */ // Label 1598: @79638 |
| 28758 | /* 79638 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(79701), // Rule ID 2850 // |
| 28759 | /* 79643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28760 | /* 79646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 28761 | /* 79651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 28762 | /* 79654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 28763 | /* 79657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 28764 | /* 79660 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 28765 | /* 79663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28766 | /* 79667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28767 | /* 79671 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28768 | /* 79675 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28769 | /* 79679 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4069:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 28770 | /* 79679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32), |
| 28771 | /* 79682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28772 | /* 79684 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28773 | /* 79686 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28774 | /* 79688 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28775 | /* 79690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28776 | /* 79693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28777 | /* 79699 */ GIR_RootConstrainSelectedInstOperands, |
| 28778 | /* 79700 */ // GIR_Coverage, 2850, |
| 28779 | /* 79700 */ GIR_EraseRootFromParent_Done, |
| 28780 | /* 79701 */ // Label 1599: @79701 |
| 28781 | /* 79701 */ GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(79764), // Rule ID 2851 // |
| 28782 | /* 79706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28783 | /* 79709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 28784 | /* 79714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28785 | /* 79717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28786 | /* 79720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28787 | /* 79723 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 28788 | /* 79726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28789 | /* 79730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28790 | /* 79734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28791 | /* 79738 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28792 | /* 79742 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4069:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 28793 | /* 79742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16), |
| 28794 | /* 79745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28795 | /* 79747 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28796 | /* 79749 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28797 | /* 79751 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28798 | /* 79753 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28799 | /* 79756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28800 | /* 79762 */ GIR_RootConstrainSelectedInstOperands, |
| 28801 | /* 79763 */ // GIR_Coverage, 2851, |
| 28802 | /* 79763 */ GIR_EraseRootFromParent_Done, |
| 28803 | /* 79764 */ // Label 1600: @79764 |
| 28804 | /* 79764 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(79827), // Rule ID 2852 // |
| 28805 | /* 79769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 28806 | /* 79772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 28807 | /* 79777 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28808 | /* 79780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28809 | /* 79783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28810 | /* 79786 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28811 | /* 79789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28812 | /* 79793 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28813 | /* 79797 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28814 | /* 79801 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28815 | /* 79805 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4069:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 28816 | /* 79805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32), |
| 28817 | /* 79808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28818 | /* 79810 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 28819 | /* 79812 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 28820 | /* 79814 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 28821 | /* 79816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28822 | /* 79819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28823 | /* 79825 */ GIR_RootConstrainSelectedInstOperands, |
| 28824 | /* 79826 */ // GIR_Coverage, 2852, |
| 28825 | /* 79826 */ GIR_EraseRootFromParent_Done, |
| 28826 | /* 79827 */ // Label 1601: @79827 |
| 28827 | /* 79827 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(79896), // Rule ID 4421 // |
| 28828 | /* 79832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 28829 | /* 79835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 28830 | /* 79840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28831 | /* 79843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28832 | /* 79846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28833 | /* 79849 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28834 | /* 79852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28835 | /* 79856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28836 | /* 79860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28837 | /* 79864 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28838 | /* 79868 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3783:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 28839 | /* 79868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 28840 | /* 79871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28841 | /* 79873 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 28842 | /* 79875 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 28843 | /* 79877 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 28844 | /* 79879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28845 | /* 79882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28846 | /* 79888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28847 | /* 79894 */ GIR_RootConstrainSelectedInstOperands, |
| 28848 | /* 79895 */ // GIR_Coverage, 4421, |
| 28849 | /* 79895 */ GIR_EraseRootFromParent_Done, |
| 28850 | /* 79896 */ // Label 1602: @79896 |
| 28851 | /* 79896 */ GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(79965), // Rule ID 4425 // |
| 28852 | /* 79901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 28853 | /* 79904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 28854 | /* 79909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28855 | /* 79912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28856 | /* 79915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28857 | /* 79918 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 28858 | /* 79921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28859 | /* 79925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28860 | /* 79929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28861 | /* 79933 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28862 | /* 79937 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3783:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 28863 | /* 79937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 28864 | /* 79940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28865 | /* 79942 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 28866 | /* 79944 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 28867 | /* 79946 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 28868 | /* 79948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28869 | /* 79951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28870 | /* 79957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28871 | /* 79963 */ GIR_RootConstrainSelectedInstOperands, |
| 28872 | /* 79964 */ // GIR_Coverage, 4425, |
| 28873 | /* 79964 */ GIR_EraseRootFromParent_Done, |
| 28874 | /* 79965 */ // Label 1603: @79965 |
| 28875 | /* 79965 */ GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(80034), // Rule ID 5354 // |
| 28876 | /* 79970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 28877 | /* 79973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 28878 | /* 79978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28879 | /* 79981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28880 | /* 79984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28881 | /* 79987 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28882 | /* 79990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28883 | /* 79994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28884 | /* 79998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28885 | /* 80002 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28886 | /* 80006 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28887 | /* 80006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8), |
| 28888 | /* 80009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28889 | /* 80011 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28890 | /* 80013 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28891 | /* 80015 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28892 | /* 80017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28893 | /* 80020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28894 | /* 80026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28895 | /* 80032 */ GIR_RootConstrainSelectedInstOperands, |
| 28896 | /* 80033 */ // GIR_Coverage, 5354, |
| 28897 | /* 80033 */ GIR_EraseRootFromParent_Done, |
| 28898 | /* 80034 */ // Label 1604: @80034 |
| 28899 | /* 80034 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(80103), // Rule ID 5356 // |
| 28900 | /* 80039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 28901 | /* 80042 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 28902 | /* 80047 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28903 | /* 80050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28904 | /* 80053 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28905 | /* 80056 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28906 | /* 80059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28907 | /* 80063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28908 | /* 80067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28909 | /* 80071 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28910 | /* 80075 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28911 | /* 80075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16), |
| 28912 | /* 80078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28913 | /* 80080 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28914 | /* 80082 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28915 | /* 80084 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28916 | /* 80086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28917 | /* 80089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28918 | /* 80095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28919 | /* 80101 */ GIR_RootConstrainSelectedInstOperands, |
| 28920 | /* 80102 */ // GIR_Coverage, 5356, |
| 28921 | /* 80102 */ GIR_EraseRootFromParent_Done, |
| 28922 | /* 80103 */ // Label 1605: @80103 |
| 28923 | /* 80103 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(80172), // Rule ID 5358 // |
| 28924 | /* 80108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 28925 | /* 80111 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 28926 | /* 80116 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28927 | /* 80119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28928 | /* 80122 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28929 | /* 80125 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28930 | /* 80128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28931 | /* 80132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28932 | /* 80136 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28933 | /* 80140 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28934 | /* 80144 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28935 | /* 80144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32), |
| 28936 | /* 80147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28937 | /* 80149 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28938 | /* 80151 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28939 | /* 80153 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28940 | /* 80155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28941 | /* 80158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28942 | /* 80164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28943 | /* 80170 */ GIR_RootConstrainSelectedInstOperands, |
| 28944 | /* 80171 */ // GIR_Coverage, 5358, |
| 28945 | /* 80171 */ GIR_EraseRootFromParent_Done, |
| 28946 | /* 80172 */ // Label 1606: @80172 |
| 28947 | /* 80172 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(80241), // Rule ID 5360 // |
| 28948 | /* 80177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 28949 | /* 80180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 28950 | /* 80185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28951 | /* 80188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28952 | /* 80191 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28953 | /* 80194 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28954 | /* 80197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28955 | /* 80201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28956 | /* 80205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28957 | /* 80209 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28958 | /* 80213 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3922:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28959 | /* 80213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8), |
| 28960 | /* 80216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28961 | /* 80218 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28962 | /* 80220 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28963 | /* 80222 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28964 | /* 80224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28965 | /* 80227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28966 | /* 80233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28967 | /* 80239 */ GIR_RootConstrainSelectedInstOperands, |
| 28968 | /* 80240 */ // GIR_Coverage, 5360, |
| 28969 | /* 80240 */ GIR_EraseRootFromParent_Done, |
| 28970 | /* 80241 */ // Label 1607: @80241 |
| 28971 | /* 80241 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(80310), // Rule ID 5362 // |
| 28972 | /* 80246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 28973 | /* 80249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 28974 | /* 80254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28975 | /* 80257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28976 | /* 80260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28977 | /* 80263 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28978 | /* 80266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28979 | /* 80270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28980 | /* 80274 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28981 | /* 80278 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28982 | /* 80282 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3922:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28983 | /* 80282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16), |
| 28984 | /* 80285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28985 | /* 80287 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28986 | /* 80289 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28987 | /* 80291 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28988 | /* 80293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28989 | /* 80296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28990 | /* 80302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28991 | /* 80308 */ GIR_RootConstrainSelectedInstOperands, |
| 28992 | /* 80309 */ // GIR_Coverage, 5362, |
| 28993 | /* 80309 */ GIR_EraseRootFromParent_Done, |
| 28994 | /* 80310 */ // Label 1608: @80310 |
| 28995 | /* 80310 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(80379), // Rule ID 5364 // |
| 28996 | /* 80315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 28997 | /* 80318 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 28998 | /* 80323 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28999 | /* 80326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29000 | /* 80329 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29001 | /* 80332 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29002 | /* 80335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29003 | /* 80339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29004 | /* 80343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29005 | /* 80347 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29006 | /* 80351 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3922:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 29007 | /* 80351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32), |
| 29008 | /* 80354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29009 | /* 80356 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 29010 | /* 80358 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 29011 | /* 80360 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 29012 | /* 80362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29013 | /* 80365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29014 | /* 80371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29015 | /* 80377 */ GIR_RootConstrainSelectedInstOperands, |
| 29016 | /* 80378 */ // GIR_Coverage, 5364, |
| 29017 | /* 80378 */ GIR_EraseRootFromParent_Done, |
| 29018 | /* 80379 */ // Label 1609: @80379 |
| 29019 | /* 80379 */ GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(80448), // Rule ID 5366 // |
| 29020 | /* 80384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29021 | /* 80387 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 29022 | /* 80392 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29023 | /* 80395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29024 | /* 80398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29025 | /* 80401 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29026 | /* 80404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29027 | /* 80408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29028 | /* 80412 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29029 | /* 80416 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29030 | /* 80420 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 29031 | /* 80420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8), |
| 29032 | /* 80423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29033 | /* 80425 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 29034 | /* 80427 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 29035 | /* 80429 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 29036 | /* 80431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29037 | /* 80434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29038 | /* 80440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29039 | /* 80446 */ GIR_RootConstrainSelectedInstOperands, |
| 29040 | /* 80447 */ // GIR_Coverage, 5366, |
| 29041 | /* 80447 */ GIR_EraseRootFromParent_Done, |
| 29042 | /* 80448 */ // Label 1610: @80448 |
| 29043 | /* 80448 */ GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(80517), // Rule ID 5368 // |
| 29044 | /* 80453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29045 | /* 80456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 29046 | /* 80461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29047 | /* 80464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29048 | /* 80467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29049 | /* 80470 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29050 | /* 80473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29051 | /* 80477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29052 | /* 80481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29053 | /* 80485 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29054 | /* 80489 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 29055 | /* 80489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16), |
| 29056 | /* 80492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29057 | /* 80494 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 29058 | /* 80496 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 29059 | /* 80498 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 29060 | /* 80500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29061 | /* 80503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29062 | /* 80509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29063 | /* 80515 */ GIR_RootConstrainSelectedInstOperands, |
| 29064 | /* 80516 */ // GIR_Coverage, 5368, |
| 29065 | /* 80516 */ GIR_EraseRootFromParent_Done, |
| 29066 | /* 80517 */ // Label 1611: @80517 |
| 29067 | /* 80517 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(80586), // Rule ID 5370 // |
| 29068 | /* 80522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29069 | /* 80525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 29070 | /* 80530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29071 | /* 80533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29072 | /* 80536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29073 | /* 80539 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29074 | /* 80542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29075 | /* 80546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29076 | /* 80550 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29077 | /* 80554 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29078 | /* 80558 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 29079 | /* 80558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32), |
| 29080 | /* 80561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29081 | /* 80563 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 29082 | /* 80565 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 29083 | /* 80567 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 29084 | /* 80569 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29085 | /* 80572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29086 | /* 80578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29087 | /* 80584 */ GIR_RootConstrainSelectedInstOperands, |
| 29088 | /* 80585 */ // GIR_Coverage, 5370, |
| 29089 | /* 80585 */ GIR_EraseRootFromParent_Done, |
| 29090 | /* 80586 */ // Label 1612: @80586 |
| 29091 | /* 80586 */ GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(80655), // Rule ID 5372 // |
| 29092 | /* 80591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29093 | /* 80594 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 29094 | /* 80599 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29095 | /* 80602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29096 | /* 80605 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29097 | /* 80608 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29098 | /* 80611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29099 | /* 80615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29100 | /* 80619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29101 | /* 80623 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29102 | /* 80627 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 29103 | /* 80627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8), |
| 29104 | /* 80630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29105 | /* 80632 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 29106 | /* 80634 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 29107 | /* 80636 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 29108 | /* 80638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29109 | /* 80641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29110 | /* 80647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29111 | /* 80653 */ GIR_RootConstrainSelectedInstOperands, |
| 29112 | /* 80654 */ // GIR_Coverage, 5372, |
| 29113 | /* 80654 */ GIR_EraseRootFromParent_Done, |
| 29114 | /* 80655 */ // Label 1613: @80655 |
| 29115 | /* 80655 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(80724), // Rule ID 5374 // |
| 29116 | /* 80660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29117 | /* 80663 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 29118 | /* 80668 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29119 | /* 80671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29120 | /* 80674 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29121 | /* 80677 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29122 | /* 80680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29123 | /* 80684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29124 | /* 80688 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29125 | /* 80692 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29126 | /* 80696 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 29127 | /* 80696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16), |
| 29128 | /* 80699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29129 | /* 80701 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 29130 | /* 80703 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 29131 | /* 80705 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 29132 | /* 80707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29133 | /* 80710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29134 | /* 80716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29135 | /* 80722 */ GIR_RootConstrainSelectedInstOperands, |
| 29136 | /* 80723 */ // GIR_Coverage, 5374, |
| 29137 | /* 80723 */ GIR_EraseRootFromParent_Done, |
| 29138 | /* 80724 */ // Label 1614: @80724 |
| 29139 | /* 80724 */ GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(80793), // Rule ID 5376 // |
| 29140 | /* 80729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29141 | /* 80732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 29142 | /* 80737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29143 | /* 80740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29144 | /* 80743 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29145 | /* 80746 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29146 | /* 80749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29147 | /* 80753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29148 | /* 80757 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29149 | /* 80761 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29150 | /* 80765 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3924:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 29151 | /* 80765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32), |
| 29152 | /* 80768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29153 | /* 80770 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 29154 | /* 80772 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 29155 | /* 80774 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 29156 | /* 80776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29157 | /* 80779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29158 | /* 80785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29159 | /* 80791 */ GIR_RootConstrainSelectedInstOperands, |
| 29160 | /* 80792 */ // GIR_Coverage, 5376, |
| 29161 | /* 80792 */ GIR_EraseRootFromParent_Done, |
| 29162 | /* 80793 */ // Label 1615: @80793 |
| 29163 | /* 80793 */ GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(80907), // Rule ID 3068 // |
| 29164 | /* 80798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 29165 | /* 80801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c), |
| 29166 | /* 80806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29167 | /* 80809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29168 | /* 80812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29169 | /* 80815 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29170 | /* 80818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 29171 | /* 80822 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3985:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 29172 | /* 80822 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 29173 | /* 80825 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 29174 | /* 80829 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29175 | /* 80834 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 29176 | /* 80838 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 29177 | /* 80843 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 29178 | /* 80846 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29179 | /* 80850 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29180 | /* 80855 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 29181 | /* 80857 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 29182 | /* 80860 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29183 | /* 80864 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29184 | /* 80869 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 29185 | /* 80872 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 29186 | /* 80875 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 29187 | /* 80878 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 29188 | /* 80883 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 29189 | /* 80888 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 29190 | /* 80893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C), |
| 29191 | /* 80896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 29192 | /* 80898 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 29193 | /* 80900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29194 | /* 80903 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 29195 | /* 80905 */ GIR_RootConstrainSelectedInstOperands, |
| 29196 | /* 80906 */ // GIR_Coverage, 3068, |
| 29197 | /* 80906 */ GIR_EraseRootFromParent_Done, |
| 29198 | /* 80907 */ // Label 1616: @80907 |
| 29199 | /* 80907 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(81021), // Rule ID 3069 // |
| 29200 | /* 80912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 29201 | /* 80915 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m), |
| 29202 | /* 80920 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29203 | /* 80923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29204 | /* 80926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29205 | /* 80929 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29206 | /* 80932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 29207 | /* 80936 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 29208 | /* 80936 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 29209 | /* 80939 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 29210 | /* 80943 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29211 | /* 80948 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 29212 | /* 80952 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 29213 | /* 80957 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 29214 | /* 80960 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29215 | /* 80964 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29216 | /* 80969 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 29217 | /* 80971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 29218 | /* 80974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29219 | /* 80978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29220 | /* 80983 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 29221 | /* 80986 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 29222 | /* 80989 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 29223 | /* 80992 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 29224 | /* 80997 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 29225 | /* 81002 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 29226 | /* 81007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M), |
| 29227 | /* 81010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 29228 | /* 81012 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 29229 | /* 81014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29230 | /* 81017 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 29231 | /* 81019 */ GIR_RootConstrainSelectedInstOperands, |
| 29232 | /* 81020 */ // GIR_Coverage, 3069, |
| 29233 | /* 81020 */ GIR_EraseRootFromParent_Done, |
| 29234 | /* 81021 */ // Label 1617: @81021 |
| 29235 | /* 81021 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(81135), // Rule ID 3070 // |
| 29236 | /* 81026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 29237 | /* 81029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p), |
| 29238 | /* 81034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29239 | /* 81037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29240 | /* 81040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29241 | /* 81043 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29242 | /* 81046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 29243 | /* 81050 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3988:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 29244 | /* 81050 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 29245 | /* 81053 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 29246 | /* 81057 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29247 | /* 81062 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 29248 | /* 81066 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 29249 | /* 81071 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 29250 | /* 81074 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29251 | /* 81078 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29252 | /* 81083 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 29253 | /* 81085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 29254 | /* 81088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29255 | /* 81092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29256 | /* 81097 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 29257 | /* 81100 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 29258 | /* 81103 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 29259 | /* 81106 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 29260 | /* 81111 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 29261 | /* 81116 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 29262 | /* 81121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P), |
| 29263 | /* 81124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 29264 | /* 81126 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 29265 | /* 81128 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29266 | /* 81131 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 29267 | /* 81133 */ GIR_RootConstrainSelectedInstOperands, |
| 29268 | /* 81134 */ // GIR_Coverage, 3070, |
| 29269 | /* 81134 */ GIR_EraseRootFromParent_Done, |
| 29270 | /* 81135 */ // Label 1618: @81135 |
| 29271 | /* 81135 */ GIM_Reject, |
| 29272 | /* 81136 */ // Label 1465: @81136 |
| 29273 | /* 81136 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(84522), |
| 29274 | /* 81141 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 29275 | /* 81144 */ GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(81228), // Rule ID 4109 // |
| 29276 | /* 81149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29277 | /* 81154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29278 | /* 81157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29279 | /* 81160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29280 | /* 81163 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29281 | /* 81166 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29282 | /* 81169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29283 | /* 81173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29284 | /* 81177 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 29285 | /* 81181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29286 | /* 81185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29287 | /* 81189 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 29288 | /* 81189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29289 | /* 81192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29290 | /* 81196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29291 | /* 81201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh), |
| 29292 | /* 81204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29293 | /* 81206 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29294 | /* 81208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29295 | /* 81211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29296 | /* 81217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29297 | /* 81223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29298 | /* 81226 */ GIR_RootConstrainSelectedInstOperands, |
| 29299 | /* 81227 */ // GIR_Coverage, 4109, |
| 29300 | /* 81227 */ GIR_EraseRootFromParent_Done, |
| 29301 | /* 81228 */ // Label 1620: @81228 |
| 29302 | /* 81228 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(81312), // Rule ID 4113 // |
| 29303 | /* 81233 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29304 | /* 81238 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29305 | /* 81241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29306 | /* 81244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29307 | /* 81247 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29308 | /* 81250 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29309 | /* 81253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29310 | /* 81257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29311 | /* 81261 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 29312 | /* 81265 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29313 | /* 81269 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29314 | /* 81273 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 29315 | /* 81273 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29316 | /* 81276 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29317 | /* 81280 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29318 | /* 81285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th), |
| 29319 | /* 81288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29320 | /* 81290 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29321 | /* 81292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29322 | /* 81295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29323 | /* 81301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29324 | /* 81307 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29325 | /* 81310 */ GIR_RootConstrainSelectedInstOperands, |
| 29326 | /* 81311 */ // GIR_Coverage, 4113, |
| 29327 | /* 81311 */ GIR_EraseRootFromParent_Done, |
| 29328 | /* 81312 */ // Label 1621: @81312 |
| 29329 | /* 81312 */ GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(81396), // Rule ID 4117 // |
| 29330 | /* 81317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29331 | /* 81322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29332 | /* 81325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29333 | /* 81328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29334 | /* 81331 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29335 | /* 81334 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29336 | /* 81337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29337 | /* 81341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29338 | /* 81345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 29339 | /* 81349 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29340 | /* 81353 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29341 | /* 81357 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 29342 | /* 81357 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29343 | /* 81360 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29344 | /* 81364 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29345 | /* 81369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh), |
| 29346 | /* 81372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29347 | /* 81374 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29348 | /* 81376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29349 | /* 81379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29350 | /* 81385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29351 | /* 81391 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29352 | /* 81394 */ GIR_RootConstrainSelectedInstOperands, |
| 29353 | /* 81395 */ // GIR_Coverage, 4117, |
| 29354 | /* 81395 */ GIR_EraseRootFromParent_Done, |
| 29355 | /* 81396 */ // Label 1622: @81396 |
| 29356 | /* 81396 */ GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(81480), // Rule ID 4121 // |
| 29357 | /* 81401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29358 | /* 81406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29359 | /* 81409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29360 | /* 81412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29361 | /* 81415 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29362 | /* 81418 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29363 | /* 81421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29364 | /* 81425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29365 | /* 81429 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 29366 | /* 81433 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29367 | /* 81437 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29368 | /* 81441 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 29369 | /* 81441 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29370 | /* 81444 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29371 | /* 81448 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29372 | /* 81453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th), |
| 29373 | /* 81456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29374 | /* 81458 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29375 | /* 81460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29376 | /* 81463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29377 | /* 81469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29378 | /* 81475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29379 | /* 81478 */ GIR_RootConstrainSelectedInstOperands, |
| 29380 | /* 81479 */ // GIR_Coverage, 4121, |
| 29381 | /* 81479 */ GIR_EraseRootFromParent_Done, |
| 29382 | /* 81480 */ // Label 1623: @81480 |
| 29383 | /* 81480 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(81564), // Rule ID 4125 // |
| 29384 | /* 81485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29385 | /* 81490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29386 | /* 81493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29387 | /* 81496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29388 | /* 81499 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29389 | /* 81502 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29390 | /* 81505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29391 | /* 81509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29392 | /* 81513 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 29393 | /* 81517 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29394 | /* 81521 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29395 | /* 81525 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 29396 | /* 81525 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29397 | /* 81528 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29398 | /* 81532 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29399 | /* 81537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh), |
| 29400 | /* 81540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29401 | /* 81542 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29402 | /* 81544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29403 | /* 81547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29404 | /* 81553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29405 | /* 81559 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29406 | /* 81562 */ GIR_RootConstrainSelectedInstOperands, |
| 29407 | /* 81563 */ // GIR_Coverage, 4125, |
| 29408 | /* 81563 */ GIR_EraseRootFromParent_Done, |
| 29409 | /* 81564 */ // Label 1624: @81564 |
| 29410 | /* 81564 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(81648), // Rule ID 4129 // |
| 29411 | /* 81569 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29412 | /* 81574 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29413 | /* 81577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29414 | /* 81580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29415 | /* 81583 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29416 | /* 81586 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29417 | /* 81589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29418 | /* 81593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29419 | /* 81597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 29420 | /* 81601 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29421 | /* 81605 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29422 | /* 81609 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 29423 | /* 81609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29424 | /* 81612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29425 | /* 81616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29426 | /* 81621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th), |
| 29427 | /* 81624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29428 | /* 81626 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29429 | /* 81628 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29430 | /* 81631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29431 | /* 81637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29432 | /* 81643 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29433 | /* 81646 */ GIR_RootConstrainSelectedInstOperands, |
| 29434 | /* 81647 */ // GIR_Coverage, 4129, |
| 29435 | /* 81647 */ GIR_EraseRootFromParent_Done, |
| 29436 | /* 81648 */ // Label 1625: @81648 |
| 29437 | /* 81648 */ GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(81732), // Rule ID 4133 // |
| 29438 | /* 81653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29439 | /* 81658 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29440 | /* 81661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29441 | /* 81664 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29442 | /* 81667 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29443 | /* 81670 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29444 | /* 81673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29445 | /* 81677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29446 | /* 81681 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 29447 | /* 81685 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29448 | /* 81689 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29449 | /* 81693 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 29450 | /* 81693 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29451 | /* 81696 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29452 | /* 81700 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29453 | /* 81705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh), |
| 29454 | /* 81708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29455 | /* 81710 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29456 | /* 81712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29457 | /* 81715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29458 | /* 81721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29459 | /* 81727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29460 | /* 81730 */ GIR_RootConstrainSelectedInstOperands, |
| 29461 | /* 81731 */ // GIR_Coverage, 4133, |
| 29462 | /* 81731 */ GIR_EraseRootFromParent_Done, |
| 29463 | /* 81732 */ // Label 1626: @81732 |
| 29464 | /* 81732 */ GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(81816), // Rule ID 4137 // |
| 29465 | /* 81737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 29466 | /* 81742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29467 | /* 81745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29468 | /* 81748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29469 | /* 81751 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29470 | /* 81754 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29471 | /* 81757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29472 | /* 81761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29473 | /* 81765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 29474 | /* 81769 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29475 | /* 81773 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29476 | /* 81777 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 29477 | /* 81777 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29478 | /* 81780 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29479 | /* 81784 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29480 | /* 81789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th), |
| 29481 | /* 81792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29482 | /* 81794 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 29483 | /* 81796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29484 | /* 81799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29485 | /* 81805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29486 | /* 81811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29487 | /* 81814 */ GIR_RootConstrainSelectedInstOperands, |
| 29488 | /* 81815 */ // GIR_Coverage, 4137, |
| 29489 | /* 81815 */ GIR_EraseRootFromParent_Done, |
| 29490 | /* 81816 */ // Label 1627: @81816 |
| 29491 | /* 81816 */ GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(81905), // Rule ID 4877 // |
| 29492 | /* 81821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29493 | /* 81824 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29494 | /* 81829 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29495 | /* 81832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29496 | /* 81835 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29497 | /* 81838 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29498 | /* 81841 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29499 | /* 81844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29500 | /* 81848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29501 | /* 81852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29502 | /* 81856 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29503 | /* 81860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29504 | /* 81864 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 29505 | /* 81864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29506 | /* 81867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29507 | /* 81871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29508 | /* 81876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 29509 | /* 81879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29510 | /* 81881 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29511 | /* 81883 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29512 | /* 81885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29513 | /* 81888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29514 | /* 81894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29515 | /* 81900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29516 | /* 81903 */ GIR_RootConstrainSelectedInstOperands, |
| 29517 | /* 81904 */ // GIR_Coverage, 4877, |
| 29518 | /* 81904 */ GIR_EraseRootFromParent_Done, |
| 29519 | /* 81905 */ // Label 1628: @81905 |
| 29520 | /* 81905 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(81994), // Rule ID 4879 // |
| 29521 | /* 81910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29522 | /* 81913 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29523 | /* 81918 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29524 | /* 81921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29525 | /* 81924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29526 | /* 81927 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29527 | /* 81930 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29528 | /* 81933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29529 | /* 81937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29530 | /* 81941 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29531 | /* 81945 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29532 | /* 81949 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29533 | /* 81953 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 29534 | /* 81953 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29535 | /* 81956 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29536 | /* 81960 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29537 | /* 81965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8), |
| 29538 | /* 81968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29539 | /* 81970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29540 | /* 81972 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29541 | /* 81974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29542 | /* 81977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29543 | /* 81983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29544 | /* 81989 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29545 | /* 81992 */ GIR_RootConstrainSelectedInstOperands, |
| 29546 | /* 81993 */ // GIR_Coverage, 4879, |
| 29547 | /* 81993 */ GIR_EraseRootFromParent_Done, |
| 29548 | /* 81994 */ // Label 1629: @81994 |
| 29549 | /* 81994 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(82083), // Rule ID 4881 // |
| 29550 | /* 81999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29551 | /* 82002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29552 | /* 82007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29553 | /* 82010 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29554 | /* 82013 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29555 | /* 82016 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29556 | /* 82019 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29557 | /* 82022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29558 | /* 82026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29559 | /* 82030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29560 | /* 82034 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29561 | /* 82038 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29562 | /* 82042 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 29563 | /* 82042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29564 | /* 82045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29565 | /* 82049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29566 | /* 82054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 29567 | /* 82057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29568 | /* 82059 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29569 | /* 82061 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29570 | /* 82063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29571 | /* 82066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29572 | /* 82072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29573 | /* 82078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29574 | /* 82081 */ GIR_RootConstrainSelectedInstOperands, |
| 29575 | /* 82082 */ // GIR_Coverage, 4881, |
| 29576 | /* 82082 */ GIR_EraseRootFromParent_Done, |
| 29577 | /* 82083 */ // Label 1630: @82083 |
| 29578 | /* 82083 */ GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(82172), // Rule ID 4883 // |
| 29579 | /* 82088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29580 | /* 82091 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29581 | /* 82096 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29582 | /* 82099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29583 | /* 82102 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29584 | /* 82105 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29585 | /* 82108 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29586 | /* 82111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29587 | /* 82115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29588 | /* 82119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29589 | /* 82123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29590 | /* 82127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29591 | /* 82131 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 29592 | /* 82131 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29593 | /* 82134 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29594 | /* 82138 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29595 | /* 82143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16), |
| 29596 | /* 82146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29597 | /* 82148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29598 | /* 82150 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29599 | /* 82152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29600 | /* 82155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29601 | /* 82161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29602 | /* 82167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29603 | /* 82170 */ GIR_RootConstrainSelectedInstOperands, |
| 29604 | /* 82171 */ // GIR_Coverage, 4883, |
| 29605 | /* 82171 */ GIR_EraseRootFromParent_Done, |
| 29606 | /* 82172 */ // Label 1631: @82172 |
| 29607 | /* 82172 */ GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(82261), // Rule ID 4885 // |
| 29608 | /* 82177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29609 | /* 82180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29610 | /* 82185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 29611 | /* 82188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29612 | /* 82191 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29613 | /* 82194 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29614 | /* 82197 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29615 | /* 82200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29616 | /* 82204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29617 | /* 82208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29618 | /* 82212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29619 | /* 82216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29620 | /* 82220 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 29621 | /* 82220 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29622 | /* 82223 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29623 | /* 82227 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29624 | /* 82232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32), |
| 29625 | /* 82235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29626 | /* 82237 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29627 | /* 82239 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29628 | /* 82241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29629 | /* 82244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29630 | /* 82250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29631 | /* 82256 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29632 | /* 82259 */ GIR_RootConstrainSelectedInstOperands, |
| 29633 | /* 82260 */ // GIR_Coverage, 4885, |
| 29634 | /* 82260 */ GIR_EraseRootFromParent_Done, |
| 29635 | /* 82261 */ // Label 1632: @82261 |
| 29636 | /* 82261 */ GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(82350), // Rule ID 4887 // |
| 29637 | /* 82266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29638 | /* 82269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29639 | /* 82274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 29640 | /* 82277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29641 | /* 82280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29642 | /* 82283 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29643 | /* 82286 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29644 | /* 82289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29645 | /* 82293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29646 | /* 82297 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29647 | /* 82301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29648 | /* 82305 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29649 | /* 82309 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 29650 | /* 82309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29651 | /* 82312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29652 | /* 82316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29653 | /* 82321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32), |
| 29654 | /* 82324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29655 | /* 82326 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29656 | /* 82328 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29657 | /* 82330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29658 | /* 82333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29659 | /* 82339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29660 | /* 82345 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29661 | /* 82348 */ GIR_RootConstrainSelectedInstOperands, |
| 29662 | /* 82349 */ // GIR_Coverage, 4887, |
| 29663 | /* 82349 */ GIR_EraseRootFromParent_Done, |
| 29664 | /* 82350 */ // Label 1633: @82350 |
| 29665 | /* 82350 */ GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(82439), // Rule ID 4889 // |
| 29666 | /* 82355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29667 | /* 82358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29668 | /* 82363 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29669 | /* 82366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29670 | /* 82369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29671 | /* 82372 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29672 | /* 82375 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29673 | /* 82378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29674 | /* 82382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29675 | /* 82386 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29676 | /* 82390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29677 | /* 82394 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29678 | /* 82398 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 29679 | /* 82398 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29680 | /* 82401 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29681 | /* 82405 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29682 | /* 82410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8), |
| 29683 | /* 82413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29684 | /* 82415 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29685 | /* 82417 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29686 | /* 82419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29687 | /* 82422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29688 | /* 82428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29689 | /* 82434 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29690 | /* 82437 */ GIR_RootConstrainSelectedInstOperands, |
| 29691 | /* 82438 */ // GIR_Coverage, 4889, |
| 29692 | /* 82438 */ GIR_EraseRootFromParent_Done, |
| 29693 | /* 82439 */ // Label 1634: @82439 |
| 29694 | /* 82439 */ GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(82528), // Rule ID 4891 // |
| 29695 | /* 82444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29696 | /* 82447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29697 | /* 82452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29698 | /* 82455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29699 | /* 82458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29700 | /* 82461 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29701 | /* 82464 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29702 | /* 82467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29703 | /* 82471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29704 | /* 82475 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29705 | /* 82479 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29706 | /* 82483 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29707 | /* 82487 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 29708 | /* 82487 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29709 | /* 82490 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29710 | /* 82494 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29711 | /* 82499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8), |
| 29712 | /* 82502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29713 | /* 82504 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29714 | /* 82506 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29715 | /* 82508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29716 | /* 82511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29717 | /* 82517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29718 | /* 82523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29719 | /* 82526 */ GIR_RootConstrainSelectedInstOperands, |
| 29720 | /* 82527 */ // GIR_Coverage, 4891, |
| 29721 | /* 82527 */ GIR_EraseRootFromParent_Done, |
| 29722 | /* 82528 */ // Label 1635: @82528 |
| 29723 | /* 82528 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(82617), // Rule ID 4893 // |
| 29724 | /* 82533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29725 | /* 82536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29726 | /* 82541 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29727 | /* 82544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29728 | /* 82547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29729 | /* 82550 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29730 | /* 82553 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29731 | /* 82556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29732 | /* 82560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29733 | /* 82564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29734 | /* 82568 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29735 | /* 82572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29736 | /* 82576 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 29737 | /* 82576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29738 | /* 82579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29739 | /* 82583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29740 | /* 82588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16), |
| 29741 | /* 82591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29742 | /* 82593 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29743 | /* 82595 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29744 | /* 82597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29745 | /* 82600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29746 | /* 82606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29747 | /* 82612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29748 | /* 82615 */ GIR_RootConstrainSelectedInstOperands, |
| 29749 | /* 82616 */ // GIR_Coverage, 4893, |
| 29750 | /* 82616 */ GIR_EraseRootFromParent_Done, |
| 29751 | /* 82617 */ // Label 1636: @82617 |
| 29752 | /* 82617 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(82706), // Rule ID 4895 // |
| 29753 | /* 82622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29754 | /* 82625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29755 | /* 82630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29756 | /* 82633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29757 | /* 82636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29758 | /* 82639 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29759 | /* 82642 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29760 | /* 82645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29761 | /* 82649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29762 | /* 82653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29763 | /* 82657 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29764 | /* 82661 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29765 | /* 82665 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 29766 | /* 82665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29767 | /* 82668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29768 | /* 82672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29769 | /* 82677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16), |
| 29770 | /* 82680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29771 | /* 82682 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29772 | /* 82684 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29773 | /* 82686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29774 | /* 82689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29775 | /* 82695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29776 | /* 82701 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29777 | /* 82704 */ GIR_RootConstrainSelectedInstOperands, |
| 29778 | /* 82705 */ // GIR_Coverage, 4895, |
| 29779 | /* 82705 */ GIR_EraseRootFromParent_Done, |
| 29780 | /* 82706 */ // Label 1637: @82706 |
| 29781 | /* 82706 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(82795), // Rule ID 4897 // |
| 29782 | /* 82711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29783 | /* 82714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29784 | /* 82719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 29785 | /* 82722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29786 | /* 82725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29787 | /* 82728 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29788 | /* 82731 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29789 | /* 82734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29790 | /* 82738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29791 | /* 82742 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29792 | /* 82746 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29793 | /* 82750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29794 | /* 82754 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 29795 | /* 82754 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29796 | /* 82757 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29797 | /* 82761 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29798 | /* 82766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32), |
| 29799 | /* 82769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29800 | /* 82771 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29801 | /* 82773 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29802 | /* 82775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29803 | /* 82778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29804 | /* 82784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29805 | /* 82790 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29806 | /* 82793 */ GIR_RootConstrainSelectedInstOperands, |
| 29807 | /* 82794 */ // GIR_Coverage, 4897, |
| 29808 | /* 82794 */ GIR_EraseRootFromParent_Done, |
| 29809 | /* 82795 */ // Label 1638: @82795 |
| 29810 | /* 82795 */ GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(82884), // Rule ID 4899 // |
| 29811 | /* 82800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29812 | /* 82803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 29813 | /* 82808 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 29814 | /* 82811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29815 | /* 82814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29816 | /* 82817 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29817 | /* 82820 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29818 | /* 82823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29819 | /* 82827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29820 | /* 82831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29821 | /* 82835 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29822 | /* 82839 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29823 | /* 82843 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3909:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 29824 | /* 82843 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29825 | /* 82846 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29826 | /* 82850 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29827 | /* 82855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32), |
| 29828 | /* 82858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29829 | /* 82860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 29830 | /* 82862 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 29831 | /* 82864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29832 | /* 82867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29833 | /* 82873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29834 | /* 82879 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29835 | /* 82882 */ GIR_RootConstrainSelectedInstOperands, |
| 29836 | /* 82883 */ // GIR_Coverage, 4899, |
| 29837 | /* 82883 */ GIR_EraseRootFromParent_Done, |
| 29838 | /* 82884 */ // Label 1639: @82884 |
| 29839 | /* 82884 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(82982), // Rule ID 4462 // |
| 29840 | /* 82889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 29841 | /* 82892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 29842 | /* 82897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29843 | /* 82900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29844 | /* 82903 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29845 | /* 82906 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 29846 | /* 82909 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 29847 | /* 82912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29848 | /* 82916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29849 | /* 82920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 29850 | /* 82924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29851 | /* 82928 */ // MIs[1] Operand 1 |
| 29852 | /* 82928 */ // No operand predicates |
| 29853 | /* 82928 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29854 | /* 82932 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29855 | /* 82936 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29856 | /* 82938 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29857 | /* 82938 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29858 | /* 82941 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29859 | /* 82945 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29860 | /* 82950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16), |
| 29861 | /* 82953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29862 | /* 82955 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29863 | /* 82957 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29864 | /* 82959 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29865 | /* 82962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29866 | /* 82965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29867 | /* 82971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29868 | /* 82977 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29869 | /* 82980 */ GIR_RootConstrainSelectedInstOperands, |
| 29870 | /* 82981 */ // GIR_Coverage, 4462, |
| 29871 | /* 82981 */ GIR_EraseRootFromParent_Done, |
| 29872 | /* 82982 */ // Label 1640: @82982 |
| 29873 | /* 82982 */ GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(83080), // Rule ID 4464 // |
| 29874 | /* 82987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 29875 | /* 82990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 29876 | /* 82995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29877 | /* 82998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29878 | /* 83001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29879 | /* 83004 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29880 | /* 83007 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 29881 | /* 83010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29882 | /* 83014 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29883 | /* 83018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 29884 | /* 83022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29885 | /* 83026 */ // MIs[1] Operand 1 |
| 29886 | /* 83026 */ // No operand predicates |
| 29887 | /* 83026 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29888 | /* 83030 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29889 | /* 83034 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29890 | /* 83036 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29891 | /* 83036 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29892 | /* 83039 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29893 | /* 83043 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29894 | /* 83048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32), |
| 29895 | /* 83051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29896 | /* 83053 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29897 | /* 83055 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29898 | /* 83057 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29899 | /* 83060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29900 | /* 83063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29901 | /* 83069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29902 | /* 83075 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29903 | /* 83078 */ GIR_RootConstrainSelectedInstOperands, |
| 29904 | /* 83079 */ // GIR_Coverage, 4464, |
| 29905 | /* 83079 */ GIR_EraseRootFromParent_Done, |
| 29906 | /* 83080 */ // Label 1641: @83080 |
| 29907 | /* 83080 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(83178), // Rule ID 5031 // |
| 29908 | /* 83085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29909 | /* 83088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 29910 | /* 83093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29911 | /* 83096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29912 | /* 83099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29913 | /* 83102 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 29914 | /* 83105 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 29915 | /* 83108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29916 | /* 83112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29917 | /* 83116 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 29918 | /* 83120 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29919 | /* 83124 */ // MIs[1] Operand 1 |
| 29920 | /* 83124 */ // No operand predicates |
| 29921 | /* 83124 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29922 | /* 83128 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29923 | /* 83132 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29924 | /* 83134 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29925 | /* 83134 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29926 | /* 83137 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29927 | /* 83141 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29928 | /* 83146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8), |
| 29929 | /* 83149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29930 | /* 83151 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29931 | /* 83153 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29932 | /* 83155 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29933 | /* 83158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29934 | /* 83161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29935 | /* 83167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29936 | /* 83173 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29937 | /* 83176 */ GIR_RootConstrainSelectedInstOperands, |
| 29938 | /* 83177 */ // GIR_Coverage, 5031, |
| 29939 | /* 83177 */ GIR_EraseRootFromParent_Done, |
| 29940 | /* 83178 */ // Label 1642: @83178 |
| 29941 | /* 83178 */ GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(83276), // Rule ID 5033 // |
| 29942 | /* 83183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29943 | /* 83186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 29944 | /* 83191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29945 | /* 83194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29946 | /* 83197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29947 | /* 83200 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 29948 | /* 83203 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 29949 | /* 83206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29950 | /* 83210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29951 | /* 83214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 29952 | /* 83218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29953 | /* 83222 */ // MIs[1] Operand 1 |
| 29954 | /* 83222 */ // No operand predicates |
| 29955 | /* 83222 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29956 | /* 83226 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29957 | /* 83230 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29958 | /* 83232 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29959 | /* 83232 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29960 | /* 83235 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29961 | /* 83239 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29962 | /* 83244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16), |
| 29963 | /* 83247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29964 | /* 83249 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29965 | /* 83251 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29966 | /* 83253 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29967 | /* 83256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29968 | /* 83259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29969 | /* 83265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29970 | /* 83271 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29971 | /* 83274 */ GIR_RootConstrainSelectedInstOperands, |
| 29972 | /* 83275 */ // GIR_Coverage, 5033, |
| 29973 | /* 83275 */ GIR_EraseRootFromParent_Done, |
| 29974 | /* 83276 */ // Label 1643: @83276 |
| 29975 | /* 83276 */ GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(83374), // Rule ID 5035 // |
| 29976 | /* 83281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29977 | /* 83284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 29978 | /* 83289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29979 | /* 83292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29980 | /* 83295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29981 | /* 83298 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29982 | /* 83301 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 29983 | /* 83304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29984 | /* 83308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29985 | /* 83312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 29986 | /* 83316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29987 | /* 83320 */ // MIs[1] Operand 1 |
| 29988 | /* 83320 */ // No operand predicates |
| 29989 | /* 83320 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29990 | /* 83324 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29991 | /* 83328 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29992 | /* 83330 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29993 | /* 83330 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29994 | /* 83333 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29995 | /* 83337 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29996 | /* 83342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32), |
| 29997 | /* 83345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29998 | /* 83347 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29999 | /* 83349 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30000 | /* 83351 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 30001 | /* 83354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30002 | /* 83357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30003 | /* 83363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30004 | /* 83369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30005 | /* 83372 */ GIR_RootConstrainSelectedInstOperands, |
| 30006 | /* 83373 */ // GIR_Coverage, 5035, |
| 30007 | /* 83373 */ GIR_EraseRootFromParent_Done, |
| 30008 | /* 83374 */ // Label 1644: @83374 |
| 30009 | /* 83374 */ GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(83472), // Rule ID 5037 // |
| 30010 | /* 83379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30011 | /* 83382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 30012 | /* 83387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30013 | /* 83390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30014 | /* 83393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30015 | /* 83396 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30016 | /* 83399 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 30017 | /* 83402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30018 | /* 83406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30019 | /* 83410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 30020 | /* 83414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30021 | /* 83418 */ // MIs[1] Operand 1 |
| 30022 | /* 83418 */ // No operand predicates |
| 30023 | /* 83418 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30024 | /* 83422 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30025 | /* 83426 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30026 | /* 83428 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 30027 | /* 83428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30028 | /* 83431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30029 | /* 83435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30030 | /* 83440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8), |
| 30031 | /* 83443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30032 | /* 83445 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30033 | /* 83447 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30034 | /* 83449 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 30035 | /* 83452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30036 | /* 83455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30037 | /* 83461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30038 | /* 83467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30039 | /* 83470 */ GIR_RootConstrainSelectedInstOperands, |
| 30040 | /* 83471 */ // GIR_Coverage, 5037, |
| 30041 | /* 83471 */ GIR_EraseRootFromParent_Done, |
| 30042 | /* 83472 */ // Label 1645: @83472 |
| 30043 | /* 83472 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(83570), // Rule ID 5039 // |
| 30044 | /* 83477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30045 | /* 83480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 30046 | /* 83485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30047 | /* 83488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30048 | /* 83491 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30049 | /* 83494 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30050 | /* 83497 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 30051 | /* 83500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30052 | /* 83504 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30053 | /* 83508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 30054 | /* 83512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30055 | /* 83516 */ // MIs[1] Operand 1 |
| 30056 | /* 83516 */ // No operand predicates |
| 30057 | /* 83516 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30058 | /* 83520 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30059 | /* 83524 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30060 | /* 83526 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 30061 | /* 83526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30062 | /* 83529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30063 | /* 83533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30064 | /* 83538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16), |
| 30065 | /* 83541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30066 | /* 83543 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30067 | /* 83545 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30068 | /* 83547 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 30069 | /* 83550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30070 | /* 83553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30071 | /* 83559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30072 | /* 83565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30073 | /* 83568 */ GIR_RootConstrainSelectedInstOperands, |
| 30074 | /* 83569 */ // GIR_Coverage, 5039, |
| 30075 | /* 83569 */ GIR_EraseRootFromParent_Done, |
| 30076 | /* 83570 */ // Label 1646: @83570 |
| 30077 | /* 83570 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(83668), // Rule ID 5041 // |
| 30078 | /* 83575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30079 | /* 83578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 30080 | /* 83583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30081 | /* 83586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30082 | /* 83589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30083 | /* 83592 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30084 | /* 83595 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 30085 | /* 83598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30086 | /* 83602 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30087 | /* 83606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 30088 | /* 83610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30089 | /* 83614 */ // MIs[1] Operand 1 |
| 30090 | /* 83614 */ // No operand predicates |
| 30091 | /* 83614 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30092 | /* 83618 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30093 | /* 83622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30094 | /* 83624 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 30095 | /* 83624 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30096 | /* 83627 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30097 | /* 83631 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30098 | /* 83636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32), |
| 30099 | /* 83639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30100 | /* 83641 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30101 | /* 83643 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30102 | /* 83645 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 30103 | /* 83648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30104 | /* 83651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30105 | /* 83657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30106 | /* 83663 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30107 | /* 83666 */ GIR_RootConstrainSelectedInstOperands, |
| 30108 | /* 83667 */ // GIR_Coverage, 5041, |
| 30109 | /* 83667 */ GIR_EraseRootFromParent_Done, |
| 30110 | /* 83668 */ // Label 1647: @83668 |
| 30111 | /* 83668 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(83744), // Rule ID 3413 // |
| 30112 | /* 83673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30113 | /* 83676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 30114 | /* 83681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30115 | /* 83684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30116 | /* 83687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30117 | /* 83690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30118 | /* 83693 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 30119 | /* 83696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30120 | /* 83700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30121 | /* 83704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30122 | /* 83708 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30123 | /* 83712 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30124 | /* 83716 */ // (intrinsic_wo_chain:{ *:[i32] } 3839:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30125 | /* 83716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8), |
| 30126 | /* 83719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 30127 | /* 83721 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 30128 | /* 83723 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30129 | /* 83725 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30130 | /* 83727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30131 | /* 83730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30132 | /* 83736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30133 | /* 83742 */ GIR_RootConstrainSelectedInstOperands, |
| 30134 | /* 83743 */ // GIR_Coverage, 3413, |
| 30135 | /* 83743 */ GIR_EraseRootFromParent_Done, |
| 30136 | /* 83744 */ // Label 1648: @83744 |
| 30137 | /* 83744 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(83820), // Rule ID 3415 // |
| 30138 | /* 83749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30139 | /* 83752 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 30140 | /* 83757 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30141 | /* 83760 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30142 | /* 83763 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30143 | /* 83766 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30144 | /* 83769 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 30145 | /* 83772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30146 | /* 83776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30147 | /* 83780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30148 | /* 83784 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30149 | /* 83788 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30150 | /* 83792 */ // (intrinsic_wo_chain:{ *:[i32] } 3839:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30151 | /* 83792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16), |
| 30152 | /* 83795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 30153 | /* 83797 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 30154 | /* 83799 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30155 | /* 83801 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30156 | /* 83803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30157 | /* 83806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30158 | /* 83812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30159 | /* 83818 */ GIR_RootConstrainSelectedInstOperands, |
| 30160 | /* 83819 */ // GIR_Coverage, 3415, |
| 30161 | /* 83819 */ GIR_EraseRootFromParent_Done, |
| 30162 | /* 83820 */ // Label 1649: @83820 |
| 30163 | /* 83820 */ GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(83896), // Rule ID 3417 // |
| 30164 | /* 83825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30165 | /* 83828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 30166 | /* 83833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30167 | /* 83836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30168 | /* 83839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30169 | /* 83842 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30170 | /* 83845 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 30171 | /* 83848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30172 | /* 83852 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30173 | /* 83856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30174 | /* 83860 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30175 | /* 83864 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30176 | /* 83868 */ // (intrinsic_wo_chain:{ *:[i32] } 3839:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 30177 | /* 83868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32), |
| 30178 | /* 83871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 30179 | /* 83873 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 30180 | /* 83875 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30181 | /* 83877 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30182 | /* 83879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30183 | /* 83882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30184 | /* 83888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30185 | /* 83894 */ GIR_RootConstrainSelectedInstOperands, |
| 30186 | /* 83895 */ // GIR_Coverage, 3417, |
| 30187 | /* 83895 */ GIR_EraseRootFromParent_Done, |
| 30188 | /* 83896 */ // Label 1650: @83896 |
| 30189 | /* 83896 */ GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(83972), // Rule ID 3419 // |
| 30190 | /* 83901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30191 | /* 83904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 30192 | /* 83909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30193 | /* 83912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30194 | /* 83915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30195 | /* 83918 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30196 | /* 83921 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 30197 | /* 83924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30198 | /* 83928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30199 | /* 83932 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30200 | /* 83936 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30201 | /* 83940 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30202 | /* 83944 */ // (intrinsic_wo_chain:{ *:[i32] } 3839:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30203 | /* 83944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8), |
| 30204 | /* 83947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 30205 | /* 83949 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 30206 | /* 83951 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30207 | /* 83953 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30208 | /* 83955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30209 | /* 83958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30210 | /* 83964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30211 | /* 83970 */ GIR_RootConstrainSelectedInstOperands, |
| 30212 | /* 83971 */ // GIR_Coverage, 3419, |
| 30213 | /* 83971 */ GIR_EraseRootFromParent_Done, |
| 30214 | /* 83972 */ // Label 1651: @83972 |
| 30215 | /* 83972 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(84048), // Rule ID 3421 // |
| 30216 | /* 83977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30217 | /* 83980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 30218 | /* 83985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30219 | /* 83988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30220 | /* 83991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30221 | /* 83994 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30222 | /* 83997 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 30223 | /* 84000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30224 | /* 84004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30225 | /* 84008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30226 | /* 84012 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30227 | /* 84016 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30228 | /* 84020 */ // (intrinsic_wo_chain:{ *:[i32] } 3839:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30229 | /* 84020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16), |
| 30230 | /* 84023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 30231 | /* 84025 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 30232 | /* 84027 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30233 | /* 84029 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30234 | /* 84031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30235 | /* 84034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30236 | /* 84040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30237 | /* 84046 */ GIR_RootConstrainSelectedInstOperands, |
| 30238 | /* 84047 */ // GIR_Coverage, 3421, |
| 30239 | /* 84047 */ GIR_EraseRootFromParent_Done, |
| 30240 | /* 84048 */ // Label 1652: @84048 |
| 30241 | /* 84048 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(84124), // Rule ID 3423 // |
| 30242 | /* 84053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30243 | /* 84056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 30244 | /* 84061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30245 | /* 84064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30246 | /* 84067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30247 | /* 84070 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30248 | /* 84073 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 30249 | /* 84076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30250 | /* 84080 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30251 | /* 84084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30252 | /* 84088 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30253 | /* 84092 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30254 | /* 84096 */ // (intrinsic_wo_chain:{ *:[i32] } 3839:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 30255 | /* 84096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32), |
| 30256 | /* 84099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 30257 | /* 84101 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 30258 | /* 84103 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30259 | /* 84105 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30260 | /* 84107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30261 | /* 84110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30262 | /* 84116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30263 | /* 84122 */ GIR_RootConstrainSelectedInstOperands, |
| 30264 | /* 84123 */ // GIR_Coverage, 3423, |
| 30265 | /* 84123 */ GIR_EraseRootFromParent_Done, |
| 30266 | /* 84124 */ // Label 1653: @84124 |
| 30267 | /* 84124 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(84209), // Rule ID 4408 // |
| 30268 | /* 84129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 30269 | /* 84132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 30270 | /* 84137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30271 | /* 84140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30272 | /* 84143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30273 | /* 84146 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30274 | /* 84149 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 30275 | /* 84152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30276 | /* 84156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 30277 | /* 84160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30278 | /* 84164 */ // MIs[1] Operand 1 |
| 30279 | /* 84164 */ // No operand predicates |
| 30280 | /* 84164 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30281 | /* 84168 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30282 | /* 84172 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30283 | /* 84176 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30284 | /* 84178 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 30285 | /* 84178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16), |
| 30286 | /* 84181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30287 | /* 84183 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 30288 | /* 84185 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30289 | /* 84187 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30290 | /* 84189 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 30291 | /* 84192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30292 | /* 84195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30293 | /* 84201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30294 | /* 84207 */ GIR_RootConstrainSelectedInstOperands, |
| 30295 | /* 84208 */ // GIR_Coverage, 4408, |
| 30296 | /* 84208 */ GIR_EraseRootFromParent_Done, |
| 30297 | /* 84209 */ // Label 1654: @84209 |
| 30298 | /* 84209 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(84294), // Rule ID 4411 // |
| 30299 | /* 84214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 30300 | /* 84217 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 30301 | /* 84222 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30302 | /* 84225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30303 | /* 84228 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30304 | /* 84231 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30305 | /* 84234 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 30306 | /* 84237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30307 | /* 84241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 30308 | /* 84245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30309 | /* 84249 */ // MIs[1] Operand 1 |
| 30310 | /* 84249 */ // No operand predicates |
| 30311 | /* 84249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30312 | /* 84253 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30313 | /* 84257 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30314 | /* 84261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30315 | /* 84263 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3850:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 30316 | /* 84263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32), |
| 30317 | /* 84266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30318 | /* 84268 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 30319 | /* 84270 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 30320 | /* 84272 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 30321 | /* 84274 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 30322 | /* 84277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30323 | /* 84280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30324 | /* 84286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30325 | /* 84292 */ GIR_RootConstrainSelectedInstOperands, |
| 30326 | /* 84293 */ // GIR_Coverage, 4411, |
| 30327 | /* 84293 */ GIR_EraseRootFromParent_Done, |
| 30328 | /* 84294 */ // Label 1655: @84294 |
| 30329 | /* 84294 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(84390), // Rule ID 3062 // |
| 30330 | /* 84299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 30331 | /* 84302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2), |
| 30332 | /* 84307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 30333 | /* 84310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 30334 | /* 84313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 30335 | /* 84316 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 30336 | /* 84319 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 30337 | /* 84322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 30338 | /* 84326 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4111:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 30339 | /* 84326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 30340 | /* 84329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 30341 | /* 84333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30342 | /* 84338 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 30343 | /* 84342 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 30344 | /* 84345 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 30345 | /* 84349 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 30346 | /* 84352 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 30347 | /* 84357 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 30348 | /* 84362 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 30349 | /* 84367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2), |
| 30350 | /* 84370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 30351 | /* 84372 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 30352 | /* 84374 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30353 | /* 84377 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 30354 | /* 84379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 30355 | /* 84382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30356 | /* 84388 */ GIR_RootConstrainSelectedInstOperands, |
| 30357 | /* 84389 */ // GIR_Coverage, 3062, |
| 30358 | /* 84389 */ GIR_EraseRootFromParent_Done, |
| 30359 | /* 84390 */ // Label 1656: @84390 |
| 30360 | /* 84390 */ GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(84521), // Rule ID 3063 // |
| 30361 | /* 84395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 30362 | /* 84398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3), |
| 30363 | /* 84403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 30364 | /* 84406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 30365 | /* 84409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 30366 | /* 84412 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 30367 | /* 84415 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 30368 | /* 84418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 30369 | /* 84422 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4108:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 30370 | /* 84422 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 30371 | /* 84425 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30372 | /* 84429 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30373 | /* 84434 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 30374 | /* 84436 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 30375 | /* 84439 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 30376 | /* 84443 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30377 | /* 84448 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 30378 | /* 84452 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 30379 | /* 84455 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 30380 | /* 84459 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 30381 | /* 84462 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 30382 | /* 84466 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 30383 | /* 84469 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 30384 | /* 84472 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 30385 | /* 84475 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 30386 | /* 84480 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 30387 | /* 84485 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 30388 | /* 84490 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 30389 | /* 84495 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 30390 | /* 84500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo), |
| 30391 | /* 84503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30392 | /* 84505 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30393 | /* 84508 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 30394 | /* 84510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 30395 | /* 84513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30396 | /* 84519 */ GIR_RootConstrainSelectedInstOperands, |
| 30397 | /* 84520 */ // GIR_Coverage, 3063, |
| 30398 | /* 84520 */ GIR_EraseRootFromParent_Done, |
| 30399 | /* 84521 */ // Label 1657: @84521 |
| 30400 | /* 84521 */ GIM_Reject, |
| 30401 | /* 84522 */ // Label 1619: @84522 |
| 30402 | /* 84522 */ GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(89828), |
| 30403 | /* 84527 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 30404 | /* 84530 */ GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(84623), // Rule ID 4220 // |
| 30405 | /* 84535 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30406 | /* 84540 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30407 | /* 84543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30408 | /* 84546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30409 | /* 84549 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30410 | /* 84552 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30411 | /* 84555 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30412 | /* 84558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30413 | /* 84562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30414 | /* 84566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30415 | /* 84570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30416 | /* 84574 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30417 | /* 84578 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30418 | /* 84582 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 30419 | /* 84582 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30420 | /* 84585 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30421 | /* 84589 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30422 | /* 84594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8), |
| 30423 | /* 84597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30424 | /* 84599 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30425 | /* 84601 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30426 | /* 84603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30427 | /* 84606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30428 | /* 84612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30429 | /* 84618 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30430 | /* 84621 */ GIR_RootConstrainSelectedInstOperands, |
| 30431 | /* 84622 */ // GIR_Coverage, 4220, |
| 30432 | /* 84622 */ GIR_EraseRootFromParent_Done, |
| 30433 | /* 84623 */ // Label 1659: @84623 |
| 30434 | /* 84623 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(84716), // Rule ID 4222 // |
| 30435 | /* 84628 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30436 | /* 84633 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30437 | /* 84636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30438 | /* 84639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30439 | /* 84642 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30440 | /* 84645 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30441 | /* 84648 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30442 | /* 84651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30443 | /* 84655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30444 | /* 84659 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30445 | /* 84663 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30446 | /* 84667 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30447 | /* 84671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30448 | /* 84675 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 30449 | /* 84675 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30450 | /* 84678 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30451 | /* 84682 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30452 | /* 84687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16), |
| 30453 | /* 84690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30454 | /* 84692 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30455 | /* 84694 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30456 | /* 84696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30457 | /* 84699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30458 | /* 84705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30459 | /* 84711 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30460 | /* 84714 */ GIR_RootConstrainSelectedInstOperands, |
| 30461 | /* 84715 */ // GIR_Coverage, 4222, |
| 30462 | /* 84715 */ GIR_EraseRootFromParent_Done, |
| 30463 | /* 84716 */ // Label 1660: @84716 |
| 30464 | /* 84716 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(84809), // Rule ID 4224 // |
| 30465 | /* 84721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30466 | /* 84726 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30467 | /* 84729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30468 | /* 84732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30469 | /* 84735 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30470 | /* 84738 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30471 | /* 84741 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30472 | /* 84744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30473 | /* 84748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30474 | /* 84752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30475 | /* 84756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30476 | /* 84760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30477 | /* 84764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30478 | /* 84768 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 30479 | /* 84768 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30480 | /* 84771 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30481 | /* 84775 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30482 | /* 84780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32), |
| 30483 | /* 84783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30484 | /* 84785 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30485 | /* 84787 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30486 | /* 84789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30487 | /* 84792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30488 | /* 84798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30489 | /* 84804 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30490 | /* 84807 */ GIR_RootConstrainSelectedInstOperands, |
| 30491 | /* 84808 */ // GIR_Coverage, 4224, |
| 30492 | /* 84808 */ GIR_EraseRootFromParent_Done, |
| 30493 | /* 84809 */ // Label 1661: @84809 |
| 30494 | /* 84809 */ GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(84902), // Rule ID 4226 // |
| 30495 | /* 84814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30496 | /* 84819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30497 | /* 84822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30498 | /* 84825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30499 | /* 84828 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30500 | /* 84831 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30501 | /* 84834 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30502 | /* 84837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30503 | /* 84841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30504 | /* 84845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30505 | /* 84849 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30506 | /* 84853 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30507 | /* 84857 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30508 | /* 84861 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 30509 | /* 84861 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30510 | /* 84864 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30511 | /* 84868 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30512 | /* 84873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8), |
| 30513 | /* 84876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30514 | /* 84878 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30515 | /* 84880 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30516 | /* 84882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30517 | /* 84885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30518 | /* 84891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30519 | /* 84897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30520 | /* 84900 */ GIR_RootConstrainSelectedInstOperands, |
| 30521 | /* 84901 */ // GIR_Coverage, 4226, |
| 30522 | /* 84901 */ GIR_EraseRootFromParent_Done, |
| 30523 | /* 84902 */ // Label 1662: @84902 |
| 30524 | /* 84902 */ GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(84995), // Rule ID 4228 // |
| 30525 | /* 84907 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30526 | /* 84912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30527 | /* 84915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30528 | /* 84918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30529 | /* 84921 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30530 | /* 84924 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30531 | /* 84927 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30532 | /* 84930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30533 | /* 84934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30534 | /* 84938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30535 | /* 84942 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30536 | /* 84946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30537 | /* 84950 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30538 | /* 84954 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 30539 | /* 84954 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30540 | /* 84957 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30541 | /* 84961 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30542 | /* 84966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16), |
| 30543 | /* 84969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30544 | /* 84971 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30545 | /* 84973 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30546 | /* 84975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30547 | /* 84978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30548 | /* 84984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30549 | /* 84990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30550 | /* 84993 */ GIR_RootConstrainSelectedInstOperands, |
| 30551 | /* 84994 */ // GIR_Coverage, 4228, |
| 30552 | /* 84994 */ GIR_EraseRootFromParent_Done, |
| 30553 | /* 84995 */ // Label 1663: @84995 |
| 30554 | /* 84995 */ GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(85088), // Rule ID 4230 // |
| 30555 | /* 85000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30556 | /* 85005 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30557 | /* 85008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30558 | /* 85011 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30559 | /* 85014 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30560 | /* 85017 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30561 | /* 85020 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30562 | /* 85023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30563 | /* 85027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30564 | /* 85031 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30565 | /* 85035 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30566 | /* 85039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30567 | /* 85043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30568 | /* 85047 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 30569 | /* 85047 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30570 | /* 85050 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30571 | /* 85054 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30572 | /* 85059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32), |
| 30573 | /* 85062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30574 | /* 85064 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30575 | /* 85066 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30576 | /* 85068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30577 | /* 85071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30578 | /* 85077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30579 | /* 85083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30580 | /* 85086 */ GIR_RootConstrainSelectedInstOperands, |
| 30581 | /* 85087 */ // GIR_Coverage, 4230, |
| 30582 | /* 85087 */ GIR_EraseRootFromParent_Done, |
| 30583 | /* 85088 */ // Label 1664: @85088 |
| 30584 | /* 85088 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(85181), // Rule ID 4232 // |
| 30585 | /* 85093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30586 | /* 85098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30587 | /* 85101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30588 | /* 85104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30589 | /* 85107 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30590 | /* 85110 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30591 | /* 85113 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30592 | /* 85116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30593 | /* 85120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30594 | /* 85124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30595 | /* 85128 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30596 | /* 85132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30597 | /* 85136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30598 | /* 85140 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 30599 | /* 85140 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30600 | /* 85143 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30601 | /* 85147 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30602 | /* 85152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8), |
| 30603 | /* 85155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30604 | /* 85157 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30605 | /* 85159 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30606 | /* 85161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30607 | /* 85164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30608 | /* 85170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30609 | /* 85176 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30610 | /* 85179 */ GIR_RootConstrainSelectedInstOperands, |
| 30611 | /* 85180 */ // GIR_Coverage, 4232, |
| 30612 | /* 85180 */ GIR_EraseRootFromParent_Done, |
| 30613 | /* 85181 */ // Label 1665: @85181 |
| 30614 | /* 85181 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(85274), // Rule ID 4234 // |
| 30615 | /* 85186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30616 | /* 85191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30617 | /* 85194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30618 | /* 85197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30619 | /* 85200 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30620 | /* 85203 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30621 | /* 85206 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30622 | /* 85209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30623 | /* 85213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30624 | /* 85217 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30625 | /* 85221 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30626 | /* 85225 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30627 | /* 85229 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30628 | /* 85233 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 30629 | /* 85233 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30630 | /* 85236 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30631 | /* 85240 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30632 | /* 85245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16), |
| 30633 | /* 85248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30634 | /* 85250 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30635 | /* 85252 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30636 | /* 85254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30637 | /* 85257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30638 | /* 85263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30639 | /* 85269 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30640 | /* 85272 */ GIR_RootConstrainSelectedInstOperands, |
| 30641 | /* 85273 */ // GIR_Coverage, 4234, |
| 30642 | /* 85273 */ GIR_EraseRootFromParent_Done, |
| 30643 | /* 85274 */ // Label 1666: @85274 |
| 30644 | /* 85274 */ GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(85367), // Rule ID 4236 // |
| 30645 | /* 85279 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30646 | /* 85284 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30647 | /* 85287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30648 | /* 85290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30649 | /* 85293 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30650 | /* 85296 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30651 | /* 85299 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30652 | /* 85302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30653 | /* 85306 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30654 | /* 85310 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30655 | /* 85314 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30656 | /* 85318 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30657 | /* 85322 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30658 | /* 85326 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 30659 | /* 85326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30660 | /* 85329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30661 | /* 85333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30662 | /* 85338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32), |
| 30663 | /* 85341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30664 | /* 85343 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30665 | /* 85345 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30666 | /* 85347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30667 | /* 85350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30668 | /* 85356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30669 | /* 85362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30670 | /* 85365 */ GIR_RootConstrainSelectedInstOperands, |
| 30671 | /* 85366 */ // GIR_Coverage, 4236, |
| 30672 | /* 85366 */ GIR_EraseRootFromParent_Done, |
| 30673 | /* 85367 */ // Label 1667: @85367 |
| 30674 | /* 85367 */ GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(85460), // Rule ID 4238 // |
| 30675 | /* 85372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30676 | /* 85377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30677 | /* 85380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30678 | /* 85383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30679 | /* 85386 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30680 | /* 85389 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30681 | /* 85392 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30682 | /* 85395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30683 | /* 85399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30684 | /* 85403 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30685 | /* 85407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30686 | /* 85411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30687 | /* 85415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30688 | /* 85419 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 30689 | /* 85419 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30690 | /* 85422 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30691 | /* 85426 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30692 | /* 85431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8), |
| 30693 | /* 85434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30694 | /* 85436 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30695 | /* 85438 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30696 | /* 85440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30697 | /* 85443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30698 | /* 85449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30699 | /* 85455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30700 | /* 85458 */ GIR_RootConstrainSelectedInstOperands, |
| 30701 | /* 85459 */ // GIR_Coverage, 4238, |
| 30702 | /* 85459 */ GIR_EraseRootFromParent_Done, |
| 30703 | /* 85460 */ // Label 1668: @85460 |
| 30704 | /* 85460 */ GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(85553), // Rule ID 4240 // |
| 30705 | /* 85465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30706 | /* 85470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30707 | /* 85473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30708 | /* 85476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30709 | /* 85479 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30710 | /* 85482 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30711 | /* 85485 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30712 | /* 85488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30713 | /* 85492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30714 | /* 85496 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30715 | /* 85500 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30716 | /* 85504 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30717 | /* 85508 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30718 | /* 85512 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 30719 | /* 85512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30720 | /* 85515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30721 | /* 85519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30722 | /* 85524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16), |
| 30723 | /* 85527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30724 | /* 85529 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30725 | /* 85531 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30726 | /* 85533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30727 | /* 85536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30728 | /* 85542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30729 | /* 85548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30730 | /* 85551 */ GIR_RootConstrainSelectedInstOperands, |
| 30731 | /* 85552 */ // GIR_Coverage, 4240, |
| 30732 | /* 85552 */ GIR_EraseRootFromParent_Done, |
| 30733 | /* 85553 */ // Label 1669: @85553 |
| 30734 | /* 85553 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(85646), // Rule ID 4242 // |
| 30735 | /* 85558 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30736 | /* 85563 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30737 | /* 85566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30738 | /* 85569 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30739 | /* 85572 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30740 | /* 85575 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30741 | /* 85578 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30742 | /* 85581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30743 | /* 85585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30744 | /* 85589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30745 | /* 85593 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30746 | /* 85597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30747 | /* 85601 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30748 | /* 85605 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 30749 | /* 85605 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30750 | /* 85608 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30751 | /* 85612 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30752 | /* 85617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32), |
| 30753 | /* 85620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30754 | /* 85622 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30755 | /* 85624 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30756 | /* 85626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30757 | /* 85629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30758 | /* 85635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30759 | /* 85641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30760 | /* 85644 */ GIR_RootConstrainSelectedInstOperands, |
| 30761 | /* 85645 */ // GIR_Coverage, 4242, |
| 30762 | /* 85645 */ GIR_EraseRootFromParent_Done, |
| 30763 | /* 85646 */ // Label 1670: @85646 |
| 30764 | /* 85646 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(85739), // Rule ID 4244 // |
| 30765 | /* 85651 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30766 | /* 85656 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30767 | /* 85659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30768 | /* 85662 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30769 | /* 85665 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30770 | /* 85668 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30771 | /* 85671 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30772 | /* 85674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30773 | /* 85678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30774 | /* 85682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30775 | /* 85686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30776 | /* 85690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30777 | /* 85694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30778 | /* 85698 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 30779 | /* 85698 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30780 | /* 85701 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30781 | /* 85705 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30782 | /* 85710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8), |
| 30783 | /* 85713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30784 | /* 85715 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30785 | /* 85717 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30786 | /* 85719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30787 | /* 85722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30788 | /* 85728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30789 | /* 85734 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30790 | /* 85737 */ GIR_RootConstrainSelectedInstOperands, |
| 30791 | /* 85738 */ // GIR_Coverage, 4244, |
| 30792 | /* 85738 */ GIR_EraseRootFromParent_Done, |
| 30793 | /* 85739 */ // Label 1671: @85739 |
| 30794 | /* 85739 */ GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(85832), // Rule ID 4246 // |
| 30795 | /* 85744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30796 | /* 85749 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30797 | /* 85752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30798 | /* 85755 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30799 | /* 85758 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30800 | /* 85761 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30801 | /* 85764 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30802 | /* 85767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30803 | /* 85771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30804 | /* 85775 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30805 | /* 85779 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30806 | /* 85783 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30807 | /* 85787 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30808 | /* 85791 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 30809 | /* 85791 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30810 | /* 85794 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30811 | /* 85798 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30812 | /* 85803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16), |
| 30813 | /* 85806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30814 | /* 85808 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30815 | /* 85810 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30816 | /* 85812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30817 | /* 85815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30818 | /* 85821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30819 | /* 85827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30820 | /* 85830 */ GIR_RootConstrainSelectedInstOperands, |
| 30821 | /* 85831 */ // GIR_Coverage, 4246, |
| 30822 | /* 85831 */ GIR_EraseRootFromParent_Done, |
| 30823 | /* 85832 */ // Label 1672: @85832 |
| 30824 | /* 85832 */ GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(85925), // Rule ID 4248 // |
| 30825 | /* 85837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30826 | /* 85842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30827 | /* 85845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30828 | /* 85848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30829 | /* 85851 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30830 | /* 85854 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30831 | /* 85857 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30832 | /* 85860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30833 | /* 85864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30834 | /* 85868 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30835 | /* 85872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30836 | /* 85876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30837 | /* 85880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30838 | /* 85884 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 30839 | /* 85884 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30840 | /* 85887 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30841 | /* 85891 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30842 | /* 85896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32), |
| 30843 | /* 85899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30844 | /* 85901 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30845 | /* 85903 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30846 | /* 85905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30847 | /* 85908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30848 | /* 85914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30849 | /* 85920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30850 | /* 85923 */ GIR_RootConstrainSelectedInstOperands, |
| 30851 | /* 85924 */ // GIR_Coverage, 4248, |
| 30852 | /* 85924 */ GIR_EraseRootFromParent_Done, |
| 30853 | /* 85925 */ // Label 1673: @85925 |
| 30854 | /* 85925 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(86018), // Rule ID 4250 // |
| 30855 | /* 85930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30856 | /* 85935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30857 | /* 85938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30858 | /* 85941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30859 | /* 85944 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30860 | /* 85947 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30861 | /* 85950 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30862 | /* 85953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30863 | /* 85957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30864 | /* 85961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30865 | /* 85965 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30866 | /* 85969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30867 | /* 85973 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30868 | /* 85977 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 30869 | /* 85977 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30870 | /* 85980 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30871 | /* 85984 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30872 | /* 85989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8), |
| 30873 | /* 85992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30874 | /* 85994 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30875 | /* 85996 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30876 | /* 85998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30877 | /* 86001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30878 | /* 86007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30879 | /* 86013 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30880 | /* 86016 */ GIR_RootConstrainSelectedInstOperands, |
| 30881 | /* 86017 */ // GIR_Coverage, 4250, |
| 30882 | /* 86017 */ GIR_EraseRootFromParent_Done, |
| 30883 | /* 86018 */ // Label 1674: @86018 |
| 30884 | /* 86018 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(86111), // Rule ID 4252 // |
| 30885 | /* 86023 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30886 | /* 86028 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30887 | /* 86031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30888 | /* 86034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30889 | /* 86037 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30890 | /* 86040 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30891 | /* 86043 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30892 | /* 86046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30893 | /* 86050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30894 | /* 86054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30895 | /* 86058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30896 | /* 86062 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30897 | /* 86066 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30898 | /* 86070 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 30899 | /* 86070 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30900 | /* 86073 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30901 | /* 86077 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30902 | /* 86082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16), |
| 30903 | /* 86085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30904 | /* 86087 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30905 | /* 86089 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30906 | /* 86091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30907 | /* 86094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30908 | /* 86100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30909 | /* 86106 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30910 | /* 86109 */ GIR_RootConstrainSelectedInstOperands, |
| 30911 | /* 86110 */ // GIR_Coverage, 4252, |
| 30912 | /* 86110 */ GIR_EraseRootFromParent_Done, |
| 30913 | /* 86111 */ // Label 1675: @86111 |
| 30914 | /* 86111 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(86204), // Rule ID 4254 // |
| 30915 | /* 86116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30916 | /* 86121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30917 | /* 86124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30918 | /* 86127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30919 | /* 86130 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30920 | /* 86133 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30921 | /* 86136 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30922 | /* 86139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30923 | /* 86143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30924 | /* 86147 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30925 | /* 86151 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30926 | /* 86155 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30927 | /* 86159 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30928 | /* 86163 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 30929 | /* 86163 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30930 | /* 86166 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30931 | /* 86170 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30932 | /* 86175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32), |
| 30933 | /* 86178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30934 | /* 86180 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30935 | /* 86182 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30936 | /* 86184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30937 | /* 86187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30938 | /* 86193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30939 | /* 86199 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30940 | /* 86202 */ GIR_RootConstrainSelectedInstOperands, |
| 30941 | /* 86203 */ // GIR_Coverage, 4254, |
| 30942 | /* 86203 */ GIR_EraseRootFromParent_Done, |
| 30943 | /* 86204 */ // Label 1676: @86204 |
| 30944 | /* 86204 */ GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(86297), // Rule ID 4256 // |
| 30945 | /* 86209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30946 | /* 86214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30947 | /* 86217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30948 | /* 86220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30949 | /* 86223 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30950 | /* 86226 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30951 | /* 86229 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30952 | /* 86232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30953 | /* 86236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30954 | /* 86240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30955 | /* 86244 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30956 | /* 86248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30957 | /* 86252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30958 | /* 86256 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 30959 | /* 86256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30960 | /* 86259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30961 | /* 86263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30962 | /* 86268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8), |
| 30963 | /* 86271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30964 | /* 86273 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30965 | /* 86275 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30966 | /* 86277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30967 | /* 86280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30968 | /* 86286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30969 | /* 86292 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30970 | /* 86295 */ GIR_RootConstrainSelectedInstOperands, |
| 30971 | /* 86296 */ // GIR_Coverage, 4256, |
| 30972 | /* 86296 */ GIR_EraseRootFromParent_Done, |
| 30973 | /* 86297 */ // Label 1677: @86297 |
| 30974 | /* 86297 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(86390), // Rule ID 4258 // |
| 30975 | /* 86302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 30976 | /* 86307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30977 | /* 86310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30978 | /* 86313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30979 | /* 86316 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30980 | /* 86319 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30981 | /* 86322 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30982 | /* 86325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30983 | /* 86329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30984 | /* 86333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30985 | /* 86337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30986 | /* 86341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30987 | /* 86345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30988 | /* 86349 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 30989 | /* 86349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 30990 | /* 86352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30991 | /* 86356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30992 | /* 86361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16), |
| 30993 | /* 86364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30994 | /* 86366 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30995 | /* 86368 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30996 | /* 86370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30997 | /* 86373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30998 | /* 86379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30999 | /* 86385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31000 | /* 86388 */ GIR_RootConstrainSelectedInstOperands, |
| 31001 | /* 86389 */ // GIR_Coverage, 4258, |
| 31002 | /* 86389 */ GIR_EraseRootFromParent_Done, |
| 31003 | /* 86390 */ // Label 1678: @86390 |
| 31004 | /* 86390 */ GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(86483), // Rule ID 4260 // |
| 31005 | /* 86395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 31006 | /* 86400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31007 | /* 86403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31008 | /* 86406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31009 | /* 86409 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31010 | /* 86412 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31011 | /* 86415 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31012 | /* 86418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31013 | /* 86422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31014 | /* 86426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31015 | /* 86430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31016 | /* 86434 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31017 | /* 86438 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31018 | /* 86442 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 31019 | /* 86442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 31020 | /* 86445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 31021 | /* 86449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 31022 | /* 86454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32), |
| 31023 | /* 86457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31024 | /* 86459 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31025 | /* 86461 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31026 | /* 86463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31027 | /* 86466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31028 | /* 86472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31029 | /* 86478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31030 | /* 86481 */ GIR_RootConstrainSelectedInstOperands, |
| 31031 | /* 86482 */ // GIR_Coverage, 4260, |
| 31032 | /* 86482 */ GIR_EraseRootFromParent_Done, |
| 31033 | /* 86483 */ // Label 1679: @86483 |
| 31034 | /* 86483 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(86576), // Rule ID 4262 // |
| 31035 | /* 86488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 31036 | /* 86493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31037 | /* 86496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31038 | /* 86499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 31039 | /* 86502 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31040 | /* 86505 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31041 | /* 86508 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31042 | /* 86511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31043 | /* 86515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31044 | /* 86519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31045 | /* 86523 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31046 | /* 86527 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31047 | /* 86531 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31048 | /* 86535 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 31049 | /* 86535 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 31050 | /* 86538 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 31051 | /* 86542 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 31052 | /* 86547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8), |
| 31053 | /* 86550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31054 | /* 86552 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31055 | /* 86554 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31056 | /* 86556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31057 | /* 86559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31058 | /* 86565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31059 | /* 86571 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31060 | /* 86574 */ GIR_RootConstrainSelectedInstOperands, |
| 31061 | /* 86575 */ // GIR_Coverage, 4262, |
| 31062 | /* 86575 */ GIR_EraseRootFromParent_Done, |
| 31063 | /* 86576 */ // Label 1680: @86576 |
| 31064 | /* 86576 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(86669), // Rule ID 4264 // |
| 31065 | /* 86581 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 31066 | /* 86586 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31067 | /* 86589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31068 | /* 86592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31069 | /* 86595 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31070 | /* 86598 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31071 | /* 86601 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31072 | /* 86604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31073 | /* 86608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31074 | /* 86612 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31075 | /* 86616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31076 | /* 86620 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31077 | /* 86624 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31078 | /* 86628 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3955:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 31079 | /* 86628 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 31080 | /* 86631 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 31081 | /* 86635 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 31082 | /* 86640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16), |
| 31083 | /* 86643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31084 | /* 86645 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31085 | /* 86647 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31086 | /* 86649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31087 | /* 86652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31088 | /* 86658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31089 | /* 86664 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31090 | /* 86667 */ GIR_RootConstrainSelectedInstOperands, |
| 31091 | /* 86668 */ // GIR_Coverage, 4264, |
| 31092 | /* 86668 */ GIR_EraseRootFromParent_Done, |
| 31093 | /* 86669 */ // Label 1681: @86669 |
| 31094 | /* 86669 */ GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(86762), // Rule ID 4266 // |
| 31095 | /* 86674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 31096 | /* 86679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31097 | /* 86682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31098 | /* 86685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31099 | /* 86688 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31100 | /* 86691 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31101 | /* 86694 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31102 | /* 86697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31103 | /* 86701 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31104 | /* 86705 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31105 | /* 86709 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31106 | /* 86713 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31107 | /* 86717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31108 | /* 86721 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 31109 | /* 86721 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 31110 | /* 86724 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 31111 | /* 86728 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 31112 | /* 86733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32), |
| 31113 | /* 86736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31114 | /* 86738 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31115 | /* 86740 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31116 | /* 86742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31117 | /* 86745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31118 | /* 86751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31119 | /* 86757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31120 | /* 86760 */ GIR_RootConstrainSelectedInstOperands, |
| 31121 | /* 86761 */ // GIR_Coverage, 4266, |
| 31122 | /* 86761 */ GIR_EraseRootFromParent_Done, |
| 31123 | /* 86762 */ // Label 1682: @86762 |
| 31124 | /* 86762 */ GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(86840), // Rule ID 4979 // |
| 31125 | /* 86767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31126 | /* 86772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31127 | /* 86775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31128 | /* 86778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31129 | /* 86781 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31130 | /* 86784 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31131 | /* 86787 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31132 | /* 86790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31133 | /* 86794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31134 | /* 86798 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31135 | /* 86802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31136 | /* 86806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31137 | /* 86810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31138 | /* 86814 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 31139 | /* 86814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh), |
| 31140 | /* 86817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31141 | /* 86819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31142 | /* 86821 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31143 | /* 86823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31144 | /* 86826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31145 | /* 86832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31146 | /* 86838 */ GIR_RootConstrainSelectedInstOperands, |
| 31147 | /* 86839 */ // GIR_Coverage, 4979, |
| 31148 | /* 86839 */ GIR_EraseRootFromParent_Done, |
| 31149 | /* 86840 */ // Label 1683: @86840 |
| 31150 | /* 86840 */ GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(86918), // Rule ID 4981 // |
| 31151 | /* 86845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31152 | /* 86850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31153 | /* 86853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31154 | /* 86856 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31155 | /* 86859 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31156 | /* 86862 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31157 | /* 86865 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31158 | /* 86868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31159 | /* 86872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31160 | /* 86876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31161 | /* 86880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31162 | /* 86884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31163 | /* 86888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31164 | /* 86892 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 31165 | /* 86892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th), |
| 31166 | /* 86895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31167 | /* 86897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31168 | /* 86899 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31169 | /* 86901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31170 | /* 86904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31171 | /* 86910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31172 | /* 86916 */ GIR_RootConstrainSelectedInstOperands, |
| 31173 | /* 86917 */ // GIR_Coverage, 4981, |
| 31174 | /* 86917 */ GIR_EraseRootFromParent_Done, |
| 31175 | /* 86918 */ // Label 1684: @86918 |
| 31176 | /* 86918 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(86996), // Rule ID 4983 // |
| 31177 | /* 86923 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31178 | /* 86928 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31179 | /* 86931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31180 | /* 86934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31181 | /* 86937 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31182 | /* 86940 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31183 | /* 86943 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31184 | /* 86946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31185 | /* 86950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31186 | /* 86954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31187 | /* 86958 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31188 | /* 86962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31189 | /* 86966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31190 | /* 86970 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3920:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 31191 | /* 86970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh), |
| 31192 | /* 86973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31193 | /* 86975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31194 | /* 86977 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31195 | /* 86979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31196 | /* 86982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31197 | /* 86988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31198 | /* 86994 */ GIR_RootConstrainSelectedInstOperands, |
| 31199 | /* 86995 */ // GIR_Coverage, 4983, |
| 31200 | /* 86995 */ GIR_EraseRootFromParent_Done, |
| 31201 | /* 86996 */ // Label 1685: @86996 |
| 31202 | /* 86996 */ GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(87074), // Rule ID 4985 // |
| 31203 | /* 87001 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31204 | /* 87006 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31205 | /* 87009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31206 | /* 87012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31207 | /* 87015 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31208 | /* 87018 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31209 | /* 87021 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31210 | /* 87024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31211 | /* 87028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31212 | /* 87032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31213 | /* 87036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31214 | /* 87040 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31215 | /* 87044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31216 | /* 87048 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3920:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 31217 | /* 87048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th), |
| 31218 | /* 87051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31219 | /* 87053 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31220 | /* 87055 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31221 | /* 87057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31222 | /* 87060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31223 | /* 87066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31224 | /* 87072 */ GIR_RootConstrainSelectedInstOperands, |
| 31225 | /* 87073 */ // GIR_Coverage, 4985, |
| 31226 | /* 87073 */ GIR_EraseRootFromParent_Done, |
| 31227 | /* 87074 */ // Label 1686: @87074 |
| 31228 | /* 87074 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(87152), // Rule ID 4987 // |
| 31229 | /* 87079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31230 | /* 87084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31231 | /* 87087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31232 | /* 87090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31233 | /* 87093 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31234 | /* 87096 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31235 | /* 87099 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31236 | /* 87102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31237 | /* 87106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31238 | /* 87110 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31239 | /* 87114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31240 | /* 87118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31241 | /* 87122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31242 | /* 87126 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 31243 | /* 87126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh), |
| 31244 | /* 87129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31245 | /* 87131 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31246 | /* 87133 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31247 | /* 87135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31248 | /* 87138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31249 | /* 87144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31250 | /* 87150 */ GIR_RootConstrainSelectedInstOperands, |
| 31251 | /* 87151 */ // GIR_Coverage, 4987, |
| 31252 | /* 87151 */ GIR_EraseRootFromParent_Done, |
| 31253 | /* 87152 */ // Label 1687: @87152 |
| 31254 | /* 87152 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(87230), // Rule ID 4989 // |
| 31255 | /* 87157 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31256 | /* 87162 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31257 | /* 87165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31258 | /* 87168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31259 | /* 87171 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31260 | /* 87174 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31261 | /* 87177 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31262 | /* 87180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31263 | /* 87184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31264 | /* 87188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31265 | /* 87192 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31266 | /* 87196 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31267 | /* 87200 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31268 | /* 87204 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 31269 | /* 87204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th), |
| 31270 | /* 87207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31271 | /* 87209 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31272 | /* 87211 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31273 | /* 87213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31274 | /* 87216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31275 | /* 87222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31276 | /* 87228 */ GIR_RootConstrainSelectedInstOperands, |
| 31277 | /* 87229 */ // GIR_Coverage, 4989, |
| 31278 | /* 87229 */ GIR_EraseRootFromParent_Done, |
| 31279 | /* 87230 */ // Label 1688: @87230 |
| 31280 | /* 87230 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(87308), // Rule ID 4991 // |
| 31281 | /* 87235 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31282 | /* 87240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31283 | /* 87243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31284 | /* 87246 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31285 | /* 87249 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31286 | /* 87252 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31287 | /* 87255 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31288 | /* 87258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31289 | /* 87262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31290 | /* 87266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31291 | /* 87270 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31292 | /* 87274 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31293 | /* 87278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31294 | /* 87282 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3920:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 31295 | /* 87282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh), |
| 31296 | /* 87285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31297 | /* 87287 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31298 | /* 87289 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31299 | /* 87291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31300 | /* 87294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31301 | /* 87300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31302 | /* 87306 */ GIR_RootConstrainSelectedInstOperands, |
| 31303 | /* 87307 */ // GIR_Coverage, 4991, |
| 31304 | /* 87307 */ GIR_EraseRootFromParent_Done, |
| 31305 | /* 87308 */ // Label 1689: @87308 |
| 31306 | /* 87308 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(87386), // Rule ID 4993 // |
| 31307 | /* 87313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31308 | /* 87318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31309 | /* 87321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31310 | /* 87324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31311 | /* 87327 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31312 | /* 87330 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31313 | /* 87333 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31314 | /* 87336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31315 | /* 87340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31316 | /* 87344 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31317 | /* 87348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31318 | /* 87352 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31319 | /* 87356 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31320 | /* 87360 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3920:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 31321 | /* 87360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th), |
| 31322 | /* 87363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31323 | /* 87365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31324 | /* 87367 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31325 | /* 87369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31326 | /* 87372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31327 | /* 87378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31328 | /* 87384 */ GIR_RootConstrainSelectedInstOperands, |
| 31329 | /* 87385 */ // GIR_Coverage, 4993, |
| 31330 | /* 87385 */ GIR_EraseRootFromParent_Done, |
| 31331 | /* 87386 */ // Label 1690: @87386 |
| 31332 | /* 87386 */ GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(87464), // Rule ID 4995 // |
| 31333 | /* 87391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31334 | /* 87396 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31335 | /* 87399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31336 | /* 87402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31337 | /* 87405 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31338 | /* 87408 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31339 | /* 87411 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31340 | /* 87414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31341 | /* 87418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31342 | /* 87422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31343 | /* 87426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31344 | /* 87430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31345 | /* 87434 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31346 | /* 87438 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 31347 | /* 87438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh), |
| 31348 | /* 87441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31349 | /* 87443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31350 | /* 87445 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31351 | /* 87447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31352 | /* 87450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31353 | /* 87456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31354 | /* 87462 */ GIR_RootConstrainSelectedInstOperands, |
| 31355 | /* 87463 */ // GIR_Coverage, 4995, |
| 31356 | /* 87463 */ GIR_EraseRootFromParent_Done, |
| 31357 | /* 87464 */ // Label 1691: @87464 |
| 31358 | /* 87464 */ GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(87542), // Rule ID 4997 // |
| 31359 | /* 87469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31360 | /* 87474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31361 | /* 87477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31362 | /* 87480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31363 | /* 87483 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31364 | /* 87486 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31365 | /* 87489 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31366 | /* 87492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31367 | /* 87496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31368 | /* 87500 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31369 | /* 87504 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31370 | /* 87508 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31371 | /* 87512 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31372 | /* 87516 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 31373 | /* 87516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th), |
| 31374 | /* 87519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31375 | /* 87521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31376 | /* 87523 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31377 | /* 87525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31378 | /* 87528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31379 | /* 87534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31380 | /* 87540 */ GIR_RootConstrainSelectedInstOperands, |
| 31381 | /* 87541 */ // GIR_Coverage, 4997, |
| 31382 | /* 87541 */ GIR_EraseRootFromParent_Done, |
| 31383 | /* 87542 */ // Label 1692: @87542 |
| 31384 | /* 87542 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(87620), // Rule ID 4999 // |
| 31385 | /* 87547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31386 | /* 87552 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31387 | /* 87555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31388 | /* 87558 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31389 | /* 87561 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31390 | /* 87564 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31391 | /* 87567 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31392 | /* 87570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31393 | /* 87574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31394 | /* 87578 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31395 | /* 87582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31396 | /* 87586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31397 | /* 87590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31398 | /* 87594 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3920:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 31399 | /* 87594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh), |
| 31400 | /* 87597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31401 | /* 87599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31402 | /* 87601 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31403 | /* 87603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31404 | /* 87606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31405 | /* 87612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31406 | /* 87618 */ GIR_RootConstrainSelectedInstOperands, |
| 31407 | /* 87619 */ // GIR_Coverage, 4999, |
| 31408 | /* 87619 */ GIR_EraseRootFromParent_Done, |
| 31409 | /* 87620 */ // Label 1693: @87620 |
| 31410 | /* 87620 */ GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(87698), // Rule ID 5001 // |
| 31411 | /* 87625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 31412 | /* 87630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31413 | /* 87633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31414 | /* 87636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31415 | /* 87639 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31416 | /* 87642 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31417 | /* 87645 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31418 | /* 87648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31419 | /* 87652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31420 | /* 87656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31421 | /* 87660 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31422 | /* 87664 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31423 | /* 87668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31424 | /* 87672 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3920:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 31425 | /* 87672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th), |
| 31426 | /* 87675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31427 | /* 87677 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 31428 | /* 87679 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31429 | /* 87681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31430 | /* 87684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31431 | /* 87690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31432 | /* 87696 */ GIR_RootConstrainSelectedInstOperands, |
| 31433 | /* 87697 */ // GIR_Coverage, 5001, |
| 31434 | /* 87697 */ GIR_EraseRootFromParent_Done, |
| 31435 | /* 87698 */ // Label 1694: @87698 |
| 31436 | /* 87698 */ GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(87776), // Rule ID 5203 // |
| 31437 | /* 87703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31438 | /* 87708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31439 | /* 87711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31440 | /* 87714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31441 | /* 87717 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31442 | /* 87720 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31443 | /* 87723 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31444 | /* 87726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31445 | /* 87730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31446 | /* 87734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31447 | /* 87738 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31448 | /* 87742 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31449 | /* 87746 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31450 | /* 87750 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31451 | /* 87750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8), |
| 31452 | /* 87753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31453 | /* 87755 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31454 | /* 87757 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31455 | /* 87759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31456 | /* 87762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31457 | /* 87768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31458 | /* 87774 */ GIR_RootConstrainSelectedInstOperands, |
| 31459 | /* 87775 */ // GIR_Coverage, 5203, |
| 31460 | /* 87775 */ GIR_EraseRootFromParent_Done, |
| 31461 | /* 87776 */ // Label 1695: @87776 |
| 31462 | /* 87776 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(87854), // Rule ID 5205 // |
| 31463 | /* 87781 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31464 | /* 87786 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31465 | /* 87789 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31466 | /* 87792 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31467 | /* 87795 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31468 | /* 87798 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31469 | /* 87801 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31470 | /* 87804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31471 | /* 87808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31472 | /* 87812 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31473 | /* 87816 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31474 | /* 87820 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31475 | /* 87824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31476 | /* 87828 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31477 | /* 87828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16), |
| 31478 | /* 87831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31479 | /* 87833 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31480 | /* 87835 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31481 | /* 87837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31482 | /* 87840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31483 | /* 87846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31484 | /* 87852 */ GIR_RootConstrainSelectedInstOperands, |
| 31485 | /* 87853 */ // GIR_Coverage, 5205, |
| 31486 | /* 87853 */ GIR_EraseRootFromParent_Done, |
| 31487 | /* 87854 */ // Label 1696: @87854 |
| 31488 | /* 87854 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(87932), // Rule ID 5207 // |
| 31489 | /* 87859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31490 | /* 87864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31491 | /* 87867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31492 | /* 87870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31493 | /* 87873 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31494 | /* 87876 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31495 | /* 87879 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31496 | /* 87882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31497 | /* 87886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31498 | /* 87890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31499 | /* 87894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31500 | /* 87898 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31501 | /* 87902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31502 | /* 87906 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31503 | /* 87906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32), |
| 31504 | /* 87909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31505 | /* 87911 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31506 | /* 87913 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31507 | /* 87915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31508 | /* 87918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31509 | /* 87924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31510 | /* 87930 */ GIR_RootConstrainSelectedInstOperands, |
| 31511 | /* 87931 */ // GIR_Coverage, 5207, |
| 31512 | /* 87931 */ GIR_EraseRootFromParent_Done, |
| 31513 | /* 87932 */ // Label 1697: @87932 |
| 31514 | /* 87932 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(88010), // Rule ID 5209 // |
| 31515 | /* 87937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31516 | /* 87942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31517 | /* 87945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31518 | /* 87948 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31519 | /* 87951 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31520 | /* 87954 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31521 | /* 87957 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31522 | /* 87960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31523 | /* 87964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31524 | /* 87968 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31525 | /* 87972 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31526 | /* 87976 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31527 | /* 87980 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31528 | /* 87984 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31529 | /* 87984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8), |
| 31530 | /* 87987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31531 | /* 87989 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31532 | /* 87991 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31533 | /* 87993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31534 | /* 87996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31535 | /* 88002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31536 | /* 88008 */ GIR_RootConstrainSelectedInstOperands, |
| 31537 | /* 88009 */ // GIR_Coverage, 5209, |
| 31538 | /* 88009 */ GIR_EraseRootFromParent_Done, |
| 31539 | /* 88010 */ // Label 1698: @88010 |
| 31540 | /* 88010 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(88088), // Rule ID 5211 // |
| 31541 | /* 88015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31542 | /* 88020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31543 | /* 88023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31544 | /* 88026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31545 | /* 88029 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31546 | /* 88032 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31547 | /* 88035 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31548 | /* 88038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31549 | /* 88042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31550 | /* 88046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31551 | /* 88050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31552 | /* 88054 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31553 | /* 88058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31554 | /* 88062 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31555 | /* 88062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16), |
| 31556 | /* 88065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31557 | /* 88067 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31558 | /* 88069 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31559 | /* 88071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31560 | /* 88074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31561 | /* 88080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31562 | /* 88086 */ GIR_RootConstrainSelectedInstOperands, |
| 31563 | /* 88087 */ // GIR_Coverage, 5211, |
| 31564 | /* 88087 */ GIR_EraseRootFromParent_Done, |
| 31565 | /* 88088 */ // Label 1699: @88088 |
| 31566 | /* 88088 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(88166), // Rule ID 5213 // |
| 31567 | /* 88093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31568 | /* 88098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31569 | /* 88101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31570 | /* 88104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31571 | /* 88107 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31572 | /* 88110 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31573 | /* 88113 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31574 | /* 88116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31575 | /* 88120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31576 | /* 88124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31577 | /* 88128 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31578 | /* 88132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31579 | /* 88136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31580 | /* 88140 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31581 | /* 88140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32), |
| 31582 | /* 88143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31583 | /* 88145 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31584 | /* 88147 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31585 | /* 88149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31586 | /* 88152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31587 | /* 88158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31588 | /* 88164 */ GIR_RootConstrainSelectedInstOperands, |
| 31589 | /* 88165 */ // GIR_Coverage, 5213, |
| 31590 | /* 88165 */ GIR_EraseRootFromParent_Done, |
| 31591 | /* 88166 */ // Label 1700: @88166 |
| 31592 | /* 88166 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(88244), // Rule ID 5215 // |
| 31593 | /* 88171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31594 | /* 88176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31595 | /* 88179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31596 | /* 88182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31597 | /* 88185 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31598 | /* 88188 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31599 | /* 88191 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31600 | /* 88194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31601 | /* 88198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31602 | /* 88202 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31603 | /* 88206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31604 | /* 88210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31605 | /* 88214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31606 | /* 88218 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31607 | /* 88218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8), |
| 31608 | /* 88221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31609 | /* 88223 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31610 | /* 88225 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31611 | /* 88227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31612 | /* 88230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31613 | /* 88236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31614 | /* 88242 */ GIR_RootConstrainSelectedInstOperands, |
| 31615 | /* 88243 */ // GIR_Coverage, 5215, |
| 31616 | /* 88243 */ GIR_EraseRootFromParent_Done, |
| 31617 | /* 88244 */ // Label 1701: @88244 |
| 31618 | /* 88244 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(88322), // Rule ID 5217 // |
| 31619 | /* 88249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31620 | /* 88254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31621 | /* 88257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31622 | /* 88260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31623 | /* 88263 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31624 | /* 88266 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31625 | /* 88269 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31626 | /* 88272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31627 | /* 88276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31628 | /* 88280 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31629 | /* 88284 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31630 | /* 88288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31631 | /* 88292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31632 | /* 88296 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31633 | /* 88296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16), |
| 31634 | /* 88299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31635 | /* 88301 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31636 | /* 88303 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31637 | /* 88305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31638 | /* 88308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31639 | /* 88314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31640 | /* 88320 */ GIR_RootConstrainSelectedInstOperands, |
| 31641 | /* 88321 */ // GIR_Coverage, 5217, |
| 31642 | /* 88321 */ GIR_EraseRootFromParent_Done, |
| 31643 | /* 88322 */ // Label 1702: @88322 |
| 31644 | /* 88322 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(88400), // Rule ID 5219 // |
| 31645 | /* 88327 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31646 | /* 88332 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31647 | /* 88335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31648 | /* 88338 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31649 | /* 88341 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31650 | /* 88344 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31651 | /* 88347 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31652 | /* 88350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31653 | /* 88354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31654 | /* 88358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31655 | /* 88362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31656 | /* 88366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31657 | /* 88370 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31658 | /* 88374 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31659 | /* 88374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32), |
| 31660 | /* 88377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31661 | /* 88379 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31662 | /* 88381 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31663 | /* 88383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31664 | /* 88386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31665 | /* 88392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31666 | /* 88398 */ GIR_RootConstrainSelectedInstOperands, |
| 31667 | /* 88399 */ // GIR_Coverage, 5219, |
| 31668 | /* 88399 */ GIR_EraseRootFromParent_Done, |
| 31669 | /* 88400 */ // Label 1703: @88400 |
| 31670 | /* 88400 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(88478), // Rule ID 5221 // |
| 31671 | /* 88405 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31672 | /* 88410 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31673 | /* 88413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31674 | /* 88416 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31675 | /* 88419 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31676 | /* 88422 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31677 | /* 88425 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31678 | /* 88428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31679 | /* 88432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31680 | /* 88436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31681 | /* 88440 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31682 | /* 88444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31683 | /* 88448 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31684 | /* 88452 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31685 | /* 88452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8), |
| 31686 | /* 88455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31687 | /* 88457 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31688 | /* 88459 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31689 | /* 88461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31690 | /* 88464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31691 | /* 88470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31692 | /* 88476 */ GIR_RootConstrainSelectedInstOperands, |
| 31693 | /* 88477 */ // GIR_Coverage, 5221, |
| 31694 | /* 88477 */ GIR_EraseRootFromParent_Done, |
| 31695 | /* 88478 */ // Label 1704: @88478 |
| 31696 | /* 88478 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(88556), // Rule ID 5223 // |
| 31697 | /* 88483 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31698 | /* 88488 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31699 | /* 88491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31700 | /* 88494 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31701 | /* 88497 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31702 | /* 88500 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31703 | /* 88503 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31704 | /* 88506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31705 | /* 88510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31706 | /* 88514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31707 | /* 88518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31708 | /* 88522 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31709 | /* 88526 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31710 | /* 88530 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31711 | /* 88530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16), |
| 31712 | /* 88533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31713 | /* 88535 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31714 | /* 88537 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31715 | /* 88539 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31716 | /* 88542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31717 | /* 88548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31718 | /* 88554 */ GIR_RootConstrainSelectedInstOperands, |
| 31719 | /* 88555 */ // GIR_Coverage, 5223, |
| 31720 | /* 88555 */ GIR_EraseRootFromParent_Done, |
| 31721 | /* 88556 */ // Label 1705: @88556 |
| 31722 | /* 88556 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(88634), // Rule ID 5225 // |
| 31723 | /* 88561 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31724 | /* 88566 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31725 | /* 88569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31726 | /* 88572 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31727 | /* 88575 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31728 | /* 88578 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31729 | /* 88581 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31730 | /* 88584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31731 | /* 88588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31732 | /* 88592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31733 | /* 88596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31734 | /* 88600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31735 | /* 88604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31736 | /* 88608 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31737 | /* 88608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32), |
| 31738 | /* 88611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31739 | /* 88613 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31740 | /* 88615 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31741 | /* 88617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31742 | /* 88620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31743 | /* 88626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31744 | /* 88632 */ GIR_RootConstrainSelectedInstOperands, |
| 31745 | /* 88633 */ // GIR_Coverage, 5225, |
| 31746 | /* 88633 */ GIR_EraseRootFromParent_Done, |
| 31747 | /* 88634 */ // Label 1706: @88634 |
| 31748 | /* 88634 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(88712), // Rule ID 5227 // |
| 31749 | /* 88639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31750 | /* 88644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31751 | /* 88647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31752 | /* 88650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31753 | /* 88653 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31754 | /* 88656 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31755 | /* 88659 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31756 | /* 88662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31757 | /* 88666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31758 | /* 88670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31759 | /* 88674 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31760 | /* 88678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31761 | /* 88682 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31762 | /* 88686 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31763 | /* 88686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8), |
| 31764 | /* 88689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31765 | /* 88691 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31766 | /* 88693 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31767 | /* 88695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31768 | /* 88698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31769 | /* 88704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31770 | /* 88710 */ GIR_RootConstrainSelectedInstOperands, |
| 31771 | /* 88711 */ // GIR_Coverage, 5227, |
| 31772 | /* 88711 */ GIR_EraseRootFromParent_Done, |
| 31773 | /* 88712 */ // Label 1707: @88712 |
| 31774 | /* 88712 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(88790), // Rule ID 5229 // |
| 31775 | /* 88717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31776 | /* 88722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31777 | /* 88725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31778 | /* 88728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31779 | /* 88731 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31780 | /* 88734 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31781 | /* 88737 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31782 | /* 88740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31783 | /* 88744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31784 | /* 88748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31785 | /* 88752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31786 | /* 88756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31787 | /* 88760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31788 | /* 88764 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31789 | /* 88764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16), |
| 31790 | /* 88767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31791 | /* 88769 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31792 | /* 88771 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31793 | /* 88773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31794 | /* 88776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31795 | /* 88782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31796 | /* 88788 */ GIR_RootConstrainSelectedInstOperands, |
| 31797 | /* 88789 */ // GIR_Coverage, 5229, |
| 31798 | /* 88789 */ GIR_EraseRootFromParent_Done, |
| 31799 | /* 88790 */ // Label 1708: @88790 |
| 31800 | /* 88790 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(88868), // Rule ID 5231 // |
| 31801 | /* 88795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31802 | /* 88800 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31803 | /* 88803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31804 | /* 88806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31805 | /* 88809 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31806 | /* 88812 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31807 | /* 88815 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31808 | /* 88818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31809 | /* 88822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31810 | /* 88826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31811 | /* 88830 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31812 | /* 88834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31813 | /* 88838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31814 | /* 88842 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31815 | /* 88842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32), |
| 31816 | /* 88845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31817 | /* 88847 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31818 | /* 88849 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31819 | /* 88851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31820 | /* 88854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31821 | /* 88860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31822 | /* 88866 */ GIR_RootConstrainSelectedInstOperands, |
| 31823 | /* 88867 */ // GIR_Coverage, 5231, |
| 31824 | /* 88867 */ GIR_EraseRootFromParent_Done, |
| 31825 | /* 88868 */ // Label 1709: @88868 |
| 31826 | /* 88868 */ GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(88946), // Rule ID 5233 // |
| 31827 | /* 88873 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31828 | /* 88878 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31829 | /* 88881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31830 | /* 88884 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31831 | /* 88887 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31832 | /* 88890 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31833 | /* 88893 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31834 | /* 88896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31835 | /* 88900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31836 | /* 88904 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31837 | /* 88908 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31838 | /* 88912 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31839 | /* 88916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31840 | /* 88920 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31841 | /* 88920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8), |
| 31842 | /* 88923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31843 | /* 88925 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31844 | /* 88927 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31845 | /* 88929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31846 | /* 88932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31847 | /* 88938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31848 | /* 88944 */ GIR_RootConstrainSelectedInstOperands, |
| 31849 | /* 88945 */ // GIR_Coverage, 5233, |
| 31850 | /* 88945 */ GIR_EraseRootFromParent_Done, |
| 31851 | /* 88946 */ // Label 1710: @88946 |
| 31852 | /* 88946 */ GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(89024), // Rule ID 5235 // |
| 31853 | /* 88951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31854 | /* 88956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31855 | /* 88959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31856 | /* 88962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31857 | /* 88965 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31858 | /* 88968 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31859 | /* 88971 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31860 | /* 88974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31861 | /* 88978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31862 | /* 88982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31863 | /* 88986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31864 | /* 88990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31865 | /* 88994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31866 | /* 88998 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31867 | /* 88998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16), |
| 31868 | /* 89001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31869 | /* 89003 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31870 | /* 89005 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31871 | /* 89007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31872 | /* 89010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31873 | /* 89016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31874 | /* 89022 */ GIR_RootConstrainSelectedInstOperands, |
| 31875 | /* 89023 */ // GIR_Coverage, 5235, |
| 31876 | /* 89023 */ GIR_EraseRootFromParent_Done, |
| 31877 | /* 89024 */ // Label 1711: @89024 |
| 31878 | /* 89024 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(89102), // Rule ID 5237 // |
| 31879 | /* 89029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31880 | /* 89034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31881 | /* 89037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31882 | /* 89040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31883 | /* 89043 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31884 | /* 89046 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31885 | /* 89049 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31886 | /* 89052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31887 | /* 89056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31888 | /* 89060 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31889 | /* 89064 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31890 | /* 89068 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31891 | /* 89072 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31892 | /* 89076 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31893 | /* 89076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32), |
| 31894 | /* 89079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31895 | /* 89081 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31896 | /* 89083 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31897 | /* 89085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31898 | /* 89088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31899 | /* 89094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31900 | /* 89100 */ GIR_RootConstrainSelectedInstOperands, |
| 31901 | /* 89101 */ // GIR_Coverage, 5237, |
| 31902 | /* 89101 */ GIR_EraseRootFromParent_Done, |
| 31903 | /* 89102 */ // Label 1712: @89102 |
| 31904 | /* 89102 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(89180), // Rule ID 5239 // |
| 31905 | /* 89107 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31906 | /* 89112 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31907 | /* 89115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31908 | /* 89118 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31909 | /* 89121 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31910 | /* 89124 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31911 | /* 89127 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31912 | /* 89130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31913 | /* 89134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31914 | /* 89138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31915 | /* 89142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31916 | /* 89146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31917 | /* 89150 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31918 | /* 89154 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31919 | /* 89154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8), |
| 31920 | /* 89157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31921 | /* 89159 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31922 | /* 89161 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31923 | /* 89163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31924 | /* 89166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31925 | /* 89172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31926 | /* 89178 */ GIR_RootConstrainSelectedInstOperands, |
| 31927 | /* 89179 */ // GIR_Coverage, 5239, |
| 31928 | /* 89179 */ GIR_EraseRootFromParent_Done, |
| 31929 | /* 89180 */ // Label 1713: @89180 |
| 31930 | /* 89180 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(89258), // Rule ID 5241 // |
| 31931 | /* 89185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31932 | /* 89190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31933 | /* 89193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31934 | /* 89196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31935 | /* 89199 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31936 | /* 89202 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31937 | /* 89205 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31938 | /* 89208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31939 | /* 89212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31940 | /* 89216 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31941 | /* 89220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31942 | /* 89224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31943 | /* 89228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31944 | /* 89232 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31945 | /* 89232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16), |
| 31946 | /* 89235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31947 | /* 89237 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31948 | /* 89239 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31949 | /* 89241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31950 | /* 89244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31951 | /* 89250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31952 | /* 89256 */ GIR_RootConstrainSelectedInstOperands, |
| 31953 | /* 89257 */ // GIR_Coverage, 5241, |
| 31954 | /* 89257 */ GIR_EraseRootFromParent_Done, |
| 31955 | /* 89258 */ // Label 1714: @89258 |
| 31956 | /* 89258 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(89336), // Rule ID 5243 // |
| 31957 | /* 89263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31958 | /* 89268 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31959 | /* 89271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31960 | /* 89274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31961 | /* 89277 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31962 | /* 89280 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31963 | /* 89283 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31964 | /* 89286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31965 | /* 89290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31966 | /* 89294 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31967 | /* 89298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31968 | /* 89302 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31969 | /* 89306 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31970 | /* 89310 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31971 | /* 89310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32), |
| 31972 | /* 89313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31973 | /* 89315 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 31974 | /* 89317 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 31975 | /* 89319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31976 | /* 89322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31977 | /* 89328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31978 | /* 89334 */ GIR_RootConstrainSelectedInstOperands, |
| 31979 | /* 89335 */ // GIR_Coverage, 5243, |
| 31980 | /* 89335 */ GIR_EraseRootFromParent_Done, |
| 31981 | /* 89336 */ // Label 1715: @89336 |
| 31982 | /* 89336 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(89414), // Rule ID 5245 // |
| 31983 | /* 89341 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 31984 | /* 89346 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31985 | /* 89349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31986 | /* 89352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31987 | /* 89355 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31988 | /* 89358 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31989 | /* 89361 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31990 | /* 89364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31991 | /* 89368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31992 | /* 89372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 31993 | /* 89376 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31994 | /* 89380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31995 | /* 89384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31996 | /* 89388 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 31997 | /* 89388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8), |
| 31998 | /* 89391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31999 | /* 89393 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 32000 | /* 89395 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 32001 | /* 89397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32002 | /* 89400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32003 | /* 89406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32004 | /* 89412 */ GIR_RootConstrainSelectedInstOperands, |
| 32005 | /* 89413 */ // GIR_Coverage, 5245, |
| 32006 | /* 89413 */ GIR_EraseRootFromParent_Done, |
| 32007 | /* 89414 */ // Label 1716: @89414 |
| 32008 | /* 89414 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(89492), // Rule ID 5247 // |
| 32009 | /* 89419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 32010 | /* 89424 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32011 | /* 89427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32012 | /* 89430 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32013 | /* 89433 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32014 | /* 89436 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32015 | /* 89439 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32016 | /* 89442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32017 | /* 89446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32018 | /* 89450 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 32019 | /* 89454 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32020 | /* 89458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32021 | /* 89462 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32022 | /* 89466 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 32023 | /* 89466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16), |
| 32024 | /* 89469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32025 | /* 89471 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 32026 | /* 89473 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 32027 | /* 89475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32028 | /* 89478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32029 | /* 89484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32030 | /* 89490 */ GIR_RootConstrainSelectedInstOperands, |
| 32031 | /* 89491 */ // GIR_Coverage, 5247, |
| 32032 | /* 89491 */ GIR_EraseRootFromParent_Done, |
| 32033 | /* 89492 */ // Label 1717: @89492 |
| 32034 | /* 89492 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(89570), // Rule ID 5249 // |
| 32035 | /* 89497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 32036 | /* 89502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 32037 | /* 89505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 32038 | /* 89508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32039 | /* 89511 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32040 | /* 89514 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32041 | /* 89517 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32042 | /* 89520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32043 | /* 89524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32044 | /* 89528 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 32045 | /* 89532 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32046 | /* 89536 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32047 | /* 89540 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32048 | /* 89544 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 32049 | /* 89544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32), |
| 32050 | /* 89547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32051 | /* 89549 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 32052 | /* 89551 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 32053 | /* 89553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32054 | /* 89556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32055 | /* 89562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32056 | /* 89568 */ GIR_RootConstrainSelectedInstOperands, |
| 32057 | /* 89569 */ // GIR_Coverage, 5249, |
| 32058 | /* 89569 */ GIR_EraseRootFromParent_Done, |
| 32059 | /* 89570 */ // Label 1718: @89570 |
| 32060 | /* 89570 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(89706), // Rule ID 3064 // |
| 32061 | /* 89575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 32062 | /* 89578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3), |
| 32063 | /* 89583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 32064 | /* 89586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 32065 | /* 89589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 32066 | /* 89592 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 32067 | /* 89595 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 32068 | /* 89598 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 32069 | /* 89601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 32070 | /* 89605 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4112:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 32071 | /* 89605 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 32072 | /* 89608 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 32073 | /* 89612 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 32074 | /* 89617 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 32075 | /* 89619 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 32076 | /* 89622 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 32077 | /* 89626 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 32078 | /* 89631 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 32079 | /* 89635 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 32080 | /* 89638 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 32081 | /* 89642 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 32082 | /* 89645 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 32083 | /* 89649 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 32084 | /* 89652 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 32085 | /* 89655 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 32086 | /* 89658 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 32087 | /* 89663 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 32088 | /* 89668 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 32089 | /* 89673 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 32090 | /* 89678 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 32091 | /* 89683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo), |
| 32092 | /* 89686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 32093 | /* 89688 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 32094 | /* 89690 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 32095 | /* 89693 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 32096 | /* 89695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32097 | /* 89698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32098 | /* 89704 */ GIR_RootConstrainSelectedInstOperands, |
| 32099 | /* 89705 */ // GIR_Coverage, 3064, |
| 32100 | /* 89705 */ GIR_EraseRootFromParent_Done, |
| 32101 | /* 89706 */ // Label 1719: @89706 |
| 32102 | /* 89706 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(89827), // Rule ID 3065 // |
| 32103 | /* 89711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 32104 | /* 89714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4), |
| 32105 | /* 89719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 32106 | /* 89722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 32107 | /* 89725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 32108 | /* 89728 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 32109 | /* 89731 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 32110 | /* 89734 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 32111 | /* 89737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 32112 | /* 89741 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4109:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 32113 | /* 89741 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 32114 | /* 89744 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 32115 | /* 89748 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 32116 | /* 89753 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 32117 | /* 89757 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 32118 | /* 89760 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 32119 | /* 89764 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 32120 | /* 89767 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 32121 | /* 89771 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 32122 | /* 89774 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3 |
| 32123 | /* 89778 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 32124 | /* 89781 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 32125 | /* 89786 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 32126 | /* 89791 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 32127 | /* 89796 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 32128 | /* 89801 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 32129 | /* 89806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo), |
| 32130 | /* 89809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 32131 | /* 89811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 32132 | /* 89814 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 32133 | /* 89816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32134 | /* 89819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32135 | /* 89825 */ GIR_RootConstrainSelectedInstOperands, |
| 32136 | /* 89826 */ // GIR_Coverage, 3065, |
| 32137 | /* 89826 */ GIR_EraseRootFromParent_Done, |
| 32138 | /* 89827 */ // Label 1720: @89827 |
| 32139 | /* 89827 */ GIM_Reject, |
| 32140 | /* 89828 */ // Label 1658: @89828 |
| 32141 | /* 89828 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(94721), |
| 32142 | /* 89833 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 32143 | /* 89836 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(89924), // Rule ID 3557 // |
| 32144 | /* 89841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32145 | /* 89844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32146 | /* 89849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32147 | /* 89852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32148 | /* 89855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32149 | /* 89858 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32150 | /* 89861 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32151 | /* 89864 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32152 | /* 89867 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32153 | /* 89870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32154 | /* 89874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32155 | /* 89878 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32156 | /* 89882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32157 | /* 89886 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32158 | /* 89890 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32159 | /* 89894 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32160 | /* 89898 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32161 | /* 89898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8), |
| 32162 | /* 89901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32163 | /* 89903 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32164 | /* 89905 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32165 | /* 89907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32166 | /* 89910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32167 | /* 89916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32168 | /* 89922 */ GIR_RootConstrainSelectedInstOperands, |
| 32169 | /* 89923 */ // GIR_Coverage, 3557, |
| 32170 | /* 89923 */ GIR_EraseRootFromParent_Done, |
| 32171 | /* 89924 */ // Label 1722: @89924 |
| 32172 | /* 89924 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(90012), // Rule ID 3561 // |
| 32173 | /* 89929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32174 | /* 89932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32175 | /* 89937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32176 | /* 89940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32177 | /* 89943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32178 | /* 89946 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32179 | /* 89949 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32180 | /* 89952 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32181 | /* 89955 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32182 | /* 89958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32183 | /* 89962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32184 | /* 89966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32185 | /* 89970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32186 | /* 89974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32187 | /* 89978 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32188 | /* 89982 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32189 | /* 89986 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32190 | /* 89986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8), |
| 32191 | /* 89989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32192 | /* 89991 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32193 | /* 89993 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32194 | /* 89995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32195 | /* 89998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32196 | /* 90004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32197 | /* 90010 */ GIR_RootConstrainSelectedInstOperands, |
| 32198 | /* 90011 */ // GIR_Coverage, 3561, |
| 32199 | /* 90011 */ GIR_EraseRootFromParent_Done, |
| 32200 | /* 90012 */ // Label 1723: @90012 |
| 32201 | /* 90012 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(90100), // Rule ID 3565 // |
| 32202 | /* 90017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32203 | /* 90020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32204 | /* 90025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32205 | /* 90028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32206 | /* 90031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32207 | /* 90034 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32208 | /* 90037 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32209 | /* 90040 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32210 | /* 90043 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32211 | /* 90046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32212 | /* 90050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 32213 | /* 90054 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32214 | /* 90058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32215 | /* 90062 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32216 | /* 90066 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32217 | /* 90070 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32218 | /* 90074 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32219 | /* 90074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 32220 | /* 90077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32221 | /* 90079 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32222 | /* 90081 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32223 | /* 90083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32224 | /* 90086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32225 | /* 90092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32226 | /* 90098 */ GIR_RootConstrainSelectedInstOperands, |
| 32227 | /* 90099 */ // GIR_Coverage, 3565, |
| 32228 | /* 90099 */ GIR_EraseRootFromParent_Done, |
| 32229 | /* 90100 */ // Label 1724: @90100 |
| 32230 | /* 90100 */ GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(90188), // Rule ID 3569 // |
| 32231 | /* 90105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32232 | /* 90108 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32233 | /* 90113 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32234 | /* 90116 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32235 | /* 90119 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32236 | /* 90122 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32237 | /* 90125 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32238 | /* 90128 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32239 | /* 90131 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32240 | /* 90134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32241 | /* 90138 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32242 | /* 90142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32243 | /* 90146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32244 | /* 90150 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32245 | /* 90154 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32246 | /* 90158 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32247 | /* 90162 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32248 | /* 90162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16), |
| 32249 | /* 90165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32250 | /* 90167 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32251 | /* 90169 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32252 | /* 90171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32253 | /* 90174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32254 | /* 90180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32255 | /* 90186 */ GIR_RootConstrainSelectedInstOperands, |
| 32256 | /* 90187 */ // GIR_Coverage, 3569, |
| 32257 | /* 90187 */ GIR_EraseRootFromParent_Done, |
| 32258 | /* 90188 */ // Label 1725: @90188 |
| 32259 | /* 90188 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(90276), // Rule ID 3573 // |
| 32260 | /* 90193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32261 | /* 90196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32262 | /* 90201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32263 | /* 90204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32264 | /* 90207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32265 | /* 90210 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32266 | /* 90213 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32267 | /* 90216 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32268 | /* 90219 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32269 | /* 90222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32270 | /* 90226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32271 | /* 90230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32272 | /* 90234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32273 | /* 90238 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32274 | /* 90242 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32275 | /* 90246 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32276 | /* 90250 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32277 | /* 90250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16), |
| 32278 | /* 90253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32279 | /* 90255 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32280 | /* 90257 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32281 | /* 90259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32282 | /* 90262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32283 | /* 90268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32284 | /* 90274 */ GIR_RootConstrainSelectedInstOperands, |
| 32285 | /* 90275 */ // GIR_Coverage, 3573, |
| 32286 | /* 90275 */ GIR_EraseRootFromParent_Done, |
| 32287 | /* 90276 */ // Label 1726: @90276 |
| 32288 | /* 90276 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(90364), // Rule ID 3577 // |
| 32289 | /* 90281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32290 | /* 90284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32291 | /* 90289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32292 | /* 90292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32293 | /* 90295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32294 | /* 90298 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32295 | /* 90301 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32296 | /* 90304 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32297 | /* 90307 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32298 | /* 90310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32299 | /* 90314 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 32300 | /* 90318 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32301 | /* 90322 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32302 | /* 90326 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32303 | /* 90330 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32304 | /* 90334 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32305 | /* 90338 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32306 | /* 90338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 32307 | /* 90341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32308 | /* 90343 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32309 | /* 90345 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32310 | /* 90347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32311 | /* 90350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32312 | /* 90356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32313 | /* 90362 */ GIR_RootConstrainSelectedInstOperands, |
| 32314 | /* 90363 */ // GIR_Coverage, 3577, |
| 32315 | /* 90363 */ GIR_EraseRootFromParent_Done, |
| 32316 | /* 90364 */ // Label 1727: @90364 |
| 32317 | /* 90364 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(90452), // Rule ID 3581 // |
| 32318 | /* 90369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32319 | /* 90372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32320 | /* 90377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32321 | /* 90380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32322 | /* 90383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32323 | /* 90386 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32324 | /* 90389 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32325 | /* 90392 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32326 | /* 90395 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32327 | /* 90398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32328 | /* 90402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32329 | /* 90406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32330 | /* 90410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32331 | /* 90414 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32332 | /* 90418 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32333 | /* 90422 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32334 | /* 90426 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32335 | /* 90426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32), |
| 32336 | /* 90429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32337 | /* 90431 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32338 | /* 90433 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32339 | /* 90435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32340 | /* 90438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32341 | /* 90444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32342 | /* 90450 */ GIR_RootConstrainSelectedInstOperands, |
| 32343 | /* 90451 */ // GIR_Coverage, 3581, |
| 32344 | /* 90451 */ GIR_EraseRootFromParent_Done, |
| 32345 | /* 90452 */ // Label 1728: @90452 |
| 32346 | /* 90452 */ GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(90540), // Rule ID 3585 // |
| 32347 | /* 90457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32348 | /* 90460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32349 | /* 90465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32350 | /* 90468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32351 | /* 90471 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32352 | /* 90474 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32353 | /* 90477 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32354 | /* 90480 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32355 | /* 90483 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32356 | /* 90486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32357 | /* 90490 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32358 | /* 90494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32359 | /* 90498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32360 | /* 90502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32361 | /* 90506 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32362 | /* 90510 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32363 | /* 90514 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32364 | /* 90514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32), |
| 32365 | /* 90517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32366 | /* 90519 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32367 | /* 90521 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32368 | /* 90523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32369 | /* 90526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32370 | /* 90532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32371 | /* 90538 */ GIR_RootConstrainSelectedInstOperands, |
| 32372 | /* 90539 */ // GIR_Coverage, 3585, |
| 32373 | /* 90539 */ GIR_EraseRootFromParent_Done, |
| 32374 | /* 90540 */ // Label 1729: @90540 |
| 32375 | /* 90540 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(90628), // Rule ID 3589 // |
| 32376 | /* 90545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32377 | /* 90548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32378 | /* 90553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32379 | /* 90556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32380 | /* 90559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32381 | /* 90562 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32382 | /* 90565 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32383 | /* 90568 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32384 | /* 90571 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32385 | /* 90574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32386 | /* 90578 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 32387 | /* 90582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32388 | /* 90586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32389 | /* 90590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32390 | /* 90594 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32391 | /* 90598 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32392 | /* 90602 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32393 | /* 90602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 32394 | /* 90605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32395 | /* 90607 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32396 | /* 90609 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32397 | /* 90611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32398 | /* 90614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32399 | /* 90620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32400 | /* 90626 */ GIR_RootConstrainSelectedInstOperands, |
| 32401 | /* 90627 */ // GIR_Coverage, 3589, |
| 32402 | /* 90627 */ GIR_EraseRootFromParent_Done, |
| 32403 | /* 90628 */ // Label 1730: @90628 |
| 32404 | /* 90628 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(90716), // Rule ID 3593 // |
| 32405 | /* 90633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32406 | /* 90636 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32407 | /* 90641 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32408 | /* 90644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32409 | /* 90647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32410 | /* 90650 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32411 | /* 90653 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32412 | /* 90656 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32413 | /* 90659 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32414 | /* 90662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32415 | /* 90666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32416 | /* 90670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32417 | /* 90674 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32418 | /* 90678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32419 | /* 90682 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32420 | /* 90686 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32421 | /* 90690 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32422 | /* 90690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8), |
| 32423 | /* 90693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32424 | /* 90695 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32425 | /* 90697 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32426 | /* 90699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32427 | /* 90702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32428 | /* 90708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32429 | /* 90714 */ GIR_RootConstrainSelectedInstOperands, |
| 32430 | /* 90715 */ // GIR_Coverage, 3593, |
| 32431 | /* 90715 */ GIR_EraseRootFromParent_Done, |
| 32432 | /* 90716 */ // Label 1731: @90716 |
| 32433 | /* 90716 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(90804), // Rule ID 3597 // |
| 32434 | /* 90721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32435 | /* 90724 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32436 | /* 90729 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32437 | /* 90732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32438 | /* 90735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32439 | /* 90738 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32440 | /* 90741 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32441 | /* 90744 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32442 | /* 90747 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32443 | /* 90750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32444 | /* 90754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32445 | /* 90758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32446 | /* 90762 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32447 | /* 90766 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32448 | /* 90770 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32449 | /* 90774 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32450 | /* 90778 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32451 | /* 90778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8), |
| 32452 | /* 90781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32453 | /* 90783 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32454 | /* 90785 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32455 | /* 90787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32456 | /* 90790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32457 | /* 90796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32458 | /* 90802 */ GIR_RootConstrainSelectedInstOperands, |
| 32459 | /* 90803 */ // GIR_Coverage, 3597, |
| 32460 | /* 90803 */ GIR_EraseRootFromParent_Done, |
| 32461 | /* 90804 */ // Label 1732: @90804 |
| 32462 | /* 90804 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(90892), // Rule ID 3601 // |
| 32463 | /* 90809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32464 | /* 90812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32465 | /* 90817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32466 | /* 90820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32467 | /* 90823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32468 | /* 90826 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32469 | /* 90829 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32470 | /* 90832 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32471 | /* 90835 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32472 | /* 90838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32473 | /* 90842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32474 | /* 90846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32475 | /* 90850 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32476 | /* 90854 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32477 | /* 90858 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32478 | /* 90862 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32479 | /* 90866 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32480 | /* 90866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16), |
| 32481 | /* 90869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32482 | /* 90871 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32483 | /* 90873 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32484 | /* 90875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32485 | /* 90878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32486 | /* 90884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32487 | /* 90890 */ GIR_RootConstrainSelectedInstOperands, |
| 32488 | /* 90891 */ // GIR_Coverage, 3601, |
| 32489 | /* 90891 */ GIR_EraseRootFromParent_Done, |
| 32490 | /* 90892 */ // Label 1733: @90892 |
| 32491 | /* 90892 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(90980), // Rule ID 3605 // |
| 32492 | /* 90897 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32493 | /* 90900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32494 | /* 90905 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32495 | /* 90908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32496 | /* 90911 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32497 | /* 90914 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32498 | /* 90917 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32499 | /* 90920 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32500 | /* 90923 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32501 | /* 90926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32502 | /* 90930 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32503 | /* 90934 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32504 | /* 90938 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32505 | /* 90942 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32506 | /* 90946 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32507 | /* 90950 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32508 | /* 90954 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32509 | /* 90954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16), |
| 32510 | /* 90957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32511 | /* 90959 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32512 | /* 90961 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32513 | /* 90963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32514 | /* 90966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32515 | /* 90972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32516 | /* 90978 */ GIR_RootConstrainSelectedInstOperands, |
| 32517 | /* 90979 */ // GIR_Coverage, 3605, |
| 32518 | /* 90979 */ GIR_EraseRootFromParent_Done, |
| 32519 | /* 90980 */ // Label 1734: @90980 |
| 32520 | /* 90980 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(91068), // Rule ID 3609 // |
| 32521 | /* 90985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32522 | /* 90988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32523 | /* 90993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32524 | /* 90996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32525 | /* 90999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32526 | /* 91002 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32527 | /* 91005 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32528 | /* 91008 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32529 | /* 91011 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32530 | /* 91014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32531 | /* 91018 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32532 | /* 91022 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32533 | /* 91026 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32534 | /* 91030 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32535 | /* 91034 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32536 | /* 91038 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32537 | /* 91042 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32538 | /* 91042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32), |
| 32539 | /* 91045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32540 | /* 91047 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32541 | /* 91049 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32542 | /* 91051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32543 | /* 91054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32544 | /* 91060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32545 | /* 91066 */ GIR_RootConstrainSelectedInstOperands, |
| 32546 | /* 91067 */ // GIR_Coverage, 3609, |
| 32547 | /* 91067 */ GIR_EraseRootFromParent_Done, |
| 32548 | /* 91068 */ // Label 1735: @91068 |
| 32549 | /* 91068 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(91156), // Rule ID 3613 // |
| 32550 | /* 91073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32551 | /* 91076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32552 | /* 91081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32553 | /* 91084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32554 | /* 91087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32555 | /* 91090 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32556 | /* 91093 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32557 | /* 91096 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32558 | /* 91099 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32559 | /* 91102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32560 | /* 91106 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32561 | /* 91110 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32562 | /* 91114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32563 | /* 91118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32564 | /* 91122 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32565 | /* 91126 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32566 | /* 91130 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32567 | /* 91130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32), |
| 32568 | /* 91133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32569 | /* 91135 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32570 | /* 91137 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32571 | /* 91139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32572 | /* 91142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32573 | /* 91148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32574 | /* 91154 */ GIR_RootConstrainSelectedInstOperands, |
| 32575 | /* 91155 */ // GIR_Coverage, 3613, |
| 32576 | /* 91155 */ GIR_EraseRootFromParent_Done, |
| 32577 | /* 91156 */ // Label 1736: @91156 |
| 32578 | /* 91156 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(91246), // Rule ID 3559 // |
| 32579 | /* 91161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32580 | /* 91164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32581 | /* 91169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32582 | /* 91172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32583 | /* 91175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32584 | /* 91178 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32585 | /* 91181 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32586 | /* 91184 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32587 | /* 91187 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32588 | /* 91190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32589 | /* 91194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32590 | /* 91198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32591 | /* 91202 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32592 | /* 91206 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32593 | /* 91210 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32594 | /* 91214 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32595 | /* 91218 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32596 | /* 91218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8), |
| 32597 | /* 91221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32598 | /* 91223 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32599 | /* 91225 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32600 | /* 91227 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32601 | /* 91229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32602 | /* 91232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32603 | /* 91238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32604 | /* 91244 */ GIR_RootConstrainSelectedInstOperands, |
| 32605 | /* 91245 */ // GIR_Coverage, 3559, |
| 32606 | /* 91245 */ GIR_EraseRootFromParent_Done, |
| 32607 | /* 91246 */ // Label 1737: @91246 |
| 32608 | /* 91246 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(91336), // Rule ID 3563 // |
| 32609 | /* 91251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32610 | /* 91254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32611 | /* 91259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32612 | /* 91262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32613 | /* 91265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32614 | /* 91268 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32615 | /* 91271 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32616 | /* 91274 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32617 | /* 91277 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32618 | /* 91280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32619 | /* 91284 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32620 | /* 91288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32621 | /* 91292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32622 | /* 91296 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32623 | /* 91300 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32624 | /* 91304 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32625 | /* 91308 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32626 | /* 91308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8), |
| 32627 | /* 91311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32628 | /* 91313 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32629 | /* 91315 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32630 | /* 91317 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32631 | /* 91319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32632 | /* 91322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32633 | /* 91328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32634 | /* 91334 */ GIR_RootConstrainSelectedInstOperands, |
| 32635 | /* 91335 */ // GIR_Coverage, 3563, |
| 32636 | /* 91335 */ GIR_EraseRootFromParent_Done, |
| 32637 | /* 91336 */ // Label 1738: @91336 |
| 32638 | /* 91336 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(91426), // Rule ID 3567 // |
| 32639 | /* 91341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32640 | /* 91344 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32641 | /* 91349 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32642 | /* 91352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32643 | /* 91355 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32644 | /* 91358 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32645 | /* 91361 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32646 | /* 91364 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32647 | /* 91367 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32648 | /* 91370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32649 | /* 91374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 32650 | /* 91378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32651 | /* 91382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32652 | /* 91386 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32653 | /* 91390 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32654 | /* 91394 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32655 | /* 91398 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32656 | /* 91398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 32657 | /* 91401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32658 | /* 91403 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32659 | /* 91405 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32660 | /* 91407 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32661 | /* 91409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32662 | /* 91412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32663 | /* 91418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32664 | /* 91424 */ GIR_RootConstrainSelectedInstOperands, |
| 32665 | /* 91425 */ // GIR_Coverage, 3567, |
| 32666 | /* 91425 */ GIR_EraseRootFromParent_Done, |
| 32667 | /* 91426 */ // Label 1739: @91426 |
| 32668 | /* 91426 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(91516), // Rule ID 3571 // |
| 32669 | /* 91431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32670 | /* 91434 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32671 | /* 91439 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32672 | /* 91442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32673 | /* 91445 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32674 | /* 91448 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32675 | /* 91451 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32676 | /* 91454 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32677 | /* 91457 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32678 | /* 91460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32679 | /* 91464 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32680 | /* 91468 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32681 | /* 91472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32682 | /* 91476 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32683 | /* 91480 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32684 | /* 91484 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32685 | /* 91488 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32686 | /* 91488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16), |
| 32687 | /* 91491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32688 | /* 91493 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32689 | /* 91495 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32690 | /* 91497 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32691 | /* 91499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32692 | /* 91502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32693 | /* 91508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32694 | /* 91514 */ GIR_RootConstrainSelectedInstOperands, |
| 32695 | /* 91515 */ // GIR_Coverage, 3571, |
| 32696 | /* 91515 */ GIR_EraseRootFromParent_Done, |
| 32697 | /* 91516 */ // Label 1740: @91516 |
| 32698 | /* 91516 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(91606), // Rule ID 3575 // |
| 32699 | /* 91521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32700 | /* 91524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32701 | /* 91529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32702 | /* 91532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32703 | /* 91535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32704 | /* 91538 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32705 | /* 91541 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32706 | /* 91544 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32707 | /* 91547 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32708 | /* 91550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32709 | /* 91554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32710 | /* 91558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32711 | /* 91562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32712 | /* 91566 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32713 | /* 91570 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32714 | /* 91574 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32715 | /* 91578 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32716 | /* 91578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16), |
| 32717 | /* 91581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32718 | /* 91583 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32719 | /* 91585 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32720 | /* 91587 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32721 | /* 91589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32722 | /* 91592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32723 | /* 91598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32724 | /* 91604 */ GIR_RootConstrainSelectedInstOperands, |
| 32725 | /* 91605 */ // GIR_Coverage, 3575, |
| 32726 | /* 91605 */ GIR_EraseRootFromParent_Done, |
| 32727 | /* 91606 */ // Label 1741: @91606 |
| 32728 | /* 91606 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(91696), // Rule ID 3579 // |
| 32729 | /* 91611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32730 | /* 91614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32731 | /* 91619 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32732 | /* 91622 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32733 | /* 91625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32734 | /* 91628 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32735 | /* 91631 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32736 | /* 91634 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32737 | /* 91637 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32738 | /* 91640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32739 | /* 91644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 32740 | /* 91648 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32741 | /* 91652 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32742 | /* 91656 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32743 | /* 91660 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32744 | /* 91664 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32745 | /* 91668 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32746 | /* 91668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 32747 | /* 91671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32748 | /* 91673 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32749 | /* 91675 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32750 | /* 91677 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32751 | /* 91679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32752 | /* 91682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32753 | /* 91688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32754 | /* 91694 */ GIR_RootConstrainSelectedInstOperands, |
| 32755 | /* 91695 */ // GIR_Coverage, 3579, |
| 32756 | /* 91695 */ GIR_EraseRootFromParent_Done, |
| 32757 | /* 91696 */ // Label 1742: @91696 |
| 32758 | /* 91696 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(91786), // Rule ID 3583 // |
| 32759 | /* 91701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32760 | /* 91704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32761 | /* 91709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32762 | /* 91712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32763 | /* 91715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32764 | /* 91718 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32765 | /* 91721 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32766 | /* 91724 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32767 | /* 91727 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32768 | /* 91730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32769 | /* 91734 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32770 | /* 91738 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32771 | /* 91742 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32772 | /* 91746 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32773 | /* 91750 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32774 | /* 91754 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32775 | /* 91758 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32776 | /* 91758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32), |
| 32777 | /* 91761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32778 | /* 91763 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32779 | /* 91765 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32780 | /* 91767 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32781 | /* 91769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32782 | /* 91772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32783 | /* 91778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32784 | /* 91784 */ GIR_RootConstrainSelectedInstOperands, |
| 32785 | /* 91785 */ // GIR_Coverage, 3583, |
| 32786 | /* 91785 */ GIR_EraseRootFromParent_Done, |
| 32787 | /* 91786 */ // Label 1743: @91786 |
| 32788 | /* 91786 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(91876), // Rule ID 3587 // |
| 32789 | /* 91791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32790 | /* 91794 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32791 | /* 91799 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32792 | /* 91802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32793 | /* 91805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32794 | /* 91808 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32795 | /* 91811 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32796 | /* 91814 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32797 | /* 91817 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32798 | /* 91820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32799 | /* 91824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32800 | /* 91828 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32801 | /* 91832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32802 | /* 91836 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32803 | /* 91840 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32804 | /* 91844 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32805 | /* 91848 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32806 | /* 91848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32), |
| 32807 | /* 91851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32808 | /* 91853 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32809 | /* 91855 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32810 | /* 91857 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32811 | /* 91859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32812 | /* 91862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32813 | /* 91868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32814 | /* 91874 */ GIR_RootConstrainSelectedInstOperands, |
| 32815 | /* 91875 */ // GIR_Coverage, 3587, |
| 32816 | /* 91875 */ GIR_EraseRootFromParent_Done, |
| 32817 | /* 91876 */ // Label 1744: @91876 |
| 32818 | /* 91876 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(91966), // Rule ID 3591 // |
| 32819 | /* 91881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32820 | /* 91884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32821 | /* 91889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32822 | /* 91892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32823 | /* 91895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32824 | /* 91898 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32825 | /* 91901 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32826 | /* 91904 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32827 | /* 91907 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32828 | /* 91910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32829 | /* 91914 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 32830 | /* 91918 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 32831 | /* 91922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32832 | /* 91926 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32833 | /* 91930 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32834 | /* 91934 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32835 | /* 91938 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32836 | /* 91938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 32837 | /* 91941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32838 | /* 91943 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32839 | /* 91945 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32840 | /* 91947 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32841 | /* 91949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32842 | /* 91952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32843 | /* 91958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32844 | /* 91964 */ GIR_RootConstrainSelectedInstOperands, |
| 32845 | /* 91965 */ // GIR_Coverage, 3591, |
| 32846 | /* 91965 */ GIR_EraseRootFromParent_Done, |
| 32847 | /* 91966 */ // Label 1745: @91966 |
| 32848 | /* 91966 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(92056), // Rule ID 3595 // |
| 32849 | /* 91971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32850 | /* 91974 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32851 | /* 91979 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32852 | /* 91982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32853 | /* 91985 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32854 | /* 91988 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32855 | /* 91991 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32856 | /* 91994 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32857 | /* 91997 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32858 | /* 92000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32859 | /* 92004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32860 | /* 92008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32861 | /* 92012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32862 | /* 92016 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32863 | /* 92020 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32864 | /* 92024 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32865 | /* 92028 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32866 | /* 92028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8), |
| 32867 | /* 92031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32868 | /* 92033 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32869 | /* 92035 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32870 | /* 92037 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32871 | /* 92039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32872 | /* 92042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32873 | /* 92048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32874 | /* 92054 */ GIR_RootConstrainSelectedInstOperands, |
| 32875 | /* 92055 */ // GIR_Coverage, 3595, |
| 32876 | /* 92055 */ GIR_EraseRootFromParent_Done, |
| 32877 | /* 92056 */ // Label 1746: @92056 |
| 32878 | /* 92056 */ GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(92146), // Rule ID 3599 // |
| 32879 | /* 92061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32880 | /* 92064 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32881 | /* 92069 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32882 | /* 92072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32883 | /* 92075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32884 | /* 92078 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32885 | /* 92081 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32886 | /* 92084 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 32887 | /* 92087 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 32888 | /* 92090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32889 | /* 92094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32890 | /* 92098 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32891 | /* 92102 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32892 | /* 92106 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32893 | /* 92110 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32894 | /* 92114 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32895 | /* 92118 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 32896 | /* 92118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8), |
| 32897 | /* 92121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32898 | /* 92123 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32899 | /* 92125 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32900 | /* 92127 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32901 | /* 92129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32902 | /* 92132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32903 | /* 92138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32904 | /* 92144 */ GIR_RootConstrainSelectedInstOperands, |
| 32905 | /* 92145 */ // GIR_Coverage, 3599, |
| 32906 | /* 92145 */ GIR_EraseRootFromParent_Done, |
| 32907 | /* 92146 */ // Label 1747: @92146 |
| 32908 | /* 92146 */ GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(92236), // Rule ID 3603 // |
| 32909 | /* 92151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32910 | /* 92154 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32911 | /* 92159 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32912 | /* 92162 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32913 | /* 92165 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32914 | /* 92168 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32915 | /* 92171 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32916 | /* 92174 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32917 | /* 92177 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32918 | /* 92180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32919 | /* 92184 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32920 | /* 92188 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32921 | /* 92192 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32922 | /* 92196 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32923 | /* 92200 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32924 | /* 92204 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32925 | /* 92208 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32926 | /* 92208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16), |
| 32927 | /* 92211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32928 | /* 92213 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32929 | /* 92215 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32930 | /* 92217 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32931 | /* 92219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32932 | /* 92222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32933 | /* 92228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32934 | /* 92234 */ GIR_RootConstrainSelectedInstOperands, |
| 32935 | /* 92235 */ // GIR_Coverage, 3603, |
| 32936 | /* 92235 */ GIR_EraseRootFromParent_Done, |
| 32937 | /* 92236 */ // Label 1748: @92236 |
| 32938 | /* 92236 */ GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(92326), // Rule ID 3607 // |
| 32939 | /* 92241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32940 | /* 92244 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32941 | /* 92249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32942 | /* 92252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32943 | /* 92255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32944 | /* 92258 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32945 | /* 92261 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32946 | /* 92264 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 32947 | /* 92267 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 32948 | /* 92270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32949 | /* 92274 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32950 | /* 92278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32951 | /* 92282 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 32952 | /* 92286 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32953 | /* 92290 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32954 | /* 92294 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32955 | /* 92298 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 32956 | /* 92298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16), |
| 32957 | /* 92301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32958 | /* 92303 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32959 | /* 92305 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32960 | /* 92307 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32961 | /* 92309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32962 | /* 92312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32963 | /* 92318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32964 | /* 92324 */ GIR_RootConstrainSelectedInstOperands, |
| 32965 | /* 92325 */ // GIR_Coverage, 3607, |
| 32966 | /* 92325 */ GIR_EraseRootFromParent_Done, |
| 32967 | /* 92326 */ // Label 1749: @92326 |
| 32968 | /* 92326 */ GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(92416), // Rule ID 3611 // |
| 32969 | /* 92331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 32970 | /* 92334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 32971 | /* 92339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32972 | /* 92342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32973 | /* 92345 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32974 | /* 92348 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32975 | /* 92351 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32976 | /* 92354 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 32977 | /* 92357 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 32978 | /* 92360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32979 | /* 92364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 32980 | /* 92368 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 32981 | /* 92372 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 32982 | /* 92376 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 32983 | /* 92380 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32984 | /* 92384 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32985 | /* 92388 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 32986 | /* 92388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32), |
| 32987 | /* 92391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 32988 | /* 92393 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 32989 | /* 92395 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 32990 | /* 92397 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 32991 | /* 92399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32992 | /* 92402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32993 | /* 92408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32994 | /* 92414 */ GIR_RootConstrainSelectedInstOperands, |
| 32995 | /* 92415 */ // GIR_Coverage, 3611, |
| 32996 | /* 92415 */ GIR_EraseRootFromParent_Done, |
| 32997 | /* 92416 */ // Label 1750: @92416 |
| 32998 | /* 92416 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(92506), // Rule ID 3615 // |
| 32999 | /* 92421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 33000 | /* 92424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 33001 | /* 92429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33002 | /* 92432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33003 | /* 92435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33004 | /* 92438 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33005 | /* 92441 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33006 | /* 92444 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 33007 | /* 92447 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 33008 | /* 92450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 33009 | /* 92454 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 33010 | /* 92458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 33011 | /* 92462 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 33012 | /* 92466 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 33013 | /* 92470 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33014 | /* 92474 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33015 | /* 92478 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 33016 | /* 92478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32), |
| 33017 | /* 92481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 33018 | /* 92483 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 33019 | /* 92485 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 33020 | /* 92487 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 33021 | /* 92489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33022 | /* 92492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33023 | /* 92498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33024 | /* 92504 */ GIR_RootConstrainSelectedInstOperands, |
| 33025 | /* 92505 */ // GIR_Coverage, 3615, |
| 33026 | /* 92505 */ GIR_EraseRootFromParent_Done, |
| 33027 | /* 92506 */ // Label 1751: @92506 |
| 33028 | /* 92506 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(92593), // Rule ID 4825 // |
| 33029 | /* 92511 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33030 | /* 92516 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33031 | /* 92519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33032 | /* 92522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33033 | /* 92525 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33034 | /* 92528 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33035 | /* 92531 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33036 | /* 92534 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33037 | /* 92537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33038 | /* 92541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33039 | /* 92545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33040 | /* 92549 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33041 | /* 92553 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33042 | /* 92557 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33043 | /* 92561 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33044 | /* 92565 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33045 | /* 92565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8), |
| 33046 | /* 92568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33047 | /* 92570 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33048 | /* 92572 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33049 | /* 92574 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33050 | /* 92576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33051 | /* 92579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33052 | /* 92585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33053 | /* 92591 */ GIR_RootConstrainSelectedInstOperands, |
| 33054 | /* 92592 */ // GIR_Coverage, 4825, |
| 33055 | /* 92592 */ GIR_EraseRootFromParent_Done, |
| 33056 | /* 92593 */ // Label 1752: @92593 |
| 33057 | /* 92593 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(92680), // Rule ID 4827 // |
| 33058 | /* 92598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33059 | /* 92603 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33060 | /* 92606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33061 | /* 92609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33062 | /* 92612 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33063 | /* 92615 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33064 | /* 92618 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33065 | /* 92621 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33066 | /* 92624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33067 | /* 92628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33068 | /* 92632 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33069 | /* 92636 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33070 | /* 92640 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33071 | /* 92644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33072 | /* 92648 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33073 | /* 92652 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33074 | /* 92652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16), |
| 33075 | /* 92655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33076 | /* 92657 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33077 | /* 92659 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33078 | /* 92661 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33079 | /* 92663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33080 | /* 92666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33081 | /* 92672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33082 | /* 92678 */ GIR_RootConstrainSelectedInstOperands, |
| 33083 | /* 92679 */ // GIR_Coverage, 4827, |
| 33084 | /* 92679 */ GIR_EraseRootFromParent_Done, |
| 33085 | /* 92680 */ // Label 1753: @92680 |
| 33086 | /* 92680 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(92767), // Rule ID 4829 // |
| 33087 | /* 92685 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33088 | /* 92690 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33089 | /* 92693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33090 | /* 92696 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33091 | /* 92699 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33092 | /* 92702 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33093 | /* 92705 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33094 | /* 92708 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33095 | /* 92711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33096 | /* 92715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33097 | /* 92719 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33098 | /* 92723 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33099 | /* 92727 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33100 | /* 92731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33101 | /* 92735 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33102 | /* 92739 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33103 | /* 92739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32), |
| 33104 | /* 92742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33105 | /* 92744 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33106 | /* 92746 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33107 | /* 92748 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33108 | /* 92750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33109 | /* 92753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33110 | /* 92759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33111 | /* 92765 */ GIR_RootConstrainSelectedInstOperands, |
| 33112 | /* 92766 */ // GIR_Coverage, 4829, |
| 33113 | /* 92766 */ GIR_EraseRootFromParent_Done, |
| 33114 | /* 92767 */ // Label 1754: @92767 |
| 33115 | /* 92767 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(92854), // Rule ID 4831 // |
| 33116 | /* 92772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33117 | /* 92777 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33118 | /* 92780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33119 | /* 92783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33120 | /* 92786 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33121 | /* 92789 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33122 | /* 92792 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33123 | /* 92795 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33124 | /* 92798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33125 | /* 92802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33126 | /* 92806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33127 | /* 92810 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33128 | /* 92814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33129 | /* 92818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33130 | /* 92822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33131 | /* 92826 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33132 | /* 92826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8), |
| 33133 | /* 92829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33134 | /* 92831 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33135 | /* 92833 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33136 | /* 92835 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33137 | /* 92837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33138 | /* 92840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33139 | /* 92846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33140 | /* 92852 */ GIR_RootConstrainSelectedInstOperands, |
| 33141 | /* 92853 */ // GIR_Coverage, 4831, |
| 33142 | /* 92853 */ GIR_EraseRootFromParent_Done, |
| 33143 | /* 92854 */ // Label 1755: @92854 |
| 33144 | /* 92854 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(92941), // Rule ID 4833 // |
| 33145 | /* 92859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33146 | /* 92864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33147 | /* 92867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33148 | /* 92870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33149 | /* 92873 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33150 | /* 92876 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33151 | /* 92879 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33152 | /* 92882 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33153 | /* 92885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33154 | /* 92889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33155 | /* 92893 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33156 | /* 92897 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33157 | /* 92901 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33158 | /* 92905 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33159 | /* 92909 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33160 | /* 92913 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33161 | /* 92913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16), |
| 33162 | /* 92916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33163 | /* 92918 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33164 | /* 92920 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33165 | /* 92922 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33166 | /* 92924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33167 | /* 92927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33168 | /* 92933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33169 | /* 92939 */ GIR_RootConstrainSelectedInstOperands, |
| 33170 | /* 92940 */ // GIR_Coverage, 4833, |
| 33171 | /* 92940 */ GIR_EraseRootFromParent_Done, |
| 33172 | /* 92941 */ // Label 1756: @92941 |
| 33173 | /* 92941 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(93028), // Rule ID 4835 // |
| 33174 | /* 92946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33175 | /* 92951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33176 | /* 92954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33177 | /* 92957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33178 | /* 92960 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33179 | /* 92963 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33180 | /* 92966 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33181 | /* 92969 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33182 | /* 92972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33183 | /* 92976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33184 | /* 92980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33185 | /* 92984 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33186 | /* 92988 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33187 | /* 92992 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33188 | /* 92996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33189 | /* 93000 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33190 | /* 93000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32), |
| 33191 | /* 93003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33192 | /* 93005 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33193 | /* 93007 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33194 | /* 93009 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33195 | /* 93011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33196 | /* 93014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33197 | /* 93020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33198 | /* 93026 */ GIR_RootConstrainSelectedInstOperands, |
| 33199 | /* 93027 */ // GIR_Coverage, 4835, |
| 33200 | /* 93027 */ GIR_EraseRootFromParent_Done, |
| 33201 | /* 93028 */ // Label 1757: @93028 |
| 33202 | /* 93028 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(93115), // Rule ID 4837 // |
| 33203 | /* 93033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33204 | /* 93038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33205 | /* 93041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33206 | /* 93044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33207 | /* 93047 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33208 | /* 93050 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33209 | /* 93053 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33210 | /* 93056 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33211 | /* 93059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33212 | /* 93063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33213 | /* 93067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33214 | /* 93071 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33215 | /* 93075 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33216 | /* 93079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33217 | /* 93083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33218 | /* 93087 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33219 | /* 93087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8), |
| 33220 | /* 93090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33221 | /* 93092 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33222 | /* 93094 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33223 | /* 93096 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33224 | /* 93098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33225 | /* 93101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33226 | /* 93107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33227 | /* 93113 */ GIR_RootConstrainSelectedInstOperands, |
| 33228 | /* 93114 */ // GIR_Coverage, 4837, |
| 33229 | /* 93114 */ GIR_EraseRootFromParent_Done, |
| 33230 | /* 93115 */ // Label 1758: @93115 |
| 33231 | /* 93115 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(93202), // Rule ID 4839 // |
| 33232 | /* 93120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33233 | /* 93125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33234 | /* 93128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33235 | /* 93131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33236 | /* 93134 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33237 | /* 93137 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33238 | /* 93140 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33239 | /* 93143 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33240 | /* 93146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33241 | /* 93150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33242 | /* 93154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33243 | /* 93158 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33244 | /* 93162 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33245 | /* 93166 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33246 | /* 93170 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33247 | /* 93174 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33248 | /* 93174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16), |
| 33249 | /* 93177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33250 | /* 93179 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33251 | /* 93181 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33252 | /* 93183 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33253 | /* 93185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33254 | /* 93188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33255 | /* 93194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33256 | /* 93200 */ GIR_RootConstrainSelectedInstOperands, |
| 33257 | /* 93201 */ // GIR_Coverage, 4839, |
| 33258 | /* 93201 */ GIR_EraseRootFromParent_Done, |
| 33259 | /* 93202 */ // Label 1759: @93202 |
| 33260 | /* 93202 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(93289), // Rule ID 4841 // |
| 33261 | /* 93207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33262 | /* 93212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33263 | /* 93215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33264 | /* 93218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33265 | /* 93221 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33266 | /* 93224 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33267 | /* 93227 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33268 | /* 93230 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33269 | /* 93233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33270 | /* 93237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33271 | /* 93241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33272 | /* 93245 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33273 | /* 93249 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33274 | /* 93253 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33275 | /* 93257 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33276 | /* 93261 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33277 | /* 93261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32), |
| 33278 | /* 93264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33279 | /* 93266 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33280 | /* 93268 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33281 | /* 93270 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33282 | /* 93272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33283 | /* 93275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33284 | /* 93281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33285 | /* 93287 */ GIR_RootConstrainSelectedInstOperands, |
| 33286 | /* 93288 */ // GIR_Coverage, 4841, |
| 33287 | /* 93288 */ GIR_EraseRootFromParent_Done, |
| 33288 | /* 93289 */ // Label 1760: @93289 |
| 33289 | /* 93289 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(93376), // Rule ID 4843 // |
| 33290 | /* 93294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33291 | /* 93299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33292 | /* 93302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33293 | /* 93305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33294 | /* 93308 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33295 | /* 93311 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33296 | /* 93314 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33297 | /* 93317 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33298 | /* 93320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33299 | /* 93324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33300 | /* 93328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33301 | /* 93332 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33302 | /* 93336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33303 | /* 93340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33304 | /* 93344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33305 | /* 93348 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33306 | /* 93348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8), |
| 33307 | /* 93351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33308 | /* 93353 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33309 | /* 93355 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33310 | /* 93357 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33311 | /* 93359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33312 | /* 93362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33313 | /* 93368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33314 | /* 93374 */ GIR_RootConstrainSelectedInstOperands, |
| 33315 | /* 93375 */ // GIR_Coverage, 4843, |
| 33316 | /* 93375 */ GIR_EraseRootFromParent_Done, |
| 33317 | /* 93376 */ // Label 1761: @93376 |
| 33318 | /* 93376 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(93463), // Rule ID 4845 // |
| 33319 | /* 93381 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33320 | /* 93386 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33321 | /* 93389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33322 | /* 93392 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33323 | /* 93395 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33324 | /* 93398 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33325 | /* 93401 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33326 | /* 93404 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33327 | /* 93407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33328 | /* 93411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33329 | /* 93415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33330 | /* 93419 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33331 | /* 93423 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33332 | /* 93427 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33333 | /* 93431 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33334 | /* 93435 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33335 | /* 93435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16), |
| 33336 | /* 93438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33337 | /* 93440 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33338 | /* 93442 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33339 | /* 93444 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33340 | /* 93446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33341 | /* 93449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33342 | /* 93455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33343 | /* 93461 */ GIR_RootConstrainSelectedInstOperands, |
| 33344 | /* 93462 */ // GIR_Coverage, 4845, |
| 33345 | /* 93462 */ GIR_EraseRootFromParent_Done, |
| 33346 | /* 93463 */ // Label 1762: @93463 |
| 33347 | /* 93463 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(93550), // Rule ID 4847 // |
| 33348 | /* 93468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33349 | /* 93473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33350 | /* 93476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33351 | /* 93479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33352 | /* 93482 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33353 | /* 93485 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33354 | /* 93488 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33355 | /* 93491 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33356 | /* 93494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33357 | /* 93498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33358 | /* 93502 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33359 | /* 93506 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33360 | /* 93510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33361 | /* 93514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33362 | /* 93518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33363 | /* 93522 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33364 | /* 93522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32), |
| 33365 | /* 93525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33366 | /* 93527 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33367 | /* 93529 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33368 | /* 93531 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33369 | /* 93533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33370 | /* 93536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33371 | /* 93542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33372 | /* 93548 */ GIR_RootConstrainSelectedInstOperands, |
| 33373 | /* 93549 */ // GIR_Coverage, 4847, |
| 33374 | /* 93549 */ GIR_EraseRootFromParent_Done, |
| 33375 | /* 93550 */ // Label 1763: @93550 |
| 33376 | /* 93550 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(93637), // Rule ID 4849 // |
| 33377 | /* 93555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33378 | /* 93560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33379 | /* 93563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33380 | /* 93566 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33381 | /* 93569 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33382 | /* 93572 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33383 | /* 93575 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33384 | /* 93578 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33385 | /* 93581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33386 | /* 93585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33387 | /* 93589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33388 | /* 93593 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33389 | /* 93597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33390 | /* 93601 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33391 | /* 93605 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33392 | /* 93609 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33393 | /* 93609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8), |
| 33394 | /* 93612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33395 | /* 93614 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33396 | /* 93616 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33397 | /* 93618 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33398 | /* 93620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33399 | /* 93623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33400 | /* 93629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33401 | /* 93635 */ GIR_RootConstrainSelectedInstOperands, |
| 33402 | /* 93636 */ // GIR_Coverage, 4849, |
| 33403 | /* 93636 */ GIR_EraseRootFromParent_Done, |
| 33404 | /* 93637 */ // Label 1764: @93637 |
| 33405 | /* 93637 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(93724), // Rule ID 4851 // |
| 33406 | /* 93642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33407 | /* 93647 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33408 | /* 93650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33409 | /* 93653 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33410 | /* 93656 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33411 | /* 93659 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33412 | /* 93662 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33413 | /* 93665 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33414 | /* 93668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33415 | /* 93672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33416 | /* 93676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33417 | /* 93680 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33418 | /* 93684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33419 | /* 93688 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33420 | /* 93692 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33421 | /* 93696 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33422 | /* 93696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16), |
| 33423 | /* 93699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33424 | /* 93701 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33425 | /* 93703 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33426 | /* 93705 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33427 | /* 93707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33428 | /* 93710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33429 | /* 93716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33430 | /* 93722 */ GIR_RootConstrainSelectedInstOperands, |
| 33431 | /* 93723 */ // GIR_Coverage, 4851, |
| 33432 | /* 93723 */ GIR_EraseRootFromParent_Done, |
| 33433 | /* 93724 */ // Label 1765: @93724 |
| 33434 | /* 93724 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(93811), // Rule ID 4853 // |
| 33435 | /* 93729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33436 | /* 93734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33437 | /* 93737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33438 | /* 93740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33439 | /* 93743 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33440 | /* 93746 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33441 | /* 93749 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33442 | /* 93752 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33443 | /* 93755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33444 | /* 93759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33445 | /* 93763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33446 | /* 93767 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33447 | /* 93771 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33448 | /* 93775 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33449 | /* 93779 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33450 | /* 93783 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33451 | /* 93783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32), |
| 33452 | /* 93786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33453 | /* 93788 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33454 | /* 93790 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33455 | /* 93792 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33456 | /* 93794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33457 | /* 93797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33458 | /* 93803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33459 | /* 93809 */ GIR_RootConstrainSelectedInstOperands, |
| 33460 | /* 93810 */ // GIR_Coverage, 4853, |
| 33461 | /* 93810 */ GIR_EraseRootFromParent_Done, |
| 33462 | /* 93811 */ // Label 1766: @93811 |
| 33463 | /* 93811 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(93898), // Rule ID 4855 // |
| 33464 | /* 93816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33465 | /* 93821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33466 | /* 93824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33467 | /* 93827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33468 | /* 93830 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33469 | /* 93833 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33470 | /* 93836 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33471 | /* 93839 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33472 | /* 93842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33473 | /* 93846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33474 | /* 93850 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33475 | /* 93854 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33476 | /* 93858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33477 | /* 93862 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33478 | /* 93866 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33479 | /* 93870 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33480 | /* 93870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8), |
| 33481 | /* 93873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33482 | /* 93875 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33483 | /* 93877 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33484 | /* 93879 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33485 | /* 93881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33486 | /* 93884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33487 | /* 93890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33488 | /* 93896 */ GIR_RootConstrainSelectedInstOperands, |
| 33489 | /* 93897 */ // GIR_Coverage, 4855, |
| 33490 | /* 93897 */ GIR_EraseRootFromParent_Done, |
| 33491 | /* 93898 */ // Label 1767: @93898 |
| 33492 | /* 93898 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(93985), // Rule ID 4857 // |
| 33493 | /* 93903 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33494 | /* 93908 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33495 | /* 93911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33496 | /* 93914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33497 | /* 93917 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33498 | /* 93920 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33499 | /* 93923 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33500 | /* 93926 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33501 | /* 93929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33502 | /* 93933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33503 | /* 93937 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33504 | /* 93941 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33505 | /* 93945 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33506 | /* 93949 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33507 | /* 93953 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33508 | /* 93957 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33509 | /* 93957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16), |
| 33510 | /* 93960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33511 | /* 93962 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33512 | /* 93964 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33513 | /* 93966 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33514 | /* 93968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33515 | /* 93971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33516 | /* 93977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33517 | /* 93983 */ GIR_RootConstrainSelectedInstOperands, |
| 33518 | /* 93984 */ // GIR_Coverage, 4857, |
| 33519 | /* 93984 */ GIR_EraseRootFromParent_Done, |
| 33520 | /* 93985 */ // Label 1768: @93985 |
| 33521 | /* 93985 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(94072), // Rule ID 4859 // |
| 33522 | /* 93990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33523 | /* 93995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33524 | /* 93998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33525 | /* 94001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33526 | /* 94004 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33527 | /* 94007 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33528 | /* 94010 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33529 | /* 94013 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33530 | /* 94016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33531 | /* 94020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33532 | /* 94024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33533 | /* 94028 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33534 | /* 94032 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33535 | /* 94036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33536 | /* 94040 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33537 | /* 94044 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33538 | /* 94044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32), |
| 33539 | /* 94047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33540 | /* 94049 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33541 | /* 94051 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33542 | /* 94053 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33543 | /* 94055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33544 | /* 94058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33545 | /* 94064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33546 | /* 94070 */ GIR_RootConstrainSelectedInstOperands, |
| 33547 | /* 94071 */ // GIR_Coverage, 4859, |
| 33548 | /* 94071 */ GIR_EraseRootFromParent_Done, |
| 33549 | /* 94072 */ // Label 1769: @94072 |
| 33550 | /* 94072 */ GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(94159), // Rule ID 4861 // |
| 33551 | /* 94077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33552 | /* 94082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33553 | /* 94085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33554 | /* 94088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33555 | /* 94091 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33556 | /* 94094 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33557 | /* 94097 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33558 | /* 94100 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33559 | /* 94103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33560 | /* 94107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33561 | /* 94111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33562 | /* 94115 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33563 | /* 94119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33564 | /* 94123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33565 | /* 94127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33566 | /* 94131 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33567 | /* 94131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8), |
| 33568 | /* 94134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33569 | /* 94136 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33570 | /* 94138 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33571 | /* 94140 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33572 | /* 94142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33573 | /* 94145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33574 | /* 94151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33575 | /* 94157 */ GIR_RootConstrainSelectedInstOperands, |
| 33576 | /* 94158 */ // GIR_Coverage, 4861, |
| 33577 | /* 94158 */ GIR_EraseRootFromParent_Done, |
| 33578 | /* 94159 */ // Label 1770: @94159 |
| 33579 | /* 94159 */ GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(94246), // Rule ID 4863 // |
| 33580 | /* 94164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33581 | /* 94169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33582 | /* 94172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33583 | /* 94175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33584 | /* 94178 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33585 | /* 94181 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33586 | /* 94184 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33587 | /* 94187 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33588 | /* 94190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33589 | /* 94194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33590 | /* 94198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33591 | /* 94202 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33592 | /* 94206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33593 | /* 94210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33594 | /* 94214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33595 | /* 94218 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33596 | /* 94218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16), |
| 33597 | /* 94221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33598 | /* 94223 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33599 | /* 94225 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33600 | /* 94227 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33601 | /* 94229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33602 | /* 94232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33603 | /* 94238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33604 | /* 94244 */ GIR_RootConstrainSelectedInstOperands, |
| 33605 | /* 94245 */ // GIR_Coverage, 4863, |
| 33606 | /* 94245 */ GIR_EraseRootFromParent_Done, |
| 33607 | /* 94246 */ // Label 1771: @94246 |
| 33608 | /* 94246 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(94333), // Rule ID 4865 // |
| 33609 | /* 94251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33610 | /* 94256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33611 | /* 94259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33612 | /* 94262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33613 | /* 94265 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33614 | /* 94268 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33615 | /* 94271 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33616 | /* 94274 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33617 | /* 94277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33618 | /* 94281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33619 | /* 94285 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33620 | /* 94289 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33621 | /* 94293 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33622 | /* 94297 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33623 | /* 94301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33624 | /* 94305 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33625 | /* 94305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32), |
| 33626 | /* 94308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33627 | /* 94310 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33628 | /* 94312 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33629 | /* 94314 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33630 | /* 94316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33631 | /* 94319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33632 | /* 94325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33633 | /* 94331 */ GIR_RootConstrainSelectedInstOperands, |
| 33634 | /* 94332 */ // GIR_Coverage, 4865, |
| 33635 | /* 94332 */ GIR_EraseRootFromParent_Done, |
| 33636 | /* 94333 */ // Label 1772: @94333 |
| 33637 | /* 94333 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(94420), // Rule ID 4867 // |
| 33638 | /* 94338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33639 | /* 94343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33640 | /* 94346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33641 | /* 94349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33642 | /* 94352 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 33643 | /* 94355 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33644 | /* 94358 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33645 | /* 94361 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33646 | /* 94364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33647 | /* 94368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33648 | /* 94372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33649 | /* 94376 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33650 | /* 94380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33651 | /* 94384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33652 | /* 94388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33653 | /* 94392 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 33654 | /* 94392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8), |
| 33655 | /* 94395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33656 | /* 94397 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33657 | /* 94399 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33658 | /* 94401 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33659 | /* 94403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33660 | /* 94406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33661 | /* 94412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33662 | /* 94418 */ GIR_RootConstrainSelectedInstOperands, |
| 33663 | /* 94419 */ // GIR_Coverage, 4867, |
| 33664 | /* 94419 */ GIR_EraseRootFromParent_Done, |
| 33665 | /* 94420 */ // Label 1773: @94420 |
| 33666 | /* 94420 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(94507), // Rule ID 4869 // |
| 33667 | /* 94425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33668 | /* 94430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33669 | /* 94433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33670 | /* 94436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33671 | /* 94439 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 33672 | /* 94442 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33673 | /* 94445 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33674 | /* 94448 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33675 | /* 94451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33676 | /* 94455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33677 | /* 94459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33678 | /* 94463 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33679 | /* 94467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33680 | /* 94471 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33681 | /* 94475 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33682 | /* 94479 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 33683 | /* 94479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16), |
| 33684 | /* 94482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33685 | /* 94484 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33686 | /* 94486 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33687 | /* 94488 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33688 | /* 94490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33689 | /* 94493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33690 | /* 94499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33691 | /* 94505 */ GIR_RootConstrainSelectedInstOperands, |
| 33692 | /* 94506 */ // GIR_Coverage, 4869, |
| 33693 | /* 94506 */ GIR_EraseRootFromParent_Done, |
| 33694 | /* 94507 */ // Label 1774: @94507 |
| 33695 | /* 94507 */ GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(94594), // Rule ID 4871 // |
| 33696 | /* 94512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 33697 | /* 94517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33698 | /* 94520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33699 | /* 94523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33700 | /* 94526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33701 | /* 94529 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33702 | /* 94532 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33703 | /* 94535 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33704 | /* 94538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33705 | /* 94542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33706 | /* 94546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33707 | /* 94550 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33708 | /* 94554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33709 | /* 94558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33710 | /* 94562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33711 | /* 94566 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 33712 | /* 94566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32), |
| 33713 | /* 94569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33714 | /* 94571 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 33715 | /* 94573 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 33716 | /* 94575 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 33717 | /* 94577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33718 | /* 94580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33719 | /* 94586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33720 | /* 94592 */ GIR_RootConstrainSelectedInstOperands, |
| 33721 | /* 94593 */ // GIR_Coverage, 4871, |
| 33722 | /* 94593 */ GIR_EraseRootFromParent_Done, |
| 33723 | /* 94594 */ // Label 1775: @94594 |
| 33724 | /* 94594 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(94720), // Rule ID 3066 // |
| 33725 | /* 94599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 33726 | /* 94602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4), |
| 33727 | /* 94607 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 33728 | /* 94610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 33729 | /* 94613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 33730 | /* 94616 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 33731 | /* 94619 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 33732 | /* 94622 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 33733 | /* 94625 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8, |
| 33734 | /* 94628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 33735 | /* 94632 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4113:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 33736 | /* 94632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 33737 | /* 94635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 33738 | /* 94639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 33739 | /* 94644 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 33740 | /* 94648 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 33741 | /* 94651 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 33742 | /* 94655 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 33743 | /* 94658 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 33744 | /* 94662 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 33745 | /* 94665 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3 |
| 33746 | /* 94669 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 33747 | /* 94672 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 33748 | /* 94677 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 33749 | /* 94682 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 33750 | /* 94687 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 33751 | /* 94692 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 33752 | /* 94697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo), |
| 33753 | /* 94700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 33754 | /* 94702 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 33755 | /* 94704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 33756 | /* 94707 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm |
| 33757 | /* 94709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33758 | /* 94712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33759 | /* 94718 */ GIR_RootConstrainSelectedInstOperands, |
| 33760 | /* 94719 */ // GIR_Coverage, 3066, |
| 33761 | /* 94719 */ GIR_EraseRootFromParent_Done, |
| 33762 | /* 94720 */ // Label 1776: @94720 |
| 33763 | /* 94720 */ GIM_Reject, |
| 33764 | /* 94721 */ // Label 1721: @94721 |
| 33765 | /* 94721 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(99015), |
| 33766 | /* 94726 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10, |
| 33767 | /* 94729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn), |
| 33768 | /* 94734 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(94841), // Rule ID 4140 // |
| 33769 | /* 94739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33770 | /* 94742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33771 | /* 94745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33772 | /* 94748 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33773 | /* 94751 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33774 | /* 94754 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33775 | /* 94757 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33776 | /* 94760 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 33777 | /* 94763 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 33778 | /* 94766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33779 | /* 94770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33780 | /* 94774 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33781 | /* 94778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 33782 | /* 94782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33783 | /* 94786 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 33784 | /* 94790 */ // MIs[1] Operand 1 |
| 33785 | /* 94790 */ // No operand predicates |
| 33786 | /* 94790 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33787 | /* 94794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33788 | /* 94798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33789 | /* 94802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 33790 | /* 94806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 33791 | /* 94810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33792 | /* 94812 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 33793 | /* 94812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 33794 | /* 94815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33795 | /* 94817 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 33796 | /* 94819 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 33797 | /* 94821 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33798 | /* 94824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33799 | /* 94827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33800 | /* 94833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33801 | /* 94839 */ GIR_RootConstrainSelectedInstOperands, |
| 33802 | /* 94840 */ // GIR_Coverage, 4140, |
| 33803 | /* 94840 */ GIR_EraseRootFromParent_Done, |
| 33804 | /* 94841 */ // Label 1778: @94841 |
| 33805 | /* 94841 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(94948), // Rule ID 4142 // |
| 33806 | /* 94846 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33807 | /* 94849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33808 | /* 94852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33809 | /* 94855 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33810 | /* 94858 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33811 | /* 94861 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33812 | /* 94864 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33813 | /* 94867 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 33814 | /* 94870 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 33815 | /* 94873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33816 | /* 94877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33817 | /* 94881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33818 | /* 94885 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 33819 | /* 94889 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33820 | /* 94893 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 33821 | /* 94897 */ // MIs[1] Operand 1 |
| 33822 | /* 94897 */ // No operand predicates |
| 33823 | /* 94897 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33824 | /* 94901 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33825 | /* 94905 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33826 | /* 94909 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 33827 | /* 94913 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 33828 | /* 94917 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33829 | /* 94919 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 33830 | /* 94919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 33831 | /* 94922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33832 | /* 94924 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 33833 | /* 94926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 33834 | /* 94928 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33835 | /* 94931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33836 | /* 94934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33837 | /* 94940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33838 | /* 94946 */ GIR_RootConstrainSelectedInstOperands, |
| 33839 | /* 94947 */ // GIR_Coverage, 4142, |
| 33840 | /* 94947 */ GIR_EraseRootFromParent_Done, |
| 33841 | /* 94948 */ // Label 1779: @94948 |
| 33842 | /* 94948 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(95055), // Rule ID 4144 // |
| 33843 | /* 94953 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33844 | /* 94956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33845 | /* 94959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33846 | /* 94962 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33847 | /* 94965 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33848 | /* 94968 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33849 | /* 94971 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33850 | /* 94974 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 33851 | /* 94977 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 33852 | /* 94980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33853 | /* 94984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33854 | /* 94988 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33855 | /* 94992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 33856 | /* 94996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33857 | /* 95000 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 33858 | /* 95004 */ // MIs[1] Operand 1 |
| 33859 | /* 95004 */ // No operand predicates |
| 33860 | /* 95004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33861 | /* 95008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33862 | /* 95012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33863 | /* 95016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 33864 | /* 95020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 33865 | /* 95024 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33866 | /* 95026 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 33867 | /* 95026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 33868 | /* 95029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33869 | /* 95031 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 33870 | /* 95033 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 33871 | /* 95035 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33872 | /* 95038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33873 | /* 95041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33874 | /* 95047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33875 | /* 95053 */ GIR_RootConstrainSelectedInstOperands, |
| 33876 | /* 95054 */ // GIR_Coverage, 4144, |
| 33877 | /* 95054 */ GIR_EraseRootFromParent_Done, |
| 33878 | /* 95055 */ // Label 1780: @95055 |
| 33879 | /* 95055 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(95162), // Rule ID 4146 // |
| 33880 | /* 95060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33881 | /* 95063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33882 | /* 95066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33883 | /* 95069 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33884 | /* 95072 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33885 | /* 95075 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33886 | /* 95078 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33887 | /* 95081 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 33888 | /* 95084 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 33889 | /* 95087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33890 | /* 95091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33891 | /* 95095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33892 | /* 95099 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 33893 | /* 95103 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33894 | /* 95107 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 33895 | /* 95111 */ // MIs[1] Operand 1 |
| 33896 | /* 95111 */ // No operand predicates |
| 33897 | /* 95111 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33898 | /* 95115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33899 | /* 95119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 33900 | /* 95123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 33901 | /* 95127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 33902 | /* 95131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33903 | /* 95133 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 33904 | /* 95133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 33905 | /* 95136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33906 | /* 95138 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 33907 | /* 95140 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 33908 | /* 95142 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33909 | /* 95145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33910 | /* 95148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33911 | /* 95154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33912 | /* 95160 */ GIR_RootConstrainSelectedInstOperands, |
| 33913 | /* 95161 */ // GIR_Coverage, 4146, |
| 33914 | /* 95161 */ GIR_EraseRootFromParent_Done, |
| 33915 | /* 95162 */ // Label 1781: @95162 |
| 33916 | /* 95162 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(95269), // Rule ID 4148 // |
| 33917 | /* 95167 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33918 | /* 95170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33919 | /* 95173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33920 | /* 95176 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33921 | /* 95179 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33922 | /* 95182 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33923 | /* 95185 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33924 | /* 95188 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 33925 | /* 95191 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 33926 | /* 95194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33927 | /* 95198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33928 | /* 95202 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33929 | /* 95206 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 33930 | /* 95210 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33931 | /* 95214 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 33932 | /* 95218 */ // MIs[1] Operand 1 |
| 33933 | /* 95218 */ // No operand predicates |
| 33934 | /* 95218 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33935 | /* 95222 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33936 | /* 95226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33937 | /* 95230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 33938 | /* 95234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 33939 | /* 95238 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33940 | /* 95240 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 33941 | /* 95240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 33942 | /* 95243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33943 | /* 95245 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 33944 | /* 95247 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 33945 | /* 95249 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33946 | /* 95252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33947 | /* 95255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33948 | /* 95261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33949 | /* 95267 */ GIR_RootConstrainSelectedInstOperands, |
| 33950 | /* 95268 */ // GIR_Coverage, 4148, |
| 33951 | /* 95268 */ GIR_EraseRootFromParent_Done, |
| 33952 | /* 95269 */ // Label 1782: @95269 |
| 33953 | /* 95269 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(95376), // Rule ID 4150 // |
| 33954 | /* 95274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33955 | /* 95277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33956 | /* 95280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33957 | /* 95283 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33958 | /* 95286 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33959 | /* 95289 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33960 | /* 95292 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33961 | /* 95295 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 33962 | /* 95298 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 33963 | /* 95301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33964 | /* 95305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33965 | /* 95309 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33966 | /* 95313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 33967 | /* 95317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33968 | /* 95321 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 33969 | /* 95325 */ // MIs[1] Operand 1 |
| 33970 | /* 95325 */ // No operand predicates |
| 33971 | /* 95325 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33972 | /* 95329 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33973 | /* 95333 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 33974 | /* 95337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 33975 | /* 95341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 33976 | /* 95345 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33977 | /* 95347 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 33978 | /* 95347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 33979 | /* 95350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33980 | /* 95352 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 33981 | /* 95354 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 33982 | /* 95356 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33983 | /* 95359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33984 | /* 95362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33985 | /* 95368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33986 | /* 95374 */ GIR_RootConstrainSelectedInstOperands, |
| 33987 | /* 95375 */ // GIR_Coverage, 4150, |
| 33988 | /* 95375 */ GIR_EraseRootFromParent_Done, |
| 33989 | /* 95376 */ // Label 1783: @95376 |
| 33990 | /* 95376 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(95483), // Rule ID 4152 // |
| 33991 | /* 95381 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33992 | /* 95384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33993 | /* 95387 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33994 | /* 95390 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33995 | /* 95393 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33996 | /* 95396 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33997 | /* 95399 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 33998 | /* 95402 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 33999 | /* 95405 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34000 | /* 95408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34001 | /* 95412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34002 | /* 95416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34003 | /* 95420 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34004 | /* 95424 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34005 | /* 95428 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34006 | /* 95432 */ // MIs[1] Operand 1 |
| 34007 | /* 95432 */ // No operand predicates |
| 34008 | /* 95432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34009 | /* 95436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34010 | /* 95440 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34011 | /* 95444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34012 | /* 95448 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34013 | /* 95452 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34014 | /* 95454 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34015 | /* 95454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 34016 | /* 95457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34017 | /* 95459 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34018 | /* 95461 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34019 | /* 95463 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34020 | /* 95466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34021 | /* 95469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34022 | /* 95475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34023 | /* 95481 */ GIR_RootConstrainSelectedInstOperands, |
| 34024 | /* 95482 */ // GIR_Coverage, 4152, |
| 34025 | /* 95482 */ GIR_EraseRootFromParent_Done, |
| 34026 | /* 95483 */ // Label 1784: @95483 |
| 34027 | /* 95483 */ GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(95590), // Rule ID 4154 // |
| 34028 | /* 95488 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34029 | /* 95491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34030 | /* 95494 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34031 | /* 95497 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34032 | /* 95500 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34033 | /* 95503 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34034 | /* 95506 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34035 | /* 95509 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34036 | /* 95512 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34037 | /* 95515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34038 | /* 95519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34039 | /* 95523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34040 | /* 95527 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34041 | /* 95531 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34042 | /* 95535 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34043 | /* 95539 */ // MIs[1] Operand 1 |
| 34044 | /* 95539 */ // No operand predicates |
| 34045 | /* 95539 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34046 | /* 95543 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34047 | /* 95547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34048 | /* 95551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34049 | /* 95555 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34050 | /* 95559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34051 | /* 95561 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34052 | /* 95561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 34053 | /* 95564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34054 | /* 95566 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34055 | /* 95568 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34056 | /* 95570 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34057 | /* 95573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34058 | /* 95576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34059 | /* 95582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34060 | /* 95588 */ GIR_RootConstrainSelectedInstOperands, |
| 34061 | /* 95589 */ // GIR_Coverage, 4154, |
| 34062 | /* 95589 */ GIR_EraseRootFromParent_Done, |
| 34063 | /* 95590 */ // Label 1785: @95590 |
| 34064 | /* 95590 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(95697), // Rule ID 4156 // |
| 34065 | /* 95595 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34066 | /* 95598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34067 | /* 95601 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34068 | /* 95604 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34069 | /* 95607 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34070 | /* 95610 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34071 | /* 95613 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34072 | /* 95616 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34073 | /* 95619 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34074 | /* 95622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34075 | /* 95626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34076 | /* 95630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34077 | /* 95634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34078 | /* 95638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34079 | /* 95642 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34080 | /* 95646 */ // MIs[1] Operand 1 |
| 34081 | /* 95646 */ // No operand predicates |
| 34082 | /* 95646 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34083 | /* 95650 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34084 | /* 95654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34085 | /* 95658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34086 | /* 95662 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34087 | /* 95666 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34088 | /* 95668 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34089 | /* 95668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 34090 | /* 95671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34091 | /* 95673 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34092 | /* 95675 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34093 | /* 95677 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34094 | /* 95680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34095 | /* 95683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34096 | /* 95689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34097 | /* 95695 */ GIR_RootConstrainSelectedInstOperands, |
| 34098 | /* 95696 */ // GIR_Coverage, 4156, |
| 34099 | /* 95696 */ GIR_EraseRootFromParent_Done, |
| 34100 | /* 95697 */ // Label 1786: @95697 |
| 34101 | /* 95697 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(95804), // Rule ID 4158 // |
| 34102 | /* 95702 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34103 | /* 95705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34104 | /* 95708 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34105 | /* 95711 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34106 | /* 95714 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34107 | /* 95717 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34108 | /* 95720 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34109 | /* 95723 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34110 | /* 95726 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34111 | /* 95729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34112 | /* 95733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34113 | /* 95737 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34114 | /* 95741 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34115 | /* 95745 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34116 | /* 95749 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34117 | /* 95753 */ // MIs[1] Operand 1 |
| 34118 | /* 95753 */ // No operand predicates |
| 34119 | /* 95753 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34120 | /* 95757 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34121 | /* 95761 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34122 | /* 95765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34123 | /* 95769 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34124 | /* 95773 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34125 | /* 95775 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34126 | /* 95775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 34127 | /* 95778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34128 | /* 95780 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34129 | /* 95782 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34130 | /* 95784 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34131 | /* 95787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34132 | /* 95790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34133 | /* 95796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34134 | /* 95802 */ GIR_RootConstrainSelectedInstOperands, |
| 34135 | /* 95803 */ // GIR_Coverage, 4158, |
| 34136 | /* 95803 */ GIR_EraseRootFromParent_Done, |
| 34137 | /* 95804 */ // Label 1787: @95804 |
| 34138 | /* 95804 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(95911), // Rule ID 4160 // |
| 34139 | /* 95809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34140 | /* 95812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34141 | /* 95815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34142 | /* 95818 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34143 | /* 95821 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34144 | /* 95824 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34145 | /* 95827 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34146 | /* 95830 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34147 | /* 95833 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34148 | /* 95836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34149 | /* 95840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34150 | /* 95844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34151 | /* 95848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34152 | /* 95852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34153 | /* 95856 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34154 | /* 95860 */ // MIs[1] Operand 1 |
| 34155 | /* 95860 */ // No operand predicates |
| 34156 | /* 95860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34157 | /* 95864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34158 | /* 95868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34159 | /* 95872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34160 | /* 95876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34161 | /* 95880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34162 | /* 95882 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34163 | /* 95882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 34164 | /* 95885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34165 | /* 95887 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34166 | /* 95889 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34167 | /* 95891 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34168 | /* 95894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34169 | /* 95897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34170 | /* 95903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34171 | /* 95909 */ GIR_RootConstrainSelectedInstOperands, |
| 34172 | /* 95910 */ // GIR_Coverage, 4160, |
| 34173 | /* 95910 */ GIR_EraseRootFromParent_Done, |
| 34174 | /* 95911 */ // Label 1788: @95911 |
| 34175 | /* 95911 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(96018), // Rule ID 4162 // |
| 34176 | /* 95916 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34177 | /* 95919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34178 | /* 95922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34179 | /* 95925 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34180 | /* 95928 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34181 | /* 95931 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34182 | /* 95934 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34183 | /* 95937 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34184 | /* 95940 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34185 | /* 95943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34186 | /* 95947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34187 | /* 95951 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34188 | /* 95955 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34189 | /* 95959 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34190 | /* 95963 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34191 | /* 95967 */ // MIs[1] Operand 1 |
| 34192 | /* 95967 */ // No operand predicates |
| 34193 | /* 95967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34194 | /* 95971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34195 | /* 95975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34196 | /* 95979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34197 | /* 95983 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34198 | /* 95987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34199 | /* 95989 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34200 | /* 95989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 34201 | /* 95992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34202 | /* 95994 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34203 | /* 95996 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34204 | /* 95998 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34205 | /* 96001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34206 | /* 96004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34207 | /* 96010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34208 | /* 96016 */ GIR_RootConstrainSelectedInstOperands, |
| 34209 | /* 96017 */ // GIR_Coverage, 4162, |
| 34210 | /* 96017 */ GIR_EraseRootFromParent_Done, |
| 34211 | /* 96018 */ // Label 1789: @96018 |
| 34212 | /* 96018 */ GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(96125), // Rule ID 4164 // |
| 34213 | /* 96023 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34214 | /* 96026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34215 | /* 96029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34216 | /* 96032 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34217 | /* 96035 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34218 | /* 96038 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34219 | /* 96041 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34220 | /* 96044 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34221 | /* 96047 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34222 | /* 96050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34223 | /* 96054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34224 | /* 96058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34225 | /* 96062 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34226 | /* 96066 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34227 | /* 96070 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34228 | /* 96074 */ // MIs[1] Operand 1 |
| 34229 | /* 96074 */ // No operand predicates |
| 34230 | /* 96074 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34231 | /* 96078 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34232 | /* 96082 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34233 | /* 96086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34234 | /* 96090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34235 | /* 96094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34236 | /* 96096 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34237 | /* 96096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 34238 | /* 96099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34239 | /* 96101 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34240 | /* 96103 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34241 | /* 96105 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34242 | /* 96108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34243 | /* 96111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34244 | /* 96117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34245 | /* 96123 */ GIR_RootConstrainSelectedInstOperands, |
| 34246 | /* 96124 */ // GIR_Coverage, 4164, |
| 34247 | /* 96124 */ GIR_EraseRootFromParent_Done, |
| 34248 | /* 96125 */ // Label 1790: @96125 |
| 34249 | /* 96125 */ GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(96232), // Rule ID 4166 // |
| 34250 | /* 96130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34251 | /* 96133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34252 | /* 96136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34253 | /* 96139 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34254 | /* 96142 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34255 | /* 96145 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34256 | /* 96148 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34257 | /* 96151 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34258 | /* 96154 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34259 | /* 96157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34260 | /* 96161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34261 | /* 96165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34262 | /* 96169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34263 | /* 96173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34264 | /* 96177 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34265 | /* 96181 */ // MIs[1] Operand 1 |
| 34266 | /* 96181 */ // No operand predicates |
| 34267 | /* 96181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34268 | /* 96185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34269 | /* 96189 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34270 | /* 96193 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34271 | /* 96197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34272 | /* 96201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34273 | /* 96203 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34274 | /* 96203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 34275 | /* 96206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34276 | /* 96208 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34277 | /* 96210 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34278 | /* 96212 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34279 | /* 96215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34280 | /* 96218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34281 | /* 96224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34282 | /* 96230 */ GIR_RootConstrainSelectedInstOperands, |
| 34283 | /* 96231 */ // GIR_Coverage, 4166, |
| 34284 | /* 96231 */ GIR_EraseRootFromParent_Done, |
| 34285 | /* 96232 */ // Label 1791: @96232 |
| 34286 | /* 96232 */ GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(96339), // Rule ID 4168 // |
| 34287 | /* 96237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34288 | /* 96240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34289 | /* 96243 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34290 | /* 96246 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34291 | /* 96249 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34292 | /* 96252 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34293 | /* 96255 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34294 | /* 96258 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34295 | /* 96261 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34296 | /* 96264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34297 | /* 96268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34298 | /* 96272 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34299 | /* 96276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34300 | /* 96280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34301 | /* 96284 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34302 | /* 96288 */ // MIs[1] Operand 1 |
| 34303 | /* 96288 */ // No operand predicates |
| 34304 | /* 96288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34305 | /* 96292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34306 | /* 96296 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34307 | /* 96300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34308 | /* 96304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34309 | /* 96308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34310 | /* 96310 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34311 | /* 96310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 34312 | /* 96313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34313 | /* 96315 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34314 | /* 96317 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34315 | /* 96319 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34316 | /* 96322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34317 | /* 96325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34318 | /* 96331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34319 | /* 96337 */ GIR_RootConstrainSelectedInstOperands, |
| 34320 | /* 96338 */ // GIR_Coverage, 4168, |
| 34321 | /* 96338 */ GIR_EraseRootFromParent_Done, |
| 34322 | /* 96339 */ // Label 1792: @96339 |
| 34323 | /* 96339 */ GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(96446), // Rule ID 4170 // |
| 34324 | /* 96344 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34325 | /* 96347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34326 | /* 96350 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34327 | /* 96353 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34328 | /* 96356 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34329 | /* 96359 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34330 | /* 96362 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34331 | /* 96365 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34332 | /* 96368 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34333 | /* 96371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34334 | /* 96375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34335 | /* 96379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34336 | /* 96383 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34337 | /* 96387 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34338 | /* 96391 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34339 | /* 96395 */ // MIs[1] Operand 1 |
| 34340 | /* 96395 */ // No operand predicates |
| 34341 | /* 96395 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34342 | /* 96399 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34343 | /* 96403 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34344 | /* 96407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34345 | /* 96411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34346 | /* 96415 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34347 | /* 96417 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34348 | /* 96417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 34349 | /* 96420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34350 | /* 96422 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34351 | /* 96424 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34352 | /* 96426 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34353 | /* 96429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34354 | /* 96432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34355 | /* 96438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34356 | /* 96444 */ GIR_RootConstrainSelectedInstOperands, |
| 34357 | /* 96445 */ // GIR_Coverage, 4170, |
| 34358 | /* 96445 */ GIR_EraseRootFromParent_Done, |
| 34359 | /* 96446 */ // Label 1793: @96446 |
| 34360 | /* 96446 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(96553), // Rule ID 4172 // |
| 34361 | /* 96451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34362 | /* 96454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34363 | /* 96457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34364 | /* 96460 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34365 | /* 96463 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34366 | /* 96466 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34367 | /* 96469 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34368 | /* 96472 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34369 | /* 96475 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34370 | /* 96478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34371 | /* 96482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34372 | /* 96486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34373 | /* 96490 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34374 | /* 96494 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34375 | /* 96498 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34376 | /* 96502 */ // MIs[1] Operand 1 |
| 34377 | /* 96502 */ // No operand predicates |
| 34378 | /* 96502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34379 | /* 96506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34380 | /* 96510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34381 | /* 96514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34382 | /* 96518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34383 | /* 96522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34384 | /* 96524 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34385 | /* 96524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16), |
| 34386 | /* 96527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34387 | /* 96529 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34388 | /* 96531 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34389 | /* 96533 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34390 | /* 96536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34391 | /* 96539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34392 | /* 96545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34393 | /* 96551 */ GIR_RootConstrainSelectedInstOperands, |
| 34394 | /* 96552 */ // GIR_Coverage, 4172, |
| 34395 | /* 96552 */ GIR_EraseRootFromParent_Done, |
| 34396 | /* 96553 */ // Label 1794: @96553 |
| 34397 | /* 96553 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(96660), // Rule ID 4174 // |
| 34398 | /* 96558 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34399 | /* 96561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34400 | /* 96564 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34401 | /* 96567 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34402 | /* 96570 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34403 | /* 96573 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34404 | /* 96576 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34405 | /* 96579 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34406 | /* 96582 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34407 | /* 96585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34408 | /* 96589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34409 | /* 96593 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34410 | /* 96597 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34411 | /* 96601 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34412 | /* 96605 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34413 | /* 96609 */ // MIs[1] Operand 1 |
| 34414 | /* 96609 */ // No operand predicates |
| 34415 | /* 96609 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34416 | /* 96613 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34417 | /* 96617 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34418 | /* 96621 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34419 | /* 96625 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34420 | /* 96629 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34421 | /* 96631 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34422 | /* 96631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16), |
| 34423 | /* 96634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34424 | /* 96636 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34425 | /* 96638 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34426 | /* 96640 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34427 | /* 96643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34428 | /* 96646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34429 | /* 96652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34430 | /* 96658 */ GIR_RootConstrainSelectedInstOperands, |
| 34431 | /* 96659 */ // GIR_Coverage, 4174, |
| 34432 | /* 96659 */ GIR_EraseRootFromParent_Done, |
| 34433 | /* 96660 */ // Label 1795: @96660 |
| 34434 | /* 96660 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(96767), // Rule ID 4176 // |
| 34435 | /* 96665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34436 | /* 96668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34437 | /* 96671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34438 | /* 96674 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34439 | /* 96677 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34440 | /* 96680 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34441 | /* 96683 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34442 | /* 96686 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34443 | /* 96689 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34444 | /* 96692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34445 | /* 96696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34446 | /* 96700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34447 | /* 96704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34448 | /* 96708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34449 | /* 96712 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34450 | /* 96716 */ // MIs[1] Operand 1 |
| 34451 | /* 96716 */ // No operand predicates |
| 34452 | /* 96716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34453 | /* 96720 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34454 | /* 96724 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34455 | /* 96728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34456 | /* 96732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34457 | /* 96736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34458 | /* 96738 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34459 | /* 96738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32), |
| 34460 | /* 96741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34461 | /* 96743 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34462 | /* 96745 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34463 | /* 96747 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34464 | /* 96750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34465 | /* 96753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34466 | /* 96759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34467 | /* 96765 */ GIR_RootConstrainSelectedInstOperands, |
| 34468 | /* 96766 */ // GIR_Coverage, 4176, |
| 34469 | /* 96766 */ GIR_EraseRootFromParent_Done, |
| 34470 | /* 96767 */ // Label 1796: @96767 |
| 34471 | /* 96767 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(96874), // Rule ID 4178 // |
| 34472 | /* 96772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34473 | /* 96775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34474 | /* 96778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34475 | /* 96781 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34476 | /* 96784 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34477 | /* 96787 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34478 | /* 96790 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34479 | /* 96793 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34480 | /* 96796 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34481 | /* 96799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34482 | /* 96803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34483 | /* 96807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34484 | /* 96811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34485 | /* 96815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34486 | /* 96819 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34487 | /* 96823 */ // MIs[1] Operand 1 |
| 34488 | /* 96823 */ // No operand predicates |
| 34489 | /* 96823 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34490 | /* 96827 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34491 | /* 96831 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34492 | /* 96835 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34493 | /* 96839 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34494 | /* 96843 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34495 | /* 96845 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34496 | /* 96845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32), |
| 34497 | /* 96848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34498 | /* 96850 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34499 | /* 96852 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34500 | /* 96854 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34501 | /* 96857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34502 | /* 96860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34503 | /* 96866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34504 | /* 96872 */ GIR_RootConstrainSelectedInstOperands, |
| 34505 | /* 96873 */ // GIR_Coverage, 4178, |
| 34506 | /* 96873 */ GIR_EraseRootFromParent_Done, |
| 34507 | /* 96874 */ // Label 1797: @96874 |
| 34508 | /* 96874 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(96981), // Rule ID 4180 // |
| 34509 | /* 96879 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34510 | /* 96882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34511 | /* 96885 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34512 | /* 96888 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34513 | /* 96891 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34514 | /* 96894 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34515 | /* 96897 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34516 | /* 96900 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34517 | /* 96903 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34518 | /* 96906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34519 | /* 96910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34520 | /* 96914 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34521 | /* 96918 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34522 | /* 96922 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34523 | /* 96926 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34524 | /* 96930 */ // MIs[1] Operand 1 |
| 34525 | /* 96930 */ // No operand predicates |
| 34526 | /* 96930 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34527 | /* 96934 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34528 | /* 96938 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34529 | /* 96942 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34530 | /* 96946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34531 | /* 96950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34532 | /* 96952 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34533 | /* 96952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16), |
| 34534 | /* 96955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34535 | /* 96957 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34536 | /* 96959 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34537 | /* 96961 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34538 | /* 96964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34539 | /* 96967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34540 | /* 96973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34541 | /* 96979 */ GIR_RootConstrainSelectedInstOperands, |
| 34542 | /* 96980 */ // GIR_Coverage, 4180, |
| 34543 | /* 96980 */ GIR_EraseRootFromParent_Done, |
| 34544 | /* 96981 */ // Label 1798: @96981 |
| 34545 | /* 96981 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(97088), // Rule ID 4182 // |
| 34546 | /* 96986 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34547 | /* 96989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34548 | /* 96992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34549 | /* 96995 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34550 | /* 96998 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34551 | /* 97001 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34552 | /* 97004 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34553 | /* 97007 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34554 | /* 97010 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34555 | /* 97013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34556 | /* 97017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34557 | /* 97021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34558 | /* 97025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34559 | /* 97029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34560 | /* 97033 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34561 | /* 97037 */ // MIs[1] Operand 1 |
| 34562 | /* 97037 */ // No operand predicates |
| 34563 | /* 97037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34564 | /* 97041 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34565 | /* 97045 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34566 | /* 97049 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34567 | /* 97053 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34568 | /* 97057 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34569 | /* 97059 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34570 | /* 97059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16), |
| 34571 | /* 97062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34572 | /* 97064 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34573 | /* 97066 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34574 | /* 97068 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34575 | /* 97071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34576 | /* 97074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34577 | /* 97080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34578 | /* 97086 */ GIR_RootConstrainSelectedInstOperands, |
| 34579 | /* 97087 */ // GIR_Coverage, 4182, |
| 34580 | /* 97087 */ GIR_EraseRootFromParent_Done, |
| 34581 | /* 97088 */ // Label 1799: @97088 |
| 34582 | /* 97088 */ GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(97195), // Rule ID 4184 // |
| 34583 | /* 97093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34584 | /* 97096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34585 | /* 97099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34586 | /* 97102 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34587 | /* 97105 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34588 | /* 97108 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34589 | /* 97111 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34590 | /* 97114 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34591 | /* 97117 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34592 | /* 97120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34593 | /* 97124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34594 | /* 97128 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34595 | /* 97132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34596 | /* 97136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34597 | /* 97140 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34598 | /* 97144 */ // MIs[1] Operand 1 |
| 34599 | /* 97144 */ // No operand predicates |
| 34600 | /* 97144 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34601 | /* 97148 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34602 | /* 97152 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34603 | /* 97156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34604 | /* 97160 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34605 | /* 97164 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34606 | /* 97166 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34607 | /* 97166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32), |
| 34608 | /* 97169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34609 | /* 97171 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34610 | /* 97173 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34611 | /* 97175 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34612 | /* 97178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34613 | /* 97181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34614 | /* 97187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34615 | /* 97193 */ GIR_RootConstrainSelectedInstOperands, |
| 34616 | /* 97194 */ // GIR_Coverage, 4184, |
| 34617 | /* 97194 */ GIR_EraseRootFromParent_Done, |
| 34618 | /* 97195 */ // Label 1800: @97195 |
| 34619 | /* 97195 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(97302), // Rule ID 4186 // |
| 34620 | /* 97200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34621 | /* 97203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34622 | /* 97206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34623 | /* 97209 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34624 | /* 97212 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34625 | /* 97215 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34626 | /* 97218 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34627 | /* 97221 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34628 | /* 97224 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34629 | /* 97227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34630 | /* 97231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34631 | /* 97235 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34632 | /* 97239 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34633 | /* 97243 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34634 | /* 97247 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34635 | /* 97251 */ // MIs[1] Operand 1 |
| 34636 | /* 97251 */ // No operand predicates |
| 34637 | /* 97251 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34638 | /* 97255 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34639 | /* 97259 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34640 | /* 97263 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34641 | /* 97267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34642 | /* 97271 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34643 | /* 97273 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34644 | /* 97273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32), |
| 34645 | /* 97276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34646 | /* 97278 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34647 | /* 97280 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34648 | /* 97282 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34649 | /* 97285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34650 | /* 97288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34651 | /* 97294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34652 | /* 97300 */ GIR_RootConstrainSelectedInstOperands, |
| 34653 | /* 97301 */ // GIR_Coverage, 4186, |
| 34654 | /* 97301 */ GIR_EraseRootFromParent_Done, |
| 34655 | /* 97302 */ // Label 1801: @97302 |
| 34656 | /* 97302 */ GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(97409), // Rule ID 4188 // |
| 34657 | /* 97307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34658 | /* 97310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34659 | /* 97313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34660 | /* 97316 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34661 | /* 97319 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34662 | /* 97322 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34663 | /* 97325 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34664 | /* 97328 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34665 | /* 97331 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34666 | /* 97334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34667 | /* 97338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34668 | /* 97342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34669 | /* 97346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34670 | /* 97350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34671 | /* 97354 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34672 | /* 97358 */ // MIs[1] Operand 1 |
| 34673 | /* 97358 */ // No operand predicates |
| 34674 | /* 97358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34675 | /* 97362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34676 | /* 97366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34677 | /* 97370 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34678 | /* 97374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34679 | /* 97378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34680 | /* 97380 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34681 | /* 97380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16), |
| 34682 | /* 97383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34683 | /* 97385 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34684 | /* 97387 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34685 | /* 97389 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34686 | /* 97392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34687 | /* 97395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34688 | /* 97401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34689 | /* 97407 */ GIR_RootConstrainSelectedInstOperands, |
| 34690 | /* 97408 */ // GIR_Coverage, 4188, |
| 34691 | /* 97408 */ GIR_EraseRootFromParent_Done, |
| 34692 | /* 97409 */ // Label 1802: @97409 |
| 34693 | /* 97409 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(97516), // Rule ID 4190 // |
| 34694 | /* 97414 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34695 | /* 97417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34696 | /* 97420 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34697 | /* 97423 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34698 | /* 97426 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34699 | /* 97429 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34700 | /* 97432 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34701 | /* 97435 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34702 | /* 97438 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34703 | /* 97441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34704 | /* 97445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34705 | /* 97449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34706 | /* 97453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34707 | /* 97457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34708 | /* 97461 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34709 | /* 97465 */ // MIs[1] Operand 1 |
| 34710 | /* 97465 */ // No operand predicates |
| 34711 | /* 97465 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34712 | /* 97469 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34713 | /* 97473 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34714 | /* 97477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34715 | /* 97481 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34716 | /* 97485 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34717 | /* 97487 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34718 | /* 97487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16), |
| 34719 | /* 97490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34720 | /* 97492 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34721 | /* 97494 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34722 | /* 97496 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34723 | /* 97499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34724 | /* 97502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34725 | /* 97508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34726 | /* 97514 */ GIR_RootConstrainSelectedInstOperands, |
| 34727 | /* 97515 */ // GIR_Coverage, 4190, |
| 34728 | /* 97515 */ GIR_EraseRootFromParent_Done, |
| 34729 | /* 97516 */ // Label 1803: @97516 |
| 34730 | /* 97516 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(97623), // Rule ID 4192 // |
| 34731 | /* 97521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34732 | /* 97524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34733 | /* 97527 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34734 | /* 97530 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34735 | /* 97533 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34736 | /* 97536 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34737 | /* 97539 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34738 | /* 97542 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34739 | /* 97545 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34740 | /* 97548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34741 | /* 97552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34742 | /* 97556 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34743 | /* 97560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34744 | /* 97564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34745 | /* 97568 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34746 | /* 97572 */ // MIs[1] Operand 1 |
| 34747 | /* 97572 */ // No operand predicates |
| 34748 | /* 97572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34749 | /* 97576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34750 | /* 97580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34751 | /* 97584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34752 | /* 97588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34753 | /* 97592 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34754 | /* 97594 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34755 | /* 97594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32), |
| 34756 | /* 97597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34757 | /* 97599 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34758 | /* 97601 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34759 | /* 97603 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34760 | /* 97606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34761 | /* 97609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34762 | /* 97615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34763 | /* 97621 */ GIR_RootConstrainSelectedInstOperands, |
| 34764 | /* 97622 */ // GIR_Coverage, 4192, |
| 34765 | /* 97622 */ GIR_EraseRootFromParent_Done, |
| 34766 | /* 97623 */ // Label 1804: @97623 |
| 34767 | /* 97623 */ GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(97730), // Rule ID 4194 // |
| 34768 | /* 97628 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34769 | /* 97631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34770 | /* 97634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34771 | /* 97637 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34772 | /* 97640 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34773 | /* 97643 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34774 | /* 97646 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34775 | /* 97649 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34776 | /* 97652 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34777 | /* 97655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34778 | /* 97659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34779 | /* 97663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34780 | /* 97667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34781 | /* 97671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34782 | /* 97675 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34783 | /* 97679 */ // MIs[1] Operand 1 |
| 34784 | /* 97679 */ // No operand predicates |
| 34785 | /* 97679 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34786 | /* 97683 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34787 | /* 97687 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 34788 | /* 97691 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34789 | /* 97695 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34790 | /* 97699 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34791 | /* 97701 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34792 | /* 97701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32), |
| 34793 | /* 97704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34794 | /* 97706 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34795 | /* 97708 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34796 | /* 97710 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34797 | /* 97713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34798 | /* 97716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34799 | /* 97722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34800 | /* 97728 */ GIR_RootConstrainSelectedInstOperands, |
| 34801 | /* 97729 */ // GIR_Coverage, 4194, |
| 34802 | /* 97729 */ GIR_EraseRootFromParent_Done, |
| 34803 | /* 97730 */ // Label 1805: @97730 |
| 34804 | /* 97730 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(97837), // Rule ID 4196 // |
| 34805 | /* 97735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34806 | /* 97738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34807 | /* 97741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34808 | /* 97744 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34809 | /* 97747 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34810 | /* 97750 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34811 | /* 97753 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34812 | /* 97756 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34813 | /* 97759 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34814 | /* 97762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34815 | /* 97766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34816 | /* 97770 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34817 | /* 97774 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34818 | /* 97778 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34819 | /* 97782 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34820 | /* 97786 */ // MIs[1] Operand 1 |
| 34821 | /* 97786 */ // No operand predicates |
| 34822 | /* 97786 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34823 | /* 97790 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34824 | /* 97794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34825 | /* 97798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34826 | /* 97802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34827 | /* 97806 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34828 | /* 97808 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34829 | /* 97808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16), |
| 34830 | /* 97811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34831 | /* 97813 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34832 | /* 97815 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34833 | /* 97817 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34834 | /* 97820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34835 | /* 97823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34836 | /* 97829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34837 | /* 97835 */ GIR_RootConstrainSelectedInstOperands, |
| 34838 | /* 97836 */ // GIR_Coverage, 4196, |
| 34839 | /* 97836 */ GIR_EraseRootFromParent_Done, |
| 34840 | /* 97837 */ // Label 1806: @97837 |
| 34841 | /* 97837 */ GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(97944), // Rule ID 4198 // |
| 34842 | /* 97842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34843 | /* 97845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34844 | /* 97848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34845 | /* 97851 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34846 | /* 97854 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34847 | /* 97857 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34848 | /* 97860 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34849 | /* 97863 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34850 | /* 97866 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34851 | /* 97869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34852 | /* 97873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34853 | /* 97877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34854 | /* 97881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34855 | /* 97885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34856 | /* 97889 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34857 | /* 97893 */ // MIs[1] Operand 1 |
| 34858 | /* 97893 */ // No operand predicates |
| 34859 | /* 97893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34860 | /* 97897 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34861 | /* 97901 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34862 | /* 97905 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34863 | /* 97909 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34864 | /* 97913 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34865 | /* 97915 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34866 | /* 97915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16), |
| 34867 | /* 97918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34868 | /* 97920 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34869 | /* 97922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34870 | /* 97924 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34871 | /* 97927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34872 | /* 97930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34873 | /* 97936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34874 | /* 97942 */ GIR_RootConstrainSelectedInstOperands, |
| 34875 | /* 97943 */ // GIR_Coverage, 4198, |
| 34876 | /* 97943 */ GIR_EraseRootFromParent_Done, |
| 34877 | /* 97944 */ // Label 1807: @97944 |
| 34878 | /* 97944 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(98051), // Rule ID 4200 // |
| 34879 | /* 97949 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34880 | /* 97952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34881 | /* 97955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34882 | /* 97958 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34883 | /* 97961 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34884 | /* 97964 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34885 | /* 97967 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34886 | /* 97970 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34887 | /* 97973 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34888 | /* 97976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34889 | /* 97980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34890 | /* 97984 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34891 | /* 97988 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34892 | /* 97992 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34893 | /* 97996 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34894 | /* 98000 */ // MIs[1] Operand 1 |
| 34895 | /* 98000 */ // No operand predicates |
| 34896 | /* 98000 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34897 | /* 98004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34898 | /* 98008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34899 | /* 98012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34900 | /* 98016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34901 | /* 98020 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34902 | /* 98022 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34903 | /* 98022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32), |
| 34904 | /* 98025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34905 | /* 98027 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34906 | /* 98029 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34907 | /* 98031 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34908 | /* 98034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34909 | /* 98037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34910 | /* 98043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34911 | /* 98049 */ GIR_RootConstrainSelectedInstOperands, |
| 34912 | /* 98050 */ // GIR_Coverage, 4200, |
| 34913 | /* 98050 */ GIR_EraseRootFromParent_Done, |
| 34914 | /* 98051 */ // Label 1808: @98051 |
| 34915 | /* 98051 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(98158), // Rule ID 4202 // |
| 34916 | /* 98056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34917 | /* 98059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34918 | /* 98062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34919 | /* 98065 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34920 | /* 98068 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34921 | /* 98071 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34922 | /* 98074 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34923 | /* 98077 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34924 | /* 98080 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34925 | /* 98083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34926 | /* 98087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34927 | /* 98091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34928 | /* 98095 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34929 | /* 98099 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34930 | /* 98103 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 34931 | /* 98107 */ // MIs[1] Operand 1 |
| 34932 | /* 98107 */ // No operand predicates |
| 34933 | /* 98107 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34934 | /* 98111 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34935 | /* 98115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34936 | /* 98119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 34937 | /* 98123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 34938 | /* 98127 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34939 | /* 98129 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34940 | /* 98129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32), |
| 34941 | /* 98132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34942 | /* 98134 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34943 | /* 98136 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34944 | /* 98138 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34945 | /* 98141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34946 | /* 98144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34947 | /* 98150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34948 | /* 98156 */ GIR_RootConstrainSelectedInstOperands, |
| 34949 | /* 98157 */ // GIR_Coverage, 4202, |
| 34950 | /* 98157 */ GIR_EraseRootFromParent_Done, |
| 34951 | /* 98158 */ // Label 1809: @98158 |
| 34952 | /* 98158 */ GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(98265), // Rule ID 4204 // |
| 34953 | /* 98163 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34954 | /* 98166 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34955 | /* 98169 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34956 | /* 98172 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34957 | /* 98175 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34958 | /* 98178 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34959 | /* 98181 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34960 | /* 98184 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34961 | /* 98187 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34962 | /* 98190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34963 | /* 98194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34964 | /* 98198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34965 | /* 98202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 34966 | /* 98206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 34967 | /* 98210 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 34968 | /* 98214 */ // MIs[1] Operand 1 |
| 34969 | /* 98214 */ // No operand predicates |
| 34970 | /* 98214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34971 | /* 98218 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34972 | /* 98222 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 34973 | /* 98226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 34974 | /* 98230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 34975 | /* 98234 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 34976 | /* 98236 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 34977 | /* 98236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh), |
| 34978 | /* 98239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34979 | /* 98241 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 34980 | /* 98243 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 34981 | /* 98245 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 34982 | /* 98248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34983 | /* 98251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34984 | /* 98257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34985 | /* 98263 */ GIR_RootConstrainSelectedInstOperands, |
| 34986 | /* 98264 */ // GIR_Coverage, 4204, |
| 34987 | /* 98264 */ GIR_EraseRootFromParent_Done, |
| 34988 | /* 98265 */ // Label 1810: @98265 |
| 34989 | /* 98265 */ GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(98372), // Rule ID 4206 // |
| 34990 | /* 98270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34991 | /* 98273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34992 | /* 98276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34993 | /* 98279 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34994 | /* 98282 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34995 | /* 98285 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34996 | /* 98288 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 34997 | /* 98291 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 34998 | /* 98294 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 34999 | /* 98297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35000 | /* 98301 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35001 | /* 98305 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35002 | /* 98309 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 35003 | /* 98313 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35004 | /* 98317 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 35005 | /* 98321 */ // MIs[1] Operand 1 |
| 35006 | /* 98321 */ // No operand predicates |
| 35007 | /* 98321 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 35008 | /* 98325 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35009 | /* 98329 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 35010 | /* 98333 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 35011 | /* 98337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 35012 | /* 98341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35013 | /* 98343 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 35014 | /* 98343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th), |
| 35015 | /* 98346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35016 | /* 98348 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 35017 | /* 98350 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 35018 | /* 98352 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35019 | /* 98355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35020 | /* 98358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35021 | /* 98364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35022 | /* 98370 */ GIR_RootConstrainSelectedInstOperands, |
| 35023 | /* 98371 */ // GIR_Coverage, 4206, |
| 35024 | /* 98371 */ GIR_EraseRootFromParent_Done, |
| 35025 | /* 98372 */ // Label 1811: @98372 |
| 35026 | /* 98372 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(98479), // Rule ID 4208 // |
| 35027 | /* 98377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35028 | /* 98380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35029 | /* 98383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35030 | /* 98386 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35031 | /* 98389 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35032 | /* 98392 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35033 | /* 98395 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 35034 | /* 98398 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 35035 | /* 98401 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 35036 | /* 98404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35037 | /* 98408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35038 | /* 98412 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35039 | /* 98416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 35040 | /* 98420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35041 | /* 98424 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 35042 | /* 98428 */ // MIs[1] Operand 1 |
| 35043 | /* 98428 */ // No operand predicates |
| 35044 | /* 98428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 35045 | /* 98432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35046 | /* 98436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 35047 | /* 98440 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 35048 | /* 98444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 35049 | /* 98448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35050 | /* 98450 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 35051 | /* 98450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh), |
| 35052 | /* 98453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35053 | /* 98455 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 35054 | /* 98457 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 35055 | /* 98459 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35056 | /* 98462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35057 | /* 98465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35058 | /* 98471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35059 | /* 98477 */ GIR_RootConstrainSelectedInstOperands, |
| 35060 | /* 98478 */ // GIR_Coverage, 4208, |
| 35061 | /* 98478 */ GIR_EraseRootFromParent_Done, |
| 35062 | /* 98479 */ // Label 1812: @98479 |
| 35063 | /* 98479 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(98586), // Rule ID 4210 // |
| 35064 | /* 98484 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35065 | /* 98487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35066 | /* 98490 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35067 | /* 98493 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35068 | /* 98496 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35069 | /* 98499 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35070 | /* 98502 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 35071 | /* 98505 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 35072 | /* 98508 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 35073 | /* 98511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35074 | /* 98515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35075 | /* 98519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35076 | /* 98523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 35077 | /* 98527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35078 | /* 98531 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 35079 | /* 98535 */ // MIs[1] Operand 1 |
| 35080 | /* 98535 */ // No operand predicates |
| 35081 | /* 98535 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 35082 | /* 98539 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35083 | /* 98543 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 35084 | /* 98547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 35085 | /* 98551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 35086 | /* 98555 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35087 | /* 98557 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 35088 | /* 98557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th), |
| 35089 | /* 98560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35090 | /* 98562 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 35091 | /* 98564 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 35092 | /* 98566 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35093 | /* 98569 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35094 | /* 98572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35095 | /* 98578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35096 | /* 98584 */ GIR_RootConstrainSelectedInstOperands, |
| 35097 | /* 98585 */ // GIR_Coverage, 4210, |
| 35098 | /* 98585 */ GIR_EraseRootFromParent_Done, |
| 35099 | /* 98586 */ // Label 1813: @98586 |
| 35100 | /* 98586 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(98693), // Rule ID 4212 // |
| 35101 | /* 98591 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 35102 | /* 98594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 35103 | /* 98597 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 35104 | /* 98600 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35105 | /* 98603 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35106 | /* 98606 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35107 | /* 98609 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 35108 | /* 98612 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 35109 | /* 98615 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 35110 | /* 98618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35111 | /* 98622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35112 | /* 98626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35113 | /* 98630 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 35114 | /* 98634 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35115 | /* 98638 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 35116 | /* 98642 */ // MIs[1] Operand 1 |
| 35117 | /* 98642 */ // No operand predicates |
| 35118 | /* 98642 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 35119 | /* 98646 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35120 | /* 98650 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 35121 | /* 98654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 35122 | /* 98658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 35123 | /* 98662 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35124 | /* 98664 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 35125 | /* 98664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh), |
| 35126 | /* 98667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35127 | /* 98669 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 35128 | /* 98671 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 35129 | /* 98673 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35130 | /* 98676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35131 | /* 98679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35132 | /* 98685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35133 | /* 98691 */ GIR_RootConstrainSelectedInstOperands, |
| 35134 | /* 98692 */ // GIR_Coverage, 4212, |
| 35135 | /* 98692 */ GIR_EraseRootFromParent_Done, |
| 35136 | /* 98693 */ // Label 1814: @98693 |
| 35137 | /* 98693 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(98800), // Rule ID 4214 // |
| 35138 | /* 98698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 35139 | /* 98701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 35140 | /* 98704 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 35141 | /* 98707 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35142 | /* 98710 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35143 | /* 98713 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35144 | /* 98716 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 35145 | /* 98719 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 35146 | /* 98722 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 35147 | /* 98725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35148 | /* 98729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35149 | /* 98733 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35150 | /* 98737 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 35151 | /* 98741 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35152 | /* 98745 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 35153 | /* 98749 */ // MIs[1] Operand 1 |
| 35154 | /* 98749 */ // No operand predicates |
| 35155 | /* 98749 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 35156 | /* 98753 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35157 | /* 98757 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 35158 | /* 98761 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 35159 | /* 98765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 35160 | /* 98769 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35161 | /* 98771 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 35162 | /* 98771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th), |
| 35163 | /* 98774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35164 | /* 98776 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 35165 | /* 98778 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 35166 | /* 98780 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35167 | /* 98783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35168 | /* 98786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35169 | /* 98792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35170 | /* 98798 */ GIR_RootConstrainSelectedInstOperands, |
| 35171 | /* 98799 */ // GIR_Coverage, 4214, |
| 35172 | /* 98799 */ GIR_EraseRootFromParent_Done, |
| 35173 | /* 98800 */ // Label 1815: @98800 |
| 35174 | /* 98800 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(98907), // Rule ID 4216 // |
| 35175 | /* 98805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35176 | /* 98808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35177 | /* 98811 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35178 | /* 98814 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35179 | /* 98817 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35180 | /* 98820 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35181 | /* 98823 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 35182 | /* 98826 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 35183 | /* 98829 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 35184 | /* 98832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35185 | /* 98836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35186 | /* 98840 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35187 | /* 98844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 35188 | /* 98848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35189 | /* 98852 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 35190 | /* 98856 */ // MIs[1] Operand 1 |
| 35191 | /* 98856 */ // No operand predicates |
| 35192 | /* 98856 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 35193 | /* 98860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35194 | /* 98864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 35195 | /* 98868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 35196 | /* 98872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 35197 | /* 98876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35198 | /* 98878 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 35199 | /* 98878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh), |
| 35200 | /* 98881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35201 | /* 98883 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 35202 | /* 98885 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 35203 | /* 98887 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35204 | /* 98890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35205 | /* 98893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35206 | /* 98899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35207 | /* 98905 */ GIR_RootConstrainSelectedInstOperands, |
| 35208 | /* 98906 */ // GIR_Coverage, 4216, |
| 35209 | /* 98906 */ GIR_EraseRootFromParent_Done, |
| 35210 | /* 98907 */ // Label 1816: @98907 |
| 35211 | /* 98907 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(99014), // Rule ID 4218 // |
| 35212 | /* 98912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35213 | /* 98915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35214 | /* 98918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35215 | /* 98921 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35216 | /* 98924 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35217 | /* 98927 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35218 | /* 98930 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 35219 | /* 98933 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 35220 | /* 98936 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 35221 | /* 98939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35222 | /* 98943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35223 | /* 98947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35224 | /* 98951 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 35225 | /* 98955 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35226 | /* 98959 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 35227 | /* 98963 */ // MIs[1] Operand 1 |
| 35228 | /* 98963 */ // No operand predicates |
| 35229 | /* 98963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 35230 | /* 98967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35231 | /* 98971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 35232 | /* 98975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 35233 | /* 98979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 35234 | /* 98983 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35235 | /* 98985 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 35236 | /* 98985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th), |
| 35237 | /* 98988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35238 | /* 98990 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 35239 | /* 98992 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 35240 | /* 98994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35241 | /* 98997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35242 | /* 99000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35243 | /* 99006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35244 | /* 99012 */ GIR_RootConstrainSelectedInstOperands, |
| 35245 | /* 99013 */ // GIR_Coverage, 4218, |
| 35246 | /* 99013 */ GIR_EraseRootFromParent_Done, |
| 35247 | /* 99014 */ // Label 1817: @99014 |
| 35248 | /* 99014 */ GIM_Reject, |
| 35249 | /* 99015 */ // Label 1777: @99015 |
| 35250 | /* 99015 */ GIM_Reject, |
| 35251 | /* 99016 */ // Label 22: @99016 |
| 35252 | /* 99016 */ GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(99073), |
| 35253 | /* 99021 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 35254 | /* 99024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex), |
| 35255 | /* 99029 */ GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(99046), // Rule ID 244 // |
| 35256 | /* 99034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6K_IsARM), |
| 35257 | /* 99037 */ // (intrinsic_void 3728:{ *:[iPTR] }) => (CLREX) |
| 35258 | /* 99037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX), |
| 35259 | /* 99040 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35260 | /* 99044 */ GIR_RootConstrainSelectedInstOperands, |
| 35261 | /* 99045 */ // GIR_Coverage, 244, |
| 35262 | /* 99045 */ GIR_EraseRootFromParent_Done, |
| 35263 | /* 99046 */ // Label 1819: @99046 |
| 35264 | /* 99046 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(99072), // Rule ID 573 // |
| 35265 | /* 99051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb), |
| 35266 | /* 99054 */ // (intrinsic_void 3728:{ *:[iPTR] }) => (t2CLREX) |
| 35267 | /* 99054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX), |
| 35268 | /* 99057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35269 | /* 99060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35270 | /* 99066 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35271 | /* 99070 */ GIR_RootConstrainSelectedInstOperands, |
| 35272 | /* 99071 */ // GIR_Coverage, 573, |
| 35273 | /* 99071 */ GIR_EraseRootFromParent_Done, |
| 35274 | /* 99072 */ // Label 1820: @99072 |
| 35275 | /* 99072 */ GIM_Reject, |
| 35276 | /* 99073 */ // Label 1818: @99073 |
| 35277 | /* 99073 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(99875), |
| 35278 | /* 99078 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 35279 | /* 99081 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(99117), // Rule ID 343 // |
| 35280 | /* 99086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsWindows), |
| 35281 | /* 99089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 35282 | /* 99094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35283 | /* 99097 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249), |
| 35284 | /* 99108 */ // (intrinsic_void 4182:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0) |
| 35285 | /* 99108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0), |
| 35286 | /* 99111 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35287 | /* 99115 */ GIR_RootConstrainSelectedInstOperands, |
| 35288 | /* 99116 */ // GIR_Coverage, 343, |
| 35289 | /* 99116 */ GIR_EraseRootFromParent_Done, |
| 35290 | /* 99117 */ // Label 1822: @99117 |
| 35291 | /* 99117 */ GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(99169), // Rule ID 2 // |
| 35292 | /* 99122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 35293 | /* 99125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 35294 | /* 99130 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35295 | /* 99133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35296 | /* 99137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35297 | /* 99141 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 35298 | /* 99145 */ // MIs[1] Operand 1 |
| 35299 | /* 99145 */ // No operand predicates |
| 35300 | /* 99145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35301 | /* 99147 */ // (intrinsic_void 3746:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm) |
| 35302 | /* 99147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT), |
| 35303 | /* 99150 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35304 | /* 99153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35305 | /* 99156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35306 | /* 99162 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35307 | /* 99167 */ GIR_RootConstrainSelectedInstOperands, |
| 35308 | /* 99168 */ // GIR_Coverage, 2, |
| 35309 | /* 99168 */ GIR_EraseRootFromParent_Done, |
| 35310 | /* 99169 */ // Label 1823: @99169 |
| 35311 | /* 99169 */ GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(99221), // Rule ID 10 // |
| 35312 | /* 99174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7_IsARM), |
| 35313 | /* 99177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 35314 | /* 99182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35315 | /* 99185 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35316 | /* 99189 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35317 | /* 99193 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35318 | /* 99197 */ // MIs[1] Operand 1 |
| 35319 | /* 99197 */ // No operand predicates |
| 35320 | /* 99197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35321 | /* 99199 */ // (intrinsic_void 3741:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt) |
| 35322 | /* 99199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG), |
| 35323 | /* 99202 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35324 | /* 99205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35325 | /* 99208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35326 | /* 99214 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35327 | /* 99219 */ GIR_RootConstrainSelectedInstOperands, |
| 35328 | /* 99220 */ // GIR_Coverage, 10, |
| 35329 | /* 99220 */ GIR_EraseRootFromParent_Done, |
| 35330 | /* 99221 */ // Label 1824: @99221 |
| 35331 | /* 99221 */ GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(99264), // Rule ID 11 // |
| 35332 | /* 99226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35333 | /* 99229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 35334 | /* 99234 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35335 | /* 99237 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35336 | /* 99241 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35337 | /* 99245 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35338 | /* 99249 */ // MIs[1] Operand 1 |
| 35339 | /* 99249 */ // No operand predicates |
| 35340 | /* 99249 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35341 | /* 99251 */ // (intrinsic_void 4182:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16) |
| 35342 | /* 99251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 35343 | /* 99254 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 35344 | /* 99257 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35345 | /* 99262 */ GIR_RootConstrainSelectedInstOperands, |
| 35346 | /* 99263 */ // GIR_Coverage, 11, |
| 35347 | /* 99263 */ GIR_EraseRootFromParent_Done, |
| 35348 | /* 99264 */ // Label 1825: @99264 |
| 35349 | /* 99264 */ GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(99307), // Rule ID 227 // |
| 35350 | /* 99269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 35351 | /* 99272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 35352 | /* 99277 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35353 | /* 99280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35354 | /* 99284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35355 | /* 99288 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35356 | /* 99292 */ // MIs[1] Operand 1 |
| 35357 | /* 99292 */ // No operand predicates |
| 35358 | /* 99292 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35359 | /* 99294 */ // (intrinsic_void 3742:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt) |
| 35360 | /* 99294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB), |
| 35361 | /* 99297 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35362 | /* 99300 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35363 | /* 99305 */ GIR_RootConstrainSelectedInstOperands, |
| 35364 | /* 99306 */ // GIR_Coverage, 227, |
| 35365 | /* 99306 */ GIR_EraseRootFromParent_Done, |
| 35366 | /* 99307 */ // Label 1826: @99307 |
| 35367 | /* 99307 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(99350), // Rule ID 228 // |
| 35368 | /* 99312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 35369 | /* 99315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 35370 | /* 99320 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35371 | /* 99323 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35372 | /* 99327 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35373 | /* 99331 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35374 | /* 99335 */ // MIs[1] Operand 1 |
| 35375 | /* 99335 */ // No operand predicates |
| 35376 | /* 99335 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35377 | /* 99337 */ // (intrinsic_void 3743:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt) |
| 35378 | /* 99337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB), |
| 35379 | /* 99340 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35380 | /* 99343 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35381 | /* 99348 */ GIR_RootConstrainSelectedInstOperands, |
| 35382 | /* 99349 */ // GIR_Coverage, 228, |
| 35383 | /* 99349 */ GIR_EraseRootFromParent_Done, |
| 35384 | /* 99350 */ // Label 1827: @99350 |
| 35385 | /* 99350 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(99393), // Rule ID 229 // |
| 35386 | /* 99355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 35387 | /* 99358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 35388 | /* 99363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35389 | /* 99366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35390 | /* 99370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35391 | /* 99374 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35392 | /* 99378 */ // MIs[1] Operand 1 |
| 35393 | /* 99378 */ // No operand predicates |
| 35394 | /* 99378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35395 | /* 99380 */ // (intrinsic_void 3747:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt) |
| 35396 | /* 99380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB), |
| 35397 | /* 99383 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35398 | /* 99386 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35399 | /* 99391 */ GIR_RootConstrainSelectedInstOperands, |
| 35400 | /* 99392 */ // GIR_Coverage, 229, |
| 35401 | /* 99392 */ GIR_EraseRootFromParent_Done, |
| 35402 | /* 99393 */ // Label 1828: @99393 |
| 35403 | /* 99393 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(99445), // Rule ID 275 // |
| 35404 | /* 99398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6M_IsThumb), |
| 35405 | /* 99401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 35406 | /* 99406 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35407 | /* 99409 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35408 | /* 99413 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35409 | /* 99417 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35410 | /* 99421 */ // MIs[1] Operand 1 |
| 35411 | /* 99421 */ // No operand predicates |
| 35412 | /* 99421 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35413 | /* 99423 */ // (intrinsic_void 3746:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm) |
| 35414 | /* 99423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT), |
| 35415 | /* 99426 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35416 | /* 99429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35417 | /* 99432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35418 | /* 99438 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35419 | /* 99443 */ GIR_RootConstrainSelectedInstOperands, |
| 35420 | /* 99444 */ // GIR_Coverage, 275, |
| 35421 | /* 99444 */ GIR_EraseRootFromParent_Done, |
| 35422 | /* 99445 */ // Label 1829: @99445 |
| 35423 | /* 99445 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(99488), // Rule ID 342 // |
| 35424 | /* 99450 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 35425 | /* 99453 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 35426 | /* 99458 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35427 | /* 99461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35428 | /* 99465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35429 | /* 99469 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255), |
| 35430 | /* 99473 */ // MIs[1] Operand 1 |
| 35431 | /* 99473 */ // No operand predicates |
| 35432 | /* 99473 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35433 | /* 99475 */ // (intrinsic_void 4182:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8) |
| 35434 | /* 99475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 35435 | /* 99478 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 35436 | /* 99481 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35437 | /* 99486 */ GIR_RootConstrainSelectedInstOperands, |
| 35438 | /* 99487 */ // GIR_Coverage, 342, |
| 35439 | /* 99487 */ GIR_EraseRootFromParent_Done, |
| 35440 | /* 99488 */ // Label 1830: @99488 |
| 35441 | /* 99488 */ GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(99531), // Rule ID 493 // |
| 35442 | /* 99493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35443 | /* 99496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 35444 | /* 99501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35445 | /* 99504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35446 | /* 99508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35447 | /* 99512 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35448 | /* 99516 */ // MIs[1] Operand 1 |
| 35449 | /* 99516 */ // No operand predicates |
| 35450 | /* 99516 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35451 | /* 99518 */ // (intrinsic_void 4182:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16) |
| 35452 | /* 99518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF), |
| 35453 | /* 99521 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 35454 | /* 99524 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35455 | /* 99529 */ GIR_RootConstrainSelectedInstOperands, |
| 35456 | /* 99530 */ // GIR_Coverage, 493, |
| 35457 | /* 99530 */ GIR_EraseRootFromParent_Done, |
| 35458 | /* 99531 */ // Label 1831: @99531 |
| 35459 | /* 99531 */ GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(99583), // Rule ID 558 // |
| 35460 | /* 99536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 35461 | /* 99539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 35462 | /* 99544 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35463 | /* 99547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35464 | /* 99551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35465 | /* 99555 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35466 | /* 99559 */ // MIs[1] Operand 1 |
| 35467 | /* 99559 */ // No operand predicates |
| 35468 | /* 99559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35469 | /* 99561 */ // (intrinsic_void 3742:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt) |
| 35470 | /* 99561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB), |
| 35471 | /* 99564 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35472 | /* 99567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35473 | /* 99570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35474 | /* 99576 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35475 | /* 99581 */ GIR_RootConstrainSelectedInstOperands, |
| 35476 | /* 99582 */ // GIR_Coverage, 558, |
| 35477 | /* 99582 */ GIR_EraseRootFromParent_Done, |
| 35478 | /* 99583 */ // Label 1832: @99583 |
| 35479 | /* 99583 */ GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(99635), // Rule ID 559 // |
| 35480 | /* 99588 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 35481 | /* 99591 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 35482 | /* 99596 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35483 | /* 99599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35484 | /* 99603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35485 | /* 99607 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35486 | /* 99611 */ // MIs[1] Operand 1 |
| 35487 | /* 99611 */ // No operand predicates |
| 35488 | /* 99611 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35489 | /* 99613 */ // (intrinsic_void 3743:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt) |
| 35490 | /* 99613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB), |
| 35491 | /* 99616 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35492 | /* 99619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35493 | /* 99622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35494 | /* 99628 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35495 | /* 99633 */ GIR_RootConstrainSelectedInstOperands, |
| 35496 | /* 99634 */ // GIR_Coverage, 559, |
| 35497 | /* 99634 */ GIR_EraseRootFromParent_Done, |
| 35498 | /* 99635 */ // Label 1833: @99635 |
| 35499 | /* 99635 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(99687), // Rule ID 560 // |
| 35500 | /* 99640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 35501 | /* 99643 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 35502 | /* 99648 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35503 | /* 99651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35504 | /* 99655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35505 | /* 99659 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35506 | /* 99663 */ // MIs[1] Operand 1 |
| 35507 | /* 99663 */ // No operand predicates |
| 35508 | /* 99663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35509 | /* 99665 */ // (intrinsic_void 3747:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt) |
| 35510 | /* 99665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB), |
| 35511 | /* 99668 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35512 | /* 99671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35513 | /* 99674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35514 | /* 99680 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35515 | /* 99685 */ GIR_RootConstrainSelectedInstOperands, |
| 35516 | /* 99686 */ // GIR_Coverage, 560, |
| 35517 | /* 99686 */ GIR_EraseRootFromParent_Done, |
| 35518 | /* 99687 */ // Label 1834: @99687 |
| 35519 | /* 99687 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(99739), // Rule ID 578 // |
| 35520 | /* 99692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35521 | /* 99695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 35522 | /* 99700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35523 | /* 99703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35524 | /* 99707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35525 | /* 99711 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 35526 | /* 99715 */ // MIs[1] Operand 1 |
| 35527 | /* 99715 */ // No operand predicates |
| 35528 | /* 99715 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35529 | /* 99717 */ // (intrinsic_void 3746:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm) |
| 35530 | /* 99717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT), |
| 35531 | /* 99720 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35532 | /* 99723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35533 | /* 99726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35534 | /* 99732 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35535 | /* 99737 */ GIR_RootConstrainSelectedInstOperands, |
| 35536 | /* 99738 */ // GIR_Coverage, 578, |
| 35537 | /* 99738 */ GIR_EraseRootFromParent_Done, |
| 35538 | /* 99739 */ // Label 1835: @99739 |
| 35539 | /* 99739 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(99791), // Rule ID 579 // |
| 35540 | /* 99744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35541 | /* 99747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 35542 | /* 99752 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35543 | /* 99755 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35544 | /* 99759 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35545 | /* 99763 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 35546 | /* 99767 */ // MIs[1] Operand 1 |
| 35547 | /* 99767 */ // No operand predicates |
| 35548 | /* 99767 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35549 | /* 99769 */ // (intrinsic_void 3741:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt) |
| 35550 | /* 99769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG), |
| 35551 | /* 99772 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 35552 | /* 99775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35553 | /* 99778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35554 | /* 99784 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35555 | /* 99789 */ GIR_RootConstrainSelectedInstOperands, |
| 35556 | /* 99790 */ // GIR_Coverage, 579, |
| 35557 | /* 99790 */ GIR_EraseRootFromParent_Done, |
| 35558 | /* 99791 */ // Label 1836: @99791 |
| 35559 | /* 99791 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(99831), // Rule ID 844 // |
| 35560 | /* 99796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 35561 | /* 99799 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr), |
| 35562 | /* 99804 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35563 | /* 99807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35564 | /* 99811 */ // (intrinsic_w_chain:{ *:[i32] } 3744:{ *:[iPTR] }) => (VMRS:{ *:[i32] }) |
| 35565 | /* 99811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 35566 | /* 99814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 35567 | /* 99816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35568 | /* 99819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35569 | /* 99825 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35570 | /* 99829 */ GIR_RootConstrainSelectedInstOperands, |
| 35571 | /* 99830 */ // GIR_Coverage, 844, |
| 35572 | /* 99830 */ GIR_EraseRootFromParent_Done, |
| 35573 | /* 99831 */ // Label 1837: @99831 |
| 35574 | /* 99831 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(99874), // Rule ID 845 // |
| 35575 | /* 99836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 35576 | /* 99839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr), |
| 35577 | /* 99844 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35578 | /* 99847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35579 | /* 99851 */ // (intrinsic_void 4126:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 35580 | /* 99851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 35581 | /* 99854 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 35582 | /* 99856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35583 | /* 99859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35584 | /* 99865 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 35585 | /* 99868 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35586 | /* 99872 */ GIR_RootConstrainSelectedInstOperands, |
| 35587 | /* 99873 */ // GIR_Coverage, 845, |
| 35588 | /* 99873 */ GIR_EraseRootFromParent_Done, |
| 35589 | /* 99874 */ // Label 1838: @99874 |
| 35590 | /* 99874 */ GIM_Reject, |
| 35591 | /* 99875 */ // Label 1821: @99875 |
| 35592 | /* 99875 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(99918), // Rule ID 603 // |
| 35593 | /* 99880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2), |
| 35594 | /* 99883 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 35595 | /* 99886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations), |
| 35596 | /* 99891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35597 | /* 99894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35598 | /* 99897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID), |
| 35599 | /* 99901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35600 | /* 99905 */ // (intrinsic_w_chain:{ *:[i32] } 361:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc) |
| 35601 | /* 99905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart), |
| 35602 | /* 99908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X] |
| 35603 | /* 99910 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc |
| 35604 | /* 99912 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35605 | /* 99916 */ GIR_RootConstrainSelectedInstOperands, |
| 35606 | /* 99917 */ // GIR_Coverage, 603, |
| 35607 | /* 99917 */ GIR_EraseRootFromParent_Done, |
| 35608 | /* 99918 */ // Label 1839: @99918 |
| 35609 | /* 99918 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(101909), |
| 35610 | /* 99923 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 35611 | /* 99926 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(99980), // Rule ID 5565 // |
| 35612 | /* 99931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 35613 | /* 99936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35614 | /* 99939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35615 | /* 99942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35616 | /* 99945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35617 | /* 99949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35618 | /* 99953 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 35619 | /* 99957 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35620 | /* 99961 */ // MIs[1] Operand 1 |
| 35621 | /* 99961 */ // No operand predicates |
| 35622 | /* 99961 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35623 | /* 99963 */ // (intrinsic_w_chain:{ *:[v4i32] } 3887:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35624 | /* 99963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 35625 | /* 99966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35626 | /* 99968 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 35627 | /* 99970 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35628 | /* 99973 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35629 | /* 99978 */ GIR_RootConstrainSelectedInstOperands, |
| 35630 | /* 99979 */ // GIR_Coverage, 5565, |
| 35631 | /* 99979 */ GIR_EraseRootFromParent_Done, |
| 35632 | /* 99980 */ // Label 1841: @99980 |
| 35633 | /* 99980 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(100034), // Rule ID 5571 // |
| 35634 | /* 99985 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 35635 | /* 99990 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35636 | /* 99993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35637 | /* 99996 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35638 | /* 99999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35639 | /* 100003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35640 | /* 100007 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 35641 | /* 100011 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35642 | /* 100015 */ // MIs[1] Operand 1 |
| 35643 | /* 100015 */ // No operand predicates |
| 35644 | /* 100015 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35645 | /* 100017 */ // (intrinsic_w_chain:{ *:[v4f32] } 3887:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35646 | /* 100017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 35647 | /* 100020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35648 | /* 100022 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 35649 | /* 100024 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35650 | /* 100027 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35651 | /* 100032 */ GIR_RootConstrainSelectedInstOperands, |
| 35652 | /* 100033 */ // GIR_Coverage, 5571, |
| 35653 | /* 100033 */ GIR_EraseRootFromParent_Done, |
| 35654 | /* 100034 */ // Label 1842: @100034 |
| 35655 | /* 100034 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(100088), // Rule ID 5573 // |
| 35656 | /* 100039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 35657 | /* 100044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35658 | /* 100047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35659 | /* 100050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35660 | /* 100053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35661 | /* 100057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35662 | /* 100061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 35663 | /* 100065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35664 | /* 100069 */ // MIs[1] Operand 1 |
| 35665 | /* 100069 */ // No operand predicates |
| 35666 | /* 100069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35667 | /* 100071 */ // (intrinsic_w_chain:{ *:[v2i64] } 3887:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35668 | /* 100071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 35669 | /* 100074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35670 | /* 100076 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 35671 | /* 100078 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35672 | /* 100081 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35673 | /* 100086 */ GIR_RootConstrainSelectedInstOperands, |
| 35674 | /* 100087 */ // GIR_Coverage, 5573, |
| 35675 | /* 100087 */ GIR_EraseRootFromParent_Done, |
| 35676 | /* 100088 */ // Label 1843: @100088 |
| 35677 | /* 100088 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(100142), // Rule ID 5575 // |
| 35678 | /* 100093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 35679 | /* 100098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35680 | /* 100101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35681 | /* 100104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35682 | /* 100107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35683 | /* 100111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35684 | /* 100115 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 35685 | /* 100119 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35686 | /* 100123 */ // MIs[1] Operand 1 |
| 35687 | /* 100123 */ // No operand predicates |
| 35688 | /* 100123 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35689 | /* 100125 */ // (intrinsic_w_chain:{ *:[v2f64] } 3887:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35690 | /* 100125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 35691 | /* 100128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35692 | /* 100130 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 35693 | /* 100132 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35694 | /* 100135 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35695 | /* 100140 */ GIR_RootConstrainSelectedInstOperands, |
| 35696 | /* 100141 */ // GIR_Coverage, 5575, |
| 35697 | /* 100141 */ GIR_EraseRootFromParent_Done, |
| 35698 | /* 100142 */ // Label 1844: @100142 |
| 35699 | /* 100142 */ GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(100184), // Rule ID 1926 // |
| 35700 | /* 100147 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space), |
| 35701 | /* 100152 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35702 | /* 100155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35703 | /* 100158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35704 | /* 100162 */ // MIs[0] size |
| 35705 | /* 100162 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35706 | /* 100165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35707 | /* 100169 */ // (intrinsic_w_chain:{ *:[i32] } 4157:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) |
| 35708 | /* 100169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE), |
| 35709 | /* 100172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35710 | /* 100174 */ GIR_RootToRootCopy, /*OpIdx*/2, // size |
| 35711 | /* 100176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 35712 | /* 100178 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35713 | /* 100182 */ GIR_RootConstrainSelectedInstOperands, |
| 35714 | /* 100183 */ // GIR_Coverage, 1926, |
| 35715 | /* 100183 */ GIR_EraseRootFromParent_Done, |
| 35716 | /* 100184 */ // Label 1845: @100184 |
| 35717 | /* 100184 */ GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(100238), // Rule ID 5567 // |
| 35718 | /* 100189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 35719 | /* 100194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35720 | /* 100197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35721 | /* 100200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35722 | /* 100203 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35723 | /* 100207 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35724 | /* 100211 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35725 | /* 100215 */ // MIs[1] Operand 1 |
| 35726 | /* 100215 */ // No operand predicates |
| 35727 | /* 100215 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35728 | /* 100219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35729 | /* 100221 */ // (intrinsic_void 3969:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35730 | /* 100221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 35731 | /* 100224 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 35732 | /* 100226 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 35733 | /* 100228 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35734 | /* 100231 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35735 | /* 100236 */ GIR_RootConstrainSelectedInstOperands, |
| 35736 | /* 100237 */ // GIR_Coverage, 5567, |
| 35737 | /* 100237 */ GIR_EraseRootFromParent_Done, |
| 35738 | /* 100238 */ // Label 1846: @100238 |
| 35739 | /* 100238 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(100292), // Rule ID 5577 // |
| 35740 | /* 100243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 35741 | /* 100248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35742 | /* 100251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35743 | /* 100254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35744 | /* 100257 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35745 | /* 100261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35746 | /* 100265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35747 | /* 100269 */ // MIs[1] Operand 1 |
| 35748 | /* 100269 */ // No operand predicates |
| 35749 | /* 100269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35750 | /* 100273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35751 | /* 100275 */ // (intrinsic_void 3969:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35752 | /* 100275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 35753 | /* 100278 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 35754 | /* 100280 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 35755 | /* 100282 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35756 | /* 100285 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35757 | /* 100290 */ GIR_RootConstrainSelectedInstOperands, |
| 35758 | /* 100291 */ // GIR_Coverage, 5577, |
| 35759 | /* 100291 */ GIR_EraseRootFromParent_Done, |
| 35760 | /* 100292 */ // Label 1847: @100292 |
| 35761 | /* 100292 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(100346), // Rule ID 5581 // |
| 35762 | /* 100297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 35763 | /* 100302 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 35764 | /* 100305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35765 | /* 100308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35766 | /* 100311 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35767 | /* 100315 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35768 | /* 100319 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35769 | /* 100323 */ // MIs[1] Operand 1 |
| 35770 | /* 100323 */ // No operand predicates |
| 35771 | /* 100323 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35772 | /* 100327 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35773 | /* 100329 */ // (intrinsic_void 3969:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35774 | /* 100329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 35775 | /* 100332 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 35776 | /* 100334 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 35777 | /* 100336 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35778 | /* 100339 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35779 | /* 100344 */ GIR_RootConstrainSelectedInstOperands, |
| 35780 | /* 100345 */ // GIR_Coverage, 5581, |
| 35781 | /* 100345 */ GIR_EraseRootFromParent_Done, |
| 35782 | /* 100346 */ // Label 1848: @100346 |
| 35783 | /* 100346 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(100400), // Rule ID 5585 // |
| 35784 | /* 100351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 35785 | /* 100356 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 35786 | /* 100359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35787 | /* 100362 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35788 | /* 100365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35789 | /* 100369 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35790 | /* 100373 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35791 | /* 100377 */ // MIs[1] Operand 1 |
| 35792 | /* 100377 */ // No operand predicates |
| 35793 | /* 100377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35794 | /* 100381 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35795 | /* 100383 */ // (intrinsic_void 3969:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 35796 | /* 100383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 35797 | /* 100386 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 35798 | /* 100388 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 35799 | /* 100390 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 35800 | /* 100393 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 35801 | /* 100398 */ GIR_RootConstrainSelectedInstOperands, |
| 35802 | /* 100399 */ // GIR_Coverage, 5585, |
| 35803 | /* 100399 */ GIR_EraseRootFromParent_Done, |
| 35804 | /* 100400 */ // Label 1849: @100400 |
| 35805 | /* 100400 */ GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(100458), // Rule ID 3 // |
| 35806 | /* 100405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 35807 | /* 100408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 35808 | /* 100413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35809 | /* 100416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35810 | /* 100419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35811 | /* 100422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35812 | /* 100426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35813 | /* 100430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35814 | /* 100434 */ // (intrinsic_w_chain:{ *:[i32] } 4125:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 35815 | /* 100434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL), |
| 35816 | /* 100437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35817 | /* 100439 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35818 | /* 100441 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35819 | /* 100443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35820 | /* 100446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35821 | /* 100452 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35822 | /* 100456 */ GIR_RootConstrainSelectedInstOperands, |
| 35823 | /* 100457 */ // GIR_Coverage, 3, |
| 35824 | /* 100457 */ GIR_EraseRootFromParent_Done, |
| 35825 | /* 100458 */ // Label 1850: @100458 |
| 35826 | /* 100458 */ GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(100516), // Rule ID 120 // |
| 35827 | /* 100463 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35828 | /* 100466 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 35829 | /* 100471 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35830 | /* 100474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35831 | /* 100477 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35832 | /* 100480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35833 | /* 100484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35834 | /* 100488 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35835 | /* 100492 */ // (intrinsic_w_chain:{ *:[i32] } 4124:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35836 | /* 100492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX), |
| 35837 | /* 100495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35838 | /* 100497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35839 | /* 100499 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35840 | /* 100501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35841 | /* 100504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35842 | /* 100510 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35843 | /* 100514 */ GIR_RootConstrainSelectedInstOperands, |
| 35844 | /* 100515 */ // GIR_Coverage, 120, |
| 35845 | /* 100515 */ GIR_EraseRootFromParent_Done, |
| 35846 | /* 100516 */ // Label 1851: @100516 |
| 35847 | /* 100516 */ GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(100574), // Rule ID 121 // |
| 35848 | /* 100521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35849 | /* 100524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 35850 | /* 100529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35851 | /* 100532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35852 | /* 100535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35853 | /* 100538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35854 | /* 100542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35855 | /* 100546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35856 | /* 100550 */ // (intrinsic_w_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35857 | /* 100550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16), |
| 35858 | /* 100553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35859 | /* 100555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35860 | /* 100557 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35861 | /* 100559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35862 | /* 100562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35863 | /* 100568 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35864 | /* 100572 */ GIR_RootConstrainSelectedInstOperands, |
| 35865 | /* 100573 */ // GIR_Coverage, 121, |
| 35866 | /* 100573 */ GIR_EraseRootFromParent_Done, |
| 35867 | /* 100574 */ // Label 1852: @100574 |
| 35868 | /* 100574 */ GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(100632), // Rule ID 122 // |
| 35869 | /* 100579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35870 | /* 100582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 35871 | /* 100587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35872 | /* 100590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35873 | /* 100593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35874 | /* 100596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35875 | /* 100600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35876 | /* 100604 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35877 | /* 100608 */ // (intrinsic_w_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35878 | /* 100608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8), |
| 35879 | /* 100611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35880 | /* 100613 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35881 | /* 100615 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35882 | /* 100617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35883 | /* 100620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35884 | /* 100626 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35885 | /* 100630 */ GIR_RootConstrainSelectedInstOperands, |
| 35886 | /* 100631 */ // GIR_Coverage, 122, |
| 35887 | /* 100631 */ GIR_EraseRootFromParent_Done, |
| 35888 | /* 100632 */ // Label 1853: @100632 |
| 35889 | /* 100632 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(100690), // Rule ID 123 // |
| 35890 | /* 100637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35891 | /* 100640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 35892 | /* 100645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35893 | /* 100648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35894 | /* 100651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35895 | /* 100654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35896 | /* 100658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35897 | /* 100662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35898 | /* 100666 */ // (intrinsic_w_chain:{ *:[i32] } 4160:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35899 | /* 100666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX), |
| 35900 | /* 100669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35901 | /* 100671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35902 | /* 100673 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35903 | /* 100675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35904 | /* 100678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35905 | /* 100684 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35906 | /* 100688 */ GIR_RootConstrainSelectedInstOperands, |
| 35907 | /* 100689 */ // GIR_Coverage, 123, |
| 35908 | /* 100689 */ GIR_EraseRootFromParent_Done, |
| 35909 | /* 100690 */ // Label 1854: @100690 |
| 35910 | /* 100690 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(100748), // Rule ID 124 // |
| 35911 | /* 100695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35912 | /* 100698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 35913 | /* 100703 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35914 | /* 100706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35915 | /* 100709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35916 | /* 100712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35917 | /* 100716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35918 | /* 100720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35919 | /* 100724 */ // (intrinsic_w_chain:{ *:[i32] } 4161:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35920 | /* 100724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16), |
| 35921 | /* 100727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35922 | /* 100729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35923 | /* 100731 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35924 | /* 100733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35925 | /* 100736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35926 | /* 100742 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35927 | /* 100746 */ GIR_RootConstrainSelectedInstOperands, |
| 35928 | /* 100747 */ // GIR_Coverage, 124, |
| 35929 | /* 100747 */ GIR_EraseRootFromParent_Done, |
| 35930 | /* 100748 */ // Label 1855: @100748 |
| 35931 | /* 100748 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(100806), // Rule ID 125 // |
| 35932 | /* 100753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35933 | /* 100756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 35934 | /* 100761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35935 | /* 100764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35936 | /* 100767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35937 | /* 100770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35938 | /* 100774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35939 | /* 100778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35940 | /* 100782 */ // (intrinsic_w_chain:{ *:[i32] } 4162:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35941 | /* 100782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8), |
| 35942 | /* 100785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35943 | /* 100787 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35944 | /* 100789 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35945 | /* 100791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35946 | /* 100794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35947 | /* 100800 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35948 | /* 100804 */ GIR_RootConstrainSelectedInstOperands, |
| 35949 | /* 100805 */ // GIR_Coverage, 125, |
| 35950 | /* 100805 */ GIR_EraseRootFromParent_Done, |
| 35951 | /* 100806 */ // Label 1856: @100806 |
| 35952 | /* 100806 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(100864), // Rule ID 126 // |
| 35953 | /* 100811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35954 | /* 100814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 35955 | /* 100819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35956 | /* 100822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35957 | /* 100825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35958 | /* 100828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35959 | /* 100832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35960 | /* 100836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35961 | /* 100840 */ // (intrinsic_w_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35962 | /* 100840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX), |
| 35963 | /* 100843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35964 | /* 100845 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35965 | /* 100847 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35966 | /* 100849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35967 | /* 100852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35968 | /* 100858 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35969 | /* 100862 */ GIR_RootConstrainSelectedInstOperands, |
| 35970 | /* 100863 */ // GIR_Coverage, 126, |
| 35971 | /* 100863 */ GIR_EraseRootFromParent_Done, |
| 35972 | /* 100864 */ // Label 1857: @100864 |
| 35973 | /* 100864 */ GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(100922), // Rule ID 127 // |
| 35974 | /* 100869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35975 | /* 100872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 35976 | /* 100877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35977 | /* 100880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35978 | /* 100883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35979 | /* 100886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35980 | /* 100890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35981 | /* 100894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35982 | /* 100898 */ // (intrinsic_w_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 35983 | /* 100898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16), |
| 35984 | /* 100901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35985 | /* 100903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 35986 | /* 100905 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 35987 | /* 100907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35988 | /* 100910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35989 | /* 100916 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35990 | /* 100920 */ GIR_RootConstrainSelectedInstOperands, |
| 35991 | /* 100921 */ // GIR_Coverage, 127, |
| 35992 | /* 100921 */ GIR_EraseRootFromParent_Done, |
| 35993 | /* 100922 */ // Label 1858: @100922 |
| 35994 | /* 100922 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(100980), // Rule ID 128 // |
| 35995 | /* 100927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35996 | /* 100930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 35997 | /* 100935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35998 | /* 100938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35999 | /* 100941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36000 | /* 100944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36001 | /* 100948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36002 | /* 100952 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36003 | /* 100956 */ // (intrinsic_w_chain:{ *:[i32] } 4174:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 36004 | /* 100956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8), |
| 36005 | /* 100959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36006 | /* 100961 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36007 | /* 100963 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36008 | /* 100965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36009 | /* 100968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36010 | /* 100974 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36011 | /* 100978 */ GIR_RootConstrainSelectedInstOperands, |
| 36012 | /* 100979 */ // GIR_Coverage, 128, |
| 36013 | /* 100979 */ GIR_EraseRootFromParent_Done, |
| 36014 | /* 100980 */ // Label 1859: @100980 |
| 36015 | /* 100980 */ GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(101038), // Rule ID 129 // |
| 36016 | /* 100985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 36017 | /* 100988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 36018 | /* 100993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36019 | /* 100996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36020 | /* 100999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36021 | /* 101002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36022 | /* 101006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36023 | /* 101010 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36024 | /* 101014 */ // (intrinsic_w_chain:{ *:[i32] } 4193:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 36025 | /* 101014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX), |
| 36026 | /* 101017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36027 | /* 101019 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36028 | /* 101021 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36029 | /* 101023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36030 | /* 101026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36031 | /* 101032 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36032 | /* 101036 */ GIR_RootConstrainSelectedInstOperands, |
| 36033 | /* 101037 */ // GIR_Coverage, 129, |
| 36034 | /* 101037 */ GIR_EraseRootFromParent_Done, |
| 36035 | /* 101038 */ // Label 1860: @101038 |
| 36036 | /* 101038 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(101096), // Rule ID 130 // |
| 36037 | /* 101043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 36038 | /* 101046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 36039 | /* 101051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36040 | /* 101054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36041 | /* 101057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36042 | /* 101060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36043 | /* 101064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36044 | /* 101068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36045 | /* 101072 */ // (intrinsic_w_chain:{ *:[i32] } 4194:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 36046 | /* 101072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16), |
| 36047 | /* 101075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36048 | /* 101077 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36049 | /* 101079 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36050 | /* 101081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36051 | /* 101084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36052 | /* 101090 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36053 | /* 101094 */ GIR_RootConstrainSelectedInstOperands, |
| 36054 | /* 101095 */ // GIR_Coverage, 130, |
| 36055 | /* 101095 */ GIR_EraseRootFromParent_Done, |
| 36056 | /* 101096 */ // Label 1861: @101096 |
| 36057 | /* 101096 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(101154), // Rule ID 131 // |
| 36058 | /* 101101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 36059 | /* 101104 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 36060 | /* 101109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36061 | /* 101112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36062 | /* 101115 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36063 | /* 101118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36064 | /* 101122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36065 | /* 101126 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36066 | /* 101130 */ // (intrinsic_w_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 36067 | /* 101130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8), |
| 36068 | /* 101133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36069 | /* 101135 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36070 | /* 101137 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36071 | /* 101139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36072 | /* 101142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36073 | /* 101148 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36074 | /* 101152 */ GIR_RootConstrainSelectedInstOperands, |
| 36075 | /* 101153 */ // GIR_Coverage, 131, |
| 36076 | /* 101153 */ GIR_EraseRootFromParent_Done, |
| 36077 | /* 101154 */ // Label 1862: @101154 |
| 36078 | /* 101154 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(101212), // Rule ID 430 // |
| 36079 | /* 101159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36080 | /* 101162 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 36081 | /* 101167 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36082 | /* 101170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36083 | /* 101173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36084 | /* 101176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36085 | /* 101180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36086 | /* 101184 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36087 | /* 101188 */ // (intrinsic_w_chain:{ *:[i32] } 4125:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 36088 | /* 101188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL), |
| 36089 | /* 101191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36090 | /* 101193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36091 | /* 101195 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36092 | /* 101197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36093 | /* 101200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36094 | /* 101206 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36095 | /* 101210 */ GIR_RootConstrainSelectedInstOperands, |
| 36096 | /* 101211 */ // GIR_Coverage, 430, |
| 36097 | /* 101211 */ GIR_EraseRootFromParent_Done, |
| 36098 | /* 101212 */ // Label 1863: @101212 |
| 36099 | /* 101212 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(101270), // Rule ID 443 // |
| 36100 | /* 101217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36101 | /* 101220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 36102 | /* 101225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36103 | /* 101228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36104 | /* 101231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36105 | /* 101234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36106 | /* 101238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36107 | /* 101242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36108 | /* 101246 */ // (intrinsic_w_chain:{ *:[i32] } 4124:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36109 | /* 101246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX), |
| 36110 | /* 101249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36111 | /* 101251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36112 | /* 101253 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36113 | /* 101255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36114 | /* 101258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36115 | /* 101264 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36116 | /* 101268 */ GIR_RootConstrainSelectedInstOperands, |
| 36117 | /* 101269 */ // GIR_Coverage, 443, |
| 36118 | /* 101269 */ GIR_EraseRootFromParent_Done, |
| 36119 | /* 101270 */ // Label 1864: @101270 |
| 36120 | /* 101270 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(101328), // Rule ID 444 // |
| 36121 | /* 101275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36122 | /* 101278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 36123 | /* 101283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36124 | /* 101286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36125 | /* 101289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36126 | /* 101292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36127 | /* 101296 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36128 | /* 101300 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36129 | /* 101304 */ // (intrinsic_w_chain:{ *:[i32] } 4122:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36130 | /* 101304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16), |
| 36131 | /* 101307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36132 | /* 101309 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36133 | /* 101311 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36134 | /* 101313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36135 | /* 101316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36136 | /* 101322 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36137 | /* 101326 */ GIR_RootConstrainSelectedInstOperands, |
| 36138 | /* 101327 */ // GIR_Coverage, 444, |
| 36139 | /* 101327 */ GIR_EraseRootFromParent_Done, |
| 36140 | /* 101328 */ // Label 1865: @101328 |
| 36141 | /* 101328 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(101386), // Rule ID 445 // |
| 36142 | /* 101333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36143 | /* 101336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 36144 | /* 101341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36145 | /* 101344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36146 | /* 101347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36147 | /* 101350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36148 | /* 101354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36149 | /* 101358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36150 | /* 101362 */ // (intrinsic_w_chain:{ *:[i32] } 4123:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36151 | /* 101362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8), |
| 36152 | /* 101365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36153 | /* 101367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36154 | /* 101369 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36155 | /* 101371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36156 | /* 101374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36157 | /* 101380 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36158 | /* 101384 */ GIR_RootConstrainSelectedInstOperands, |
| 36159 | /* 101385 */ // GIR_Coverage, 445, |
| 36160 | /* 101385 */ GIR_EraseRootFromParent_Done, |
| 36161 | /* 101386 */ // Label 1866: @101386 |
| 36162 | /* 101386 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(101444), // Rule ID 446 // |
| 36163 | /* 101391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36164 | /* 101394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 36165 | /* 101399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36166 | /* 101402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36167 | /* 101405 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36168 | /* 101408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36169 | /* 101412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36170 | /* 101416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36171 | /* 101420 */ // (intrinsic_w_chain:{ *:[i32] } 4160:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36172 | /* 101420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX), |
| 36173 | /* 101423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36174 | /* 101425 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36175 | /* 101427 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36176 | /* 101429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36177 | /* 101432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36178 | /* 101438 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36179 | /* 101442 */ GIR_RootConstrainSelectedInstOperands, |
| 36180 | /* 101443 */ // GIR_Coverage, 446, |
| 36181 | /* 101443 */ GIR_EraseRootFromParent_Done, |
| 36182 | /* 101444 */ // Label 1867: @101444 |
| 36183 | /* 101444 */ GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(101502), // Rule ID 447 // |
| 36184 | /* 101449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36185 | /* 101452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 36186 | /* 101457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36187 | /* 101460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36188 | /* 101463 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36189 | /* 101466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36190 | /* 101470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36191 | /* 101474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36192 | /* 101478 */ // (intrinsic_w_chain:{ *:[i32] } 4161:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36193 | /* 101478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16), |
| 36194 | /* 101481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36195 | /* 101483 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36196 | /* 101485 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36197 | /* 101487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36198 | /* 101490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36199 | /* 101496 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36200 | /* 101500 */ GIR_RootConstrainSelectedInstOperands, |
| 36201 | /* 101501 */ // GIR_Coverage, 447, |
| 36202 | /* 101501 */ GIR_EraseRootFromParent_Done, |
| 36203 | /* 101502 */ // Label 1868: @101502 |
| 36204 | /* 101502 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(101560), // Rule ID 448 // |
| 36205 | /* 101507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36206 | /* 101510 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 36207 | /* 101515 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36208 | /* 101518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36209 | /* 101521 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36210 | /* 101524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36211 | /* 101528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36212 | /* 101532 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36213 | /* 101536 */ // (intrinsic_w_chain:{ *:[i32] } 4162:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36214 | /* 101536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8), |
| 36215 | /* 101539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36216 | /* 101541 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36217 | /* 101543 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36218 | /* 101545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36219 | /* 101548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36220 | /* 101554 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36221 | /* 101558 */ GIR_RootConstrainSelectedInstOperands, |
| 36222 | /* 101559 */ // GIR_Coverage, 448, |
| 36223 | /* 101559 */ GIR_EraseRootFromParent_Done, |
| 36224 | /* 101560 */ // Label 1869: @101560 |
| 36225 | /* 101560 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(101618), // Rule ID 449 // |
| 36226 | /* 101565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36227 | /* 101568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 36228 | /* 101573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36229 | /* 101576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36230 | /* 101579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36231 | /* 101582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36232 | /* 101586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36233 | /* 101590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36234 | /* 101594 */ // (intrinsic_w_chain:{ *:[i32] } 4175:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36235 | /* 101594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX), |
| 36236 | /* 101597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36237 | /* 101599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36238 | /* 101601 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36239 | /* 101603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36240 | /* 101606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36241 | /* 101612 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36242 | /* 101616 */ GIR_RootConstrainSelectedInstOperands, |
| 36243 | /* 101617 */ // GIR_Coverage, 449, |
| 36244 | /* 101617 */ GIR_EraseRootFromParent_Done, |
| 36245 | /* 101618 */ // Label 1870: @101618 |
| 36246 | /* 101618 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(101676), // Rule ID 450 // |
| 36247 | /* 101623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36248 | /* 101626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 36249 | /* 101631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36250 | /* 101634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36251 | /* 101637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36252 | /* 101640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36253 | /* 101644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36254 | /* 101648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36255 | /* 101652 */ // (intrinsic_w_chain:{ *:[i32] } 4173:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36256 | /* 101652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16), |
| 36257 | /* 101655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36258 | /* 101657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36259 | /* 101659 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36260 | /* 101661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36261 | /* 101664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36262 | /* 101670 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36263 | /* 101674 */ GIR_RootConstrainSelectedInstOperands, |
| 36264 | /* 101675 */ // GIR_Coverage, 450, |
| 36265 | /* 101675 */ GIR_EraseRootFromParent_Done, |
| 36266 | /* 101676 */ // Label 1871: @101676 |
| 36267 | /* 101676 */ GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(101734), // Rule ID 451 // |
| 36268 | /* 101681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36269 | /* 101684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 36270 | /* 101689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36271 | /* 101692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36272 | /* 101695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36273 | /* 101698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36274 | /* 101702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36275 | /* 101706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36276 | /* 101710 */ // (intrinsic_w_chain:{ *:[i32] } 4174:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36277 | /* 101710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8), |
| 36278 | /* 101713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36279 | /* 101715 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36280 | /* 101717 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36281 | /* 101719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36282 | /* 101722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36283 | /* 101728 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36284 | /* 101732 */ GIR_RootConstrainSelectedInstOperands, |
| 36285 | /* 101733 */ // GIR_Coverage, 451, |
| 36286 | /* 101733 */ GIR_EraseRootFromParent_Done, |
| 36287 | /* 101734 */ // Label 1872: @101734 |
| 36288 | /* 101734 */ GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(101792), // Rule ID 452 // |
| 36289 | /* 101739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36290 | /* 101742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 36291 | /* 101747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36292 | /* 101750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36293 | /* 101753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36294 | /* 101756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36295 | /* 101760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36296 | /* 101764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36297 | /* 101768 */ // (intrinsic_w_chain:{ *:[i32] } 4193:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36298 | /* 101768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX), |
| 36299 | /* 101771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36300 | /* 101773 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36301 | /* 101775 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36302 | /* 101777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36303 | /* 101780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36304 | /* 101786 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36305 | /* 101790 */ GIR_RootConstrainSelectedInstOperands, |
| 36306 | /* 101791 */ // GIR_Coverage, 452, |
| 36307 | /* 101791 */ GIR_EraseRootFromParent_Done, |
| 36308 | /* 101792 */ // Label 1873: @101792 |
| 36309 | /* 101792 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(101850), // Rule ID 453 // |
| 36310 | /* 101797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36311 | /* 101800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 36312 | /* 101805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36313 | /* 101808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36314 | /* 101811 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36315 | /* 101814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36316 | /* 101818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36317 | /* 101822 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36318 | /* 101826 */ // (intrinsic_w_chain:{ *:[i32] } 4194:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36319 | /* 101826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16), |
| 36320 | /* 101829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36321 | /* 101831 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36322 | /* 101833 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36323 | /* 101835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36324 | /* 101838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36325 | /* 101844 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36326 | /* 101848 */ GIR_RootConstrainSelectedInstOperands, |
| 36327 | /* 101849 */ // GIR_Coverage, 453, |
| 36328 | /* 101849 */ GIR_EraseRootFromParent_Done, |
| 36329 | /* 101850 */ // Label 1874: @101850 |
| 36330 | /* 101850 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(101908), // Rule ID 454 // |
| 36331 | /* 101855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36332 | /* 101858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 36333 | /* 101863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36334 | /* 101866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36335 | /* 101869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36336 | /* 101872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36337 | /* 101876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36338 | /* 101880 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36339 | /* 101884 */ // (intrinsic_w_chain:{ *:[i32] } 4195:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36340 | /* 101884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8), |
| 36341 | /* 101887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36342 | /* 101889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36343 | /* 101891 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 36344 | /* 101893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36345 | /* 101896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36346 | /* 101902 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36347 | /* 101906 */ GIR_RootConstrainSelectedInstOperands, |
| 36348 | /* 101907 */ // GIR_Coverage, 454, |
| 36349 | /* 101907 */ GIR_EraseRootFromParent_Done, |
| 36350 | /* 101908 */ // Label 1875: @101908 |
| 36351 | /* 101908 */ GIM_Reject, |
| 36352 | /* 101909 */ // Label 1840: @101909 |
| 36353 | /* 101909 */ GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(102155), |
| 36354 | /* 101914 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 36355 | /* 101917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb), |
| 36356 | /* 101922 */ GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(101980), // Rule ID 5569 // |
| 36357 | /* 101927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36358 | /* 101930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36359 | /* 101933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36360 | /* 101936 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 36361 | /* 101939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36362 | /* 101943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36363 | /* 101947 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 36364 | /* 101951 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36365 | /* 101955 */ // MIs[1] Operand 1 |
| 36366 | /* 101955 */ // No operand predicates |
| 36367 | /* 101955 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36368 | /* 101959 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36369 | /* 101961 */ // (intrinsic_w_chain:{ *:[v4i32] } 3971:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 36370 | /* 101961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 36371 | /* 101964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 36372 | /* 101966 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 36373 | /* 101968 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 36374 | /* 101970 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 36375 | /* 101973 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 36376 | /* 101978 */ GIR_RootConstrainSelectedInstOperands, |
| 36377 | /* 101979 */ // GIR_Coverage, 5569, |
| 36378 | /* 101979 */ GIR_EraseRootFromParent_Done, |
| 36379 | /* 101980 */ // Label 1877: @101980 |
| 36380 | /* 101980 */ GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(102038), // Rule ID 5579 // |
| 36381 | /* 101985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36382 | /* 101988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36383 | /* 101991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36384 | /* 101994 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 36385 | /* 101997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36386 | /* 102001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36387 | /* 102005 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 36388 | /* 102009 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36389 | /* 102013 */ // MIs[1] Operand 1 |
| 36390 | /* 102013 */ // No operand predicates |
| 36391 | /* 102013 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36392 | /* 102017 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36393 | /* 102019 */ // (intrinsic_w_chain:{ *:[v4i32] } 3971:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 36394 | /* 102019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 36395 | /* 102022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 36396 | /* 102024 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 36397 | /* 102026 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 36398 | /* 102028 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 36399 | /* 102031 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 36400 | /* 102036 */ GIR_RootConstrainSelectedInstOperands, |
| 36401 | /* 102037 */ // GIR_Coverage, 5579, |
| 36402 | /* 102037 */ GIR_EraseRootFromParent_Done, |
| 36403 | /* 102038 */ // Label 1878: @102038 |
| 36404 | /* 102038 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(102096), // Rule ID 5583 // |
| 36405 | /* 102043 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 36406 | /* 102046 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36407 | /* 102049 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36408 | /* 102052 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 36409 | /* 102055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36410 | /* 102059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36411 | /* 102063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 36412 | /* 102067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36413 | /* 102071 */ // MIs[1] Operand 1 |
| 36414 | /* 102071 */ // No operand predicates |
| 36415 | /* 102071 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36416 | /* 102075 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36417 | /* 102077 */ // (intrinsic_w_chain:{ *:[v2i64] } 3971:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 36418 | /* 102077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 36419 | /* 102080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 36420 | /* 102082 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 36421 | /* 102084 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 36422 | /* 102086 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 36423 | /* 102089 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 36424 | /* 102094 */ GIR_RootConstrainSelectedInstOperands, |
| 36425 | /* 102095 */ // GIR_Coverage, 5583, |
| 36426 | /* 102095 */ GIR_EraseRootFromParent_Done, |
| 36427 | /* 102096 */ // Label 1879: @102096 |
| 36428 | /* 102096 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(102154), // Rule ID 5587 // |
| 36429 | /* 102101 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 36430 | /* 102104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36431 | /* 102107 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36432 | /* 102110 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 36433 | /* 102113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36434 | /* 102117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36435 | /* 102121 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 36436 | /* 102125 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36437 | /* 102129 */ // MIs[1] Operand 1 |
| 36438 | /* 102129 */ // No operand predicates |
| 36439 | /* 102129 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36440 | /* 102133 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36441 | /* 102135 */ // (intrinsic_w_chain:{ *:[v2i64] } 3971:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 36442 | /* 102135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 36443 | /* 102138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 36444 | /* 102140 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 36445 | /* 102142 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 36446 | /* 102144 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 36447 | /* 102147 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 36448 | /* 102152 */ GIR_RootConstrainSelectedInstOperands, |
| 36449 | /* 102153 */ // GIR_Coverage, 5587, |
| 36450 | /* 102153 */ GIR_EraseRootFromParent_Done, |
| 36451 | /* 102154 */ // Label 1880: @102154 |
| 36452 | /* 102154 */ GIM_Reject, |
| 36453 | /* 102155 */ // Label 1876: @102155 |
| 36454 | /* 102155 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(103326), |
| 36455 | /* 102160 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 36456 | /* 102163 */ GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(102224), // Rule ID 5457 // |
| 36457 | /* 102168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36458 | /* 102173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36459 | /* 102176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 36460 | /* 102179 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36461 | /* 102182 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36462 | /* 102185 */ // MIs[0] base |
| 36463 | /* 102185 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36464 | /* 102189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36465 | /* 102193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36466 | /* 102197 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36467 | /* 102201 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 36468 | /* 102205 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36469 | /* 102209 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 36470 | /* 102209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 36471 | /* 102212 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36472 | /* 102214 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36473 | /* 102216 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36474 | /* 102218 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36475 | /* 102222 */ GIR_RootConstrainSelectedInstOperands, |
| 36476 | /* 102223 */ // GIR_Coverage, 5457, |
| 36477 | /* 102223 */ GIR_EraseRootFromParent_Done, |
| 36478 | /* 102224 */ // Label 1882: @102224 |
| 36479 | /* 102224 */ GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(102285), // Rule ID 5458 // |
| 36480 | /* 102229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36481 | /* 102234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36482 | /* 102237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 36483 | /* 102240 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36484 | /* 102243 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36485 | /* 102246 */ // MIs[0] base |
| 36486 | /* 102246 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36487 | /* 102250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36488 | /* 102254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36489 | /* 102258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36490 | /* 102262 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 36491 | /* 102266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 36492 | /* 102270 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 36493 | /* 102270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 36494 | /* 102273 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36495 | /* 102275 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36496 | /* 102277 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36497 | /* 102279 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36498 | /* 102283 */ GIR_RootConstrainSelectedInstOperands, |
| 36499 | /* 102284 */ // GIR_Coverage, 5458, |
| 36500 | /* 102284 */ GIR_EraseRootFromParent_Done, |
| 36501 | /* 102285 */ // Label 1883: @102285 |
| 36502 | /* 102285 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(102346), // Rule ID 5461 // |
| 36503 | /* 102290 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36504 | /* 102295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36505 | /* 102298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 36506 | /* 102301 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36507 | /* 102304 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36508 | /* 102307 */ // MIs[0] base |
| 36509 | /* 102307 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36510 | /* 102311 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36511 | /* 102315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36512 | /* 102319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36513 | /* 102323 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 36514 | /* 102327 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36515 | /* 102331 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 36516 | /* 102331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq), |
| 36517 | /* 102334 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36518 | /* 102336 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36519 | /* 102338 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36520 | /* 102340 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36521 | /* 102344 */ GIR_RootConstrainSelectedInstOperands, |
| 36522 | /* 102345 */ // GIR_Coverage, 5461, |
| 36523 | /* 102345 */ GIR_EraseRootFromParent_Done, |
| 36524 | /* 102346 */ // Label 1884: @102346 |
| 36525 | /* 102346 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(102407), // Rule ID 5541 // |
| 36526 | /* 102351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36527 | /* 102356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36528 | /* 102359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 36529 | /* 102362 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36530 | /* 102365 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36531 | /* 102368 */ // MIs[0] base |
| 36532 | /* 102368 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36533 | /* 102372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36534 | /* 102376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36535 | /* 102380 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36536 | /* 102384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 36537 | /* 102388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36538 | /* 102392 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 36539 | /* 102392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq), |
| 36540 | /* 102395 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36541 | /* 102397 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36542 | /* 102399 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36543 | /* 102401 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36544 | /* 102405 */ GIR_RootConstrainSelectedInstOperands, |
| 36545 | /* 102406 */ // GIR_Coverage, 5541, |
| 36546 | /* 102406 */ GIR_EraseRootFromParent_Done, |
| 36547 | /* 102407 */ // Label 1885: @102407 |
| 36548 | /* 102407 */ GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(102468), // Rule ID 5543 // |
| 36549 | /* 102412 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36550 | /* 102417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36551 | /* 102420 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 36552 | /* 102423 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36553 | /* 102426 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36554 | /* 102429 */ // MIs[0] base |
| 36555 | /* 102429 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36556 | /* 102433 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36557 | /* 102437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36558 | /* 102441 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36559 | /* 102445 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 36560 | /* 102449 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36561 | /* 102453 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 36562 | /* 102453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq), |
| 36563 | /* 102456 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36564 | /* 102458 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36565 | /* 102460 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36566 | /* 102462 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36567 | /* 102466 */ GIR_RootConstrainSelectedInstOperands, |
| 36568 | /* 102467 */ // GIR_Coverage, 5543, |
| 36569 | /* 102467 */ GIR_EraseRootFromParent_Done, |
| 36570 | /* 102468 */ // Label 1886: @102468 |
| 36571 | /* 102468 */ GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(102529), // Rule ID 5545 // |
| 36572 | /* 102473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36573 | /* 102478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36574 | /* 102481 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 36575 | /* 102484 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36576 | /* 102487 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36577 | /* 102490 */ // MIs[0] base |
| 36578 | /* 102490 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36579 | /* 102494 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36580 | /* 102498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36581 | /* 102502 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36582 | /* 102506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 36583 | /* 102510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36584 | /* 102514 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 36585 | /* 102514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 36586 | /* 102517 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36587 | /* 102519 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36588 | /* 102521 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36589 | /* 102523 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36590 | /* 102527 */ GIR_RootConstrainSelectedInstOperands, |
| 36591 | /* 102528 */ // GIR_Coverage, 5545, |
| 36592 | /* 102528 */ GIR_EraseRootFromParent_Done, |
| 36593 | /* 102529 */ // Label 1887: @102529 |
| 36594 | /* 102529 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(102590), // Rule ID 5546 // |
| 36595 | /* 102534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36596 | /* 102539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36597 | /* 102542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 36598 | /* 102545 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36599 | /* 102548 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36600 | /* 102551 */ // MIs[0] base |
| 36601 | /* 102551 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36602 | /* 102555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36603 | /* 102559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36604 | /* 102563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36605 | /* 102567 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 36606 | /* 102571 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 36607 | /* 102575 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 36608 | /* 102575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 36609 | /* 102578 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36610 | /* 102580 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36611 | /* 102582 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36612 | /* 102584 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36613 | /* 102588 */ GIR_RootConstrainSelectedInstOperands, |
| 36614 | /* 102589 */ // GIR_Coverage, 5546, |
| 36615 | /* 102589 */ GIR_EraseRootFromParent_Done, |
| 36616 | /* 102590 */ // Label 1888: @102590 |
| 36617 | /* 102590 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(102651), // Rule ID 5549 // |
| 36618 | /* 102595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36619 | /* 102600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36620 | /* 102603 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 36621 | /* 102606 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36622 | /* 102609 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36623 | /* 102612 */ // MIs[0] base |
| 36624 | /* 102612 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36625 | /* 102616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36626 | /* 102620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36627 | /* 102624 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36628 | /* 102628 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 36629 | /* 102632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36630 | /* 102636 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 36631 | /* 102636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u), |
| 36632 | /* 102639 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36633 | /* 102641 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36634 | /* 102643 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36635 | /* 102645 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36636 | /* 102649 */ GIR_RootConstrainSelectedInstOperands, |
| 36637 | /* 102650 */ // GIR_Coverage, 5549, |
| 36638 | /* 102650 */ GIR_EraseRootFromParent_Done, |
| 36639 | /* 102651 */ // Label 1889: @102651 |
| 36640 | /* 102651 */ GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(102712), // Rule ID 5550 // |
| 36641 | /* 102656 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36642 | /* 102661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36643 | /* 102664 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 36644 | /* 102667 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36645 | /* 102670 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36646 | /* 102673 */ // MIs[0] base |
| 36647 | /* 102673 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36648 | /* 102677 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36649 | /* 102681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36650 | /* 102685 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36651 | /* 102689 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 36652 | /* 102693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 36653 | /* 102697 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 36654 | /* 102697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq), |
| 36655 | /* 102700 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36656 | /* 102702 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36657 | /* 102704 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36658 | /* 102706 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36659 | /* 102710 */ GIR_RootConstrainSelectedInstOperands, |
| 36660 | /* 102711 */ // GIR_Coverage, 5550, |
| 36661 | /* 102711 */ GIR_EraseRootFromParent_Done, |
| 36662 | /* 102712 */ // Label 1890: @102712 |
| 36663 | /* 102712 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(102773), // Rule ID 5553 // |
| 36664 | /* 102717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36665 | /* 102722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36666 | /* 102725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 36667 | /* 102728 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36668 | /* 102731 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36669 | /* 102734 */ // MIs[0] base |
| 36670 | /* 102734 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36671 | /* 102738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36672 | /* 102742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36673 | /* 102746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36674 | /* 102750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 36675 | /* 102754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36676 | /* 102758 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 36677 | /* 102758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 36678 | /* 102761 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36679 | /* 102763 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36680 | /* 102765 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36681 | /* 102767 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36682 | /* 102771 */ GIR_RootConstrainSelectedInstOperands, |
| 36683 | /* 102772 */ // GIR_Coverage, 5553, |
| 36684 | /* 102772 */ GIR_EraseRootFromParent_Done, |
| 36685 | /* 102773 */ // Label 1891: @102773 |
| 36686 | /* 102773 */ GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(102834), // Rule ID 5554 // |
| 36687 | /* 102778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36688 | /* 102783 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36689 | /* 102786 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 36690 | /* 102789 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36691 | /* 102792 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36692 | /* 102795 */ // MIs[0] base |
| 36693 | /* 102795 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36694 | /* 102799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36695 | /* 102803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36696 | /* 102807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36697 | /* 102811 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 36698 | /* 102815 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 36699 | /* 102819 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 36700 | /* 102819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 36701 | /* 102822 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36702 | /* 102824 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36703 | /* 102826 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36704 | /* 102828 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36705 | /* 102832 */ GIR_RootConstrainSelectedInstOperands, |
| 36706 | /* 102833 */ // GIR_Coverage, 5554, |
| 36707 | /* 102833 */ GIR_EraseRootFromParent_Done, |
| 36708 | /* 102834 */ // Label 1892: @102834 |
| 36709 | /* 102834 */ GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(102895), // Rule ID 5557 // |
| 36710 | /* 102839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36711 | /* 102844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36712 | /* 102847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 36713 | /* 102850 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36714 | /* 102853 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36715 | /* 102856 */ // MIs[0] base |
| 36716 | /* 102856 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36717 | /* 102860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36718 | /* 102864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36719 | /* 102868 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36720 | /* 102872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 36721 | /* 102876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36722 | /* 102880 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 36723 | /* 102880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 36724 | /* 102883 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36725 | /* 102885 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36726 | /* 102887 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36727 | /* 102889 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36728 | /* 102893 */ GIR_RootConstrainSelectedInstOperands, |
| 36729 | /* 102894 */ // GIR_Coverage, 5557, |
| 36730 | /* 102894 */ GIR_EraseRootFromParent_Done, |
| 36731 | /* 102895 */ // Label 1893: @102895 |
| 36732 | /* 102895 */ GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(102956), // Rule ID 5558 // |
| 36733 | /* 102900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36734 | /* 102905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36735 | /* 102908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 36736 | /* 102911 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36737 | /* 102914 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36738 | /* 102917 */ // MIs[0] base |
| 36739 | /* 102917 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36740 | /* 102921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36741 | /* 102925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36742 | /* 102929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36743 | /* 102933 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 36744 | /* 102937 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 36745 | /* 102941 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 36746 | /* 102941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 36747 | /* 102944 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36748 | /* 102946 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36749 | /* 102948 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36750 | /* 102950 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36751 | /* 102954 */ GIR_RootConstrainSelectedInstOperands, |
| 36752 | /* 102955 */ // GIR_Coverage, 5558, |
| 36753 | /* 102955 */ GIR_EraseRootFromParent_Done, |
| 36754 | /* 102956 */ // Label 1894: @102956 |
| 36755 | /* 102956 */ GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(103017), // Rule ID 5561 // |
| 36756 | /* 102961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36757 | /* 102966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36758 | /* 102969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 36759 | /* 102972 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36760 | /* 102975 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36761 | /* 102978 */ // MIs[0] base |
| 36762 | /* 102978 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36763 | /* 102982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36764 | /* 102986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36765 | /* 102990 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36766 | /* 102994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 36767 | /* 102998 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 36768 | /* 103002 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 36769 | /* 103002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u), |
| 36770 | /* 103005 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36771 | /* 103007 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36772 | /* 103009 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36773 | /* 103011 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36774 | /* 103015 */ GIR_RootConstrainSelectedInstOperands, |
| 36775 | /* 103016 */ // GIR_Coverage, 5561, |
| 36776 | /* 103016 */ GIR_EraseRootFromParent_Done, |
| 36777 | /* 103017 */ // Label 1895: @103017 |
| 36778 | /* 103017 */ GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(103078), // Rule ID 5562 // |
| 36779 | /* 103022 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 36780 | /* 103027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36781 | /* 103030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 36782 | /* 103033 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36783 | /* 103036 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 36784 | /* 103039 */ // MIs[0] base |
| 36785 | /* 103039 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36786 | /* 103043 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36787 | /* 103047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36788 | /* 103051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36789 | /* 103055 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 36790 | /* 103059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 36791 | /* 103063 */ // (intrinsic_void 3973:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 36792 | /* 103063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq), |
| 36793 | /* 103066 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 36794 | /* 103068 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 36795 | /* 103070 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 36796 | /* 103072 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36797 | /* 103076 */ GIR_RootConstrainSelectedInstOperands, |
| 36798 | /* 103077 */ // GIR_Coverage, 5562, |
| 36799 | /* 103077 */ GIR_EraseRootFromParent_Done, |
| 36800 | /* 103078 */ // Label 1896: @103078 |
| 36801 | /* 103078 */ GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(103142), // Rule ID 257 // |
| 36802 | /* 103083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 36803 | /* 103086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 36804 | /* 103091 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36805 | /* 103094 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36806 | /* 103097 */ // MIs[0] cop |
| 36807 | /* 103097 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 36808 | /* 103100 */ // MIs[0] opc1 |
| 36809 | /* 103100 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 36810 | /* 103103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36811 | /* 103107 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36812 | /* 103111 */ // MIs[0] CRm |
| 36813 | /* 103111 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 36814 | /* 103114 */ // (intrinsic_void 3758:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 36815 | /* 103114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR), |
| 36816 | /* 103117 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 36817 | /* 103119 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 36818 | /* 103121 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 36819 | /* 103123 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 36820 | /* 103125 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 36821 | /* 103127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36822 | /* 103130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36823 | /* 103136 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36824 | /* 103140 */ GIR_RootConstrainSelectedInstOperands, |
| 36825 | /* 103141 */ // GIR_Coverage, 257, |
| 36826 | /* 103141 */ GIR_EraseRootFromParent_Done, |
| 36827 | /* 103142 */ // Label 1897: @103142 |
| 36828 | /* 103142 */ GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(103197), // Rule ID 258 // |
| 36829 | /* 103147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 36830 | /* 103150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 36831 | /* 103155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36832 | /* 103158 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36833 | /* 103161 */ // MIs[0] cop |
| 36834 | /* 103161 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 36835 | /* 103164 */ // MIs[0] opc1 |
| 36836 | /* 103164 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 36837 | /* 103167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36838 | /* 103171 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36839 | /* 103175 */ // MIs[0] CRm |
| 36840 | /* 103175 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 36841 | /* 103178 */ // (intrinsic_void 3759:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 36842 | /* 103178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2), |
| 36843 | /* 103181 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 36844 | /* 103183 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 36845 | /* 103185 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 36846 | /* 103187 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 36847 | /* 103189 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 36848 | /* 103191 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36849 | /* 103195 */ GIR_RootConstrainSelectedInstOperands, |
| 36850 | /* 103196 */ // GIR_Coverage, 258, |
| 36851 | /* 103196 */ GIR_EraseRootFromParent_Done, |
| 36852 | /* 103197 */ // Label 1898: @103197 |
| 36853 | /* 103197 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(103261), // Rule ID 595 // |
| 36854 | /* 103202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36855 | /* 103205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 36856 | /* 103210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36857 | /* 103213 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36858 | /* 103216 */ // MIs[0] cop |
| 36859 | /* 103216 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 36860 | /* 103219 */ // MIs[0] opc1 |
| 36861 | /* 103219 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 36862 | /* 103222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36863 | /* 103226 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36864 | /* 103230 */ // MIs[0] CRm |
| 36865 | /* 103230 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 36866 | /* 103233 */ // (intrinsic_void 3758:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 36867 | /* 103233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR), |
| 36868 | /* 103236 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 36869 | /* 103238 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 36870 | /* 103240 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 36871 | /* 103242 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 36872 | /* 103244 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 36873 | /* 103246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36874 | /* 103249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36875 | /* 103255 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36876 | /* 103259 */ GIR_RootConstrainSelectedInstOperands, |
| 36877 | /* 103260 */ // GIR_Coverage, 595, |
| 36878 | /* 103260 */ GIR_EraseRootFromParent_Done, |
| 36879 | /* 103261 */ // Label 1899: @103261 |
| 36880 | /* 103261 */ GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(103325), // Rule ID 596 // |
| 36881 | /* 103266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 36882 | /* 103269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 36883 | /* 103274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 36884 | /* 103277 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 36885 | /* 103280 */ // MIs[0] cop |
| 36886 | /* 103280 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 36887 | /* 103283 */ // MIs[0] opc1 |
| 36888 | /* 103283 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 36889 | /* 103286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36890 | /* 103290 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36891 | /* 103294 */ // MIs[0] CRm |
| 36892 | /* 103294 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 36893 | /* 103297 */ // (intrinsic_void 3759:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 36894 | /* 103297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2), |
| 36895 | /* 103300 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 36896 | /* 103302 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 36897 | /* 103304 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 36898 | /* 103306 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 36899 | /* 103308 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 36900 | /* 103310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36901 | /* 103313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36902 | /* 103319 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36903 | /* 103323 */ GIR_RootConstrainSelectedInstOperands, |
| 36904 | /* 103324 */ // GIR_Coverage, 596, |
| 36905 | /* 103324 */ GIR_EraseRootFromParent_Done, |
| 36906 | /* 103325 */ // Label 1900: @103325 |
| 36907 | /* 103325 */ GIM_Reject, |
| 36908 | /* 103326 */ // Label 1881: @103326 |
| 36909 | /* 103326 */ GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(106677), |
| 36910 | /* 103331 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 36911 | /* 103334 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(103395), // Rule ID 245 // |
| 36912 | /* 103339 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 36913 | /* 103342 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 36914 | /* 103347 */ // MIs[0] cop |
| 36915 | /* 103347 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 36916 | /* 103350 */ // MIs[0] opc1 |
| 36917 | /* 103350 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 36918 | /* 103353 */ // MIs[0] CRd |
| 36919 | /* 103353 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 36920 | /* 103356 */ // MIs[0] CRn |
| 36921 | /* 103356 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 36922 | /* 103359 */ // MIs[0] CRm |
| 36923 | /* 103359 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 36924 | /* 103362 */ // MIs[0] opc2 |
| 36925 | /* 103362 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 36926 | /* 103365 */ // (intrinsic_void 3726:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 36927 | /* 103365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP), |
| 36928 | /* 103368 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 36929 | /* 103370 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 36930 | /* 103372 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 36931 | /* 103374 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 36932 | /* 103376 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 36933 | /* 103378 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 36934 | /* 103380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36935 | /* 103383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36936 | /* 103389 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36937 | /* 103393 */ GIR_RootConstrainSelectedInstOperands, |
| 36938 | /* 103394 */ // GIR_Coverage, 245, |
| 36939 | /* 103394 */ GIR_EraseRootFromParent_Done, |
| 36940 | /* 103395 */ // Label 1902: @103395 |
| 36941 | /* 103395 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(103447), // Rule ID 246 // |
| 36942 | /* 103400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 36943 | /* 103403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 36944 | /* 103408 */ // MIs[0] cop |
| 36945 | /* 103408 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 36946 | /* 103411 */ // MIs[0] opc1 |
| 36947 | /* 103411 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 36948 | /* 103414 */ // MIs[0] CRd |
| 36949 | /* 103414 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 36950 | /* 103417 */ // MIs[0] CRn |
| 36951 | /* 103417 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 36952 | /* 103420 */ // MIs[0] CRm |
| 36953 | /* 103420 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 36954 | /* 103423 */ // MIs[0] opc2 |
| 36955 | /* 103423 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 36956 | /* 103426 */ // (intrinsic_void 3727:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 36957 | /* 103426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2), |
| 36958 | /* 103429 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 36959 | /* 103431 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 36960 | /* 103433 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 36961 | /* 103435 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 36962 | /* 103437 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 36963 | /* 103439 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 36964 | /* 103441 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36965 | /* 103445 */ GIR_RootConstrainSelectedInstOperands, |
| 36966 | /* 103446 */ // GIR_Coverage, 246, |
| 36967 | /* 103446 */ GIR_EraseRootFromParent_Done, |
| 36968 | /* 103447 */ // Label 1903: @103447 |
| 36969 | /* 103447 */ GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(103508), // Rule ID 597 // |
| 36970 | /* 103452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 36971 | /* 103455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 36972 | /* 103460 */ // MIs[0] cop |
| 36973 | /* 103460 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 36974 | /* 103463 */ // MIs[0] opc1 |
| 36975 | /* 103463 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 36976 | /* 103466 */ // MIs[0] CRd |
| 36977 | /* 103466 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 36978 | /* 103469 */ // MIs[0] CRn |
| 36979 | /* 103469 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 36980 | /* 103472 */ // MIs[0] CRm |
| 36981 | /* 103472 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 36982 | /* 103475 */ // MIs[0] opc2 |
| 36983 | /* 103475 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 36984 | /* 103478 */ // (intrinsic_void 3726:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 36985 | /* 103478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP), |
| 36986 | /* 103481 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 36987 | /* 103483 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 36988 | /* 103485 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 36989 | /* 103487 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 36990 | /* 103489 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 36991 | /* 103491 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 36992 | /* 103493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36993 | /* 103496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36994 | /* 103502 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36995 | /* 103506 */ GIR_RootConstrainSelectedInstOperands, |
| 36996 | /* 103507 */ // GIR_Coverage, 597, |
| 36997 | /* 103507 */ GIR_EraseRootFromParent_Done, |
| 36998 | /* 103508 */ // Label 1904: @103508 |
| 36999 | /* 103508 */ GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(103569), // Rule ID 598 // |
| 37000 | /* 103513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 37001 | /* 103516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 37002 | /* 103521 */ // MIs[0] cop |
| 37003 | /* 103521 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 37004 | /* 103524 */ // MIs[0] opc1 |
| 37005 | /* 103524 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 37006 | /* 103527 */ // MIs[0] CRd |
| 37007 | /* 103527 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 37008 | /* 103530 */ // MIs[0] CRn |
| 37009 | /* 103530 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 37010 | /* 103533 */ // MIs[0] CRm |
| 37011 | /* 103533 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 37012 | /* 103536 */ // MIs[0] opc2 |
| 37013 | /* 103536 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 37014 | /* 103539 */ // (intrinsic_void 3727:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 37015 | /* 103539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2), |
| 37016 | /* 103542 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 37017 | /* 103544 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 37018 | /* 103546 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 37019 | /* 103548 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 37020 | /* 103550 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 37021 | /* 103552 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 37022 | /* 103554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37023 | /* 103557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37024 | /* 103563 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37025 | /* 103567 */ GIR_RootConstrainSelectedInstOperands, |
| 37026 | /* 103568 */ // GIR_Coverage, 598, |
| 37027 | /* 103568 */ GIR_EraseRootFromParent_Done, |
| 37028 | /* 103569 */ // Label 1905: @103569 |
| 37029 | /* 103569 */ GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(103637), // Rule ID 5451 // |
| 37030 | /* 103574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37031 | /* 103579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37032 | /* 103582 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37033 | /* 103585 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37034 | /* 103588 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37035 | /* 103591 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37036 | /* 103594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37037 | /* 103598 */ // MIs[0] base |
| 37038 | /* 103598 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37039 | /* 103602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37040 | /* 103606 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37041 | /* 103610 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37042 | /* 103614 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37043 | /* 103618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37044 | /* 103622 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37045 | /* 103622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 37046 | /* 103625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37047 | /* 103627 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37048 | /* 103629 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37049 | /* 103631 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37050 | /* 103635 */ GIR_RootConstrainSelectedInstOperands, |
| 37051 | /* 103636 */ // GIR_Coverage, 5451, |
| 37052 | /* 103636 */ GIR_EraseRootFromParent_Done, |
| 37053 | /* 103637 */ // Label 1906: @103637 |
| 37054 | /* 103637 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(103705), // Rule ID 5452 // |
| 37055 | /* 103642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37056 | /* 103647 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37057 | /* 103650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37058 | /* 103653 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37059 | /* 103656 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37060 | /* 103659 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37061 | /* 103662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37062 | /* 103666 */ // MIs[0] base |
| 37063 | /* 103666 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37064 | /* 103670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37065 | /* 103674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37066 | /* 103678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37067 | /* 103682 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37068 | /* 103686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37069 | /* 103690 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37070 | /* 103690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 37071 | /* 103693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37072 | /* 103695 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37073 | /* 103697 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37074 | /* 103699 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37075 | /* 103703 */ GIR_RootConstrainSelectedInstOperands, |
| 37076 | /* 103704 */ // GIR_Coverage, 5452, |
| 37077 | /* 103704 */ GIR_EraseRootFromParent_Done, |
| 37078 | /* 103705 */ // Label 1907: @103705 |
| 37079 | /* 103705 */ GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(103773), // Rule ID 5455 // |
| 37080 | /* 103710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37081 | /* 103715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 37082 | /* 103718 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 37083 | /* 103721 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37084 | /* 103724 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37085 | /* 103727 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37086 | /* 103730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37087 | /* 103734 */ // MIs[0] base |
| 37088 | /* 103734 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37089 | /* 103738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37090 | /* 103742 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37091 | /* 103746 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 37092 | /* 103750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37093 | /* 103754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37094 | /* 103758 */ // (intrinsic_w_chain:{ *:[v16i8] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 37095 | /* 103758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 37096 | /* 103761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37097 | /* 103763 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37098 | /* 103765 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37099 | /* 103767 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37100 | /* 103771 */ GIR_RootConstrainSelectedInstOperands, |
| 37101 | /* 103772 */ // GIR_Coverage, 5455, |
| 37102 | /* 103772 */ GIR_EraseRootFromParent_Done, |
| 37103 | /* 103773 */ // Label 1908: @103773 |
| 37104 | /* 103773 */ GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(103841), // Rule ID 5463 // |
| 37105 | /* 103778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37106 | /* 103783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 37107 | /* 103786 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 37108 | /* 103789 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37109 | /* 103792 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37110 | /* 103795 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37111 | /* 103798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37112 | /* 103802 */ // MIs[0] base |
| 37113 | /* 103802 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37114 | /* 103806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37115 | /* 103810 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37116 | /* 103814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 37117 | /* 103818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37118 | /* 103822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37119 | /* 103826 */ // (intrinsic_w_chain:{ *:[v16i8] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 37120 | /* 103826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 37121 | /* 103829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37122 | /* 103831 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37123 | /* 103833 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37124 | /* 103835 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37125 | /* 103839 */ GIR_RootConstrainSelectedInstOperands, |
| 37126 | /* 103840 */ // GIR_Coverage, 5463, |
| 37127 | /* 103840 */ GIR_EraseRootFromParent_Done, |
| 37128 | /* 103841 */ // Label 1909: @103841 |
| 37129 | /* 103841 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(103909), // Rule ID 5465 // |
| 37130 | /* 103846 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37131 | /* 103851 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37132 | /* 103854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37133 | /* 103857 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37134 | /* 103860 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37135 | /* 103863 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37136 | /* 103866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37137 | /* 103870 */ // MIs[0] base |
| 37138 | /* 103870 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37139 | /* 103874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37140 | /* 103878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37141 | /* 103882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 37142 | /* 103886 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37143 | /* 103890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37144 | /* 103894 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37145 | /* 103894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq), |
| 37146 | /* 103897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37147 | /* 103899 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37148 | /* 103901 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37149 | /* 103903 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37150 | /* 103907 */ GIR_RootConstrainSelectedInstOperands, |
| 37151 | /* 103908 */ // GIR_Coverage, 5465, |
| 37152 | /* 103908 */ GIR_EraseRootFromParent_Done, |
| 37153 | /* 103909 */ // Label 1910: @103909 |
| 37154 | /* 103909 */ GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(103977), // Rule ID 5467 // |
| 37155 | /* 103914 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37156 | /* 103919 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37157 | /* 103922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37158 | /* 103925 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37159 | /* 103928 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37160 | /* 103931 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37161 | /* 103934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37162 | /* 103938 */ // MIs[0] base |
| 37163 | /* 103938 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37164 | /* 103942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37165 | /* 103946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37166 | /* 103950 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 37167 | /* 103954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37168 | /* 103958 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37169 | /* 103962 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37170 | /* 103962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq), |
| 37171 | /* 103965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37172 | /* 103967 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37173 | /* 103969 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37174 | /* 103971 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37175 | /* 103975 */ GIR_RootConstrainSelectedInstOperands, |
| 37176 | /* 103976 */ // GIR_Coverage, 5467, |
| 37177 | /* 103976 */ GIR_EraseRootFromParent_Done, |
| 37178 | /* 103977 */ // Label 1911: @103977 |
| 37179 | /* 103977 */ GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(104045), // Rule ID 5469 // |
| 37180 | /* 103982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37181 | /* 103987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37182 | /* 103990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37183 | /* 103993 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37184 | /* 103996 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37185 | /* 103999 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37186 | /* 104002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37187 | /* 104006 */ // MIs[0] base |
| 37188 | /* 104006 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37189 | /* 104010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37190 | /* 104014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37191 | /* 104018 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 37192 | /* 104022 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37193 | /* 104026 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37194 | /* 104030 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37195 | /* 104030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq), |
| 37196 | /* 104033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37197 | /* 104035 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37198 | /* 104037 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37199 | /* 104039 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37200 | /* 104043 */ GIR_RootConstrainSelectedInstOperands, |
| 37201 | /* 104044 */ // GIR_Coverage, 5469, |
| 37202 | /* 104044 */ GIR_EraseRootFromParent_Done, |
| 37203 | /* 104045 */ // Label 1912: @104045 |
| 37204 | /* 104045 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(104113), // Rule ID 5471 // |
| 37205 | /* 104050 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37206 | /* 104055 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37207 | /* 104058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37208 | /* 104061 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37209 | /* 104064 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37210 | /* 104067 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37211 | /* 104070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37212 | /* 104074 */ // MIs[0] base |
| 37213 | /* 104074 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37214 | /* 104078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37215 | /* 104082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37216 | /* 104086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 37217 | /* 104090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37218 | /* 104094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37219 | /* 104098 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37220 | /* 104098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq), |
| 37221 | /* 104101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37222 | /* 104103 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37223 | /* 104105 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37224 | /* 104107 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37225 | /* 104111 */ GIR_RootConstrainSelectedInstOperands, |
| 37226 | /* 104112 */ // GIR_Coverage, 5471, |
| 37227 | /* 104112 */ GIR_EraseRootFromParent_Done, |
| 37228 | /* 104113 */ // Label 1913: @104113 |
| 37229 | /* 104113 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(104181), // Rule ID 5473 // |
| 37230 | /* 104118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37231 | /* 104123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37232 | /* 104126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37233 | /* 104129 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37234 | /* 104132 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37235 | /* 104135 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37236 | /* 104138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37237 | /* 104142 */ // MIs[0] base |
| 37238 | /* 104142 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37239 | /* 104146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37240 | /* 104150 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37241 | /* 104154 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37242 | /* 104158 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37243 | /* 104162 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37244 | /* 104166 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37245 | /* 104166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 37246 | /* 104169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37247 | /* 104171 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37248 | /* 104173 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37249 | /* 104175 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37250 | /* 104179 */ GIR_RootConstrainSelectedInstOperands, |
| 37251 | /* 104180 */ // GIR_Coverage, 5473, |
| 37252 | /* 104180 */ GIR_EraseRootFromParent_Done, |
| 37253 | /* 104181 */ // Label 1914: @104181 |
| 37254 | /* 104181 */ GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(104249), // Rule ID 5474 // |
| 37255 | /* 104186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37256 | /* 104191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37257 | /* 104194 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37258 | /* 104197 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37259 | /* 104200 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37260 | /* 104203 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37261 | /* 104206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37262 | /* 104210 */ // MIs[0] base |
| 37263 | /* 104210 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37264 | /* 104214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37265 | /* 104218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37266 | /* 104222 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37267 | /* 104226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37268 | /* 104230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37269 | /* 104234 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37270 | /* 104234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 37271 | /* 104237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37272 | /* 104239 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37273 | /* 104241 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37274 | /* 104243 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37275 | /* 104247 */ GIR_RootConstrainSelectedInstOperands, |
| 37276 | /* 104248 */ // GIR_Coverage, 5474, |
| 37277 | /* 104248 */ GIR_EraseRootFromParent_Done, |
| 37278 | /* 104249 */ // Label 1915: @104249 |
| 37279 | /* 104249 */ GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(104317), // Rule ID 5477 // |
| 37280 | /* 104254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37281 | /* 104259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37282 | /* 104262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37283 | /* 104265 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37284 | /* 104268 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37285 | /* 104271 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37286 | /* 104274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37287 | /* 104278 */ // MIs[0] base |
| 37288 | /* 104278 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37289 | /* 104282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37290 | /* 104286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37291 | /* 104290 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37292 | /* 104294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37293 | /* 104298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37294 | /* 104302 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37295 | /* 104302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 37296 | /* 104305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37297 | /* 104307 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37298 | /* 104309 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37299 | /* 104311 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37300 | /* 104315 */ GIR_RootConstrainSelectedInstOperands, |
| 37301 | /* 104316 */ // GIR_Coverage, 5477, |
| 37302 | /* 104316 */ GIR_EraseRootFromParent_Done, |
| 37303 | /* 104317 */ // Label 1916: @104317 |
| 37304 | /* 104317 */ GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(104385), // Rule ID 5478 // |
| 37305 | /* 104322 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37306 | /* 104327 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37307 | /* 104330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37308 | /* 104333 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37309 | /* 104336 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37310 | /* 104339 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37311 | /* 104342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37312 | /* 104346 */ // MIs[0] base |
| 37313 | /* 104346 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37314 | /* 104350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37315 | /* 104354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37316 | /* 104358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37317 | /* 104362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37318 | /* 104366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37319 | /* 104370 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37320 | /* 104370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 37321 | /* 104373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37322 | /* 104375 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37323 | /* 104377 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37324 | /* 104379 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37325 | /* 104383 */ GIR_RootConstrainSelectedInstOperands, |
| 37326 | /* 104384 */ // GIR_Coverage, 5478, |
| 37327 | /* 104384 */ GIR_EraseRootFromParent_Done, |
| 37328 | /* 104385 */ // Label 1917: @104385 |
| 37329 | /* 104385 */ GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(104453), // Rule ID 5481 // |
| 37330 | /* 104390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37331 | /* 104395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37332 | /* 104398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37333 | /* 104401 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37334 | /* 104404 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37335 | /* 104407 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37336 | /* 104410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37337 | /* 104414 */ // MIs[0] base |
| 37338 | /* 104414 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37339 | /* 104418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37340 | /* 104422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37341 | /* 104426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37342 | /* 104430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37343 | /* 104434 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37344 | /* 104438 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37345 | /* 104438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 37346 | /* 104441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37347 | /* 104443 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37348 | /* 104445 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37349 | /* 104447 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37350 | /* 104451 */ GIR_RootConstrainSelectedInstOperands, |
| 37351 | /* 104452 */ // GIR_Coverage, 5481, |
| 37352 | /* 104452 */ GIR_EraseRootFromParent_Done, |
| 37353 | /* 104453 */ // Label 1918: @104453 |
| 37354 | /* 104453 */ GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(104521), // Rule ID 5482 // |
| 37355 | /* 104458 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37356 | /* 104463 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37357 | /* 104466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37358 | /* 104469 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37359 | /* 104472 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37360 | /* 104475 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37361 | /* 104478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37362 | /* 104482 */ // MIs[0] base |
| 37363 | /* 104482 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37364 | /* 104486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37365 | /* 104490 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37366 | /* 104494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37367 | /* 104498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37368 | /* 104502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37369 | /* 104506 */ // (intrinsic_w_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37370 | /* 104506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 37371 | /* 104509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37372 | /* 104511 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37373 | /* 104513 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37374 | /* 104515 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37375 | /* 104519 */ GIR_RootConstrainSelectedInstOperands, |
| 37376 | /* 104520 */ // GIR_Coverage, 5482, |
| 37377 | /* 104520 */ GIR_EraseRootFromParent_Done, |
| 37378 | /* 104521 */ // Label 1919: @104521 |
| 37379 | /* 104521 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(104589), // Rule ID 5485 // |
| 37380 | /* 104526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37381 | /* 104531 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37382 | /* 104534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37383 | /* 104537 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37384 | /* 104540 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37385 | /* 104543 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37386 | /* 104546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37387 | /* 104550 */ // MIs[0] base |
| 37388 | /* 104550 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37389 | /* 104554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37390 | /* 104558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37391 | /* 104562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37392 | /* 104566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37393 | /* 104570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37394 | /* 104574 */ // (intrinsic_w_chain:{ *:[v8f16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37395 | /* 104574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 37396 | /* 104577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37397 | /* 104579 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37398 | /* 104581 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37399 | /* 104583 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37400 | /* 104587 */ GIR_RootConstrainSelectedInstOperands, |
| 37401 | /* 104588 */ // GIR_Coverage, 5485, |
| 37402 | /* 104588 */ GIR_EraseRootFromParent_Done, |
| 37403 | /* 104589 */ // Label 1920: @104589 |
| 37404 | /* 104589 */ GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(104657), // Rule ID 5486 // |
| 37405 | /* 104594 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37406 | /* 104599 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37407 | /* 104602 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37408 | /* 104605 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37409 | /* 104608 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37410 | /* 104611 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37411 | /* 104614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37412 | /* 104618 */ // MIs[0] base |
| 37413 | /* 104618 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37414 | /* 104622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37415 | /* 104626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37416 | /* 104630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37417 | /* 104634 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37418 | /* 104638 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37419 | /* 104642 */ // (intrinsic_w_chain:{ *:[v8f16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37420 | /* 104642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 37421 | /* 104645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37422 | /* 104647 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37423 | /* 104649 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37424 | /* 104651 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37425 | /* 104655 */ GIR_RootConstrainSelectedInstOperands, |
| 37426 | /* 104656 */ // GIR_Coverage, 5486, |
| 37427 | /* 104656 */ GIR_EraseRootFromParent_Done, |
| 37428 | /* 104657 */ // Label 1921: @104657 |
| 37429 | /* 104657 */ GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(104725), // Rule ID 5489 // |
| 37430 | /* 104662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37431 | /* 104667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37432 | /* 104670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37433 | /* 104673 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37434 | /* 104676 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37435 | /* 104679 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37436 | /* 104682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37437 | /* 104686 */ // MIs[0] base |
| 37438 | /* 104686 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37439 | /* 104690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37440 | /* 104694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37441 | /* 104698 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37442 | /* 104702 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37443 | /* 104706 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37444 | /* 104710 */ // (intrinsic_w_chain:{ *:[v8f16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37445 | /* 104710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 37446 | /* 104713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37447 | /* 104715 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37448 | /* 104717 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37449 | /* 104719 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37450 | /* 104723 */ GIR_RootConstrainSelectedInstOperands, |
| 37451 | /* 104724 */ // GIR_Coverage, 5489, |
| 37452 | /* 104724 */ GIR_EraseRootFromParent_Done, |
| 37453 | /* 104725 */ // Label 1922: @104725 |
| 37454 | /* 104725 */ GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(104793), // Rule ID 5490 // |
| 37455 | /* 104730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37456 | /* 104735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 37457 | /* 104738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 37458 | /* 104741 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37459 | /* 104744 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37460 | /* 104747 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37461 | /* 104750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37462 | /* 104754 */ // MIs[0] base |
| 37463 | /* 104754 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37464 | /* 104758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37465 | /* 104762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37466 | /* 104766 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37467 | /* 104770 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37468 | /* 104774 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37469 | /* 104778 */ // (intrinsic_w_chain:{ *:[v8f16] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 37470 | /* 104778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 37471 | /* 104781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37472 | /* 104783 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37473 | /* 104785 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37474 | /* 104787 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37475 | /* 104791 */ GIR_RootConstrainSelectedInstOperands, |
| 37476 | /* 104792 */ // GIR_Coverage, 5490, |
| 37477 | /* 104792 */ GIR_EraseRootFromParent_Done, |
| 37478 | /* 104793 */ // Label 1923: @104793 |
| 37479 | /* 104793 */ GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(104861), // Rule ID 5493 // |
| 37480 | /* 104798 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37481 | /* 104803 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37482 | /* 104806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37483 | /* 104809 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37484 | /* 104812 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37485 | /* 104815 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37486 | /* 104818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37487 | /* 104822 */ // MIs[0] base |
| 37488 | /* 104822 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37489 | /* 104826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37490 | /* 104830 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37491 | /* 104834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37492 | /* 104838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37493 | /* 104842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37494 | /* 104846 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37495 | /* 104846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u), |
| 37496 | /* 104849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37497 | /* 104851 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37498 | /* 104853 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37499 | /* 104855 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37500 | /* 104859 */ GIR_RootConstrainSelectedInstOperands, |
| 37501 | /* 104860 */ // GIR_Coverage, 5493, |
| 37502 | /* 104860 */ GIR_EraseRootFromParent_Done, |
| 37503 | /* 104861 */ // Label 1924: @104861 |
| 37504 | /* 104861 */ GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(104929), // Rule ID 5494 // |
| 37505 | /* 104866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37506 | /* 104871 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37507 | /* 104874 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37508 | /* 104877 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37509 | /* 104880 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37510 | /* 104883 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37511 | /* 104886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37512 | /* 104890 */ // MIs[0] base |
| 37513 | /* 104890 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37514 | /* 104894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37515 | /* 104898 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37516 | /* 104902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37517 | /* 104906 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37518 | /* 104910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37519 | /* 104914 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37520 | /* 104914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq), |
| 37521 | /* 104917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37522 | /* 104919 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37523 | /* 104921 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37524 | /* 104923 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37525 | /* 104927 */ GIR_RootConstrainSelectedInstOperands, |
| 37526 | /* 104928 */ // GIR_Coverage, 5494, |
| 37527 | /* 104928 */ GIR_EraseRootFromParent_Done, |
| 37528 | /* 104929 */ // Label 1925: @104929 |
| 37529 | /* 104929 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(104997), // Rule ID 5497 // |
| 37530 | /* 104934 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37531 | /* 104939 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37532 | /* 104942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37533 | /* 104945 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37534 | /* 104948 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37535 | /* 104951 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37536 | /* 104954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37537 | /* 104958 */ // MIs[0] base |
| 37538 | /* 104958 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37539 | /* 104962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37540 | /* 104966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37541 | /* 104970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37542 | /* 104974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37543 | /* 104978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37544 | /* 104982 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37545 | /* 104982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u), |
| 37546 | /* 104985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37547 | /* 104987 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37548 | /* 104989 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37549 | /* 104991 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37550 | /* 104995 */ GIR_RootConstrainSelectedInstOperands, |
| 37551 | /* 104996 */ // GIR_Coverage, 5497, |
| 37552 | /* 104996 */ GIR_EraseRootFromParent_Done, |
| 37553 | /* 104997 */ // Label 1926: @104997 |
| 37554 | /* 104997 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(105065), // Rule ID 5498 // |
| 37555 | /* 105002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37556 | /* 105007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37557 | /* 105010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37558 | /* 105013 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37559 | /* 105016 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37560 | /* 105019 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37561 | /* 105022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37562 | /* 105026 */ // MIs[0] base |
| 37563 | /* 105026 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37564 | /* 105030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37565 | /* 105034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37566 | /* 105038 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 37567 | /* 105042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 37568 | /* 105046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37569 | /* 105050 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37570 | /* 105050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq), |
| 37571 | /* 105053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37572 | /* 105055 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37573 | /* 105057 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37574 | /* 105059 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37575 | /* 105063 */ GIR_RootConstrainSelectedInstOperands, |
| 37576 | /* 105064 */ // GIR_Coverage, 5498, |
| 37577 | /* 105064 */ GIR_EraseRootFromParent_Done, |
| 37578 | /* 105065 */ // Label 1927: @105065 |
| 37579 | /* 105065 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(105133), // Rule ID 5501 // |
| 37580 | /* 105070 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37581 | /* 105075 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37582 | /* 105078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37583 | /* 105081 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37584 | /* 105084 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37585 | /* 105087 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37586 | /* 105090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37587 | /* 105094 */ // MIs[0] base |
| 37588 | /* 105094 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37589 | /* 105098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37590 | /* 105102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37591 | /* 105106 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37592 | /* 105110 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37593 | /* 105114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37594 | /* 105118 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37595 | /* 105118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 37596 | /* 105121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37597 | /* 105123 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37598 | /* 105125 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37599 | /* 105127 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37600 | /* 105131 */ GIR_RootConstrainSelectedInstOperands, |
| 37601 | /* 105132 */ // GIR_Coverage, 5501, |
| 37602 | /* 105132 */ GIR_EraseRootFromParent_Done, |
| 37603 | /* 105133 */ // Label 1928: @105133 |
| 37604 | /* 105133 */ GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(105201), // Rule ID 5502 // |
| 37605 | /* 105138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37606 | /* 105143 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37607 | /* 105146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37608 | /* 105149 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37609 | /* 105152 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37610 | /* 105155 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37611 | /* 105158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37612 | /* 105162 */ // MIs[0] base |
| 37613 | /* 105162 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37614 | /* 105166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37615 | /* 105170 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37616 | /* 105174 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37617 | /* 105178 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 37618 | /* 105182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37619 | /* 105186 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37620 | /* 105186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 37621 | /* 105189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37622 | /* 105191 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37623 | /* 105193 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37624 | /* 105195 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37625 | /* 105199 */ GIR_RootConstrainSelectedInstOperands, |
| 37626 | /* 105200 */ // GIR_Coverage, 5502, |
| 37627 | /* 105200 */ GIR_EraseRootFromParent_Done, |
| 37628 | /* 105201 */ // Label 1929: @105201 |
| 37629 | /* 105201 */ GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(105269), // Rule ID 5505 // |
| 37630 | /* 105206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37631 | /* 105211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37632 | /* 105214 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37633 | /* 105217 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37634 | /* 105220 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37635 | /* 105223 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37636 | /* 105226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37637 | /* 105230 */ // MIs[0] base |
| 37638 | /* 105230 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37639 | /* 105234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37640 | /* 105238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37641 | /* 105242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37642 | /* 105246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37643 | /* 105250 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37644 | /* 105254 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37645 | /* 105254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 37646 | /* 105257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37647 | /* 105259 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37648 | /* 105261 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37649 | /* 105263 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37650 | /* 105267 */ GIR_RootConstrainSelectedInstOperands, |
| 37651 | /* 105268 */ // GIR_Coverage, 5505, |
| 37652 | /* 105268 */ GIR_EraseRootFromParent_Done, |
| 37653 | /* 105269 */ // Label 1930: @105269 |
| 37654 | /* 105269 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(105337), // Rule ID 5506 // |
| 37655 | /* 105274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37656 | /* 105279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37657 | /* 105282 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37658 | /* 105285 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37659 | /* 105288 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37660 | /* 105291 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37661 | /* 105294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37662 | /* 105298 */ // MIs[0] base |
| 37663 | /* 105298 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37664 | /* 105302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37665 | /* 105306 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37666 | /* 105310 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37667 | /* 105314 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 37668 | /* 105318 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37669 | /* 105322 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37670 | /* 105322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 37671 | /* 105325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37672 | /* 105327 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37673 | /* 105329 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37674 | /* 105331 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37675 | /* 105335 */ GIR_RootConstrainSelectedInstOperands, |
| 37676 | /* 105336 */ // GIR_Coverage, 5506, |
| 37677 | /* 105336 */ GIR_EraseRootFromParent_Done, |
| 37678 | /* 105337 */ // Label 1931: @105337 |
| 37679 | /* 105337 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(105405), // Rule ID 5509 // |
| 37680 | /* 105342 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37681 | /* 105347 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37682 | /* 105350 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37683 | /* 105353 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37684 | /* 105356 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37685 | /* 105359 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37686 | /* 105362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37687 | /* 105366 */ // MIs[0] base |
| 37688 | /* 105366 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37689 | /* 105370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37690 | /* 105374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37691 | /* 105378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37692 | /* 105382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37693 | /* 105386 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37694 | /* 105390 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37695 | /* 105390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 37696 | /* 105393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37697 | /* 105395 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37698 | /* 105397 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37699 | /* 105399 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37700 | /* 105403 */ GIR_RootConstrainSelectedInstOperands, |
| 37701 | /* 105404 */ // GIR_Coverage, 5509, |
| 37702 | /* 105404 */ GIR_EraseRootFromParent_Done, |
| 37703 | /* 105405 */ // Label 1932: @105405 |
| 37704 | /* 105405 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(105473), // Rule ID 5510 // |
| 37705 | /* 105410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37706 | /* 105415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37707 | /* 105418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37708 | /* 105421 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37709 | /* 105424 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37710 | /* 105427 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37711 | /* 105430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37712 | /* 105434 */ // MIs[0] base |
| 37713 | /* 105434 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37714 | /* 105438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37715 | /* 105442 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37716 | /* 105446 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37717 | /* 105450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 37718 | /* 105454 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37719 | /* 105458 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37720 | /* 105458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 37721 | /* 105461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37722 | /* 105463 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37723 | /* 105465 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37724 | /* 105467 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37725 | /* 105471 */ GIR_RootConstrainSelectedInstOperands, |
| 37726 | /* 105472 */ // GIR_Coverage, 5510, |
| 37727 | /* 105472 */ GIR_EraseRootFromParent_Done, |
| 37728 | /* 105473 */ // Label 1933: @105473 |
| 37729 | /* 105473 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(105541), // Rule ID 5513 // |
| 37730 | /* 105478 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37731 | /* 105483 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37732 | /* 105486 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37733 | /* 105489 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37734 | /* 105492 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37735 | /* 105495 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37736 | /* 105498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37737 | /* 105502 */ // MIs[0] base |
| 37738 | /* 105502 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37739 | /* 105506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37740 | /* 105510 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37741 | /* 105514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37742 | /* 105518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37743 | /* 105522 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37744 | /* 105526 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37745 | /* 105526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 37746 | /* 105529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37747 | /* 105531 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37748 | /* 105533 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37749 | /* 105535 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37750 | /* 105539 */ GIR_RootConstrainSelectedInstOperands, |
| 37751 | /* 105540 */ // GIR_Coverage, 5513, |
| 37752 | /* 105540 */ GIR_EraseRootFromParent_Done, |
| 37753 | /* 105541 */ // Label 1934: @105541 |
| 37754 | /* 105541 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(105609), // Rule ID 5514 // |
| 37755 | /* 105546 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37756 | /* 105551 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37757 | /* 105554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37758 | /* 105557 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37759 | /* 105560 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37760 | /* 105563 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37761 | /* 105566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37762 | /* 105570 */ // MIs[0] base |
| 37763 | /* 105570 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37764 | /* 105574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37765 | /* 105578 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37766 | /* 105582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37767 | /* 105586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 37768 | /* 105590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37769 | /* 105594 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37770 | /* 105594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 37771 | /* 105597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37772 | /* 105599 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37773 | /* 105601 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37774 | /* 105603 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37775 | /* 105607 */ GIR_RootConstrainSelectedInstOperands, |
| 37776 | /* 105608 */ // GIR_Coverage, 5514, |
| 37777 | /* 105608 */ GIR_EraseRootFromParent_Done, |
| 37778 | /* 105609 */ // Label 1935: @105609 |
| 37779 | /* 105609 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(105677), // Rule ID 5517 // |
| 37780 | /* 105614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37781 | /* 105619 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37782 | /* 105622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37783 | /* 105625 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37784 | /* 105628 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37785 | /* 105631 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37786 | /* 105634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37787 | /* 105638 */ // MIs[0] base |
| 37788 | /* 105638 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37789 | /* 105642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37790 | /* 105646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37791 | /* 105650 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37792 | /* 105654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37793 | /* 105658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37794 | /* 105662 */ // (intrinsic_w_chain:{ *:[v4f32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37795 | /* 105662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 37796 | /* 105665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37797 | /* 105667 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37798 | /* 105669 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37799 | /* 105671 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37800 | /* 105675 */ GIR_RootConstrainSelectedInstOperands, |
| 37801 | /* 105676 */ // GIR_Coverage, 5517, |
| 37802 | /* 105676 */ GIR_EraseRootFromParent_Done, |
| 37803 | /* 105677 */ // Label 1936: @105677 |
| 37804 | /* 105677 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(105745), // Rule ID 5518 // |
| 37805 | /* 105682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37806 | /* 105687 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37807 | /* 105690 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37808 | /* 105693 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37809 | /* 105696 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37810 | /* 105699 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37811 | /* 105702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37812 | /* 105706 */ // MIs[0] base |
| 37813 | /* 105706 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37814 | /* 105710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37815 | /* 105714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37816 | /* 105718 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37817 | /* 105722 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 37818 | /* 105726 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37819 | /* 105730 */ // (intrinsic_w_chain:{ *:[v4f32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37820 | /* 105730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 37821 | /* 105733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37822 | /* 105735 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37823 | /* 105737 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37824 | /* 105739 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37825 | /* 105743 */ GIR_RootConstrainSelectedInstOperands, |
| 37826 | /* 105744 */ // GIR_Coverage, 5518, |
| 37827 | /* 105744 */ GIR_EraseRootFromParent_Done, |
| 37828 | /* 105745 */ // Label 1937: @105745 |
| 37829 | /* 105745 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(105813), // Rule ID 5521 // |
| 37830 | /* 105750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37831 | /* 105755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37832 | /* 105758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37833 | /* 105761 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37834 | /* 105764 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37835 | /* 105767 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37836 | /* 105770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37837 | /* 105774 */ // MIs[0] base |
| 37838 | /* 105774 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37839 | /* 105778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37840 | /* 105782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37841 | /* 105786 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37842 | /* 105790 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37843 | /* 105794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37844 | /* 105798 */ // (intrinsic_w_chain:{ *:[v4f32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37845 | /* 105798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 37846 | /* 105801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37847 | /* 105803 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37848 | /* 105805 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37849 | /* 105807 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37850 | /* 105811 */ GIR_RootConstrainSelectedInstOperands, |
| 37851 | /* 105812 */ // GIR_Coverage, 5521, |
| 37852 | /* 105812 */ GIR_EraseRootFromParent_Done, |
| 37853 | /* 105813 */ // Label 1938: @105813 |
| 37854 | /* 105813 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(105881), // Rule ID 5522 // |
| 37855 | /* 105818 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37856 | /* 105823 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 37857 | /* 105826 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 37858 | /* 105829 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37859 | /* 105832 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37860 | /* 105835 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37861 | /* 105838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37862 | /* 105842 */ // MIs[0] base |
| 37863 | /* 105842 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37864 | /* 105846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37865 | /* 105850 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37866 | /* 105854 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 37867 | /* 105858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 37868 | /* 105862 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37869 | /* 105866 */ // (intrinsic_w_chain:{ *:[v4f32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 37870 | /* 105866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 37871 | /* 105869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37872 | /* 105871 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37873 | /* 105873 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37874 | /* 105875 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37875 | /* 105879 */ GIR_RootConstrainSelectedInstOperands, |
| 37876 | /* 105880 */ // GIR_Coverage, 5522, |
| 37877 | /* 105880 */ GIR_EraseRootFromParent_Done, |
| 37878 | /* 105881 */ // Label 1939: @105881 |
| 37879 | /* 105881 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(105949), // Rule ID 5525 // |
| 37880 | /* 105886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37881 | /* 105891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 37882 | /* 105894 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 37883 | /* 105897 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37884 | /* 105900 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37885 | /* 105903 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37886 | /* 105906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37887 | /* 105910 */ // MIs[0] base |
| 37888 | /* 105910 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37889 | /* 105914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37890 | /* 105918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37891 | /* 105922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 37892 | /* 105926 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37893 | /* 105930 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37894 | /* 105934 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 37895 | /* 105934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 37896 | /* 105937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37897 | /* 105939 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37898 | /* 105941 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37899 | /* 105943 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37900 | /* 105947 */ GIR_RootConstrainSelectedInstOperands, |
| 37901 | /* 105948 */ // GIR_Coverage, 5525, |
| 37902 | /* 105948 */ GIR_EraseRootFromParent_Done, |
| 37903 | /* 105949 */ // Label 1940: @105949 |
| 37904 | /* 105949 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(106017), // Rule ID 5526 // |
| 37905 | /* 105954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37906 | /* 105959 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 37907 | /* 105962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 37908 | /* 105965 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37909 | /* 105968 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37910 | /* 105971 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37911 | /* 105974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37912 | /* 105978 */ // MIs[0] base |
| 37913 | /* 105978 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37914 | /* 105982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37915 | /* 105986 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37916 | /* 105990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 37917 | /* 105994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 37918 | /* 105998 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37919 | /* 106002 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 37920 | /* 106002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 37921 | /* 106005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37922 | /* 106007 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37923 | /* 106009 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37924 | /* 106011 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37925 | /* 106015 */ GIR_RootConstrainSelectedInstOperands, |
| 37926 | /* 106016 */ // GIR_Coverage, 5526, |
| 37927 | /* 106016 */ GIR_EraseRootFromParent_Done, |
| 37928 | /* 106017 */ // Label 1941: @106017 |
| 37929 | /* 106017 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(106085), // Rule ID 5529 // |
| 37930 | /* 106022 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37931 | /* 106027 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 37932 | /* 106030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 37933 | /* 106033 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37934 | /* 106036 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37935 | /* 106039 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37936 | /* 106042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37937 | /* 106046 */ // MIs[0] base |
| 37938 | /* 106046 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37939 | /* 106050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37940 | /* 106054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37941 | /* 106058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 37942 | /* 106062 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37943 | /* 106066 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37944 | /* 106070 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 37945 | /* 106070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 37946 | /* 106073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37947 | /* 106075 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37948 | /* 106077 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37949 | /* 106079 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37950 | /* 106083 */ GIR_RootConstrainSelectedInstOperands, |
| 37951 | /* 106084 */ // GIR_Coverage, 5529, |
| 37952 | /* 106084 */ GIR_EraseRootFromParent_Done, |
| 37953 | /* 106085 */ // Label 1942: @106085 |
| 37954 | /* 106085 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(106153), // Rule ID 5530 // |
| 37955 | /* 106090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37956 | /* 106095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 37957 | /* 106098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 37958 | /* 106101 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37959 | /* 106104 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37960 | /* 106107 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37961 | /* 106110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37962 | /* 106114 */ // MIs[0] base |
| 37963 | /* 106114 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37964 | /* 106118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37965 | /* 106122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37966 | /* 106126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 37967 | /* 106130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 37968 | /* 106134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 37969 | /* 106138 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 37970 | /* 106138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 37971 | /* 106141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37972 | /* 106143 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37973 | /* 106145 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37974 | /* 106147 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37975 | /* 106151 */ GIR_RootConstrainSelectedInstOperands, |
| 37976 | /* 106152 */ // GIR_Coverage, 5530, |
| 37977 | /* 106152 */ GIR_EraseRootFromParent_Done, |
| 37978 | /* 106153 */ // Label 1943: @106153 |
| 37979 | /* 106153 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(106221), // Rule ID 5533 // |
| 37980 | /* 106158 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 37981 | /* 106163 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 37982 | /* 106166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 37983 | /* 106169 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 37984 | /* 106172 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 37985 | /* 106175 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 37986 | /* 106178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37987 | /* 106182 */ // MIs[0] base |
| 37988 | /* 106182 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 37989 | /* 106186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37990 | /* 106190 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37991 | /* 106194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 37992 | /* 106198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 37993 | /* 106202 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 37994 | /* 106206 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 37995 | /* 106206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 37996 | /* 106209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37997 | /* 106211 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 37998 | /* 106213 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 37999 | /* 106215 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38000 | /* 106219 */ GIR_RootConstrainSelectedInstOperands, |
| 38001 | /* 106220 */ // GIR_Coverage, 5533, |
| 38002 | /* 106220 */ GIR_EraseRootFromParent_Done, |
| 38003 | /* 106221 */ // Label 1944: @106221 |
| 38004 | /* 106221 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(106289), // Rule ID 5534 // |
| 38005 | /* 106226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 38006 | /* 106231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 38007 | /* 106234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 38008 | /* 106237 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 38009 | /* 106240 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 38010 | /* 106243 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 38011 | /* 106246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38012 | /* 106250 */ // MIs[0] base |
| 38013 | /* 106250 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 38014 | /* 106254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38015 | /* 106258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38016 | /* 106262 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 38017 | /* 106266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 38018 | /* 106270 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 38019 | /* 106274 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 38020 | /* 106274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 38021 | /* 106277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38022 | /* 106279 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 38023 | /* 106281 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 38024 | /* 106283 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38025 | /* 106287 */ GIR_RootConstrainSelectedInstOperands, |
| 38026 | /* 106288 */ // GIR_Coverage, 5534, |
| 38027 | /* 106288 */ GIR_EraseRootFromParent_Done, |
| 38028 | /* 106289 */ // Label 1945: @106289 |
| 38029 | /* 106289 */ GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(106357), // Rule ID 5537 // |
| 38030 | /* 106294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 38031 | /* 106299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 38032 | /* 106302 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 38033 | /* 106305 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 38034 | /* 106308 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 38035 | /* 106311 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 38036 | /* 106314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38037 | /* 106318 */ // MIs[0] base |
| 38038 | /* 106318 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 38039 | /* 106322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38040 | /* 106326 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38041 | /* 106330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 38042 | /* 106334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 38043 | /* 106338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 38044 | /* 106342 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 38045 | /* 106342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 38046 | /* 106345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38047 | /* 106347 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 38048 | /* 106349 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 38049 | /* 106351 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38050 | /* 106355 */ GIR_RootConstrainSelectedInstOperands, |
| 38051 | /* 106356 */ // GIR_Coverage, 5537, |
| 38052 | /* 106356 */ GIR_EraseRootFromParent_Done, |
| 38053 | /* 106357 */ // Label 1946: @106357 |
| 38054 | /* 106357 */ GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(106425), // Rule ID 5538 // |
| 38055 | /* 106362 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 38056 | /* 106367 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 38057 | /* 106370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 38058 | /* 106373 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 38059 | /* 106376 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 38060 | /* 106379 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 38061 | /* 106382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38062 | /* 106386 */ // MIs[0] base |
| 38063 | /* 106386 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 38064 | /* 106390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38065 | /* 106394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38066 | /* 106398 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 38067 | /* 106402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 38068 | /* 106406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 38069 | /* 106410 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 38070 | /* 106410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 38071 | /* 106413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38072 | /* 106415 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 38073 | /* 106417 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 38074 | /* 106419 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38075 | /* 106423 */ GIR_RootConstrainSelectedInstOperands, |
| 38076 | /* 106424 */ // GIR_Coverage, 5538, |
| 38077 | /* 106424 */ GIR_EraseRootFromParent_Done, |
| 38078 | /* 106425 */ // Label 1947: @106425 |
| 38079 | /* 106425 */ GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(106490), // Rule ID 255 // |
| 38080 | /* 106430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 38081 | /* 106433 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 38082 | /* 106438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 38083 | /* 106441 */ // MIs[0] cop |
| 38084 | /* 106441 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 38085 | /* 106444 */ // MIs[0] opc1 |
| 38086 | /* 106444 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 38087 | /* 106447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38088 | /* 106451 */ // MIs[0] CRn |
| 38089 | /* 106451 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 38090 | /* 106454 */ // MIs[0] CRm |
| 38091 | /* 106454 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 38092 | /* 106457 */ // MIs[0] opc2 |
| 38093 | /* 106457 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 38094 | /* 106460 */ // (intrinsic_void 3756:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 38095 | /* 106460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR), |
| 38096 | /* 106463 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 38097 | /* 106465 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 38098 | /* 106467 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 38099 | /* 106469 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 38100 | /* 106471 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 38101 | /* 106473 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 38102 | /* 106475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38103 | /* 106478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38104 | /* 106484 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38105 | /* 106488 */ GIR_RootConstrainSelectedInstOperands, |
| 38106 | /* 106489 */ // GIR_Coverage, 255, |
| 38107 | /* 106489 */ GIR_EraseRootFromParent_Done, |
| 38108 | /* 106490 */ // Label 1948: @106490 |
| 38109 | /* 106490 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(106546), // Rule ID 256 // |
| 38110 | /* 106495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 38111 | /* 106498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 38112 | /* 106503 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 38113 | /* 106506 */ // MIs[0] cop |
| 38114 | /* 106506 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 38115 | /* 106509 */ // MIs[0] opc1 |
| 38116 | /* 106509 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 38117 | /* 106512 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38118 | /* 106516 */ // MIs[0] CRn |
| 38119 | /* 106516 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 38120 | /* 106519 */ // MIs[0] CRm |
| 38121 | /* 106519 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 38122 | /* 106522 */ // MIs[0] opc2 |
| 38123 | /* 106522 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 38124 | /* 106525 */ // (intrinsic_void 3757:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 38125 | /* 106525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2), |
| 38126 | /* 106528 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 38127 | /* 106530 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 38128 | /* 106532 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 38129 | /* 106534 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 38130 | /* 106536 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 38131 | /* 106538 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 38132 | /* 106540 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38133 | /* 106544 */ GIR_RootConstrainSelectedInstOperands, |
| 38134 | /* 106545 */ // GIR_Coverage, 256, |
| 38135 | /* 106545 */ GIR_EraseRootFromParent_Done, |
| 38136 | /* 106546 */ // Label 1949: @106546 |
| 38137 | /* 106546 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(106611), // Rule ID 593 // |
| 38138 | /* 106551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 38139 | /* 106554 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 38140 | /* 106559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 38141 | /* 106562 */ // MIs[0] cop |
| 38142 | /* 106562 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 38143 | /* 106565 */ // MIs[0] opc1 |
| 38144 | /* 106565 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 38145 | /* 106568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38146 | /* 106572 */ // MIs[0] CRn |
| 38147 | /* 106572 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 38148 | /* 106575 */ // MIs[0] CRm |
| 38149 | /* 106575 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 38150 | /* 106578 */ // MIs[0] opc2 |
| 38151 | /* 106578 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 38152 | /* 106581 */ // (intrinsic_void 3756:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 38153 | /* 106581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR), |
| 38154 | /* 106584 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 38155 | /* 106586 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 38156 | /* 106588 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 38157 | /* 106590 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 38158 | /* 106592 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 38159 | /* 106594 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 38160 | /* 106596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38161 | /* 106599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38162 | /* 106605 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38163 | /* 106609 */ GIR_RootConstrainSelectedInstOperands, |
| 38164 | /* 106610 */ // GIR_Coverage, 593, |
| 38165 | /* 106610 */ GIR_EraseRootFromParent_Done, |
| 38166 | /* 106611 */ // Label 1950: @106611 |
| 38167 | /* 106611 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(106676), // Rule ID 594 // |
| 38168 | /* 106616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 38169 | /* 106619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 38170 | /* 106624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 38171 | /* 106627 */ // MIs[0] cop |
| 38172 | /* 106627 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 38173 | /* 106630 */ // MIs[0] opc1 |
| 38174 | /* 106630 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 38175 | /* 106633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38176 | /* 106637 */ // MIs[0] CRn |
| 38177 | /* 106637 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 38178 | /* 106640 */ // MIs[0] CRm |
| 38179 | /* 106640 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 38180 | /* 106643 */ // MIs[0] opc2 |
| 38181 | /* 106643 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 38182 | /* 106646 */ // (intrinsic_void 3757:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 38183 | /* 106646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2), |
| 38184 | /* 106649 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 38185 | /* 106651 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 38186 | /* 106653 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 38187 | /* 106655 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 38188 | /* 106657 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 38189 | /* 106659 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 38190 | /* 106661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38191 | /* 106664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38192 | /* 106670 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38193 | /* 106674 */ GIR_RootConstrainSelectedInstOperands, |
| 38194 | /* 106675 */ // GIR_Coverage, 594, |
| 38195 | /* 106675 */ GIR_EraseRootFromParent_Done, |
| 38196 | /* 106676 */ // Label 1951: @106676 |
| 38197 | /* 106676 */ GIM_Reject, |
| 38198 | /* 106677 */ // Label 1901: @106677 |
| 38199 | /* 106677 */ GIM_Reject, |
| 38200 | /* 106678 */ // Label 23: @106678 |
| 38201 | /* 106678 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1955*/ GIMT_Encode4(106835), |
| 38202 | /* 106689 */ /*GILLT_v2s64*//*Label 1952*/ GIMT_Encode4(106721), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38203 | /* 106701 */ /*GILLT_v4s32*//*Label 1953*/ GIMT_Encode4(106759), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38204 | /* 106717 */ /*GILLT_v8s16*//*Label 1954*/ GIMT_Encode4(106797), |
| 38205 | /* 106721 */ // Label 1952: @106721 |
| 38206 | /* 106721 */ GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(106758), // Rule ID 3042 // |
| 38207 | /* 106726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38208 | /* 106729 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38209 | /* 106732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38210 | /* 106736 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38211 | /* 106740 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 38212 | /* 106740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 38213 | /* 106743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38214 | /* 106745 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38215 | /* 106747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38216 | /* 106750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38217 | /* 106756 */ GIR_RootConstrainSelectedInstOperands, |
| 38218 | /* 106757 */ // GIR_Coverage, 3042, |
| 38219 | /* 106757 */ GIR_EraseRootFromParent_Done, |
| 38220 | /* 106758 */ // Label 1956: @106758 |
| 38221 | /* 106758 */ GIM_Reject, |
| 38222 | /* 106759 */ // Label 1953: @106759 |
| 38223 | /* 106759 */ GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(106796), // Rule ID 3041 // |
| 38224 | /* 106764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38225 | /* 106767 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38226 | /* 106770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38227 | /* 106774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38228 | /* 106778 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 38229 | /* 106778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 38230 | /* 106781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38231 | /* 106783 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38232 | /* 106785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38233 | /* 106788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38234 | /* 106794 */ GIR_RootConstrainSelectedInstOperands, |
| 38235 | /* 106795 */ // GIR_Coverage, 3041, |
| 38236 | /* 106795 */ GIR_EraseRootFromParent_Done, |
| 38237 | /* 106796 */ // Label 1957: @106796 |
| 38238 | /* 106796 */ GIM_Reject, |
| 38239 | /* 106797 */ // Label 1954: @106797 |
| 38240 | /* 106797 */ GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(106834), // Rule ID 3040 // |
| 38241 | /* 106802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38242 | /* 106805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 38243 | /* 106808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38244 | /* 106812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38245 | /* 106816 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 38246 | /* 106816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 38247 | /* 106819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38248 | /* 106821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38249 | /* 106823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38250 | /* 106826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38251 | /* 106832 */ GIR_RootConstrainSelectedInstOperands, |
| 38252 | /* 106833 */ // GIR_Coverage, 3040, |
| 38253 | /* 106833 */ GIR_EraseRootFromParent_Done, |
| 38254 | /* 106834 */ // Label 1958: @106834 |
| 38255 | /* 106834 */ GIM_Reject, |
| 38256 | /* 106835 */ // Label 1955: @106835 |
| 38257 | /* 106835 */ GIM_Reject, |
| 38258 | /* 106836 */ // Label 24: @106836 |
| 38259 | /* 106836 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(12), /*)*//*default:*//*Label 1962*/ GIMT_Encode4(106993), |
| 38260 | /* 106847 */ /*GILLT_v2s32*//*Label 1959*/ GIMT_Encode4(106879), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38261 | /* 106859 */ /*GILLT_v4s16*//*Label 1960*/ GIMT_Encode4(106917), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38262 | /* 106875 */ /*GILLT_v8s8*//*Label 1961*/ GIMT_Encode4(106955), |
| 38263 | /* 106879 */ // Label 1959: @106879 |
| 38264 | /* 106879 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(106916), // Rule ID 1749 // |
| 38265 | /* 106884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38266 | /* 106887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 38267 | /* 106890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38268 | /* 106894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38269 | /* 106898 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 38270 | /* 106898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32), |
| 38271 | /* 106901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38272 | /* 106903 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38273 | /* 106905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38274 | /* 106908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38275 | /* 106914 */ GIR_RootConstrainSelectedInstOperands, |
| 38276 | /* 106915 */ // GIR_Coverage, 1749, |
| 38277 | /* 106915 */ GIR_EraseRootFromParent_Done, |
| 38278 | /* 106916 */ // Label 1963: @106916 |
| 38279 | /* 106916 */ GIM_Reject, |
| 38280 | /* 106917 */ // Label 1960: @106917 |
| 38281 | /* 106917 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(106954), // Rule ID 1748 // |
| 38282 | /* 106922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38283 | /* 106925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38284 | /* 106928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38285 | /* 106932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38286 | /* 106936 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 38287 | /* 106936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16), |
| 38288 | /* 106939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38289 | /* 106941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38290 | /* 106943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38291 | /* 106946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38292 | /* 106952 */ GIR_RootConstrainSelectedInstOperands, |
| 38293 | /* 106953 */ // GIR_Coverage, 1748, |
| 38294 | /* 106953 */ GIR_EraseRootFromParent_Done, |
| 38295 | /* 106954 */ // Label 1964: @106954 |
| 38296 | /* 106954 */ GIM_Reject, |
| 38297 | /* 106955 */ // Label 1961: @106955 |
| 38298 | /* 106955 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(106992), // Rule ID 1747 // |
| 38299 | /* 106960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38300 | /* 106963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38301 | /* 106966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38302 | /* 106970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38303 | /* 106974 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 38304 | /* 106974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8), |
| 38305 | /* 106977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38306 | /* 106979 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38307 | /* 106981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38308 | /* 106984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38309 | /* 106990 */ GIR_RootConstrainSelectedInstOperands, |
| 38310 | /* 106991 */ // GIR_Coverage, 1747, |
| 38311 | /* 106991 */ GIR_EraseRootFromParent_Done, |
| 38312 | /* 106992 */ // Label 1965: @106992 |
| 38313 | /* 106992 */ GIM_Reject, |
| 38314 | /* 106993 */ // Label 1962: @106993 |
| 38315 | /* 106993 */ GIM_Reject, |
| 38316 | /* 106994 */ // Label 25: @106994 |
| 38317 | /* 106994 */ GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(107314), |
| 38318 | /* 106999 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 38319 | /* 107002 */ GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(107043), // Rule ID 403 // |
| 38320 | /* 107007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 38321 | /* 107010 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 38322 | /* 107014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 38323 | /* 107018 */ // MIs[0] Operand 1 |
| 38324 | /* 107018 */ // No operand predicates |
| 38325 | /* 107018 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 38326 | /* 107018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 38327 | /* 107021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38328 | /* 107023 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 38329 | /* 107026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38330 | /* 107029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38331 | /* 107035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38332 | /* 107041 */ GIR_RootConstrainSelectedInstOperands, |
| 38333 | /* 107042 */ // GIR_Coverage, 403, |
| 38334 | /* 107042 */ GIR_EraseRootFromParent_Done, |
| 38335 | /* 107043 */ // Label 1967: @107043 |
| 38336 | /* 107043 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(107084), // Rule ID 56 // |
| 38337 | /* 107048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 38338 | /* 107051 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 38339 | /* 107055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38340 | /* 107059 */ // MIs[0] Operand 1 |
| 38341 | /* 107059 */ // No operand predicates |
| 38342 | /* 107059 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 38343 | /* 107059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 38344 | /* 107062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38345 | /* 107064 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 38346 | /* 107067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38347 | /* 107070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38348 | /* 107076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38349 | /* 107082 */ GIR_RootConstrainSelectedInstOperands, |
| 38350 | /* 107083 */ // GIR_Coverage, 56, |
| 38351 | /* 107083 */ GIR_EraseRootFromParent_Done, |
| 38352 | /* 107084 */ // Label 1968: @107084 |
| 38353 | /* 107084 */ GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(107119), // Rule ID 57 // |
| 38354 | /* 107089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 38355 | /* 107092 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 38356 | /* 107096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38357 | /* 107100 */ // MIs[0] Operand 1 |
| 38358 | /* 107100 */ // No operand predicates |
| 38359 | /* 107100 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 38360 | /* 107100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16), |
| 38361 | /* 107103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38362 | /* 107105 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 38363 | /* 107108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38364 | /* 107111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38365 | /* 107117 */ GIR_RootConstrainSelectedInstOperands, |
| 38366 | /* 107118 */ // GIR_Coverage, 57, |
| 38367 | /* 107118 */ GIR_EraseRootFromParent_Done, |
| 38368 | /* 107119 */ // Label 1969: @107119 |
| 38369 | /* 107119 */ GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(107162), // Rule ID 167 // |
| 38370 | /* 107124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 38371 | /* 107127 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 38372 | /* 107131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38373 | /* 107135 */ // MIs[0] Operand 1 |
| 38374 | /* 107135 */ // No operand predicates |
| 38375 | /* 107135 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 38376 | /* 107135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi), |
| 38377 | /* 107138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38378 | /* 107140 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 38379 | /* 107145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38380 | /* 107148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38381 | /* 107154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38382 | /* 107160 */ GIR_RootConstrainSelectedInstOperands, |
| 38383 | /* 107161 */ // GIR_Coverage, 167, |
| 38384 | /* 107161 */ GIR_EraseRootFromParent_Done, |
| 38385 | /* 107162 */ // Label 1970: @107162 |
| 38386 | /* 107162 */ GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(107188), // Rule ID 267 // |
| 38387 | /* 107167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 38388 | /* 107170 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm), |
| 38389 | /* 107174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38390 | /* 107178 */ // MIs[0] Operand 1 |
| 38391 | /* 107178 */ // No operand predicates |
| 38392 | /* 107178 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 38393 | /* 107178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm), |
| 38394 | /* 107181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38395 | /* 107183 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 38396 | /* 107186 */ GIR_RootConstrainSelectedInstOperands, |
| 38397 | /* 107187 */ // GIR_Coverage, 267, |
| 38398 | /* 107187 */ GIR_EraseRootFromParent_Done, |
| 38399 | /* 107188 */ // Label 1971: @107188 |
| 38400 | /* 107188 */ GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(107229), // Rule ID 321 // |
| 38401 | /* 107193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 38402 | /* 107196 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 38403 | /* 107200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 38404 | /* 107204 */ // MIs[0] Operand 1 |
| 38405 | /* 107204 */ // No operand predicates |
| 38406 | /* 107204 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8) |
| 38407 | /* 107204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 38408 | /* 107207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38409 | /* 107209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 38410 | /* 107215 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8 |
| 38411 | /* 107218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38412 | /* 107221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38413 | /* 107227 */ GIR_RootConstrainSelectedInstOperands, |
| 38414 | /* 107228 */ // GIR_Coverage, 321, |
| 38415 | /* 107228 */ GIR_EraseRootFromParent_Done, |
| 38416 | /* 107229 */ // Label 1972: @107229 |
| 38417 | /* 107229 */ GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(107264), // Rule ID 404 // |
| 38418 | /* 107234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), |
| 38419 | /* 107237 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 38420 | /* 107241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 38421 | /* 107245 */ // MIs[0] Operand 1 |
| 38422 | /* 107245 */ // No operand predicates |
| 38423 | /* 107245 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 38424 | /* 107245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 38425 | /* 107248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38426 | /* 107250 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 38427 | /* 107253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38428 | /* 107256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38429 | /* 107262 */ GIR_RootConstrainSelectedInstOperands, |
| 38430 | /* 107263 */ // GIR_Coverage, 404, |
| 38431 | /* 107263 */ GIR_EraseRootFromParent_Done, |
| 38432 | /* 107264 */ // Label 1973: @107264 |
| 38433 | /* 107264 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(107313), |
| 38434 | /* 107269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 38435 | /* 107273 */ GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(107294), // Rule ID 352 // |
| 38436 | /* 107278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only), |
| 38437 | /* 107281 */ // MIs[0] Operand 1 |
| 38438 | /* 107281 */ // No operand predicates |
| 38439 | /* 107281 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 38440 | /* 107281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm), |
| 38441 | /* 107284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38442 | /* 107286 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 38443 | /* 107289 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0, |
| 38444 | /* 107292 */ GIR_RootConstrainSelectedInstOperands, |
| 38445 | /* 107293 */ // GIR_Coverage, 352, |
| 38446 | /* 107293 */ GIR_EraseRootFromParent_Done, |
| 38447 | /* 107294 */ // Label 1975: @107294 |
| 38448 | /* 107294 */ GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(107312), // Rule ID 581 // |
| 38449 | /* 107299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_UseMovt), |
| 38450 | /* 107302 */ // MIs[0] Operand 1 |
| 38451 | /* 107302 */ // No operand predicates |
| 38452 | /* 107302 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 38453 | /* 107302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 38454 | /* 107305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38455 | /* 107307 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 38456 | /* 107310 */ GIR_RootConstrainSelectedInstOperands, |
| 38457 | /* 107311 */ // GIR_Coverage, 581, |
| 38458 | /* 107311 */ GIR_EraseRootFromParent_Done, |
| 38459 | /* 107312 */ // Label 1976: @107312 |
| 38460 | /* 107312 */ GIM_Reject, |
| 38461 | /* 107313 */ // Label 1974: @107313 |
| 38462 | /* 107313 */ GIM_Reject, |
| 38463 | /* 107314 */ // Label 1966: @107314 |
| 38464 | /* 107314 */ GIM_Reject, |
| 38465 | /* 107315 */ // Label 26: @107315 |
| 38466 | /* 107315 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1979*/ GIMT_Encode4(107410), |
| 38467 | /* 107326 */ /*GILLT_s32*//*Label 1977*/ GIMT_Encode4(107334), |
| 38468 | /* 107330 */ /*GILLT_s64*//*Label 1978*/ GIMT_Encode4(107372), |
| 38469 | /* 107334 */ // Label 1977: @107334 |
| 38470 | /* 107334 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(107371), // Rule ID 847 // |
| 38471 | /* 107339 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP3), |
| 38472 | /* 107342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38473 | /* 107346 */ // MIs[0] Operand 1 |
| 38474 | /* 107346 */ // No operand predicates |
| 38475 | /* 107346 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm), |
| 38476 | /* 107350 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)) |
| 38477 | /* 107350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS), |
| 38478 | /* 107353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38479 | /* 107355 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm |
| 38480 | /* 107360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38481 | /* 107363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38482 | /* 107369 */ GIR_RootConstrainSelectedInstOperands, |
| 38483 | /* 107370 */ // GIR_Coverage, 847, |
| 38484 | /* 107370 */ GIR_EraseRootFromParent_Done, |
| 38485 | /* 107371 */ // Label 1980: @107371 |
| 38486 | /* 107371 */ GIM_Reject, |
| 38487 | /* 107372 */ // Label 1978: @107372 |
| 38488 | /* 107372 */ GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(107409), // Rule ID 846 // |
| 38489 | /* 107377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3), |
| 38490 | /* 107380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38491 | /* 107384 */ // MIs[0] Operand 1 |
| 38492 | /* 107384 */ // No operand predicates |
| 38493 | /* 107384 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm), |
| 38494 | /* 107388 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm)) |
| 38495 | /* 107388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD), |
| 38496 | /* 107391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38497 | /* 107393 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm |
| 38498 | /* 107398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38499 | /* 107401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38500 | /* 107407 */ GIR_RootConstrainSelectedInstOperands, |
| 38501 | /* 107408 */ // GIR_Coverage, 846, |
| 38502 | /* 107408 */ GIR_EraseRootFromParent_Done, |
| 38503 | /* 107409 */ // Label 1981: @107409 |
| 38504 | /* 107409 */ GIM_Reject, |
| 38505 | /* 107410 */ // Label 1979: @107410 |
| 38506 | /* 107410 */ GIM_Reject, |
| 38507 | /* 107411 */ // Label 27: @107411 |
| 38508 | /* 107411 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1985*/ GIMT_Encode4(107568), |
| 38509 | /* 107422 */ /*GILLT_v2s64*//*Label 1982*/ GIMT_Encode4(107454), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38510 | /* 107434 */ /*GILLT_v4s32*//*Label 1983*/ GIMT_Encode4(107492), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38511 | /* 107450 */ /*GILLT_v8s16*//*Label 1984*/ GIMT_Encode4(107530), |
| 38512 | /* 107454 */ // Label 1982: @107454 |
| 38513 | /* 107454 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(107491), // Rule ID 1761 // |
| 38514 | /* 107459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38515 | /* 107462 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38516 | /* 107465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38517 | /* 107469 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38518 | /* 107473 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 38519 | /* 107473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64), |
| 38520 | /* 107476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38521 | /* 107478 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38522 | /* 107480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38523 | /* 107483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38524 | /* 107489 */ GIR_RootConstrainSelectedInstOperands, |
| 38525 | /* 107490 */ // GIR_Coverage, 1761, |
| 38526 | /* 107490 */ GIR_EraseRootFromParent_Done, |
| 38527 | /* 107491 */ // Label 1986: @107491 |
| 38528 | /* 107491 */ GIM_Reject, |
| 38529 | /* 107492 */ // Label 1983: @107492 |
| 38530 | /* 107492 */ GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(107529), // Rule ID 1760 // |
| 38531 | /* 107497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38532 | /* 107500 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38533 | /* 107503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38534 | /* 107507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38535 | /* 107511 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 38536 | /* 107511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32), |
| 38537 | /* 107514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38538 | /* 107516 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38539 | /* 107518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38540 | /* 107521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38541 | /* 107527 */ GIR_RootConstrainSelectedInstOperands, |
| 38542 | /* 107528 */ // GIR_Coverage, 1760, |
| 38543 | /* 107528 */ GIR_EraseRootFromParent_Done, |
| 38544 | /* 107529 */ // Label 1987: @107529 |
| 38545 | /* 107529 */ GIM_Reject, |
| 38546 | /* 107530 */ // Label 1984: @107530 |
| 38547 | /* 107530 */ GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(107567), // Rule ID 1759 // |
| 38548 | /* 107535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38549 | /* 107538 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 38550 | /* 107541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38551 | /* 107545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38552 | /* 107549 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 38553 | /* 107549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16), |
| 38554 | /* 107552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38555 | /* 107554 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38556 | /* 107556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38557 | /* 107559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38558 | /* 107565 */ GIR_RootConstrainSelectedInstOperands, |
| 38559 | /* 107566 */ // GIR_Coverage, 1759, |
| 38560 | /* 107566 */ GIR_EraseRootFromParent_Done, |
| 38561 | /* 107567 */ // Label 1988: @107567 |
| 38562 | /* 107567 */ GIM_Reject, |
| 38563 | /* 107568 */ // Label 1985: @107568 |
| 38564 | /* 107568 */ GIM_Reject, |
| 38565 | /* 107569 */ // Label 28: @107569 |
| 38566 | /* 107569 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 1992*/ GIMT_Encode4(108173), |
| 38567 | /* 107580 */ /*GILLT_s32*//*Label 1989*/ GIMT_Encode4(107628), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38568 | /* 107608 */ /*GILLT_v4s32*//*Label 1990*/ GIMT_Encode4(107920), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38569 | /* 107624 */ /*GILLT_v8s16*//*Label 1991*/ GIMT_Encode4(108103), |
| 38570 | /* 107628 */ // Label 1989: @107628 |
| 38571 | /* 107628 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(107919), |
| 38572 | /* 107633 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38573 | /* 107636 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(107681), // Rule ID 339 // |
| 38574 | /* 107641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 38575 | /* 107644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 38576 | /* 107648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 38577 | /* 107652 */ // MIs[0] Operand 2 |
| 38578 | /* 107652 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 38579 | /* 107663 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 38580 | /* 107663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB), |
| 38581 | /* 107666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38582 | /* 107668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 38583 | /* 107670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38584 | /* 107673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38585 | /* 107679 */ GIR_RootConstrainSelectedInstOperands, |
| 38586 | /* 107680 */ // GIR_Coverage, 339, |
| 38587 | /* 107680 */ GIR_EraseRootFromParent_Done, |
| 38588 | /* 107681 */ // Label 1994: @107681 |
| 38589 | /* 107681 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(107726), // Rule ID 340 // |
| 38590 | /* 107686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 38591 | /* 107689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 38592 | /* 107693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 38593 | /* 107697 */ // MIs[0] Operand 2 |
| 38594 | /* 107697 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 38595 | /* 107708 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 38596 | /* 107708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH), |
| 38597 | /* 107711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38598 | /* 107713 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 38599 | /* 107715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38600 | /* 107718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38601 | /* 107724 */ GIR_RootConstrainSelectedInstOperands, |
| 38602 | /* 107725 */ // GIR_Coverage, 340, |
| 38603 | /* 107725 */ GIR_EraseRootFromParent_Done, |
| 38604 | /* 107726 */ // Label 1995: @107726 |
| 38605 | /* 107726 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(107774), // Rule ID 2187 // |
| 38606 | /* 107731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 38607 | /* 107734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 38608 | /* 107738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38609 | /* 107742 */ // MIs[0] Operand 2 |
| 38610 | /* 107742 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 38611 | /* 107753 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 38612 | /* 107753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB), |
| 38613 | /* 107756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38614 | /* 107758 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 38615 | /* 107760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38616 | /* 107763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38617 | /* 107766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38618 | /* 107772 */ GIR_RootConstrainSelectedInstOperands, |
| 38619 | /* 107773 */ // GIR_Coverage, 2187, |
| 38620 | /* 107773 */ GIR_EraseRootFromParent_Done, |
| 38621 | /* 107774 */ // Label 1996: @107774 |
| 38622 | /* 107774 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(107822), // Rule ID 2188 // |
| 38623 | /* 107779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 38624 | /* 107782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 38625 | /* 107786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 38626 | /* 107790 */ // MIs[0] Operand 2 |
| 38627 | /* 107790 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 38628 | /* 107801 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 38629 | /* 107801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH), |
| 38630 | /* 107804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38631 | /* 107806 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 38632 | /* 107808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38633 | /* 107811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38634 | /* 107814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38635 | /* 107820 */ GIR_RootConstrainSelectedInstOperands, |
| 38636 | /* 107821 */ // GIR_Coverage, 2188, |
| 38637 | /* 107821 */ GIR_EraseRootFromParent_Done, |
| 38638 | /* 107822 */ // Label 1997: @107822 |
| 38639 | /* 107822 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(107870), // Rule ID 2426 // |
| 38640 | /* 107827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 38641 | /* 107830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 38642 | /* 107834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 38643 | /* 107838 */ // MIs[0] Operand 2 |
| 38644 | /* 107838 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 38645 | /* 107849 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 38646 | /* 107849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB), |
| 38647 | /* 107852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38648 | /* 107854 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 38649 | /* 107856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38650 | /* 107859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38651 | /* 107862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38652 | /* 107868 */ GIR_RootConstrainSelectedInstOperands, |
| 38653 | /* 107869 */ // GIR_Coverage, 2426, |
| 38654 | /* 107869 */ GIR_EraseRootFromParent_Done, |
| 38655 | /* 107870 */ // Label 1998: @107870 |
| 38656 | /* 107870 */ GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(107918), // Rule ID 2427 // |
| 38657 | /* 107875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 38658 | /* 107878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 38659 | /* 107882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 38660 | /* 107886 */ // MIs[0] Operand 2 |
| 38661 | /* 107886 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 38662 | /* 107897 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 38663 | /* 107897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH), |
| 38664 | /* 107900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 38665 | /* 107902 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 38666 | /* 107904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38667 | /* 107907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38668 | /* 107910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38669 | /* 107916 */ GIR_RootConstrainSelectedInstOperands, |
| 38670 | /* 107917 */ // GIR_Coverage, 2427, |
| 38671 | /* 107917 */ GIR_EraseRootFromParent_Done, |
| 38672 | /* 107918 */ // Label 1999: @107918 |
| 38673 | /* 107918 */ GIM_Reject, |
| 38674 | /* 107919 */ // Label 1993: @107919 |
| 38675 | /* 107919 */ GIM_Reject, |
| 38676 | /* 107920 */ // Label 1990: @107920 |
| 38677 | /* 107920 */ GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(108102), |
| 38678 | /* 107925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38679 | /* 107928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38680 | /* 107932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38681 | /* 107936 */ GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(107994), // Rule ID 4095 // |
| 38682 | /* 107941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 38683 | /* 107944 */ // MIs[0] Operand 2 |
| 38684 | /* 107944 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 38685 | /* 107955 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 38686 | /* 107955 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38687 | /* 107958 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38688 | /* 107962 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38689 | /* 107967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 38690 | /* 107970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38691 | /* 107972 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 38692 | /* 107974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38693 | /* 107977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38694 | /* 107983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38695 | /* 107989 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38696 | /* 107992 */ GIR_RootConstrainSelectedInstOperands, |
| 38697 | /* 107993 */ // GIR_Coverage, 4095, |
| 38698 | /* 107993 */ GIR_EraseRootFromParent_Done, |
| 38699 | /* 107994 */ // Label 2001: @107994 |
| 38700 | /* 107994 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(108101), // Rule ID 4097 // |
| 38701 | /* 107999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 38702 | /* 108002 */ // MIs[0] Operand 2 |
| 38703 | /* 108002 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 38704 | /* 108013 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)) |
| 38705 | /* 108013 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 38706 | /* 108016 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38707 | /* 108020 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38708 | /* 108025 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 38709 | /* 108028 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38710 | /* 108032 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38711 | /* 108037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 38712 | /* 108040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 38713 | /* 108044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38714 | /* 108049 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 38715 | /* 108053 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 38716 | /* 108056 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38717 | /* 108062 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38718 | /* 108068 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38719 | /* 108071 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38720 | /* 108073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 38721 | /* 108076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38722 | /* 108078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38723 | /* 108081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38724 | /* 108084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38725 | /* 108090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38726 | /* 108096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 38727 | /* 108099 */ GIR_RootConstrainSelectedInstOperands, |
| 38728 | /* 108100 */ // GIR_Coverage, 4097, |
| 38729 | /* 108100 */ GIR_EraseRootFromParent_Done, |
| 38730 | /* 108101 */ // Label 2002: @108101 |
| 38731 | /* 108101 */ GIM_Reject, |
| 38732 | /* 108102 */ // Label 2000: @108102 |
| 38733 | /* 108102 */ GIM_Reject, |
| 38734 | /* 108103 */ // Label 1991: @108103 |
| 38735 | /* 108103 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(108172), // Rule ID 4096 // |
| 38736 | /* 108108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 38737 | /* 108111 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38738 | /* 108114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38739 | /* 108118 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38740 | /* 108122 */ // MIs[0] Operand 2 |
| 38741 | /* 108122 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 38742 | /* 108133 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 38743 | /* 108133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38744 | /* 108136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38745 | /* 108140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38746 | /* 108145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 38747 | /* 108148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38748 | /* 108150 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 38749 | /* 108152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38750 | /* 108155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38751 | /* 108161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38752 | /* 108167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38753 | /* 108170 */ GIR_RootConstrainSelectedInstOperands, |
| 38754 | /* 108171 */ // GIR_Coverage, 4096, |
| 38755 | /* 108171 */ GIR_EraseRootFromParent_Done, |
| 38756 | /* 108172 */ // Label 2003: @108172 |
| 38757 | /* 108172 */ GIM_Reject, |
| 38758 | /* 108173 */ // Label 1992: @108173 |
| 38759 | /* 108173 */ GIM_Reject, |
| 38760 | /* 108174 */ // Label 29: @108174 |
| 38761 | /* 108174 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 2007*/ GIMT_Encode4(108889), |
| 38762 | /* 108185 */ /*GILLT_v2s64*//*Label 2004*/ GIMT_Encode4(108217), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38763 | /* 108197 */ /*GILLT_v4s32*//*Label 2005*/ GIMT_Encode4(108441), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38764 | /* 108213 */ /*GILLT_v8s16*//*Label 2006*/ GIMT_Encode4(108665), |
| 38765 | /* 108217 */ // Label 2004: @108217 |
| 38766 | /* 108217 */ GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(108440), |
| 38767 | /* 108222 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38768 | /* 108225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38769 | /* 108229 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(108289), // Rule ID 1336 // |
| 38770 | /* 108234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38771 | /* 108237 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38772 | /* 108241 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 38773 | /* 108245 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38774 | /* 108249 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38775 | /* 108253 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38776 | /* 108258 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38777 | /* 108263 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38778 | /* 108265 */ // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 38779 | /* 108265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64), |
| 38780 | /* 108268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38781 | /* 108270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38782 | /* 108274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38783 | /* 108278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38784 | /* 108281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38785 | /* 108287 */ GIR_RootConstrainSelectedInstOperands, |
| 38786 | /* 108288 */ // GIR_Coverage, 1336, |
| 38787 | /* 108288 */ GIR_EraseRootFromParent_Done, |
| 38788 | /* 108289 */ // Label 2009: @108289 |
| 38789 | /* 108289 */ GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(108349), // Rule ID 1339 // |
| 38790 | /* 108294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38791 | /* 108297 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38792 | /* 108301 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 38793 | /* 108305 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38794 | /* 108309 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38795 | /* 108313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38796 | /* 108318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38797 | /* 108323 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38798 | /* 108325 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 38799 | /* 108325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64), |
| 38800 | /* 108328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38801 | /* 108330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38802 | /* 108334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38803 | /* 108338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38804 | /* 108341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38805 | /* 108347 */ GIR_RootConstrainSelectedInstOperands, |
| 38806 | /* 108348 */ // GIR_Coverage, 1339, |
| 38807 | /* 108348 */ GIR_EraseRootFromParent_Done, |
| 38808 | /* 108349 */ // Label 2010: @108349 |
| 38809 | /* 108349 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(108409), // Rule ID 2954 // |
| 38810 | /* 108354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38811 | /* 108357 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38812 | /* 108361 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 38813 | /* 108365 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38814 | /* 108369 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38815 | /* 108373 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38816 | /* 108378 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38817 | /* 108383 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38818 | /* 108385 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB) |
| 38819 | /* 108385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64), |
| 38820 | /* 108388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38821 | /* 108390 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 38822 | /* 108394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 38823 | /* 108398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38824 | /* 108401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38825 | /* 108407 */ GIR_RootConstrainSelectedInstOperands, |
| 38826 | /* 108408 */ // GIR_Coverage, 2954, |
| 38827 | /* 108408 */ GIR_EraseRootFromParent_Done, |
| 38828 | /* 108409 */ // Label 2011: @108409 |
| 38829 | /* 108409 */ GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(108439), // Rule ID 1764 // |
| 38830 | /* 108414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38831 | /* 108417 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38832 | /* 108421 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 38833 | /* 108421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 38834 | /* 108424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38835 | /* 108426 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38836 | /* 108428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38837 | /* 108431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38838 | /* 108437 */ GIR_RootConstrainSelectedInstOperands, |
| 38839 | /* 108438 */ // GIR_Coverage, 1764, |
| 38840 | /* 108438 */ GIR_EraseRootFromParent_Done, |
| 38841 | /* 108439 */ // Label 2012: @108439 |
| 38842 | /* 108439 */ GIM_Reject, |
| 38843 | /* 108440 */ // Label 2008: @108440 |
| 38844 | /* 108440 */ GIM_Reject, |
| 38845 | /* 108441 */ // Label 2005: @108441 |
| 38846 | /* 108441 */ GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(108664), |
| 38847 | /* 108446 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38848 | /* 108449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38849 | /* 108453 */ GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(108513), // Rule ID 1335 // |
| 38850 | /* 108458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38851 | /* 108461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38852 | /* 108465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 38853 | /* 108469 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38854 | /* 108473 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38855 | /* 108477 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38856 | /* 108482 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38857 | /* 108487 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38858 | /* 108489 */ // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 38859 | /* 108489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32), |
| 38860 | /* 108492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38861 | /* 108494 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38862 | /* 108498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38863 | /* 108502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38864 | /* 108505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38865 | /* 108511 */ GIR_RootConstrainSelectedInstOperands, |
| 38866 | /* 108512 */ // GIR_Coverage, 1335, |
| 38867 | /* 108512 */ GIR_EraseRootFromParent_Done, |
| 38868 | /* 108513 */ // Label 2014: @108513 |
| 38869 | /* 108513 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(108573), // Rule ID 1338 // |
| 38870 | /* 108518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38871 | /* 108521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38872 | /* 108525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 38873 | /* 108529 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38874 | /* 108533 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38875 | /* 108537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38876 | /* 108542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38877 | /* 108547 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38878 | /* 108549 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 38879 | /* 108549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32), |
| 38880 | /* 108552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38881 | /* 108554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38882 | /* 108558 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38883 | /* 108562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38884 | /* 108565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38885 | /* 108571 */ GIR_RootConstrainSelectedInstOperands, |
| 38886 | /* 108572 */ // GIR_Coverage, 1338, |
| 38887 | /* 108572 */ GIR_EraseRootFromParent_Done, |
| 38888 | /* 108573 */ // Label 2015: @108573 |
| 38889 | /* 108573 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(108633), // Rule ID 2953 // |
| 38890 | /* 108578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38891 | /* 108581 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38892 | /* 108585 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 38893 | /* 108589 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38894 | /* 108593 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38895 | /* 108597 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38896 | /* 108602 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38897 | /* 108607 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38898 | /* 108609 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB) |
| 38899 | /* 108609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32), |
| 38900 | /* 108612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38901 | /* 108614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 38902 | /* 108618 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 38903 | /* 108622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38904 | /* 108625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38905 | /* 108631 */ GIR_RootConstrainSelectedInstOperands, |
| 38906 | /* 108632 */ // GIR_Coverage, 2953, |
| 38907 | /* 108632 */ GIR_EraseRootFromParent_Done, |
| 38908 | /* 108633 */ // Label 2016: @108633 |
| 38909 | /* 108633 */ GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(108663), // Rule ID 1763 // |
| 38910 | /* 108638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38911 | /* 108641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38912 | /* 108645 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 38913 | /* 108645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 38914 | /* 108648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38915 | /* 108650 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38916 | /* 108652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38917 | /* 108655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38918 | /* 108661 */ GIR_RootConstrainSelectedInstOperands, |
| 38919 | /* 108662 */ // GIR_Coverage, 1763, |
| 38920 | /* 108662 */ GIR_EraseRootFromParent_Done, |
| 38921 | /* 108663 */ // Label 2017: @108663 |
| 38922 | /* 108663 */ GIM_Reject, |
| 38923 | /* 108664 */ // Label 2013: @108664 |
| 38924 | /* 108664 */ GIM_Reject, |
| 38925 | /* 108665 */ // Label 2006: @108665 |
| 38926 | /* 108665 */ GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(108888), |
| 38927 | /* 108670 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 38928 | /* 108673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38929 | /* 108677 */ GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(108737), // Rule ID 1334 // |
| 38930 | /* 108682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38931 | /* 108685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38932 | /* 108689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 38933 | /* 108693 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 38934 | /* 108697 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 38935 | /* 108701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38936 | /* 108706 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38937 | /* 108711 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38938 | /* 108713 */ // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 38939 | /* 108713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16), |
| 38940 | /* 108716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38941 | /* 108718 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38942 | /* 108722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38943 | /* 108726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38944 | /* 108729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38945 | /* 108735 */ GIR_RootConstrainSelectedInstOperands, |
| 38946 | /* 108736 */ // GIR_Coverage, 1334, |
| 38947 | /* 108736 */ GIR_EraseRootFromParent_Done, |
| 38948 | /* 108737 */ // Label 2019: @108737 |
| 38949 | /* 108737 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(108797), // Rule ID 1337 // |
| 38950 | /* 108742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38951 | /* 108745 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38952 | /* 108749 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 38953 | /* 108753 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 38954 | /* 108757 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 38955 | /* 108761 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38956 | /* 108766 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38957 | /* 108771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38958 | /* 108773 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 38959 | /* 108773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16), |
| 38960 | /* 108776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38961 | /* 108778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38962 | /* 108782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38963 | /* 108786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38964 | /* 108789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38965 | /* 108795 */ GIR_RootConstrainSelectedInstOperands, |
| 38966 | /* 108796 */ // GIR_Coverage, 1337, |
| 38967 | /* 108796 */ GIR_EraseRootFromParent_Done, |
| 38968 | /* 108797 */ // Label 2020: @108797 |
| 38969 | /* 108797 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(108857), // Rule ID 2952 // |
| 38970 | /* 108802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38971 | /* 108805 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38972 | /* 108809 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 38973 | /* 108813 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 38974 | /* 108817 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 38975 | /* 108821 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38976 | /* 108826 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38977 | /* 108831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38978 | /* 108833 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB) |
| 38979 | /* 108833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16), |
| 38980 | /* 108836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38981 | /* 108838 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 38982 | /* 108842 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 38983 | /* 108846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38984 | /* 108849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38985 | /* 108855 */ GIR_RootConstrainSelectedInstOperands, |
| 38986 | /* 108856 */ // GIR_Coverage, 2952, |
| 38987 | /* 108856 */ GIR_EraseRootFromParent_Done, |
| 38988 | /* 108857 */ // Label 2021: @108857 |
| 38989 | /* 108857 */ GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(108887), // Rule ID 1762 // |
| 38990 | /* 108862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38991 | /* 108865 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38992 | /* 108869 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 38993 | /* 108869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 38994 | /* 108872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38995 | /* 108874 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 38996 | /* 108876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38997 | /* 108879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38998 | /* 108885 */ GIR_RootConstrainSelectedInstOperands, |
| 38999 | /* 108886 */ // GIR_Coverage, 1762, |
| 39000 | /* 108886 */ GIR_EraseRootFromParent_Done, |
| 39001 | /* 108887 */ // Label 2022: @108887 |
| 39002 | /* 108887 */ GIM_Reject, |
| 39003 | /* 108888 */ // Label 2018: @108888 |
| 39004 | /* 108888 */ GIM_Reject, |
| 39005 | /* 108889 */ // Label 2007: @108889 |
| 39006 | /* 108889 */ GIM_Reject, |
| 39007 | /* 108890 */ // Label 30: @108890 |
| 39008 | /* 108890 */ GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(109105), |
| 39009 | /* 108895 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 39010 | /* 108898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39011 | /* 108901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39012 | /* 108904 */ GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(108961), // Rule ID 469 // |
| 39013 | /* 108909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39014 | /* 108912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39015 | /* 108916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39016 | /* 108920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39017 | /* 108924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 39018 | /* 108928 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 39019 | /* 108932 */ // MIs[1] Operand 1 |
| 39020 | /* 108932 */ // No operand predicates |
| 39021 | /* 108932 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39022 | /* 108934 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 39023 | /* 108934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri), |
| 39024 | /* 108937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39025 | /* 108939 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 39026 | /* 108941 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 39027 | /* 108944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39028 | /* 108947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39029 | /* 108953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39030 | /* 108959 */ GIR_RootConstrainSelectedInstOperands, |
| 39031 | /* 108960 */ // GIR_Coverage, 469, |
| 39032 | /* 108960 */ GIR_EraseRootFromParent_Done, |
| 39033 | /* 108961 */ // Label 2024: @108961 |
| 39034 | /* 108961 */ GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(109058), |
| 39035 | /* 108966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39036 | /* 108970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39037 | /* 108974 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(109019), // Rule ID 317 // |
| 39038 | /* 108979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 39039 | /* 108982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39040 | /* 108986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 39041 | /* 108990 */ // MIs[1] Operand 1 |
| 39042 | /* 108990 */ // No operand predicates |
| 39043 | /* 108990 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39044 | /* 108992 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) |
| 39045 | /* 108992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri), |
| 39046 | /* 108995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39047 | /* 108997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 39048 | /* 109003 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 39049 | /* 109005 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5 |
| 39050 | /* 109008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39051 | /* 109011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39052 | /* 109017 */ GIR_RootConstrainSelectedInstOperands, |
| 39053 | /* 109018 */ // GIR_Coverage, 317, |
| 39054 | /* 109018 */ GIR_EraseRootFromParent_Done, |
| 39055 | /* 109019 */ // Label 2026: @109019 |
| 39056 | /* 109019 */ GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(109057), // Rule ID 318 // |
| 39057 | /* 109024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 39058 | /* 109027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39059 | /* 109031 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 39060 | /* 109031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr), |
| 39061 | /* 109034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 39062 | /* 109036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 39063 | /* 109042 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39064 | /* 109044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39065 | /* 109046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39066 | /* 109049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39067 | /* 109055 */ GIR_RootConstrainSelectedInstOperands, |
| 39068 | /* 109056 */ // GIR_Coverage, 318, |
| 39069 | /* 109056 */ GIR_EraseRootFromParent_Done, |
| 39070 | /* 109057 */ // Label 2027: @109057 |
| 39071 | /* 109057 */ GIM_Reject, |
| 39072 | /* 109058 */ // Label 2025: @109058 |
| 39073 | /* 109058 */ GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(109104), // Rule ID 470 // |
| 39074 | /* 109063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39075 | /* 109066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39076 | /* 109070 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39077 | /* 109074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39078 | /* 109078 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 39079 | /* 109078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr), |
| 39080 | /* 109081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39081 | /* 109083 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39082 | /* 109085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39083 | /* 109087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39084 | /* 109090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39085 | /* 109096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39086 | /* 109102 */ GIR_RootConstrainSelectedInstOperands, |
| 39087 | /* 109103 */ // GIR_Coverage, 470, |
| 39088 | /* 109103 */ GIR_EraseRootFromParent_Done, |
| 39089 | /* 109104 */ // Label 2028: @109104 |
| 39090 | /* 109104 */ GIM_Reject, |
| 39091 | /* 109105 */ // Label 2023: @109105 |
| 39092 | /* 109105 */ GIM_Reject, |
| 39093 | /* 109106 */ // Label 31: @109106 |
| 39094 | /* 109106 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(109213), |
| 39095 | /* 109111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 39096 | /* 109114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39097 | /* 109117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39098 | /* 109120 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(109166), // Rule ID 320 // |
| 39099 | /* 109125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 39100 | /* 109128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39101 | /* 109132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39102 | /* 109136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39103 | /* 109140 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 39104 | /* 109140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr), |
| 39105 | /* 109143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 39106 | /* 109145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 39107 | /* 109151 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39108 | /* 109153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39109 | /* 109155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39110 | /* 109158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39111 | /* 109164 */ GIR_RootConstrainSelectedInstOperands, |
| 39112 | /* 109165 */ // GIR_Coverage, 320, |
| 39113 | /* 109165 */ GIR_EraseRootFromParent_Done, |
| 39114 | /* 109166 */ // Label 2030: @109166 |
| 39115 | /* 109166 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(109212), // Rule ID 472 // |
| 39116 | /* 109171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39117 | /* 109174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39118 | /* 109178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39119 | /* 109182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39120 | /* 109186 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 39121 | /* 109186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr), |
| 39122 | /* 109189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39123 | /* 109191 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39124 | /* 109193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39125 | /* 109195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39126 | /* 109198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39127 | /* 109204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39128 | /* 109210 */ GIR_RootConstrainSelectedInstOperands, |
| 39129 | /* 109211 */ // GIR_Coverage, 472, |
| 39130 | /* 109211 */ GIR_EraseRootFromParent_Done, |
| 39131 | /* 109212 */ // Label 2031: @109212 |
| 39132 | /* 109212 */ GIM_Reject, |
| 39133 | /* 109213 */ // Label 2029: @109213 |
| 39134 | /* 109213 */ GIM_Reject, |
| 39135 | /* 109214 */ // Label 32: @109214 |
| 39136 | /* 109214 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(109486), |
| 39137 | /* 109219 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 39138 | /* 109222 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39139 | /* 109225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39140 | /* 109228 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(109283), // Rule ID 200 // |
| 39141 | /* 109233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 39142 | /* 109236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39143 | /* 109240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39144 | /* 109244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 39145 | /* 109248 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39146 | /* 109252 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39147 | /* 109257 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 39148 | /* 109261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39149 | /* 109263 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 39150 | /* 109263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 39151 | /* 109266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39152 | /* 109268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39153 | /* 109272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39154 | /* 109275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39155 | /* 109281 */ GIR_RootConstrainSelectedInstOperands, |
| 39156 | /* 109282 */ // GIR_Coverage, 200, |
| 39157 | /* 109282 */ GIR_EraseRootFromParent_Done, |
| 39158 | /* 109283 */ // Label 2033: @109283 |
| 39159 | /* 109283 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(109338), // Rule ID 327 // |
| 39160 | /* 109288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 39161 | /* 109291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39162 | /* 109295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39163 | /* 109299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 39164 | /* 109303 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39165 | /* 109307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39166 | /* 109312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 39167 | /* 109316 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39168 | /* 109318 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 39169 | /* 109318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH), |
| 39170 | /* 109321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39171 | /* 109323 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39172 | /* 109327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39173 | /* 109330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39174 | /* 109336 */ GIR_RootConstrainSelectedInstOperands, |
| 39175 | /* 109337 */ // GIR_Coverage, 327, |
| 39176 | /* 109337 */ GIR_EraseRootFromParent_Done, |
| 39177 | /* 109338 */ // Label 2034: @109338 |
| 39178 | /* 109338 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(109393), // Rule ID 537 // |
| 39179 | /* 109343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39180 | /* 109346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39181 | /* 109350 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39182 | /* 109354 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 39183 | /* 109358 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39184 | /* 109362 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39185 | /* 109367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 39186 | /* 109371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39187 | /* 109373 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 39188 | /* 109373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 39189 | /* 109376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39190 | /* 109378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39191 | /* 109382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39192 | /* 109385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39193 | /* 109391 */ GIR_RootConstrainSelectedInstOperands, |
| 39194 | /* 109392 */ // GIR_Coverage, 537, |
| 39195 | /* 109392 */ GIR_EraseRootFromParent_Done, |
| 39196 | /* 109393 */ // Label 2035: @109393 |
| 39197 | /* 109393 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(109439), // Rule ID 311 // |
| 39198 | /* 109398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 39199 | /* 109401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39200 | /* 109405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39201 | /* 109409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39202 | /* 109413 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 39203 | /* 109413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr), |
| 39204 | /* 109416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 39205 | /* 109418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 39206 | /* 109424 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39207 | /* 109426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39208 | /* 109428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39209 | /* 109431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39210 | /* 109437 */ GIR_RootConstrainSelectedInstOperands, |
| 39211 | /* 109438 */ // GIR_Coverage, 311, |
| 39212 | /* 109438 */ GIR_EraseRootFromParent_Done, |
| 39213 | /* 109439 */ // Label 2036: @109439 |
| 39214 | /* 109439 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(109485), // Rule ID 474 // |
| 39215 | /* 109444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39216 | /* 109447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39217 | /* 109451 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39218 | /* 109455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39219 | /* 109459 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 39220 | /* 109459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr), |
| 39221 | /* 109462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39222 | /* 109464 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39223 | /* 109466 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39224 | /* 109468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39225 | /* 109471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39226 | /* 109477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39227 | /* 109483 */ GIR_RootConstrainSelectedInstOperands, |
| 39228 | /* 109484 */ // GIR_Coverage, 474, |
| 39229 | /* 109484 */ GIR_EraseRootFromParent_Done, |
| 39230 | /* 109485 */ // Label 2037: @109485 |
| 39231 | /* 109485 */ GIM_Reject, |
| 39232 | /* 109486 */ // Label 2032: @109486 |
| 39233 | /* 109486 */ GIM_Reject, |
| 39234 | /* 109487 */ // Label 33: @109487 |
| 39235 | /* 109487 */ GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(109818), |
| 39236 | /* 109492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 39237 | /* 109495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39238 | /* 109498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39239 | /* 109501 */ GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(109556), // Rule ID 199 // |
| 39240 | /* 109506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 39241 | /* 109509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39242 | /* 109513 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39243 | /* 109517 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 39244 | /* 109521 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39245 | /* 109525 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39246 | /* 109530 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 39247 | /* 109534 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39248 | /* 109536 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 39249 | /* 109536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16), |
| 39250 | /* 109539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39251 | /* 109541 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39252 | /* 109545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39253 | /* 109548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39254 | /* 109554 */ GIR_RootConstrainSelectedInstOperands, |
| 39255 | /* 109555 */ // GIR_Coverage, 199, |
| 39256 | /* 109555 */ GIR_EraseRootFromParent_Done, |
| 39257 | /* 109556 */ // Label 2039: @109556 |
| 39258 | /* 109556 */ GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(109611), // Rule ID 326 // |
| 39259 | /* 109561 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 39260 | /* 109564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39261 | /* 109568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39262 | /* 109572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 39263 | /* 109576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39264 | /* 109580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39265 | /* 109585 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 39266 | /* 109589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39267 | /* 109591 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 39268 | /* 109591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16), |
| 39269 | /* 109594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39270 | /* 109596 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39271 | /* 109600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39272 | /* 109603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39273 | /* 109609 */ GIR_RootConstrainSelectedInstOperands, |
| 39274 | /* 109610 */ // GIR_Coverage, 326, |
| 39275 | /* 109610 */ GIR_EraseRootFromParent_Done, |
| 39276 | /* 109611 */ // Label 2040: @109611 |
| 39277 | /* 109611 */ GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(109725), |
| 39278 | /* 109616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39279 | /* 109620 */ GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(109671), // Rule ID 536 // |
| 39280 | /* 109625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39281 | /* 109628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39282 | /* 109632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 39283 | /* 109636 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39284 | /* 109640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39285 | /* 109645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 39286 | /* 109649 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39287 | /* 109651 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 39288 | /* 109651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16), |
| 39289 | /* 109654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39290 | /* 109656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39291 | /* 109660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39292 | /* 109663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39293 | /* 109669 */ GIR_RootConstrainSelectedInstOperands, |
| 39294 | /* 109670 */ // GIR_Coverage, 536, |
| 39295 | /* 109670 */ GIR_EraseRootFromParent_Done, |
| 39296 | /* 109671 */ // Label 2042: @109671 |
| 39297 | /* 109671 */ GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(109724), // Rule ID 475 // |
| 39298 | /* 109676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39299 | /* 109679 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39300 | /* 109683 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39301 | /* 109687 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 39302 | /* 109691 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 39303 | /* 109695 */ // MIs[1] Operand 1 |
| 39304 | /* 109695 */ // No operand predicates |
| 39305 | /* 109695 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39306 | /* 109697 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 39307 | /* 109697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri), |
| 39308 | /* 109700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39309 | /* 109702 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 39310 | /* 109704 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 39311 | /* 109707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39312 | /* 109710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39313 | /* 109716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39314 | /* 109722 */ GIR_RootConstrainSelectedInstOperands, |
| 39315 | /* 109723 */ // GIR_Coverage, 475, |
| 39316 | /* 109723 */ GIR_EraseRootFromParent_Done, |
| 39317 | /* 109724 */ // Label 2043: @109724 |
| 39318 | /* 109724 */ GIM_Reject, |
| 39319 | /* 109725 */ // Label 2041: @109725 |
| 39320 | /* 109725 */ GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(109771), // Rule ID 328 // |
| 39321 | /* 109730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 39322 | /* 109733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39323 | /* 109737 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39324 | /* 109741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 39325 | /* 109745 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 39326 | /* 109745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR), |
| 39327 | /* 109748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 39328 | /* 109750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 39329 | /* 109756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39330 | /* 109758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39331 | /* 109760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39332 | /* 109763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39333 | /* 109769 */ GIR_RootConstrainSelectedInstOperands, |
| 39334 | /* 109770 */ // GIR_Coverage, 328, |
| 39335 | /* 109770 */ GIR_EraseRootFromParent_Done, |
| 39336 | /* 109771 */ // Label 2044: @109771 |
| 39337 | /* 109771 */ GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(109817), // Rule ID 476 // |
| 39338 | /* 109776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 39339 | /* 109779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39340 | /* 109783 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39341 | /* 109787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39342 | /* 109791 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 39343 | /* 109791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr), |
| 39344 | /* 109794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39345 | /* 109796 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39346 | /* 109798 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39347 | /* 109800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39348 | /* 109803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39349 | /* 109809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39350 | /* 109815 */ GIR_RootConstrainSelectedInstOperands, |
| 39351 | /* 109816 */ // GIR_Coverage, 476, |
| 39352 | /* 109816 */ GIR_EraseRootFromParent_Done, |
| 39353 | /* 109817 */ // Label 2045: @109817 |
| 39354 | /* 109817 */ GIM_Reject, |
| 39355 | /* 109818 */ // Label 2038: @109818 |
| 39356 | /* 109818 */ GIM_Reject, |
| 39357 | /* 109819 */ // Label 34: @109819 |
| 39358 | /* 109819 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2049*/ GIMT_Encode4(110066), |
| 39359 | /* 109830 */ /*GILLT_v4s32*//*Label 2046*/ GIMT_Encode4(109862), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39360 | /* 109846 */ /*GILLT_v8s16*//*Label 2047*/ GIMT_Encode4(109930), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39361 | /* 109858 */ /*GILLT_v16s8*//*Label 2048*/ GIMT_Encode4(109998), |
| 39362 | /* 109862 */ // Label 2046: @109862 |
| 39363 | /* 109862 */ GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(109929), // Rule ID 4954 // |
| 39364 | /* 109867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39365 | /* 109870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39366 | /* 109873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39367 | /* 109876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39368 | /* 109880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39369 | /* 109884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39370 | /* 109888 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 39371 | /* 109888 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39372 | /* 109891 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39373 | /* 109895 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39374 | /* 109900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 39375 | /* 109903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39376 | /* 109905 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39377 | /* 109907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39378 | /* 109909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39379 | /* 109912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39380 | /* 109918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39381 | /* 109924 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39382 | /* 109927 */ GIR_RootConstrainSelectedInstOperands, |
| 39383 | /* 109928 */ // GIR_Coverage, 4954, |
| 39384 | /* 109928 */ GIR_EraseRootFromParent_Done, |
| 39385 | /* 109929 */ // Label 2050: @109929 |
| 39386 | /* 109929 */ GIM_Reject, |
| 39387 | /* 109930 */ // Label 2047: @109930 |
| 39388 | /* 109930 */ GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(109997), // Rule ID 4950 // |
| 39389 | /* 109935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39390 | /* 109938 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39391 | /* 109941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39392 | /* 109944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39393 | /* 109948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39394 | /* 109952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39395 | /* 109956 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 39396 | /* 109956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39397 | /* 109959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39398 | /* 109963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39399 | /* 109968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 39400 | /* 109971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39401 | /* 109973 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39402 | /* 109975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39403 | /* 109977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39404 | /* 109980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39405 | /* 109986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39406 | /* 109992 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39407 | /* 109995 */ GIR_RootConstrainSelectedInstOperands, |
| 39408 | /* 109996 */ // GIR_Coverage, 4950, |
| 39409 | /* 109996 */ GIR_EraseRootFromParent_Done, |
| 39410 | /* 109997 */ // Label 2051: @109997 |
| 39411 | /* 109997 */ GIM_Reject, |
| 39412 | /* 109998 */ // Label 2048: @109998 |
| 39413 | /* 109998 */ GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(110065), // Rule ID 4946 // |
| 39414 | /* 110003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39415 | /* 110006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 39416 | /* 110009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 39417 | /* 110012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39418 | /* 110016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39419 | /* 110020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39420 | /* 110024 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 39421 | /* 110024 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39422 | /* 110027 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39423 | /* 110031 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39424 | /* 110036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 39425 | /* 110039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39426 | /* 110041 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39427 | /* 110043 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39428 | /* 110045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39429 | /* 110048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39430 | /* 110054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39431 | /* 110060 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39432 | /* 110063 */ GIR_RootConstrainSelectedInstOperands, |
| 39433 | /* 110064 */ // GIR_Coverage, 4946, |
| 39434 | /* 110064 */ GIR_EraseRootFromParent_Done, |
| 39435 | /* 110065 */ // Label 2052: @110065 |
| 39436 | /* 110065 */ GIM_Reject, |
| 39437 | /* 110066 */ // Label 2049: @110066 |
| 39438 | /* 110066 */ GIM_Reject, |
| 39439 | /* 110067 */ // Label 35: @110067 |
| 39440 | /* 110067 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2057*/ GIMT_Encode4(110435), |
| 39441 | /* 110078 */ /*GILLT_s32*//*Label 2053*/ GIMT_Encode4(110138), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39442 | /* 110106 */ /*GILLT_v4s32*//*Label 2054*/ GIMT_Encode4(110231), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39443 | /* 110122 */ /*GILLT_v8s16*//*Label 2055*/ GIMT_Encode4(110299), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39444 | /* 110134 */ /*GILLT_v16s8*//*Label 2056*/ GIMT_Encode4(110367), |
| 39445 | /* 110138 */ // Label 2053: @110138 |
| 39446 | /* 110138 */ GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(110230), |
| 39447 | /* 110143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39448 | /* 110146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39449 | /* 110149 */ GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(110189), // Rule ID 177 // |
| 39450 | /* 110154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 39451 | /* 110157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39452 | /* 110161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39453 | /* 110165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39454 | /* 110169 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 39455 | /* 110169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL), |
| 39456 | /* 110172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39457 | /* 110174 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39458 | /* 110176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39459 | /* 110178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39460 | /* 110181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39461 | /* 110187 */ GIR_RootConstrainSelectedInstOperands, |
| 39462 | /* 110188 */ // GIR_Coverage, 177, |
| 39463 | /* 110188 */ GIR_EraseRootFromParent_Done, |
| 39464 | /* 110189 */ // Label 2059: @110189 |
| 39465 | /* 110189 */ GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(110229), // Rule ID 506 // |
| 39466 | /* 110194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 39467 | /* 110197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39468 | /* 110201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39469 | /* 110205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39470 | /* 110209 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 39471 | /* 110209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL), |
| 39472 | /* 110212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39473 | /* 110214 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 39474 | /* 110216 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39475 | /* 110218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39476 | /* 110221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39477 | /* 110227 */ GIR_RootConstrainSelectedInstOperands, |
| 39478 | /* 110228 */ // GIR_Coverage, 506, |
| 39479 | /* 110228 */ GIR_EraseRootFromParent_Done, |
| 39480 | /* 110229 */ // Label 2060: @110229 |
| 39481 | /* 110229 */ GIM_Reject, |
| 39482 | /* 110230 */ // Label 2058: @110230 |
| 39483 | /* 110230 */ GIM_Reject, |
| 39484 | /* 110231 */ // Label 2054: @110231 |
| 39485 | /* 110231 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(110298), // Rule ID 4942 // |
| 39486 | /* 110236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39487 | /* 110239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39488 | /* 110242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39489 | /* 110245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39490 | /* 110249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39491 | /* 110253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39492 | /* 110257 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 39493 | /* 110257 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39494 | /* 110260 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39495 | /* 110264 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39496 | /* 110269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 39497 | /* 110272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39498 | /* 110274 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39499 | /* 110276 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39500 | /* 110278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39501 | /* 110281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39502 | /* 110287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39503 | /* 110293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39504 | /* 110296 */ GIR_RootConstrainSelectedInstOperands, |
| 39505 | /* 110297 */ // GIR_Coverage, 4942, |
| 39506 | /* 110297 */ GIR_EraseRootFromParent_Done, |
| 39507 | /* 110298 */ // Label 2061: @110298 |
| 39508 | /* 110298 */ GIM_Reject, |
| 39509 | /* 110299 */ // Label 2055: @110299 |
| 39510 | /* 110299 */ GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(110366), // Rule ID 4938 // |
| 39511 | /* 110304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39512 | /* 110307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39513 | /* 110310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39514 | /* 110313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39515 | /* 110317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39516 | /* 110321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39517 | /* 110325 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 39518 | /* 110325 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39519 | /* 110328 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39520 | /* 110332 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39521 | /* 110337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 39522 | /* 110340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39523 | /* 110342 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39524 | /* 110344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39525 | /* 110346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39526 | /* 110349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39527 | /* 110355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39528 | /* 110361 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39529 | /* 110364 */ GIR_RootConstrainSelectedInstOperands, |
| 39530 | /* 110365 */ // GIR_Coverage, 4938, |
| 39531 | /* 110365 */ GIR_EraseRootFromParent_Done, |
| 39532 | /* 110366 */ // Label 2062: @110366 |
| 39533 | /* 110366 */ GIM_Reject, |
| 39534 | /* 110367 */ // Label 2056: @110367 |
| 39535 | /* 110367 */ GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(110434), // Rule ID 4935 // |
| 39536 | /* 110372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39537 | /* 110375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 39538 | /* 110378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 39539 | /* 110381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39540 | /* 110385 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39541 | /* 110389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39542 | /* 110393 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 39543 | /* 110393 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39544 | /* 110396 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39545 | /* 110400 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39546 | /* 110405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 39547 | /* 110408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39548 | /* 110410 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39549 | /* 110412 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39550 | /* 110414 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39551 | /* 110417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39552 | /* 110423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39553 | /* 110429 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39554 | /* 110432 */ GIR_RootConstrainSelectedInstOperands, |
| 39555 | /* 110433 */ // GIR_Coverage, 4935, |
| 39556 | /* 110433 */ GIR_EraseRootFromParent_Done, |
| 39557 | /* 110434 */ // Label 2063: @110434 |
| 39558 | /* 110434 */ GIM_Reject, |
| 39559 | /* 110435 */ // Label 2057: @110435 |
| 39560 | /* 110435 */ GIM_Reject, |
| 39561 | /* 110436 */ // Label 36: @110436 |
| 39562 | /* 110436 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 2072*/ GIMT_Encode4(111080), |
| 39563 | /* 110447 */ /*GILLT_s64*//*Label 2064*/ GIMT_Encode4(110503), GIMT_Encode4(0), |
| 39564 | /* 110455 */ /*GILLT_v2s32*//*Label 2065*/ GIMT_Encode4(110550), |
| 39565 | /* 110459 */ /*GILLT_v2s64*//*Label 2066*/ GIMT_Encode4(110597), GIMT_Encode4(0), |
| 39566 | /* 110467 */ /*GILLT_v4s16*//*Label 2067*/ GIMT_Encode4(110644), |
| 39567 | /* 110471 */ /*GILLT_v4s32*//*Label 2068*/ GIMT_Encode4(110691), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39568 | /* 110483 */ /*GILLT_v8s8*//*Label 2069*/ GIMT_Encode4(110805), |
| 39569 | /* 110487 */ /*GILLT_v8s16*//*Label 2070*/ GIMT_Encode4(110852), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39570 | /* 110499 */ /*GILLT_v16s8*//*Label 2071*/ GIMT_Encode4(110966), |
| 39571 | /* 110503 */ // Label 2064: @110503 |
| 39572 | /* 110503 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(110549), // Rule ID 949 // |
| 39573 | /* 110508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39574 | /* 110511 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39575 | /* 110514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39576 | /* 110517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39577 | /* 110521 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39578 | /* 110525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39579 | /* 110529 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 39580 | /* 110529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64), |
| 39581 | /* 110532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39582 | /* 110534 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39583 | /* 110536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39584 | /* 110538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39585 | /* 110541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39586 | /* 110547 */ GIR_RootConstrainSelectedInstOperands, |
| 39587 | /* 110548 */ // GIR_Coverage, 949, |
| 39588 | /* 110548 */ GIR_EraseRootFromParent_Done, |
| 39589 | /* 110549 */ // Label 2073: @110549 |
| 39590 | /* 110549 */ GIM_Reject, |
| 39591 | /* 110550 */ // Label 2065: @110550 |
| 39592 | /* 110550 */ GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(110596), // Rule ID 944 // |
| 39593 | /* 110555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39594 | /* 110558 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39595 | /* 110561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39596 | /* 110564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39597 | /* 110568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39598 | /* 110572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39599 | /* 110576 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 39600 | /* 110576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32), |
| 39601 | /* 110579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39602 | /* 110581 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39603 | /* 110583 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39604 | /* 110585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39605 | /* 110588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39606 | /* 110594 */ GIR_RootConstrainSelectedInstOperands, |
| 39607 | /* 110595 */ // GIR_Coverage, 944, |
| 39608 | /* 110595 */ GIR_EraseRootFromParent_Done, |
| 39609 | /* 110596 */ // Label 2074: @110596 |
| 39610 | /* 110596 */ GIM_Reject, |
| 39611 | /* 110597 */ // Label 2066: @110597 |
| 39612 | /* 110597 */ GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(110643), // Rule ID 950 // |
| 39613 | /* 110602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39614 | /* 110605 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 39615 | /* 110608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 39616 | /* 110611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39617 | /* 110615 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39618 | /* 110619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39619 | /* 110623 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 39620 | /* 110623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64), |
| 39621 | /* 110626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39622 | /* 110628 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39623 | /* 110630 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39624 | /* 110632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39625 | /* 110635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39626 | /* 110641 */ GIR_RootConstrainSelectedInstOperands, |
| 39627 | /* 110642 */ // GIR_Coverage, 950, |
| 39628 | /* 110642 */ GIR_EraseRootFromParent_Done, |
| 39629 | /* 110643 */ // Label 2075: @110643 |
| 39630 | /* 110643 */ GIM_Reject, |
| 39631 | /* 110644 */ // Label 2067: @110644 |
| 39632 | /* 110644 */ GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(110690), // Rule ID 943 // |
| 39633 | /* 110649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39634 | /* 110652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39635 | /* 110655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39636 | /* 110658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39637 | /* 110662 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39638 | /* 110666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39639 | /* 110670 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 39640 | /* 110670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16), |
| 39641 | /* 110673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39642 | /* 110675 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39643 | /* 110677 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39644 | /* 110679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39645 | /* 110682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39646 | /* 110688 */ GIR_RootConstrainSelectedInstOperands, |
| 39647 | /* 110689 */ // GIR_Coverage, 943, |
| 39648 | /* 110689 */ GIR_EraseRootFromParent_Done, |
| 39649 | /* 110690 */ // Label 2076: @110690 |
| 39650 | /* 110690 */ GIM_Reject, |
| 39651 | /* 110691 */ // Label 2068: @110691 |
| 39652 | /* 110691 */ GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(110804), |
| 39653 | /* 110696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39654 | /* 110699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39655 | /* 110702 */ GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(110742), // Rule ID 946 // |
| 39656 | /* 110707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39657 | /* 110710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39658 | /* 110714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39659 | /* 110718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39660 | /* 110722 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 39661 | /* 110722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32), |
| 39662 | /* 110725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39663 | /* 110727 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39664 | /* 110729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39665 | /* 110731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39666 | /* 110734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39667 | /* 110740 */ GIR_RootConstrainSelectedInstOperands, |
| 39668 | /* 110741 */ // GIR_Coverage, 946, |
| 39669 | /* 110741 */ GIR_EraseRootFromParent_Done, |
| 39670 | /* 110742 */ // Label 2078: @110742 |
| 39671 | /* 110742 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(110803), // Rule ID 3909 // |
| 39672 | /* 110747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39673 | /* 110750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39674 | /* 110754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39675 | /* 110758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39676 | /* 110762 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 39677 | /* 110762 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39678 | /* 110765 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39679 | /* 110769 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39680 | /* 110774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32), |
| 39681 | /* 110777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39682 | /* 110779 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39683 | /* 110781 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39684 | /* 110783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39685 | /* 110786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39686 | /* 110792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39687 | /* 110798 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39688 | /* 110801 */ GIR_RootConstrainSelectedInstOperands, |
| 39689 | /* 110802 */ // GIR_Coverage, 3909, |
| 39690 | /* 110802 */ GIR_EraseRootFromParent_Done, |
| 39691 | /* 110803 */ // Label 2079: @110803 |
| 39692 | /* 110803 */ GIM_Reject, |
| 39693 | /* 110804 */ // Label 2077: @110804 |
| 39694 | /* 110804 */ GIM_Reject, |
| 39695 | /* 110805 */ // Label 2069: @110805 |
| 39696 | /* 110805 */ GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(110851), // Rule ID 947 // |
| 39697 | /* 110810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39698 | /* 110813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 39699 | /* 110816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 39700 | /* 110819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39701 | /* 110823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39702 | /* 110827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39703 | /* 110831 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 39704 | /* 110831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8), |
| 39705 | /* 110834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39706 | /* 110836 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39707 | /* 110838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39708 | /* 110840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39709 | /* 110843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39710 | /* 110849 */ GIR_RootConstrainSelectedInstOperands, |
| 39711 | /* 110850 */ // GIR_Coverage, 947, |
| 39712 | /* 110850 */ GIR_EraseRootFromParent_Done, |
| 39713 | /* 110851 */ // Label 2080: @110851 |
| 39714 | /* 110851 */ GIM_Reject, |
| 39715 | /* 110852 */ // Label 2070: @110852 |
| 39716 | /* 110852 */ GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(110965), |
| 39717 | /* 110857 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39718 | /* 110860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39719 | /* 110863 */ GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(110903), // Rule ID 945 // |
| 39720 | /* 110868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39721 | /* 110871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39722 | /* 110875 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39723 | /* 110879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39724 | /* 110883 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 39725 | /* 110883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16), |
| 39726 | /* 110886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39727 | /* 110888 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39728 | /* 110890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39729 | /* 110892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39730 | /* 110895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39731 | /* 110901 */ GIR_RootConstrainSelectedInstOperands, |
| 39732 | /* 110902 */ // GIR_Coverage, 945, |
| 39733 | /* 110902 */ GIR_EraseRootFromParent_Done, |
| 39734 | /* 110903 */ // Label 2082: @110903 |
| 39735 | /* 110903 */ GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(110964), // Rule ID 3906 // |
| 39736 | /* 110908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39737 | /* 110911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39738 | /* 110915 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39739 | /* 110919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39740 | /* 110923 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 39741 | /* 110923 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39742 | /* 110926 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39743 | /* 110930 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39744 | /* 110935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16), |
| 39745 | /* 110938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39746 | /* 110940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39747 | /* 110942 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39748 | /* 110944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39749 | /* 110947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39750 | /* 110953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39751 | /* 110959 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39752 | /* 110962 */ GIR_RootConstrainSelectedInstOperands, |
| 39753 | /* 110963 */ // GIR_Coverage, 3906, |
| 39754 | /* 110963 */ GIR_EraseRootFromParent_Done, |
| 39755 | /* 110964 */ // Label 2083: @110964 |
| 39756 | /* 110964 */ GIM_Reject, |
| 39757 | /* 110965 */ // Label 2081: @110965 |
| 39758 | /* 110965 */ GIM_Reject, |
| 39759 | /* 110966 */ // Label 2071: @110966 |
| 39760 | /* 110966 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(111079), |
| 39761 | /* 110971 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 39762 | /* 110974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 39763 | /* 110977 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(111017), // Rule ID 948 // |
| 39764 | /* 110982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39765 | /* 110985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39766 | /* 110989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39767 | /* 110993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39768 | /* 110997 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 39769 | /* 110997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8), |
| 39770 | /* 111000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39771 | /* 111002 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39772 | /* 111004 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39773 | /* 111006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39774 | /* 111009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39775 | /* 111015 */ GIR_RootConstrainSelectedInstOperands, |
| 39776 | /* 111016 */ // GIR_Coverage, 948, |
| 39777 | /* 111016 */ GIR_EraseRootFromParent_Done, |
| 39778 | /* 111017 */ // Label 2085: @111017 |
| 39779 | /* 111017 */ GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(111078), // Rule ID 3903 // |
| 39780 | /* 111022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 39781 | /* 111025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39782 | /* 111029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39783 | /* 111033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39784 | /* 111037 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 39785 | /* 111037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39786 | /* 111040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39787 | /* 111044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39788 | /* 111049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8), |
| 39789 | /* 111052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39790 | /* 111054 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39791 | /* 111056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39792 | /* 111058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39793 | /* 111061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39794 | /* 111067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39795 | /* 111073 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39796 | /* 111076 */ GIR_RootConstrainSelectedInstOperands, |
| 39797 | /* 111077 */ // GIR_Coverage, 3903, |
| 39798 | /* 111077 */ GIR_EraseRootFromParent_Done, |
| 39799 | /* 111078 */ // Label 2086: @111078 |
| 39800 | /* 111078 */ GIM_Reject, |
| 39801 | /* 111079 */ // Label 2084: @111079 |
| 39802 | /* 111079 */ GIM_Reject, |
| 39803 | /* 111080 */ // Label 2072: @111080 |
| 39804 | /* 111080 */ GIM_Reject, |
| 39805 | /* 111081 */ // Label 37: @111081 |
| 39806 | /* 111081 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2096*/ GIMT_Encode4(112380), |
| 39807 | /* 111092 */ /*GILLT_s32*//*Label 2087*/ GIMT_Encode4(111152), |
| 39808 | /* 111096 */ /*GILLT_s64*//*Label 2088*/ GIMT_Encode4(111493), GIMT_Encode4(0), |
| 39809 | /* 111104 */ /*GILLT_v2s32*//*Label 2089*/ GIMT_Encode4(111540), |
| 39810 | /* 111108 */ /*GILLT_v2s64*//*Label 2090*/ GIMT_Encode4(111587), GIMT_Encode4(0), |
| 39811 | /* 111116 */ /*GILLT_v4s16*//*Label 2091*/ GIMT_Encode4(111788), |
| 39812 | /* 111120 */ /*GILLT_v4s32*//*Label 2092*/ GIMT_Encode4(111835), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39813 | /* 111132 */ /*GILLT_v8s8*//*Label 2093*/ GIMT_Encode4(112105), |
| 39814 | /* 111136 */ /*GILLT_v8s16*//*Label 2094*/ GIMT_Encode4(112152), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39815 | /* 111148 */ /*GILLT_v16s8*//*Label 2095*/ GIMT_Encode4(112266), |
| 39816 | /* 111152 */ // Label 2087: @111152 |
| 39817 | /* 111152 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(111492), |
| 39818 | /* 111157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39819 | /* 111160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39820 | /* 111163 */ GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(111225), // Rule ID 6234 // |
| 39821 | /* 111168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 39822 | /* 111171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 39823 | /* 111175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39824 | /* 111179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 39825 | /* 111183 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39826 | /* 111187 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39827 | /* 111192 */ // MIs[1] Rn |
| 39828 | /* 111192 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 39829 | /* 111197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39830 | /* 111201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39831 | /* 111203 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 39832 | /* 111203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 39833 | /* 111206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39834 | /* 111208 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39835 | /* 111210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 39836 | /* 111214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39837 | /* 111217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39838 | /* 111223 */ GIR_RootConstrainSelectedInstOperands, |
| 39839 | /* 111224 */ // GIR_Coverage, 6234, |
| 39840 | /* 111224 */ GIR_EraseRootFromParent_Done, |
| 39841 | /* 111225 */ // Label 2098: @111225 |
| 39842 | /* 111225 */ GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(111287), // Rule ID 6268 // |
| 39843 | /* 111230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 39844 | /* 111233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39845 | /* 111237 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39846 | /* 111241 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 39847 | /* 111245 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39848 | /* 111249 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39849 | /* 111254 */ // MIs[1] Rn |
| 39850 | /* 111254 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 39851 | /* 111259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39852 | /* 111263 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39853 | /* 111265 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 39854 | /* 111265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 39855 | /* 111268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39856 | /* 111270 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 39857 | /* 111272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 39858 | /* 111276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39859 | /* 111279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39860 | /* 111285 */ GIR_RootConstrainSelectedInstOperands, |
| 39861 | /* 111286 */ // GIR_Coverage, 6268, |
| 39862 | /* 111286 */ GIR_EraseRootFromParent_Done, |
| 39863 | /* 111287 */ // Label 2099: @111287 |
| 39864 | /* 111287 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(111349), // Rule ID 2055 // |
| 39865 | /* 111292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 39866 | /* 111295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 39867 | /* 111299 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39868 | /* 111303 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39869 | /* 111307 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 39870 | /* 111311 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39871 | /* 111315 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39872 | /* 111320 */ // MIs[1] Rn |
| 39873 | /* 111320 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 39874 | /* 111325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39875 | /* 111327 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 39876 | /* 111327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 39877 | /* 111330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39878 | /* 111332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 39879 | /* 111334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 39880 | /* 111338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39881 | /* 111341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39882 | /* 111347 */ GIR_RootConstrainSelectedInstOperands, |
| 39883 | /* 111348 */ // GIR_Coverage, 2055, |
| 39884 | /* 111348 */ GIR_EraseRootFromParent_Done, |
| 39885 | /* 111349 */ // Label 2100: @111349 |
| 39886 | /* 111349 */ GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(111411), // Rule ID 2321 // |
| 39887 | /* 111354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 39888 | /* 111357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39889 | /* 111361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39890 | /* 111365 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39891 | /* 111369 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 39892 | /* 111373 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39893 | /* 111377 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39894 | /* 111382 */ // MIs[1] Rn |
| 39895 | /* 111382 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 39896 | /* 111387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39897 | /* 111389 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 39898 | /* 111389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 39899 | /* 111392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39900 | /* 111394 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 39901 | /* 111396 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 39902 | /* 111400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39903 | /* 111403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39904 | /* 111409 */ GIR_RootConstrainSelectedInstOperands, |
| 39905 | /* 111410 */ // GIR_Coverage, 2321, |
| 39906 | /* 111410 */ GIR_EraseRootFromParent_Done, |
| 39907 | /* 111411 */ // Label 2101: @111411 |
| 39908 | /* 111411 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(111451), // Rule ID 2053 // |
| 39909 | /* 111416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 39910 | /* 111419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 39911 | /* 111423 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39912 | /* 111427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 39913 | /* 111431 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 39914 | /* 111431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 39915 | /* 111434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39916 | /* 111436 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 39917 | /* 111438 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 39918 | /* 111440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39919 | /* 111443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39920 | /* 111449 */ GIR_RootConstrainSelectedInstOperands, |
| 39921 | /* 111450 */ // GIR_Coverage, 2053, |
| 39922 | /* 111450 */ GIR_EraseRootFromParent_Done, |
| 39923 | /* 111451 */ // Label 2102: @111451 |
| 39924 | /* 111451 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(111491), // Rule ID 2319 // |
| 39925 | /* 111456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 39926 | /* 111459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39927 | /* 111463 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39928 | /* 111467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 39929 | /* 111471 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 39930 | /* 111471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 39931 | /* 111474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 39932 | /* 111476 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 39933 | /* 111478 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 39934 | /* 111480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39935 | /* 111483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39936 | /* 111489 */ GIR_RootConstrainSelectedInstOperands, |
| 39937 | /* 111490 */ // GIR_Coverage, 2319, |
| 39938 | /* 111490 */ GIR_EraseRootFromParent_Done, |
| 39939 | /* 111491 */ // Label 2103: @111491 |
| 39940 | /* 111491 */ GIM_Reject, |
| 39941 | /* 111492 */ // Label 2097: @111492 |
| 39942 | /* 111492 */ GIM_Reject, |
| 39943 | /* 111493 */ // Label 2088: @111493 |
| 39944 | /* 111493 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(111539), // Rule ID 941 // |
| 39945 | /* 111498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39946 | /* 111501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39947 | /* 111504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39948 | /* 111507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39949 | /* 111511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39950 | /* 111515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39951 | /* 111519 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 39952 | /* 111519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64), |
| 39953 | /* 111522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39954 | /* 111524 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39955 | /* 111526 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39956 | /* 111528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39957 | /* 111531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39958 | /* 111537 */ GIR_RootConstrainSelectedInstOperands, |
| 39959 | /* 111538 */ // GIR_Coverage, 941, |
| 39960 | /* 111538 */ GIR_EraseRootFromParent_Done, |
| 39961 | /* 111539 */ // Label 2104: @111539 |
| 39962 | /* 111539 */ GIM_Reject, |
| 39963 | /* 111540 */ // Label 2089: @111540 |
| 39964 | /* 111540 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(111586), // Rule ID 936 // |
| 39965 | /* 111545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39966 | /* 111548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39967 | /* 111551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39968 | /* 111554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39969 | /* 111558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39970 | /* 111562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39971 | /* 111566 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 39972 | /* 111566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32), |
| 39973 | /* 111569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39974 | /* 111571 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39975 | /* 111573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39976 | /* 111575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39977 | /* 111578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39978 | /* 111584 */ GIR_RootConstrainSelectedInstOperands, |
| 39979 | /* 111585 */ // GIR_Coverage, 936, |
| 39980 | /* 111585 */ GIR_EraseRootFromParent_Done, |
| 39981 | /* 111586 */ // Label 2105: @111586 |
| 39982 | /* 111586 */ GIM_Reject, |
| 39983 | /* 111587 */ // Label 2090: @111587 |
| 39984 | /* 111587 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(111787), |
| 39985 | /* 111592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 39986 | /* 111595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 39987 | /* 111598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39988 | /* 111602 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(111676), // Rule ID 6349 // |
| 39989 | /* 111607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39990 | /* 111610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39991 | /* 111614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 39992 | /* 111618 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39993 | /* 111621 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 39994 | /* 111626 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39995 | /* 111630 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39996 | /* 111634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39997 | /* 111639 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39998 | /* 111644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39999 | /* 111648 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40000 | /* 111650 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 4063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 40001 | /* 111650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 40002 | /* 111653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40003 | /* 111655 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 40004 | /* 111657 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 40005 | /* 111661 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 40006 | /* 111665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40007 | /* 111668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40008 | /* 111674 */ GIR_RootConstrainSelectedInstOperands, |
| 40009 | /* 111675 */ // GIR_Coverage, 6349, |
| 40010 | /* 111675 */ GIR_EraseRootFromParent_Done, |
| 40011 | /* 111676 */ // Label 2107: @111676 |
| 40012 | /* 111676 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(111750), // Rule ID 2858 // |
| 40013 | /* 111681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40014 | /* 111684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40015 | /* 111688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40016 | /* 111692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 40017 | /* 111696 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 40018 | /* 111699 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 40019 | /* 111704 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40020 | /* 111708 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 40021 | /* 111712 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40022 | /* 111717 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40023 | /* 111722 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40024 | /* 111724 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 40025 | /* 111724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 40026 | /* 111727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40027 | /* 111729 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 40028 | /* 111731 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 40029 | /* 111735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 40030 | /* 111739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40031 | /* 111742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40032 | /* 111748 */ GIR_RootConstrainSelectedInstOperands, |
| 40033 | /* 111749 */ // GIR_Coverage, 2858, |
| 40034 | /* 111749 */ GIR_EraseRootFromParent_Done, |
| 40035 | /* 111750 */ // Label 2108: @111750 |
| 40036 | /* 111750 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(111786), // Rule ID 942 // |
| 40037 | /* 111755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40038 | /* 111758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40039 | /* 111762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40040 | /* 111766 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 40041 | /* 111766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64), |
| 40042 | /* 111769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40043 | /* 111771 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40044 | /* 111773 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40045 | /* 111775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40046 | /* 111778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40047 | /* 111784 */ GIR_RootConstrainSelectedInstOperands, |
| 40048 | /* 111785 */ // GIR_Coverage, 942, |
| 40049 | /* 111785 */ GIR_EraseRootFromParent_Done, |
| 40050 | /* 111786 */ // Label 2109: @111786 |
| 40051 | /* 111786 */ GIM_Reject, |
| 40052 | /* 111787 */ // Label 2106: @111787 |
| 40053 | /* 111787 */ GIM_Reject, |
| 40054 | /* 111788 */ // Label 2091: @111788 |
| 40055 | /* 111788 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(111834), // Rule ID 935 // |
| 40056 | /* 111793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40057 | /* 111796 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40058 | /* 111799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 40059 | /* 111802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40060 | /* 111806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40061 | /* 111810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40062 | /* 111814 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 40063 | /* 111814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16), |
| 40064 | /* 111817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40065 | /* 111819 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40066 | /* 111821 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40067 | /* 111823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40068 | /* 111826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40069 | /* 111832 */ GIR_RootConstrainSelectedInstOperands, |
| 40070 | /* 111833 */ // GIR_Coverage, 935, |
| 40071 | /* 111833 */ GIR_EraseRootFromParent_Done, |
| 40072 | /* 111834 */ // Label 2110: @111834 |
| 40073 | /* 111834 */ GIM_Reject, |
| 40074 | /* 111835 */ // Label 2092: @111835 |
| 40075 | /* 111835 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(112104), |
| 40076 | /* 111840 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40077 | /* 111843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40078 | /* 111846 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(111924), // Rule ID 6348 // |
| 40079 | /* 111851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40080 | /* 111854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40081 | /* 111858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40082 | /* 111862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 40083 | /* 111866 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 40084 | /* 111869 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 40085 | /* 111874 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 40086 | /* 111878 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 40087 | /* 111882 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40088 | /* 111887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40089 | /* 111892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40090 | /* 111896 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40091 | /* 111898 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 4063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 40092 | /* 111898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 40093 | /* 111901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40094 | /* 111903 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 40095 | /* 111905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 40096 | /* 111909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 40097 | /* 111913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40098 | /* 111916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40099 | /* 111922 */ GIR_RootConstrainSelectedInstOperands, |
| 40100 | /* 111923 */ // GIR_Coverage, 6348, |
| 40101 | /* 111923 */ GIR_EraseRootFromParent_Done, |
| 40102 | /* 111924 */ // Label 2112: @111924 |
| 40103 | /* 111924 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(112002), // Rule ID 2857 // |
| 40104 | /* 111929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40105 | /* 111932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40106 | /* 111936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40107 | /* 111940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40108 | /* 111944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 40109 | /* 111948 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 40110 | /* 111951 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 40111 | /* 111956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 40112 | /* 111960 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 40113 | /* 111964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40114 | /* 111969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40115 | /* 111974 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40116 | /* 111976 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 40117 | /* 111976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 40118 | /* 111979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40119 | /* 111981 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 40120 | /* 111983 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 40121 | /* 111987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 40122 | /* 111991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40123 | /* 111994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40124 | /* 112000 */ GIR_RootConstrainSelectedInstOperands, |
| 40125 | /* 112001 */ // GIR_Coverage, 2857, |
| 40126 | /* 112001 */ GIR_EraseRootFromParent_Done, |
| 40127 | /* 112002 */ // Label 2113: @112002 |
| 40128 | /* 112002 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(112042), // Rule ID 938 // |
| 40129 | /* 112007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40130 | /* 112010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40131 | /* 112014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40132 | /* 112018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40133 | /* 112022 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 40134 | /* 112022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32), |
| 40135 | /* 112025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40136 | /* 112027 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40137 | /* 112029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40138 | /* 112031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40139 | /* 112034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40140 | /* 112040 */ GIR_RootConstrainSelectedInstOperands, |
| 40141 | /* 112041 */ // GIR_Coverage, 938, |
| 40142 | /* 112041 */ GIR_EraseRootFromParent_Done, |
| 40143 | /* 112042 */ // Label 2114: @112042 |
| 40144 | /* 112042 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(112103), // Rule ID 3900 // |
| 40145 | /* 112047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40146 | /* 112050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40147 | /* 112054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40148 | /* 112058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40149 | /* 112062 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 40150 | /* 112062 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40151 | /* 112065 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40152 | /* 112069 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40153 | /* 112074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32), |
| 40154 | /* 112077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40155 | /* 112079 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40156 | /* 112081 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40157 | /* 112083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40158 | /* 112086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40159 | /* 112092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40160 | /* 112098 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40161 | /* 112101 */ GIR_RootConstrainSelectedInstOperands, |
| 40162 | /* 112102 */ // GIR_Coverage, 3900, |
| 40163 | /* 112102 */ GIR_EraseRootFromParent_Done, |
| 40164 | /* 112103 */ // Label 2115: @112103 |
| 40165 | /* 112103 */ GIM_Reject, |
| 40166 | /* 112104 */ // Label 2111: @112104 |
| 40167 | /* 112104 */ GIM_Reject, |
| 40168 | /* 112105 */ // Label 2093: @112105 |
| 40169 | /* 112105 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(112151), // Rule ID 939 // |
| 40170 | /* 112110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40171 | /* 112113 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 40172 | /* 112116 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 40173 | /* 112119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40174 | /* 112123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40175 | /* 112127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40176 | /* 112131 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 40177 | /* 112131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8), |
| 40178 | /* 112134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40179 | /* 112136 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40180 | /* 112138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40181 | /* 112140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40182 | /* 112143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40183 | /* 112149 */ GIR_RootConstrainSelectedInstOperands, |
| 40184 | /* 112150 */ // GIR_Coverage, 939, |
| 40185 | /* 112150 */ GIR_EraseRootFromParent_Done, |
| 40186 | /* 112151 */ // Label 2116: @112151 |
| 40187 | /* 112151 */ GIM_Reject, |
| 40188 | /* 112152 */ // Label 2094: @112152 |
| 40189 | /* 112152 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(112265), |
| 40190 | /* 112157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40191 | /* 112160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40192 | /* 112163 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(112203), // Rule ID 937 // |
| 40193 | /* 112168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40194 | /* 112171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40195 | /* 112175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40196 | /* 112179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40197 | /* 112183 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 40198 | /* 112183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16), |
| 40199 | /* 112186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40200 | /* 112188 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40201 | /* 112190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40202 | /* 112192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40203 | /* 112195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40204 | /* 112201 */ GIR_RootConstrainSelectedInstOperands, |
| 40205 | /* 112202 */ // GIR_Coverage, 937, |
| 40206 | /* 112202 */ GIR_EraseRootFromParent_Done, |
| 40207 | /* 112203 */ // Label 2118: @112203 |
| 40208 | /* 112203 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(112264), // Rule ID 3897 // |
| 40209 | /* 112208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40210 | /* 112211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40211 | /* 112215 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40212 | /* 112219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40213 | /* 112223 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 40214 | /* 112223 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40215 | /* 112226 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40216 | /* 112230 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40217 | /* 112235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16), |
| 40218 | /* 112238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40219 | /* 112240 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40220 | /* 112242 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40221 | /* 112244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40222 | /* 112247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40223 | /* 112253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40224 | /* 112259 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40225 | /* 112262 */ GIR_RootConstrainSelectedInstOperands, |
| 40226 | /* 112263 */ // GIR_Coverage, 3897, |
| 40227 | /* 112263 */ GIR_EraseRootFromParent_Done, |
| 40228 | /* 112264 */ // Label 2119: @112264 |
| 40229 | /* 112264 */ GIM_Reject, |
| 40230 | /* 112265 */ // Label 2117: @112265 |
| 40231 | /* 112265 */ GIM_Reject, |
| 40232 | /* 112266 */ // Label 2095: @112266 |
| 40233 | /* 112266 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(112379), |
| 40234 | /* 112271 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 40235 | /* 112274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 40236 | /* 112277 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(112317), // Rule ID 940 // |
| 40237 | /* 112282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40238 | /* 112285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40239 | /* 112289 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40240 | /* 112293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40241 | /* 112297 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 40242 | /* 112297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8), |
| 40243 | /* 112300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40244 | /* 112302 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40245 | /* 112304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40246 | /* 112306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40247 | /* 112309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40248 | /* 112315 */ GIR_RootConstrainSelectedInstOperands, |
| 40249 | /* 112316 */ // GIR_Coverage, 940, |
| 40250 | /* 112316 */ GIR_EraseRootFromParent_Done, |
| 40251 | /* 112317 */ // Label 2121: @112317 |
| 40252 | /* 112317 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(112378), // Rule ID 3894 // |
| 40253 | /* 112322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40254 | /* 112325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40255 | /* 112329 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40256 | /* 112333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40257 | /* 112337 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 40258 | /* 112337 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40259 | /* 112340 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40260 | /* 112344 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40261 | /* 112349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8), |
| 40262 | /* 112352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40263 | /* 112354 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40264 | /* 112356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40265 | /* 112358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40266 | /* 112361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40267 | /* 112367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40268 | /* 112373 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40269 | /* 112376 */ GIR_RootConstrainSelectedInstOperands, |
| 40270 | /* 112377 */ // GIR_Coverage, 3894, |
| 40271 | /* 112377 */ GIR_EraseRootFromParent_Done, |
| 40272 | /* 112378 */ // Label 2122: @112378 |
| 40273 | /* 112378 */ GIM_Reject, |
| 40274 | /* 112379 */ // Label 2120: @112379 |
| 40275 | /* 112379 */ GIM_Reject, |
| 40276 | /* 112380 */ // Label 2096: @112380 |
| 40277 | /* 112380 */ GIM_Reject, |
| 40278 | /* 112381 */ // Label 38: @112381 |
| 40279 | /* 112381 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 2131*/ GIMT_Encode4(113025), |
| 40280 | /* 112392 */ /*GILLT_s64*//*Label 2123*/ GIMT_Encode4(112448), GIMT_Encode4(0), |
| 40281 | /* 112400 */ /*GILLT_v2s32*//*Label 2124*/ GIMT_Encode4(112495), |
| 40282 | /* 112404 */ /*GILLT_v2s64*//*Label 2125*/ GIMT_Encode4(112542), GIMT_Encode4(0), |
| 40283 | /* 112412 */ /*GILLT_v4s16*//*Label 2126*/ GIMT_Encode4(112589), |
| 40284 | /* 112416 */ /*GILLT_v4s32*//*Label 2127*/ GIMT_Encode4(112636), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40285 | /* 112428 */ /*GILLT_v8s8*//*Label 2128*/ GIMT_Encode4(112750), |
| 40286 | /* 112432 */ /*GILLT_v8s16*//*Label 2129*/ GIMT_Encode4(112797), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40287 | /* 112444 */ /*GILLT_v16s8*//*Label 2130*/ GIMT_Encode4(112911), |
| 40288 | /* 112448 */ // Label 2123: @112448 |
| 40289 | /* 112448 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(112494), // Rule ID 1183 // |
| 40290 | /* 112453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40291 | /* 112456 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40292 | /* 112459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 40293 | /* 112462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40294 | /* 112466 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40295 | /* 112470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40296 | /* 112474 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 40297 | /* 112474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64), |
| 40298 | /* 112477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40299 | /* 112479 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40300 | /* 112481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40301 | /* 112483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40302 | /* 112486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40303 | /* 112492 */ GIR_RootConstrainSelectedInstOperands, |
| 40304 | /* 112493 */ // GIR_Coverage, 1183, |
| 40305 | /* 112493 */ GIR_EraseRootFromParent_Done, |
| 40306 | /* 112494 */ // Label 2132: @112494 |
| 40307 | /* 112494 */ GIM_Reject, |
| 40308 | /* 112495 */ // Label 2124: @112495 |
| 40309 | /* 112495 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(112541), // Rule ID 1178 // |
| 40310 | /* 112500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40311 | /* 112503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40312 | /* 112506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40313 | /* 112509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40314 | /* 112513 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40315 | /* 112517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40316 | /* 112521 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 40317 | /* 112521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32), |
| 40318 | /* 112524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40319 | /* 112526 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40320 | /* 112528 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40321 | /* 112530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40322 | /* 112533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40323 | /* 112539 */ GIR_RootConstrainSelectedInstOperands, |
| 40324 | /* 112540 */ // GIR_Coverage, 1178, |
| 40325 | /* 112540 */ GIR_EraseRootFromParent_Done, |
| 40326 | /* 112541 */ // Label 2133: @112541 |
| 40327 | /* 112541 */ GIM_Reject, |
| 40328 | /* 112542 */ // Label 2125: @112542 |
| 40329 | /* 112542 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(112588), // Rule ID 1184 // |
| 40330 | /* 112547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40331 | /* 112550 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 40332 | /* 112553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40333 | /* 112556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40334 | /* 112560 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40335 | /* 112564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40336 | /* 112568 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 40337 | /* 112568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64), |
| 40338 | /* 112571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40339 | /* 112573 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40340 | /* 112575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40341 | /* 112577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40342 | /* 112580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40343 | /* 112586 */ GIR_RootConstrainSelectedInstOperands, |
| 40344 | /* 112587 */ // GIR_Coverage, 1184, |
| 40345 | /* 112587 */ GIR_EraseRootFromParent_Done, |
| 40346 | /* 112588 */ // Label 2134: @112588 |
| 40347 | /* 112588 */ GIM_Reject, |
| 40348 | /* 112589 */ // Label 2126: @112589 |
| 40349 | /* 112589 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(112635), // Rule ID 1177 // |
| 40350 | /* 112594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40351 | /* 112597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40352 | /* 112600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 40353 | /* 112603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40354 | /* 112607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40355 | /* 112611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40356 | /* 112615 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 40357 | /* 112615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16), |
| 40358 | /* 112618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40359 | /* 112620 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40360 | /* 112622 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40361 | /* 112624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40362 | /* 112627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40363 | /* 112633 */ GIR_RootConstrainSelectedInstOperands, |
| 40364 | /* 112634 */ // GIR_Coverage, 1177, |
| 40365 | /* 112634 */ GIR_EraseRootFromParent_Done, |
| 40366 | /* 112635 */ // Label 2135: @112635 |
| 40367 | /* 112635 */ GIM_Reject, |
| 40368 | /* 112636 */ // Label 2127: @112636 |
| 40369 | /* 112636 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(112749), |
| 40370 | /* 112641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40371 | /* 112644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40372 | /* 112647 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(112687), // Rule ID 1180 // |
| 40373 | /* 112652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40374 | /* 112655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40375 | /* 112659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40376 | /* 112663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40377 | /* 112667 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 40378 | /* 112667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32), |
| 40379 | /* 112670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40380 | /* 112672 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40381 | /* 112674 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40382 | /* 112676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40383 | /* 112679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40384 | /* 112685 */ GIR_RootConstrainSelectedInstOperands, |
| 40385 | /* 112686 */ // GIR_Coverage, 1180, |
| 40386 | /* 112686 */ GIR_EraseRootFromParent_Done, |
| 40387 | /* 112687 */ // Label 2137: @112687 |
| 40388 | /* 112687 */ GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(112748), // Rule ID 3927 // |
| 40389 | /* 112692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40390 | /* 112695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40391 | /* 112699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40392 | /* 112703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40393 | /* 112707 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 40394 | /* 112707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40395 | /* 112710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40396 | /* 112714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40397 | /* 112719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32), |
| 40398 | /* 112722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40399 | /* 112724 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40400 | /* 112726 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40401 | /* 112728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40402 | /* 112731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40403 | /* 112737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40404 | /* 112743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40405 | /* 112746 */ GIR_RootConstrainSelectedInstOperands, |
| 40406 | /* 112747 */ // GIR_Coverage, 3927, |
| 40407 | /* 112747 */ GIR_EraseRootFromParent_Done, |
| 40408 | /* 112748 */ // Label 2138: @112748 |
| 40409 | /* 112748 */ GIM_Reject, |
| 40410 | /* 112749 */ // Label 2136: @112749 |
| 40411 | /* 112749 */ GIM_Reject, |
| 40412 | /* 112750 */ // Label 2128: @112750 |
| 40413 | /* 112750 */ GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(112796), // Rule ID 1181 // |
| 40414 | /* 112755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40415 | /* 112758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 40416 | /* 112761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 40417 | /* 112764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40418 | /* 112768 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40419 | /* 112772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40420 | /* 112776 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 40421 | /* 112776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8), |
| 40422 | /* 112779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40423 | /* 112781 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40424 | /* 112783 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40425 | /* 112785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40426 | /* 112788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40427 | /* 112794 */ GIR_RootConstrainSelectedInstOperands, |
| 40428 | /* 112795 */ // GIR_Coverage, 1181, |
| 40429 | /* 112795 */ GIR_EraseRootFromParent_Done, |
| 40430 | /* 112796 */ // Label 2139: @112796 |
| 40431 | /* 112796 */ GIM_Reject, |
| 40432 | /* 112797 */ // Label 2129: @112797 |
| 40433 | /* 112797 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(112910), |
| 40434 | /* 112802 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40435 | /* 112805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40436 | /* 112808 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(112848), // Rule ID 1179 // |
| 40437 | /* 112813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40438 | /* 112816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40439 | /* 112820 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40440 | /* 112824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40441 | /* 112828 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 40442 | /* 112828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16), |
| 40443 | /* 112831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40444 | /* 112833 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40445 | /* 112835 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40446 | /* 112837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40447 | /* 112840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40448 | /* 112846 */ GIR_RootConstrainSelectedInstOperands, |
| 40449 | /* 112847 */ // GIR_Coverage, 1179, |
| 40450 | /* 112847 */ GIR_EraseRootFromParent_Done, |
| 40451 | /* 112848 */ // Label 2141: @112848 |
| 40452 | /* 112848 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(112909), // Rule ID 3924 // |
| 40453 | /* 112853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40454 | /* 112856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40455 | /* 112860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40456 | /* 112864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40457 | /* 112868 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 40458 | /* 112868 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40459 | /* 112871 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40460 | /* 112875 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40461 | /* 112880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16), |
| 40462 | /* 112883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40463 | /* 112885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40464 | /* 112887 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40465 | /* 112889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40466 | /* 112892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40467 | /* 112898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40468 | /* 112904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40469 | /* 112907 */ GIR_RootConstrainSelectedInstOperands, |
| 40470 | /* 112908 */ // GIR_Coverage, 3924, |
| 40471 | /* 112908 */ GIR_EraseRootFromParent_Done, |
| 40472 | /* 112909 */ // Label 2142: @112909 |
| 40473 | /* 112909 */ GIM_Reject, |
| 40474 | /* 112910 */ // Label 2140: @112910 |
| 40475 | /* 112910 */ GIM_Reject, |
| 40476 | /* 112911 */ // Label 2130: @112911 |
| 40477 | /* 112911 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(113024), |
| 40478 | /* 112916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 40479 | /* 112919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 40480 | /* 112922 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(112962), // Rule ID 1182 // |
| 40481 | /* 112927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40482 | /* 112930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40483 | /* 112934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40484 | /* 112938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40485 | /* 112942 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 40486 | /* 112942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8), |
| 40487 | /* 112945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40488 | /* 112947 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40489 | /* 112949 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40490 | /* 112951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40491 | /* 112954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40492 | /* 112960 */ GIR_RootConstrainSelectedInstOperands, |
| 40493 | /* 112961 */ // GIR_Coverage, 1182, |
| 40494 | /* 112961 */ GIR_EraseRootFromParent_Done, |
| 40495 | /* 112962 */ // Label 2144: @112962 |
| 40496 | /* 112962 */ GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(113023), // Rule ID 3921 // |
| 40497 | /* 112967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40498 | /* 112970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40499 | /* 112974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40500 | /* 112978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40501 | /* 112982 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 40502 | /* 112982 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40503 | /* 112985 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40504 | /* 112989 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40505 | /* 112994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8), |
| 40506 | /* 112997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40507 | /* 112999 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40508 | /* 113001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40509 | /* 113003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40510 | /* 113006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40511 | /* 113012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40512 | /* 113018 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40513 | /* 113021 */ GIR_RootConstrainSelectedInstOperands, |
| 40514 | /* 113022 */ // GIR_Coverage, 3921, |
| 40515 | /* 113022 */ GIR_EraseRootFromParent_Done, |
| 40516 | /* 113023 */ // Label 2145: @113023 |
| 40517 | /* 113023 */ GIM_Reject, |
| 40518 | /* 113024 */ // Label 2143: @113024 |
| 40519 | /* 113024 */ GIM_Reject, |
| 40520 | /* 113025 */ // Label 2131: @113025 |
| 40521 | /* 113025 */ GIM_Reject, |
| 40522 | /* 113026 */ // Label 39: @113026 |
| 40523 | /* 113026 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2155*/ GIMT_Encode4(114045), |
| 40524 | /* 113037 */ /*GILLT_s32*//*Label 2146*/ GIMT_Encode4(113097), |
| 40525 | /* 113041 */ /*GILLT_s64*//*Label 2147*/ GIMT_Encode4(113314), GIMT_Encode4(0), |
| 40526 | /* 113049 */ /*GILLT_v2s32*//*Label 2148*/ GIMT_Encode4(113361), |
| 40527 | /* 113053 */ /*GILLT_v2s64*//*Label 2149*/ GIMT_Encode4(113408), GIMT_Encode4(0), |
| 40528 | /* 113061 */ /*GILLT_v4s16*//*Label 2150*/ GIMT_Encode4(113531), |
| 40529 | /* 113065 */ /*GILLT_v4s32*//*Label 2151*/ GIMT_Encode4(113578), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40530 | /* 113077 */ /*GILLT_v8s8*//*Label 2152*/ GIMT_Encode4(113770), |
| 40531 | /* 113081 */ /*GILLT_v8s16*//*Label 2153*/ GIMT_Encode4(113817), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40532 | /* 113093 */ /*GILLT_v16s8*//*Label 2154*/ GIMT_Encode4(113931), |
| 40533 | /* 113097 */ // Label 2146: @113097 |
| 40534 | /* 113097 */ GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(113313), |
| 40535 | /* 113102 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40536 | /* 113105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 40537 | /* 113108 */ GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(113170), // Rule ID 2056 // |
| 40538 | /* 113113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 40539 | /* 113116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 40540 | /* 113120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40541 | /* 113124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40542 | /* 113128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 40543 | /* 113132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40544 | /* 113136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40545 | /* 113141 */ // MIs[1] Rn |
| 40546 | /* 113141 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 40547 | /* 113146 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40548 | /* 113148 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 40549 | /* 113148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 40550 | /* 113151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 40551 | /* 113153 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 40552 | /* 113155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 40553 | /* 113159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40554 | /* 113162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40555 | /* 113168 */ GIR_RootConstrainSelectedInstOperands, |
| 40556 | /* 113169 */ // GIR_Coverage, 2056, |
| 40557 | /* 113169 */ GIR_EraseRootFromParent_Done, |
| 40558 | /* 113170 */ // Label 2157: @113170 |
| 40559 | /* 113170 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(113232), // Rule ID 2322 // |
| 40560 | /* 113175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 40561 | /* 113178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40562 | /* 113182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40563 | /* 113186 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40564 | /* 113190 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 40565 | /* 113194 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40566 | /* 113198 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40567 | /* 113203 */ // MIs[1] Rn |
| 40568 | /* 113203 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 40569 | /* 113208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40570 | /* 113210 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 40571 | /* 113210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 40572 | /* 113213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 40573 | /* 113215 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 40574 | /* 113217 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 40575 | /* 113221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40576 | /* 113224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40577 | /* 113230 */ GIR_RootConstrainSelectedInstOperands, |
| 40578 | /* 113231 */ // GIR_Coverage, 2322, |
| 40579 | /* 113231 */ GIR_EraseRootFromParent_Done, |
| 40580 | /* 113232 */ // Label 2158: @113232 |
| 40581 | /* 113232 */ GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(113272), // Rule ID 2054 // |
| 40582 | /* 113237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 40583 | /* 113240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 40584 | /* 113244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40585 | /* 113248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40586 | /* 113252 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 40587 | /* 113252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 40588 | /* 113255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 40589 | /* 113257 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 40590 | /* 113259 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 40591 | /* 113261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40592 | /* 113264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40593 | /* 113270 */ GIR_RootConstrainSelectedInstOperands, |
| 40594 | /* 113271 */ // GIR_Coverage, 2054, |
| 40595 | /* 113271 */ GIR_EraseRootFromParent_Done, |
| 40596 | /* 113272 */ // Label 2159: @113272 |
| 40597 | /* 113272 */ GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(113312), // Rule ID 2320 // |
| 40598 | /* 113277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 40599 | /* 113280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40600 | /* 113284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40601 | /* 113288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 40602 | /* 113292 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 40603 | /* 113292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 40604 | /* 113295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 40605 | /* 113297 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 40606 | /* 113299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 40607 | /* 113301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40608 | /* 113304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40609 | /* 113310 */ GIR_RootConstrainSelectedInstOperands, |
| 40610 | /* 113311 */ // GIR_Coverage, 2320, |
| 40611 | /* 113311 */ GIR_EraseRootFromParent_Done, |
| 40612 | /* 113312 */ // Label 2160: @113312 |
| 40613 | /* 113312 */ GIM_Reject, |
| 40614 | /* 113313 */ // Label 2156: @113313 |
| 40615 | /* 113313 */ GIM_Reject, |
| 40616 | /* 113314 */ // Label 2147: @113314 |
| 40617 | /* 113314 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(113360), // Rule ID 1175 // |
| 40618 | /* 113319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40619 | /* 113322 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40620 | /* 113325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 40621 | /* 113328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40622 | /* 113332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40623 | /* 113336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40624 | /* 113340 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 40625 | /* 113340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64), |
| 40626 | /* 113343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40627 | /* 113345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40628 | /* 113347 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40629 | /* 113349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40630 | /* 113352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40631 | /* 113358 */ GIR_RootConstrainSelectedInstOperands, |
| 40632 | /* 113359 */ // GIR_Coverage, 1175, |
| 40633 | /* 113359 */ GIR_EraseRootFromParent_Done, |
| 40634 | /* 113360 */ // Label 2161: @113360 |
| 40635 | /* 113360 */ GIM_Reject, |
| 40636 | /* 113361 */ // Label 2148: @113361 |
| 40637 | /* 113361 */ GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(113407), // Rule ID 1170 // |
| 40638 | /* 113366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40639 | /* 113369 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40640 | /* 113372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40641 | /* 113375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40642 | /* 113379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40643 | /* 113383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40644 | /* 113387 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 40645 | /* 113387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32), |
| 40646 | /* 113390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40647 | /* 113392 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40648 | /* 113394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40649 | /* 113396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40650 | /* 113399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40651 | /* 113405 */ GIR_RootConstrainSelectedInstOperands, |
| 40652 | /* 113406 */ // GIR_Coverage, 1170, |
| 40653 | /* 113406 */ GIR_EraseRootFromParent_Done, |
| 40654 | /* 113407 */ // Label 2162: @113407 |
| 40655 | /* 113407 */ GIM_Reject, |
| 40656 | /* 113408 */ // Label 2149: @113408 |
| 40657 | /* 113408 */ GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(113530), |
| 40658 | /* 113413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 40659 | /* 113416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40660 | /* 113419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40661 | /* 113423 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40662 | /* 113427 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(113497), // Rule ID 2868 // |
| 40663 | /* 113432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40664 | /* 113435 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40665 | /* 113439 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 40666 | /* 113443 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 40667 | /* 113446 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 40668 | /* 113451 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40669 | /* 113455 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 40670 | /* 113459 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40671 | /* 113464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40672 | /* 113469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40673 | /* 113471 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 40674 | /* 113471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64), |
| 40675 | /* 113474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40676 | /* 113476 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 40677 | /* 113478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 40678 | /* 113482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 40679 | /* 113486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40680 | /* 113489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40681 | /* 113495 */ GIR_RootConstrainSelectedInstOperands, |
| 40682 | /* 113496 */ // GIR_Coverage, 2868, |
| 40683 | /* 113496 */ GIR_EraseRootFromParent_Done, |
| 40684 | /* 113497 */ // Label 2164: @113497 |
| 40685 | /* 113497 */ GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(113529), // Rule ID 1176 // |
| 40686 | /* 113502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40687 | /* 113505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40688 | /* 113509 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 40689 | /* 113509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64), |
| 40690 | /* 113512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40691 | /* 113514 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40692 | /* 113516 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40693 | /* 113518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40694 | /* 113521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40695 | /* 113527 */ GIR_RootConstrainSelectedInstOperands, |
| 40696 | /* 113528 */ // GIR_Coverage, 1176, |
| 40697 | /* 113528 */ GIR_EraseRootFromParent_Done, |
| 40698 | /* 113529 */ // Label 2165: @113529 |
| 40699 | /* 113529 */ GIM_Reject, |
| 40700 | /* 113530 */ // Label 2163: @113530 |
| 40701 | /* 113530 */ GIM_Reject, |
| 40702 | /* 113531 */ // Label 2150: @113531 |
| 40703 | /* 113531 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(113577), // Rule ID 1169 // |
| 40704 | /* 113536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40705 | /* 113539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40706 | /* 113542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 40707 | /* 113545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40708 | /* 113549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40709 | /* 113553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40710 | /* 113557 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 40711 | /* 113557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16), |
| 40712 | /* 113560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40713 | /* 113562 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40714 | /* 113564 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40715 | /* 113566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40716 | /* 113569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40717 | /* 113575 */ GIR_RootConstrainSelectedInstOperands, |
| 40718 | /* 113576 */ // GIR_Coverage, 1169, |
| 40719 | /* 113576 */ GIR_EraseRootFromParent_Done, |
| 40720 | /* 113577 */ // Label 2166: @113577 |
| 40721 | /* 113577 */ GIM_Reject, |
| 40722 | /* 113578 */ // Label 2151: @113578 |
| 40723 | /* 113578 */ GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(113769), |
| 40724 | /* 113583 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40725 | /* 113586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40726 | /* 113589 */ GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(113667), // Rule ID 2867 // |
| 40727 | /* 113594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40728 | /* 113597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40729 | /* 113601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40730 | /* 113605 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40731 | /* 113609 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 40732 | /* 113613 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 40733 | /* 113616 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 40734 | /* 113621 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 40735 | /* 113625 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 40736 | /* 113629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40737 | /* 113634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40738 | /* 113639 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40739 | /* 113641 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 40740 | /* 113641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32), |
| 40741 | /* 113644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40742 | /* 113646 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 40743 | /* 113648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 40744 | /* 113652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 40745 | /* 113656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40746 | /* 113659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40747 | /* 113665 */ GIR_RootConstrainSelectedInstOperands, |
| 40748 | /* 113666 */ // GIR_Coverage, 2867, |
| 40749 | /* 113666 */ GIR_EraseRootFromParent_Done, |
| 40750 | /* 113667 */ // Label 2168: @113667 |
| 40751 | /* 113667 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(113707), // Rule ID 1172 // |
| 40752 | /* 113672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40753 | /* 113675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40754 | /* 113679 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40755 | /* 113683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40756 | /* 113687 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 40757 | /* 113687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32), |
| 40758 | /* 113690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40759 | /* 113692 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40760 | /* 113694 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40761 | /* 113696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40762 | /* 113699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40763 | /* 113705 */ GIR_RootConstrainSelectedInstOperands, |
| 40764 | /* 113706 */ // GIR_Coverage, 1172, |
| 40765 | /* 113706 */ GIR_EraseRootFromParent_Done, |
| 40766 | /* 113707 */ // Label 2169: @113707 |
| 40767 | /* 113707 */ GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(113768), // Rule ID 3918 // |
| 40768 | /* 113712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40769 | /* 113715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40770 | /* 113719 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40771 | /* 113723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40772 | /* 113727 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 40773 | /* 113727 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40774 | /* 113730 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40775 | /* 113734 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40776 | /* 113739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32), |
| 40777 | /* 113742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40778 | /* 113744 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40779 | /* 113746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40780 | /* 113748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40781 | /* 113751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40782 | /* 113757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40783 | /* 113763 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40784 | /* 113766 */ GIR_RootConstrainSelectedInstOperands, |
| 40785 | /* 113767 */ // GIR_Coverage, 3918, |
| 40786 | /* 113767 */ GIR_EraseRootFromParent_Done, |
| 40787 | /* 113768 */ // Label 2170: @113768 |
| 40788 | /* 113768 */ GIM_Reject, |
| 40789 | /* 113769 */ // Label 2167: @113769 |
| 40790 | /* 113769 */ GIM_Reject, |
| 40791 | /* 113770 */ // Label 2152: @113770 |
| 40792 | /* 113770 */ GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(113816), // Rule ID 1173 // |
| 40793 | /* 113775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40794 | /* 113778 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 40795 | /* 113781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 40796 | /* 113784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40797 | /* 113788 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40798 | /* 113792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40799 | /* 113796 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 40800 | /* 113796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8), |
| 40801 | /* 113799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40802 | /* 113801 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40803 | /* 113803 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40804 | /* 113805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40805 | /* 113808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40806 | /* 113814 */ GIR_RootConstrainSelectedInstOperands, |
| 40807 | /* 113815 */ // GIR_Coverage, 1173, |
| 40808 | /* 113815 */ GIR_EraseRootFromParent_Done, |
| 40809 | /* 113816 */ // Label 2171: @113816 |
| 40810 | /* 113816 */ GIM_Reject, |
| 40811 | /* 113817 */ // Label 2153: @113817 |
| 40812 | /* 113817 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(113930), |
| 40813 | /* 113822 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40814 | /* 113825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40815 | /* 113828 */ GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(113868), // Rule ID 1171 // |
| 40816 | /* 113833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40817 | /* 113836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40818 | /* 113840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40819 | /* 113844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40820 | /* 113848 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 40821 | /* 113848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16), |
| 40822 | /* 113851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40823 | /* 113853 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40824 | /* 113855 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40825 | /* 113857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40826 | /* 113860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40827 | /* 113866 */ GIR_RootConstrainSelectedInstOperands, |
| 40828 | /* 113867 */ // GIR_Coverage, 1171, |
| 40829 | /* 113867 */ GIR_EraseRootFromParent_Done, |
| 40830 | /* 113868 */ // Label 2173: @113868 |
| 40831 | /* 113868 */ GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(113929), // Rule ID 3915 // |
| 40832 | /* 113873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40833 | /* 113876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40834 | /* 113880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40835 | /* 113884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40836 | /* 113888 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 40837 | /* 113888 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40838 | /* 113891 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40839 | /* 113895 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40840 | /* 113900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16), |
| 40841 | /* 113903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40842 | /* 113905 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40843 | /* 113907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40844 | /* 113909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40845 | /* 113912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40846 | /* 113918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40847 | /* 113924 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40848 | /* 113927 */ GIR_RootConstrainSelectedInstOperands, |
| 40849 | /* 113928 */ // GIR_Coverage, 3915, |
| 40850 | /* 113928 */ GIR_EraseRootFromParent_Done, |
| 40851 | /* 113929 */ // Label 2174: @113929 |
| 40852 | /* 113929 */ GIM_Reject, |
| 40853 | /* 113930 */ // Label 2172: @113930 |
| 40854 | /* 113930 */ GIM_Reject, |
| 40855 | /* 113931 */ // Label 2154: @113931 |
| 40856 | /* 113931 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(114044), |
| 40857 | /* 113936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 40858 | /* 113939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 40859 | /* 113942 */ GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(113982), // Rule ID 1174 // |
| 40860 | /* 113947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40861 | /* 113950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40862 | /* 113954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40863 | /* 113958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40864 | /* 113962 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 40865 | /* 113962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8), |
| 40866 | /* 113965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40867 | /* 113967 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40868 | /* 113969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40869 | /* 113971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40870 | /* 113974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40871 | /* 113980 */ GIR_RootConstrainSelectedInstOperands, |
| 40872 | /* 113981 */ // GIR_Coverage, 1174, |
| 40873 | /* 113981 */ GIR_EraseRootFromParent_Done, |
| 40874 | /* 113982 */ // Label 2176: @113982 |
| 40875 | /* 113982 */ GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(114043), // Rule ID 3912 // |
| 40876 | /* 113987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40877 | /* 113990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40878 | /* 113994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40879 | /* 113998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40880 | /* 114002 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 40881 | /* 114002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40882 | /* 114005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40883 | /* 114009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40884 | /* 114014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8), |
| 40885 | /* 114017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40886 | /* 114019 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 40887 | /* 114021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 40888 | /* 114023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40889 | /* 114026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40890 | /* 114032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40891 | /* 114038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40892 | /* 114041 */ GIR_RootConstrainSelectedInstOperands, |
| 40893 | /* 114042 */ // GIR_Coverage, 3912, |
| 40894 | /* 114042 */ GIR_EraseRootFromParent_Done, |
| 40895 | /* 114043 */ // Label 2177: @114043 |
| 40896 | /* 114043 */ GIM_Reject, |
| 40897 | /* 114044 */ // Label 2175: @114044 |
| 40898 | /* 114044 */ GIM_Reject, |
| 40899 | /* 114045 */ // Label 2155: @114045 |
| 40900 | /* 114045 */ GIM_Reject, |
| 40901 | /* 114046 */ // Label 40: @114046 |
| 40902 | /* 114046 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2185*/ GIMT_Encode4(116398), |
| 40903 | /* 114057 */ /*GILLT_s16*//*Label 2178*/ GIMT_Encode4(114109), |
| 40904 | /* 114061 */ /*GILLT_s32*//*Label 2179*/ GIMT_Encode4(114156), |
| 40905 | /* 114065 */ /*GILLT_s64*//*Label 2180*/ GIMT_Encode4(115751), GIMT_Encode4(0), |
| 40906 | /* 114073 */ /*GILLT_v2s32*//*Label 2181*/ GIMT_Encode4(115798), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40907 | /* 114085 */ /*GILLT_v4s16*//*Label 2182*/ GIMT_Encode4(115845), |
| 40908 | /* 114089 */ /*GILLT_v4s32*//*Label 2183*/ GIMT_Encode4(116030), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40909 | /* 114105 */ /*GILLT_v8s16*//*Label 2184*/ GIMT_Encode4(116144), |
| 40910 | /* 114109 */ // Label 2178: @114109 |
| 40911 | /* 114109 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(114155), // Rule ID 620 // |
| 40912 | /* 114114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40913 | /* 114117 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40914 | /* 114120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 40915 | /* 114123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40916 | /* 114127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40917 | /* 114131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40918 | /* 114135 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40919 | /* 114135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 40920 | /* 114138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40921 | /* 114140 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 40922 | /* 114142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 40923 | /* 114144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40924 | /* 114147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40925 | /* 114153 */ GIR_RootConstrainSelectedInstOperands, |
| 40926 | /* 114154 */ // GIR_Coverage, 620, |
| 40927 | /* 114154 */ GIR_EraseRootFromParent_Done, |
| 40928 | /* 114155 */ // Label 2186: @114155 |
| 40929 | /* 114155 */ GIM_Reject, |
| 40930 | /* 114156 */ // Label 2179: @114156 |
| 40931 | /* 114156 */ GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(115750), |
| 40932 | /* 114161 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40933 | /* 114164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 40934 | /* 114167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40935 | /* 114171 */ GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(114499), // Rule ID 6528 // |
| 40936 | /* 114176 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 40937 | /* 114179 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40938 | /* 114183 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40939 | /* 114187 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40940 | /* 114191 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40941 | /* 114195 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40942 | /* 114200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40943 | /* 114205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40944 | /* 114209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40945 | /* 114211 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 40946 | /* 114211 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 40947 | /* 114214 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40948 | /* 114218 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40949 | /* 114223 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 40950 | /* 114225 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 40951 | /* 114228 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40952 | /* 114232 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40953 | /* 114237 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 40954 | /* 114240 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40955 | /* 114245 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 40956 | /* 114248 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 40957 | /* 114252 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40958 | /* 114257 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 40959 | /* 114260 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 40960 | /* 114264 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 40961 | /* 114267 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40962 | /* 114272 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40963 | /* 114277 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 40964 | /* 114282 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 40965 | /* 114285 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40966 | /* 114289 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40967 | /* 114294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 40968 | /* 114296 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 40969 | /* 114299 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40970 | /* 114303 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40971 | /* 114308 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 40972 | /* 114311 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40973 | /* 114316 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 40974 | /* 114319 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 40975 | /* 114323 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40976 | /* 114328 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 40977 | /* 114331 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40978 | /* 114335 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 40979 | /* 114338 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40980 | /* 114343 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40981 | /* 114348 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 40982 | /* 114353 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 40983 | /* 114356 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40984 | /* 114360 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40985 | /* 114365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 40986 | /* 114367 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 40987 | /* 114370 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40988 | /* 114374 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40989 | /* 114379 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 40990 | /* 114382 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40991 | /* 114387 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 40992 | /* 114390 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 40993 | /* 114394 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40994 | /* 114399 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 40995 | /* 114402 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 40996 | /* 114406 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 40997 | /* 114409 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40998 | /* 114414 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40999 | /* 114419 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41000 | /* 114424 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41001 | /* 114427 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 41002 | /* 114431 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41003 | /* 114436 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41004 | /* 114439 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41005 | /* 114442 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 41006 | /* 114445 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41007 | /* 114448 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41008 | /* 114454 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41009 | /* 114456 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41010 | /* 114459 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41011 | /* 114463 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41012 | /* 114468 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41013 | /* 114471 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41014 | /* 114476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41015 | /* 114479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41016 | /* 114481 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41017 | /* 114488 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41018 | /* 114493 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41019 | /* 114498 */ // GIR_Coverage, 6528, |
| 41020 | /* 114498 */ GIR_EraseRootFromParent_Done, |
| 41021 | /* 114499 */ // Label 2188: @114499 |
| 41022 | /* 114499 */ GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(114827), // Rule ID 6529 // |
| 41023 | /* 114504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 41024 | /* 114507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41025 | /* 114511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41026 | /* 114515 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41027 | /* 114519 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 41028 | /* 114523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41029 | /* 114528 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41030 | /* 114533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41031 | /* 114537 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41032 | /* 114539 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41033 | /* 114539 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 41034 | /* 114542 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41035 | /* 114546 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41036 | /* 114551 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 41037 | /* 114553 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 41038 | /* 114556 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41039 | /* 114560 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41040 | /* 114565 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 41041 | /* 114568 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41042 | /* 114573 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 41043 | /* 114576 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41044 | /* 114580 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41045 | /* 114585 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 41046 | /* 114588 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 41047 | /* 114592 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 41048 | /* 114595 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41049 | /* 114600 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41050 | /* 114605 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41051 | /* 114610 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 41052 | /* 114613 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41053 | /* 114617 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41054 | /* 114622 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 41055 | /* 114624 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 41056 | /* 114627 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41057 | /* 114631 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41058 | /* 114636 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 41059 | /* 114639 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41060 | /* 114644 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 41061 | /* 114647 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41062 | /* 114651 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41063 | /* 114656 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 41064 | /* 114659 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41065 | /* 114663 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 41066 | /* 114666 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41067 | /* 114671 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41068 | /* 114676 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41069 | /* 114681 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41070 | /* 114684 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41071 | /* 114688 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41072 | /* 114693 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41073 | /* 114695 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41074 | /* 114698 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41075 | /* 114702 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41076 | /* 114707 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41077 | /* 114710 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41078 | /* 114715 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41079 | /* 114718 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41080 | /* 114722 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41081 | /* 114727 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41082 | /* 114730 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 41083 | /* 114734 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41084 | /* 114737 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41085 | /* 114742 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41086 | /* 114747 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41087 | /* 114752 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41088 | /* 114755 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 41089 | /* 114759 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41090 | /* 114764 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41091 | /* 114767 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41092 | /* 114770 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 41093 | /* 114773 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41094 | /* 114776 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41095 | /* 114782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41096 | /* 114784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41097 | /* 114787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41098 | /* 114791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41099 | /* 114796 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41100 | /* 114799 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41101 | /* 114804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41102 | /* 114807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41103 | /* 114809 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41104 | /* 114816 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41105 | /* 114821 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41106 | /* 114826 */ // GIR_Coverage, 6529, |
| 41107 | /* 114826 */ GIR_EraseRootFromParent_Done, |
| 41108 | /* 114827 */ // Label 2189: @114827 |
| 41109 | /* 114827 */ GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(115155), // Rule ID 3074 // |
| 41110 | /* 114832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 41111 | /* 114835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41112 | /* 114839 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41113 | /* 114843 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41114 | /* 114847 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41115 | /* 114851 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 41116 | /* 114855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41117 | /* 114860 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41118 | /* 114865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41119 | /* 114867 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41120 | /* 114867 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 41121 | /* 114870 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41122 | /* 114874 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41123 | /* 114879 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 41124 | /* 114881 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 41125 | /* 114884 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41126 | /* 114888 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41127 | /* 114893 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 41128 | /* 114896 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41129 | /* 114901 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 41130 | /* 114904 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41131 | /* 114908 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41132 | /* 114913 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 41133 | /* 114916 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 41134 | /* 114920 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 41135 | /* 114923 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41136 | /* 114928 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41137 | /* 114933 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41138 | /* 114938 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 41139 | /* 114941 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41140 | /* 114945 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41141 | /* 114950 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 41142 | /* 114952 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 41143 | /* 114955 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41144 | /* 114959 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41145 | /* 114964 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 41146 | /* 114967 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41147 | /* 114972 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 41148 | /* 114975 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41149 | /* 114979 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41150 | /* 114984 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 41151 | /* 114987 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41152 | /* 114991 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 41153 | /* 114994 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41154 | /* 114999 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41155 | /* 115004 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41156 | /* 115009 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41157 | /* 115012 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41158 | /* 115016 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41159 | /* 115021 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41160 | /* 115023 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41161 | /* 115026 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41162 | /* 115030 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41163 | /* 115035 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41164 | /* 115038 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41165 | /* 115043 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41166 | /* 115046 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41167 | /* 115050 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41168 | /* 115055 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41169 | /* 115058 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 41170 | /* 115062 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41171 | /* 115065 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41172 | /* 115070 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41173 | /* 115075 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41174 | /* 115080 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41175 | /* 115083 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 41176 | /* 115087 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41177 | /* 115092 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41178 | /* 115095 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41179 | /* 115098 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 41180 | /* 115101 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41181 | /* 115104 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41182 | /* 115110 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41183 | /* 115112 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41184 | /* 115115 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41185 | /* 115119 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41186 | /* 115124 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41187 | /* 115127 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41188 | /* 115132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41189 | /* 115135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41190 | /* 115137 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41191 | /* 115144 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41192 | /* 115149 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41193 | /* 115154 */ // GIR_Coverage, 3074, |
| 41194 | /* 115154 */ GIR_EraseRootFromParent_Done, |
| 41195 | /* 115155 */ // Label 2190: @115155 |
| 41196 | /* 115155 */ GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(115483), // Rule ID 3076 // |
| 41197 | /* 115160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 41198 | /* 115163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41199 | /* 115167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41200 | /* 115171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41201 | /* 115175 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41202 | /* 115179 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 41203 | /* 115183 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41204 | /* 115188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41205 | /* 115193 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41206 | /* 115195 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41207 | /* 115195 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 41208 | /* 115198 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41209 | /* 115202 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41210 | /* 115207 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 41211 | /* 115209 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 41212 | /* 115212 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41213 | /* 115216 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41214 | /* 115221 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 41215 | /* 115224 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41216 | /* 115229 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 41217 | /* 115232 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41218 | /* 115236 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41219 | /* 115241 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 41220 | /* 115244 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 41221 | /* 115248 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 41222 | /* 115251 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41223 | /* 115256 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41224 | /* 115261 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41225 | /* 115266 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 41226 | /* 115269 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41227 | /* 115273 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41228 | /* 115278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 41229 | /* 115280 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 41230 | /* 115283 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41231 | /* 115287 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41232 | /* 115292 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 41233 | /* 115295 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41234 | /* 115300 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 41235 | /* 115303 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41236 | /* 115307 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41237 | /* 115312 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 41238 | /* 115315 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41239 | /* 115319 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 41240 | /* 115322 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41241 | /* 115327 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41242 | /* 115332 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41243 | /* 115337 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41244 | /* 115340 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41245 | /* 115344 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41246 | /* 115349 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41247 | /* 115351 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41248 | /* 115354 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41249 | /* 115358 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41250 | /* 115363 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41251 | /* 115366 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41252 | /* 115371 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41253 | /* 115374 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41254 | /* 115378 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41255 | /* 115383 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41256 | /* 115386 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 41257 | /* 115390 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41258 | /* 115393 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41259 | /* 115398 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41260 | /* 115403 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41261 | /* 115408 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41262 | /* 115411 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 41263 | /* 115415 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41264 | /* 115420 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41265 | /* 115423 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41266 | /* 115426 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 41267 | /* 115429 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41268 | /* 115432 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41269 | /* 115438 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41270 | /* 115440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41271 | /* 115443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41272 | /* 115447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41273 | /* 115452 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41274 | /* 115455 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41275 | /* 115460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41276 | /* 115463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41277 | /* 115465 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41278 | /* 115472 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41279 | /* 115477 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41280 | /* 115482 */ // GIR_Coverage, 3076, |
| 41281 | /* 115482 */ GIR_EraseRootFromParent_Done, |
| 41282 | /* 115483 */ // Label 2191: @115483 |
| 41283 | /* 115483 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(115519), // Rule ID 618 // |
| 41284 | /* 115488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41285 | /* 115491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41286 | /* 115495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41287 | /* 115499 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 41288 | /* 115499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 41289 | /* 115502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41290 | /* 115504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 41291 | /* 115506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 41292 | /* 115508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41293 | /* 115511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41294 | /* 115517 */ GIR_RootConstrainSelectedInstOperands, |
| 41295 | /* 115518 */ // GIR_Coverage, 618, |
| 41296 | /* 115518 */ GIR_EraseRootFromParent_Done, |
| 41297 | /* 115519 */ // Label 2192: @115519 |
| 41298 | /* 115519 */ GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(115749), // Rule ID 3071 // |
| 41299 | /* 115524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 41300 | /* 115527 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41301 | /* 115531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41302 | /* 115535 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41303 | /* 115535 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 41304 | /* 115538 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41305 | /* 115542 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41306 | /* 115547 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 41307 | /* 115549 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 41308 | /* 115552 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41309 | /* 115556 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41310 | /* 115561 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 41311 | /* 115564 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41312 | /* 115569 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 41313 | /* 115572 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41314 | /* 115576 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41315 | /* 115581 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 41316 | /* 115584 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 41317 | /* 115588 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 41318 | /* 115591 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41319 | /* 115596 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41320 | /* 115601 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41321 | /* 115606 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41322 | /* 115609 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41323 | /* 115613 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41324 | /* 115618 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41325 | /* 115620 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41326 | /* 115623 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41327 | /* 115627 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41328 | /* 115632 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41329 | /* 115635 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41330 | /* 115640 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41331 | /* 115643 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41332 | /* 115647 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41333 | /* 115652 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41334 | /* 115655 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41335 | /* 115659 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41336 | /* 115662 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41337 | /* 115667 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41338 | /* 115672 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41339 | /* 115677 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41340 | /* 115680 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 41341 | /* 115684 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41342 | /* 115689 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41343 | /* 115692 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41344 | /* 115695 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41345 | /* 115698 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41346 | /* 115704 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41347 | /* 115706 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41348 | /* 115709 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41349 | /* 115713 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41350 | /* 115718 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41351 | /* 115721 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41352 | /* 115726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41353 | /* 115729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41354 | /* 115731 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41355 | /* 115738 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41356 | /* 115743 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41357 | /* 115748 */ // GIR_Coverage, 3071, |
| 41358 | /* 115748 */ GIR_EraseRootFromParent_Done, |
| 41359 | /* 115749 */ // Label 2193: @115749 |
| 41360 | /* 115749 */ GIM_Reject, |
| 41361 | /* 115750 */ // Label 2187: @115750 |
| 41362 | /* 115750 */ GIM_Reject, |
| 41363 | /* 115751 */ // Label 2180: @115751 |
| 41364 | /* 115751 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(115797), // Rule ID 616 // |
| 41365 | /* 115756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41366 | /* 115759 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41367 | /* 115762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 41368 | /* 115765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41369 | /* 115769 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41370 | /* 115773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41371 | /* 115777 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 41372 | /* 115777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 41373 | /* 115780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41374 | /* 115782 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 41375 | /* 115784 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 41376 | /* 115786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41377 | /* 115789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41378 | /* 115795 */ GIR_RootConstrainSelectedInstOperands, |
| 41379 | /* 115796 */ // GIR_Coverage, 616, |
| 41380 | /* 115796 */ GIR_EraseRootFromParent_Done, |
| 41381 | /* 115797 */ // Label 2194: @115797 |
| 41382 | /* 115797 */ GIM_Reject, |
| 41383 | /* 115798 */ // Label 2181: @115798 |
| 41384 | /* 115798 */ GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(115844), // Rule ID 883 // |
| 41385 | /* 115803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41386 | /* 115806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41387 | /* 115809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 41388 | /* 115812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41389 | /* 115816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41390 | /* 115820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41391 | /* 115824 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 41392 | /* 115824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 41393 | /* 115827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41394 | /* 115829 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 41395 | /* 115831 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 41396 | /* 115833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41397 | /* 115836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41398 | /* 115842 */ GIR_RootConstrainSelectedInstOperands, |
| 41399 | /* 115843 */ // GIR_Coverage, 883, |
| 41400 | /* 115843 */ GIR_EraseRootFromParent_Done, |
| 41401 | /* 115844 */ // Label 2195: @115844 |
| 41402 | /* 115844 */ GIM_Reject, |
| 41403 | /* 115845 */ // Label 2182: @115845 |
| 41404 | /* 115845 */ GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(116029), |
| 41405 | /* 115850 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41406 | /* 115853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41407 | /* 115856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41408 | /* 115860 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(115926), // Rule ID 6164 // |
| 41409 | /* 115865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 41410 | /* 115868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41411 | /* 115872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41412 | /* 115876 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41413 | /* 115880 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41414 | /* 115884 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41415 | /* 115889 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41416 | /* 115894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41417 | /* 115898 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41418 | /* 115900 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 41419 | /* 115900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 41420 | /* 115903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41421 | /* 115905 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 41422 | /* 115907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 41423 | /* 115911 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 41424 | /* 115915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41425 | /* 115918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41426 | /* 115924 */ GIR_RootConstrainSelectedInstOperands, |
| 41427 | /* 115925 */ // GIR_Coverage, 6164, |
| 41428 | /* 115925 */ GIR_EraseRootFromParent_Done, |
| 41429 | /* 115926 */ // Label 2197: @115926 |
| 41430 | /* 115926 */ GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(115992), // Rule ID 1100 // |
| 41431 | /* 115931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 41432 | /* 115934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41433 | /* 115938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41434 | /* 115942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41435 | /* 115946 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41436 | /* 115950 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41437 | /* 115954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41438 | /* 115959 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41439 | /* 115964 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41440 | /* 115966 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 41441 | /* 115966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 41442 | /* 115969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41443 | /* 115971 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 41444 | /* 115973 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 41445 | /* 115977 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 41446 | /* 115981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41447 | /* 115984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41448 | /* 115990 */ GIR_RootConstrainSelectedInstOperands, |
| 41449 | /* 115991 */ // GIR_Coverage, 1100, |
| 41450 | /* 115991 */ GIR_EraseRootFromParent_Done, |
| 41451 | /* 115992 */ // Label 2198: @115992 |
| 41452 | /* 115992 */ GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(116028), // Rule ID 885 // |
| 41453 | /* 115997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41454 | /* 116000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41455 | /* 116004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41456 | /* 116008 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 41457 | /* 116008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd), |
| 41458 | /* 116011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41459 | /* 116013 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 41460 | /* 116015 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 41461 | /* 116017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41462 | /* 116020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41463 | /* 116026 */ GIR_RootConstrainSelectedInstOperands, |
| 41464 | /* 116027 */ // GIR_Coverage, 885, |
| 41465 | /* 116027 */ GIR_EraseRootFromParent_Done, |
| 41466 | /* 116028 */ // Label 2199: @116028 |
| 41467 | /* 116028 */ GIM_Reject, |
| 41468 | /* 116029 */ // Label 2196: @116029 |
| 41469 | /* 116029 */ GIM_Reject, |
| 41470 | /* 116030 */ // Label 2183: @116030 |
| 41471 | /* 116030 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(116143), |
| 41472 | /* 116035 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41473 | /* 116038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 41474 | /* 116041 */ GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(116081), // Rule ID 884 // |
| 41475 | /* 116046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41476 | /* 116049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41477 | /* 116053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41478 | /* 116057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41479 | /* 116061 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 41480 | /* 116061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq), |
| 41481 | /* 116064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41482 | /* 116066 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 41483 | /* 116068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 41484 | /* 116070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41485 | /* 116073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41486 | /* 116079 */ GIR_RootConstrainSelectedInstOperands, |
| 41487 | /* 116080 */ // GIR_Coverage, 884, |
| 41488 | /* 116080 */ GIR_EraseRootFromParent_Done, |
| 41489 | /* 116081 */ // Label 2201: @116081 |
| 41490 | /* 116081 */ GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(116142), // Rule ID 4434 // |
| 41491 | /* 116086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41492 | /* 116089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41493 | /* 116093 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41494 | /* 116097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41495 | /* 116101 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 41496 | /* 116101 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41497 | /* 116104 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41498 | /* 116108 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41499 | /* 116113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 41500 | /* 116116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41501 | /* 116118 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 41502 | /* 116120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 41503 | /* 116122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41504 | /* 116125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41505 | /* 116131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41506 | /* 116137 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41507 | /* 116140 */ GIR_RootConstrainSelectedInstOperands, |
| 41508 | /* 116141 */ // GIR_Coverage, 4434, |
| 41509 | /* 116141 */ GIR_EraseRootFromParent_Done, |
| 41510 | /* 116142 */ // Label 2202: @116142 |
| 41511 | /* 116142 */ GIM_Reject, |
| 41512 | /* 116143 */ // Label 2200: @116143 |
| 41513 | /* 116143 */ GIM_Reject, |
| 41514 | /* 116144 */ // Label 2184: @116144 |
| 41515 | /* 116144 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(116397), |
| 41516 | /* 116149 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41517 | /* 116152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41518 | /* 116155 */ GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(116225), // Rule ID 6165 // |
| 41519 | /* 116160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 41520 | /* 116163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41521 | /* 116167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41522 | /* 116171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41523 | /* 116175 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41524 | /* 116179 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41525 | /* 116183 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41526 | /* 116188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41527 | /* 116193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41528 | /* 116197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41529 | /* 116199 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 41530 | /* 116199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 41531 | /* 116202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41532 | /* 116204 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 41533 | /* 116206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 41534 | /* 116210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 41535 | /* 116214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41536 | /* 116217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41537 | /* 116223 */ GIR_RootConstrainSelectedInstOperands, |
| 41538 | /* 116224 */ // GIR_Coverage, 6165, |
| 41539 | /* 116224 */ GIR_EraseRootFromParent_Done, |
| 41540 | /* 116225 */ // Label 2204: @116225 |
| 41541 | /* 116225 */ GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(116295), // Rule ID 1101 // |
| 41542 | /* 116230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 41543 | /* 116233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41544 | /* 116237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41545 | /* 116241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41546 | /* 116245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41547 | /* 116249 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41548 | /* 116253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41549 | /* 116257 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41550 | /* 116262 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41551 | /* 116267 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41552 | /* 116269 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 41553 | /* 116269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 41554 | /* 116272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41555 | /* 116274 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 41556 | /* 116276 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 41557 | /* 116280 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 41558 | /* 116284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41559 | /* 116287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41560 | /* 116293 */ GIR_RootConstrainSelectedInstOperands, |
| 41561 | /* 116294 */ // GIR_Coverage, 1101, |
| 41562 | /* 116294 */ GIR_EraseRootFromParent_Done, |
| 41563 | /* 116295 */ // Label 2205: @116295 |
| 41564 | /* 116295 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(116335), // Rule ID 886 // |
| 41565 | /* 116300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41566 | /* 116303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41567 | /* 116307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41568 | /* 116311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41569 | /* 116315 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 41570 | /* 116315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq), |
| 41571 | /* 116318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41572 | /* 116320 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 41573 | /* 116322 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 41574 | /* 116324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41575 | /* 116327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41576 | /* 116333 */ GIR_RootConstrainSelectedInstOperands, |
| 41577 | /* 116334 */ // GIR_Coverage, 886, |
| 41578 | /* 116334 */ GIR_EraseRootFromParent_Done, |
| 41579 | /* 116335 */ // Label 2206: @116335 |
| 41580 | /* 116335 */ GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(116396), // Rule ID 4441 // |
| 41581 | /* 116340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41582 | /* 116343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41583 | /* 116347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41584 | /* 116351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41585 | /* 116355 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 41586 | /* 116355 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41587 | /* 116358 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41588 | /* 116362 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41589 | /* 116367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 41590 | /* 116370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41591 | /* 116372 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 41592 | /* 116374 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 41593 | /* 116376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41594 | /* 116379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41595 | /* 116385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41596 | /* 116391 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41597 | /* 116394 */ GIR_RootConstrainSelectedInstOperands, |
| 41598 | /* 116395 */ // GIR_Coverage, 4441, |
| 41599 | /* 116395 */ GIR_EraseRootFromParent_Done, |
| 41600 | /* 116396 */ // Label 2207: @116396 |
| 41601 | /* 116396 */ GIM_Reject, |
| 41602 | /* 116397 */ // Label 2203: @116397 |
| 41603 | /* 116397 */ GIM_Reject, |
| 41604 | /* 116398 */ // Label 2185: @116398 |
| 41605 | /* 116398 */ GIM_Reject, |
| 41606 | /* 116399 */ // Label 41: @116399 |
| 41607 | /* 116399 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2215*/ GIMT_Encode4(118075), |
| 41608 | /* 116410 */ /*GILLT_s16*//*Label 2208*/ GIMT_Encode4(116462), |
| 41609 | /* 116414 */ /*GILLT_s32*//*Label 2209*/ GIMT_Encode4(116509), |
| 41610 | /* 116418 */ /*GILLT_s64*//*Label 2210*/ GIMT_Encode4(117436), GIMT_Encode4(0), |
| 41611 | /* 116426 */ /*GILLT_v2s32*//*Label 2211*/ GIMT_Encode4(117483), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41612 | /* 116438 */ /*GILLT_v4s16*//*Label 2212*/ GIMT_Encode4(117530), |
| 41613 | /* 116442 */ /*GILLT_v4s32*//*Label 2213*/ GIMT_Encode4(117707), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41614 | /* 116458 */ /*GILLT_v8s16*//*Label 2214*/ GIMT_Encode4(117821), |
| 41615 | /* 116462 */ // Label 2208: @116462 |
| 41616 | /* 116462 */ GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(116508), // Rule ID 626 // |
| 41617 | /* 116467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41618 | /* 116470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41619 | /* 116473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 41620 | /* 116476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41621 | /* 116480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41622 | /* 116484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41623 | /* 116488 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 41624 | /* 116488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 41625 | /* 116491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41626 | /* 116493 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 41627 | /* 116495 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 41628 | /* 116497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41629 | /* 116500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41630 | /* 116506 */ GIR_RootConstrainSelectedInstOperands, |
| 41631 | /* 116507 */ // GIR_Coverage, 626, |
| 41632 | /* 116507 */ GIR_EraseRootFromParent_Done, |
| 41633 | /* 116508 */ // Label 2216: @116508 |
| 41634 | /* 116508 */ GIM_Reject, |
| 41635 | /* 116509 */ // Label 2209: @116509 |
| 41636 | /* 116509 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(117435), |
| 41637 | /* 116514 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41638 | /* 116517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 41639 | /* 116520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41640 | /* 116524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41641 | /* 116528 */ GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(116852), // Rule ID 3075 // |
| 41642 | /* 116533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 41643 | /* 116536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41644 | /* 116540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41645 | /* 116544 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41646 | /* 116548 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 41647 | /* 116552 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41648 | /* 116557 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41649 | /* 116562 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41650 | /* 116564 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41651 | /* 116564 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 41652 | /* 116567 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41653 | /* 116571 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41654 | /* 116576 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 41655 | /* 116578 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 41656 | /* 116581 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41657 | /* 116585 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41658 | /* 116590 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 41659 | /* 116593 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41660 | /* 116598 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 41661 | /* 116601 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41662 | /* 116605 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41663 | /* 116610 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 41664 | /* 116613 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 41665 | /* 116617 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 41666 | /* 116620 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41667 | /* 116625 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41668 | /* 116630 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41669 | /* 116635 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 41670 | /* 116638 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41671 | /* 116642 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41672 | /* 116647 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 41673 | /* 116649 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 41674 | /* 116652 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41675 | /* 116656 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41676 | /* 116661 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 41677 | /* 116664 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41678 | /* 116669 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 41679 | /* 116672 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41680 | /* 116676 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41681 | /* 116681 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 41682 | /* 116684 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41683 | /* 116688 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 41684 | /* 116691 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41685 | /* 116696 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41686 | /* 116701 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41687 | /* 116706 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41688 | /* 116709 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41689 | /* 116713 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41690 | /* 116718 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41691 | /* 116720 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41692 | /* 116723 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41693 | /* 116727 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41694 | /* 116732 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41695 | /* 116735 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41696 | /* 116740 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41697 | /* 116743 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41698 | /* 116747 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41699 | /* 116752 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41700 | /* 116755 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 41701 | /* 116759 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41702 | /* 116762 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41703 | /* 116767 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41704 | /* 116772 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41705 | /* 116777 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41706 | /* 116780 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd), |
| 41707 | /* 116784 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41708 | /* 116789 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41709 | /* 116792 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41710 | /* 116795 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 41711 | /* 116798 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41712 | /* 116801 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41713 | /* 116807 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41714 | /* 116809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41715 | /* 116812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41716 | /* 116816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41717 | /* 116821 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41718 | /* 116824 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41719 | /* 116829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41720 | /* 116832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41721 | /* 116834 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41722 | /* 116841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41723 | /* 116846 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41724 | /* 116851 */ // GIR_Coverage, 3075, |
| 41725 | /* 116851 */ GIR_EraseRootFromParent_Done, |
| 41726 | /* 116852 */ // Label 2218: @116852 |
| 41727 | /* 116852 */ GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(117176), // Rule ID 3077 // |
| 41728 | /* 116857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 41729 | /* 116860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41730 | /* 116864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41731 | /* 116868 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41732 | /* 116872 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 41733 | /* 116876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41734 | /* 116881 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41735 | /* 116886 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41736 | /* 116888 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41737 | /* 116888 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 41738 | /* 116891 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41739 | /* 116895 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41740 | /* 116900 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 41741 | /* 116902 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 41742 | /* 116905 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41743 | /* 116909 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41744 | /* 116914 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 41745 | /* 116917 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41746 | /* 116922 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 41747 | /* 116925 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41748 | /* 116929 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41749 | /* 116934 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 41750 | /* 116937 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 41751 | /* 116941 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 41752 | /* 116944 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41753 | /* 116949 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41754 | /* 116954 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41755 | /* 116959 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 41756 | /* 116962 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41757 | /* 116966 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41758 | /* 116971 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 41759 | /* 116973 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 41760 | /* 116976 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41761 | /* 116980 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41762 | /* 116985 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 41763 | /* 116988 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41764 | /* 116993 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 41765 | /* 116996 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41766 | /* 117000 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41767 | /* 117005 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 41768 | /* 117008 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41769 | /* 117012 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 41770 | /* 117015 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41771 | /* 117020 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41772 | /* 117025 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41773 | /* 117030 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41774 | /* 117033 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41775 | /* 117037 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41776 | /* 117042 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41777 | /* 117044 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41778 | /* 117047 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41779 | /* 117051 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41780 | /* 117056 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41781 | /* 117059 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41782 | /* 117064 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41783 | /* 117067 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41784 | /* 117071 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41785 | /* 117076 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41786 | /* 117079 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 41787 | /* 117083 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41788 | /* 117086 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41789 | /* 117091 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41790 | /* 117096 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41791 | /* 117101 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41792 | /* 117104 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 41793 | /* 117108 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41794 | /* 117113 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41795 | /* 117116 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41796 | /* 117119 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 41797 | /* 117122 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41798 | /* 117125 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41799 | /* 117131 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41800 | /* 117133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41801 | /* 117136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41802 | /* 117140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41803 | /* 117145 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41804 | /* 117148 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41805 | /* 117153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41806 | /* 117156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41807 | /* 117158 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41808 | /* 117165 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41809 | /* 117170 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41810 | /* 117175 */ // GIR_Coverage, 3077, |
| 41811 | /* 117175 */ GIR_EraseRootFromParent_Done, |
| 41812 | /* 117176 */ // Label 2219: @117176 |
| 41813 | /* 117176 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(117208), // Rule ID 624 // |
| 41814 | /* 117181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41815 | /* 117184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41816 | /* 117188 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 41817 | /* 117188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 41818 | /* 117191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41819 | /* 117193 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 41820 | /* 117195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 41821 | /* 117197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41822 | /* 117200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41823 | /* 117206 */ GIR_RootConstrainSelectedInstOperands, |
| 41824 | /* 117207 */ // GIR_Coverage, 624, |
| 41825 | /* 117207 */ GIR_EraseRootFromParent_Done, |
| 41826 | /* 117208 */ // Label 2220: @117208 |
| 41827 | /* 117208 */ GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(117434), // Rule ID 3072 // |
| 41828 | /* 117213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 41829 | /* 117216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41830 | /* 117220 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41831 | /* 117220 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 41832 | /* 117223 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41833 | /* 117227 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41834 | /* 117232 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 41835 | /* 117234 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 41836 | /* 117237 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41837 | /* 117241 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41838 | /* 117246 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 41839 | /* 117249 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41840 | /* 117254 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 41841 | /* 117257 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41842 | /* 117261 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41843 | /* 117266 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 41844 | /* 117269 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 41845 | /* 117273 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 41846 | /* 117276 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41847 | /* 117281 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41848 | /* 117286 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41849 | /* 117291 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41850 | /* 117294 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41851 | /* 117298 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41852 | /* 117303 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41853 | /* 117305 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41854 | /* 117308 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41855 | /* 117312 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41856 | /* 117317 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41857 | /* 117320 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41858 | /* 117325 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41859 | /* 117328 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41860 | /* 117332 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41861 | /* 117337 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41862 | /* 117340 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41863 | /* 117344 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41864 | /* 117347 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41865 | /* 117352 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41866 | /* 117357 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41867 | /* 117362 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41868 | /* 117365 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 41869 | /* 117369 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41870 | /* 117374 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41871 | /* 117377 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 41872 | /* 117380 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41873 | /* 117383 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41874 | /* 117389 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41875 | /* 117391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41876 | /* 117394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41877 | /* 117398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41878 | /* 117403 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41879 | /* 117406 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41880 | /* 117411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41881 | /* 117414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41882 | /* 117416 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41883 | /* 117423 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41884 | /* 117428 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41885 | /* 117433 */ // GIR_Coverage, 3072, |
| 41886 | /* 117433 */ GIR_EraseRootFromParent_Done, |
| 41887 | /* 117434 */ // Label 2221: @117434 |
| 41888 | /* 117434 */ GIM_Reject, |
| 41889 | /* 117435 */ // Label 2217: @117435 |
| 41890 | /* 117435 */ GIM_Reject, |
| 41891 | /* 117436 */ // Label 2210: @117436 |
| 41892 | /* 117436 */ GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(117482), // Rule ID 622 // |
| 41893 | /* 117441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41894 | /* 117444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41895 | /* 117447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 41896 | /* 117450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41897 | /* 117454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41898 | /* 117458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41899 | /* 117462 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 41900 | /* 117462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 41901 | /* 117465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41902 | /* 117467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 41903 | /* 117469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 41904 | /* 117471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41905 | /* 117474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41906 | /* 117480 */ GIR_RootConstrainSelectedInstOperands, |
| 41907 | /* 117481 */ // GIR_Coverage, 622, |
| 41908 | /* 117481 */ GIR_EraseRootFromParent_Done, |
| 41909 | /* 117482 */ // Label 2222: @117482 |
| 41910 | /* 117482 */ GIM_Reject, |
| 41911 | /* 117483 */ // Label 2211: @117483 |
| 41912 | /* 117483 */ GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(117529), // Rule ID 1129 // |
| 41913 | /* 117488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41914 | /* 117491 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41915 | /* 117494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 41916 | /* 117497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41917 | /* 117501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41918 | /* 117505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41919 | /* 117509 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 41920 | /* 117509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 41921 | /* 117512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41922 | /* 117514 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 41923 | /* 117516 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 41924 | /* 117518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41925 | /* 117521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41926 | /* 117527 */ GIR_RootConstrainSelectedInstOperands, |
| 41927 | /* 117528 */ // GIR_Coverage, 1129, |
| 41928 | /* 117528 */ GIR_EraseRootFromParent_Done, |
| 41929 | /* 117529 */ // Label 2223: @117529 |
| 41930 | /* 117529 */ GIM_Reject, |
| 41931 | /* 117530 */ // Label 2212: @117530 |
| 41932 | /* 117530 */ GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(117706), |
| 41933 | /* 117535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41934 | /* 117538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41935 | /* 117541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41936 | /* 117545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41937 | /* 117549 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(117611), // Rule ID 1066 // |
| 41938 | /* 117554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), |
| 41939 | /* 117557 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41940 | /* 117561 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41941 | /* 117565 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41942 | /* 117569 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41943 | /* 117573 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41944 | /* 117578 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41945 | /* 117583 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41946 | /* 117585 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 41947 | /* 117585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd), |
| 41948 | /* 117588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41949 | /* 117590 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 41950 | /* 117592 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 41951 | /* 117596 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 41952 | /* 117600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41953 | /* 117603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41954 | /* 117609 */ GIR_RootConstrainSelectedInstOperands, |
| 41955 | /* 117610 */ // GIR_Coverage, 1066, |
| 41956 | /* 117610 */ GIR_EraseRootFromParent_Done, |
| 41957 | /* 117611 */ // Label 2225: @117611 |
| 41958 | /* 117611 */ GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(117673), // Rule ID 1110 // |
| 41959 | /* 117616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 41960 | /* 117619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 41961 | /* 117623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 41962 | /* 117627 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41963 | /* 117631 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41964 | /* 117635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41965 | /* 117640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41966 | /* 117645 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41967 | /* 117647 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 41968 | /* 117647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd), |
| 41969 | /* 117650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41970 | /* 117652 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 41971 | /* 117654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 41972 | /* 117658 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 41973 | /* 117662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41974 | /* 117665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41975 | /* 117671 */ GIR_RootConstrainSelectedInstOperands, |
| 41976 | /* 117672 */ // GIR_Coverage, 1110, |
| 41977 | /* 117672 */ GIR_EraseRootFromParent_Done, |
| 41978 | /* 117673 */ // Label 2226: @117673 |
| 41979 | /* 117673 */ GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(117705), // Rule ID 1131 // |
| 41980 | /* 117678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41981 | /* 117681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41982 | /* 117685 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 41983 | /* 117685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd), |
| 41984 | /* 117688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41985 | /* 117690 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 41986 | /* 117692 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 41987 | /* 117694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41988 | /* 117697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41989 | /* 117703 */ GIR_RootConstrainSelectedInstOperands, |
| 41990 | /* 117704 */ // GIR_Coverage, 1131, |
| 41991 | /* 117704 */ GIR_EraseRootFromParent_Done, |
| 41992 | /* 117705 */ // Label 2227: @117705 |
| 41993 | /* 117705 */ GIM_Reject, |
| 41994 | /* 117706 */ // Label 2224: @117706 |
| 41995 | /* 117706 */ GIM_Reject, |
| 41996 | /* 117707 */ // Label 2213: @117707 |
| 41997 | /* 117707 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(117820), |
| 41998 | /* 117712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41999 | /* 117715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42000 | /* 117718 */ GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(117758), // Rule ID 1130 // |
| 42001 | /* 117723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42002 | /* 117726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42003 | /* 117730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42004 | /* 117734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42005 | /* 117738 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42006 | /* 117738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq), |
| 42007 | /* 117741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42008 | /* 117743 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42009 | /* 117745 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42010 | /* 117747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42011 | /* 117750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42012 | /* 117756 */ GIR_RootConstrainSelectedInstOperands, |
| 42013 | /* 117757 */ // GIR_Coverage, 1130, |
| 42014 | /* 117757 */ GIR_EraseRootFromParent_Done, |
| 42015 | /* 117758 */ // Label 2229: @117758 |
| 42016 | /* 117758 */ GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(117819), // Rule ID 4448 // |
| 42017 | /* 117763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42018 | /* 117766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42019 | /* 117770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42020 | /* 117774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42021 | /* 117778 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42022 | /* 117778 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42023 | /* 117781 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42024 | /* 117785 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42025 | /* 117790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 42026 | /* 117793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42027 | /* 117795 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42028 | /* 117797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42029 | /* 117799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42030 | /* 117802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42031 | /* 117808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42032 | /* 117814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42033 | /* 117817 */ GIR_RootConstrainSelectedInstOperands, |
| 42034 | /* 117818 */ // GIR_Coverage, 4448, |
| 42035 | /* 117818 */ GIR_EraseRootFromParent_Done, |
| 42036 | /* 117819 */ // Label 2230: @117819 |
| 42037 | /* 117819 */ GIM_Reject, |
| 42038 | /* 117820 */ // Label 2228: @117820 |
| 42039 | /* 117820 */ GIM_Reject, |
| 42040 | /* 117821 */ // Label 2214: @117821 |
| 42041 | /* 117821 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(118074), |
| 42042 | /* 117826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42043 | /* 117829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42044 | /* 117832 */ GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(117902), // Rule ID 1067 // |
| 42045 | /* 117837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), |
| 42046 | /* 117840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42047 | /* 117844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42048 | /* 117848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42049 | /* 117852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 42050 | /* 117856 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42051 | /* 117860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42052 | /* 117864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42053 | /* 117869 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42054 | /* 117874 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42055 | /* 117876 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42056 | /* 117876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq), |
| 42057 | /* 117879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42058 | /* 117881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 42059 | /* 117883 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 42060 | /* 117887 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 42061 | /* 117891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42062 | /* 117894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42063 | /* 117900 */ GIR_RootConstrainSelectedInstOperands, |
| 42064 | /* 117901 */ // GIR_Coverage, 1067, |
| 42065 | /* 117901 */ GIR_EraseRootFromParent_Done, |
| 42066 | /* 117902 */ // Label 2232: @117902 |
| 42067 | /* 117902 */ GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(117972), // Rule ID 1111 // |
| 42068 | /* 117907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 42069 | /* 117910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42070 | /* 117914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42071 | /* 117918 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42072 | /* 117922 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 42073 | /* 117926 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42074 | /* 117930 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42075 | /* 117934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42076 | /* 117939 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42077 | /* 117944 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42078 | /* 117946 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42079 | /* 117946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq), |
| 42080 | /* 117949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42081 | /* 117951 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 42082 | /* 117953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 42083 | /* 117957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 42084 | /* 117961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42085 | /* 117964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42086 | /* 117970 */ GIR_RootConstrainSelectedInstOperands, |
| 42087 | /* 117971 */ // GIR_Coverage, 1111, |
| 42088 | /* 117971 */ GIR_EraseRootFromParent_Done, |
| 42089 | /* 117972 */ // Label 2233: @117972 |
| 42090 | /* 117972 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(118012), // Rule ID 1132 // |
| 42091 | /* 117977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42092 | /* 117980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42093 | /* 117984 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42094 | /* 117988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42095 | /* 117992 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42096 | /* 117992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq), |
| 42097 | /* 117995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42098 | /* 117997 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42099 | /* 117999 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42100 | /* 118001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42101 | /* 118004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42102 | /* 118010 */ GIR_RootConstrainSelectedInstOperands, |
| 42103 | /* 118011 */ // GIR_Coverage, 1132, |
| 42104 | /* 118011 */ GIR_EraseRootFromParent_Done, |
| 42105 | /* 118012 */ // Label 2234: @118012 |
| 42106 | /* 118012 */ GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(118073), // Rule ID 4455 // |
| 42107 | /* 118017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42108 | /* 118020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42109 | /* 118024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42110 | /* 118028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42111 | /* 118032 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42112 | /* 118032 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42113 | /* 118035 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42114 | /* 118039 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42115 | /* 118044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 42116 | /* 118047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42117 | /* 118049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42118 | /* 118051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42119 | /* 118053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42120 | /* 118056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42121 | /* 118062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42122 | /* 118068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42123 | /* 118071 */ GIR_RootConstrainSelectedInstOperands, |
| 42124 | /* 118072 */ // GIR_Coverage, 4455, |
| 42125 | /* 118072 */ GIR_EraseRootFromParent_Done, |
| 42126 | /* 118073 */ // Label 2235: @118073 |
| 42127 | /* 118073 */ GIM_Reject, |
| 42128 | /* 118074 */ // Label 2231: @118074 |
| 42129 | /* 118074 */ GIM_Reject, |
| 42130 | /* 118075 */ // Label 2215: @118075 |
| 42131 | /* 118075 */ GIM_Reject, |
| 42132 | /* 118076 */ // Label 42: @118076 |
| 42133 | /* 118076 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2243*/ GIMT_Encode4(119056), |
| 42134 | /* 118087 */ /*GILLT_s16*//*Label 2236*/ GIMT_Encode4(118139), |
| 42135 | /* 118091 */ /*GILLT_s32*//*Label 2237*/ GIMT_Encode4(118186), |
| 42136 | /* 118095 */ /*GILLT_s64*//*Label 2238*/ GIMT_Encode4(118575), GIMT_Encode4(0), |
| 42137 | /* 118103 */ /*GILLT_v2s32*//*Label 2239*/ GIMT_Encode4(118734), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42138 | /* 118115 */ /*GILLT_v4s16*//*Label 2240*/ GIMT_Encode4(118781), |
| 42139 | /* 118119 */ /*GILLT_v4s32*//*Label 2241*/ GIMT_Encode4(118828), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42140 | /* 118135 */ /*GILLT_v8s16*//*Label 2242*/ GIMT_Encode4(118942), |
| 42141 | /* 118139 */ // Label 2236: @118139 |
| 42142 | /* 118139 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(118185), // Rule ID 638 // |
| 42143 | /* 118144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42144 | /* 118147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42145 | /* 118150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42146 | /* 118153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42147 | /* 118157 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42148 | /* 118161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42149 | /* 118165 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42150 | /* 118165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 42151 | /* 118168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42152 | /* 118170 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 42153 | /* 118172 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42154 | /* 118174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42155 | /* 118177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42156 | /* 118183 */ GIR_RootConstrainSelectedInstOperands, |
| 42157 | /* 118184 */ // GIR_Coverage, 638, |
| 42158 | /* 118184 */ GIR_EraseRootFromParent_Done, |
| 42159 | /* 118185 */ // Label 2244: @118185 |
| 42160 | /* 118185 */ GIM_Reject, |
| 42161 | /* 118186 */ // Label 2237: @118186 |
| 42162 | /* 118186 */ GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(118574), |
| 42163 | /* 118191 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42164 | /* 118194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42165 | /* 118197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42166 | /* 118201 */ GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(118254), // Rule ID 2487 // |
| 42167 | /* 118206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), |
| 42168 | /* 118209 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42169 | /* 118213 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42170 | /* 118217 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 42171 | /* 118221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42172 | /* 118226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42173 | /* 118230 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42174 | /* 118232 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 42175 | /* 118232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 42176 | /* 118235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42177 | /* 118237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 42178 | /* 118241 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 42179 | /* 118243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42180 | /* 118246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42181 | /* 118252 */ GIR_RootConstrainSelectedInstOperands, |
| 42182 | /* 118253 */ // GIR_Coverage, 2487, |
| 42183 | /* 118253 */ GIR_EraseRootFromParent_Done, |
| 42184 | /* 118254 */ // Label 2246: @118254 |
| 42185 | /* 118254 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(118307), // Rule ID 6291 // |
| 42186 | /* 118259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), |
| 42187 | /* 118262 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42188 | /* 118266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42189 | /* 118270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42190 | /* 118274 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 42191 | /* 118278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42192 | /* 118283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42193 | /* 118285 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 42194 | /* 118285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 42195 | /* 118288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42196 | /* 118290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 42197 | /* 118294 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 42198 | /* 118296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42199 | /* 118299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42200 | /* 118305 */ GIR_RootConstrainSelectedInstOperands, |
| 42201 | /* 118306 */ // GIR_Coverage, 6291, |
| 42202 | /* 118306 */ GIR_EraseRootFromParent_Done, |
| 42203 | /* 118307 */ // Label 2247: @118307 |
| 42204 | /* 118307 */ GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(118343), // Rule ID 636 // |
| 42205 | /* 118312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 42206 | /* 118315 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42207 | /* 118319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42208 | /* 118323 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42209 | /* 118323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 42210 | /* 118326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42211 | /* 118328 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 42212 | /* 118330 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42213 | /* 118332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42214 | /* 118335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42215 | /* 118341 */ GIR_RootConstrainSelectedInstOperands, |
| 42216 | /* 118342 */ // GIR_Coverage, 636, |
| 42217 | /* 118342 */ GIR_EraseRootFromParent_Done, |
| 42218 | /* 118343 */ // Label 2248: @118343 |
| 42219 | /* 118343 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(118573), // Rule ID 3073 // |
| 42220 | /* 118348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 42221 | /* 118351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42222 | /* 118355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42223 | /* 118359 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42224 | /* 118359 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 42225 | /* 118362 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42226 | /* 118366 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42227 | /* 118371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 42228 | /* 118373 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 42229 | /* 118376 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42230 | /* 118380 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42231 | /* 118385 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 42232 | /* 118388 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42233 | /* 118393 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 42234 | /* 118396 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42235 | /* 118400 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42236 | /* 118405 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 42237 | /* 118408 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 42238 | /* 118412 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 42239 | /* 118415 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42240 | /* 118420 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42241 | /* 118425 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42242 | /* 118430 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 42243 | /* 118433 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42244 | /* 118437 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42245 | /* 118442 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42246 | /* 118444 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 42247 | /* 118447 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42248 | /* 118451 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42249 | /* 118456 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42250 | /* 118459 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42251 | /* 118464 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42252 | /* 118467 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42253 | /* 118471 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42254 | /* 118476 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42255 | /* 118479 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42256 | /* 118483 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42257 | /* 118486 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42258 | /* 118491 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42259 | /* 118496 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42260 | /* 118501 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42261 | /* 118504 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 42262 | /* 118508 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42263 | /* 118513 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42264 | /* 118516 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 42265 | /* 118519 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42266 | /* 118522 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42267 | /* 118528 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42268 | /* 118530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42269 | /* 118533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42270 | /* 118537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42271 | /* 118542 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42272 | /* 118545 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42273 | /* 118550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42274 | /* 118553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42275 | /* 118555 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42276 | /* 118562 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42277 | /* 118567 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42278 | /* 118572 */ // GIR_Coverage, 3073, |
| 42279 | /* 118572 */ GIR_EraseRootFromParent_Done, |
| 42280 | /* 118573 */ // Label 2249: @118573 |
| 42281 | /* 118573 */ GIM_Reject, |
| 42282 | /* 118574 */ // Label 2245: @118574 |
| 42283 | /* 118574 */ GIM_Reject, |
| 42284 | /* 118575 */ // Label 2238: @118575 |
| 42285 | /* 118575 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(118733), |
| 42286 | /* 118580 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42287 | /* 118583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42288 | /* 118586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42289 | /* 118590 */ GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(118643), // Rule ID 2486 // |
| 42290 | /* 118595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), |
| 42291 | /* 118598 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42292 | /* 118602 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42293 | /* 118606 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 42294 | /* 118610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42295 | /* 118615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42296 | /* 118619 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42297 | /* 118621 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 42298 | /* 118621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 42299 | /* 118624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42300 | /* 118626 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 42301 | /* 118630 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 42302 | /* 118632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42303 | /* 118635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42304 | /* 118641 */ GIR_RootConstrainSelectedInstOperands, |
| 42305 | /* 118642 */ // GIR_Coverage, 2486, |
| 42306 | /* 118642 */ GIR_EraseRootFromParent_Done, |
| 42307 | /* 118643 */ // Label 2251: @118643 |
| 42308 | /* 118643 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(118696), // Rule ID 6290 // |
| 42309 | /* 118648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), |
| 42310 | /* 118651 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42311 | /* 118655 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42312 | /* 118659 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42313 | /* 118663 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 42314 | /* 118667 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42315 | /* 118672 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42316 | /* 118674 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 42317 | /* 118674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 42318 | /* 118677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42319 | /* 118679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 42320 | /* 118683 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 42321 | /* 118685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42322 | /* 118688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42323 | /* 118694 */ GIR_RootConstrainSelectedInstOperands, |
| 42324 | /* 118695 */ // GIR_Coverage, 6290, |
| 42325 | /* 118695 */ GIR_EraseRootFromParent_Done, |
| 42326 | /* 118696 */ // Label 2252: @118696 |
| 42327 | /* 118696 */ GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(118732), // Rule ID 634 // |
| 42328 | /* 118701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 42329 | /* 118704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42330 | /* 118708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42331 | /* 118712 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42332 | /* 118712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 42333 | /* 118715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42334 | /* 118717 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 42335 | /* 118719 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 42336 | /* 118721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42337 | /* 118724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42338 | /* 118730 */ GIR_RootConstrainSelectedInstOperands, |
| 42339 | /* 118731 */ // GIR_Coverage, 634, |
| 42340 | /* 118731 */ GIR_EraseRootFromParent_Done, |
| 42341 | /* 118732 */ // Label 2253: @118732 |
| 42342 | /* 118732 */ GIM_Reject, |
| 42343 | /* 118733 */ // Label 2250: @118733 |
| 42344 | /* 118733 */ GIM_Reject, |
| 42345 | /* 118734 */ // Label 2239: @118734 |
| 42346 | /* 118734 */ GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(118780), // Rule ID 962 // |
| 42347 | /* 118739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42348 | /* 118742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42349 | /* 118745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42350 | /* 118748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42351 | /* 118752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42352 | /* 118756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42353 | /* 118760 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42354 | /* 118760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 42355 | /* 118763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42356 | /* 118765 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42357 | /* 118767 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42358 | /* 118769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42359 | /* 118772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42360 | /* 118778 */ GIR_RootConstrainSelectedInstOperands, |
| 42361 | /* 118779 */ // GIR_Coverage, 962, |
| 42362 | /* 118779 */ GIR_EraseRootFromParent_Done, |
| 42363 | /* 118780 */ // Label 2254: @118780 |
| 42364 | /* 118780 */ GIM_Reject, |
| 42365 | /* 118781 */ // Label 2240: @118781 |
| 42366 | /* 118781 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(118827), // Rule ID 964 // |
| 42367 | /* 118786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42368 | /* 118789 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42369 | /* 118792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42370 | /* 118795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42371 | /* 118799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42372 | /* 118803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42373 | /* 118807 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 42374 | /* 118807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd), |
| 42375 | /* 118810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42376 | /* 118812 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42377 | /* 118814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42378 | /* 118816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42379 | /* 118819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42380 | /* 118825 */ GIR_RootConstrainSelectedInstOperands, |
| 42381 | /* 118826 */ // GIR_Coverage, 964, |
| 42382 | /* 118826 */ GIR_EraseRootFromParent_Done, |
| 42383 | /* 118827 */ // Label 2255: @118827 |
| 42384 | /* 118827 */ GIM_Reject, |
| 42385 | /* 118828 */ // Label 2241: @118828 |
| 42386 | /* 118828 */ GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(118941), |
| 42387 | /* 118833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42388 | /* 118836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42389 | /* 118839 */ GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(118879), // Rule ID 963 // |
| 42390 | /* 118844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42391 | /* 118847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42392 | /* 118851 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42393 | /* 118855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42394 | /* 118859 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42395 | /* 118859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq), |
| 42396 | /* 118862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42397 | /* 118864 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42398 | /* 118866 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42399 | /* 118868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42400 | /* 118871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42401 | /* 118877 */ GIR_RootConstrainSelectedInstOperands, |
| 42402 | /* 118878 */ // GIR_Coverage, 963, |
| 42403 | /* 118878 */ GIR_EraseRootFromParent_Done, |
| 42404 | /* 118879 */ // Label 2257: @118879 |
| 42405 | /* 118879 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(118940), // Rule ID 4394 // |
| 42406 | /* 118884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42407 | /* 118887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42408 | /* 118891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42409 | /* 118895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42410 | /* 118899 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42411 | /* 118899 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42412 | /* 118902 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42413 | /* 118906 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42414 | /* 118911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 42415 | /* 118914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42416 | /* 118916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42417 | /* 118918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42418 | /* 118920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42419 | /* 118923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42420 | /* 118929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42421 | /* 118935 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42422 | /* 118938 */ GIR_RootConstrainSelectedInstOperands, |
| 42423 | /* 118939 */ // GIR_Coverage, 4394, |
| 42424 | /* 118939 */ GIR_EraseRootFromParent_Done, |
| 42425 | /* 118940 */ // Label 2258: @118940 |
| 42426 | /* 118940 */ GIM_Reject, |
| 42427 | /* 118941 */ // Label 2256: @118941 |
| 42428 | /* 118941 */ GIM_Reject, |
| 42429 | /* 118942 */ // Label 2242: @118942 |
| 42430 | /* 118942 */ GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(119055), |
| 42431 | /* 118947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42432 | /* 118950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42433 | /* 118953 */ GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(118993), // Rule ID 965 // |
| 42434 | /* 118958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42435 | /* 118961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42436 | /* 118965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42437 | /* 118969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42438 | /* 118973 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42439 | /* 118973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq), |
| 42440 | /* 118976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42441 | /* 118978 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42442 | /* 118980 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42443 | /* 118982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42444 | /* 118985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42445 | /* 118991 */ GIR_RootConstrainSelectedInstOperands, |
| 42446 | /* 118992 */ // GIR_Coverage, 965, |
| 42447 | /* 118992 */ GIR_EraseRootFromParent_Done, |
| 42448 | /* 118993 */ // Label 2260: @118993 |
| 42449 | /* 118993 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(119054), // Rule ID 4401 // |
| 42450 | /* 118998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42451 | /* 119001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42452 | /* 119005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42453 | /* 119009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42454 | /* 119013 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42455 | /* 119013 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42456 | /* 119016 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42457 | /* 119020 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42458 | /* 119025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 42459 | /* 119028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42460 | /* 119030 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42461 | /* 119032 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42462 | /* 119034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42463 | /* 119037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42464 | /* 119043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42465 | /* 119049 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42466 | /* 119052 */ GIR_RootConstrainSelectedInstOperands, |
| 42467 | /* 119053 */ // GIR_Coverage, 4401, |
| 42468 | /* 119053 */ GIR_EraseRootFromParent_Done, |
| 42469 | /* 119054 */ // Label 2261: @119054 |
| 42470 | /* 119054 */ GIM_Reject, |
| 42471 | /* 119055 */ // Label 2259: @119055 |
| 42472 | /* 119055 */ GIM_Reject, |
| 42473 | /* 119056 */ // Label 2243: @119056 |
| 42474 | /* 119056 */ GIM_Reject, |
| 42475 | /* 119057 */ // Label 43: @119057 |
| 42476 | /* 119057 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2269*/ GIMT_Encode4(121147), |
| 42477 | /* 119068 */ /*GILLT_s16*//*Label 2262*/ GIMT_Encode4(119120), |
| 42478 | /* 119072 */ /*GILLT_s32*//*Label 2263*/ GIMT_Encode4(119507), |
| 42479 | /* 119076 */ /*GILLT_s64*//*Label 2264*/ GIMT_Encode4(119894), GIMT_Encode4(0), |
| 42480 | /* 119084 */ /*GILLT_v2s32*//*Label 2265*/ GIMT_Encode4(120281), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42481 | /* 119096 */ /*GILLT_v4s16*//*Label 2266*/ GIMT_Encode4(120461), |
| 42482 | /* 119100 */ /*GILLT_v4s32*//*Label 2267*/ GIMT_Encode4(120517), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42483 | /* 119116 */ /*GILLT_v8s16*//*Label 2268*/ GIMT_Encode4(120895), |
| 42484 | /* 119120 */ // Label 2262: @119120 |
| 42485 | /* 119120 */ GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(119506), |
| 42486 | /* 119125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42487 | /* 119128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42488 | /* 119131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 42489 | /* 119134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42490 | /* 119138 */ GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(119212), // Rule ID 2760 // |
| 42491 | /* 119143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42492 | /* 119146 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42493 | /* 119150 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42494 | /* 119154 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 42495 | /* 119158 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42496 | /* 119163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42497 | /* 119167 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 42498 | /* 119171 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42499 | /* 119175 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 42500 | /* 119179 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42501 | /* 119184 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42502 | /* 119186 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42503 | /* 119186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 42504 | /* 119189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42505 | /* 119191 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 42506 | /* 119195 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42507 | /* 119199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42508 | /* 119201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42509 | /* 119204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42510 | /* 119210 */ GIR_RootConstrainSelectedInstOperands, |
| 42511 | /* 119211 */ // GIR_Coverage, 2760, |
| 42512 | /* 119211 */ GIR_EraseRootFromParent_Done, |
| 42513 | /* 119212 */ // Label 2271: @119212 |
| 42514 | /* 119212 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(119286), // Rule ID 6311 // |
| 42515 | /* 119217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42516 | /* 119220 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42517 | /* 119224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42518 | /* 119228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42519 | /* 119232 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 42520 | /* 119236 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42521 | /* 119241 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 42522 | /* 119245 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42523 | /* 119249 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 42524 | /* 119253 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42525 | /* 119258 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42526 | /* 119260 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42527 | /* 119260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 42528 | /* 119263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42529 | /* 119265 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 42530 | /* 119269 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42531 | /* 119273 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42532 | /* 119275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42533 | /* 119278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42534 | /* 119284 */ GIR_RootConstrainSelectedInstOperands, |
| 42535 | /* 119285 */ // GIR_Coverage, 6311, |
| 42536 | /* 119285 */ GIR_EraseRootFromParent_Done, |
| 42537 | /* 119286 */ // Label 2272: @119286 |
| 42538 | /* 119286 */ GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(119345), // Rule ID 2740 // |
| 42539 | /* 119291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42540 | /* 119294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42541 | /* 119298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42542 | /* 119302 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 42543 | /* 119306 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42544 | /* 119311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42545 | /* 119315 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42546 | /* 119319 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42547 | /* 119321 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42548 | /* 119321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 42549 | /* 119324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42550 | /* 119326 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 42551 | /* 119328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42552 | /* 119332 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42553 | /* 119334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42554 | /* 119337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42555 | /* 119343 */ GIR_RootConstrainSelectedInstOperands, |
| 42556 | /* 119344 */ // GIR_Coverage, 2740, |
| 42557 | /* 119344 */ GIR_EraseRootFromParent_Done, |
| 42558 | /* 119345 */ // Label 2273: @119345 |
| 42559 | /* 119345 */ GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(119404), // Rule ID 6305 // |
| 42560 | /* 119350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42561 | /* 119353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42562 | /* 119357 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42563 | /* 119361 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42564 | /* 119365 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 42565 | /* 119369 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42566 | /* 119374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42567 | /* 119378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42568 | /* 119380 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42569 | /* 119380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 42570 | /* 119383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42571 | /* 119385 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 42572 | /* 119387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42573 | /* 119391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42574 | /* 119393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42575 | /* 119396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42576 | /* 119402 */ GIR_RootConstrainSelectedInstOperands, |
| 42577 | /* 119403 */ // GIR_Coverage, 6305, |
| 42578 | /* 119403 */ GIR_EraseRootFromParent_Done, |
| 42579 | /* 119404 */ // Label 2274: @119404 |
| 42580 | /* 119404 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(119463), // Rule ID 2774 // |
| 42581 | /* 119409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42582 | /* 119412 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42583 | /* 119416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42584 | /* 119420 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 42585 | /* 119424 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42586 | /* 119428 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 42587 | /* 119432 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42588 | /* 119437 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42589 | /* 119439 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42590 | /* 119439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 42591 | /* 119442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42592 | /* 119444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 42593 | /* 119448 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 42594 | /* 119450 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42595 | /* 119452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42596 | /* 119455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42597 | /* 119461 */ GIR_RootConstrainSelectedInstOperands, |
| 42598 | /* 119462 */ // GIR_Coverage, 2774, |
| 42599 | /* 119462 */ GIR_EraseRootFromParent_Done, |
| 42600 | /* 119463 */ // Label 2275: @119463 |
| 42601 | /* 119463 */ GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(119505), // Rule ID 2722 // |
| 42602 | /* 119468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42603 | /* 119471 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42604 | /* 119475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42605 | /* 119479 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42606 | /* 119483 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42607 | /* 119483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 42608 | /* 119486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42609 | /* 119488 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 42610 | /* 119490 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 42611 | /* 119492 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42612 | /* 119494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42613 | /* 119497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42614 | /* 119503 */ GIR_RootConstrainSelectedInstOperands, |
| 42615 | /* 119504 */ // GIR_Coverage, 2722, |
| 42616 | /* 119504 */ GIR_EraseRootFromParent_Done, |
| 42617 | /* 119505 */ // Label 2276: @119505 |
| 42618 | /* 119505 */ GIM_Reject, |
| 42619 | /* 119506 */ // Label 2270: @119506 |
| 42620 | /* 119506 */ GIM_Reject, |
| 42621 | /* 119507 */ // Label 2263: @119507 |
| 42622 | /* 119507 */ GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(119893), |
| 42623 | /* 119512 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42624 | /* 119515 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42625 | /* 119518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42626 | /* 119521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42627 | /* 119525 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(119599), // Rule ID 2758 // |
| 42628 | /* 119530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 42629 | /* 119533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42630 | /* 119537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42631 | /* 119541 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 42632 | /* 119545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42633 | /* 119550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42634 | /* 119554 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 42635 | /* 119558 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42636 | /* 119562 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 42637 | /* 119566 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42638 | /* 119571 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42639 | /* 119573 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42640 | /* 119573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 42641 | /* 119576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42642 | /* 119578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 42643 | /* 119582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42644 | /* 119586 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42645 | /* 119588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42646 | /* 119591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42647 | /* 119597 */ GIR_RootConstrainSelectedInstOperands, |
| 42648 | /* 119598 */ // GIR_Coverage, 2758, |
| 42649 | /* 119598 */ GIR_EraseRootFromParent_Done, |
| 42650 | /* 119599 */ // Label 2278: @119599 |
| 42651 | /* 119599 */ GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(119673), // Rule ID 6309 // |
| 42652 | /* 119604 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 42653 | /* 119607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42654 | /* 119611 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42655 | /* 119615 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42656 | /* 119619 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 42657 | /* 119623 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42658 | /* 119628 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 42659 | /* 119632 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42660 | /* 119636 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 42661 | /* 119640 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42662 | /* 119645 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42663 | /* 119647 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42664 | /* 119647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 42665 | /* 119650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42666 | /* 119652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 42667 | /* 119656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42668 | /* 119660 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42669 | /* 119662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42670 | /* 119665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42671 | /* 119671 */ GIR_RootConstrainSelectedInstOperands, |
| 42672 | /* 119672 */ // GIR_Coverage, 6309, |
| 42673 | /* 119672 */ GIR_EraseRootFromParent_Done, |
| 42674 | /* 119673 */ // Label 2279: @119673 |
| 42675 | /* 119673 */ GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(119732), // Rule ID 2738 // |
| 42676 | /* 119678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 42677 | /* 119681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42678 | /* 119685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42679 | /* 119689 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 42680 | /* 119693 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42681 | /* 119698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42682 | /* 119702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42683 | /* 119706 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42684 | /* 119708 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42685 | /* 119708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 42686 | /* 119711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42687 | /* 119713 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 42688 | /* 119715 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42689 | /* 119719 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42690 | /* 119721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42691 | /* 119724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42692 | /* 119730 */ GIR_RootConstrainSelectedInstOperands, |
| 42693 | /* 119731 */ // GIR_Coverage, 2738, |
| 42694 | /* 119731 */ GIR_EraseRootFromParent_Done, |
| 42695 | /* 119732 */ // Label 2280: @119732 |
| 42696 | /* 119732 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(119791), // Rule ID 6303 // |
| 42697 | /* 119737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 42698 | /* 119740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42699 | /* 119744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42700 | /* 119748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42701 | /* 119752 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 42702 | /* 119756 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42703 | /* 119761 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42704 | /* 119765 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42705 | /* 119767 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42706 | /* 119767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 42707 | /* 119770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42708 | /* 119772 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 42709 | /* 119774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 42710 | /* 119778 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42711 | /* 119780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42712 | /* 119783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42713 | /* 119789 */ GIR_RootConstrainSelectedInstOperands, |
| 42714 | /* 119790 */ // GIR_Coverage, 6303, |
| 42715 | /* 119790 */ GIR_EraseRootFromParent_Done, |
| 42716 | /* 119791 */ // Label 2281: @119791 |
| 42717 | /* 119791 */ GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(119850), // Rule ID 2772 // |
| 42718 | /* 119796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 42719 | /* 119799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42720 | /* 119803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42721 | /* 119807 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 42722 | /* 119811 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42723 | /* 119815 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 42724 | /* 119819 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42725 | /* 119824 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42726 | /* 119826 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42727 | /* 119826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 42728 | /* 119829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42729 | /* 119831 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 42730 | /* 119835 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 42731 | /* 119837 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42732 | /* 119839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42733 | /* 119842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42734 | /* 119848 */ GIR_RootConstrainSelectedInstOperands, |
| 42735 | /* 119849 */ // GIR_Coverage, 2772, |
| 42736 | /* 119849 */ GIR_EraseRootFromParent_Done, |
| 42737 | /* 119850 */ // Label 2282: @119850 |
| 42738 | /* 119850 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(119892), // Rule ID 2720 // |
| 42739 | /* 119855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 42740 | /* 119858 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42741 | /* 119862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42742 | /* 119866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42743 | /* 119870 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42744 | /* 119870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 42745 | /* 119873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42746 | /* 119875 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 42747 | /* 119877 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 42748 | /* 119879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 42749 | /* 119881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42750 | /* 119884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42751 | /* 119890 */ GIR_RootConstrainSelectedInstOperands, |
| 42752 | /* 119891 */ // GIR_Coverage, 2720, |
| 42753 | /* 119891 */ GIR_EraseRootFromParent_Done, |
| 42754 | /* 119892 */ // Label 2283: @119892 |
| 42755 | /* 119892 */ GIM_Reject, |
| 42756 | /* 119893 */ // Label 2277: @119893 |
| 42757 | /* 119893 */ GIM_Reject, |
| 42758 | /* 119894 */ // Label 2264: @119894 |
| 42759 | /* 119894 */ GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(120280), |
| 42760 | /* 119899 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42761 | /* 119902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42762 | /* 119905 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42763 | /* 119908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42764 | /* 119912 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(119986), // Rule ID 2756 // |
| 42765 | /* 119917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 42766 | /* 119920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42767 | /* 119924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42768 | /* 119928 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 42769 | /* 119932 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42770 | /* 119937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42771 | /* 119941 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 42772 | /* 119945 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42773 | /* 119949 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 42774 | /* 119953 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42775 | /* 119958 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42776 | /* 119960 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42777 | /* 119960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 42778 | /* 119963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42779 | /* 119965 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 42780 | /* 119969 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 42781 | /* 119973 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 42782 | /* 119975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42783 | /* 119978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42784 | /* 119984 */ GIR_RootConstrainSelectedInstOperands, |
| 42785 | /* 119985 */ // GIR_Coverage, 2756, |
| 42786 | /* 119985 */ GIR_EraseRootFromParent_Done, |
| 42787 | /* 119986 */ // Label 2285: @119986 |
| 42788 | /* 119986 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(120060), // Rule ID 6307 // |
| 42789 | /* 119991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 42790 | /* 119994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42791 | /* 119998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42792 | /* 120002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42793 | /* 120006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 42794 | /* 120010 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42795 | /* 120015 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 42796 | /* 120019 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42797 | /* 120023 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 42798 | /* 120027 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42799 | /* 120032 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42800 | /* 120034 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42801 | /* 120034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 42802 | /* 120037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42803 | /* 120039 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 42804 | /* 120043 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 42805 | /* 120047 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 42806 | /* 120049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42807 | /* 120052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42808 | /* 120058 */ GIR_RootConstrainSelectedInstOperands, |
| 42809 | /* 120059 */ // GIR_Coverage, 6307, |
| 42810 | /* 120059 */ GIR_EraseRootFromParent_Done, |
| 42811 | /* 120060 */ // Label 2286: @120060 |
| 42812 | /* 120060 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(120119), // Rule ID 2736 // |
| 42813 | /* 120065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 42814 | /* 120068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42815 | /* 120072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42816 | /* 120076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 42817 | /* 120080 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42818 | /* 120085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42819 | /* 120089 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42820 | /* 120093 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42821 | /* 120095 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42822 | /* 120095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 42823 | /* 120098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42824 | /* 120100 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 42825 | /* 120102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 42826 | /* 120106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 42827 | /* 120108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42828 | /* 120111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42829 | /* 120117 */ GIR_RootConstrainSelectedInstOperands, |
| 42830 | /* 120118 */ // GIR_Coverage, 2736, |
| 42831 | /* 120118 */ GIR_EraseRootFromParent_Done, |
| 42832 | /* 120119 */ // Label 2287: @120119 |
| 42833 | /* 120119 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(120178), // Rule ID 6301 // |
| 42834 | /* 120124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 42835 | /* 120127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42836 | /* 120131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42837 | /* 120135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42838 | /* 120139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 42839 | /* 120143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42840 | /* 120148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42841 | /* 120152 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42842 | /* 120154 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42843 | /* 120154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 42844 | /* 120157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42845 | /* 120159 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 42846 | /* 120161 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 42847 | /* 120165 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 42848 | /* 120167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42849 | /* 120170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42850 | /* 120176 */ GIR_RootConstrainSelectedInstOperands, |
| 42851 | /* 120177 */ // GIR_Coverage, 6301, |
| 42852 | /* 120177 */ GIR_EraseRootFromParent_Done, |
| 42853 | /* 120178 */ // Label 2288: @120178 |
| 42854 | /* 120178 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(120237), // Rule ID 2770 // |
| 42855 | /* 120183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 42856 | /* 120186 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42857 | /* 120190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42858 | /* 120194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 42859 | /* 120198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42860 | /* 120202 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 42861 | /* 120206 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42862 | /* 120211 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42863 | /* 120213 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42864 | /* 120213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 42865 | /* 120216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42866 | /* 120218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 42867 | /* 120222 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 42868 | /* 120224 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 42869 | /* 120226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42870 | /* 120229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42871 | /* 120235 */ GIR_RootConstrainSelectedInstOperands, |
| 42872 | /* 120236 */ // GIR_Coverage, 2770, |
| 42873 | /* 120236 */ GIR_EraseRootFromParent_Done, |
| 42874 | /* 120237 */ // Label 2289: @120237 |
| 42875 | /* 120237 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(120279), // Rule ID 2718 // |
| 42876 | /* 120242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 42877 | /* 120245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42878 | /* 120249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42879 | /* 120253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42880 | /* 120257 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42881 | /* 120257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 42882 | /* 120260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42883 | /* 120262 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 42884 | /* 120264 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 42885 | /* 120266 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 42886 | /* 120268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42887 | /* 120271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42888 | /* 120277 */ GIR_RootConstrainSelectedInstOperands, |
| 42889 | /* 120278 */ // GIR_Coverage, 2718, |
| 42890 | /* 120278 */ GIR_EraseRootFromParent_Done, |
| 42891 | /* 120279 */ // Label 2290: @120279 |
| 42892 | /* 120279 */ GIM_Reject, |
| 42893 | /* 120280 */ // Label 2284: @120280 |
| 42894 | /* 120280 */ GIM_Reject, |
| 42895 | /* 120281 */ // Label 2265: @120281 |
| 42896 | /* 120281 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(120460), |
| 42897 | /* 120286 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42898 | /* 120289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42899 | /* 120292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42900 | /* 120295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42901 | /* 120299 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(120358), // Rule ID 2875 // |
| 42902 | /* 120304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 42903 | /* 120307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42904 | /* 120311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42905 | /* 120315 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42906 | /* 120319 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42907 | /* 120324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42908 | /* 120328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42909 | /* 120332 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42910 | /* 120334 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42911 | /* 120334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 42912 | /* 120337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42913 | /* 120339 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 42914 | /* 120341 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 42915 | /* 120345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42916 | /* 120347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42917 | /* 120350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42918 | /* 120356 */ GIR_RootConstrainSelectedInstOperands, |
| 42919 | /* 120357 */ // GIR_Coverage, 2875, |
| 42920 | /* 120357 */ GIR_EraseRootFromParent_Done, |
| 42921 | /* 120358 */ // Label 2292: @120358 |
| 42922 | /* 120358 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(120417), // Rule ID 6364 // |
| 42923 | /* 120363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 42924 | /* 120366 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42925 | /* 120370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 42926 | /* 120374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42927 | /* 120378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42928 | /* 120382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42929 | /* 120387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42930 | /* 120391 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42931 | /* 120393 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42932 | /* 120393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 42933 | /* 120396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42934 | /* 120398 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 42935 | /* 120400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 42936 | /* 120404 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42937 | /* 120406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42938 | /* 120409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42939 | /* 120415 */ GIR_RootConstrainSelectedInstOperands, |
| 42940 | /* 120416 */ // GIR_Coverage, 6364, |
| 42941 | /* 120416 */ GIR_EraseRootFromParent_Done, |
| 42942 | /* 120417 */ // Label 2293: @120417 |
| 42943 | /* 120417 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(120459), // Rule ID 2873 // |
| 42944 | /* 120422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 42945 | /* 120425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42946 | /* 120429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42947 | /* 120433 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42948 | /* 120437 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42949 | /* 120437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 42950 | /* 120440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42951 | /* 120442 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 42952 | /* 120444 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42953 | /* 120446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42954 | /* 120448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42955 | /* 120451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42956 | /* 120457 */ GIR_RootConstrainSelectedInstOperands, |
| 42957 | /* 120458 */ // GIR_Coverage, 2873, |
| 42958 | /* 120458 */ GIR_EraseRootFromParent_Done, |
| 42959 | /* 120459 */ // Label 2294: @120459 |
| 42960 | /* 120459 */ GIM_Reject, |
| 42961 | /* 120460 */ // Label 2291: @120460 |
| 42962 | /* 120460 */ GIM_Reject, |
| 42963 | /* 120461 */ // Label 2266: @120461 |
| 42964 | /* 120461 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(120516), // Rule ID 2871 // |
| 42965 | /* 120466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42966 | /* 120469 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42967 | /* 120472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42968 | /* 120475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42969 | /* 120478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42970 | /* 120482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42971 | /* 120486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42972 | /* 120490 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42973 | /* 120494 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 42974 | /* 120494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 42975 | /* 120497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42976 | /* 120499 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 42977 | /* 120501 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42978 | /* 120503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42979 | /* 120505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42980 | /* 120508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42981 | /* 120514 */ GIR_RootConstrainSelectedInstOperands, |
| 42982 | /* 120515 */ // GIR_Coverage, 2871, |
| 42983 | /* 120515 */ GIR_EraseRootFromParent_Done, |
| 42984 | /* 120516 */ // Label 2295: @120516 |
| 42985 | /* 120516 */ GIM_Reject, |
| 42986 | /* 120517 */ // Label 2267: @120517 |
| 42987 | /* 120517 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(120894), |
| 42988 | /* 120522 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42989 | /* 120525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42990 | /* 120528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42991 | /* 120531 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(120594), // Rule ID 2876 // |
| 42992 | /* 120536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 42993 | /* 120539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42994 | /* 120543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42995 | /* 120547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 42996 | /* 120551 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42997 | /* 120555 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42998 | /* 120560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42999 | /* 120564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43000 | /* 120568 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43001 | /* 120570 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43002 | /* 120570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 43003 | /* 120573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43004 | /* 120575 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 43005 | /* 120577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 43006 | /* 120581 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43007 | /* 120583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43008 | /* 120586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43009 | /* 120592 */ GIR_RootConstrainSelectedInstOperands, |
| 43010 | /* 120593 */ // GIR_Coverage, 2876, |
| 43011 | /* 120593 */ GIR_EraseRootFromParent_Done, |
| 43012 | /* 120594 */ // Label 2297: @120594 |
| 43013 | /* 120594 */ GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(120663), // Rule ID 4414 // |
| 43014 | /* 120599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43015 | /* 120602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43016 | /* 120606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43017 | /* 120610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43018 | /* 120614 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43019 | /* 120618 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43020 | /* 120623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43021 | /* 120627 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43022 | /* 120631 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43023 | /* 120633 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 43024 | /* 120633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 43025 | /* 120636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43026 | /* 120638 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 43027 | /* 120640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 43028 | /* 120644 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 43029 | /* 120646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43030 | /* 120649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43031 | /* 120655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43032 | /* 120661 */ GIR_RootConstrainSelectedInstOperands, |
| 43033 | /* 120662 */ // GIR_Coverage, 4414, |
| 43034 | /* 120662 */ GIR_EraseRootFromParent_Done, |
| 43035 | /* 120663 */ // Label 2298: @120663 |
| 43036 | /* 120663 */ GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(120726), // Rule ID 6365 // |
| 43037 | /* 120668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 43038 | /* 120671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43039 | /* 120675 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43040 | /* 120679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43041 | /* 120683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43042 | /* 120687 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43043 | /* 120691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43044 | /* 120696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43045 | /* 120700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43046 | /* 120702 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43047 | /* 120702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 43048 | /* 120705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43049 | /* 120707 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 43050 | /* 120709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 43051 | /* 120713 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 43052 | /* 120715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43053 | /* 120718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43054 | /* 120724 */ GIR_RootConstrainSelectedInstOperands, |
| 43055 | /* 120725 */ // GIR_Coverage, 6365, |
| 43056 | /* 120725 */ GIR_EraseRootFromParent_Done, |
| 43057 | /* 120726 */ // Label 2299: @120726 |
| 43058 | /* 120726 */ GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(120795), // Rule ID 6645 // |
| 43059 | /* 120731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43060 | /* 120734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43061 | /* 120738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43062 | /* 120742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43063 | /* 120746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43064 | /* 120750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43065 | /* 120754 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43066 | /* 120759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43067 | /* 120763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43068 | /* 120765 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 43069 | /* 120765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 43070 | /* 120768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43071 | /* 120770 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 43072 | /* 120772 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 43073 | /* 120776 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 43074 | /* 120778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43075 | /* 120781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43076 | /* 120787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43077 | /* 120793 */ GIR_RootConstrainSelectedInstOperands, |
| 43078 | /* 120794 */ // GIR_Coverage, 6645, |
| 43079 | /* 120794 */ GIR_EraseRootFromParent_Done, |
| 43080 | /* 120795 */ // Label 2300: @120795 |
| 43081 | /* 120795 */ GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(120841), // Rule ID 2874 // |
| 43082 | /* 120800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 43083 | /* 120803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43084 | /* 120807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43085 | /* 120811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43086 | /* 120815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43087 | /* 120819 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43088 | /* 120819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq), |
| 43089 | /* 120822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43090 | /* 120824 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 43091 | /* 120826 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43092 | /* 120828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43093 | /* 120830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43094 | /* 120833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43095 | /* 120839 */ GIR_RootConstrainSelectedInstOperands, |
| 43096 | /* 120840 */ // GIR_Coverage, 2874, |
| 43097 | /* 120840 */ GIR_EraseRootFromParent_Done, |
| 43098 | /* 120841 */ // Label 2301: @120841 |
| 43099 | /* 120841 */ GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(120893), // Rule ID 4420 // |
| 43100 | /* 120846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43101 | /* 120849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43102 | /* 120853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43103 | /* 120857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43104 | /* 120861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43105 | /* 120865 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 43106 | /* 120865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 43107 | /* 120868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43108 | /* 120870 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 43109 | /* 120872 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 43110 | /* 120874 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 43111 | /* 120876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43112 | /* 120879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43113 | /* 120885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43114 | /* 120891 */ GIR_RootConstrainSelectedInstOperands, |
| 43115 | /* 120892 */ // GIR_Coverage, 4420, |
| 43116 | /* 120892 */ GIR_EraseRootFromParent_Done, |
| 43117 | /* 120893 */ // Label 2302: @120893 |
| 43118 | /* 120893 */ GIM_Reject, |
| 43119 | /* 120894 */ // Label 2296: @120894 |
| 43120 | /* 120894 */ GIM_Reject, |
| 43121 | /* 120895 */ // Label 2268: @120895 |
| 43122 | /* 120895 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(121146), |
| 43123 | /* 120900 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43124 | /* 120903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43125 | /* 120906 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43126 | /* 120909 */ GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(120978), // Rule ID 4428 // |
| 43127 | /* 120914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43128 | /* 120917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43129 | /* 120921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43130 | /* 120925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43131 | /* 120929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43132 | /* 120933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43133 | /* 120938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43134 | /* 120942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43135 | /* 120946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43136 | /* 120948 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 43137 | /* 120948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 43138 | /* 120951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43139 | /* 120953 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 43140 | /* 120955 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 43141 | /* 120959 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 43142 | /* 120961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43143 | /* 120964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43144 | /* 120970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43145 | /* 120976 */ GIR_RootConstrainSelectedInstOperands, |
| 43146 | /* 120977 */ // GIR_Coverage, 4428, |
| 43147 | /* 120977 */ GIR_EraseRootFromParent_Done, |
| 43148 | /* 120978 */ // Label 2304: @120978 |
| 43149 | /* 120978 */ GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(121047), // Rule ID 6647 // |
| 43150 | /* 120983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43151 | /* 120986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43152 | /* 120990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43153 | /* 120994 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43154 | /* 120998 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43155 | /* 121002 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43156 | /* 121006 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43157 | /* 121011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43158 | /* 121015 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43159 | /* 121017 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 43160 | /* 121017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 43161 | /* 121020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43162 | /* 121022 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 43163 | /* 121024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 43164 | /* 121028 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 43165 | /* 121030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43166 | /* 121033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43167 | /* 121039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43168 | /* 121045 */ GIR_RootConstrainSelectedInstOperands, |
| 43169 | /* 121046 */ // GIR_Coverage, 6647, |
| 43170 | /* 121046 */ GIR_EraseRootFromParent_Done, |
| 43171 | /* 121047 */ // Label 2305: @121047 |
| 43172 | /* 121047 */ GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(121093), // Rule ID 2872 // |
| 43173 | /* 121052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 43174 | /* 121055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43175 | /* 121059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43176 | /* 121063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43177 | /* 121067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43178 | /* 121071 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43179 | /* 121071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 43180 | /* 121074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43181 | /* 121076 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 43182 | /* 121078 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43183 | /* 121080 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43184 | /* 121082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43185 | /* 121085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43186 | /* 121091 */ GIR_RootConstrainSelectedInstOperands, |
| 43187 | /* 121092 */ // GIR_Coverage, 2872, |
| 43188 | /* 121092 */ GIR_EraseRootFromParent_Done, |
| 43189 | /* 121093 */ // Label 2306: @121093 |
| 43190 | /* 121093 */ GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(121145), // Rule ID 4424 // |
| 43191 | /* 121098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43192 | /* 121101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43193 | /* 121105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43194 | /* 121109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43195 | /* 121113 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43196 | /* 121117 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 43197 | /* 121117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 43198 | /* 121120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43199 | /* 121122 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 43200 | /* 121124 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 43201 | /* 121126 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 43202 | /* 121128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43203 | /* 121131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43204 | /* 121137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43205 | /* 121143 */ GIR_RootConstrainSelectedInstOperands, |
| 43206 | /* 121144 */ // GIR_Coverage, 4424, |
| 43207 | /* 121144 */ GIR_EraseRootFromParent_Done, |
| 43208 | /* 121145 */ // Label 2307: @121145 |
| 43209 | /* 121145 */ GIM_Reject, |
| 43210 | /* 121146 */ // Label 2303: @121146 |
| 43211 | /* 121146 */ GIM_Reject, |
| 43212 | /* 121147 */ // Label 2269: @121147 |
| 43213 | /* 121147 */ GIM_Reject, |
| 43214 | /* 121148 */ // Label 44: @121148 |
| 43215 | /* 121148 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2311*/ GIMT_Encode4(121312), |
| 43216 | /* 121159 */ /*GILLT_s16*//*Label 2308*/ GIMT_Encode4(121171), |
| 43217 | /* 121163 */ /*GILLT_s32*//*Label 2309*/ GIMT_Encode4(121218), |
| 43218 | /* 121167 */ /*GILLT_s64*//*Label 2310*/ GIMT_Encode4(121265), |
| 43219 | /* 121171 */ // Label 2308: @121171 |
| 43220 | /* 121171 */ GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(121217), // Rule ID 632 // |
| 43221 | /* 121176 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43222 | /* 121179 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43223 | /* 121182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43224 | /* 121185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43225 | /* 121189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43226 | /* 121193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43227 | /* 121197 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43228 | /* 121197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 43229 | /* 121200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43230 | /* 121202 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 43231 | /* 121204 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 43232 | /* 121206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43233 | /* 121209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43234 | /* 121215 */ GIR_RootConstrainSelectedInstOperands, |
| 43235 | /* 121216 */ // GIR_Coverage, 632, |
| 43236 | /* 121216 */ GIR_EraseRootFromParent_Done, |
| 43237 | /* 121217 */ // Label 2312: @121217 |
| 43238 | /* 121217 */ GIM_Reject, |
| 43239 | /* 121218 */ // Label 2309: @121218 |
| 43240 | /* 121218 */ GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(121264), // Rule ID 630 // |
| 43241 | /* 121223 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 43242 | /* 121226 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43243 | /* 121229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43244 | /* 121232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43245 | /* 121236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43246 | /* 121240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43247 | /* 121244 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43248 | /* 121244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 43249 | /* 121247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43250 | /* 121249 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 43251 | /* 121251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 43252 | /* 121253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43253 | /* 121256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43254 | /* 121262 */ GIR_RootConstrainSelectedInstOperands, |
| 43255 | /* 121263 */ // GIR_Coverage, 630, |
| 43256 | /* 121263 */ GIR_EraseRootFromParent_Done, |
| 43257 | /* 121264 */ // Label 2313: @121264 |
| 43258 | /* 121264 */ GIM_Reject, |
| 43259 | /* 121265 */ // Label 2310: @121265 |
| 43260 | /* 121265 */ GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(121311), // Rule ID 628 // |
| 43261 | /* 121270 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 43262 | /* 121273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 43263 | /* 121276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 43264 | /* 121279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43265 | /* 121283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43266 | /* 121287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43267 | /* 121291 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43268 | /* 121291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 43269 | /* 121294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43270 | /* 121296 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 43271 | /* 121298 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 43272 | /* 121300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43273 | /* 121303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43274 | /* 121309 */ GIR_RootConstrainSelectedInstOperands, |
| 43275 | /* 121310 */ // GIR_Coverage, 628, |
| 43276 | /* 121310 */ GIR_EraseRootFromParent_Done, |
| 43277 | /* 121311 */ // Label 2314: @121311 |
| 43278 | /* 121311 */ GIM_Reject, |
| 43279 | /* 121312 */ // Label 2311: @121312 |
| 43280 | /* 121312 */ GIM_Reject, |
| 43281 | /* 121313 */ // Label 45: @121313 |
| 43282 | /* 121313 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2322*/ GIMT_Encode4(123752), |
| 43283 | /* 121324 */ /*GILLT_s16*//*Label 2315*/ GIMT_Encode4(121376), |
| 43284 | /* 121328 */ /*GILLT_s32*//*Label 2316*/ GIMT_Encode4(122026), |
| 43285 | /* 121332 */ /*GILLT_s64*//*Label 2317*/ GIMT_Encode4(122828), GIMT_Encode4(0), |
| 43286 | /* 121340 */ /*GILLT_v2s32*//*Label 2318*/ GIMT_Encode4(123478), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43287 | /* 121352 */ /*GILLT_v4s16*//*Label 2319*/ GIMT_Encode4(123516), |
| 43288 | /* 121356 */ /*GILLT_v4s32*//*Label 2320*/ GIMT_Encode4(123554), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43289 | /* 121372 */ /*GILLT_v8s16*//*Label 2321*/ GIMT_Encode4(123653), |
| 43290 | /* 121376 */ // Label 2315: @121376 |
| 43291 | /* 121376 */ GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(122025), |
| 43292 | /* 121381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43293 | /* 121384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43294 | /* 121388 */ GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(121473), // Rule ID 2780 // |
| 43295 | /* 121393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43296 | /* 121396 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43297 | /* 121400 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43298 | /* 121404 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43299 | /* 121408 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43300 | /* 121412 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 43301 | /* 121416 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 43302 | /* 121420 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43303 | /* 121424 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 43304 | /* 121428 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43305 | /* 121433 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43306 | /* 121438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43307 | /* 121443 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43308 | /* 121445 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43309 | /* 121445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 43310 | /* 121448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43311 | /* 121450 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43312 | /* 121454 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43313 | /* 121458 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43314 | /* 121462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43315 | /* 121465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43316 | /* 121471 */ GIR_RootConstrainSelectedInstOperands, |
| 43317 | /* 121472 */ // GIR_Coverage, 2780, |
| 43318 | /* 121472 */ GIR_EraseRootFromParent_Done, |
| 43319 | /* 121473 */ // Label 2324: @121473 |
| 43320 | /* 121473 */ GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(121558), // Rule ID 6317 // |
| 43321 | /* 121478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43322 | /* 121481 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43323 | /* 121485 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43324 | /* 121489 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43325 | /* 121493 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43326 | /* 121497 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 43327 | /* 121501 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43328 | /* 121506 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 43329 | /* 121510 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43330 | /* 121514 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 43331 | /* 121518 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43332 | /* 121523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43333 | /* 121528 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43334 | /* 121530 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43335 | /* 121530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 43336 | /* 121533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43337 | /* 121535 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43338 | /* 121539 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43339 | /* 121543 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 43340 | /* 121547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43341 | /* 121550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43342 | /* 121556 */ GIR_RootConstrainSelectedInstOperands, |
| 43343 | /* 121557 */ // GIR_Coverage, 6317, |
| 43344 | /* 121557 */ GIR_EraseRootFromParent_Done, |
| 43345 | /* 121558 */ // Label 2325: @121558 |
| 43346 | /* 121558 */ GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(121643), // Rule ID 2779 // |
| 43347 | /* 121563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43348 | /* 121566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43349 | /* 121570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43350 | /* 121574 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43351 | /* 121578 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43352 | /* 121582 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 43353 | /* 121586 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 43354 | /* 121590 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43355 | /* 121594 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 43356 | /* 121598 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43357 | /* 121603 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43358 | /* 121608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43359 | /* 121613 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43360 | /* 121615 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43361 | /* 121615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 43362 | /* 121618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43363 | /* 121620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43364 | /* 121624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43365 | /* 121628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43366 | /* 121632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43367 | /* 121635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43368 | /* 121641 */ GIR_RootConstrainSelectedInstOperands, |
| 43369 | /* 121642 */ // GIR_Coverage, 2779, |
| 43370 | /* 121642 */ GIR_EraseRootFromParent_Done, |
| 43371 | /* 121643 */ // Label 2326: @121643 |
| 43372 | /* 121643 */ GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(121728), // Rule ID 6316 // |
| 43373 | /* 121648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43374 | /* 121651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43375 | /* 121655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43376 | /* 121659 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43377 | /* 121663 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43378 | /* 121667 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 43379 | /* 121671 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43380 | /* 121676 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 43381 | /* 121680 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43382 | /* 121684 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 43383 | /* 121688 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43384 | /* 121693 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43385 | /* 121698 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43386 | /* 121700 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43387 | /* 121700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 43388 | /* 121703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43389 | /* 121705 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43390 | /* 121709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43391 | /* 121713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 43392 | /* 121717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43393 | /* 121720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43394 | /* 121726 */ GIR_RootConstrainSelectedInstOperands, |
| 43395 | /* 121727 */ // GIR_Coverage, 6316, |
| 43396 | /* 121727 */ GIR_EraseRootFromParent_Done, |
| 43397 | /* 121728 */ // Label 2327: @121728 |
| 43398 | /* 121728 */ GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(121801), // Rule ID 2754 // |
| 43399 | /* 121733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43400 | /* 121736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43401 | /* 121740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43402 | /* 121744 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43403 | /* 121748 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43404 | /* 121752 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 43405 | /* 121756 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43406 | /* 121761 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43407 | /* 121766 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43408 | /* 121771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43409 | /* 121773 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43410 | /* 121773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 43411 | /* 121776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43412 | /* 121778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43413 | /* 121782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43414 | /* 121786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43415 | /* 121790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43416 | /* 121793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43417 | /* 121799 */ GIR_RootConstrainSelectedInstOperands, |
| 43418 | /* 121800 */ // GIR_Coverage, 2754, |
| 43419 | /* 121800 */ GIR_EraseRootFromParent_Done, |
| 43420 | /* 121801 */ // Label 2328: @121801 |
| 43421 | /* 121801 */ GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(121874), // Rule ID 2753 // |
| 43422 | /* 121806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43423 | /* 121809 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43424 | /* 121813 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43425 | /* 121817 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43426 | /* 121821 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43427 | /* 121825 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 43428 | /* 121829 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43429 | /* 121834 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43430 | /* 121839 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43431 | /* 121844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43432 | /* 121846 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43433 | /* 121846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 43434 | /* 121849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43435 | /* 121851 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43436 | /* 121855 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43437 | /* 121859 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43438 | /* 121863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43439 | /* 121866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43440 | /* 121872 */ GIR_RootConstrainSelectedInstOperands, |
| 43441 | /* 121873 */ // GIR_Coverage, 2753, |
| 43442 | /* 121873 */ GIR_EraseRootFromParent_Done, |
| 43443 | /* 121874 */ // Label 2329: @121874 |
| 43444 | /* 121874 */ GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(121934), // Rule ID 644 // |
| 43445 | /* 121879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43446 | /* 121882 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43447 | /* 121886 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 43448 | /* 121890 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43449 | /* 121894 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43450 | /* 121898 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43451 | /* 121903 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43452 | /* 121908 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43453 | /* 121910 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43454 | /* 121910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 43455 | /* 121913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43456 | /* 121915 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43457 | /* 121919 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43458 | /* 121923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43459 | /* 121926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43460 | /* 121932 */ GIR_RootConstrainSelectedInstOperands, |
| 43461 | /* 121933 */ // GIR_Coverage, 644, |
| 43462 | /* 121933 */ GIR_EraseRootFromParent_Done, |
| 43463 | /* 121934 */ // Label 2330: @121934 |
| 43464 | /* 121934 */ GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(121994), // Rule ID 643 // |
| 43465 | /* 121939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43466 | /* 121942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43467 | /* 121946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 43468 | /* 121950 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 43469 | /* 121954 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 43470 | /* 121958 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43471 | /* 121963 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43472 | /* 121968 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43473 | /* 121970 */ // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43474 | /* 121970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 43475 | /* 121973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43476 | /* 121975 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43477 | /* 121979 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43478 | /* 121983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43479 | /* 121986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43480 | /* 121992 */ GIR_RootConstrainSelectedInstOperands, |
| 43481 | /* 121993 */ // GIR_Coverage, 643, |
| 43482 | /* 121993 */ GIR_EraseRootFromParent_Done, |
| 43483 | /* 121994 */ // Label 2331: @121994 |
| 43484 | /* 121994 */ GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(122024), // Rule ID 690 // |
| 43485 | /* 121999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43486 | /* 122002 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43487 | /* 122006 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 43488 | /* 122006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH), |
| 43489 | /* 122009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43490 | /* 122011 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 43491 | /* 122013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43492 | /* 122016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43493 | /* 122022 */ GIR_RootConstrainSelectedInstOperands, |
| 43494 | /* 122023 */ // GIR_Coverage, 690, |
| 43495 | /* 122023 */ GIR_EraseRootFromParent_Done, |
| 43496 | /* 122024 */ // Label 2332: @122024 |
| 43497 | /* 122024 */ GIM_Reject, |
| 43498 | /* 122025 */ // Label 2323: @122025 |
| 43499 | /* 122025 */ GIM_Reject, |
| 43500 | /* 122026 */ // Label 2316: @122026 |
| 43501 | /* 122026 */ GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(122827), |
| 43502 | /* 122031 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43503 | /* 122034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43504 | /* 122038 */ GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(122123), // Rule ID 2778 // |
| 43505 | /* 122043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 43506 | /* 122046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43507 | /* 122050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43508 | /* 122054 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43509 | /* 122058 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43510 | /* 122062 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 43511 | /* 122066 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 43512 | /* 122070 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43513 | /* 122074 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 43514 | /* 122078 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43515 | /* 122083 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43516 | /* 122088 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43517 | /* 122093 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43518 | /* 122095 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43519 | /* 122095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 43520 | /* 122098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43521 | /* 122100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43522 | /* 122104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43523 | /* 122108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43524 | /* 122112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43525 | /* 122115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43526 | /* 122121 */ GIR_RootConstrainSelectedInstOperands, |
| 43527 | /* 122122 */ // GIR_Coverage, 2778, |
| 43528 | /* 122122 */ GIR_EraseRootFromParent_Done, |
| 43529 | /* 122123 */ // Label 2334: @122123 |
| 43530 | /* 122123 */ GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(122208), // Rule ID 6315 // |
| 43531 | /* 122128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 43532 | /* 122131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43533 | /* 122135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43534 | /* 122139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43535 | /* 122143 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43536 | /* 122147 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 43537 | /* 122151 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43538 | /* 122156 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 43539 | /* 122160 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43540 | /* 122164 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 43541 | /* 122168 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43542 | /* 122173 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43543 | /* 122178 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43544 | /* 122180 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43545 | /* 122180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 43546 | /* 122183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43547 | /* 122185 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43548 | /* 122189 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43549 | /* 122193 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 43550 | /* 122197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43551 | /* 122200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43552 | /* 122206 */ GIR_RootConstrainSelectedInstOperands, |
| 43553 | /* 122207 */ // GIR_Coverage, 6315, |
| 43554 | /* 122207 */ GIR_EraseRootFromParent_Done, |
| 43555 | /* 122208 */ // Label 2335: @122208 |
| 43556 | /* 122208 */ GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(122293), // Rule ID 2777 // |
| 43557 | /* 122213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 43558 | /* 122216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43559 | /* 122220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43560 | /* 122224 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43561 | /* 122228 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43562 | /* 122232 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 43563 | /* 122236 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 43564 | /* 122240 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43565 | /* 122244 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 43566 | /* 122248 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43567 | /* 122253 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43568 | /* 122258 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43569 | /* 122263 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43570 | /* 122265 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43571 | /* 122265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 43572 | /* 122268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43573 | /* 122270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43574 | /* 122274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43575 | /* 122278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43576 | /* 122282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43577 | /* 122285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43578 | /* 122291 */ GIR_RootConstrainSelectedInstOperands, |
| 43579 | /* 122292 */ // GIR_Coverage, 2777, |
| 43580 | /* 122292 */ GIR_EraseRootFromParent_Done, |
| 43581 | /* 122293 */ // Label 2336: @122293 |
| 43582 | /* 122293 */ GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(122378), // Rule ID 6314 // |
| 43583 | /* 122298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 43584 | /* 122301 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43585 | /* 122305 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43586 | /* 122309 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43587 | /* 122313 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43588 | /* 122317 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 43589 | /* 122321 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43590 | /* 122326 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 43591 | /* 122330 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43592 | /* 122334 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 43593 | /* 122338 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43594 | /* 122343 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43595 | /* 122348 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43596 | /* 122350 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43597 | /* 122350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 43598 | /* 122353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43599 | /* 122355 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43600 | /* 122359 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 43601 | /* 122363 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 43602 | /* 122367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43603 | /* 122370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43604 | /* 122376 */ GIR_RootConstrainSelectedInstOperands, |
| 43605 | /* 122377 */ // GIR_Coverage, 6314, |
| 43606 | /* 122377 */ GIR_EraseRootFromParent_Done, |
| 43607 | /* 122378 */ // Label 2337: @122378 |
| 43608 | /* 122378 */ GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(122451), // Rule ID 2752 // |
| 43609 | /* 122383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 43610 | /* 122386 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43611 | /* 122390 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43612 | /* 122394 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43613 | /* 122398 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43614 | /* 122402 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 43615 | /* 122406 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43616 | /* 122411 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43617 | /* 122416 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43618 | /* 122421 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43619 | /* 122423 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43620 | /* 122423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 43621 | /* 122426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43622 | /* 122428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43623 | /* 122432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43624 | /* 122436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43625 | /* 122440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43626 | /* 122443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43627 | /* 122449 */ GIR_RootConstrainSelectedInstOperands, |
| 43628 | /* 122450 */ // GIR_Coverage, 2752, |
| 43629 | /* 122450 */ GIR_EraseRootFromParent_Done, |
| 43630 | /* 122451 */ // Label 2338: @122451 |
| 43631 | /* 122451 */ GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(122524), // Rule ID 2751 // |
| 43632 | /* 122456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 43633 | /* 122459 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43634 | /* 122463 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43635 | /* 122467 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43636 | /* 122471 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43637 | /* 122475 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 43638 | /* 122479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43639 | /* 122484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43640 | /* 122489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43641 | /* 122494 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43642 | /* 122496 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43643 | /* 122496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 43644 | /* 122499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43645 | /* 122501 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 43646 | /* 122505 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43647 | /* 122509 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43648 | /* 122513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43649 | /* 122516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43650 | /* 122522 */ GIR_RootConstrainSelectedInstOperands, |
| 43651 | /* 122523 */ // GIR_Coverage, 2751, |
| 43652 | /* 122523 */ GIR_EraseRootFromParent_Done, |
| 43653 | /* 122524 */ // Label 2339: @122524 |
| 43654 | /* 122524 */ GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(122584), // Rule ID 642 // |
| 43655 | /* 122529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 43656 | /* 122532 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43657 | /* 122536 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 43658 | /* 122540 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43659 | /* 122544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43660 | /* 122548 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43661 | /* 122553 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43662 | /* 122558 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43663 | /* 122560 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43664 | /* 122560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 43665 | /* 122563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43666 | /* 122565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43667 | /* 122569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43668 | /* 122573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43669 | /* 122576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43670 | /* 122582 */ GIR_RootConstrainSelectedInstOperands, |
| 43671 | /* 122583 */ // GIR_Coverage, 642, |
| 43672 | /* 122583 */ GIR_EraseRootFromParent_Done, |
| 43673 | /* 122584 */ // Label 2340: @122584 |
| 43674 | /* 122584 */ GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(122644), // Rule ID 641 // |
| 43675 | /* 122589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 43676 | /* 122592 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43677 | /* 122596 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 43678 | /* 122600 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 43679 | /* 122604 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 43680 | /* 122608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43681 | /* 122613 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43682 | /* 122618 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43683 | /* 122620 */ // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43684 | /* 122620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 43685 | /* 122623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43686 | /* 122625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 43687 | /* 122629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 43688 | /* 122633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43689 | /* 122636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43690 | /* 122642 */ GIR_RootConstrainSelectedInstOperands, |
| 43691 | /* 122643 */ // GIR_Coverage, 641, |
| 43692 | /* 122643 */ GIR_EraseRootFromParent_Done, |
| 43693 | /* 122644 */ // Label 2341: @122644 |
| 43694 | /* 122644 */ GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(122674), // Rule ID 689 // |
| 43695 | /* 122649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 43696 | /* 122652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43697 | /* 122656 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 43698 | /* 122656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS), |
| 43699 | /* 122659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 43700 | /* 122661 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 43701 | /* 122663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43702 | /* 122666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43703 | /* 122672 */ GIR_RootConstrainSelectedInstOperands, |
| 43704 | /* 122673 */ // GIR_Coverage, 689, |
| 43705 | /* 122673 */ GIR_EraseRootFromParent_Done, |
| 43706 | /* 122674 */ // Label 2342: @122674 |
| 43707 | /* 122674 */ GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(122826), // Rule ID 3079 // |
| 43708 | /* 122679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 43709 | /* 122682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43710 | /* 122686 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43711 | /* 122686 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 43712 | /* 122689 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43713 | /* 122693 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43714 | /* 122698 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43715 | /* 122700 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 43716 | /* 122703 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43717 | /* 122707 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43718 | /* 122712 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43719 | /* 122715 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43720 | /* 122720 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 43721 | /* 122723 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43722 | /* 122727 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43723 | /* 122732 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43724 | /* 122735 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43725 | /* 122739 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43726 | /* 122742 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43727 | /* 122747 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43728 | /* 122752 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43729 | /* 122757 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43730 | /* 122760 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 43731 | /* 122764 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43732 | /* 122769 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43733 | /* 122772 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43734 | /* 122775 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43735 | /* 122781 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43736 | /* 122783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 43737 | /* 122786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43738 | /* 122790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43739 | /* 122795 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43740 | /* 122798 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43741 | /* 122803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43742 | /* 122806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43743 | /* 122808 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43744 | /* 122815 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43745 | /* 122820 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43746 | /* 122825 */ // GIR_Coverage, 3079, |
| 43747 | /* 122825 */ GIR_EraseRootFromParent_Done, |
| 43748 | /* 122826 */ // Label 2343: @122826 |
| 43749 | /* 122826 */ GIM_Reject, |
| 43750 | /* 122827 */ // Label 2333: @122827 |
| 43751 | /* 122827 */ GIM_Reject, |
| 43752 | /* 122828 */ // Label 2317: @122828 |
| 43753 | /* 122828 */ GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(123477), |
| 43754 | /* 122833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 43755 | /* 122836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43756 | /* 122840 */ GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(122925), // Rule ID 2776 // |
| 43757 | /* 122845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 43758 | /* 122848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43759 | /* 122852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43760 | /* 122856 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43761 | /* 122860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43762 | /* 122864 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 43763 | /* 122868 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 43764 | /* 122872 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43765 | /* 122876 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 43766 | /* 122880 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43767 | /* 122885 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43768 | /* 122890 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43769 | /* 122895 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43770 | /* 122897 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43771 | /* 122897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 43772 | /* 122900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43773 | /* 122902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 43774 | /* 122906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 43775 | /* 122910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 43776 | /* 122914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43777 | /* 122917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43778 | /* 122923 */ GIR_RootConstrainSelectedInstOperands, |
| 43779 | /* 122924 */ // GIR_Coverage, 2776, |
| 43780 | /* 122924 */ GIR_EraseRootFromParent_Done, |
| 43781 | /* 122925 */ // Label 2345: @122925 |
| 43782 | /* 122925 */ GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(123010), // Rule ID 6313 // |
| 43783 | /* 122930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 43784 | /* 122933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43785 | /* 122937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43786 | /* 122941 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43787 | /* 122945 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43788 | /* 122949 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 43789 | /* 122953 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43790 | /* 122958 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 43791 | /* 122962 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43792 | /* 122966 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 43793 | /* 122970 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43794 | /* 122975 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43795 | /* 122980 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43796 | /* 122982 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43797 | /* 122982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 43798 | /* 122985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43799 | /* 122987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 43800 | /* 122991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 43801 | /* 122995 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 43802 | /* 122999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43803 | /* 123002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43804 | /* 123008 */ GIR_RootConstrainSelectedInstOperands, |
| 43805 | /* 123009 */ // GIR_Coverage, 6313, |
| 43806 | /* 123009 */ GIR_EraseRootFromParent_Done, |
| 43807 | /* 123010 */ // Label 2346: @123010 |
| 43808 | /* 123010 */ GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(123095), // Rule ID 2775 // |
| 43809 | /* 123015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 43810 | /* 123018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43811 | /* 123022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43812 | /* 123026 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43813 | /* 123030 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43814 | /* 123034 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 43815 | /* 123038 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 43816 | /* 123042 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43817 | /* 123046 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 43818 | /* 123050 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43819 | /* 123055 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43820 | /* 123060 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43821 | /* 123065 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43822 | /* 123067 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43823 | /* 123067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 43824 | /* 123070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43825 | /* 123072 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 43826 | /* 123076 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 43827 | /* 123080 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 43828 | /* 123084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43829 | /* 123087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43830 | /* 123093 */ GIR_RootConstrainSelectedInstOperands, |
| 43831 | /* 123094 */ // GIR_Coverage, 2775, |
| 43832 | /* 123094 */ GIR_EraseRootFromParent_Done, |
| 43833 | /* 123095 */ // Label 2347: @123095 |
| 43834 | /* 123095 */ GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(123180), // Rule ID 6312 // |
| 43835 | /* 123100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 43836 | /* 123103 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43837 | /* 123107 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43838 | /* 123111 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43839 | /* 123115 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43840 | /* 123119 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 43841 | /* 123123 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43842 | /* 123128 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 43843 | /* 123132 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 43844 | /* 123136 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 43845 | /* 123140 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43846 | /* 123145 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43847 | /* 123150 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43848 | /* 123152 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43849 | /* 123152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 43850 | /* 123155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43851 | /* 123157 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 43852 | /* 123161 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 43853 | /* 123165 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 43854 | /* 123169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43855 | /* 123172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43856 | /* 123178 */ GIR_RootConstrainSelectedInstOperands, |
| 43857 | /* 123179 */ // GIR_Coverage, 6312, |
| 43858 | /* 123179 */ GIR_EraseRootFromParent_Done, |
| 43859 | /* 123180 */ // Label 2348: @123180 |
| 43860 | /* 123180 */ GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(123253), // Rule ID 2750 // |
| 43861 | /* 123185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 43862 | /* 123188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43863 | /* 123192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 43864 | /* 123196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43865 | /* 123200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43866 | /* 123204 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 43867 | /* 123208 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43868 | /* 123213 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43869 | /* 123218 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43870 | /* 123223 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43871 | /* 123225 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43872 | /* 123225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 43873 | /* 123228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43874 | /* 123230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 43875 | /* 123234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 43876 | /* 123238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 43877 | /* 123242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43878 | /* 123245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43879 | /* 123251 */ GIR_RootConstrainSelectedInstOperands, |
| 43880 | /* 123252 */ // GIR_Coverage, 2750, |
| 43881 | /* 123252 */ GIR_EraseRootFromParent_Done, |
| 43882 | /* 123253 */ // Label 2349: @123253 |
| 43883 | /* 123253 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(123326), // Rule ID 2749 // |
| 43884 | /* 123258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 43885 | /* 123261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43886 | /* 123265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 43887 | /* 123269 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43888 | /* 123273 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43889 | /* 123277 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 43890 | /* 123281 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43891 | /* 123286 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43892 | /* 123291 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43893 | /* 123296 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43894 | /* 123298 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43895 | /* 123298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 43896 | /* 123301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43897 | /* 123303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 43898 | /* 123307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 43899 | /* 123311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 43900 | /* 123315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43901 | /* 123318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43902 | /* 123324 */ GIR_RootConstrainSelectedInstOperands, |
| 43903 | /* 123325 */ // GIR_Coverage, 2749, |
| 43904 | /* 123325 */ GIR_EraseRootFromParent_Done, |
| 43905 | /* 123326 */ // Label 2350: @123326 |
| 43906 | /* 123326 */ GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(123386), // Rule ID 640 // |
| 43907 | /* 123331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 43908 | /* 123334 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43909 | /* 123338 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 43910 | /* 123342 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43911 | /* 123346 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43912 | /* 123350 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43913 | /* 123355 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43914 | /* 123360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43915 | /* 123362 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43916 | /* 123362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 43917 | /* 123365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43918 | /* 123367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 43919 | /* 123371 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 43920 | /* 123375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43921 | /* 123378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43922 | /* 123384 */ GIR_RootConstrainSelectedInstOperands, |
| 43923 | /* 123385 */ // GIR_Coverage, 640, |
| 43924 | /* 123385 */ GIR_EraseRootFromParent_Done, |
| 43925 | /* 123386 */ // Label 2351: @123386 |
| 43926 | /* 123386 */ GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(123446), // Rule ID 639 // |
| 43927 | /* 123391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 43928 | /* 123394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43929 | /* 123398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 43930 | /* 123402 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 43931 | /* 123406 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 43932 | /* 123410 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43933 | /* 123415 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43934 | /* 123420 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43935 | /* 123422 */ // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43936 | /* 123422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 43937 | /* 123425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43938 | /* 123427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 43939 | /* 123431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 43940 | /* 123435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43941 | /* 123438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43942 | /* 123444 */ GIR_RootConstrainSelectedInstOperands, |
| 43943 | /* 123445 */ // GIR_Coverage, 639, |
| 43944 | /* 123445 */ GIR_EraseRootFromParent_Done, |
| 43945 | /* 123446 */ // Label 2352: @123446 |
| 43946 | /* 123446 */ GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(123476), // Rule ID 688 // |
| 43947 | /* 123451 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 43948 | /* 123454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43949 | /* 123458 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 43950 | /* 123458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD), |
| 43951 | /* 123461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 43952 | /* 123463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 43953 | /* 123465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43954 | /* 123468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43955 | /* 123474 */ GIR_RootConstrainSelectedInstOperands, |
| 43956 | /* 123475 */ // GIR_Coverage, 688, |
| 43957 | /* 123475 */ GIR_EraseRootFromParent_Done, |
| 43958 | /* 123476 */ // Label 2353: @123476 |
| 43959 | /* 123476 */ GIM_Reject, |
| 43960 | /* 123477 */ // Label 2344: @123477 |
| 43961 | /* 123477 */ GIM_Reject, |
| 43962 | /* 123478 */ // Label 2318: @123478 |
| 43963 | /* 123478 */ GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(123515), // Rule ID 1691 // |
| 43964 | /* 123483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43965 | /* 123486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43966 | /* 123489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43967 | /* 123493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43968 | /* 123497 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 43969 | /* 123497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 43970 | /* 123500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43971 | /* 123502 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 43972 | /* 123504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43973 | /* 123507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43974 | /* 123513 */ GIR_RootConstrainSelectedInstOperands, |
| 43975 | /* 123514 */ // GIR_Coverage, 1691, |
| 43976 | /* 123514 */ GIR_EraseRootFromParent_Done, |
| 43977 | /* 123515 */ // Label 2354: @123515 |
| 43978 | /* 123515 */ GIM_Reject, |
| 43979 | /* 123516 */ // Label 2319: @123516 |
| 43980 | /* 123516 */ GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(123553), // Rule ID 1693 // |
| 43981 | /* 123521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 43982 | /* 123524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43983 | /* 123527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43984 | /* 123531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43985 | /* 123535 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 43986 | /* 123535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd), |
| 43987 | /* 123538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43988 | /* 123540 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 43989 | /* 123542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43990 | /* 123545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43991 | /* 123551 */ GIR_RootConstrainSelectedInstOperands, |
| 43992 | /* 123552 */ // GIR_Coverage, 1693, |
| 43993 | /* 123552 */ GIR_EraseRootFromParent_Done, |
| 43994 | /* 123553 */ // Label 2355: @123553 |
| 43995 | /* 123553 */ GIM_Reject, |
| 43996 | /* 123554 */ // Label 2320: @123554 |
| 43997 | /* 123554 */ GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(123652), |
| 43998 | /* 123559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43999 | /* 123562 */ GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(123596), // Rule ID 1692 // |
| 44000 | /* 123567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44001 | /* 123570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44002 | /* 123574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44003 | /* 123578 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 44004 | /* 123578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q), |
| 44005 | /* 123581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44006 | /* 123583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44007 | /* 123585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44008 | /* 123588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44009 | /* 123594 */ GIR_RootConstrainSelectedInstOperands, |
| 44010 | /* 123595 */ // GIR_Coverage, 1692, |
| 44011 | /* 123595 */ GIR_EraseRootFromParent_Done, |
| 44012 | /* 123596 */ // Label 2357: @123596 |
| 44013 | /* 123596 */ GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(123651), // Rule ID 4554 // |
| 44014 | /* 123601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44015 | /* 123604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44016 | /* 123608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44017 | /* 123612 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 44018 | /* 123612 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44019 | /* 123615 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44020 | /* 123619 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44021 | /* 123624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32), |
| 44022 | /* 123627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44023 | /* 123629 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44024 | /* 123631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44025 | /* 123634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44026 | /* 123640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44027 | /* 123646 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44028 | /* 123649 */ GIR_RootConstrainSelectedInstOperands, |
| 44029 | /* 123650 */ // GIR_Coverage, 4554, |
| 44030 | /* 123650 */ GIR_EraseRootFromParent_Done, |
| 44031 | /* 123651 */ // Label 2358: @123651 |
| 44032 | /* 123651 */ GIM_Reject, |
| 44033 | /* 123652 */ // Label 2356: @123652 |
| 44034 | /* 123652 */ GIM_Reject, |
| 44035 | /* 123653 */ // Label 2321: @123653 |
| 44036 | /* 123653 */ GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(123751), |
| 44037 | /* 123658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44038 | /* 123661 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(123695), // Rule ID 1694 // |
| 44039 | /* 123666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 44040 | /* 123669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44041 | /* 123673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44042 | /* 123677 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 44043 | /* 123677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq), |
| 44044 | /* 123680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44045 | /* 123682 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44046 | /* 123684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44047 | /* 123687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44048 | /* 123693 */ GIR_RootConstrainSelectedInstOperands, |
| 44049 | /* 123694 */ // GIR_Coverage, 1694, |
| 44050 | /* 123694 */ GIR_EraseRootFromParent_Done, |
| 44051 | /* 123695 */ // Label 2360: @123695 |
| 44052 | /* 123695 */ GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(123750), // Rule ID 4552 // |
| 44053 | /* 123700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44054 | /* 123703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44055 | /* 123707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44056 | /* 123711 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 44057 | /* 123711 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44058 | /* 123714 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44059 | /* 123718 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44060 | /* 123723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16), |
| 44061 | /* 123726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44062 | /* 123728 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44063 | /* 123730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44064 | /* 123733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44065 | /* 123739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44066 | /* 123745 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44067 | /* 123748 */ GIR_RootConstrainSelectedInstOperands, |
| 44068 | /* 123749 */ // GIR_Coverage, 4552, |
| 44069 | /* 123749 */ GIR_EraseRootFromParent_Done, |
| 44070 | /* 123750 */ // Label 2361: @123750 |
| 44071 | /* 123750 */ GIM_Reject, |
| 44072 | /* 123751 */ // Label 2359: @123751 |
| 44073 | /* 123751 */ GIM_Reject, |
| 44074 | /* 123752 */ // Label 2322: @123752 |
| 44075 | /* 123752 */ GIM_Reject, |
| 44076 | /* 123753 */ // Label 46: @123753 |
| 44077 | /* 123753 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 2365*/ GIMT_Encode4(123988), |
| 44078 | /* 123764 */ /*GILLT_s32*//*Label 2362*/ GIMT_Encode4(123796), |
| 44079 | /* 123768 */ /*GILLT_s64*//*Label 2363*/ GIMT_Encode4(123856), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44080 | /* 123792 */ /*GILLT_v4s32*//*Label 2364*/ GIMT_Encode4(123953), |
| 44081 | /* 123796 */ // Label 2362: @123796 |
| 44082 | /* 123796 */ GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(123855), // Rule ID 2489 // |
| 44083 | /* 123801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16), |
| 44084 | /* 123804 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44085 | /* 123807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44086 | /* 123811 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44087 | /* 123815 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 44088 | /* 123815 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44089 | /* 123818 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44090 | /* 123822 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44091 | /* 123827 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 44092 | /* 123831 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 44093 | /* 123836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS), |
| 44094 | /* 123839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 44095 | /* 123841 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44096 | /* 123844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44097 | /* 123847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44098 | /* 123853 */ GIR_RootConstrainSelectedInstOperands, |
| 44099 | /* 123854 */ // GIR_Coverage, 2489, |
| 44100 | /* 123854 */ GIR_EraseRootFromParent_Done, |
| 44101 | /* 123855 */ // Label 2366: @123855 |
| 44102 | /* 123855 */ GIM_Reject, |
| 44103 | /* 123856 */ // Label 2363: @123856 |
| 44104 | /* 123856 */ GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(123893), // Rule ID 685 // |
| 44105 | /* 123861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 44106 | /* 123864 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44107 | /* 123867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44108 | /* 123871 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44109 | /* 123875 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm) |
| 44110 | /* 123875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS), |
| 44111 | /* 123878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 44112 | /* 123880 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 44113 | /* 123882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44114 | /* 123885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44115 | /* 123891 */ GIR_RootConstrainSelectedInstOperands, |
| 44116 | /* 123892 */ // GIR_Coverage, 685, |
| 44117 | /* 123892 */ GIR_EraseRootFromParent_Done, |
| 44118 | /* 123893 */ // Label 2367: @123893 |
| 44119 | /* 123893 */ GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(123952), // Rule ID 2509 // |
| 44120 | /* 123898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44121 | /* 123901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44122 | /* 123904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44123 | /* 123908 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44124 | /* 123912 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 44125 | /* 123912 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44126 | /* 123915 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44127 | /* 123919 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44128 | /* 123924 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 44129 | /* 123928 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 44130 | /* 123933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD), |
| 44131 | /* 123936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 44132 | /* 123938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44133 | /* 123941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44134 | /* 123944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44135 | /* 123950 */ GIR_RootConstrainSelectedInstOperands, |
| 44136 | /* 123951 */ // GIR_Coverage, 2509, |
| 44137 | /* 123951 */ GIR_EraseRootFromParent_Done, |
| 44138 | /* 123952 */ // Label 2368: @123952 |
| 44139 | /* 123952 */ GIM_Reject, |
| 44140 | /* 123953 */ // Label 2364: @123953 |
| 44141 | /* 123953 */ GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(123987), // Rule ID 3044 // |
| 44142 | /* 123958 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44143 | /* 123961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44144 | /* 123965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44145 | /* 123969 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) |
| 44146 | /* 123969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 44147 | /* 123972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44148 | /* 123974 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 44149 | /* 123976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44150 | /* 123979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44151 | /* 123985 */ GIR_RootConstrainSelectedInstOperands, |
| 44152 | /* 123986 */ // GIR_Coverage, 3044, |
| 44153 | /* 123986 */ GIR_EraseRootFromParent_Done, |
| 44154 | /* 123987 */ // Label 2369: @123987 |
| 44155 | /* 123987 */ GIM_Reject, |
| 44156 | /* 123988 */ // Label 2365: @123988 |
| 44157 | /* 123988 */ GIM_Reject, |
| 44158 | /* 123989 */ // Label 47: @123989 |
| 44159 | /* 123989 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 2373*/ GIMT_Encode4(124260), |
| 44160 | /* 124000 */ /*GILLT_s16*//*Label 2370*/ GIMT_Encode4(124032), |
| 44161 | /* 124004 */ /*GILLT_s32*//*Label 2371*/ GIMT_Encode4(124187), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44162 | /* 124028 */ /*GILLT_v4s16*//*Label 2372*/ GIMT_Encode4(124225), |
| 44163 | /* 124032 */ // Label 2370: @124032 |
| 44164 | /* 124032 */ GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(124109), // Rule ID 2493 // |
| 44165 | /* 124037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16), |
| 44166 | /* 124040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44167 | /* 124043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44168 | /* 124047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44169 | /* 124051 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] }) |
| 44170 | /* 124051 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 44171 | /* 124054 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44172 | /* 124058 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44173 | /* 124063 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 44174 | /* 124065 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44175 | /* 124068 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH), |
| 44176 | /* 124072 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44177 | /* 124077 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 44178 | /* 124080 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 44179 | /* 124084 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44180 | /* 124087 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44181 | /* 124093 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44182 | /* 124095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44183 | /* 124098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44184 | /* 124100 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44185 | /* 124103 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 44186 | /* 124108 */ // GIR_Coverage, 2493, |
| 44187 | /* 124108 */ GIR_EraseRootFromParent_Done, |
| 44188 | /* 124109 */ // Label 2374: @124109 |
| 44189 | /* 124109 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(124186), // Rule ID 2513 // |
| 44190 | /* 124114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44191 | /* 124117 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44192 | /* 124120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44193 | /* 124124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44194 | /* 124128 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] }) |
| 44195 | /* 124128 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 44196 | /* 124131 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44197 | /* 124135 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44198 | /* 124140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 44199 | /* 124142 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44200 | /* 124145 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH), |
| 44201 | /* 124149 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44202 | /* 124154 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 44203 | /* 124157 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm |
| 44204 | /* 124161 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44205 | /* 124164 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44206 | /* 124170 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44207 | /* 124172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44208 | /* 124175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44209 | /* 124177 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44210 | /* 124180 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 44211 | /* 124185 */ // GIR_Coverage, 2513, |
| 44212 | /* 124185 */ GIR_EraseRootFromParent_Done, |
| 44213 | /* 124186 */ // Label 2375: @124186 |
| 44214 | /* 124186 */ GIM_Reject, |
| 44215 | /* 124187 */ // Label 2371: @124187 |
| 44216 | /* 124187 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(124224), // Rule ID 687 // |
| 44217 | /* 124192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 44218 | /* 124195 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44219 | /* 124198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44220 | /* 124202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44221 | /* 124206 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 44222 | /* 124206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD), |
| 44223 | /* 124209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 44224 | /* 124211 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 44225 | /* 124213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44226 | /* 124216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44227 | /* 124222 */ GIR_RootConstrainSelectedInstOperands, |
| 44228 | /* 124223 */ // GIR_Coverage, 687, |
| 44229 | /* 124223 */ GIR_EraseRootFromParent_Done, |
| 44230 | /* 124224 */ // Label 2376: @124224 |
| 44231 | /* 124224 */ GIM_Reject, |
| 44232 | /* 124225 */ // Label 2372: @124225 |
| 44233 | /* 124225 */ GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(124259), // Rule ID 3043 // |
| 44234 | /* 124230 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44235 | /* 124233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44236 | /* 124237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44237 | /* 124241 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) |
| 44238 | /* 124241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 44239 | /* 124244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44240 | /* 124246 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 44241 | /* 124248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44242 | /* 124251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44243 | /* 124257 */ GIR_RootConstrainSelectedInstOperands, |
| 44244 | /* 124258 */ // GIR_Coverage, 3043, |
| 44245 | /* 124258 */ GIR_EraseRootFromParent_Done, |
| 44246 | /* 124259 */ // Label 2377: @124259 |
| 44247 | /* 124259 */ GIM_Reject, |
| 44248 | /* 124260 */ // Label 2373: @124260 |
| 44249 | /* 124260 */ GIM_Reject, |
| 44250 | /* 124261 */ // Label 48: @124261 |
| 44251 | /* 124261 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2385*/ GIMT_Encode4(125594), |
| 44252 | /* 124272 */ /*GILLT_s32*//*Label 2378*/ GIMT_Encode4(124320), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44253 | /* 124284 */ /*GILLT_v2s32*//*Label 2379*/ GIMT_Encode4(125214), GIMT_Encode4(0), |
| 44254 | /* 124292 */ /*GILLT_v4s1*//*Label 2380*/ GIMT_Encode4(125252), |
| 44255 | /* 124296 */ /*GILLT_v4s16*//*Label 2381*/ GIMT_Encode4(125305), |
| 44256 | /* 124300 */ /*GILLT_v4s32*//*Label 2382*/ GIMT_Encode4(125343), GIMT_Encode4(0), |
| 44257 | /* 124308 */ /*GILLT_v8s1*//*Label 2383*/ GIMT_Encode4(125442), GIMT_Encode4(0), |
| 44258 | /* 124316 */ /*GILLT_v8s16*//*Label 2384*/ GIMT_Encode4(125495), |
| 44259 | /* 124320 */ // Label 2378: @124320 |
| 44260 | /* 124320 */ GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(124386), // Rule ID 2543 // |
| 44261 | /* 124325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44262 | /* 124328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44263 | /* 124331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44264 | /* 124335 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44265 | /* 124339 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 44266 | /* 124343 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 44267 | /* 124347 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44268 | /* 124352 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44269 | /* 124354 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44270 | /* 124354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44271 | /* 124357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH), |
| 44272 | /* 124361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44273 | /* 124366 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44274 | /* 124370 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44275 | /* 124372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44276 | /* 124375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44277 | /* 124377 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44278 | /* 124380 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44279 | /* 124385 */ // GIR_Coverage, 2543, |
| 44280 | /* 124385 */ GIR_EraseRootFromParent_Done, |
| 44281 | /* 124386 */ // Label 2386: @124386 |
| 44282 | /* 124386 */ GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(124452), // Rule ID 2551 // |
| 44283 | /* 124391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44284 | /* 124394 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44285 | /* 124397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44286 | /* 124401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44287 | /* 124405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 44288 | /* 124409 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44289 | /* 124413 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44290 | /* 124418 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44291 | /* 124420 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44292 | /* 124420 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44293 | /* 124423 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS), |
| 44294 | /* 124427 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44295 | /* 124432 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44296 | /* 124436 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44297 | /* 124438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44298 | /* 124441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44299 | /* 124443 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44300 | /* 124446 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44301 | /* 124451 */ // GIR_Coverage, 2551, |
| 44302 | /* 124451 */ GIR_EraseRootFromParent_Done, |
| 44303 | /* 124452 */ // Label 2387: @124452 |
| 44304 | /* 124452 */ GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(124518), // Rule ID 2559 // |
| 44305 | /* 124457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44306 | /* 124460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44307 | /* 124463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44308 | /* 124467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44309 | /* 124471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 44310 | /* 124475 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 44311 | /* 124479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44312 | /* 124484 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44313 | /* 124486 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44314 | /* 124486 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44315 | /* 124489 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD), |
| 44316 | /* 124493 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44317 | /* 124498 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44318 | /* 124502 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44319 | /* 124504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44320 | /* 124507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44321 | /* 124509 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44322 | /* 124512 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44323 | /* 124517 */ // GIR_Coverage, 2559, |
| 44324 | /* 124517 */ GIR_EraseRootFromParent_Done, |
| 44325 | /* 124518 */ // Label 2388: @124518 |
| 44326 | /* 124518 */ GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(124584), // Rule ID 2567 // |
| 44327 | /* 124523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44328 | /* 124526 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44329 | /* 124529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44330 | /* 124533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44331 | /* 124537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 44332 | /* 124541 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 44333 | /* 124545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44334 | /* 124550 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44335 | /* 124552 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44336 | /* 124552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44337 | /* 124555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH), |
| 44338 | /* 124559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44339 | /* 124564 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44340 | /* 124568 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44341 | /* 124570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44342 | /* 124573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44343 | /* 124575 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44344 | /* 124578 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44345 | /* 124583 */ // GIR_Coverage, 2567, |
| 44346 | /* 124583 */ GIR_EraseRootFromParent_Done, |
| 44347 | /* 124584 */ // Label 2389: @124584 |
| 44348 | /* 124584 */ GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(124650), // Rule ID 2575 // |
| 44349 | /* 124589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44350 | /* 124592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44351 | /* 124595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44352 | /* 124599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44353 | /* 124603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 44354 | /* 124607 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44355 | /* 124611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44356 | /* 124616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44357 | /* 124618 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44358 | /* 124618 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44359 | /* 124621 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS), |
| 44360 | /* 124625 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44361 | /* 124630 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44362 | /* 124634 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44363 | /* 124636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44364 | /* 124639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44365 | /* 124641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44366 | /* 124644 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44367 | /* 124649 */ // GIR_Coverage, 2575, |
| 44368 | /* 124649 */ GIR_EraseRootFromParent_Done, |
| 44369 | /* 124650 */ // Label 2390: @124650 |
| 44370 | /* 124650 */ GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(124716), // Rule ID 2583 // |
| 44371 | /* 124655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44372 | /* 124658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44373 | /* 124661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44374 | /* 124665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44375 | /* 124669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 44376 | /* 124673 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 44377 | /* 124677 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44378 | /* 124682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44379 | /* 124684 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44380 | /* 124684 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44381 | /* 124687 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD), |
| 44382 | /* 124691 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44383 | /* 124696 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44384 | /* 124700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44385 | /* 124702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44386 | /* 124705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44387 | /* 124707 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44388 | /* 124710 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44389 | /* 124715 */ // GIR_Coverage, 2583, |
| 44390 | /* 124715 */ GIR_EraseRootFromParent_Done, |
| 44391 | /* 124716 */ // Label 2391: @124716 |
| 44392 | /* 124716 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(124782), // Rule ID 2519 // |
| 44393 | /* 124721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44394 | /* 124724 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44395 | /* 124727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44396 | /* 124731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44397 | /* 124735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 44398 | /* 124739 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 44399 | /* 124743 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44400 | /* 124748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44401 | /* 124750 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44402 | /* 124750 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44403 | /* 124753 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH), |
| 44404 | /* 124757 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44405 | /* 124762 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44406 | /* 124766 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44407 | /* 124768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44408 | /* 124771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44409 | /* 124773 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44410 | /* 124776 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44411 | /* 124781 */ // GIR_Coverage, 2519, |
| 44412 | /* 124781 */ GIR_EraseRootFromParent_Done, |
| 44413 | /* 124782 */ // Label 2392: @124782 |
| 44414 | /* 124782 */ GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(124848), // Rule ID 2527 // |
| 44415 | /* 124787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44416 | /* 124790 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44417 | /* 124793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44418 | /* 124797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44419 | /* 124801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 44420 | /* 124805 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44421 | /* 124809 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44422 | /* 124814 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44423 | /* 124816 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44424 | /* 124816 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44425 | /* 124819 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS), |
| 44426 | /* 124823 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44427 | /* 124828 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44428 | /* 124832 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44429 | /* 124834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44430 | /* 124837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44431 | /* 124839 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44432 | /* 124842 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44433 | /* 124847 */ // GIR_Coverage, 2527, |
| 44434 | /* 124847 */ GIR_EraseRootFromParent_Done, |
| 44435 | /* 124848 */ // Label 2393: @124848 |
| 44436 | /* 124848 */ GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(124914), // Rule ID 2535 // |
| 44437 | /* 124853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44438 | /* 124856 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44439 | /* 124859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44440 | /* 124863 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44441 | /* 124867 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 44442 | /* 124871 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 44443 | /* 124875 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44444 | /* 124880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44445 | /* 124882 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44446 | /* 124882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44447 | /* 124885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD), |
| 44448 | /* 124889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44449 | /* 124894 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44450 | /* 124898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44451 | /* 124900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44452 | /* 124903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44453 | /* 124905 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44454 | /* 124908 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44455 | /* 124913 */ // GIR_Coverage, 2535, |
| 44456 | /* 124913 */ GIR_EraseRootFromParent_Done, |
| 44457 | /* 124914 */ // Label 2394: @124914 |
| 44458 | /* 124914 */ GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(124974), // Rule ID 2616 // |
| 44459 | /* 124919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 44460 | /* 124922 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44461 | /* 124925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44462 | /* 124929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44463 | /* 124933 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44464 | /* 124933 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44465 | /* 124936 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD), |
| 44466 | /* 124940 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44467 | /* 124945 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44468 | /* 124949 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44469 | /* 124952 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44470 | /* 124958 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44471 | /* 124960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44472 | /* 124963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44473 | /* 124965 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44474 | /* 124968 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44475 | /* 124973 */ // GIR_Coverage, 2616, |
| 44476 | /* 124973 */ GIR_EraseRootFromParent_Done, |
| 44477 | /* 124974 */ // Label 2395: @124974 |
| 44478 | /* 124974 */ GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(125034), // Rule ID 2622 // |
| 44479 | /* 124979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 44480 | /* 124982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44481 | /* 124985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44482 | /* 124989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44483 | /* 124993 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44484 | /* 124993 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44485 | /* 124996 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS), |
| 44486 | /* 125000 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44487 | /* 125005 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44488 | /* 125009 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44489 | /* 125012 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44490 | /* 125018 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44491 | /* 125020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44492 | /* 125023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44493 | /* 125025 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44494 | /* 125028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44495 | /* 125033 */ // GIR_Coverage, 2622, |
| 44496 | /* 125033 */ GIR_EraseRootFromParent_Done, |
| 44497 | /* 125034 */ // Label 2396: @125034 |
| 44498 | /* 125034 */ GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(125094), // Rule ID 2628 // |
| 44499 | /* 125039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 44500 | /* 125042 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44501 | /* 125045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44502 | /* 125049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44503 | /* 125053 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44504 | /* 125053 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44505 | /* 125056 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH), |
| 44506 | /* 125060 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44507 | /* 125065 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44508 | /* 125069 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44509 | /* 125072 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44510 | /* 125078 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44511 | /* 125080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44512 | /* 125083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44513 | /* 125085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44514 | /* 125088 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44515 | /* 125093 */ // GIR_Coverage, 2628, |
| 44516 | /* 125093 */ GIR_EraseRootFromParent_Done, |
| 44517 | /* 125094 */ // Label 2397: @125094 |
| 44518 | /* 125094 */ GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(125213), // Rule ID 3084 // |
| 44519 | /* 125099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 44520 | /* 125102 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44521 | /* 125105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44522 | /* 125109 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44523 | /* 125113 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 44524 | /* 125113 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 44525 | /* 125116 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44526 | /* 125120 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44527 | /* 125125 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 44528 | /* 125127 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 44529 | /* 125130 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 44530 | /* 125134 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44531 | /* 125139 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 44532 | /* 125142 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44533 | /* 125146 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 44534 | /* 125149 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 44535 | /* 125154 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 44536 | /* 125159 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 44537 | /* 125164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 44538 | /* 125167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 44539 | /* 125171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44540 | /* 125176 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 44541 | /* 125179 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44542 | /* 125182 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44543 | /* 125188 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44544 | /* 125190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44545 | /* 125193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44546 | /* 125195 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 44547 | /* 125202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 44548 | /* 125207 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 44549 | /* 125212 */ // GIR_Coverage, 3084, |
| 44550 | /* 125212 */ GIR_EraseRootFromParent_Done, |
| 44551 | /* 125213 */ // Label 2398: @125213 |
| 44552 | /* 125213 */ GIM_Reject, |
| 44553 | /* 125214 */ // Label 2379: @125214 |
| 44554 | /* 125214 */ GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(125251), // Rule ID 1765 // |
| 44555 | /* 125219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44556 | /* 125222 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44557 | /* 125225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44558 | /* 125229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44559 | /* 125233 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 44560 | /* 125233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 44561 | /* 125236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44562 | /* 125238 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44563 | /* 125240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44564 | /* 125243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44565 | /* 125249 */ GIR_RootConstrainSelectedInstOperands, |
| 44566 | /* 125250 */ // GIR_Coverage, 1765, |
| 44567 | /* 125250 */ GIR_EraseRootFromParent_Done, |
| 44568 | /* 125251 */ // Label 2399: @125251 |
| 44569 | /* 125251 */ GIM_Reject, |
| 44570 | /* 125252 */ // Label 2380: @125252 |
| 44571 | /* 125252 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(125304), // Rule ID 5619 // |
| 44572 | /* 125257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 44573 | /* 125260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44574 | /* 125263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 44575 | /* 125267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44576 | /* 125271 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 44577 | /* 125271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 44578 | /* 125274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 44579 | /* 125276 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 44580 | /* 125278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44581 | /* 125284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 44582 | /* 125287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44583 | /* 125290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44584 | /* 125296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44585 | /* 125302 */ GIR_RootConstrainSelectedInstOperands, |
| 44586 | /* 125303 */ // GIR_Coverage, 5619, |
| 44587 | /* 125303 */ GIR_EraseRootFromParent_Done, |
| 44588 | /* 125304 */ // Label 2400: @125304 |
| 44589 | /* 125304 */ GIM_Reject, |
| 44590 | /* 125305 */ // Label 2381: @125305 |
| 44591 | /* 125305 */ GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(125342), // Rule ID 1773 // |
| 44592 | /* 125310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 44593 | /* 125313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44594 | /* 125316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44595 | /* 125320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44596 | /* 125324 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 44597 | /* 125324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd), |
| 44598 | /* 125327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44599 | /* 125329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44600 | /* 125331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44601 | /* 125334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44602 | /* 125340 */ GIR_RootConstrainSelectedInstOperands, |
| 44603 | /* 125341 */ // GIR_Coverage, 1773, |
| 44604 | /* 125341 */ GIR_EraseRootFromParent_Done, |
| 44605 | /* 125342 */ // Label 2401: @125342 |
| 44606 | /* 125342 */ GIM_Reject, |
| 44607 | /* 125343 */ // Label 2382: @125343 |
| 44608 | /* 125343 */ GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(125441), |
| 44609 | /* 125348 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44610 | /* 125351 */ GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(125385), // Rule ID 1769 // |
| 44611 | /* 125356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44612 | /* 125359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44613 | /* 125363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44614 | /* 125367 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 44615 | /* 125367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq), |
| 44616 | /* 125370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44617 | /* 125372 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44618 | /* 125374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44619 | /* 125377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44620 | /* 125383 */ GIR_RootConstrainSelectedInstOperands, |
| 44621 | /* 125384 */ // GIR_Coverage, 1769, |
| 44622 | /* 125384 */ GIR_EraseRootFromParent_Done, |
| 44623 | /* 125385 */ // Label 2403: @125385 |
| 44624 | /* 125385 */ GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(125440), // Rule ID 4526 // |
| 44625 | /* 125390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 44626 | /* 125393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44627 | /* 125397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44628 | /* 125401 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 44629 | /* 125401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44630 | /* 125404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44631 | /* 125408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44632 | /* 125413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 44633 | /* 125416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44634 | /* 125418 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 44635 | /* 125420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44636 | /* 125423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44637 | /* 125429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44638 | /* 125435 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44639 | /* 125438 */ GIR_RootConstrainSelectedInstOperands, |
| 44640 | /* 125439 */ // GIR_Coverage, 4526, |
| 44641 | /* 125439 */ GIR_EraseRootFromParent_Done, |
| 44642 | /* 125440 */ // Label 2404: @125440 |
| 44643 | /* 125440 */ GIM_Reject, |
| 44644 | /* 125441 */ // Label 2402: @125441 |
| 44645 | /* 125441 */ GIM_Reject, |
| 44646 | /* 125442 */ // Label 2383: @125442 |
| 44647 | /* 125442 */ GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(125494), // Rule ID 5620 // |
| 44648 | /* 125447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 44649 | /* 125450 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44650 | /* 125453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 44651 | /* 125457 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44652 | /* 125461 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 44653 | /* 125461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 44654 | /* 125464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 44655 | /* 125466 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 44656 | /* 125468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44657 | /* 125474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 44658 | /* 125477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44659 | /* 125480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44660 | /* 125486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44661 | /* 125492 */ GIR_RootConstrainSelectedInstOperands, |
| 44662 | /* 125493 */ // GIR_Coverage, 5620, |
| 44663 | /* 125493 */ GIR_EraseRootFromParent_Done, |
| 44664 | /* 125494 */ // Label 2405: @125494 |
| 44665 | /* 125494 */ GIM_Reject, |
| 44666 | /* 125495 */ // Label 2384: @125495 |
| 44667 | /* 125495 */ GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(125593), |
| 44668 | /* 125500 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44669 | /* 125503 */ GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(125537), // Rule ID 1777 // |
| 44670 | /* 125508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 44671 | /* 125511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44672 | /* 125515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44673 | /* 125519 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 44674 | /* 125519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq), |
| 44675 | /* 125522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44676 | /* 125524 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44677 | /* 125526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44678 | /* 125529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44679 | /* 125535 */ GIR_RootConstrainSelectedInstOperands, |
| 44680 | /* 125536 */ // GIR_Coverage, 1777, |
| 44681 | /* 125536 */ GIR_EraseRootFromParent_Done, |
| 44682 | /* 125537 */ // Label 2407: @125537 |
| 44683 | /* 125537 */ GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(125592), // Rule ID 4520 // |
| 44684 | /* 125542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 44685 | /* 125545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44686 | /* 125549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44687 | /* 125553 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 44688 | /* 125553 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44689 | /* 125556 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44690 | /* 125560 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44691 | /* 125565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 44692 | /* 125568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44693 | /* 125570 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 44694 | /* 125572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44695 | /* 125575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44696 | /* 125581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44697 | /* 125587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44698 | /* 125590 */ GIR_RootConstrainSelectedInstOperands, |
| 44699 | /* 125591 */ // GIR_Coverage, 4520, |
| 44700 | /* 125591 */ GIR_EraseRootFromParent_Done, |
| 44701 | /* 125592 */ // Label 2408: @125592 |
| 44702 | /* 125592 */ GIM_Reject, |
| 44703 | /* 125593 */ // Label 2406: @125593 |
| 44704 | /* 125593 */ GIM_Reject, |
| 44705 | /* 125594 */ // Label 2385: @125594 |
| 44706 | /* 125594 */ GIM_Reject, |
| 44707 | /* 125595 */ // Label 49: @125595 |
| 44708 | /* 125595 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2416*/ GIMT_Encode4(126928), |
| 44709 | /* 125606 */ /*GILLT_s32*//*Label 2409*/ GIMT_Encode4(125654), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44710 | /* 125618 */ /*GILLT_v2s32*//*Label 2410*/ GIMT_Encode4(126548), GIMT_Encode4(0), |
| 44711 | /* 125626 */ /*GILLT_v4s1*//*Label 2411*/ GIMT_Encode4(126586), |
| 44712 | /* 125630 */ /*GILLT_v4s16*//*Label 2412*/ GIMT_Encode4(126639), |
| 44713 | /* 125634 */ /*GILLT_v4s32*//*Label 2413*/ GIMT_Encode4(126677), GIMT_Encode4(0), |
| 44714 | /* 125642 */ /*GILLT_v8s1*//*Label 2414*/ GIMT_Encode4(126776), GIMT_Encode4(0), |
| 44715 | /* 125650 */ /*GILLT_v8s16*//*Label 2415*/ GIMT_Encode4(126829), |
| 44716 | /* 125654 */ // Label 2409: @125654 |
| 44717 | /* 125654 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(125720), // Rule ID 2547 // |
| 44718 | /* 125659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44719 | /* 125662 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44720 | /* 125665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44721 | /* 125669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44722 | /* 125673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 44723 | /* 125677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 44724 | /* 125681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44725 | /* 125686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44726 | /* 125688 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44727 | /* 125688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44728 | /* 125691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH), |
| 44729 | /* 125695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44730 | /* 125700 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44731 | /* 125704 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44732 | /* 125706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44733 | /* 125709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44734 | /* 125711 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44735 | /* 125714 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44736 | /* 125719 */ // GIR_Coverage, 2547, |
| 44737 | /* 125719 */ GIR_EraseRootFromParent_Done, |
| 44738 | /* 125720 */ // Label 2417: @125720 |
| 44739 | /* 125720 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(125786), // Rule ID 2555 // |
| 44740 | /* 125725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44741 | /* 125728 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44742 | /* 125731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44743 | /* 125735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44744 | /* 125739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 44745 | /* 125743 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44746 | /* 125747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44747 | /* 125752 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44748 | /* 125754 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44749 | /* 125754 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44750 | /* 125757 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS), |
| 44751 | /* 125761 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44752 | /* 125766 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44753 | /* 125770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44754 | /* 125772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44755 | /* 125775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44756 | /* 125777 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44757 | /* 125780 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44758 | /* 125785 */ // GIR_Coverage, 2555, |
| 44759 | /* 125785 */ GIR_EraseRootFromParent_Done, |
| 44760 | /* 125786 */ // Label 2418: @125786 |
| 44761 | /* 125786 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(125852), // Rule ID 2563 // |
| 44762 | /* 125791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44763 | /* 125794 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44764 | /* 125797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44765 | /* 125801 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44766 | /* 125805 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 44767 | /* 125809 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 44768 | /* 125813 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44769 | /* 125818 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44770 | /* 125820 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44771 | /* 125820 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44772 | /* 125823 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD), |
| 44773 | /* 125827 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44774 | /* 125832 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44775 | /* 125836 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44776 | /* 125838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44777 | /* 125841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44778 | /* 125843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44779 | /* 125846 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44780 | /* 125851 */ // GIR_Coverage, 2563, |
| 44781 | /* 125851 */ GIR_EraseRootFromParent_Done, |
| 44782 | /* 125852 */ // Label 2419: @125852 |
| 44783 | /* 125852 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(125918), // Rule ID 2571 // |
| 44784 | /* 125857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44785 | /* 125860 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44786 | /* 125863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44787 | /* 125867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44788 | /* 125871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 44789 | /* 125875 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 44790 | /* 125879 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44791 | /* 125884 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44792 | /* 125886 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44793 | /* 125886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44794 | /* 125889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH), |
| 44795 | /* 125893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44796 | /* 125898 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44797 | /* 125902 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44798 | /* 125904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44799 | /* 125907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44800 | /* 125909 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44801 | /* 125912 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44802 | /* 125917 */ // GIR_Coverage, 2571, |
| 44803 | /* 125917 */ GIR_EraseRootFromParent_Done, |
| 44804 | /* 125918 */ // Label 2420: @125918 |
| 44805 | /* 125918 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(125984), // Rule ID 2579 // |
| 44806 | /* 125923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44807 | /* 125926 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44808 | /* 125929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44809 | /* 125933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44810 | /* 125937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 44811 | /* 125941 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44812 | /* 125945 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44813 | /* 125950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44814 | /* 125952 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44815 | /* 125952 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44816 | /* 125955 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS), |
| 44817 | /* 125959 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44818 | /* 125964 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44819 | /* 125968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44820 | /* 125970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44821 | /* 125973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44822 | /* 125975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44823 | /* 125978 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44824 | /* 125983 */ // GIR_Coverage, 2579, |
| 44825 | /* 125983 */ GIR_EraseRootFromParent_Done, |
| 44826 | /* 125984 */ // Label 2421: @125984 |
| 44827 | /* 125984 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(126050), // Rule ID 2587 // |
| 44828 | /* 125989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44829 | /* 125992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44830 | /* 125995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44831 | /* 125999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44832 | /* 126003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 44833 | /* 126007 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 44834 | /* 126011 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44835 | /* 126016 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44836 | /* 126018 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44837 | /* 126018 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44838 | /* 126021 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD), |
| 44839 | /* 126025 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44840 | /* 126030 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44841 | /* 126034 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44842 | /* 126036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44843 | /* 126039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44844 | /* 126041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44845 | /* 126044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44846 | /* 126049 */ // GIR_Coverage, 2587, |
| 44847 | /* 126049 */ GIR_EraseRootFromParent_Done, |
| 44848 | /* 126050 */ // Label 2422: @126050 |
| 44849 | /* 126050 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(126116), // Rule ID 2523 // |
| 44850 | /* 126055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44851 | /* 126058 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44852 | /* 126061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44853 | /* 126065 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44854 | /* 126069 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 44855 | /* 126073 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 44856 | /* 126077 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44857 | /* 126082 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44858 | /* 126084 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44859 | /* 126084 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44860 | /* 126087 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH), |
| 44861 | /* 126091 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44862 | /* 126096 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44863 | /* 126100 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44864 | /* 126102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44865 | /* 126105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44866 | /* 126107 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44867 | /* 126110 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44868 | /* 126115 */ // GIR_Coverage, 2523, |
| 44869 | /* 126115 */ GIR_EraseRootFromParent_Done, |
| 44870 | /* 126116 */ // Label 2423: @126116 |
| 44871 | /* 126116 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(126182), // Rule ID 2531 // |
| 44872 | /* 126121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44873 | /* 126124 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44874 | /* 126127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44875 | /* 126131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44876 | /* 126135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 44877 | /* 126139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44878 | /* 126143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44879 | /* 126148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44880 | /* 126150 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44881 | /* 126150 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44882 | /* 126153 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS), |
| 44883 | /* 126157 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44884 | /* 126162 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44885 | /* 126166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44886 | /* 126168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44887 | /* 126171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44888 | /* 126173 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44889 | /* 126176 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44890 | /* 126181 */ // GIR_Coverage, 2531, |
| 44891 | /* 126181 */ GIR_EraseRootFromParent_Done, |
| 44892 | /* 126182 */ // Label 2424: @126182 |
| 44893 | /* 126182 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(126248), // Rule ID 2539 // |
| 44894 | /* 126187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44895 | /* 126190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44896 | /* 126193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44897 | /* 126197 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44898 | /* 126201 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 44899 | /* 126205 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 44900 | /* 126209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44901 | /* 126214 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44902 | /* 126216 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44903 | /* 126216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44904 | /* 126219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD), |
| 44905 | /* 126223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44906 | /* 126228 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 44907 | /* 126232 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44908 | /* 126234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44909 | /* 126237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44910 | /* 126239 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44911 | /* 126242 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44912 | /* 126247 */ // GIR_Coverage, 2539, |
| 44913 | /* 126247 */ GIR_EraseRootFromParent_Done, |
| 44914 | /* 126248 */ // Label 2425: @126248 |
| 44915 | /* 126248 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(126308), // Rule ID 2631 // |
| 44916 | /* 126253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 44917 | /* 126256 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44918 | /* 126259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44919 | /* 126263 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44920 | /* 126267 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 44921 | /* 126267 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44922 | /* 126270 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD), |
| 44923 | /* 126274 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44924 | /* 126279 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44925 | /* 126283 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44926 | /* 126286 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44927 | /* 126292 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44928 | /* 126294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44929 | /* 126297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44930 | /* 126299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44931 | /* 126302 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44932 | /* 126307 */ // GIR_Coverage, 2631, |
| 44933 | /* 126307 */ GIR_EraseRootFromParent_Done, |
| 44934 | /* 126308 */ // Label 2426: @126308 |
| 44935 | /* 126308 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(126368), // Rule ID 2637 // |
| 44936 | /* 126313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 44937 | /* 126316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44938 | /* 126319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44939 | /* 126323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44940 | /* 126327 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 44941 | /* 126327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44942 | /* 126330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS), |
| 44943 | /* 126334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44944 | /* 126339 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44945 | /* 126343 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44946 | /* 126346 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44947 | /* 126352 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44948 | /* 126354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44949 | /* 126357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44950 | /* 126359 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44951 | /* 126362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44952 | /* 126367 */ // GIR_Coverage, 2637, |
| 44953 | /* 126367 */ GIR_EraseRootFromParent_Done, |
| 44954 | /* 126368 */ // Label 2427: @126368 |
| 44955 | /* 126368 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(126428), // Rule ID 2643 // |
| 44956 | /* 126373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 44957 | /* 126376 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44958 | /* 126379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44959 | /* 126383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44960 | /* 126387 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 44961 | /* 126387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44962 | /* 126390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH), |
| 44963 | /* 126394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44964 | /* 126399 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44965 | /* 126403 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44966 | /* 126406 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44967 | /* 126412 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44968 | /* 126414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44969 | /* 126417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44970 | /* 126419 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44971 | /* 126422 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 44972 | /* 126427 */ // GIR_Coverage, 2643, |
| 44973 | /* 126427 */ GIR_EraseRootFromParent_Done, |
| 44974 | /* 126428 */ // Label 2428: @126428 |
| 44975 | /* 126428 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(126547), // Rule ID 3085 // |
| 44976 | /* 126433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 44977 | /* 126436 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44978 | /* 126439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44979 | /* 126443 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44980 | /* 126447 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 44981 | /* 126447 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 44982 | /* 126450 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44983 | /* 126454 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44984 | /* 126459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 44985 | /* 126461 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 44986 | /* 126464 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 44987 | /* 126468 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44988 | /* 126473 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 44989 | /* 126476 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 44990 | /* 126480 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 44991 | /* 126483 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 44992 | /* 126488 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 44993 | /* 126493 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 44994 | /* 126498 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 44995 | /* 126501 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 44996 | /* 126505 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44997 | /* 126510 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 44998 | /* 126513 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44999 | /* 126516 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45000 | /* 126522 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45001 | /* 126524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45002 | /* 126527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 45003 | /* 126529 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 45004 | /* 126536 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45005 | /* 126541 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45006 | /* 126546 */ // GIR_Coverage, 3085, |
| 45007 | /* 126546 */ GIR_EraseRootFromParent_Done, |
| 45008 | /* 126547 */ // Label 2429: @126547 |
| 45009 | /* 126547 */ GIM_Reject, |
| 45010 | /* 126548 */ // Label 2410: @126548 |
| 45011 | /* 126548 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(126585), // Rule ID 1766 // |
| 45012 | /* 126553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45013 | /* 126556 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45014 | /* 126559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45015 | /* 126563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45016 | /* 126567 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 45017 | /* 126567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 45018 | /* 126570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45019 | /* 126572 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45020 | /* 126574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45021 | /* 126577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45022 | /* 126583 */ GIR_RootConstrainSelectedInstOperands, |
| 45023 | /* 126584 */ // GIR_Coverage, 1766, |
| 45024 | /* 126584 */ GIR_EraseRootFromParent_Done, |
| 45025 | /* 126585 */ // Label 2430: @126585 |
| 45026 | /* 126585 */ GIM_Reject, |
| 45027 | /* 126586 */ // Label 2411: @126586 |
| 45028 | /* 126586 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(126638), // Rule ID 5617 // |
| 45029 | /* 126591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45030 | /* 126594 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45031 | /* 126597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 45032 | /* 126601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45033 | /* 126605 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 45034 | /* 126605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 45035 | /* 126608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 45036 | /* 126610 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 45037 | /* 126612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45038 | /* 126618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 45039 | /* 126621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45040 | /* 126624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45041 | /* 126630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45042 | /* 126636 */ GIR_RootConstrainSelectedInstOperands, |
| 45043 | /* 126637 */ // GIR_Coverage, 5617, |
| 45044 | /* 126637 */ GIR_EraseRootFromParent_Done, |
| 45045 | /* 126638 */ // Label 2431: @126638 |
| 45046 | /* 126638 */ GIM_Reject, |
| 45047 | /* 126639 */ // Label 2412: @126639 |
| 45048 | /* 126639 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(126676), // Rule ID 1774 // |
| 45049 | /* 126644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45050 | /* 126647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45051 | /* 126650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45052 | /* 126654 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45053 | /* 126658 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 45054 | /* 126658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud), |
| 45055 | /* 126661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45056 | /* 126663 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45057 | /* 126665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45058 | /* 126668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45059 | /* 126674 */ GIR_RootConstrainSelectedInstOperands, |
| 45060 | /* 126675 */ // GIR_Coverage, 1774, |
| 45061 | /* 126675 */ GIR_EraseRootFromParent_Done, |
| 45062 | /* 126676 */ // Label 2432: @126676 |
| 45063 | /* 126676 */ GIM_Reject, |
| 45064 | /* 126677 */ // Label 2413: @126677 |
| 45065 | /* 126677 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(126775), |
| 45066 | /* 126682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45067 | /* 126685 */ GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(126719), // Rule ID 1770 // |
| 45068 | /* 126690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45069 | /* 126693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45070 | /* 126697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45071 | /* 126701 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 45072 | /* 126701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq), |
| 45073 | /* 126704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45074 | /* 126706 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45075 | /* 126708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45076 | /* 126711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45077 | /* 126717 */ GIR_RootConstrainSelectedInstOperands, |
| 45078 | /* 126718 */ // GIR_Coverage, 1770, |
| 45079 | /* 126718 */ GIR_EraseRootFromParent_Done, |
| 45080 | /* 126719 */ // Label 2434: @126719 |
| 45081 | /* 126719 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(126774), // Rule ID 4529 // |
| 45082 | /* 126724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45083 | /* 126727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45084 | /* 126731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45085 | /* 126735 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 45086 | /* 126735 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45087 | /* 126738 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45088 | /* 126742 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45089 | /* 126747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 45090 | /* 126750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45091 | /* 126752 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45092 | /* 126754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45093 | /* 126757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45094 | /* 126763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45095 | /* 126769 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45096 | /* 126772 */ GIR_RootConstrainSelectedInstOperands, |
| 45097 | /* 126773 */ // GIR_Coverage, 4529, |
| 45098 | /* 126773 */ GIR_EraseRootFromParent_Done, |
| 45099 | /* 126774 */ // Label 2435: @126774 |
| 45100 | /* 126774 */ GIM_Reject, |
| 45101 | /* 126775 */ // Label 2433: @126775 |
| 45102 | /* 126775 */ GIM_Reject, |
| 45103 | /* 126776 */ // Label 2414: @126776 |
| 45104 | /* 126776 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(126828), // Rule ID 5618 // |
| 45105 | /* 126781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45106 | /* 126784 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45107 | /* 126787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 45108 | /* 126791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45109 | /* 126795 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 45110 | /* 126795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 45111 | /* 126798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 45112 | /* 126800 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 45113 | /* 126802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45114 | /* 126808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 45115 | /* 126811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45116 | /* 126814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45117 | /* 126820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45118 | /* 126826 */ GIR_RootConstrainSelectedInstOperands, |
| 45119 | /* 126827 */ // GIR_Coverage, 5618, |
| 45120 | /* 126827 */ GIR_EraseRootFromParent_Done, |
| 45121 | /* 126828 */ // Label 2436: @126828 |
| 45122 | /* 126828 */ GIM_Reject, |
| 45123 | /* 126829 */ // Label 2415: @126829 |
| 45124 | /* 126829 */ GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(126927), |
| 45125 | /* 126834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45126 | /* 126837 */ GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(126871), // Rule ID 1778 // |
| 45127 | /* 126842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45128 | /* 126845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45129 | /* 126849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45130 | /* 126853 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 45131 | /* 126853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq), |
| 45132 | /* 126856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45133 | /* 126858 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45134 | /* 126860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45135 | /* 126863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45136 | /* 126869 */ GIR_RootConstrainSelectedInstOperands, |
| 45137 | /* 126870 */ // GIR_Coverage, 1778, |
| 45138 | /* 126870 */ GIR_EraseRootFromParent_Done, |
| 45139 | /* 126871 */ // Label 2438: @126871 |
| 45140 | /* 126871 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(126926), // Rule ID 4523 // |
| 45141 | /* 126876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45142 | /* 126879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45143 | /* 126883 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45144 | /* 126887 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 45145 | /* 126887 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45146 | /* 126890 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45147 | /* 126894 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45148 | /* 126899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 45149 | /* 126902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45150 | /* 126904 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45151 | /* 126906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45152 | /* 126909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45153 | /* 126915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45154 | /* 126921 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45155 | /* 126924 */ GIR_RootConstrainSelectedInstOperands, |
| 45156 | /* 126925 */ // GIR_Coverage, 4523, |
| 45157 | /* 126925 */ GIR_EraseRootFromParent_Done, |
| 45158 | /* 126926 */ // Label 2439: @126926 |
| 45159 | /* 126926 */ GIM_Reject, |
| 45160 | /* 126927 */ // Label 2437: @126927 |
| 45161 | /* 126927 */ GIM_Reject, |
| 45162 | /* 126928 */ // Label 2416: @126928 |
| 45163 | /* 126928 */ GIM_Reject, |
| 45164 | /* 126929 */ // Label 50: @126929 |
| 45165 | /* 126929 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2447*/ GIMT_Encode4(127580), |
| 45166 | /* 126940 */ /*GILLT_s16*//*Label 2440*/ GIMT_Encode4(126992), |
| 45167 | /* 126944 */ /*GILLT_s32*//*Label 2441*/ GIMT_Encode4(127052), |
| 45168 | /* 126948 */ /*GILLT_s64*//*Label 2442*/ GIMT_Encode4(127246), GIMT_Encode4(0), |
| 45169 | /* 126956 */ /*GILLT_v2s32*//*Label 2443*/ GIMT_Encode4(127306), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45170 | /* 126968 */ /*GILLT_v4s16*//*Label 2444*/ GIMT_Encode4(127344), |
| 45171 | /* 126972 */ /*GILLT_v4s32*//*Label 2445*/ GIMT_Encode4(127382), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45172 | /* 126988 */ /*GILLT_v8s16*//*Label 2446*/ GIMT_Encode4(127481), |
| 45173 | /* 126992 */ // Label 2440: @126992 |
| 45174 | /* 126992 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(127051), // Rule ID 2604 // |
| 45175 | /* 126997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 45176 | /* 127000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45177 | /* 127003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45178 | /* 127007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45179 | /* 127011 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 45180 | /* 127011 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45181 | /* 127014 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45182 | /* 127018 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45183 | /* 127023 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45184 | /* 127027 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45185 | /* 127032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH), |
| 45186 | /* 127035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45187 | /* 127037 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45188 | /* 127040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45189 | /* 127043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45190 | /* 127049 */ GIR_RootConstrainSelectedInstOperands, |
| 45191 | /* 127050 */ // GIR_Coverage, 2604, |
| 45192 | /* 127050 */ GIR_EraseRootFromParent_Done, |
| 45193 | /* 127051 */ // Label 2448: @127051 |
| 45194 | /* 127051 */ GIM_Reject, |
| 45195 | /* 127052 */ // Label 2441: @127052 |
| 45196 | /* 127052 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(127245), |
| 45197 | /* 127057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45198 | /* 127060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45199 | /* 127064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45200 | /* 127068 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(127116), // Rule ID 2600 // |
| 45201 | /* 127073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 45202 | /* 127076 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 45203 | /* 127076 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45204 | /* 127079 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45205 | /* 127083 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45206 | /* 127088 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45207 | /* 127092 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45208 | /* 127097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS), |
| 45209 | /* 127100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45210 | /* 127102 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45211 | /* 127105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45212 | /* 127108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45213 | /* 127114 */ GIR_RootConstrainSelectedInstOperands, |
| 45214 | /* 127115 */ // GIR_Coverage, 2600, |
| 45215 | /* 127115 */ GIR_EraseRootFromParent_Done, |
| 45216 | /* 127116 */ // Label 2450: @127116 |
| 45217 | /* 127116 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(127244), // Rule ID 3086 // |
| 45218 | /* 127121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 45219 | /* 127124 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 45220 | /* 127124 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 45221 | /* 127127 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45222 | /* 127131 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45223 | /* 127136 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45224 | /* 127140 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45225 | /* 127145 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 45226 | /* 127148 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45227 | /* 127152 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45228 | /* 127157 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 45229 | /* 127159 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 45230 | /* 127162 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 45231 | /* 127166 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45232 | /* 127171 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 45233 | /* 127174 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 45234 | /* 127177 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 45235 | /* 127180 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45236 | /* 127185 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45237 | /* 127190 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 45238 | /* 127195 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 45239 | /* 127198 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 45240 | /* 127202 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45241 | /* 127207 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 45242 | /* 127210 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45243 | /* 127213 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45244 | /* 127219 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45245 | /* 127221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45246 | /* 127224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 45247 | /* 127226 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 45248 | /* 127233 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45249 | /* 127238 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45250 | /* 127243 */ // GIR_Coverage, 3086, |
| 45251 | /* 127243 */ GIR_EraseRootFromParent_Done, |
| 45252 | /* 127244 */ // Label 2451: @127244 |
| 45253 | /* 127244 */ GIM_Reject, |
| 45254 | /* 127245 */ // Label 2449: @127245 |
| 45255 | /* 127245 */ GIM_Reject, |
| 45256 | /* 127246 */ // Label 2442: @127246 |
| 45257 | /* 127246 */ GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(127305), // Rule ID 2596 // |
| 45258 | /* 127251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 45259 | /* 127254 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45260 | /* 127257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45261 | /* 127261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45262 | /* 127265 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 45263 | /* 127265 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45264 | /* 127268 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45265 | /* 127272 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45266 | /* 127277 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45267 | /* 127281 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45268 | /* 127286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD), |
| 45269 | /* 127289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 45270 | /* 127291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45271 | /* 127294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45272 | /* 127297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45273 | /* 127303 */ GIR_RootConstrainSelectedInstOperands, |
| 45274 | /* 127304 */ // GIR_Coverage, 2596, |
| 45275 | /* 127304 */ GIR_EraseRootFromParent_Done, |
| 45276 | /* 127305 */ // Label 2452: @127305 |
| 45277 | /* 127305 */ GIM_Reject, |
| 45278 | /* 127306 */ // Label 2443: @127306 |
| 45279 | /* 127306 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(127343), // Rule ID 1767 // |
| 45280 | /* 127311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45281 | /* 127314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45282 | /* 127317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45283 | /* 127321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45284 | /* 127325 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 45285 | /* 127325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 45286 | /* 127328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45287 | /* 127330 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45288 | /* 127332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45289 | /* 127335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45290 | /* 127341 */ GIR_RootConstrainSelectedInstOperands, |
| 45291 | /* 127342 */ // GIR_Coverage, 1767, |
| 45292 | /* 127342 */ GIR_EraseRootFromParent_Done, |
| 45293 | /* 127343 */ // Label 2453: @127343 |
| 45294 | /* 127343 */ GIM_Reject, |
| 45295 | /* 127344 */ // Label 2444: @127344 |
| 45296 | /* 127344 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(127381), // Rule ID 1775 // |
| 45297 | /* 127349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45298 | /* 127352 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45299 | /* 127355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45300 | /* 127359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45301 | /* 127363 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 45302 | /* 127363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd), |
| 45303 | /* 127366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45304 | /* 127368 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45305 | /* 127370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45306 | /* 127373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45307 | /* 127379 */ GIR_RootConstrainSelectedInstOperands, |
| 45308 | /* 127380 */ // GIR_Coverage, 1775, |
| 45309 | /* 127380 */ GIR_EraseRootFromParent_Done, |
| 45310 | /* 127381 */ // Label 2454: @127381 |
| 45311 | /* 127381 */ GIM_Reject, |
| 45312 | /* 127382 */ // Label 2445: @127382 |
| 45313 | /* 127382 */ GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(127480), |
| 45314 | /* 127387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45315 | /* 127390 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(127424), // Rule ID 1771 // |
| 45316 | /* 127395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45317 | /* 127398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45318 | /* 127402 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45319 | /* 127406 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 45320 | /* 127406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq), |
| 45321 | /* 127409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45322 | /* 127411 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45323 | /* 127413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45324 | /* 127416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45325 | /* 127422 */ GIR_RootConstrainSelectedInstOperands, |
| 45326 | /* 127423 */ // GIR_Coverage, 1771, |
| 45327 | /* 127423 */ GIR_EraseRootFromParent_Done, |
| 45328 | /* 127424 */ // Label 2456: @127424 |
| 45329 | /* 127424 */ GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(127479), // Rule ID 4538 // |
| 45330 | /* 127429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45331 | /* 127432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45332 | /* 127436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45333 | /* 127440 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 45334 | /* 127440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45335 | /* 127443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45336 | /* 127447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45337 | /* 127452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 45338 | /* 127455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45339 | /* 127457 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45340 | /* 127459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45341 | /* 127462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45342 | /* 127468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45343 | /* 127474 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45344 | /* 127477 */ GIR_RootConstrainSelectedInstOperands, |
| 45345 | /* 127478 */ // GIR_Coverage, 4538, |
| 45346 | /* 127478 */ GIR_EraseRootFromParent_Done, |
| 45347 | /* 127479 */ // Label 2457: @127479 |
| 45348 | /* 127479 */ GIM_Reject, |
| 45349 | /* 127480 */ // Label 2455: @127480 |
| 45350 | /* 127480 */ GIM_Reject, |
| 45351 | /* 127481 */ // Label 2446: @127481 |
| 45352 | /* 127481 */ GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(127579), |
| 45353 | /* 127486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45354 | /* 127489 */ GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(127523), // Rule ID 1779 // |
| 45355 | /* 127494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45356 | /* 127497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45357 | /* 127501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45358 | /* 127505 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 45359 | /* 127505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq), |
| 45360 | /* 127508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45361 | /* 127510 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45362 | /* 127512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45363 | /* 127515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45364 | /* 127521 */ GIR_RootConstrainSelectedInstOperands, |
| 45365 | /* 127522 */ // GIR_Coverage, 1779, |
| 45366 | /* 127522 */ GIR_EraseRootFromParent_Done, |
| 45367 | /* 127523 */ // Label 2459: @127523 |
| 45368 | /* 127523 */ GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(127578), // Rule ID 4532 // |
| 45369 | /* 127528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45370 | /* 127531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45371 | /* 127535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45372 | /* 127539 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 45373 | /* 127539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45374 | /* 127542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45375 | /* 127546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45376 | /* 127551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 45377 | /* 127554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45378 | /* 127556 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45379 | /* 127558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45380 | /* 127561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45381 | /* 127567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45382 | /* 127573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45383 | /* 127576 */ GIR_RootConstrainSelectedInstOperands, |
| 45384 | /* 127577 */ // GIR_Coverage, 4532, |
| 45385 | /* 127577 */ GIR_EraseRootFromParent_Done, |
| 45386 | /* 127578 */ // Label 2460: @127578 |
| 45387 | /* 127578 */ GIM_Reject, |
| 45388 | /* 127579 */ // Label 2458: @127579 |
| 45389 | /* 127579 */ GIM_Reject, |
| 45390 | /* 127580 */ // Label 2447: @127580 |
| 45391 | /* 127580 */ GIM_Reject, |
| 45392 | /* 127581 */ // Label 51: @127581 |
| 45393 | /* 127581 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2468*/ GIMT_Encode4(128232), |
| 45394 | /* 127592 */ /*GILLT_s16*//*Label 2461*/ GIMT_Encode4(127644), |
| 45395 | /* 127596 */ /*GILLT_s32*//*Label 2462*/ GIMT_Encode4(127704), |
| 45396 | /* 127600 */ /*GILLT_s64*//*Label 2463*/ GIMT_Encode4(127898), GIMT_Encode4(0), |
| 45397 | /* 127608 */ /*GILLT_v2s32*//*Label 2464*/ GIMT_Encode4(127958), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45398 | /* 127620 */ /*GILLT_v4s16*//*Label 2465*/ GIMT_Encode4(127996), |
| 45399 | /* 127624 */ /*GILLT_v4s32*//*Label 2466*/ GIMT_Encode4(128034), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45400 | /* 127640 */ /*GILLT_v8s16*//*Label 2467*/ GIMT_Encode4(128133), |
| 45401 | /* 127644 */ // Label 2461: @127644 |
| 45402 | /* 127644 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(127703), // Rule ID 2614 // |
| 45403 | /* 127649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 45404 | /* 127652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45405 | /* 127655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45406 | /* 127659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45407 | /* 127663 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 45408 | /* 127663 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45409 | /* 127666 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45410 | /* 127670 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45411 | /* 127675 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45412 | /* 127679 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45413 | /* 127684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH), |
| 45414 | /* 127687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45415 | /* 127689 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45416 | /* 127692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45417 | /* 127695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45418 | /* 127701 */ GIR_RootConstrainSelectedInstOperands, |
| 45419 | /* 127702 */ // GIR_Coverage, 2614, |
| 45420 | /* 127702 */ GIR_EraseRootFromParent_Done, |
| 45421 | /* 127703 */ // Label 2469: @127703 |
| 45422 | /* 127703 */ GIM_Reject, |
| 45423 | /* 127704 */ // Label 2462: @127704 |
| 45424 | /* 127704 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(127897), |
| 45425 | /* 127709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45426 | /* 127712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45427 | /* 127716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45428 | /* 127720 */ GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(127768), // Rule ID 2610 // |
| 45429 | /* 127725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 45430 | /* 127728 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 45431 | /* 127728 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45432 | /* 127731 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45433 | /* 127735 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45434 | /* 127740 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45435 | /* 127744 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45436 | /* 127749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS), |
| 45437 | /* 127752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45438 | /* 127754 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45439 | /* 127757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45440 | /* 127760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45441 | /* 127766 */ GIR_RootConstrainSelectedInstOperands, |
| 45442 | /* 127767 */ // GIR_Coverage, 2610, |
| 45443 | /* 127767 */ GIR_EraseRootFromParent_Done, |
| 45444 | /* 127768 */ // Label 2471: @127768 |
| 45445 | /* 127768 */ GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(127896), // Rule ID 3087 // |
| 45446 | /* 127773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 45447 | /* 127776 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 45448 | /* 127776 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 45449 | /* 127779 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45450 | /* 127783 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45451 | /* 127788 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45452 | /* 127792 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45453 | /* 127797 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 45454 | /* 127800 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45455 | /* 127804 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45456 | /* 127809 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 45457 | /* 127811 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 45458 | /* 127814 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 45459 | /* 127818 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45460 | /* 127823 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 45461 | /* 127826 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 45462 | /* 127829 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 45463 | /* 127832 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45464 | /* 127837 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45465 | /* 127842 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 45466 | /* 127847 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 45467 | /* 127850 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 45468 | /* 127854 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45469 | /* 127859 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 45470 | /* 127862 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45471 | /* 127865 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45472 | /* 127871 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45473 | /* 127873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45474 | /* 127876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 45475 | /* 127878 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 45476 | /* 127885 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45477 | /* 127890 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45478 | /* 127895 */ // GIR_Coverage, 3087, |
| 45479 | /* 127895 */ GIR_EraseRootFromParent_Done, |
| 45480 | /* 127896 */ // Label 2472: @127896 |
| 45481 | /* 127896 */ GIM_Reject, |
| 45482 | /* 127897 */ // Label 2470: @127897 |
| 45483 | /* 127897 */ GIM_Reject, |
| 45484 | /* 127898 */ // Label 2463: @127898 |
| 45485 | /* 127898 */ GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(127957), // Rule ID 2606 // |
| 45486 | /* 127903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 45487 | /* 127906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45488 | /* 127909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45489 | /* 127913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45490 | /* 127917 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 45491 | /* 127917 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45492 | /* 127920 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45493 | /* 127924 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45494 | /* 127929 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45495 | /* 127933 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45496 | /* 127938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD), |
| 45497 | /* 127941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 45498 | /* 127943 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45499 | /* 127946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45500 | /* 127949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45501 | /* 127955 */ GIR_RootConstrainSelectedInstOperands, |
| 45502 | /* 127956 */ // GIR_Coverage, 2606, |
| 45503 | /* 127956 */ GIR_EraseRootFromParent_Done, |
| 45504 | /* 127957 */ // Label 2473: @127957 |
| 45505 | /* 127957 */ GIM_Reject, |
| 45506 | /* 127958 */ // Label 2464: @127958 |
| 45507 | /* 127958 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(127995), // Rule ID 1768 // |
| 45508 | /* 127963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45509 | /* 127966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45510 | /* 127969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45511 | /* 127973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45512 | /* 127977 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 45513 | /* 127977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 45514 | /* 127980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45515 | /* 127982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45516 | /* 127984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45517 | /* 127987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45518 | /* 127993 */ GIR_RootConstrainSelectedInstOperands, |
| 45519 | /* 127994 */ // GIR_Coverage, 1768, |
| 45520 | /* 127994 */ GIR_EraseRootFromParent_Done, |
| 45521 | /* 127995 */ // Label 2474: @127995 |
| 45522 | /* 127995 */ GIM_Reject, |
| 45523 | /* 127996 */ // Label 2465: @127996 |
| 45524 | /* 127996 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(128033), // Rule ID 1776 // |
| 45525 | /* 128001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45526 | /* 128004 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45527 | /* 128007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45528 | /* 128011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45529 | /* 128015 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 45530 | /* 128015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd), |
| 45531 | /* 128018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45532 | /* 128020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45533 | /* 128022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45534 | /* 128025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45535 | /* 128031 */ GIR_RootConstrainSelectedInstOperands, |
| 45536 | /* 128032 */ // GIR_Coverage, 1776, |
| 45537 | /* 128032 */ GIR_EraseRootFromParent_Done, |
| 45538 | /* 128033 */ // Label 2475: @128033 |
| 45539 | /* 128033 */ GIM_Reject, |
| 45540 | /* 128034 */ // Label 2466: @128034 |
| 45541 | /* 128034 */ GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(128132), |
| 45542 | /* 128039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45543 | /* 128042 */ GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(128076), // Rule ID 1772 // |
| 45544 | /* 128047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45545 | /* 128050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45546 | /* 128054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45547 | /* 128058 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 45548 | /* 128058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq), |
| 45549 | /* 128061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45550 | /* 128063 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45551 | /* 128065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45552 | /* 128068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45553 | /* 128074 */ GIR_RootConstrainSelectedInstOperands, |
| 45554 | /* 128075 */ // GIR_Coverage, 1772, |
| 45555 | /* 128075 */ GIR_EraseRootFromParent_Done, |
| 45556 | /* 128076 */ // Label 2477: @128076 |
| 45557 | /* 128076 */ GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(128131), // Rule ID 4541 // |
| 45558 | /* 128081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45559 | /* 128084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45560 | /* 128088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45561 | /* 128092 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 45562 | /* 128092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45563 | /* 128095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45564 | /* 128099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45565 | /* 128104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 45566 | /* 128107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45567 | /* 128109 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45568 | /* 128111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45569 | /* 128114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45570 | /* 128120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45571 | /* 128126 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45572 | /* 128129 */ GIR_RootConstrainSelectedInstOperands, |
| 45573 | /* 128130 */ // GIR_Coverage, 4541, |
| 45574 | /* 128130 */ GIR_EraseRootFromParent_Done, |
| 45575 | /* 128131 */ // Label 2478: @128131 |
| 45576 | /* 128131 */ GIM_Reject, |
| 45577 | /* 128132 */ // Label 2476: @128132 |
| 45578 | /* 128132 */ GIM_Reject, |
| 45579 | /* 128133 */ // Label 2467: @128133 |
| 45580 | /* 128133 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(128231), |
| 45581 | /* 128138 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45582 | /* 128141 */ GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(128175), // Rule ID 1780 // |
| 45583 | /* 128146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45584 | /* 128149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45585 | /* 128153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45586 | /* 128157 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 45587 | /* 128157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq), |
| 45588 | /* 128160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45589 | /* 128162 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45590 | /* 128164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45591 | /* 128167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45592 | /* 128173 */ GIR_RootConstrainSelectedInstOperands, |
| 45593 | /* 128174 */ // GIR_Coverage, 1780, |
| 45594 | /* 128174 */ GIR_EraseRootFromParent_Done, |
| 45595 | /* 128175 */ // Label 2480: @128175 |
| 45596 | /* 128175 */ GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(128230), // Rule ID 4535 // |
| 45597 | /* 128180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45598 | /* 128183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45599 | /* 128187 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45600 | /* 128191 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 45601 | /* 128191 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45602 | /* 128194 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45603 | /* 128198 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45604 | /* 128203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 45605 | /* 128206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45606 | /* 128208 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45607 | /* 128210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45608 | /* 128213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45609 | /* 128219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45610 | /* 128225 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45611 | /* 128228 */ GIR_RootConstrainSelectedInstOperands, |
| 45612 | /* 128229 */ // GIR_Coverage, 4535, |
| 45613 | /* 128229 */ GIR_EraseRootFromParent_Done, |
| 45614 | /* 128230 */ // Label 2481: @128230 |
| 45615 | /* 128230 */ GIM_Reject, |
| 45616 | /* 128231 */ // Label 2479: @128231 |
| 45617 | /* 128231 */ GIM_Reject, |
| 45618 | /* 128232 */ // Label 2468: @128232 |
| 45619 | /* 128232 */ GIM_Reject, |
| 45620 | /* 128233 */ // Label 52: @128233 |
| 45621 | /* 128233 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2489*/ GIMT_Encode4(129008), |
| 45622 | /* 128244 */ /*GILLT_s16*//*Label 2482*/ GIMT_Encode4(128296), |
| 45623 | /* 128248 */ /*GILLT_s32*//*Label 2483*/ GIMT_Encode4(128334), |
| 45624 | /* 128252 */ /*GILLT_s64*//*Label 2484*/ GIMT_Encode4(128526), GIMT_Encode4(0), |
| 45625 | /* 128260 */ /*GILLT_v2s32*//*Label 2485*/ GIMT_Encode4(128564), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45626 | /* 128272 */ /*GILLT_v4s16*//*Label 2486*/ GIMT_Encode4(128602), |
| 45627 | /* 128276 */ /*GILLT_v4s32*//*Label 2487*/ GIMT_Encode4(128640), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45628 | /* 128292 */ /*GILLT_v8s16*//*Label 2488*/ GIMT_Encode4(128824), |
| 45629 | /* 128296 */ // Label 2482: @128296 |
| 45630 | /* 128296 */ GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(128333), // Rule ID 677 // |
| 45631 | /* 128301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 45632 | /* 128304 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45633 | /* 128307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45634 | /* 128311 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45635 | /* 128315 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45636 | /* 128315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH), |
| 45637 | /* 128318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45638 | /* 128320 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45639 | /* 128322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45640 | /* 128325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45641 | /* 128331 */ GIR_RootConstrainSelectedInstOperands, |
| 45642 | /* 128332 */ // GIR_Coverage, 677, |
| 45643 | /* 128332 */ GIR_EraseRootFromParent_Done, |
| 45644 | /* 128333 */ // Label 2490: @128333 |
| 45645 | /* 128333 */ GIM_Reject, |
| 45646 | /* 128334 */ // Label 2483: @128334 |
| 45647 | /* 128334 */ GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(128525), |
| 45648 | /* 128339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45649 | /* 128342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45650 | /* 128346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45651 | /* 128350 */ GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(128376), // Rule ID 676 // |
| 45652 | /* 128355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 45653 | /* 128358 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45654 | /* 128358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS), |
| 45655 | /* 128361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45656 | /* 128363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45657 | /* 128365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45658 | /* 128368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45659 | /* 128374 */ GIR_RootConstrainSelectedInstOperands, |
| 45660 | /* 128375 */ // GIR_Coverage, 676, |
| 45661 | /* 128375 */ GIR_EraseRootFromParent_Done, |
| 45662 | /* 128376 */ // Label 2492: @128376 |
| 45663 | /* 128376 */ GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(128524), // Rule ID 3078 // |
| 45664 | /* 128381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 45665 | /* 128384 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 45666 | /* 128384 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 45667 | /* 128387 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45668 | /* 128391 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45669 | /* 128396 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 45670 | /* 128398 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 45671 | /* 128401 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45672 | /* 128405 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45673 | /* 128410 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 45674 | /* 128413 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45675 | /* 128418 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 45676 | /* 128421 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 45677 | /* 128425 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45678 | /* 128430 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 45679 | /* 128433 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 45680 | /* 128437 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 45681 | /* 128440 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45682 | /* 128445 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45683 | /* 128450 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 45684 | /* 128455 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 45685 | /* 128458 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 45686 | /* 128462 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45687 | /* 128467 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 45688 | /* 128470 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 45689 | /* 128473 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45690 | /* 128479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 45691 | /* 128481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 45692 | /* 128484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45693 | /* 128488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45694 | /* 128493 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 45695 | /* 128496 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45696 | /* 128501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 45697 | /* 128504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 45698 | /* 128506 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 45699 | /* 128513 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 45700 | /* 128518 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 45701 | /* 128523 */ // GIR_Coverage, 3078, |
| 45702 | /* 128523 */ GIR_EraseRootFromParent_Done, |
| 45703 | /* 128524 */ // Label 2493: @128524 |
| 45704 | /* 128524 */ GIM_Reject, |
| 45705 | /* 128525 */ // Label 2491: @128525 |
| 45706 | /* 128525 */ GIM_Reject, |
| 45707 | /* 128526 */ // Label 2484: @128526 |
| 45708 | /* 128526 */ GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(128563), // Rule ID 675 // |
| 45709 | /* 128531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 45710 | /* 128534 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45711 | /* 128537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45712 | /* 128541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45713 | /* 128545 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45714 | /* 128545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD), |
| 45715 | /* 128548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 45716 | /* 128550 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 45717 | /* 128552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45718 | /* 128555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45719 | /* 128561 */ GIR_RootConstrainSelectedInstOperands, |
| 45720 | /* 128562 */ // GIR_Coverage, 675, |
| 45721 | /* 128562 */ GIR_EraseRootFromParent_Done, |
| 45722 | /* 128563 */ // Label 2494: @128563 |
| 45723 | /* 128563 */ GIM_Reject, |
| 45724 | /* 128564 */ // Label 2485: @128564 |
| 45725 | /* 128564 */ GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(128601), // Rule ID 1675 // |
| 45726 | /* 128569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45727 | /* 128572 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45728 | /* 128575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45729 | /* 128579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45730 | /* 128583 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 45731 | /* 128583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 45732 | /* 128586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45733 | /* 128588 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45734 | /* 128590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45735 | /* 128593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45736 | /* 128599 */ GIR_RootConstrainSelectedInstOperands, |
| 45737 | /* 128600 */ // GIR_Coverage, 1675, |
| 45738 | /* 128600 */ GIR_EraseRootFromParent_Done, |
| 45739 | /* 128601 */ // Label 2495: @128601 |
| 45740 | /* 128601 */ GIM_Reject, |
| 45741 | /* 128602 */ // Label 2486: @128602 |
| 45742 | /* 128602 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(128639), // Rule ID 1677 // |
| 45743 | /* 128607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45744 | /* 128610 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45745 | /* 128613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45746 | /* 128617 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45747 | /* 128621 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 45748 | /* 128621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd), |
| 45749 | /* 128624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45750 | /* 128626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45751 | /* 128628 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45752 | /* 128631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45753 | /* 128637 */ GIR_RootConstrainSelectedInstOperands, |
| 45754 | /* 128638 */ // GIR_Coverage, 1677, |
| 45755 | /* 128638 */ GIR_EraseRootFromParent_Done, |
| 45756 | /* 128639 */ // Label 2496: @128639 |
| 45757 | /* 128639 */ GIM_Reject, |
| 45758 | /* 128640 */ // Label 2487: @128640 |
| 45759 | /* 128640 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(128823), |
| 45760 | /* 128645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45761 | /* 128648 */ GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(128733), // Rule ID 4471 // |
| 45762 | /* 128653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45763 | /* 128656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45764 | /* 128660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 45765 | /* 128664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 45766 | /* 128668 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45767 | /* 128672 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45768 | /* 128676 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45769 | /* 128681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45770 | /* 128686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45771 | /* 128688 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 45772 | /* 128688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45773 | /* 128691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45774 | /* 128695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45775 | /* 128700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 45776 | /* 128703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45777 | /* 128705 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 45778 | /* 128709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 45779 | /* 128713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45780 | /* 128716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45781 | /* 128722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45782 | /* 128728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45783 | /* 128731 */ GIR_RootConstrainSelectedInstOperands, |
| 45784 | /* 128732 */ // GIR_Coverage, 4471, |
| 45785 | /* 128732 */ GIR_EraseRootFromParent_Done, |
| 45786 | /* 128733 */ // Label 2498: @128733 |
| 45787 | /* 128733 */ GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(128767), // Rule ID 1676 // |
| 45788 | /* 128738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45789 | /* 128741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45790 | /* 128745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45791 | /* 128749 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 45792 | /* 128749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq), |
| 45793 | /* 128752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45794 | /* 128754 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45795 | /* 128756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45796 | /* 128759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45797 | /* 128765 */ GIR_RootConstrainSelectedInstOperands, |
| 45798 | /* 128766 */ // GIR_Coverage, 1676, |
| 45799 | /* 128766 */ GIR_EraseRootFromParent_Done, |
| 45800 | /* 128767 */ // Label 2499: @128767 |
| 45801 | /* 128767 */ GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(128822), // Rule ID 4550 // |
| 45802 | /* 128772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45803 | /* 128775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45804 | /* 128779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45805 | /* 128783 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 45806 | /* 128783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45807 | /* 128786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45808 | /* 128790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45809 | /* 128795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32), |
| 45810 | /* 128798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45811 | /* 128800 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 45812 | /* 128802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45813 | /* 128805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45814 | /* 128811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45815 | /* 128817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45816 | /* 128820 */ GIR_RootConstrainSelectedInstOperands, |
| 45817 | /* 128821 */ // GIR_Coverage, 4550, |
| 45818 | /* 128821 */ GIR_EraseRootFromParent_Done, |
| 45819 | /* 128822 */ // Label 2500: @128822 |
| 45820 | /* 128822 */ GIM_Reject, |
| 45821 | /* 128823 */ // Label 2497: @128823 |
| 45822 | /* 128823 */ GIM_Reject, |
| 45823 | /* 128824 */ // Label 2488: @128824 |
| 45824 | /* 128824 */ GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(129007), |
| 45825 | /* 128829 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45826 | /* 128832 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(128917), // Rule ID 4470 // |
| 45827 | /* 128837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45828 | /* 128840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45829 | /* 128844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 45830 | /* 128848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 45831 | /* 128852 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45832 | /* 128856 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45833 | /* 128860 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45834 | /* 128865 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45835 | /* 128870 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45836 | /* 128872 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 45837 | /* 128872 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45838 | /* 128875 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45839 | /* 128879 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45840 | /* 128884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 45841 | /* 128887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45842 | /* 128889 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 45843 | /* 128893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 45844 | /* 128897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45845 | /* 128900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45846 | /* 128906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45847 | /* 128912 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45848 | /* 128915 */ GIR_RootConstrainSelectedInstOperands, |
| 45849 | /* 128916 */ // GIR_Coverage, 4470, |
| 45850 | /* 128916 */ GIR_EraseRootFromParent_Done, |
| 45851 | /* 128917 */ // Label 2502: @128917 |
| 45852 | /* 128917 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(128951), // Rule ID 1678 // |
| 45853 | /* 128922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 45854 | /* 128925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45855 | /* 128929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45856 | /* 128933 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 45857 | /* 128933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq), |
| 45858 | /* 128936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45859 | /* 128938 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45860 | /* 128940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45861 | /* 128943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45862 | /* 128949 */ GIR_RootConstrainSelectedInstOperands, |
| 45863 | /* 128950 */ // GIR_Coverage, 1678, |
| 45864 | /* 128950 */ GIR_EraseRootFromParent_Done, |
| 45865 | /* 128951 */ // Label 2503: @128951 |
| 45866 | /* 128951 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(129006), // Rule ID 4548 // |
| 45867 | /* 128956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45868 | /* 128959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45869 | /* 128963 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45870 | /* 128967 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 45871 | /* 128967 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45872 | /* 128970 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45873 | /* 128974 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45874 | /* 128979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16), |
| 45875 | /* 128982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45876 | /* 128984 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 45877 | /* 128986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45878 | /* 128989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45879 | /* 128995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45880 | /* 129001 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45881 | /* 129004 */ GIR_RootConstrainSelectedInstOperands, |
| 45882 | /* 129005 */ // GIR_Coverage, 4548, |
| 45883 | /* 129005 */ GIR_EraseRootFromParent_Done, |
| 45884 | /* 129006 */ // Label 2504: @129006 |
| 45885 | /* 129006 */ GIM_Reject, |
| 45886 | /* 129007 */ // Label 2501: @129007 |
| 45887 | /* 129007 */ GIM_Reject, |
| 45888 | /* 129008 */ // Label 2489: @129008 |
| 45889 | /* 129008 */ GIM_Reject, |
| 45890 | /* 129009 */ // Label 53: @129009 |
| 45891 | /* 129009 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2512*/ GIMT_Encode4(129600), |
| 45892 | /* 129020 */ /*GILLT_s16*//*Label 2505*/ GIMT_Encode4(129072), |
| 45893 | /* 129024 */ /*GILLT_s32*//*Label 2506*/ GIMT_Encode4(129106), |
| 45894 | /* 129028 */ /*GILLT_s64*//*Label 2507*/ GIMT_Encode4(129140), GIMT_Encode4(0), |
| 45895 | /* 129036 */ /*GILLT_v2s32*//*Label 2508*/ GIMT_Encode4(129174), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45896 | /* 129048 */ /*GILLT_v4s16*//*Label 2509*/ GIMT_Encode4(129208), |
| 45897 | /* 129052 */ /*GILLT_v4s32*//*Label 2510*/ GIMT_Encode4(129242), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45898 | /* 129068 */ /*GILLT_v8s16*//*Label 2511*/ GIMT_Encode4(129421), |
| 45899 | /* 129072 */ // Label 2505: @129072 |
| 45900 | /* 129072 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(129105), // Rule ID 664 // |
| 45901 | /* 129077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 45902 | /* 129080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45903 | /* 129083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 45904 | /* 129086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45905 | /* 129090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45906 | /* 129094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45907 | /* 129098 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 45908 | /* 129098 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH), |
| 45909 | /* 129103 */ GIR_RootConstrainSelectedInstOperands, |
| 45910 | /* 129104 */ // GIR_Coverage, 664, |
| 45911 | /* 129104 */ GIR_Done, |
| 45912 | /* 129105 */ // Label 2513: @129105 |
| 45913 | /* 129105 */ GIM_Reject, |
| 45914 | /* 129106 */ // Label 2506: @129106 |
| 45915 | /* 129106 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(129139), // Rule ID 666 // |
| 45916 | /* 129111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 45917 | /* 129114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45918 | /* 129117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45919 | /* 129120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45920 | /* 129124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45921 | /* 129128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45922 | /* 129132 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 45923 | /* 129132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS), |
| 45924 | /* 129137 */ GIR_RootConstrainSelectedInstOperands, |
| 45925 | /* 129138 */ // GIR_Coverage, 666, |
| 45926 | /* 129138 */ GIR_Done, |
| 45927 | /* 129139 */ // Label 2514: @129139 |
| 45928 | /* 129139 */ GIM_Reject, |
| 45929 | /* 129140 */ // Label 2507: @129140 |
| 45930 | /* 129140 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(129173), // Rule ID 668 // |
| 45931 | /* 129145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 45932 | /* 129148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45933 | /* 129151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 45934 | /* 129154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45935 | /* 129158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45936 | /* 129162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45937 | /* 129166 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 45938 | /* 129166 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD), |
| 45939 | /* 129171 */ GIR_RootConstrainSelectedInstOperands, |
| 45940 | /* 129172 */ // GIR_Coverage, 668, |
| 45941 | /* 129172 */ GIR_Done, |
| 45942 | /* 129173 */ // Label 2515: @129173 |
| 45943 | /* 129173 */ GIM_Reject, |
| 45944 | /* 129174 */ // Label 2508: @129174 |
| 45945 | /* 129174 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(129207), // Rule ID 1394 // |
| 45946 | /* 129179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 45947 | /* 129182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45948 | /* 129185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45949 | /* 129188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45950 | /* 129192 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45951 | /* 129196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45952 | /* 129200 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 45953 | /* 129200 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf), |
| 45954 | /* 129205 */ GIR_RootConstrainSelectedInstOperands, |
| 45955 | /* 129206 */ // GIR_Coverage, 1394, |
| 45956 | /* 129206 */ GIR_Done, |
| 45957 | /* 129207 */ // Label 2516: @129207 |
| 45958 | /* 129207 */ GIM_Reject, |
| 45959 | /* 129208 */ // Label 2509: @129208 |
| 45960 | /* 129208 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(129241), // Rule ID 1396 // |
| 45961 | /* 129213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 45962 | /* 129216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45963 | /* 129219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45964 | /* 129222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45965 | /* 129226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45966 | /* 129230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45967 | /* 129234 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 45968 | /* 129234 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh), |
| 45969 | /* 129239 */ GIR_RootConstrainSelectedInstOperands, |
| 45970 | /* 129240 */ // GIR_Coverage, 1396, |
| 45971 | /* 129240 */ GIR_Done, |
| 45972 | /* 129241 */ // Label 2517: @129241 |
| 45973 | /* 129241 */ GIM_Reject, |
| 45974 | /* 129242 */ // Label 2510: @129242 |
| 45975 | /* 129242 */ GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(129420), |
| 45976 | /* 129247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45977 | /* 129250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45978 | /* 129253 */ GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(129331), // Rule ID 4562 // |
| 45979 | /* 129258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45980 | /* 129261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45981 | /* 129265 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 45982 | /* 129269 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 45983 | /* 129273 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45984 | /* 129277 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45985 | /* 129282 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 45986 | /* 129286 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 45987 | /* 129290 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45988 | /* 129294 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45989 | /* 129299 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 45990 | /* 129301 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 45991 | /* 129301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 45992 | /* 129304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45993 | /* 129306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 45994 | /* 129310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 45995 | /* 129314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45996 | /* 129317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45997 | /* 129323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45998 | /* 129329 */ GIR_RootConstrainSelectedInstOperands, |
| 45999 | /* 129330 */ // GIR_Coverage, 4562, |
| 46000 | /* 129330 */ GIR_EraseRootFromParent_Done, |
| 46001 | /* 129331 */ // Label 2519: @129331 |
| 46002 | /* 129331 */ GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(129358), // Rule ID 1395 // |
| 46003 | /* 129336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 46004 | /* 129339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46005 | /* 129343 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46006 | /* 129347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46007 | /* 129351 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 46008 | /* 129351 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf), |
| 46009 | /* 129356 */ GIR_RootConstrainSelectedInstOperands, |
| 46010 | /* 129357 */ // GIR_Coverage, 1395, |
| 46011 | /* 129357 */ GIR_Done, |
| 46012 | /* 129358 */ // Label 2520: @129358 |
| 46013 | /* 129358 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(129419), // Rule ID 3666 // |
| 46014 | /* 129363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 46015 | /* 129366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46016 | /* 129370 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46017 | /* 129374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46018 | /* 129378 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 46019 | /* 129378 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46020 | /* 129381 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46021 | /* 129385 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46022 | /* 129390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 46023 | /* 129393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46024 | /* 129395 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 46025 | /* 129397 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 46026 | /* 129399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46027 | /* 129402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46028 | /* 129408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46029 | /* 129414 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46030 | /* 129417 */ GIR_RootConstrainSelectedInstOperands, |
| 46031 | /* 129418 */ // GIR_Coverage, 3666, |
| 46032 | /* 129418 */ GIR_EraseRootFromParent_Done, |
| 46033 | /* 129419 */ // Label 2521: @129419 |
| 46034 | /* 129419 */ GIM_Reject, |
| 46035 | /* 129420 */ // Label 2518: @129420 |
| 46036 | /* 129420 */ GIM_Reject, |
| 46037 | /* 129421 */ // Label 2511: @129421 |
| 46038 | /* 129421 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(129599), |
| 46039 | /* 129426 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46040 | /* 129429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46041 | /* 129432 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(129510), // Rule ID 4565 // |
| 46042 | /* 129437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46043 | /* 129440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46044 | /* 129444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46045 | /* 129448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 46046 | /* 129452 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46047 | /* 129456 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46048 | /* 129461 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 46049 | /* 129465 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 46050 | /* 129469 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46051 | /* 129473 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46052 | /* 129478 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46053 | /* 129480 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 46054 | /* 129480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 46055 | /* 129483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46056 | /* 129485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 46057 | /* 129489 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 46058 | /* 129493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46059 | /* 129496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46060 | /* 129502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46061 | /* 129508 */ GIR_RootConstrainSelectedInstOperands, |
| 46062 | /* 129509 */ // GIR_Coverage, 4565, |
| 46063 | /* 129509 */ GIR_EraseRootFromParent_Done, |
| 46064 | /* 129510 */ // Label 2523: @129510 |
| 46065 | /* 129510 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(129537), // Rule ID 1397 // |
| 46066 | /* 129515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 46067 | /* 129518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46068 | /* 129522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46069 | /* 129526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46070 | /* 129530 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 46071 | /* 129530 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh), |
| 46072 | /* 129535 */ GIR_RootConstrainSelectedInstOperands, |
| 46073 | /* 129536 */ // GIR_Coverage, 1397, |
| 46074 | /* 129536 */ GIR_Done, |
| 46075 | /* 129537 */ // Label 2524: @129537 |
| 46076 | /* 129537 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(129598), // Rule ID 3671 // |
| 46077 | /* 129542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 46078 | /* 129545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46079 | /* 129549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46080 | /* 129553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46081 | /* 129557 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 46082 | /* 129557 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46083 | /* 129560 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46084 | /* 129564 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46085 | /* 129569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 46086 | /* 129572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46087 | /* 129574 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 46088 | /* 129576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 46089 | /* 129578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46090 | /* 129581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46091 | /* 129587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46092 | /* 129593 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46093 | /* 129596 */ GIR_RootConstrainSelectedInstOperands, |
| 46094 | /* 129597 */ // GIR_Coverage, 3671, |
| 46095 | /* 129597 */ GIR_EraseRootFromParent_Done, |
| 46096 | /* 129598 */ // Label 2525: @129598 |
| 46097 | /* 129598 */ GIM_Reject, |
| 46098 | /* 129599 */ // Label 2522: @129599 |
| 46099 | /* 129599 */ GIM_Reject, |
| 46100 | /* 129600 */ // Label 2512: @129600 |
| 46101 | /* 129600 */ GIM_Reject, |
| 46102 | /* 129601 */ // Label 54: @129601 |
| 46103 | /* 129601 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2533*/ GIMT_Encode4(130192), |
| 46104 | /* 129612 */ /*GILLT_s16*//*Label 2526*/ GIMT_Encode4(129664), |
| 46105 | /* 129616 */ /*GILLT_s32*//*Label 2527*/ GIMT_Encode4(129698), |
| 46106 | /* 129620 */ /*GILLT_s64*//*Label 2528*/ GIMT_Encode4(129732), GIMT_Encode4(0), |
| 46107 | /* 129628 */ /*GILLT_v2s32*//*Label 2529*/ GIMT_Encode4(129766), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46108 | /* 129640 */ /*GILLT_v4s16*//*Label 2530*/ GIMT_Encode4(129800), |
| 46109 | /* 129644 */ /*GILLT_v4s32*//*Label 2531*/ GIMT_Encode4(129834), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46110 | /* 129660 */ /*GILLT_v8s16*//*Label 2532*/ GIMT_Encode4(130013), |
| 46111 | /* 129664 */ // Label 2526: @129664 |
| 46112 | /* 129664 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(129697), // Rule ID 658 // |
| 46113 | /* 129669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 46114 | /* 129672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46115 | /* 129675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46116 | /* 129678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46117 | /* 129682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46118 | /* 129686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46119 | /* 129690 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46120 | /* 129690 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH), |
| 46121 | /* 129695 */ GIR_RootConstrainSelectedInstOperands, |
| 46122 | /* 129696 */ // GIR_Coverage, 658, |
| 46123 | /* 129696 */ GIR_Done, |
| 46124 | /* 129697 */ // Label 2534: @129697 |
| 46125 | /* 129697 */ GIM_Reject, |
| 46126 | /* 129698 */ // Label 2527: @129698 |
| 46127 | /* 129698 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(129731), // Rule ID 660 // |
| 46128 | /* 129703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 46129 | /* 129706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46130 | /* 129709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46131 | /* 129712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46132 | /* 129716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46133 | /* 129720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46134 | /* 129724 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46135 | /* 129724 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS), |
| 46136 | /* 129729 */ GIR_RootConstrainSelectedInstOperands, |
| 46137 | /* 129730 */ // GIR_Coverage, 660, |
| 46138 | /* 129730 */ GIR_Done, |
| 46139 | /* 129731 */ // Label 2535: @129731 |
| 46140 | /* 129731 */ GIM_Reject, |
| 46141 | /* 129732 */ // Label 2528: @129732 |
| 46142 | /* 129732 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(129765), // Rule ID 662 // |
| 46143 | /* 129737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 46144 | /* 129740 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46145 | /* 129743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46146 | /* 129746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46147 | /* 129750 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46148 | /* 129754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46149 | /* 129758 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46150 | /* 129758 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD), |
| 46151 | /* 129763 */ GIR_RootConstrainSelectedInstOperands, |
| 46152 | /* 129764 */ // GIR_Coverage, 662, |
| 46153 | /* 129764 */ GIR_Done, |
| 46154 | /* 129765 */ // Label 2536: @129765 |
| 46155 | /* 129765 */ GIM_Reject, |
| 46156 | /* 129766 */ // Label 2529: @129766 |
| 46157 | /* 129766 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(129799), // Rule ID 1374 // |
| 46158 | /* 129771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 46159 | /* 129774 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46160 | /* 129777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 46161 | /* 129780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46162 | /* 129784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46163 | /* 129788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46164 | /* 129792 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 46165 | /* 129792 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf), |
| 46166 | /* 129797 */ GIR_RootConstrainSelectedInstOperands, |
| 46167 | /* 129798 */ // GIR_Coverage, 1374, |
| 46168 | /* 129798 */ GIR_Done, |
| 46169 | /* 129799 */ // Label 2537: @129799 |
| 46170 | /* 129799 */ GIM_Reject, |
| 46171 | /* 129800 */ // Label 2530: @129800 |
| 46172 | /* 129800 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(129833), // Rule ID 1376 // |
| 46173 | /* 129805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 46174 | /* 129808 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46175 | /* 129811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 46176 | /* 129814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46177 | /* 129818 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46178 | /* 129822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46179 | /* 129826 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 46180 | /* 129826 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh), |
| 46181 | /* 129831 */ GIR_RootConstrainSelectedInstOperands, |
| 46182 | /* 129832 */ // GIR_Coverage, 1376, |
| 46183 | /* 129832 */ GIR_Done, |
| 46184 | /* 129833 */ // Label 2538: @129833 |
| 46185 | /* 129833 */ GIM_Reject, |
| 46186 | /* 129834 */ // Label 2531: @129834 |
| 46187 | /* 129834 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(130012), |
| 46188 | /* 129839 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46189 | /* 129842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46190 | /* 129845 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(129923), // Rule ID 4556 // |
| 46191 | /* 129850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46192 | /* 129853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46193 | /* 129857 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46194 | /* 129861 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 46195 | /* 129865 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46196 | /* 129869 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46197 | /* 129874 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 46198 | /* 129878 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 46199 | /* 129882 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46200 | /* 129886 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46201 | /* 129891 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46202 | /* 129893 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 46203 | /* 129893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 46204 | /* 129896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46205 | /* 129898 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 46206 | /* 129902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 46207 | /* 129906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46208 | /* 129909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46209 | /* 129915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46210 | /* 129921 */ GIR_RootConstrainSelectedInstOperands, |
| 46211 | /* 129922 */ // GIR_Coverage, 4556, |
| 46212 | /* 129922 */ GIR_EraseRootFromParent_Done, |
| 46213 | /* 129923 */ // Label 2540: @129923 |
| 46214 | /* 129923 */ GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(129950), // Rule ID 1375 // |
| 46215 | /* 129928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 46216 | /* 129931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46217 | /* 129935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46218 | /* 129939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46219 | /* 129943 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 46220 | /* 129943 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf), |
| 46221 | /* 129948 */ GIR_RootConstrainSelectedInstOperands, |
| 46222 | /* 129949 */ // GIR_Coverage, 1375, |
| 46223 | /* 129949 */ GIR_Done, |
| 46224 | /* 129950 */ // Label 2541: @129950 |
| 46225 | /* 129950 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(130011), // Rule ID 3404 // |
| 46226 | /* 129955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 46227 | /* 129958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46228 | /* 129962 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46229 | /* 129966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46230 | /* 129970 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 46231 | /* 129970 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46232 | /* 129973 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46233 | /* 129977 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46234 | /* 129982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 46235 | /* 129985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46236 | /* 129987 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 46237 | /* 129989 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 46238 | /* 129991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46239 | /* 129994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46240 | /* 130000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46241 | /* 130006 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46242 | /* 130009 */ GIR_RootConstrainSelectedInstOperands, |
| 46243 | /* 130010 */ // GIR_Coverage, 3404, |
| 46244 | /* 130010 */ GIR_EraseRootFromParent_Done, |
| 46245 | /* 130011 */ // Label 2542: @130011 |
| 46246 | /* 130011 */ GIM_Reject, |
| 46247 | /* 130012 */ // Label 2539: @130012 |
| 46248 | /* 130012 */ GIM_Reject, |
| 46249 | /* 130013 */ // Label 2532: @130013 |
| 46250 | /* 130013 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(130191), |
| 46251 | /* 130018 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46252 | /* 130021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46253 | /* 130024 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(130102), // Rule ID 4559 // |
| 46254 | /* 130029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46255 | /* 130032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46256 | /* 130036 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46257 | /* 130040 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 46258 | /* 130044 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46259 | /* 130048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46260 | /* 130053 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 46261 | /* 130057 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 46262 | /* 130061 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46263 | /* 130065 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46264 | /* 130070 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46265 | /* 130072 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 46266 | /* 130072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 46267 | /* 130075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46268 | /* 130077 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 46269 | /* 130081 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 46270 | /* 130085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46271 | /* 130088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46272 | /* 130094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46273 | /* 130100 */ GIR_RootConstrainSelectedInstOperands, |
| 46274 | /* 130101 */ // GIR_Coverage, 4559, |
| 46275 | /* 130101 */ GIR_EraseRootFromParent_Done, |
| 46276 | /* 130102 */ // Label 2544: @130102 |
| 46277 | /* 130102 */ GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(130129), // Rule ID 1377 // |
| 46278 | /* 130107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 46279 | /* 130110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46280 | /* 130114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46281 | /* 130118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46282 | /* 130122 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 46283 | /* 130122 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh), |
| 46284 | /* 130127 */ GIR_RootConstrainSelectedInstOperands, |
| 46285 | /* 130128 */ // GIR_Coverage, 1377, |
| 46286 | /* 130128 */ GIR_Done, |
| 46287 | /* 130129 */ // Label 2545: @130129 |
| 46288 | /* 130129 */ GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(130190), // Rule ID 3661 // |
| 46289 | /* 130134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 46290 | /* 130137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46291 | /* 130141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46292 | /* 130145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46293 | /* 130149 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 46294 | /* 130149 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46295 | /* 130152 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46296 | /* 130156 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46297 | /* 130161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 46298 | /* 130164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46299 | /* 130166 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 46300 | /* 130168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 46301 | /* 130170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46302 | /* 130173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46303 | /* 130179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46304 | /* 130185 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46305 | /* 130188 */ GIR_RootConstrainSelectedInstOperands, |
| 46306 | /* 130189 */ // GIR_Coverage, 3661, |
| 46307 | /* 130189 */ GIR_EraseRootFromParent_Done, |
| 46308 | /* 130190 */ // Label 2546: @130190 |
| 46309 | /* 130190 */ GIM_Reject, |
| 46310 | /* 130191 */ // Label 2543: @130191 |
| 46311 | /* 130191 */ GIM_Reject, |
| 46312 | /* 130192 */ // Label 2533: @130192 |
| 46313 | /* 130192 */ GIM_Reject, |
| 46314 | /* 130193 */ // Label 55: @130193 |
| 46315 | /* 130193 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2553*/ GIMT_Encode4(130926), |
| 46316 | /* 130204 */ /*GILLT_s16*//*Label 2547*/ GIMT_Encode4(130256), |
| 46317 | /* 130208 */ /*GILLT_s32*//*Label 2548*/ GIMT_Encode4(130497), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46318 | /* 130220 */ /*GILLT_v2s32*//*Label 2549*/ GIMT_Encode4(130738), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46319 | /* 130232 */ /*GILLT_v4s16*//*Label 2550*/ GIMT_Encode4(130785), |
| 46320 | /* 130236 */ /*GILLT_v4s32*//*Label 2551*/ GIMT_Encode4(130832), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46321 | /* 130252 */ /*GILLT_v8s16*//*Label 2552*/ GIMT_Encode4(130879), |
| 46322 | /* 130256 */ // Label 2547: @130256 |
| 46323 | /* 130256 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(130496), // Rule ID 3081 // |
| 46324 | /* 130261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 46325 | /* 130264 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46326 | /* 130267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46327 | /* 130270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46328 | /* 130274 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46329 | /* 130278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46330 | /* 130282 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 46331 | /* 130282 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 46332 | /* 130285 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46333 | /* 130289 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46334 | /* 130294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 46335 | /* 130296 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 46336 | /* 130299 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46337 | /* 130303 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46338 | /* 130308 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 46339 | /* 130311 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46340 | /* 130316 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 46341 | /* 130319 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46342 | /* 130323 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46343 | /* 130328 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 46344 | /* 130331 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 46345 | /* 130335 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 46346 | /* 130338 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46347 | /* 130343 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46348 | /* 130348 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 46349 | /* 130353 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 46350 | /* 130356 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46351 | /* 130360 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46352 | /* 130365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 46353 | /* 130367 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 46354 | /* 130370 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46355 | /* 130374 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46356 | /* 130379 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 46357 | /* 130382 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46358 | /* 130387 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 46359 | /* 130390 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46360 | /* 130394 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46361 | /* 130399 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 46362 | /* 130402 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 46363 | /* 130406 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 46364 | /* 130409 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46365 | /* 130414 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46366 | /* 130419 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 46367 | /* 130424 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 46368 | /* 130427 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 46369 | /* 130431 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46370 | /* 130436 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 46371 | /* 130439 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 46372 | /* 130442 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 46373 | /* 130445 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46374 | /* 130451 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 46375 | /* 130453 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 46376 | /* 130456 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46377 | /* 130460 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46378 | /* 130465 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 46379 | /* 130468 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46380 | /* 130473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46381 | /* 130476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 46382 | /* 130478 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 46383 | /* 130485 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 46384 | /* 130490 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46385 | /* 130495 */ // GIR_Coverage, 3081, |
| 46386 | /* 130495 */ GIR_EraseRootFromParent_Done, |
| 46387 | /* 130496 */ // Label 2554: @130496 |
| 46388 | /* 130496 */ GIM_Reject, |
| 46389 | /* 130497 */ // Label 2548: @130497 |
| 46390 | /* 130497 */ GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(130737), // Rule ID 3083 // |
| 46391 | /* 130502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46392 | /* 130505 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46393 | /* 130508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46394 | /* 130511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46395 | /* 130515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46396 | /* 130519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46397 | /* 130523 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 46398 | /* 130523 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 46399 | /* 130526 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46400 | /* 130530 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46401 | /* 130535 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 46402 | /* 130537 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 46403 | /* 130540 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46404 | /* 130544 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46405 | /* 130549 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 46406 | /* 130552 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46407 | /* 130557 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 46408 | /* 130560 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46409 | /* 130564 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46410 | /* 130569 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 46411 | /* 130572 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 46412 | /* 130576 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 46413 | /* 130579 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46414 | /* 130584 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46415 | /* 130589 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 46416 | /* 130594 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 46417 | /* 130597 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46418 | /* 130601 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46419 | /* 130606 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 46420 | /* 130608 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 46421 | /* 130611 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46422 | /* 130615 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46423 | /* 130620 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 46424 | /* 130623 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46425 | /* 130628 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 46426 | /* 130631 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46427 | /* 130635 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46428 | /* 130640 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 46429 | /* 130643 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 46430 | /* 130647 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 46431 | /* 130650 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46432 | /* 130655 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46433 | /* 130660 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 46434 | /* 130665 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 46435 | /* 130668 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 46436 | /* 130672 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46437 | /* 130677 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 46438 | /* 130680 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 46439 | /* 130683 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 46440 | /* 130686 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46441 | /* 130692 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 46442 | /* 130694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 46443 | /* 130697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46444 | /* 130701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46445 | /* 130706 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 46446 | /* 130709 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46447 | /* 130714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46448 | /* 130717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 46449 | /* 130719 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 46450 | /* 130726 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 46451 | /* 130731 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46452 | /* 130736 */ // GIR_Coverage, 3083, |
| 46453 | /* 130736 */ GIR_EraseRootFromParent_Done, |
| 46454 | /* 130737 */ // Label 2555: @130737 |
| 46455 | /* 130737 */ GIM_Reject, |
| 46456 | /* 130738 */ // Label 2549: @130738 |
| 46457 | /* 130738 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(130784), // Rule ID 1390 // |
| 46458 | /* 130743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46459 | /* 130746 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46460 | /* 130749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 46461 | /* 130752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46462 | /* 130756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46463 | /* 130760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46464 | /* 130764 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 46465 | /* 130764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 46466 | /* 130767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46467 | /* 130769 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46468 | /* 130771 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46469 | /* 130773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46470 | /* 130776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46471 | /* 130782 */ GIR_RootConstrainSelectedInstOperands, |
| 46472 | /* 130783 */ // GIR_Coverage, 1390, |
| 46473 | /* 130783 */ GIR_EraseRootFromParent_Done, |
| 46474 | /* 130784 */ // Label 2556: @130784 |
| 46475 | /* 130784 */ GIM_Reject, |
| 46476 | /* 130785 */ // Label 2550: @130785 |
| 46477 | /* 130785 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(130831), // Rule ID 1392 // |
| 46478 | /* 130790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 46479 | /* 130793 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46480 | /* 130796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 46481 | /* 130799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46482 | /* 130803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46483 | /* 130807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46484 | /* 130811 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 46485 | /* 130811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 46486 | /* 130814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46487 | /* 130816 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46488 | /* 130818 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46489 | /* 130820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46490 | /* 130823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46491 | /* 130829 */ GIR_RootConstrainSelectedInstOperands, |
| 46492 | /* 130830 */ // GIR_Coverage, 1392, |
| 46493 | /* 130830 */ GIR_EraseRootFromParent_Done, |
| 46494 | /* 130831 */ // Label 2557: @130831 |
| 46495 | /* 130831 */ GIM_Reject, |
| 46496 | /* 130832 */ // Label 2551: @130832 |
| 46497 | /* 130832 */ GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(130878), // Rule ID 1391 // |
| 46498 | /* 130837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46499 | /* 130840 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46500 | /* 130843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46501 | /* 130846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46502 | /* 130850 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46503 | /* 130854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46504 | /* 130858 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 46505 | /* 130858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq), |
| 46506 | /* 130861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46507 | /* 130863 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46508 | /* 130865 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46509 | /* 130867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46510 | /* 130870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46511 | /* 130876 */ GIR_RootConstrainSelectedInstOperands, |
| 46512 | /* 130877 */ // GIR_Coverage, 1391, |
| 46513 | /* 130877 */ GIR_EraseRootFromParent_Done, |
| 46514 | /* 130878 */ // Label 2558: @130878 |
| 46515 | /* 130878 */ GIM_Reject, |
| 46516 | /* 130879 */ // Label 2552: @130879 |
| 46517 | /* 130879 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(130925), // Rule ID 1393 // |
| 46518 | /* 130884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 46519 | /* 130887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46520 | /* 130890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46521 | /* 130893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46522 | /* 130897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46523 | /* 130901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46524 | /* 130905 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 46525 | /* 130905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq), |
| 46526 | /* 130908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46527 | /* 130910 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46528 | /* 130912 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46529 | /* 130914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46530 | /* 130917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46531 | /* 130923 */ GIR_RootConstrainSelectedInstOperands, |
| 46532 | /* 130924 */ // GIR_Coverage, 1393, |
| 46533 | /* 130924 */ GIR_EraseRootFromParent_Done, |
| 46534 | /* 130925 */ // Label 2559: @130925 |
| 46535 | /* 130925 */ GIM_Reject, |
| 46536 | /* 130926 */ // Label 2553: @130926 |
| 46537 | /* 130926 */ GIM_Reject, |
| 46538 | /* 130927 */ // Label 56: @130927 |
| 46539 | /* 130927 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2566*/ GIMT_Encode4(131660), |
| 46540 | /* 130938 */ /*GILLT_s16*//*Label 2560*/ GIMT_Encode4(130990), |
| 46541 | /* 130942 */ /*GILLT_s32*//*Label 2561*/ GIMT_Encode4(131231), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46542 | /* 130954 */ /*GILLT_v2s32*//*Label 2562*/ GIMT_Encode4(131472), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46543 | /* 130966 */ /*GILLT_v4s16*//*Label 2563*/ GIMT_Encode4(131519), |
| 46544 | /* 130970 */ /*GILLT_v4s32*//*Label 2564*/ GIMT_Encode4(131566), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46545 | /* 130986 */ /*GILLT_v8s16*//*Label 2565*/ GIMT_Encode4(131613), |
| 46546 | /* 130990 */ // Label 2560: @130990 |
| 46547 | /* 130990 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(131230), // Rule ID 3080 // |
| 46548 | /* 130995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 46549 | /* 130998 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46550 | /* 131001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46551 | /* 131004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46552 | /* 131008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46553 | /* 131012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46554 | /* 131016 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 46555 | /* 131016 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 46556 | /* 131019 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46557 | /* 131023 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46558 | /* 131028 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 46559 | /* 131030 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 46560 | /* 131033 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46561 | /* 131037 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46562 | /* 131042 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 46563 | /* 131045 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46564 | /* 131050 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 46565 | /* 131053 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46566 | /* 131057 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46567 | /* 131062 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 46568 | /* 131065 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 46569 | /* 131069 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 46570 | /* 131072 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46571 | /* 131077 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46572 | /* 131082 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 46573 | /* 131087 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 46574 | /* 131090 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46575 | /* 131094 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46576 | /* 131099 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 46577 | /* 131101 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 46578 | /* 131104 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46579 | /* 131108 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46580 | /* 131113 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 46581 | /* 131116 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46582 | /* 131121 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 46583 | /* 131124 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46584 | /* 131128 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46585 | /* 131133 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 46586 | /* 131136 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 46587 | /* 131140 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 46588 | /* 131143 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46589 | /* 131148 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46590 | /* 131153 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 46591 | /* 131158 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 46592 | /* 131161 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 46593 | /* 131165 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46594 | /* 131170 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 46595 | /* 131173 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 46596 | /* 131176 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 46597 | /* 131179 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46598 | /* 131185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 46599 | /* 131187 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 46600 | /* 131190 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46601 | /* 131194 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46602 | /* 131199 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 46603 | /* 131202 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46604 | /* 131207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46605 | /* 131210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 46606 | /* 131212 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 46607 | /* 131219 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 46608 | /* 131224 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46609 | /* 131229 */ // GIR_Coverage, 3080, |
| 46610 | /* 131229 */ GIR_EraseRootFromParent_Done, |
| 46611 | /* 131230 */ // Label 2567: @131230 |
| 46612 | /* 131230 */ GIM_Reject, |
| 46613 | /* 131231 */ // Label 2561: @131231 |
| 46614 | /* 131231 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(131471), // Rule ID 3082 // |
| 46615 | /* 131236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46616 | /* 131239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46617 | /* 131242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46618 | /* 131245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46619 | /* 131249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46620 | /* 131253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46621 | /* 131257 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 46622 | /* 131257 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 46623 | /* 131260 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46624 | /* 131264 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46625 | /* 131269 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 46626 | /* 131271 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 46627 | /* 131274 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46628 | /* 131278 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46629 | /* 131283 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 46630 | /* 131286 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46631 | /* 131291 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 46632 | /* 131294 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46633 | /* 131298 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46634 | /* 131303 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 46635 | /* 131306 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 46636 | /* 131310 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 46637 | /* 131313 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46638 | /* 131318 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46639 | /* 131323 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 46640 | /* 131328 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 46641 | /* 131331 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46642 | /* 131335 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46643 | /* 131340 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 46644 | /* 131342 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 46645 | /* 131345 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46646 | /* 131349 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46647 | /* 131354 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 46648 | /* 131357 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46649 | /* 131362 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 46650 | /* 131365 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 46651 | /* 131369 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46652 | /* 131374 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 46653 | /* 131377 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 46654 | /* 131381 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 46655 | /* 131384 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46656 | /* 131389 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46657 | /* 131394 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 46658 | /* 131399 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 46659 | /* 131402 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 46660 | /* 131406 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46661 | /* 131411 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 46662 | /* 131414 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 46663 | /* 131417 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 46664 | /* 131420 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46665 | /* 131426 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 46666 | /* 131428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 46667 | /* 131431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46668 | /* 131435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46669 | /* 131440 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 46670 | /* 131443 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46671 | /* 131448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 46672 | /* 131451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 46673 | /* 131453 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 46674 | /* 131460 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 46675 | /* 131465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 46676 | /* 131470 */ // GIR_Coverage, 3082, |
| 46677 | /* 131470 */ GIR_EraseRootFromParent_Done, |
| 46678 | /* 131471 */ // Label 2568: @131471 |
| 46679 | /* 131471 */ GIM_Reject, |
| 46680 | /* 131472 */ // Label 2562: @131472 |
| 46681 | /* 131472 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(131518), // Rule ID 1370 // |
| 46682 | /* 131477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46683 | /* 131480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46684 | /* 131483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 46685 | /* 131486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46686 | /* 131490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46687 | /* 131494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46688 | /* 131498 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 46689 | /* 131498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 46690 | /* 131501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46691 | /* 131503 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46692 | /* 131505 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46693 | /* 131507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46694 | /* 131510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46695 | /* 131516 */ GIR_RootConstrainSelectedInstOperands, |
| 46696 | /* 131517 */ // GIR_Coverage, 1370, |
| 46697 | /* 131517 */ GIR_EraseRootFromParent_Done, |
| 46698 | /* 131518 */ // Label 2569: @131518 |
| 46699 | /* 131518 */ GIM_Reject, |
| 46700 | /* 131519 */ // Label 2563: @131519 |
| 46701 | /* 131519 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(131565), // Rule ID 1372 // |
| 46702 | /* 131524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 46703 | /* 131527 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46704 | /* 131530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 46705 | /* 131533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46706 | /* 131537 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46707 | /* 131541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46708 | /* 131545 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 46709 | /* 131545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 46710 | /* 131548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46711 | /* 131550 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46712 | /* 131552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46713 | /* 131554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46714 | /* 131557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46715 | /* 131563 */ GIR_RootConstrainSelectedInstOperands, |
| 46716 | /* 131564 */ // GIR_Coverage, 1372, |
| 46717 | /* 131564 */ GIR_EraseRootFromParent_Done, |
| 46718 | /* 131565 */ // Label 2570: @131565 |
| 46719 | /* 131565 */ GIM_Reject, |
| 46720 | /* 131566 */ // Label 2564: @131566 |
| 46721 | /* 131566 */ GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(131612), // Rule ID 1371 // |
| 46722 | /* 131571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46723 | /* 131574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46724 | /* 131577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46725 | /* 131580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46726 | /* 131584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46727 | /* 131588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46728 | /* 131592 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 46729 | /* 131592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq), |
| 46730 | /* 131595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46731 | /* 131597 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46732 | /* 131599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46733 | /* 131601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46734 | /* 131604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46735 | /* 131610 */ GIR_RootConstrainSelectedInstOperands, |
| 46736 | /* 131611 */ // GIR_Coverage, 1371, |
| 46737 | /* 131611 */ GIR_EraseRootFromParent_Done, |
| 46738 | /* 131612 */ // Label 2571: @131612 |
| 46739 | /* 131612 */ GIM_Reject, |
| 46740 | /* 131613 */ // Label 2565: @131613 |
| 46741 | /* 131613 */ GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(131659), // Rule ID 1373 // |
| 46742 | /* 131618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 46743 | /* 131621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46744 | /* 131624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46745 | /* 131627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46746 | /* 131631 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46747 | /* 131635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46748 | /* 131639 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 46749 | /* 131639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq), |
| 46750 | /* 131642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46751 | /* 131644 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46752 | /* 131646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46753 | /* 131648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46754 | /* 131651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46755 | /* 131657 */ GIR_RootConstrainSelectedInstOperands, |
| 46756 | /* 131658 */ // GIR_Coverage, 1373, |
| 46757 | /* 131658 */ GIR_EraseRootFromParent_Done, |
| 46758 | /* 131659 */ // Label 2572: @131659 |
| 46759 | /* 131659 */ GIM_Reject, |
| 46760 | /* 131660 */ // Label 2566: @131660 |
| 46761 | /* 131660 */ GIM_Reject, |
| 46762 | /* 131661 */ // Label 57: @131661 |
| 46763 | /* 131661 */ GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(131693), // Rule ID 2785 // |
| 46764 | /* 131666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46765 | /* 131669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 46766 | /* 131673 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 46767 | /* 131673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 46768 | /* 131676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 46769 | /* 131678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46770 | /* 131681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46771 | /* 131687 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46772 | /* 131691 */ GIR_RootConstrainSelectedInstOperands, |
| 46773 | /* 131692 */ // GIR_Coverage, 2785, |
| 46774 | /* 131692 */ GIR_EraseRootFromParent_Done, |
| 46775 | /* 131693 */ // Label 2573: @131693 |
| 46776 | /* 131693 */ GIM_Reject, |
| 46777 | /* 131694 */ // Label 58: @131694 |
| 46778 | /* 131694 */ GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(131729), // Rule ID 2786 // |
| 46779 | /* 131699 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46780 | /* 131702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 46781 | /* 131706 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 46782 | /* 131706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 46783 | /* 131709 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt |
| 46784 | /* 131711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46785 | /* 131714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46786 | /* 131720 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 46787 | /* 131723 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46788 | /* 131727 */ GIR_RootConstrainSelectedInstOperands, |
| 46789 | /* 131728 */ // GIR_Coverage, 2786, |
| 46790 | /* 131728 */ GIR_EraseRootFromParent_Done, |
| 46791 | /* 131729 */ // Label 2574: @131729 |
| 46792 | /* 131729 */ GIM_Reject, |
| 46793 | /* 131730 */ // Label 59: @131730 |
| 46794 | /* 131730 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(131794), // Rule ID 2787 // |
| 46795 | /* 131735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 46796 | /* 131738 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] })) |
| 46797 | /* 131738 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46798 | /* 131741 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 46799 | /* 131745 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46800 | /* 131750 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 46801 | /* 131753 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46802 | /* 131756 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46803 | /* 131762 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46804 | /* 131768 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46805 | /* 131770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 46806 | /* 131773 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46807 | /* 131776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46808 | /* 131779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46809 | /* 131785 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 46810 | /* 131788 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46811 | /* 131792 */ GIR_RootConstrainSelectedInstOperands, |
| 46812 | /* 131793 */ // GIR_Coverage, 2787, |
| 46813 | /* 131793 */ GIR_EraseRootFromParent_Done, |
| 46814 | /* 131794 */ // Label 2575: @131794 |
| 46815 | /* 131794 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(131858), // Rule ID 2788 // |
| 46816 | /* 131799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 46817 | /* 131802 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 46818 | /* 131802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46819 | /* 131805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 46820 | /* 131809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46821 | /* 131814 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 46822 | /* 131820 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 46823 | /* 131823 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46824 | /* 131826 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46825 | /* 131832 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46826 | /* 131834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 46827 | /* 131837 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46828 | /* 131840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46829 | /* 131843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46830 | /* 131849 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 46831 | /* 131852 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46832 | /* 131856 */ GIR_RootConstrainSelectedInstOperands, |
| 46833 | /* 131857 */ // GIR_Coverage, 2788, |
| 46834 | /* 131857 */ GIR_EraseRootFromParent_Done, |
| 46835 | /* 131858 */ // Label 2576: @131858 |
| 46836 | /* 131858 */ GIM_Reject, |
| 46837 | /* 131859 */ // Label 60: @131859 |
| 46838 | /* 131859 */ GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(131891), // Rule ID 2789 // |
| 46839 | /* 131864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46840 | /* 131867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 46841 | /* 131871 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 46842 | /* 131871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 46843 | /* 131874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 46844 | /* 131876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46845 | /* 131879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46846 | /* 131885 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46847 | /* 131889 */ GIR_RootConstrainSelectedInstOperands, |
| 46848 | /* 131890 */ // GIR_Coverage, 2789, |
| 46849 | /* 131890 */ GIR_EraseRootFromParent_Done, |
| 46850 | /* 131891 */ // Label 2577: @131891 |
| 46851 | /* 131891 */ GIM_Reject, |
| 46852 | /* 131892 */ // Label 61: @131892 |
| 46853 | /* 131892 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2584*/ GIMT_Encode4(132434), |
| 46854 | /* 131903 */ /*GILLT_v2s32*//*Label 2578*/ GIMT_Encode4(131951), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46855 | /* 131915 */ /*GILLT_v4s16*//*Label 2579*/ GIMT_Encode4(131998), |
| 46856 | /* 131919 */ /*GILLT_v4s32*//*Label 2580*/ GIMT_Encode4(132045), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46857 | /* 131931 */ /*GILLT_v8s8*//*Label 2581*/ GIMT_Encode4(132159), |
| 46858 | /* 131935 */ /*GILLT_v8s16*//*Label 2582*/ GIMT_Encode4(132206), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46859 | /* 131947 */ /*GILLT_v16s8*//*Label 2583*/ GIMT_Encode4(132320), |
| 46860 | /* 131951 */ // Label 2578: @131951 |
| 46861 | /* 131951 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(131997), // Rule ID 1379 // |
| 46862 | /* 131956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46863 | /* 131959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46864 | /* 131962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 46865 | /* 131965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46866 | /* 131969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46867 | /* 131973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46868 | /* 131977 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 46869 | /* 131977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32), |
| 46870 | /* 131980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46871 | /* 131982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46872 | /* 131984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46873 | /* 131986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46874 | /* 131989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46875 | /* 131995 */ GIR_RootConstrainSelectedInstOperands, |
| 46876 | /* 131996 */ // GIR_Coverage, 1379, |
| 46877 | /* 131996 */ GIR_EraseRootFromParent_Done, |
| 46878 | /* 131997 */ // Label 2585: @131997 |
| 46879 | /* 131997 */ GIM_Reject, |
| 46880 | /* 131998 */ // Label 2579: @131998 |
| 46881 | /* 131998 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(132044), // Rule ID 1378 // |
| 46882 | /* 132003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46883 | /* 132006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46884 | /* 132009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 46885 | /* 132012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46886 | /* 132016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46887 | /* 132020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46888 | /* 132024 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 46889 | /* 132024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16), |
| 46890 | /* 132027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46891 | /* 132029 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46892 | /* 132031 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46893 | /* 132033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46894 | /* 132036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46895 | /* 132042 */ GIR_RootConstrainSelectedInstOperands, |
| 46896 | /* 132043 */ // GIR_Coverage, 1378, |
| 46897 | /* 132043 */ GIR_EraseRootFromParent_Done, |
| 46898 | /* 132044 */ // Label 2586: @132044 |
| 46899 | /* 132044 */ GIM_Reject, |
| 46900 | /* 132045 */ // Label 2580: @132045 |
| 46901 | /* 132045 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(132158), |
| 46902 | /* 132050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46903 | /* 132053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46904 | /* 132056 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(132096), // Rule ID 1381 // |
| 46905 | /* 132061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46906 | /* 132064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46907 | /* 132068 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46908 | /* 132072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46909 | /* 132076 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 46910 | /* 132076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32), |
| 46911 | /* 132079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46912 | /* 132081 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46913 | /* 132083 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46914 | /* 132085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46915 | /* 132088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46916 | /* 132094 */ GIR_RootConstrainSelectedInstOperands, |
| 46917 | /* 132095 */ // GIR_Coverage, 1381, |
| 46918 | /* 132095 */ GIR_EraseRootFromParent_Done, |
| 46919 | /* 132096 */ // Label 2588: @132096 |
| 46920 | /* 132096 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(132157), // Rule ID 3682 // |
| 46921 | /* 132101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46922 | /* 132104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46923 | /* 132108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46924 | /* 132112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46925 | /* 132116 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 46926 | /* 132116 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46927 | /* 132119 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46928 | /* 132123 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46929 | /* 132128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32), |
| 46930 | /* 132131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46931 | /* 132133 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 46932 | /* 132135 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 46933 | /* 132137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46934 | /* 132140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46935 | /* 132146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46936 | /* 132152 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46937 | /* 132155 */ GIR_RootConstrainSelectedInstOperands, |
| 46938 | /* 132156 */ // GIR_Coverage, 3682, |
| 46939 | /* 132156 */ GIR_EraseRootFromParent_Done, |
| 46940 | /* 132157 */ // Label 2589: @132157 |
| 46941 | /* 132157 */ GIM_Reject, |
| 46942 | /* 132158 */ // Label 2587: @132158 |
| 46943 | /* 132158 */ GIM_Reject, |
| 46944 | /* 132159 */ // Label 2581: @132159 |
| 46945 | /* 132159 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(132205), // Rule ID 1382 // |
| 46946 | /* 132164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46947 | /* 132167 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 46948 | /* 132170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 46949 | /* 132173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46950 | /* 132177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46951 | /* 132181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46952 | /* 132185 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 46953 | /* 132185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8), |
| 46954 | /* 132188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46955 | /* 132190 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46956 | /* 132192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46957 | /* 132194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46958 | /* 132197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46959 | /* 132203 */ GIR_RootConstrainSelectedInstOperands, |
| 46960 | /* 132204 */ // GIR_Coverage, 1382, |
| 46961 | /* 132204 */ GIR_EraseRootFromParent_Done, |
| 46962 | /* 132205 */ // Label 2590: @132205 |
| 46963 | /* 132205 */ GIM_Reject, |
| 46964 | /* 132206 */ // Label 2582: @132206 |
| 46965 | /* 132206 */ GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(132319), |
| 46966 | /* 132211 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46967 | /* 132214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46968 | /* 132217 */ GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(132257), // Rule ID 1380 // |
| 46969 | /* 132222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 46970 | /* 132225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46971 | /* 132229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46972 | /* 132233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46973 | /* 132237 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 46974 | /* 132237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16), |
| 46975 | /* 132240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 46976 | /* 132242 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 46977 | /* 132244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 46978 | /* 132246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46979 | /* 132249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46980 | /* 132255 */ GIR_RootConstrainSelectedInstOperands, |
| 46981 | /* 132256 */ // GIR_Coverage, 1380, |
| 46982 | /* 132256 */ GIR_EraseRootFromParent_Done, |
| 46983 | /* 132257 */ // Label 2592: @132257 |
| 46984 | /* 132257 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(132318), // Rule ID 3679 // |
| 46985 | /* 132262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46986 | /* 132265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46987 | /* 132269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46988 | /* 132273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46989 | /* 132277 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 46990 | /* 132277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46991 | /* 132280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46992 | /* 132284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46993 | /* 132289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16), |
| 46994 | /* 132292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46995 | /* 132294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 46996 | /* 132296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 46997 | /* 132298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46998 | /* 132301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46999 | /* 132307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47000 | /* 132313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47001 | /* 132316 */ GIR_RootConstrainSelectedInstOperands, |
| 47002 | /* 132317 */ // GIR_Coverage, 3679, |
| 47003 | /* 132317 */ GIR_EraseRootFromParent_Done, |
| 47004 | /* 132318 */ // Label 2593: @132318 |
| 47005 | /* 132318 */ GIM_Reject, |
| 47006 | /* 132319 */ // Label 2591: @132319 |
| 47007 | /* 132319 */ GIM_Reject, |
| 47008 | /* 132320 */ // Label 2583: @132320 |
| 47009 | /* 132320 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(132433), |
| 47010 | /* 132325 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47011 | /* 132328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47012 | /* 132331 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(132371), // Rule ID 1383 // |
| 47013 | /* 132336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47014 | /* 132339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47015 | /* 132343 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47016 | /* 132347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47017 | /* 132351 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 47018 | /* 132351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8), |
| 47019 | /* 132354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47020 | /* 132356 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47021 | /* 132358 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47022 | /* 132360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47023 | /* 132363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47024 | /* 132369 */ GIR_RootConstrainSelectedInstOperands, |
| 47025 | /* 132370 */ // GIR_Coverage, 1383, |
| 47026 | /* 132370 */ GIR_EraseRootFromParent_Done, |
| 47027 | /* 132371 */ // Label 2595: @132371 |
| 47028 | /* 132371 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(132432), // Rule ID 3676 // |
| 47029 | /* 132376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47030 | /* 132379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47031 | /* 132383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47032 | /* 132387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47033 | /* 132391 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 47034 | /* 132391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47035 | /* 132394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47036 | /* 132398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47037 | /* 132403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8), |
| 47038 | /* 132406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47039 | /* 132408 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47040 | /* 132410 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47041 | /* 132412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47042 | /* 132415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47043 | /* 132421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47044 | /* 132427 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47045 | /* 132430 */ GIR_RootConstrainSelectedInstOperands, |
| 47046 | /* 132431 */ // GIR_Coverage, 3676, |
| 47047 | /* 132431 */ GIR_EraseRootFromParent_Done, |
| 47048 | /* 132432 */ // Label 2596: @132432 |
| 47049 | /* 132432 */ GIM_Reject, |
| 47050 | /* 132433 */ // Label 2594: @132433 |
| 47051 | /* 132433 */ GIM_Reject, |
| 47052 | /* 132434 */ // Label 2584: @132434 |
| 47053 | /* 132434 */ GIM_Reject, |
| 47054 | /* 132435 */ // Label 62: @132435 |
| 47055 | /* 132435 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2603*/ GIMT_Encode4(132977), |
| 47056 | /* 132446 */ /*GILLT_v2s32*//*Label 2597*/ GIMT_Encode4(132494), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47057 | /* 132458 */ /*GILLT_v4s16*//*Label 2598*/ GIMT_Encode4(132541), |
| 47058 | /* 132462 */ /*GILLT_v4s32*//*Label 2599*/ GIMT_Encode4(132588), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47059 | /* 132474 */ /*GILLT_v8s8*//*Label 2600*/ GIMT_Encode4(132702), |
| 47060 | /* 132478 */ /*GILLT_v8s16*//*Label 2601*/ GIMT_Encode4(132749), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47061 | /* 132490 */ /*GILLT_v16s8*//*Label 2602*/ GIMT_Encode4(132863), |
| 47062 | /* 132494 */ // Label 2597: @132494 |
| 47063 | /* 132494 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(132540), // Rule ID 1359 // |
| 47064 | /* 132499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47065 | /* 132502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 47066 | /* 132505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47067 | /* 132508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47068 | /* 132512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47069 | /* 132516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47070 | /* 132520 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 47071 | /* 132520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32), |
| 47072 | /* 132523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47073 | /* 132525 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47074 | /* 132527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47075 | /* 132529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47076 | /* 132532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47077 | /* 132538 */ GIR_RootConstrainSelectedInstOperands, |
| 47078 | /* 132539 */ // GIR_Coverage, 1359, |
| 47079 | /* 132539 */ GIR_EraseRootFromParent_Done, |
| 47080 | /* 132540 */ // Label 2604: @132540 |
| 47081 | /* 132540 */ GIM_Reject, |
| 47082 | /* 132541 */ // Label 2598: @132541 |
| 47083 | /* 132541 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(132587), // Rule ID 1358 // |
| 47084 | /* 132546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47085 | /* 132549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 47086 | /* 132552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47087 | /* 132555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47088 | /* 132559 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47089 | /* 132563 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47090 | /* 132567 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 47091 | /* 132567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16), |
| 47092 | /* 132570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47093 | /* 132572 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47094 | /* 132574 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47095 | /* 132576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47096 | /* 132579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47097 | /* 132585 */ GIR_RootConstrainSelectedInstOperands, |
| 47098 | /* 132586 */ // GIR_Coverage, 1358, |
| 47099 | /* 132586 */ GIR_EraseRootFromParent_Done, |
| 47100 | /* 132587 */ // Label 2605: @132587 |
| 47101 | /* 132587 */ GIM_Reject, |
| 47102 | /* 132588 */ // Label 2599: @132588 |
| 47103 | /* 132588 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(132701), |
| 47104 | /* 132593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47105 | /* 132596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47106 | /* 132599 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(132639), // Rule ID 1361 // |
| 47107 | /* 132604 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47108 | /* 132607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47109 | /* 132611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47110 | /* 132615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47111 | /* 132619 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 47112 | /* 132619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32), |
| 47113 | /* 132622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47114 | /* 132624 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47115 | /* 132626 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47116 | /* 132628 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47117 | /* 132631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47118 | /* 132637 */ GIR_RootConstrainSelectedInstOperands, |
| 47119 | /* 132638 */ // GIR_Coverage, 1361, |
| 47120 | /* 132638 */ GIR_EraseRootFromParent_Done, |
| 47121 | /* 132639 */ // Label 2607: @132639 |
| 47122 | /* 132639 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(132700), // Rule ID 3700 // |
| 47123 | /* 132644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47124 | /* 132647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47125 | /* 132651 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47126 | /* 132655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47127 | /* 132659 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 47128 | /* 132659 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47129 | /* 132662 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47130 | /* 132666 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47131 | /* 132671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32), |
| 47132 | /* 132674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47133 | /* 132676 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47134 | /* 132678 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47135 | /* 132680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47136 | /* 132683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47137 | /* 132689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47138 | /* 132695 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47139 | /* 132698 */ GIR_RootConstrainSelectedInstOperands, |
| 47140 | /* 132699 */ // GIR_Coverage, 3700, |
| 47141 | /* 132699 */ GIR_EraseRootFromParent_Done, |
| 47142 | /* 132700 */ // Label 2608: @132700 |
| 47143 | /* 132700 */ GIM_Reject, |
| 47144 | /* 132701 */ // Label 2606: @132701 |
| 47145 | /* 132701 */ GIM_Reject, |
| 47146 | /* 132702 */ // Label 2600: @132702 |
| 47147 | /* 132702 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(132748), // Rule ID 1362 // |
| 47148 | /* 132707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47149 | /* 132710 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 47150 | /* 132713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 47151 | /* 132716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47152 | /* 132720 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47153 | /* 132724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47154 | /* 132728 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 47155 | /* 132728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8), |
| 47156 | /* 132731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47157 | /* 132733 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47158 | /* 132735 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47159 | /* 132737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47160 | /* 132740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47161 | /* 132746 */ GIR_RootConstrainSelectedInstOperands, |
| 47162 | /* 132747 */ // GIR_Coverage, 1362, |
| 47163 | /* 132747 */ GIR_EraseRootFromParent_Done, |
| 47164 | /* 132748 */ // Label 2609: @132748 |
| 47165 | /* 132748 */ GIM_Reject, |
| 47166 | /* 132749 */ // Label 2601: @132749 |
| 47167 | /* 132749 */ GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(132862), |
| 47168 | /* 132754 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47169 | /* 132757 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47170 | /* 132760 */ GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(132800), // Rule ID 1360 // |
| 47171 | /* 132765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47172 | /* 132768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47173 | /* 132772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47174 | /* 132776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47175 | /* 132780 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 47176 | /* 132780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16), |
| 47177 | /* 132783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47178 | /* 132785 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47179 | /* 132787 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47180 | /* 132789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47181 | /* 132792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47182 | /* 132798 */ GIR_RootConstrainSelectedInstOperands, |
| 47183 | /* 132799 */ // GIR_Coverage, 1360, |
| 47184 | /* 132799 */ GIR_EraseRootFromParent_Done, |
| 47185 | /* 132800 */ // Label 2611: @132800 |
| 47186 | /* 132800 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(132861), // Rule ID 3697 // |
| 47187 | /* 132805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47188 | /* 132808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47189 | /* 132812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47190 | /* 132816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47191 | /* 132820 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 47192 | /* 132820 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47193 | /* 132823 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47194 | /* 132827 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47195 | /* 132832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16), |
| 47196 | /* 132835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47197 | /* 132837 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47198 | /* 132839 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47199 | /* 132841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47200 | /* 132844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47201 | /* 132850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47202 | /* 132856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47203 | /* 132859 */ GIR_RootConstrainSelectedInstOperands, |
| 47204 | /* 132860 */ // GIR_Coverage, 3697, |
| 47205 | /* 132860 */ GIR_EraseRootFromParent_Done, |
| 47206 | /* 132861 */ // Label 2612: @132861 |
| 47207 | /* 132861 */ GIM_Reject, |
| 47208 | /* 132862 */ // Label 2610: @132862 |
| 47209 | /* 132862 */ GIM_Reject, |
| 47210 | /* 132863 */ // Label 2602: @132863 |
| 47211 | /* 132863 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(132976), |
| 47212 | /* 132868 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47213 | /* 132871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47214 | /* 132874 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(132914), // Rule ID 1363 // |
| 47215 | /* 132879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47216 | /* 132882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47217 | /* 132886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47218 | /* 132890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47219 | /* 132894 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 47220 | /* 132894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8), |
| 47221 | /* 132897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47222 | /* 132899 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47223 | /* 132901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47224 | /* 132903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47225 | /* 132906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47226 | /* 132912 */ GIR_RootConstrainSelectedInstOperands, |
| 47227 | /* 132913 */ // GIR_Coverage, 1363, |
| 47228 | /* 132913 */ GIR_EraseRootFromParent_Done, |
| 47229 | /* 132914 */ // Label 2614: @132914 |
| 47230 | /* 132914 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(132975), // Rule ID 3694 // |
| 47231 | /* 132919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47232 | /* 132922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47233 | /* 132926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47234 | /* 132930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47235 | /* 132934 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 47236 | /* 132934 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47237 | /* 132937 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47238 | /* 132941 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47239 | /* 132946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8), |
| 47240 | /* 132949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47241 | /* 132951 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47242 | /* 132953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47243 | /* 132955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47244 | /* 132958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47245 | /* 132964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47246 | /* 132970 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47247 | /* 132973 */ GIR_RootConstrainSelectedInstOperands, |
| 47248 | /* 132974 */ // GIR_Coverage, 3694, |
| 47249 | /* 132974 */ GIR_EraseRootFromParent_Done, |
| 47250 | /* 132975 */ // Label 2615: @132975 |
| 47251 | /* 132975 */ GIM_Reject, |
| 47252 | /* 132976 */ // Label 2613: @132976 |
| 47253 | /* 132976 */ GIM_Reject, |
| 47254 | /* 132977 */ // Label 2603: @132977 |
| 47255 | /* 132977 */ GIM_Reject, |
| 47256 | /* 132978 */ // Label 63: @132978 |
| 47257 | /* 132978 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2622*/ GIMT_Encode4(133898), |
| 47258 | /* 132989 */ /*GILLT_v2s32*//*Label 2616*/ GIMT_Encode4(133037), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47259 | /* 133001 */ /*GILLT_v4s16*//*Label 2617*/ GIMT_Encode4(133084), |
| 47260 | /* 133005 */ /*GILLT_v4s32*//*Label 2618*/ GIMT_Encode4(133131), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47261 | /* 133017 */ /*GILLT_v8s8*//*Label 2619*/ GIMT_Encode4(133371), |
| 47262 | /* 133021 */ /*GILLT_v8s16*//*Label 2620*/ GIMT_Encode4(133418), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47263 | /* 133033 */ /*GILLT_v16s8*//*Label 2621*/ GIMT_Encode4(133658), |
| 47264 | /* 133037 */ // Label 2616: @133037 |
| 47265 | /* 133037 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(133083), // Rule ID 1385 // |
| 47266 | /* 133042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47267 | /* 133045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 47268 | /* 133048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47269 | /* 133051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47270 | /* 133055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47271 | /* 133059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47272 | /* 133063 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 47273 | /* 133063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32), |
| 47274 | /* 133066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47275 | /* 133068 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47276 | /* 133070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47277 | /* 133072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47278 | /* 133075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47279 | /* 133081 */ GIR_RootConstrainSelectedInstOperands, |
| 47280 | /* 133082 */ // GIR_Coverage, 1385, |
| 47281 | /* 133082 */ GIR_EraseRootFromParent_Done, |
| 47282 | /* 133083 */ // Label 2623: @133083 |
| 47283 | /* 133083 */ GIM_Reject, |
| 47284 | /* 133084 */ // Label 2617: @133084 |
| 47285 | /* 133084 */ GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(133130), // Rule ID 1384 // |
| 47286 | /* 133089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47287 | /* 133092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 47288 | /* 133095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47289 | /* 133098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47290 | /* 133102 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47291 | /* 133106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47292 | /* 133110 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 47293 | /* 133110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16), |
| 47294 | /* 133113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47295 | /* 133115 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47296 | /* 133117 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47297 | /* 133119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47298 | /* 133122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47299 | /* 133128 */ GIR_RootConstrainSelectedInstOperands, |
| 47300 | /* 133129 */ // GIR_Coverage, 1384, |
| 47301 | /* 133129 */ GIR_EraseRootFromParent_Done, |
| 47302 | /* 133130 */ // Label 2624: @133130 |
| 47303 | /* 133130 */ GIM_Reject, |
| 47304 | /* 133131 */ // Label 2618: @133131 |
| 47305 | /* 133131 */ GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(133370), |
| 47306 | /* 133136 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47307 | /* 133139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47308 | /* 133142 */ GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(133205), // Rule ID 6634 // |
| 47309 | /* 133147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47310 | /* 133150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47311 | /* 133154 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47312 | /* 133158 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47313 | /* 133162 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47314 | /* 133166 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47315 | /* 133171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47316 | /* 133175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47317 | /* 133177 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 47318 | /* 133177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 47319 | /* 133180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47320 | /* 133182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 47321 | /* 133184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47322 | /* 133188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47323 | /* 133191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47324 | /* 133197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47325 | /* 133203 */ GIR_RootConstrainSelectedInstOperands, |
| 47326 | /* 133204 */ // GIR_Coverage, 6634, |
| 47327 | /* 133204 */ GIR_EraseRootFromParent_Done, |
| 47328 | /* 133205 */ // Label 2626: @133205 |
| 47329 | /* 133205 */ GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(133268), // Rule ID 4079 // |
| 47330 | /* 133210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47331 | /* 133213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47332 | /* 133217 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47333 | /* 133221 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 47334 | /* 133225 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47335 | /* 133229 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47336 | /* 133233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47337 | /* 133238 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47338 | /* 133240 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 47339 | /* 133240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 47340 | /* 133243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47341 | /* 133245 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 47342 | /* 133247 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47343 | /* 133251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47344 | /* 133254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47345 | /* 133260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47346 | /* 133266 */ GIR_RootConstrainSelectedInstOperands, |
| 47347 | /* 133267 */ // GIR_Coverage, 4079, |
| 47348 | /* 133267 */ GIR_EraseRootFromParent_Done, |
| 47349 | /* 133268 */ // Label 2627: @133268 |
| 47350 | /* 133268 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(133308), // Rule ID 1387 // |
| 47351 | /* 133273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47352 | /* 133276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47353 | /* 133280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47354 | /* 133284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47355 | /* 133288 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 47356 | /* 133288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32), |
| 47357 | /* 133291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47358 | /* 133293 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47359 | /* 133295 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47360 | /* 133297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47361 | /* 133300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47362 | /* 133306 */ GIR_RootConstrainSelectedInstOperands, |
| 47363 | /* 133307 */ // GIR_Coverage, 1387, |
| 47364 | /* 133307 */ GIR_EraseRootFromParent_Done, |
| 47365 | /* 133308 */ // Label 2628: @133308 |
| 47366 | /* 133308 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(133369), // Rule ID 3691 // |
| 47367 | /* 133313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47368 | /* 133316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47369 | /* 133320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47370 | /* 133324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47371 | /* 133328 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 47372 | /* 133328 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47373 | /* 133331 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47374 | /* 133335 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47375 | /* 133340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32), |
| 47376 | /* 133343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47377 | /* 133345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47378 | /* 133347 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47379 | /* 133349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47380 | /* 133352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47381 | /* 133358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47382 | /* 133364 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47383 | /* 133367 */ GIR_RootConstrainSelectedInstOperands, |
| 47384 | /* 133368 */ // GIR_Coverage, 3691, |
| 47385 | /* 133368 */ GIR_EraseRootFromParent_Done, |
| 47386 | /* 133369 */ // Label 2629: @133369 |
| 47387 | /* 133369 */ GIM_Reject, |
| 47388 | /* 133370 */ // Label 2625: @133370 |
| 47389 | /* 133370 */ GIM_Reject, |
| 47390 | /* 133371 */ // Label 2619: @133371 |
| 47391 | /* 133371 */ GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(133417), // Rule ID 1388 // |
| 47392 | /* 133376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47393 | /* 133379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 47394 | /* 133382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 47395 | /* 133385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47396 | /* 133389 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47397 | /* 133393 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47398 | /* 133397 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 47399 | /* 133397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8), |
| 47400 | /* 133400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47401 | /* 133402 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47402 | /* 133404 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47403 | /* 133406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47404 | /* 133409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47405 | /* 133415 */ GIR_RootConstrainSelectedInstOperands, |
| 47406 | /* 133416 */ // GIR_Coverage, 1388, |
| 47407 | /* 133416 */ GIR_EraseRootFromParent_Done, |
| 47408 | /* 133417 */ // Label 2630: @133417 |
| 47409 | /* 133417 */ GIM_Reject, |
| 47410 | /* 133418 */ // Label 2620: @133418 |
| 47411 | /* 133418 */ GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(133657), |
| 47412 | /* 133423 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47413 | /* 133426 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47414 | /* 133429 */ GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(133492), // Rule ID 6633 // |
| 47415 | /* 133434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47416 | /* 133437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47417 | /* 133441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47418 | /* 133445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47419 | /* 133449 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47420 | /* 133453 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47421 | /* 133458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47422 | /* 133462 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47423 | /* 133464 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 47424 | /* 133464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 47425 | /* 133467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47426 | /* 133469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 47427 | /* 133471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47428 | /* 133475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47429 | /* 133478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47430 | /* 133484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47431 | /* 133490 */ GIR_RootConstrainSelectedInstOperands, |
| 47432 | /* 133491 */ // GIR_Coverage, 6633, |
| 47433 | /* 133491 */ GIR_EraseRootFromParent_Done, |
| 47434 | /* 133492 */ // Label 2632: @133492 |
| 47435 | /* 133492 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(133555), // Rule ID 4077 // |
| 47436 | /* 133497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47437 | /* 133500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47438 | /* 133504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47439 | /* 133508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 47440 | /* 133512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47441 | /* 133516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47442 | /* 133520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47443 | /* 133525 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47444 | /* 133527 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 47445 | /* 133527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 47446 | /* 133530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47447 | /* 133532 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 47448 | /* 133534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47449 | /* 133538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47450 | /* 133541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47451 | /* 133547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47452 | /* 133553 */ GIR_RootConstrainSelectedInstOperands, |
| 47453 | /* 133554 */ // GIR_Coverage, 4077, |
| 47454 | /* 133554 */ GIR_EraseRootFromParent_Done, |
| 47455 | /* 133555 */ // Label 2633: @133555 |
| 47456 | /* 133555 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(133595), // Rule ID 1386 // |
| 47457 | /* 133560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47458 | /* 133563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47459 | /* 133567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47460 | /* 133571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47461 | /* 133575 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 47462 | /* 133575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16), |
| 47463 | /* 133578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47464 | /* 133580 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47465 | /* 133582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47466 | /* 133584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47467 | /* 133587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47468 | /* 133593 */ GIR_RootConstrainSelectedInstOperands, |
| 47469 | /* 133594 */ // GIR_Coverage, 1386, |
| 47470 | /* 133594 */ GIR_EraseRootFromParent_Done, |
| 47471 | /* 133595 */ // Label 2634: @133595 |
| 47472 | /* 133595 */ GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(133656), // Rule ID 3688 // |
| 47473 | /* 133600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47474 | /* 133603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47475 | /* 133607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47476 | /* 133611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47477 | /* 133615 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 47478 | /* 133615 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47479 | /* 133618 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47480 | /* 133622 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47481 | /* 133627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16), |
| 47482 | /* 133630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47483 | /* 133632 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47484 | /* 133634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47485 | /* 133636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47486 | /* 133639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47487 | /* 133645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47488 | /* 133651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47489 | /* 133654 */ GIR_RootConstrainSelectedInstOperands, |
| 47490 | /* 133655 */ // GIR_Coverage, 3688, |
| 47491 | /* 133655 */ GIR_EraseRootFromParent_Done, |
| 47492 | /* 133656 */ // Label 2635: @133656 |
| 47493 | /* 133656 */ GIM_Reject, |
| 47494 | /* 133657 */ // Label 2631: @133657 |
| 47495 | /* 133657 */ GIM_Reject, |
| 47496 | /* 133658 */ // Label 2621: @133658 |
| 47497 | /* 133658 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(133897), |
| 47498 | /* 133663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47499 | /* 133666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47500 | /* 133669 */ GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(133732), // Rule ID 6632 // |
| 47501 | /* 133674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47502 | /* 133677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47503 | /* 133681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47504 | /* 133685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47505 | /* 133689 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47506 | /* 133693 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47507 | /* 133698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47508 | /* 133702 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47509 | /* 133704 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 47510 | /* 133704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 47511 | /* 133707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47512 | /* 133709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 47513 | /* 133711 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47514 | /* 133715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47515 | /* 133718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47516 | /* 133724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47517 | /* 133730 */ GIR_RootConstrainSelectedInstOperands, |
| 47518 | /* 133731 */ // GIR_Coverage, 6632, |
| 47519 | /* 133731 */ GIR_EraseRootFromParent_Done, |
| 47520 | /* 133732 */ // Label 2637: @133732 |
| 47521 | /* 133732 */ GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(133795), // Rule ID 4075 // |
| 47522 | /* 133737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47523 | /* 133740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47524 | /* 133744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47525 | /* 133748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 47526 | /* 133752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47527 | /* 133756 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47528 | /* 133760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47529 | /* 133765 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47530 | /* 133767 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 47531 | /* 133767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 47532 | /* 133770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47533 | /* 133772 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 47534 | /* 133774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47535 | /* 133778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47536 | /* 133781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47537 | /* 133787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47538 | /* 133793 */ GIR_RootConstrainSelectedInstOperands, |
| 47539 | /* 133794 */ // GIR_Coverage, 4075, |
| 47540 | /* 133794 */ GIR_EraseRootFromParent_Done, |
| 47541 | /* 133795 */ // Label 2638: @133795 |
| 47542 | /* 133795 */ GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(133835), // Rule ID 1389 // |
| 47543 | /* 133800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47544 | /* 133803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47545 | /* 133807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47546 | /* 133811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47547 | /* 133815 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 47548 | /* 133815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8), |
| 47549 | /* 133818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47550 | /* 133820 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47551 | /* 133822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47552 | /* 133824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47553 | /* 133827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47554 | /* 133833 */ GIR_RootConstrainSelectedInstOperands, |
| 47555 | /* 133834 */ // GIR_Coverage, 1389, |
| 47556 | /* 133834 */ GIR_EraseRootFromParent_Done, |
| 47557 | /* 133835 */ // Label 2639: @133835 |
| 47558 | /* 133835 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(133896), // Rule ID 3685 // |
| 47559 | /* 133840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47560 | /* 133843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47561 | /* 133847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47562 | /* 133851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47563 | /* 133855 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 47564 | /* 133855 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47565 | /* 133858 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47566 | /* 133862 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47567 | /* 133867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8), |
| 47568 | /* 133870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47569 | /* 133872 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47570 | /* 133874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47571 | /* 133876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47572 | /* 133879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47573 | /* 133885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47574 | /* 133891 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47575 | /* 133894 */ GIR_RootConstrainSelectedInstOperands, |
| 47576 | /* 133895 */ // GIR_Coverage, 3685, |
| 47577 | /* 133895 */ GIR_EraseRootFromParent_Done, |
| 47578 | /* 133896 */ // Label 2640: @133896 |
| 47579 | /* 133896 */ GIM_Reject, |
| 47580 | /* 133897 */ // Label 2636: @133897 |
| 47581 | /* 133897 */ GIM_Reject, |
| 47582 | /* 133898 */ // Label 2622: @133898 |
| 47583 | /* 133898 */ GIM_Reject, |
| 47584 | /* 133899 */ // Label 64: @133899 |
| 47585 | /* 133899 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2647*/ GIMT_Encode4(134819), |
| 47586 | /* 133910 */ /*GILLT_v2s32*//*Label 2641*/ GIMT_Encode4(133958), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47587 | /* 133922 */ /*GILLT_v4s16*//*Label 2642*/ GIMT_Encode4(134005), |
| 47588 | /* 133926 */ /*GILLT_v4s32*//*Label 2643*/ GIMT_Encode4(134052), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47589 | /* 133938 */ /*GILLT_v8s8*//*Label 2644*/ GIMT_Encode4(134292), |
| 47590 | /* 133942 */ /*GILLT_v8s16*//*Label 2645*/ GIMT_Encode4(134339), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47591 | /* 133954 */ /*GILLT_v16s8*//*Label 2646*/ GIMT_Encode4(134579), |
| 47592 | /* 133958 */ // Label 2641: @133958 |
| 47593 | /* 133958 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(134004), // Rule ID 1365 // |
| 47594 | /* 133963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47595 | /* 133966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 47596 | /* 133969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47597 | /* 133972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47598 | /* 133976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47599 | /* 133980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47600 | /* 133984 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 47601 | /* 133984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32), |
| 47602 | /* 133987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47603 | /* 133989 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47604 | /* 133991 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47605 | /* 133993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47606 | /* 133996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47607 | /* 134002 */ GIR_RootConstrainSelectedInstOperands, |
| 47608 | /* 134003 */ // GIR_Coverage, 1365, |
| 47609 | /* 134003 */ GIR_EraseRootFromParent_Done, |
| 47610 | /* 134004 */ // Label 2648: @134004 |
| 47611 | /* 134004 */ GIM_Reject, |
| 47612 | /* 134005 */ // Label 2642: @134005 |
| 47613 | /* 134005 */ GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(134051), // Rule ID 1364 // |
| 47614 | /* 134010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47615 | /* 134013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 47616 | /* 134016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47617 | /* 134019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47618 | /* 134023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47619 | /* 134027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47620 | /* 134031 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 47621 | /* 134031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16), |
| 47622 | /* 134034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47623 | /* 134036 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47624 | /* 134038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47625 | /* 134040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47626 | /* 134043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47627 | /* 134049 */ GIR_RootConstrainSelectedInstOperands, |
| 47628 | /* 134050 */ // GIR_Coverage, 1364, |
| 47629 | /* 134050 */ GIR_EraseRootFromParent_Done, |
| 47630 | /* 134051 */ // Label 2649: @134051 |
| 47631 | /* 134051 */ GIM_Reject, |
| 47632 | /* 134052 */ // Label 2643: @134052 |
| 47633 | /* 134052 */ GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(134291), |
| 47634 | /* 134057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47635 | /* 134060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47636 | /* 134063 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(134126), // Rule ID 6637 // |
| 47637 | /* 134068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47638 | /* 134071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47639 | /* 134075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47640 | /* 134079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47641 | /* 134083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47642 | /* 134087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47643 | /* 134092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47644 | /* 134096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47645 | /* 134098 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 47646 | /* 134098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 47647 | /* 134101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47648 | /* 134103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 47649 | /* 134105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47650 | /* 134109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47651 | /* 134112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47652 | /* 134118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47653 | /* 134124 */ GIR_RootConstrainSelectedInstOperands, |
| 47654 | /* 134125 */ // GIR_Coverage, 6637, |
| 47655 | /* 134125 */ GIR_EraseRootFromParent_Done, |
| 47656 | /* 134126 */ // Label 2651: @134126 |
| 47657 | /* 134126 */ GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(134189), // Rule ID 4085 // |
| 47658 | /* 134131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47659 | /* 134134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47660 | /* 134138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47661 | /* 134142 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 47662 | /* 134146 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47663 | /* 134150 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47664 | /* 134154 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47665 | /* 134159 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47666 | /* 134161 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 47667 | /* 134161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 47668 | /* 134164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47669 | /* 134166 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 47670 | /* 134168 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47671 | /* 134172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47672 | /* 134175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47673 | /* 134181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47674 | /* 134187 */ GIR_RootConstrainSelectedInstOperands, |
| 47675 | /* 134188 */ // GIR_Coverage, 4085, |
| 47676 | /* 134188 */ GIR_EraseRootFromParent_Done, |
| 47677 | /* 134189 */ // Label 2652: @134189 |
| 47678 | /* 134189 */ GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(134229), // Rule ID 1367 // |
| 47679 | /* 134194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47680 | /* 134197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47681 | /* 134201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47682 | /* 134205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47683 | /* 134209 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 47684 | /* 134209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32), |
| 47685 | /* 134212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47686 | /* 134214 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47687 | /* 134216 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47688 | /* 134218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47689 | /* 134221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47690 | /* 134227 */ GIR_RootConstrainSelectedInstOperands, |
| 47691 | /* 134228 */ // GIR_Coverage, 1367, |
| 47692 | /* 134228 */ GIR_EraseRootFromParent_Done, |
| 47693 | /* 134229 */ // Label 2653: @134229 |
| 47694 | /* 134229 */ GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(134290), // Rule ID 3709 // |
| 47695 | /* 134234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47696 | /* 134237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47697 | /* 134241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47698 | /* 134245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47699 | /* 134249 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 47700 | /* 134249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47701 | /* 134252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47702 | /* 134256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47703 | /* 134261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32), |
| 47704 | /* 134264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47705 | /* 134266 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47706 | /* 134268 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47707 | /* 134270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47708 | /* 134273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47709 | /* 134279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47710 | /* 134285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47711 | /* 134288 */ GIR_RootConstrainSelectedInstOperands, |
| 47712 | /* 134289 */ // GIR_Coverage, 3709, |
| 47713 | /* 134289 */ GIR_EraseRootFromParent_Done, |
| 47714 | /* 134290 */ // Label 2654: @134290 |
| 47715 | /* 134290 */ GIM_Reject, |
| 47716 | /* 134291 */ // Label 2650: @134291 |
| 47717 | /* 134291 */ GIM_Reject, |
| 47718 | /* 134292 */ // Label 2644: @134292 |
| 47719 | /* 134292 */ GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(134338), // Rule ID 1368 // |
| 47720 | /* 134297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47721 | /* 134300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 47722 | /* 134303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 47723 | /* 134306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47724 | /* 134310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47725 | /* 134314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47726 | /* 134318 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 47727 | /* 134318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8), |
| 47728 | /* 134321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47729 | /* 134323 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47730 | /* 134325 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47731 | /* 134327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47732 | /* 134330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47733 | /* 134336 */ GIR_RootConstrainSelectedInstOperands, |
| 47734 | /* 134337 */ // GIR_Coverage, 1368, |
| 47735 | /* 134337 */ GIR_EraseRootFromParent_Done, |
| 47736 | /* 134338 */ // Label 2655: @134338 |
| 47737 | /* 134338 */ GIM_Reject, |
| 47738 | /* 134339 */ // Label 2645: @134339 |
| 47739 | /* 134339 */ GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(134578), |
| 47740 | /* 134344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47741 | /* 134347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47742 | /* 134350 */ GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(134413), // Rule ID 6636 // |
| 47743 | /* 134355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47744 | /* 134358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47745 | /* 134362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47746 | /* 134366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47747 | /* 134370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47748 | /* 134374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47749 | /* 134379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47750 | /* 134383 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47751 | /* 134385 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 47752 | /* 134385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 47753 | /* 134388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47754 | /* 134390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 47755 | /* 134392 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47756 | /* 134396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47757 | /* 134399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47758 | /* 134405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47759 | /* 134411 */ GIR_RootConstrainSelectedInstOperands, |
| 47760 | /* 134412 */ // GIR_Coverage, 6636, |
| 47761 | /* 134412 */ GIR_EraseRootFromParent_Done, |
| 47762 | /* 134413 */ // Label 2657: @134413 |
| 47763 | /* 134413 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(134476), // Rule ID 4083 // |
| 47764 | /* 134418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47765 | /* 134421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47766 | /* 134425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47767 | /* 134429 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 47768 | /* 134433 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47769 | /* 134437 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47770 | /* 134441 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47771 | /* 134446 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47772 | /* 134448 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 47773 | /* 134448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 47774 | /* 134451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47775 | /* 134453 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 47776 | /* 134455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47777 | /* 134459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47778 | /* 134462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47779 | /* 134468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47780 | /* 134474 */ GIR_RootConstrainSelectedInstOperands, |
| 47781 | /* 134475 */ // GIR_Coverage, 4083, |
| 47782 | /* 134475 */ GIR_EraseRootFromParent_Done, |
| 47783 | /* 134476 */ // Label 2658: @134476 |
| 47784 | /* 134476 */ GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(134516), // Rule ID 1366 // |
| 47785 | /* 134481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47786 | /* 134484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47787 | /* 134488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47788 | /* 134492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47789 | /* 134496 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 47790 | /* 134496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16), |
| 47791 | /* 134499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47792 | /* 134501 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47793 | /* 134503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47794 | /* 134505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47795 | /* 134508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47796 | /* 134514 */ GIR_RootConstrainSelectedInstOperands, |
| 47797 | /* 134515 */ // GIR_Coverage, 1366, |
| 47798 | /* 134515 */ GIR_EraseRootFromParent_Done, |
| 47799 | /* 134516 */ // Label 2659: @134516 |
| 47800 | /* 134516 */ GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(134577), // Rule ID 3706 // |
| 47801 | /* 134521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47802 | /* 134524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47803 | /* 134528 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47804 | /* 134532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47805 | /* 134536 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 47806 | /* 134536 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47807 | /* 134539 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47808 | /* 134543 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47809 | /* 134548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16), |
| 47810 | /* 134551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47811 | /* 134553 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47812 | /* 134555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47813 | /* 134557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47814 | /* 134560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47815 | /* 134566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47816 | /* 134572 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47817 | /* 134575 */ GIR_RootConstrainSelectedInstOperands, |
| 47818 | /* 134576 */ // GIR_Coverage, 3706, |
| 47819 | /* 134576 */ GIR_EraseRootFromParent_Done, |
| 47820 | /* 134577 */ // Label 2660: @134577 |
| 47821 | /* 134577 */ GIM_Reject, |
| 47822 | /* 134578 */ // Label 2656: @134578 |
| 47823 | /* 134578 */ GIM_Reject, |
| 47824 | /* 134579 */ // Label 2646: @134579 |
| 47825 | /* 134579 */ GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(134818), |
| 47826 | /* 134584 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47827 | /* 134587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47828 | /* 134590 */ GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(134653), // Rule ID 6635 // |
| 47829 | /* 134595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47830 | /* 134598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47831 | /* 134602 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47832 | /* 134606 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47833 | /* 134610 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47834 | /* 134614 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47835 | /* 134619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47836 | /* 134623 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47837 | /* 134625 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 47838 | /* 134625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 47839 | /* 134628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47840 | /* 134630 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 47841 | /* 134632 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47842 | /* 134636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47843 | /* 134639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47844 | /* 134645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47845 | /* 134651 */ GIR_RootConstrainSelectedInstOperands, |
| 47846 | /* 134652 */ // GIR_Coverage, 6635, |
| 47847 | /* 134652 */ GIR_EraseRootFromParent_Done, |
| 47848 | /* 134653 */ // Label 2662: @134653 |
| 47849 | /* 134653 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(134716), // Rule ID 4081 // |
| 47850 | /* 134658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47851 | /* 134661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47852 | /* 134665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47853 | /* 134669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 47854 | /* 134673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 47855 | /* 134677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47856 | /* 134681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47857 | /* 134686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47858 | /* 134688 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 47859 | /* 134688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 47860 | /* 134691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47861 | /* 134693 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 47862 | /* 134695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 47863 | /* 134699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47864 | /* 134702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47865 | /* 134708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47866 | /* 134714 */ GIR_RootConstrainSelectedInstOperands, |
| 47867 | /* 134715 */ // GIR_Coverage, 4081, |
| 47868 | /* 134715 */ GIR_EraseRootFromParent_Done, |
| 47869 | /* 134716 */ // Label 2663: @134716 |
| 47870 | /* 134716 */ GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(134756), // Rule ID 1369 // |
| 47871 | /* 134721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47872 | /* 134724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47873 | /* 134728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47874 | /* 134732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47875 | /* 134736 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 47876 | /* 134736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8), |
| 47877 | /* 134739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47878 | /* 134741 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 47879 | /* 134743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 47880 | /* 134745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47881 | /* 134748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47882 | /* 134754 */ GIR_RootConstrainSelectedInstOperands, |
| 47883 | /* 134755 */ // GIR_Coverage, 1369, |
| 47884 | /* 134755 */ GIR_EraseRootFromParent_Done, |
| 47885 | /* 134756 */ // Label 2664: @134756 |
| 47886 | /* 134756 */ GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(134817), // Rule ID 3703 // |
| 47887 | /* 134761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47888 | /* 134764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47889 | /* 134768 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47890 | /* 134772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47891 | /* 134776 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 47892 | /* 134776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47893 | /* 134779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47894 | /* 134783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47895 | /* 134788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8), |
| 47896 | /* 134791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47897 | /* 134793 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 47898 | /* 134795 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 47899 | /* 134797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47900 | /* 134800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47901 | /* 134806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47902 | /* 134812 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47903 | /* 134815 */ GIR_RootConstrainSelectedInstOperands, |
| 47904 | /* 134816 */ // GIR_Coverage, 3703, |
| 47905 | /* 134816 */ GIR_EraseRootFromParent_Done, |
| 47906 | /* 134817 */ // Label 2665: @134817 |
| 47907 | /* 134817 */ GIM_Reject, |
| 47908 | /* 134818 */ // Label 2661: @134818 |
| 47909 | /* 134818 */ GIM_Reject, |
| 47910 | /* 134819 */ // Label 2647: @134819 |
| 47911 | /* 134819 */ GIM_Reject, |
| 47912 | /* 134820 */ // Label 65: @134820 |
| 47913 | /* 134820 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2672*/ GIMT_Encode4(135290), |
| 47914 | /* 134831 */ /*GILLT_v2s32*//*Label 2666*/ GIMT_Encode4(134879), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47915 | /* 134843 */ /*GILLT_v4s16*//*Label 2667*/ GIMT_Encode4(134917), |
| 47916 | /* 134847 */ /*GILLT_v4s32*//*Label 2668*/ GIMT_Encode4(134955), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47917 | /* 134859 */ /*GILLT_v8s8*//*Label 2669*/ GIMT_Encode4(135054), |
| 47918 | /* 134863 */ /*GILLT_v8s16*//*Label 2670*/ GIMT_Encode4(135092), GIMT_Encode4(0), GIMT_Encode4(0), |
| 47919 | /* 134875 */ /*GILLT_v16s8*//*Label 2671*/ GIMT_Encode4(135191), |
| 47920 | /* 134879 */ // Label 2666: @134879 |
| 47921 | /* 134879 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(134916), // Rule ID 1671 // |
| 47922 | /* 134884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47923 | /* 134887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 47924 | /* 134890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47925 | /* 134894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47926 | /* 134898 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 47927 | /* 134898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32), |
| 47928 | /* 134901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47929 | /* 134903 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 47930 | /* 134905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47931 | /* 134908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47932 | /* 134914 */ GIR_RootConstrainSelectedInstOperands, |
| 47933 | /* 134915 */ // GIR_Coverage, 1671, |
| 47934 | /* 134915 */ GIR_EraseRootFromParent_Done, |
| 47935 | /* 134916 */ // Label 2673: @134916 |
| 47936 | /* 134916 */ GIM_Reject, |
| 47937 | /* 134917 */ // Label 2667: @134917 |
| 47938 | /* 134917 */ GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(134954), // Rule ID 1670 // |
| 47939 | /* 134922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47940 | /* 134925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 47941 | /* 134928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47942 | /* 134932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47943 | /* 134936 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 47944 | /* 134936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16), |
| 47945 | /* 134939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47946 | /* 134941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 47947 | /* 134943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47948 | /* 134946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47949 | /* 134952 */ GIR_RootConstrainSelectedInstOperands, |
| 47950 | /* 134953 */ // GIR_Coverage, 1670, |
| 47951 | /* 134953 */ GIR_EraseRootFromParent_Done, |
| 47952 | /* 134954 */ // Label 2674: @134954 |
| 47953 | /* 134954 */ GIM_Reject, |
| 47954 | /* 134955 */ // Label 2668: @134955 |
| 47955 | /* 134955 */ GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(135053), |
| 47956 | /* 134960 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47957 | /* 134963 */ GIM_Try, /*On fail goto*//*Label 2676*/ GIMT_Encode4(134997), // Rule ID 1674 // |
| 47958 | /* 134968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47959 | /* 134971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47960 | /* 134975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 47961 | /* 134979 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 47962 | /* 134979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32), |
| 47963 | /* 134982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 47964 | /* 134984 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 47965 | /* 134986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47966 | /* 134989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47967 | /* 134995 */ GIR_RootConstrainSelectedInstOperands, |
| 47968 | /* 134996 */ // GIR_Coverage, 1674, |
| 47969 | /* 134996 */ GIR_EraseRootFromParent_Done, |
| 47970 | /* 134997 */ // Label 2676: @134997 |
| 47971 | /* 134997 */ GIM_Try, /*On fail goto*//*Label 2677*/ GIMT_Encode4(135052), // Rule ID 4054 // |
| 47972 | /* 135002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 47973 | /* 135005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47974 | /* 135009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47975 | /* 135013 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v) |
| 47976 | /* 135013 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 47977 | /* 135016 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47978 | /* 135020 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47979 | /* 135025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32), |
| 47980 | /* 135028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 47981 | /* 135030 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 47982 | /* 135032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47983 | /* 135035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47984 | /* 135041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47985 | /* 135047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47986 | /* 135050 */ GIR_RootConstrainSelectedInstOperands, |
| 47987 | /* 135051 */ // GIR_Coverage, 4054, |
| 47988 | /* 135051 */ GIR_EraseRootFromParent_Done, |
| 47989 | /* 135052 */ // Label 2677: @135052 |
| 47990 | /* 135052 */ GIM_Reject, |
| 47991 | /* 135053 */ // Label 2675: @135053 |
| 47992 | /* 135053 */ GIM_Reject, |
| 47993 | /* 135054 */ // Label 2669: @135054 |
| 47994 | /* 135054 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(135091), // Rule ID 1669 // |
| 47995 | /* 135059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 47996 | /* 135062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 47997 | /* 135065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47998 | /* 135069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47999 | /* 135073 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 48000 | /* 135073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8), |
| 48001 | /* 135076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48002 | /* 135078 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48003 | /* 135080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48004 | /* 135083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48005 | /* 135089 */ GIR_RootConstrainSelectedInstOperands, |
| 48006 | /* 135090 */ // GIR_Coverage, 1669, |
| 48007 | /* 135090 */ GIR_EraseRootFromParent_Done, |
| 48008 | /* 135091 */ // Label 2678: @135091 |
| 48009 | /* 135091 */ GIM_Reject, |
| 48010 | /* 135092 */ // Label 2670: @135092 |
| 48011 | /* 135092 */ GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(135190), |
| 48012 | /* 135097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48013 | /* 135100 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(135134), // Rule ID 1673 // |
| 48014 | /* 135105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48015 | /* 135108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48016 | /* 135112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48017 | /* 135116 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 48018 | /* 135116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16), |
| 48019 | /* 135119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48020 | /* 135121 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48021 | /* 135123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48022 | /* 135126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48023 | /* 135132 */ GIR_RootConstrainSelectedInstOperands, |
| 48024 | /* 135133 */ // GIR_Coverage, 1673, |
| 48025 | /* 135133 */ GIR_EraseRootFromParent_Done, |
| 48026 | /* 135134 */ // Label 2680: @135134 |
| 48027 | /* 135134 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(135189), // Rule ID 4048 // |
| 48028 | /* 135139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48029 | /* 135142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48030 | /* 135146 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48031 | /* 135150 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v) |
| 48032 | /* 135150 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48033 | /* 135153 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48034 | /* 135157 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48035 | /* 135162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16), |
| 48036 | /* 135165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48037 | /* 135167 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 48038 | /* 135169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48039 | /* 135172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48040 | /* 135178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48041 | /* 135184 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48042 | /* 135187 */ GIR_RootConstrainSelectedInstOperands, |
| 48043 | /* 135188 */ // GIR_Coverage, 4048, |
| 48044 | /* 135188 */ GIR_EraseRootFromParent_Done, |
| 48045 | /* 135189 */ // Label 2681: @135189 |
| 48046 | /* 135189 */ GIM_Reject, |
| 48047 | /* 135190 */ // Label 2679: @135190 |
| 48048 | /* 135190 */ GIM_Reject, |
| 48049 | /* 135191 */ // Label 2671: @135191 |
| 48050 | /* 135191 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(135289), |
| 48051 | /* 135196 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 48052 | /* 135199 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(135233), // Rule ID 1672 // |
| 48053 | /* 135204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48054 | /* 135207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48055 | /* 135211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48056 | /* 135215 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 48057 | /* 135215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8), |
| 48058 | /* 135218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48059 | /* 135220 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48060 | /* 135222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48061 | /* 135225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48062 | /* 135231 */ GIR_RootConstrainSelectedInstOperands, |
| 48063 | /* 135232 */ // GIR_Coverage, 1672, |
| 48064 | /* 135232 */ GIR_EraseRootFromParent_Done, |
| 48065 | /* 135233 */ // Label 2683: @135233 |
| 48066 | /* 135233 */ GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(135288), // Rule ID 4042 // |
| 48067 | /* 135238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48068 | /* 135241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48069 | /* 135245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48070 | /* 135249 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v) |
| 48071 | /* 135249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48072 | /* 135252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48073 | /* 135256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48074 | /* 135261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8), |
| 48075 | /* 135264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48076 | /* 135266 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 48077 | /* 135268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48078 | /* 135271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48079 | /* 135277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48080 | /* 135283 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48081 | /* 135286 */ GIR_RootConstrainSelectedInstOperands, |
| 48082 | /* 135287 */ // GIR_Coverage, 4042, |
| 48083 | /* 135287 */ GIR_EraseRootFromParent_Done, |
| 48084 | /* 135288 */ // Label 2684: @135288 |
| 48085 | /* 135288 */ GIM_Reject, |
| 48086 | /* 135289 */ // Label 2682: @135289 |
| 48087 | /* 135289 */ GIM_Reject, |
| 48088 | /* 135290 */ // Label 2672: @135290 |
| 48089 | /* 135290 */ GIM_Reject, |
| 48090 | /* 135291 */ // Label 66: @135291 |
| 48091 | /* 135291 */ GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(135363), |
| 48092 | /* 135296 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 48093 | /* 135299 */ GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(135314), // Rule ID 31 // |
| 48094 | /* 135304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 48095 | /* 135307 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target) |
| 48096 | /* 135307 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B), |
| 48097 | /* 135312 */ GIR_RootConstrainSelectedInstOperands, |
| 48098 | /* 135313 */ // GIR_Coverage, 31, |
| 48099 | /* 135313 */ GIR_Done, |
| 48100 | /* 135314 */ // Label 2686: @135314 |
| 48101 | /* 135314 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(135338), // Rule ID 282 // |
| 48102 | /* 135319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 48103 | /* 135322 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target) |
| 48104 | /* 135322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB), |
| 48105 | /* 135325 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 48106 | /* 135327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48107 | /* 135330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48108 | /* 135336 */ GIR_RootConstrainSelectedInstOperands, |
| 48109 | /* 135337 */ // GIR_Coverage, 282, |
| 48110 | /* 135337 */ GIR_EraseRootFromParent_Done, |
| 48111 | /* 135338 */ // Label 2687: @135338 |
| 48112 | /* 135338 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(135362), // Rule ID 576 // |
| 48113 | /* 135343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), |
| 48114 | /* 135346 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target) |
| 48115 | /* 135346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B), |
| 48116 | /* 135349 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 48117 | /* 135351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48118 | /* 135354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48119 | /* 135360 */ GIR_RootConstrainSelectedInstOperands, |
| 48120 | /* 135361 */ // GIR_Coverage, 576, |
| 48121 | /* 135361 */ GIR_EraseRootFromParent_Done, |
| 48122 | /* 135362 */ // Label 2688: @135362 |
| 48123 | /* 135362 */ GIM_Reject, |
| 48124 | /* 135363 */ // Label 2685: @135363 |
| 48125 | /* 135363 */ GIM_Reject, |
| 48126 | /* 135364 */ // Label 67: @135364 |
| 48127 | /* 135364 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(16), /*)*//*default:*//*Label 2693*/ GIMT_Encode4(135663), |
| 48128 | /* 135375 */ /*GILLT_v4s16*//*Label 2689*/ GIMT_Encode4(135411), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48129 | /* 135391 */ /*GILLT_v8s8*//*Label 2690*/ GIMT_Encode4(135474), |
| 48130 | /* 135395 */ /*GILLT_v8s16*//*Label 2691*/ GIMT_Encode4(135537), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48131 | /* 135407 */ /*GILLT_v16s8*//*Label 2692*/ GIMT_Encode4(135600), |
| 48132 | /* 135411 */ // Label 2689: @135411 |
| 48133 | /* 135411 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(135473), // Rule ID 1733 // |
| 48134 | /* 135416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48135 | /* 135419 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 48136 | /* 135422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48137 | /* 135425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 48138 | /* 135428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48139 | /* 135432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48140 | /* 135436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48141 | /* 135440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 48142 | /* 135444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48143 | /* 135448 */ // MIs[1] Operand 1 |
| 48144 | /* 135448 */ // No operand predicates |
| 48145 | /* 135448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48146 | /* 135450 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 48147 | /* 135450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16), |
| 48148 | /* 135453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 48149 | /* 135455 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 48150 | /* 135457 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 48151 | /* 135459 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 48152 | /* 135462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48153 | /* 135465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48154 | /* 135471 */ GIR_RootConstrainSelectedInstOperands, |
| 48155 | /* 135472 */ // GIR_Coverage, 1733, |
| 48156 | /* 135472 */ GIR_EraseRootFromParent_Done, |
| 48157 | /* 135473 */ // Label 2694: @135473 |
| 48158 | /* 135473 */ GIM_Reject, |
| 48159 | /* 135474 */ // Label 2690: @135474 |
| 48160 | /* 135474 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(135536), // Rule ID 1732 // |
| 48161 | /* 135479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48162 | /* 135482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 48163 | /* 135485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48164 | /* 135488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 48165 | /* 135491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48166 | /* 135495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48167 | /* 135499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48168 | /* 135503 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 48169 | /* 135507 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48170 | /* 135511 */ // MIs[1] Operand 1 |
| 48171 | /* 135511 */ // No operand predicates |
| 48172 | /* 135511 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48173 | /* 135513 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 48174 | /* 135513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8), |
| 48175 | /* 135516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 48176 | /* 135518 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 48177 | /* 135520 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 48178 | /* 135522 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 48179 | /* 135525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48180 | /* 135528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48181 | /* 135534 */ GIR_RootConstrainSelectedInstOperands, |
| 48182 | /* 135535 */ // GIR_Coverage, 1732, |
| 48183 | /* 135535 */ GIR_EraseRootFromParent_Done, |
| 48184 | /* 135536 */ // Label 2695: @135536 |
| 48185 | /* 135536 */ GIM_Reject, |
| 48186 | /* 135537 */ // Label 2691: @135537 |
| 48187 | /* 135537 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(135599), // Rule ID 3818 // |
| 48188 | /* 135542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48189 | /* 135545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48190 | /* 135548 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48191 | /* 135551 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 48192 | /* 135554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48193 | /* 135558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48194 | /* 135562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48195 | /* 135566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 48196 | /* 135570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48197 | /* 135574 */ // MIs[1] Operand 1 |
| 48198 | /* 135574 */ // No operand predicates |
| 48199 | /* 135574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48200 | /* 135576 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 48201 | /* 135576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16), |
| 48202 | /* 135579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48203 | /* 135581 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 48204 | /* 135583 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 48205 | /* 135585 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 48206 | /* 135588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48207 | /* 135591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48208 | /* 135597 */ GIR_RootConstrainSelectedInstOperands, |
| 48209 | /* 135598 */ // GIR_Coverage, 3818, |
| 48210 | /* 135598 */ GIR_EraseRootFromParent_Done, |
| 48211 | /* 135599 */ // Label 2696: @135599 |
| 48212 | /* 135599 */ GIM_Reject, |
| 48213 | /* 135600 */ // Label 2692: @135600 |
| 48214 | /* 135600 */ GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(135662), // Rule ID 3817 // |
| 48215 | /* 135605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48216 | /* 135608 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 48217 | /* 135611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48218 | /* 135614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 48219 | /* 135617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48220 | /* 135621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48221 | /* 135625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48222 | /* 135629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 48223 | /* 135633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48224 | /* 135637 */ // MIs[1] Operand 1 |
| 48225 | /* 135637 */ // No operand predicates |
| 48226 | /* 135637 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48227 | /* 135639 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 48228 | /* 135639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8), |
| 48229 | /* 135642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48230 | /* 135644 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 48231 | /* 135646 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 48232 | /* 135648 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 48233 | /* 135651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48234 | /* 135654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48235 | /* 135660 */ GIR_RootConstrainSelectedInstOperands, |
| 48236 | /* 135661 */ // GIR_Coverage, 3817, |
| 48237 | /* 135661 */ GIR_EraseRootFromParent_Done, |
| 48238 | /* 135662 */ // Label 2697: @135662 |
| 48239 | /* 135662 */ GIM_Reject, |
| 48240 | /* 135663 */ // Label 2693: @135663 |
| 48241 | /* 135663 */ GIM_Reject, |
| 48242 | /* 135664 */ // Label 68: @135664 |
| 48243 | /* 135664 */ GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(135720), // Rule ID 1731 // |
| 48244 | /* 135669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32), |
| 48245 | /* 135672 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 48246 | /* 135675 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48247 | /* 135678 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48248 | /* 135681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48249 | /* 135685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48250 | /* 135689 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 48251 | /* 135693 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48252 | /* 135697 */ // MIs[1] Operand 1 |
| 48253 | /* 135697 */ // No operand predicates |
| 48254 | /* 135697 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48255 | /* 135699 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) |
| 48256 | /* 135699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32), |
| 48257 | /* 135702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R] |
| 48258 | /* 135704 */ GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 48259 | /* 135706 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 48260 | /* 135709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48261 | /* 135712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48262 | /* 135718 */ GIR_RootConstrainSelectedInstOperands, |
| 48263 | /* 135719 */ // GIR_Coverage, 1731, |
| 48264 | /* 135719 */ GIR_EraseRootFromParent_Done, |
| 48265 | /* 135720 */ // Label 2698: @135720 |
| 48266 | /* 135720 */ GIM_Reject, |
| 48267 | /* 135721 */ // Label 69: @135721 |
| 48268 | /* 135721 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2706*/ GIMT_Encode4(136281), |
| 48269 | /* 135732 */ /*GILLT_s32*//*Label 2699*/ GIMT_Encode4(135792), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48270 | /* 135744 */ /*GILLT_v2s32*//*Label 2700*/ GIMT_Encode4(135870), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48271 | /* 135756 */ /*GILLT_v4s16*//*Label 2701*/ GIMT_Encode4(135908), |
| 48272 | /* 135760 */ /*GILLT_v4s32*//*Label 2702*/ GIMT_Encode4(135946), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48273 | /* 135772 */ /*GILLT_v8s8*//*Label 2703*/ GIMT_Encode4(136045), |
| 48274 | /* 135776 */ /*GILLT_v8s16*//*Label 2704*/ GIMT_Encode4(136083), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48275 | /* 135788 */ /*GILLT_v16s8*//*Label 2705*/ GIMT_Encode4(136182), |
| 48276 | /* 135792 */ // Label 2699: @135792 |
| 48277 | /* 135792 */ GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(135869), |
| 48278 | /* 135797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 48279 | /* 135800 */ GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(135834), // Rule ID 196 // |
| 48280 | /* 135805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM), |
| 48281 | /* 135808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48282 | /* 135812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48283 | /* 135816 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 48284 | /* 135816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ), |
| 48285 | /* 135819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 48286 | /* 135821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 48287 | /* 135823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48288 | /* 135826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48289 | /* 135832 */ GIR_RootConstrainSelectedInstOperands, |
| 48290 | /* 135833 */ // GIR_Coverage, 196, |
| 48291 | /* 135833 */ GIR_EraseRootFromParent_Done, |
| 48292 | /* 135834 */ // Label 2708: @135834 |
| 48293 | /* 135834 */ GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(135868), // Rule ID 533 // |
| 48294 | /* 135839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 48295 | /* 135842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48296 | /* 135846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48297 | /* 135850 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 48298 | /* 135850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ), |
| 48299 | /* 135853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 48300 | /* 135855 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 48301 | /* 135857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48302 | /* 135860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48303 | /* 135866 */ GIR_RootConstrainSelectedInstOperands, |
| 48304 | /* 135867 */ // GIR_Coverage, 533, |
| 48305 | /* 135867 */ GIR_EraseRootFromParent_Done, |
| 48306 | /* 135868 */ // Label 2709: @135868 |
| 48307 | /* 135868 */ GIM_Reject, |
| 48308 | /* 135869 */ // Label 2707: @135869 |
| 48309 | /* 135869 */ GIM_Reject, |
| 48310 | /* 135870 */ // Label 2700: @135870 |
| 48311 | /* 135870 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(135907), // Rule ID 1709 // |
| 48312 | /* 135875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48313 | /* 135878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48314 | /* 135881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48315 | /* 135885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48316 | /* 135889 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 48317 | /* 135889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32), |
| 48318 | /* 135892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48319 | /* 135894 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48320 | /* 135896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48321 | /* 135899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48322 | /* 135905 */ GIR_RootConstrainSelectedInstOperands, |
| 48323 | /* 135906 */ // GIR_Coverage, 1709, |
| 48324 | /* 135906 */ GIR_EraseRootFromParent_Done, |
| 48325 | /* 135907 */ // Label 2710: @135907 |
| 48326 | /* 135907 */ GIM_Reject, |
| 48327 | /* 135908 */ // Label 2701: @135908 |
| 48328 | /* 135908 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(135945), // Rule ID 1708 // |
| 48329 | /* 135913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48330 | /* 135916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 48331 | /* 135919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48332 | /* 135923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48333 | /* 135927 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 48334 | /* 135927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16), |
| 48335 | /* 135930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48336 | /* 135932 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48337 | /* 135934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48338 | /* 135937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48339 | /* 135943 */ GIR_RootConstrainSelectedInstOperands, |
| 48340 | /* 135944 */ // GIR_Coverage, 1708, |
| 48341 | /* 135944 */ GIR_EraseRootFromParent_Done, |
| 48342 | /* 135945 */ // Label 2711: @135945 |
| 48343 | /* 135945 */ GIM_Reject, |
| 48344 | /* 135946 */ // Label 2702: @135946 |
| 48345 | /* 135946 */ GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(136044), |
| 48346 | /* 135951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48347 | /* 135954 */ GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(135988), // Rule ID 1712 // |
| 48348 | /* 135959 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48349 | /* 135962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48350 | /* 135966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48351 | /* 135970 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 48352 | /* 135970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32), |
| 48353 | /* 135973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48354 | /* 135975 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48355 | /* 135977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48356 | /* 135980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48357 | /* 135986 */ GIR_RootConstrainSelectedInstOperands, |
| 48358 | /* 135987 */ // GIR_Coverage, 1712, |
| 48359 | /* 135987 */ GIR_EraseRootFromParent_Done, |
| 48360 | /* 135988 */ // Label 2713: @135988 |
| 48361 | /* 135988 */ GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(136043), // Rule ID 4040 // |
| 48362 | /* 135993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48363 | /* 135996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48364 | /* 136000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48365 | /* 136004 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 48366 | /* 136004 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48367 | /* 136007 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48368 | /* 136011 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48369 | /* 136016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32), |
| 48370 | /* 136019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48371 | /* 136021 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 48372 | /* 136023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48373 | /* 136026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48374 | /* 136032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48375 | /* 136038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48376 | /* 136041 */ GIR_RootConstrainSelectedInstOperands, |
| 48377 | /* 136042 */ // GIR_Coverage, 4040, |
| 48378 | /* 136042 */ GIR_EraseRootFromParent_Done, |
| 48379 | /* 136043 */ // Label 2714: @136043 |
| 48380 | /* 136043 */ GIM_Reject, |
| 48381 | /* 136044 */ // Label 2712: @136044 |
| 48382 | /* 136044 */ GIM_Reject, |
| 48383 | /* 136045 */ // Label 2703: @136045 |
| 48384 | /* 136045 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(136082), // Rule ID 1707 // |
| 48385 | /* 136050 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48386 | /* 136053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 48387 | /* 136056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48388 | /* 136060 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48389 | /* 136064 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 48390 | /* 136064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8), |
| 48391 | /* 136067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48392 | /* 136069 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48393 | /* 136071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48394 | /* 136074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48395 | /* 136080 */ GIR_RootConstrainSelectedInstOperands, |
| 48396 | /* 136081 */ // GIR_Coverage, 1707, |
| 48397 | /* 136081 */ GIR_EraseRootFromParent_Done, |
| 48398 | /* 136082 */ // Label 2715: @136082 |
| 48399 | /* 136082 */ GIM_Reject, |
| 48400 | /* 136083 */ // Label 2704: @136083 |
| 48401 | /* 136083 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(136181), |
| 48402 | /* 136088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48403 | /* 136091 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(136125), // Rule ID 1711 // |
| 48404 | /* 136096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48405 | /* 136099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48406 | /* 136103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48407 | /* 136107 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 48408 | /* 136107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16), |
| 48409 | /* 136110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48410 | /* 136112 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48411 | /* 136114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48412 | /* 136117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48413 | /* 136123 */ GIR_RootConstrainSelectedInstOperands, |
| 48414 | /* 136124 */ // GIR_Coverage, 1711, |
| 48415 | /* 136124 */ GIR_EraseRootFromParent_Done, |
| 48416 | /* 136125 */ // Label 2717: @136125 |
| 48417 | /* 136125 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(136180), // Rule ID 4038 // |
| 48418 | /* 136130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48419 | /* 136133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48420 | /* 136137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48421 | /* 136141 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 48422 | /* 136141 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48423 | /* 136144 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48424 | /* 136148 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48425 | /* 136153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16), |
| 48426 | /* 136156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48427 | /* 136158 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 48428 | /* 136160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48429 | /* 136163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48430 | /* 136169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48431 | /* 136175 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48432 | /* 136178 */ GIR_RootConstrainSelectedInstOperands, |
| 48433 | /* 136179 */ // GIR_Coverage, 4038, |
| 48434 | /* 136179 */ GIR_EraseRootFromParent_Done, |
| 48435 | /* 136180 */ // Label 2718: @136180 |
| 48436 | /* 136180 */ GIM_Reject, |
| 48437 | /* 136181 */ // Label 2716: @136181 |
| 48438 | /* 136181 */ GIM_Reject, |
| 48439 | /* 136182 */ // Label 2705: @136182 |
| 48440 | /* 136182 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(136280), |
| 48441 | /* 136187 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 48442 | /* 136190 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(136224), // Rule ID 1710 // |
| 48443 | /* 136195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48444 | /* 136198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48445 | /* 136202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48446 | /* 136206 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 48447 | /* 136206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8), |
| 48448 | /* 136209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48449 | /* 136211 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48450 | /* 136213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48451 | /* 136216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48452 | /* 136222 */ GIR_RootConstrainSelectedInstOperands, |
| 48453 | /* 136223 */ // GIR_Coverage, 1710, |
| 48454 | /* 136223 */ GIR_EraseRootFromParent_Done, |
| 48455 | /* 136224 */ // Label 2720: @136224 |
| 48456 | /* 136224 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(136279), // Rule ID 4036 // |
| 48457 | /* 136229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48458 | /* 136232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48459 | /* 136236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48460 | /* 136240 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 48461 | /* 136240 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48462 | /* 136243 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48463 | /* 136247 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48464 | /* 136252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8), |
| 48465 | /* 136255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48466 | /* 136257 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 48467 | /* 136259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48468 | /* 136262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48469 | /* 136268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48470 | /* 136274 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48471 | /* 136277 */ GIR_RootConstrainSelectedInstOperands, |
| 48472 | /* 136278 */ // GIR_Coverage, 4036, |
| 48473 | /* 136278 */ GIR_EraseRootFromParent_Done, |
| 48474 | /* 136279 */ // Label 2721: @136279 |
| 48475 | /* 136279 */ GIM_Reject, |
| 48476 | /* 136280 */ // Label 2719: @136280 |
| 48477 | /* 136280 */ GIM_Reject, |
| 48478 | /* 136281 */ // Label 2706: @136281 |
| 48479 | /* 136281 */ GIM_Reject, |
| 48480 | /* 136282 */ // Label 70: @136282 |
| 48481 | /* 136282 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2728*/ GIMT_Encode4(136752), |
| 48482 | /* 136293 */ /*GILLT_v2s32*//*Label 2722*/ GIMT_Encode4(136341), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48483 | /* 136305 */ /*GILLT_v4s16*//*Label 2723*/ GIMT_Encode4(136379), |
| 48484 | /* 136309 */ /*GILLT_v4s32*//*Label 2724*/ GIMT_Encode4(136417), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48485 | /* 136321 */ /*GILLT_v8s8*//*Label 2725*/ GIMT_Encode4(136516), |
| 48486 | /* 136325 */ /*GILLT_v8s16*//*Label 2726*/ GIMT_Encode4(136554), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48487 | /* 136337 */ /*GILLT_v16s8*//*Label 2727*/ GIMT_Encode4(136653), |
| 48488 | /* 136341 */ // Label 2722: @136341 |
| 48489 | /* 136341 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(136378), // Rule ID 1703 // |
| 48490 | /* 136346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48491 | /* 136349 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48492 | /* 136352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48493 | /* 136356 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48494 | /* 136360 */ // (ctls:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 48495 | /* 136360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32), |
| 48496 | /* 136363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48497 | /* 136365 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48498 | /* 136367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48499 | /* 136370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48500 | /* 136376 */ GIR_RootConstrainSelectedInstOperands, |
| 48501 | /* 136377 */ // GIR_Coverage, 1703, |
| 48502 | /* 136377 */ GIR_EraseRootFromParent_Done, |
| 48503 | /* 136378 */ // Label 2729: @136378 |
| 48504 | /* 136378 */ GIM_Reject, |
| 48505 | /* 136379 */ // Label 2723: @136379 |
| 48506 | /* 136379 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(136416), // Rule ID 1702 // |
| 48507 | /* 136384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48508 | /* 136387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 48509 | /* 136390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48510 | /* 136394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48511 | /* 136398 */ // (ctls:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 48512 | /* 136398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16), |
| 48513 | /* 136401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48514 | /* 136403 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48515 | /* 136405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48516 | /* 136408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48517 | /* 136414 */ GIR_RootConstrainSelectedInstOperands, |
| 48518 | /* 136415 */ // GIR_Coverage, 1702, |
| 48519 | /* 136415 */ GIR_EraseRootFromParent_Done, |
| 48520 | /* 136416 */ // Label 2730: @136416 |
| 48521 | /* 136416 */ GIM_Reject, |
| 48522 | /* 136417 */ // Label 2724: @136417 |
| 48523 | /* 136417 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(136515), |
| 48524 | /* 136422 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48525 | /* 136425 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(136459), // Rule ID 1706 // |
| 48526 | /* 136430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48527 | /* 136433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48528 | /* 136437 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48529 | /* 136441 */ // (ctls:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 48530 | /* 136441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32), |
| 48531 | /* 136444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48532 | /* 136446 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48533 | /* 136448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48534 | /* 136451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48535 | /* 136457 */ GIR_RootConstrainSelectedInstOperands, |
| 48536 | /* 136458 */ // GIR_Coverage, 1706, |
| 48537 | /* 136458 */ GIR_EraseRootFromParent_Done, |
| 48538 | /* 136459 */ // Label 2732: @136459 |
| 48539 | /* 136459 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(136514), // Rule ID 4034 // |
| 48540 | /* 136464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48541 | /* 136467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48542 | /* 136471 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48543 | /* 136475 */ // (ctls:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 48544 | /* 136475 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48545 | /* 136478 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48546 | /* 136482 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48547 | /* 136487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32), |
| 48548 | /* 136490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48549 | /* 136492 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 48550 | /* 136494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48551 | /* 136497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48552 | /* 136503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48553 | /* 136509 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48554 | /* 136512 */ GIR_RootConstrainSelectedInstOperands, |
| 48555 | /* 136513 */ // GIR_Coverage, 4034, |
| 48556 | /* 136513 */ GIR_EraseRootFromParent_Done, |
| 48557 | /* 136514 */ // Label 2733: @136514 |
| 48558 | /* 136514 */ GIM_Reject, |
| 48559 | /* 136515 */ // Label 2731: @136515 |
| 48560 | /* 136515 */ GIM_Reject, |
| 48561 | /* 136516 */ // Label 2725: @136516 |
| 48562 | /* 136516 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(136553), // Rule ID 1701 // |
| 48563 | /* 136521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48564 | /* 136524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 48565 | /* 136527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48566 | /* 136531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48567 | /* 136535 */ // (ctls:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 48568 | /* 136535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8), |
| 48569 | /* 136538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48570 | /* 136540 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48571 | /* 136542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48572 | /* 136545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48573 | /* 136551 */ GIR_RootConstrainSelectedInstOperands, |
| 48574 | /* 136552 */ // GIR_Coverage, 1701, |
| 48575 | /* 136552 */ GIR_EraseRootFromParent_Done, |
| 48576 | /* 136553 */ // Label 2734: @136553 |
| 48577 | /* 136553 */ GIM_Reject, |
| 48578 | /* 136554 */ // Label 2726: @136554 |
| 48579 | /* 136554 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(136652), |
| 48580 | /* 136559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48581 | /* 136562 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(136596), // Rule ID 1705 // |
| 48582 | /* 136567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48583 | /* 136570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48584 | /* 136574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48585 | /* 136578 */ // (ctls:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 48586 | /* 136578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16), |
| 48587 | /* 136581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48588 | /* 136583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48589 | /* 136585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48590 | /* 136588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48591 | /* 136594 */ GIR_RootConstrainSelectedInstOperands, |
| 48592 | /* 136595 */ // GIR_Coverage, 1705, |
| 48593 | /* 136595 */ GIR_EraseRootFromParent_Done, |
| 48594 | /* 136596 */ // Label 2736: @136596 |
| 48595 | /* 136596 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(136651), // Rule ID 4032 // |
| 48596 | /* 136601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48597 | /* 136604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48598 | /* 136608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48599 | /* 136612 */ // (ctls:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 48600 | /* 136612 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48601 | /* 136615 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48602 | /* 136619 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48603 | /* 136624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16), |
| 48604 | /* 136627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48605 | /* 136629 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 48606 | /* 136631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48607 | /* 136634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48608 | /* 136640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48609 | /* 136646 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48610 | /* 136649 */ GIR_RootConstrainSelectedInstOperands, |
| 48611 | /* 136650 */ // GIR_Coverage, 4032, |
| 48612 | /* 136650 */ GIR_EraseRootFromParent_Done, |
| 48613 | /* 136651 */ // Label 2737: @136651 |
| 48614 | /* 136651 */ GIM_Reject, |
| 48615 | /* 136652 */ // Label 2735: @136652 |
| 48616 | /* 136652 */ GIM_Reject, |
| 48617 | /* 136653 */ // Label 2727: @136653 |
| 48618 | /* 136653 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(136751), |
| 48619 | /* 136658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 48620 | /* 136661 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(136695), // Rule ID 1704 // |
| 48621 | /* 136666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48622 | /* 136669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48623 | /* 136673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48624 | /* 136677 */ // (ctls:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 48625 | /* 136677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8), |
| 48626 | /* 136680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48627 | /* 136682 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48628 | /* 136684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48629 | /* 136687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48630 | /* 136693 */ GIR_RootConstrainSelectedInstOperands, |
| 48631 | /* 136694 */ // GIR_Coverage, 1704, |
| 48632 | /* 136694 */ GIR_EraseRootFromParent_Done, |
| 48633 | /* 136695 */ // Label 2739: @136695 |
| 48634 | /* 136695 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(136750), // Rule ID 4030 // |
| 48635 | /* 136700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48636 | /* 136703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48637 | /* 136707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48638 | /* 136711 */ // (ctls:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 48639 | /* 136711 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48640 | /* 136714 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48641 | /* 136718 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48642 | /* 136723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8), |
| 48643 | /* 136726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48644 | /* 136728 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 48645 | /* 136730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48646 | /* 136733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48647 | /* 136739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48648 | /* 136745 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48649 | /* 136748 */ GIR_RootConstrainSelectedInstOperands, |
| 48650 | /* 136749 */ // GIR_Coverage, 4030, |
| 48651 | /* 136749 */ GIR_EraseRootFromParent_Done, |
| 48652 | /* 136750 */ // Label 2740: @136750 |
| 48653 | /* 136750 */ GIM_Reject, |
| 48654 | /* 136751 */ // Label 2738: @136751 |
| 48655 | /* 136751 */ GIM_Reject, |
| 48656 | /* 136752 */ // Label 2728: @136752 |
| 48657 | /* 136752 */ GIM_Reject, |
| 48658 | /* 136753 */ // Label 71: @136753 |
| 48659 | /* 136753 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(16), /*)*//*default:*//*Label 2743*/ GIMT_Encode4(136860), |
| 48660 | /* 136764 */ /*GILLT_v8s8*//*Label 2741*/ GIMT_Encode4(136784), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48661 | /* 136780 */ /*GILLT_v16s8*//*Label 2742*/ GIMT_Encode4(136822), |
| 48662 | /* 136784 */ // Label 2741: @136784 |
| 48663 | /* 136784 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(136821), // Rule ID 1713 // |
| 48664 | /* 136789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48665 | /* 136792 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 48666 | /* 136795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48667 | /* 136799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48668 | /* 136803 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 48669 | /* 136803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd), |
| 48670 | /* 136806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48671 | /* 136808 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48672 | /* 136810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48673 | /* 136813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48674 | /* 136819 */ GIR_RootConstrainSelectedInstOperands, |
| 48675 | /* 136820 */ // GIR_Coverage, 1713, |
| 48676 | /* 136820 */ GIR_EraseRootFromParent_Done, |
| 48677 | /* 136821 */ // Label 2744: @136821 |
| 48678 | /* 136821 */ GIM_Reject, |
| 48679 | /* 136822 */ // Label 2742: @136822 |
| 48680 | /* 136822 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(136859), // Rule ID 1714 // |
| 48681 | /* 136827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 48682 | /* 136830 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 48683 | /* 136833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48684 | /* 136837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 48685 | /* 136841 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 48686 | /* 136841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq), |
| 48687 | /* 136844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 48688 | /* 136846 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 48689 | /* 136848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48690 | /* 136851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48691 | /* 136857 */ GIR_RootConstrainSelectedInstOperands, |
| 48692 | /* 136858 */ // GIR_Coverage, 1714, |
| 48693 | /* 136858 */ GIR_EraseRootFromParent_Done, |
| 48694 | /* 136859 */ // Label 2745: @136859 |
| 48695 | /* 136859 */ GIM_Reject, |
| 48696 | /* 136860 */ // Label 2743: @136860 |
| 48697 | /* 136860 */ GIM_Reject, |
| 48698 | /* 136861 */ // Label 72: @136861 |
| 48699 | /* 136861 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2749*/ GIMT_Encode4(137150), |
| 48700 | /* 136872 */ /*GILLT_s32*//*Label 2746*/ GIMT_Encode4(136920), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48701 | /* 136900 */ /*GILLT_v4s32*//*Label 2747*/ GIMT_Encode4(137032), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48702 | /* 136916 */ /*GILLT_v8s16*//*Label 2748*/ GIMT_Encode4(137091), |
| 48703 | /* 136920 */ // Label 2746: @136920 |
| 48704 | /* 136920 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(137031), |
| 48705 | /* 136925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 48706 | /* 136928 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(136962), // Rule ID 198 // |
| 48707 | /* 136933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 48708 | /* 136936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48709 | /* 136940 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48710 | /* 136944 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 48711 | /* 136944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV), |
| 48712 | /* 136947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 48713 | /* 136949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 48714 | /* 136951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48715 | /* 136954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48716 | /* 136960 */ GIR_RootConstrainSelectedInstOperands, |
| 48717 | /* 136961 */ // GIR_Coverage, 198, |
| 48718 | /* 136961 */ GIR_EraseRootFromParent_Done, |
| 48719 | /* 136962 */ // Label 2751: @136962 |
| 48720 | /* 136962 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(136996), // Rule ID 325 // |
| 48721 | /* 136967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 48722 | /* 136970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 48723 | /* 136974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 48724 | /* 136978 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 48725 | /* 136978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV), |
| 48726 | /* 136981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 48727 | /* 136983 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 48728 | /* 136985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48729 | /* 136988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48730 | /* 136994 */ GIR_RootConstrainSelectedInstOperands, |
| 48731 | /* 136995 */ // GIR_Coverage, 325, |
| 48732 | /* 136995 */ GIR_EraseRootFromParent_Done, |
| 48733 | /* 136996 */ // Label 2752: @136996 |
| 48734 | /* 136996 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(137030), // Rule ID 535 // |
| 48735 | /* 137001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 48736 | /* 137004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48737 | /* 137008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48738 | /* 137012 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 48739 | /* 137012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV), |
| 48740 | /* 137015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 48741 | /* 137017 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 48742 | /* 137019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48743 | /* 137022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48744 | /* 137028 */ GIR_RootConstrainSelectedInstOperands, |
| 48745 | /* 137029 */ // GIR_Coverage, 535, |
| 48746 | /* 137029 */ GIR_EraseRootFromParent_Done, |
| 48747 | /* 137030 */ // Label 2753: @137030 |
| 48748 | /* 137030 */ GIM_Reject, |
| 48749 | /* 137031 */ // Label 2750: @137031 |
| 48750 | /* 137031 */ GIM_Reject, |
| 48751 | /* 137032 */ // Label 2747: @137032 |
| 48752 | /* 137032 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(137090), // Rule ID 3713 // |
| 48753 | /* 137037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48754 | /* 137040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48755 | /* 137043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48756 | /* 137047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48757 | /* 137051 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 48758 | /* 137051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48759 | /* 137054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48760 | /* 137058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48761 | /* 137063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 48762 | /* 137066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48763 | /* 137068 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 48764 | /* 137070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48765 | /* 137073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48766 | /* 137079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48767 | /* 137085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48768 | /* 137088 */ GIR_RootConstrainSelectedInstOperands, |
| 48769 | /* 137089 */ // GIR_Coverage, 3713, |
| 48770 | /* 137089 */ GIR_EraseRootFromParent_Done, |
| 48771 | /* 137090 */ // Label 2754: @137090 |
| 48772 | /* 137090 */ GIM_Reject, |
| 48773 | /* 137091 */ // Label 2748: @137091 |
| 48774 | /* 137091 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(137149), // Rule ID 3712 // |
| 48775 | /* 137096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48776 | /* 137099 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48777 | /* 137102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48778 | /* 137106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48779 | /* 137110 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 48780 | /* 137110 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 48781 | /* 137113 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48782 | /* 137117 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48783 | /* 137122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 48784 | /* 137125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48785 | /* 137127 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 48786 | /* 137129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48787 | /* 137132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48788 | /* 137138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48789 | /* 137144 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48790 | /* 137147 */ GIR_RootConstrainSelectedInstOperands, |
| 48791 | /* 137148 */ // GIR_Coverage, 3712, |
| 48792 | /* 137148 */ GIR_EraseRootFromParent_Done, |
| 48793 | /* 137149 */ // Label 2755: @137149 |
| 48794 | /* 137149 */ GIM_Reject, |
| 48795 | /* 137150 */ // Label 2749: @137150 |
| 48796 | /* 137150 */ GIM_Reject, |
| 48797 | /* 137151 */ // Label 73: @137151 |
| 48798 | /* 137151 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2760*/ GIMT_Encode4(137582), |
| 48799 | /* 137162 */ /*GILLT_s32*//*Label 2756*/ GIMT_Encode4(137222), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48800 | /* 137190 */ /*GILLT_v4s32*//*Label 2757*/ GIMT_Encode4(137300), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48801 | /* 137206 */ /*GILLT_v8s16*//*Label 2758*/ GIMT_Encode4(137394), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48802 | /* 137218 */ /*GILLT_v16s8*//*Label 2759*/ GIMT_Encode4(137488), |
| 48803 | /* 137222 */ // Label 2756: @137222 |
| 48804 | /* 137222 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(137299), |
| 48805 | /* 137227 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 48806 | /* 137230 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(137264), // Rule ID 197 // |
| 48807 | /* 137235 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 48808 | /* 137238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48809 | /* 137242 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 48810 | /* 137246 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 48811 | /* 137246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT), |
| 48812 | /* 137249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 48813 | /* 137251 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 48814 | /* 137253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48815 | /* 137256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48816 | /* 137262 */ GIR_RootConstrainSelectedInstOperands, |
| 48817 | /* 137263 */ // GIR_Coverage, 197, |
| 48818 | /* 137263 */ GIR_EraseRootFromParent_Done, |
| 48819 | /* 137264 */ // Label 2762: @137264 |
| 48820 | /* 137264 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(137298), // Rule ID 534 // |
| 48821 | /* 137269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 48822 | /* 137272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48823 | /* 137276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 48824 | /* 137280 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 48825 | /* 137280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT), |
| 48826 | /* 137283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 48827 | /* 137285 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 48828 | /* 137287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 48829 | /* 137290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48830 | /* 137296 */ GIR_RootConstrainSelectedInstOperands, |
| 48831 | /* 137297 */ // GIR_Coverage, 534, |
| 48832 | /* 137297 */ GIR_EraseRootFromParent_Done, |
| 48833 | /* 137298 */ // Label 2763: @137298 |
| 48834 | /* 137298 */ GIM_Reject, |
| 48835 | /* 137299 */ // Label 2761: @137299 |
| 48836 | /* 137299 */ GIM_Reject, |
| 48837 | /* 137300 */ // Label 2757: @137300 |
| 48838 | /* 137300 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(137393), // Rule ID 5260 // |
| 48839 | /* 137305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48840 | /* 137308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48841 | /* 137311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48842 | /* 137315 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48843 | /* 137319 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] })) |
| 48844 | /* 137319 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 48845 | /* 137322 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48846 | /* 137326 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48847 | /* 137331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48848 | /* 137334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 48849 | /* 137338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48850 | /* 137343 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 48851 | /* 137346 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 48852 | /* 137349 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48853 | /* 137355 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48854 | /* 137361 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48855 | /* 137363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 48856 | /* 137366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48857 | /* 137368 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 48858 | /* 137370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48859 | /* 137373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48860 | /* 137376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48861 | /* 137382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48862 | /* 137388 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 48863 | /* 137391 */ GIR_RootConstrainSelectedInstOperands, |
| 48864 | /* 137392 */ // GIR_Coverage, 5260, |
| 48865 | /* 137392 */ GIR_EraseRootFromParent_Done, |
| 48866 | /* 137393 */ // Label 2764: @137393 |
| 48867 | /* 137393 */ GIM_Reject, |
| 48868 | /* 137394 */ // Label 2758: @137394 |
| 48869 | /* 137394 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(137487), // Rule ID 5261 // |
| 48870 | /* 137399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48871 | /* 137402 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48872 | /* 137405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48873 | /* 137409 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48874 | /* 137413 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] })) |
| 48875 | /* 137413 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 48876 | /* 137416 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48877 | /* 137420 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48878 | /* 137425 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48879 | /* 137428 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 48880 | /* 137432 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48881 | /* 137437 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16, |
| 48882 | /* 137440 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 48883 | /* 137443 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48884 | /* 137449 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48885 | /* 137455 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48886 | /* 137457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 48887 | /* 137460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48888 | /* 137462 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 48889 | /* 137464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48890 | /* 137467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48891 | /* 137470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48892 | /* 137476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48893 | /* 137482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 48894 | /* 137485 */ GIR_RootConstrainSelectedInstOperands, |
| 48895 | /* 137486 */ // GIR_Coverage, 5261, |
| 48896 | /* 137486 */ GIR_EraseRootFromParent_Done, |
| 48897 | /* 137487 */ // Label 2765: @137487 |
| 48898 | /* 137487 */ GIM_Reject, |
| 48899 | /* 137488 */ // Label 2759: @137488 |
| 48900 | /* 137488 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(137581), // Rule ID 5259 // |
| 48901 | /* 137493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 48902 | /* 137496 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 48903 | /* 137499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48904 | /* 137503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 48905 | /* 137507 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] })) |
| 48906 | /* 137507 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 48907 | /* 137510 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48908 | /* 137514 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48909 | /* 137519 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48910 | /* 137522 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 48911 | /* 137526 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 48912 | /* 137531 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 48913 | /* 137534 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 48914 | /* 137537 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48915 | /* 137543 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48916 | /* 137549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48917 | /* 137551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 48918 | /* 137554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 48919 | /* 137556 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 48920 | /* 137558 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48921 | /* 137561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48922 | /* 137564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48923 | /* 137570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48924 | /* 137576 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 48925 | /* 137579 */ GIR_RootConstrainSelectedInstOperands, |
| 48926 | /* 137580 */ // GIR_Coverage, 5259, |
| 48927 | /* 137580 */ GIR_EraseRootFromParent_Done, |
| 48928 | /* 137581 */ // Label 2766: @137581 |
| 48929 | /* 137581 */ GIM_Reject, |
| 48930 | /* 137582 */ // Label 2760: @137582 |
| 48931 | /* 137582 */ GIM_Reject, |
| 48932 | /* 137583 */ // Label 74: @137583 |
| 48933 | /* 137583 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2774*/ GIMT_Encode4(137957), |
| 48934 | /* 137594 */ /*GILLT_s16*//*Label 2767*/ GIMT_Encode4(137646), |
| 48935 | /* 137598 */ /*GILLT_s32*//*Label 2768*/ GIMT_Encode4(137673), |
| 48936 | /* 137602 */ /*GILLT_s64*//*Label 2769*/ GIMT_Encode4(137700), GIMT_Encode4(0), |
| 48937 | /* 137610 */ /*GILLT_v2s32*//*Label 2770*/ GIMT_Encode4(137727), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48938 | /* 137622 */ /*GILLT_v4s16*//*Label 2771*/ GIMT_Encode4(137754), |
| 48939 | /* 137626 */ /*GILLT_v4s32*//*Label 2772*/ GIMT_Encode4(137781), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 48940 | /* 137642 */ /*GILLT_v8s16*//*Label 2773*/ GIMT_Encode4(137869), |
| 48941 | /* 137646 */ // Label 2767: @137646 |
| 48942 | /* 137646 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(137672), // Rule ID 722 // |
| 48943 | /* 137651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 48944 | /* 137654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 48945 | /* 137657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 48946 | /* 137661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 48947 | /* 137665 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 48948 | /* 137665 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH), |
| 48949 | /* 137670 */ GIR_RootConstrainSelectedInstOperands, |
| 48950 | /* 137671 */ // GIR_Coverage, 722, |
| 48951 | /* 137671 */ GIR_Done, |
| 48952 | /* 137672 */ // Label 2775: @137672 |
| 48953 | /* 137672 */ GIM_Reject, |
| 48954 | /* 137673 */ // Label 2768: @137673 |
| 48955 | /* 137673 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(137699), // Rule ID 724 // |
| 48956 | /* 137678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 48957 | /* 137681 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 48958 | /* 137684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 48959 | /* 137688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 48960 | /* 137692 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 48961 | /* 137692 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS), |
| 48962 | /* 137697 */ GIR_RootConstrainSelectedInstOperands, |
| 48963 | /* 137698 */ // GIR_Coverage, 724, |
| 48964 | /* 137698 */ GIR_Done, |
| 48965 | /* 137699 */ // Label 2776: @137699 |
| 48966 | /* 137699 */ GIM_Reject, |
| 48967 | /* 137700 */ // Label 2769: @137700 |
| 48968 | /* 137700 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(137726), // Rule ID 726 // |
| 48969 | /* 137705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 48970 | /* 137708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 48971 | /* 137711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48972 | /* 137715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48973 | /* 137719 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 48974 | /* 137719 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD), |
| 48975 | /* 137724 */ GIR_RootConstrainSelectedInstOperands, |
| 48976 | /* 137725 */ // GIR_Coverage, 726, |
| 48977 | /* 137725 */ GIR_Done, |
| 48978 | /* 137726 */ // Label 2777: @137726 |
| 48979 | /* 137726 */ GIM_Reject, |
| 48980 | /* 137727 */ // Label 2770: @137727 |
| 48981 | /* 137727 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(137753), // Rule ID 1893 // |
| 48982 | /* 137732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 48983 | /* 137735 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48984 | /* 137738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48985 | /* 137742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48986 | /* 137746 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 48987 | /* 137746 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf), |
| 48988 | /* 137751 */ GIR_RootConstrainSelectedInstOperands, |
| 48989 | /* 137752 */ // GIR_Coverage, 1893, |
| 48990 | /* 137752 */ GIR_Done, |
| 48991 | /* 137753 */ // Label 2778: @137753 |
| 48992 | /* 137753 */ GIM_Reject, |
| 48993 | /* 137754 */ // Label 2771: @137754 |
| 48994 | /* 137754 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(137780), // Rule ID 1897 // |
| 48995 | /* 137759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 48996 | /* 137762 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 48997 | /* 137765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48998 | /* 137769 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 48999 | /* 137773 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 49000 | /* 137773 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh), |
| 49001 | /* 137778 */ GIR_RootConstrainSelectedInstOperands, |
| 49002 | /* 137779 */ // GIR_Coverage, 1897, |
| 49003 | /* 137779 */ GIR_Done, |
| 49004 | /* 137780 */ // Label 2779: @137780 |
| 49005 | /* 137780 */ GIM_Reject, |
| 49006 | /* 137781 */ // Label 2772: @137781 |
| 49007 | /* 137781 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(137868), |
| 49008 | /* 137786 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 49009 | /* 137789 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(137812), // Rule ID 1895 // |
| 49010 | /* 137794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 49011 | /* 137797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49012 | /* 137801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49013 | /* 137805 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 49014 | /* 137805 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf), |
| 49015 | /* 137810 */ GIR_RootConstrainSelectedInstOperands, |
| 49016 | /* 137811 */ // GIR_Coverage, 1895, |
| 49017 | /* 137811 */ GIR_Done, |
| 49018 | /* 137812 */ // Label 2781: @137812 |
| 49019 | /* 137812 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(137867), // Rule ID 4391 // |
| 49020 | /* 137817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 49021 | /* 137820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49022 | /* 137824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49023 | /* 137828 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 49024 | /* 137828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 49025 | /* 137831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49026 | /* 137835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 49027 | /* 137840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 49028 | /* 137843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 49029 | /* 137845 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 49030 | /* 137847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49031 | /* 137850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49032 | /* 137856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49033 | /* 137862 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49034 | /* 137865 */ GIR_RootConstrainSelectedInstOperands, |
| 49035 | /* 137866 */ // GIR_Coverage, 4391, |
| 49036 | /* 137866 */ GIR_EraseRootFromParent_Done, |
| 49037 | /* 137867 */ // Label 2782: @137867 |
| 49038 | /* 137867 */ GIM_Reject, |
| 49039 | /* 137868 */ // Label 2780: @137868 |
| 49040 | /* 137868 */ GIM_Reject, |
| 49041 | /* 137869 */ // Label 2773: @137869 |
| 49042 | /* 137869 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(137956), |
| 49043 | /* 137874 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 49044 | /* 137877 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(137900), // Rule ID 1899 // |
| 49045 | /* 137882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 49046 | /* 137885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49047 | /* 137889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49048 | /* 137893 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 49049 | /* 137893 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh), |
| 49050 | /* 137898 */ GIR_RootConstrainSelectedInstOperands, |
| 49051 | /* 137899 */ // GIR_Coverage, 1899, |
| 49052 | /* 137899 */ GIR_Done, |
| 49053 | /* 137900 */ // Label 2784: @137900 |
| 49054 | /* 137900 */ GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(137955), // Rule ID 4367 // |
| 49055 | /* 137905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 49056 | /* 137908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49057 | /* 137912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49058 | /* 137916 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 49059 | /* 137916 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 49060 | /* 137919 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49061 | /* 137923 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 49062 | /* 137928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 49063 | /* 137931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 49064 | /* 137933 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 49065 | /* 137935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49066 | /* 137938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49067 | /* 137944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49068 | /* 137950 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49069 | /* 137953 */ GIR_RootConstrainSelectedInstOperands, |
| 49070 | /* 137954 */ // GIR_Coverage, 4367, |
| 49071 | /* 137954 */ GIR_EraseRootFromParent_Done, |
| 49072 | /* 137955 */ // Label 2785: @137955 |
| 49073 | /* 137955 */ GIM_Reject, |
| 49074 | /* 137956 */ // Label 2783: @137956 |
| 49075 | /* 137956 */ GIM_Reject, |
| 49076 | /* 137957 */ // Label 2774: @137957 |
| 49077 | /* 137957 */ GIM_Reject, |
| 49078 | /* 137958 */ // Label 75: @137958 |
| 49079 | /* 137958 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2789*/ GIMT_Encode4(138095), |
| 49080 | /* 137969 */ /*GILLT_s16*//*Label 2786*/ GIMT_Encode4(137981), |
| 49081 | /* 137973 */ /*GILLT_s32*//*Label 2787*/ GIMT_Encode4(138019), |
| 49082 | /* 137977 */ /*GILLT_s64*//*Label 2788*/ GIMT_Encode4(138057), |
| 49083 | /* 137981 */ // Label 2786: @137981 |
| 49084 | /* 137981 */ GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(138018), // Rule ID 738 // |
| 49085 | /* 137986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49086 | /* 137989 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49087 | /* 137992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49088 | /* 137996 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49089 | /* 138000 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 49090 | /* 138000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 49091 | /* 138003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49092 | /* 138005 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49093 | /* 138007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49094 | /* 138010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49095 | /* 138016 */ GIR_RootConstrainSelectedInstOperands, |
| 49096 | /* 138017 */ // GIR_Coverage, 738, |
| 49097 | /* 138017 */ GIR_EraseRootFromParent_Done, |
| 49098 | /* 138018 */ // Label 2790: @138018 |
| 49099 | /* 138018 */ GIM_Reject, |
| 49100 | /* 138019 */ // Label 2787: @138019 |
| 49101 | /* 138019 */ GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(138056), // Rule ID 736 // |
| 49102 | /* 138024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 49103 | /* 138027 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49104 | /* 138030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49105 | /* 138034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49106 | /* 138038 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 49107 | /* 138038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 49108 | /* 138041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49109 | /* 138043 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49110 | /* 138045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49111 | /* 138048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49112 | /* 138054 */ GIR_RootConstrainSelectedInstOperands, |
| 49113 | /* 138055 */ // GIR_Coverage, 736, |
| 49114 | /* 138055 */ GIR_EraseRootFromParent_Done, |
| 49115 | /* 138056 */ // Label 2791: @138056 |
| 49116 | /* 138056 */ GIM_Reject, |
| 49117 | /* 138057 */ // Label 2788: @138057 |
| 49118 | /* 138057 */ GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(138094), // Rule ID 734 // |
| 49119 | /* 138062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 49120 | /* 138065 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49121 | /* 138068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49122 | /* 138072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49123 | /* 138076 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 49124 | /* 138076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 49125 | /* 138079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 49126 | /* 138081 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 49127 | /* 138083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49128 | /* 138086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49129 | /* 138092 */ GIR_RootConstrainSelectedInstOperands, |
| 49130 | /* 138093 */ // GIR_Coverage, 734, |
| 49131 | /* 138093 */ GIR_EraseRootFromParent_Done, |
| 49132 | /* 138094 */ // Label 2792: @138094 |
| 49133 | /* 138094 */ GIM_Reject, |
| 49134 | /* 138095 */ // Label 2789: @138095 |
| 49135 | /* 138095 */ GIM_Reject, |
| 49136 | /* 138096 */ // Label 76: @138096 |
| 49137 | /* 138096 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2800*/ GIMT_Encode4(138470), |
| 49138 | /* 138107 */ /*GILLT_s16*//*Label 2793*/ GIMT_Encode4(138159), |
| 49139 | /* 138111 */ /*GILLT_s32*//*Label 2794*/ GIMT_Encode4(138186), |
| 49140 | /* 138115 */ /*GILLT_s64*//*Label 2795*/ GIMT_Encode4(138213), GIMT_Encode4(0), |
| 49141 | /* 138123 */ /*GILLT_v2s32*//*Label 2796*/ GIMT_Encode4(138240), GIMT_Encode4(0), GIMT_Encode4(0), |
| 49142 | /* 138135 */ /*GILLT_v4s16*//*Label 2797*/ GIMT_Encode4(138267), |
| 49143 | /* 138139 */ /*GILLT_v4s32*//*Label 2798*/ GIMT_Encode4(138294), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 49144 | /* 138155 */ /*GILLT_v8s16*//*Label 2799*/ GIMT_Encode4(138382), |
| 49145 | /* 138159 */ // Label 2793: @138159 |
| 49146 | /* 138159 */ GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(138185), // Rule ID 728 // |
| 49147 | /* 138164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49148 | /* 138167 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49149 | /* 138170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49150 | /* 138174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49151 | /* 138178 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 49152 | /* 138178 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH), |
| 49153 | /* 138183 */ GIR_RootConstrainSelectedInstOperands, |
| 49154 | /* 138184 */ // GIR_Coverage, 728, |
| 49155 | /* 138184 */ GIR_Done, |
| 49156 | /* 138185 */ // Label 2801: @138185 |
| 49157 | /* 138185 */ GIM_Reject, |
| 49158 | /* 138186 */ // Label 2794: @138186 |
| 49159 | /* 138186 */ GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(138212), // Rule ID 730 // |
| 49160 | /* 138191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 49161 | /* 138194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49162 | /* 138197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49163 | /* 138201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49164 | /* 138205 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 49165 | /* 138205 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS), |
| 49166 | /* 138210 */ GIR_RootConstrainSelectedInstOperands, |
| 49167 | /* 138211 */ // GIR_Coverage, 730, |
| 49168 | /* 138211 */ GIR_Done, |
| 49169 | /* 138212 */ // Label 2802: @138212 |
| 49170 | /* 138212 */ GIM_Reject, |
| 49171 | /* 138213 */ // Label 2795: @138213 |
| 49172 | /* 138213 */ GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(138239), // Rule ID 732 // |
| 49173 | /* 138218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 49174 | /* 138221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49175 | /* 138224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49176 | /* 138228 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49177 | /* 138232 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 49178 | /* 138232 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD), |
| 49179 | /* 138237 */ GIR_RootConstrainSelectedInstOperands, |
| 49180 | /* 138238 */ // GIR_Coverage, 732, |
| 49181 | /* 138238 */ GIR_Done, |
| 49182 | /* 138239 */ // Label 2803: @138239 |
| 49183 | /* 138239 */ GIM_Reject, |
| 49184 | /* 138240 */ // Label 2796: @138240 |
| 49185 | /* 138240 */ GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(138266), // Rule ID 1885 // |
| 49186 | /* 138245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 49187 | /* 138248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 49188 | /* 138251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49189 | /* 138255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49190 | /* 138259 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 49191 | /* 138259 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf), |
| 49192 | /* 138264 */ GIR_RootConstrainSelectedInstOperands, |
| 49193 | /* 138265 */ // GIR_Coverage, 1885, |
| 49194 | /* 138265 */ GIR_Done, |
| 49195 | /* 138266 */ // Label 2804: @138266 |
| 49196 | /* 138266 */ GIM_Reject, |
| 49197 | /* 138267 */ // Label 2797: @138267 |
| 49198 | /* 138267 */ GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(138293), // Rule ID 1889 // |
| 49199 | /* 138272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 49200 | /* 138275 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 49201 | /* 138278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49202 | /* 138282 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49203 | /* 138286 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 49204 | /* 138286 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh), |
| 49205 | /* 138291 */ GIR_RootConstrainSelectedInstOperands, |
| 49206 | /* 138292 */ // GIR_Coverage, 1889, |
| 49207 | /* 138292 */ GIR_Done, |
| 49208 | /* 138293 */ // Label 2805: @138293 |
| 49209 | /* 138293 */ GIM_Reject, |
| 49210 | /* 138294 */ // Label 2798: @138294 |
| 49211 | /* 138294 */ GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(138381), |
| 49212 | /* 138299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 49213 | /* 138302 */ GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(138325), // Rule ID 1887 // |
| 49214 | /* 138307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 49215 | /* 138310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49216 | /* 138314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49217 | /* 138318 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 49218 | /* 138318 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf), |
| 49219 | /* 138323 */ GIR_RootConstrainSelectedInstOperands, |
| 49220 | /* 138324 */ // GIR_Coverage, 1887, |
| 49221 | /* 138324 */ GIR_Done, |
| 49222 | /* 138325 */ // Label 2807: @138325 |
| 49223 | /* 138325 */ GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(138380), // Rule ID 4387 // |
| 49224 | /* 138330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 49225 | /* 138333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49226 | /* 138337 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49227 | /* 138341 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 49228 | /* 138341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 49229 | /* 138344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49230 | /* 138348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 49231 | /* 138353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 49232 | /* 138356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 49233 | /* 138358 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 49234 | /* 138360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49235 | /* 138363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49236 | /* 138369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49237 | /* 138375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49238 | /* 138378 */ GIR_RootConstrainSelectedInstOperands, |
| 49239 | /* 138379 */ // GIR_Coverage, 4387, |
| 49240 | /* 138379 */ GIR_EraseRootFromParent_Done, |
| 49241 | /* 138380 */ // Label 2808: @138380 |
| 49242 | /* 138380 */ GIM_Reject, |
| 49243 | /* 138381 */ // Label 2806: @138381 |
| 49244 | /* 138381 */ GIM_Reject, |
| 49245 | /* 138382 */ // Label 2799: @138382 |
| 49246 | /* 138382 */ GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(138469), |
| 49247 | /* 138387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 49248 | /* 138390 */ GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(138413), // Rule ID 1891 // |
| 49249 | /* 138395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 49250 | /* 138398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49251 | /* 138402 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49252 | /* 138406 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 49253 | /* 138406 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh), |
| 49254 | /* 138411 */ GIR_RootConstrainSelectedInstOperands, |
| 49255 | /* 138412 */ // GIR_Coverage, 1891, |
| 49256 | /* 138412 */ GIR_Done, |
| 49257 | /* 138413 */ // Label 2810: @138413 |
| 49258 | /* 138413 */ GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(138468), // Rule ID 4363 // |
| 49259 | /* 138418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 49260 | /* 138421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49261 | /* 138425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49262 | /* 138429 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 49263 | /* 138429 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 49264 | /* 138432 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49265 | /* 138436 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 49266 | /* 138441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 49267 | /* 138444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 49268 | /* 138446 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 49269 | /* 138448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49270 | /* 138451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49271 | /* 138457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49272 | /* 138463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49273 | /* 138466 */ GIR_RootConstrainSelectedInstOperands, |
| 49274 | /* 138467 */ // GIR_Coverage, 4363, |
| 49275 | /* 138467 */ GIR_EraseRootFromParent_Done, |
| 49276 | /* 138468 */ // Label 2811: @138468 |
| 49277 | /* 138468 */ GIM_Reject, |
| 49278 | /* 138469 */ // Label 2809: @138469 |
| 49279 | /* 138469 */ GIM_Reject, |
| 49280 | /* 138470 */ // Label 2800: @138470 |
| 49281 | /* 138470 */ GIM_Reject, |
| 49282 | /* 138471 */ // Label 77: @138471 |
| 49283 | /* 138471 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2819*/ GIMT_Encode4(138878), |
| 49284 | /* 138482 */ /*GILLT_s16*//*Label 2812*/ GIMT_Encode4(138534), |
| 49285 | /* 138486 */ /*GILLT_s32*//*Label 2813*/ GIMT_Encode4(138572), |
| 49286 | /* 138490 */ /*GILLT_s64*//*Label 2814*/ GIMT_Encode4(138610), GIMT_Encode4(0), |
| 49287 | /* 138498 */ /*GILLT_v2s32*//*Label 2815*/ GIMT_Encode4(138648), GIMT_Encode4(0), GIMT_Encode4(0), |
| 49288 | /* 138510 */ /*GILLT_v4s16*//*Label 2816*/ GIMT_Encode4(138675), |
| 49289 | /* 138514 */ /*GILLT_v4s32*//*Label 2817*/ GIMT_Encode4(138702), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 49290 | /* 138530 */ /*GILLT_v8s16*//*Label 2818*/ GIMT_Encode4(138790), |
| 49291 | /* 138534 */ // Label 2812: @138534 |
| 49292 | /* 138534 */ GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(138571), // Rule ID 704 // |
| 49293 | /* 138539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49294 | /* 138542 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49295 | /* 138545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49296 | /* 138549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49297 | /* 138553 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 49298 | /* 138553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH), |
| 49299 | /* 138556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49300 | /* 138558 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49301 | /* 138560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49302 | /* 138563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49303 | /* 138569 */ GIR_RootConstrainSelectedInstOperands, |
| 49304 | /* 138570 */ // GIR_Coverage, 704, |
| 49305 | /* 138570 */ GIR_EraseRootFromParent_Done, |
| 49306 | /* 138571 */ // Label 2820: @138571 |
| 49307 | /* 138571 */ GIM_Reject, |
| 49308 | /* 138572 */ // Label 2813: @138572 |
| 49309 | /* 138572 */ GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(138609), // Rule ID 706 // |
| 49310 | /* 138577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 49311 | /* 138580 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49312 | /* 138583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49313 | /* 138587 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49314 | /* 138591 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 49315 | /* 138591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS), |
| 49316 | /* 138594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49317 | /* 138596 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49318 | /* 138598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49319 | /* 138601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49320 | /* 138607 */ GIR_RootConstrainSelectedInstOperands, |
| 49321 | /* 138608 */ // GIR_Coverage, 706, |
| 49322 | /* 138608 */ GIR_EraseRootFromParent_Done, |
| 49323 | /* 138609 */ // Label 2821: @138609 |
| 49324 | /* 138609 */ GIM_Reject, |
| 49325 | /* 138610 */ // Label 2814: @138610 |
| 49326 | /* 138610 */ GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(138647), // Rule ID 708 // |
| 49327 | /* 138615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 49328 | /* 138618 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49329 | /* 138621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49330 | /* 138625 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49331 | /* 138629 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 49332 | /* 138629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD), |
| 49333 | /* 138632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 49334 | /* 138634 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 49335 | /* 138636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49336 | /* 138639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49337 | /* 138645 */ GIR_RootConstrainSelectedInstOperands, |
| 49338 | /* 138646 */ // GIR_Coverage, 708, |
| 49339 | /* 138646 */ GIR_EraseRootFromParent_Done, |
| 49340 | /* 138647 */ // Label 2822: @138647 |
| 49341 | /* 138647 */ GIM_Reject, |
| 49342 | /* 138648 */ // Label 2815: @138648 |
| 49343 | /* 138648 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(138674), // Rule ID 1861 // |
| 49344 | /* 138653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 49345 | /* 138656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 49346 | /* 138659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49347 | /* 138663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49348 | /* 138667 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 49349 | /* 138667 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf), |
| 49350 | /* 138672 */ GIR_RootConstrainSelectedInstOperands, |
| 49351 | /* 138673 */ // GIR_Coverage, 1861, |
| 49352 | /* 138673 */ GIR_Done, |
| 49353 | /* 138674 */ // Label 2823: @138674 |
| 49354 | /* 138674 */ GIM_Reject, |
| 49355 | /* 138675 */ // Label 2816: @138675 |
| 49356 | /* 138675 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(138701), // Rule ID 1865 // |
| 49357 | /* 138680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 49358 | /* 138683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 49359 | /* 138686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49360 | /* 138690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49361 | /* 138694 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 49362 | /* 138694 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh), |
| 49363 | /* 138699 */ GIR_RootConstrainSelectedInstOperands, |
| 49364 | /* 138700 */ // GIR_Coverage, 1865, |
| 49365 | /* 138700 */ GIR_Done, |
| 49366 | /* 138701 */ // Label 2824: @138701 |
| 49367 | /* 138701 */ GIM_Reject, |
| 49368 | /* 138702 */ // Label 2817: @138702 |
| 49369 | /* 138702 */ GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(138789), |
| 49370 | /* 138707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 49371 | /* 138710 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(138733), // Rule ID 1863 // |
| 49372 | /* 138715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 49373 | /* 138718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49374 | /* 138722 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49375 | /* 138726 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 49376 | /* 138726 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf), |
| 49377 | /* 138731 */ GIR_RootConstrainSelectedInstOperands, |
| 49378 | /* 138732 */ // GIR_Coverage, 1863, |
| 49379 | /* 138732 */ GIR_Done, |
| 49380 | /* 138733 */ // Label 2826: @138733 |
| 49381 | /* 138733 */ GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(138788), // Rule ID 4375 // |
| 49382 | /* 138738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 49383 | /* 138741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49384 | /* 138745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49385 | /* 138749 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 49386 | /* 138749 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 49387 | /* 138752 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49388 | /* 138756 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 49389 | /* 138761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 49390 | /* 138764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 49391 | /* 138766 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 49392 | /* 138768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49393 | /* 138771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49394 | /* 138777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49395 | /* 138783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49396 | /* 138786 */ GIR_RootConstrainSelectedInstOperands, |
| 49397 | /* 138787 */ // GIR_Coverage, 4375, |
| 49398 | /* 138787 */ GIR_EraseRootFromParent_Done, |
| 49399 | /* 138788 */ // Label 2827: @138788 |
| 49400 | /* 138788 */ GIM_Reject, |
| 49401 | /* 138789 */ // Label 2825: @138789 |
| 49402 | /* 138789 */ GIM_Reject, |
| 49403 | /* 138790 */ // Label 2818: @138790 |
| 49404 | /* 138790 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(138877), |
| 49405 | /* 138795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 49406 | /* 138798 */ GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(138821), // Rule ID 1867 // |
| 49407 | /* 138803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 49408 | /* 138806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49409 | /* 138810 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 49410 | /* 138814 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 49411 | /* 138814 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh), |
| 49412 | /* 138819 */ GIR_RootConstrainSelectedInstOperands, |
| 49413 | /* 138820 */ // GIR_Coverage, 1867, |
| 49414 | /* 138820 */ GIR_Done, |
| 49415 | /* 138821 */ // Label 2829: @138821 |
| 49416 | /* 138821 */ GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(138876), // Rule ID 4351 // |
| 49417 | /* 138826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 49418 | /* 138829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49419 | /* 138833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 49420 | /* 138837 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 49421 | /* 138837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 49422 | /* 138840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49423 | /* 138844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 49424 | /* 138849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 49425 | /* 138852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 49426 | /* 138854 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 49427 | /* 138856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49428 | /* 138859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49429 | /* 138865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49430 | /* 138871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49431 | /* 138874 */ GIR_RootConstrainSelectedInstOperands, |
| 49432 | /* 138875 */ // GIR_Coverage, 4351, |
| 49433 | /* 138875 */ GIR_EraseRootFromParent_Done, |
| 49434 | /* 138876 */ // Label 2830: @138876 |
| 49435 | /* 138876 */ GIM_Reject, |
| 49436 | /* 138877 */ // Label 2828: @138877 |
| 49437 | /* 138877 */ GIM_Reject, |
| 49438 | /* 138878 */ // Label 2819: @138878 |
| 49439 | /* 138878 */ GIM_Reject, |
| 49440 | /* 138879 */ // Label 78: @138879 |
| 49441 | /* 138879 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2834*/ GIMT_Encode4(139016), |
| 49442 | /* 138890 */ /*GILLT_s16*//*Label 2831*/ GIMT_Encode4(138902), |
| 49443 | /* 138894 */ /*GILLT_s32*//*Label 2832*/ GIMT_Encode4(138940), |
| 49444 | /* 138898 */ /*GILLT_s64*//*Label 2833*/ GIMT_Encode4(138978), |
| 49445 | /* 138902 */ // Label 2831: @138902 |
| 49446 | /* 138902 */ GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(138939), // Rule ID 698 // |
| 49447 | /* 138907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49448 | /* 138910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49449 | /* 138913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49450 | /* 138917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49451 | /* 138921 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 49452 | /* 138921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH), |
| 49453 | /* 138924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49454 | /* 138926 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49455 | /* 138928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49456 | /* 138931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49457 | /* 138937 */ GIR_RootConstrainSelectedInstOperands, |
| 49458 | /* 138938 */ // GIR_Coverage, 698, |
| 49459 | /* 138938 */ GIR_EraseRootFromParent_Done, |
| 49460 | /* 138939 */ // Label 2835: @138939 |
| 49461 | /* 138939 */ GIM_Reject, |
| 49462 | /* 138940 */ // Label 2832: @138940 |
| 49463 | /* 138940 */ GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(138977), // Rule ID 700 // |
| 49464 | /* 138945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 49465 | /* 138948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49466 | /* 138951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49467 | /* 138955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49468 | /* 138959 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 49469 | /* 138959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS), |
| 49470 | /* 138962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49471 | /* 138964 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49472 | /* 138966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49473 | /* 138969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49474 | /* 138975 */ GIR_RootConstrainSelectedInstOperands, |
| 49475 | /* 138976 */ // GIR_Coverage, 700, |
| 49476 | /* 138976 */ GIR_EraseRootFromParent_Done, |
| 49477 | /* 138977 */ // Label 2836: @138977 |
| 49478 | /* 138977 */ GIM_Reject, |
| 49479 | /* 138978 */ // Label 2833: @138978 |
| 49480 | /* 138978 */ GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(139015), // Rule ID 702 // |
| 49481 | /* 138983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 49482 | /* 138986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49483 | /* 138989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49484 | /* 138993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49485 | /* 138997 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 49486 | /* 138997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD), |
| 49487 | /* 139000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 49488 | /* 139002 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 49489 | /* 139004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49490 | /* 139007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49491 | /* 139013 */ GIR_RootConstrainSelectedInstOperands, |
| 49492 | /* 139014 */ // GIR_Coverage, 702, |
| 49493 | /* 139014 */ GIR_EraseRootFromParent_Done, |
| 49494 | /* 139015 */ // Label 2837: @139015 |
| 49495 | /* 139015 */ GIM_Reject, |
| 49496 | /* 139016 */ // Label 2834: @139016 |
| 49497 | /* 139016 */ GIM_Reject, |
| 49498 | /* 139017 */ // Label 79: @139017 |
| 49499 | /* 139017 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2841*/ GIMT_Encode4(139181), |
| 49500 | /* 139028 */ /*GILLT_s16*//*Label 2838*/ GIMT_Encode4(139040), |
| 49501 | /* 139032 */ /*GILLT_s32*//*Label 2839*/ GIMT_Encode4(139087), |
| 49502 | /* 139036 */ /*GILLT_s64*//*Label 2840*/ GIMT_Encode4(139134), |
| 49503 | /* 139040 */ // Label 2838: @139040 |
| 49504 | /* 139040 */ GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(139086), // Rule ID 619 // |
| 49505 | /* 139045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49506 | /* 139048 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49507 | /* 139051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 49508 | /* 139054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49509 | /* 139058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49510 | /* 139062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49511 | /* 139066 */ // (strict_fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49512 | /* 139066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 49513 | /* 139069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49514 | /* 139071 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49515 | /* 139073 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49516 | /* 139075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49517 | /* 139078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49518 | /* 139084 */ GIR_RootConstrainSelectedInstOperands, |
| 49519 | /* 139085 */ // GIR_Coverage, 619, |
| 49520 | /* 139085 */ GIR_EraseRootFromParent_Done, |
| 49521 | /* 139086 */ // Label 2842: @139086 |
| 49522 | /* 139086 */ GIM_Reject, |
| 49523 | /* 139087 */ // Label 2839: @139087 |
| 49524 | /* 139087 */ GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(139133), // Rule ID 617 // |
| 49525 | /* 139092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 49526 | /* 139095 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49527 | /* 139098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49528 | /* 139101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49529 | /* 139105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49530 | /* 139109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49531 | /* 139113 */ // (strict_fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49532 | /* 139113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 49533 | /* 139116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49534 | /* 139118 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49535 | /* 139120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49536 | /* 139122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49537 | /* 139125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49538 | /* 139131 */ GIR_RootConstrainSelectedInstOperands, |
| 49539 | /* 139132 */ // GIR_Coverage, 617, |
| 49540 | /* 139132 */ GIR_EraseRootFromParent_Done, |
| 49541 | /* 139133 */ // Label 2843: @139133 |
| 49542 | /* 139133 */ GIM_Reject, |
| 49543 | /* 139134 */ // Label 2840: @139134 |
| 49544 | /* 139134 */ GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(139180), // Rule ID 615 // |
| 49545 | /* 139139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 49546 | /* 139142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49547 | /* 139145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 49548 | /* 139148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49549 | /* 139152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49550 | /* 139156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49551 | /* 139160 */ // (strict_fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 49552 | /* 139160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 49553 | /* 139163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 49554 | /* 139165 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 49555 | /* 139167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 49556 | /* 139169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49557 | /* 139172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49558 | /* 139178 */ GIR_RootConstrainSelectedInstOperands, |
| 49559 | /* 139179 */ // GIR_Coverage, 615, |
| 49560 | /* 139179 */ GIR_EraseRootFromParent_Done, |
| 49561 | /* 139180 */ // Label 2844: @139180 |
| 49562 | /* 139180 */ GIM_Reject, |
| 49563 | /* 139181 */ // Label 2841: @139181 |
| 49564 | /* 139181 */ GIM_Reject, |
| 49565 | /* 139182 */ // Label 80: @139182 |
| 49566 | /* 139182 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2848*/ GIMT_Encode4(139346), |
| 49567 | /* 139193 */ /*GILLT_s16*//*Label 2845*/ GIMT_Encode4(139205), |
| 49568 | /* 139197 */ /*GILLT_s32*//*Label 2846*/ GIMT_Encode4(139252), |
| 49569 | /* 139201 */ /*GILLT_s64*//*Label 2847*/ GIMT_Encode4(139299), |
| 49570 | /* 139205 */ // Label 2845: @139205 |
| 49571 | /* 139205 */ GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(139251), // Rule ID 625 // |
| 49572 | /* 139210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49573 | /* 139213 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49574 | /* 139216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 49575 | /* 139219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49576 | /* 139223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49577 | /* 139227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49578 | /* 139231 */ // (strict_fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49579 | /* 139231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 49580 | /* 139234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49581 | /* 139236 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49582 | /* 139238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49583 | /* 139240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49584 | /* 139243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49585 | /* 139249 */ GIR_RootConstrainSelectedInstOperands, |
| 49586 | /* 139250 */ // GIR_Coverage, 625, |
| 49587 | /* 139250 */ GIR_EraseRootFromParent_Done, |
| 49588 | /* 139251 */ // Label 2849: @139251 |
| 49589 | /* 139251 */ GIM_Reject, |
| 49590 | /* 139252 */ // Label 2846: @139252 |
| 49591 | /* 139252 */ GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(139298), // Rule ID 623 // |
| 49592 | /* 139257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 49593 | /* 139260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49594 | /* 139263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49595 | /* 139266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49596 | /* 139270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49597 | /* 139274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49598 | /* 139278 */ // (strict_fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49599 | /* 139278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 49600 | /* 139281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49601 | /* 139283 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49602 | /* 139285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49603 | /* 139287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49604 | /* 139290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49605 | /* 139296 */ GIR_RootConstrainSelectedInstOperands, |
| 49606 | /* 139297 */ // GIR_Coverage, 623, |
| 49607 | /* 139297 */ GIR_EraseRootFromParent_Done, |
| 49608 | /* 139298 */ // Label 2850: @139298 |
| 49609 | /* 139298 */ GIM_Reject, |
| 49610 | /* 139299 */ // Label 2847: @139299 |
| 49611 | /* 139299 */ GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(139345), // Rule ID 621 // |
| 49612 | /* 139304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 49613 | /* 139307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49614 | /* 139310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 49615 | /* 139313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49616 | /* 139317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49617 | /* 139321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49618 | /* 139325 */ // (strict_fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 49619 | /* 139325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 49620 | /* 139328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 49621 | /* 139330 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 49622 | /* 139332 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 49623 | /* 139334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49624 | /* 139337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49625 | /* 139343 */ GIR_RootConstrainSelectedInstOperands, |
| 49626 | /* 139344 */ // GIR_Coverage, 621, |
| 49627 | /* 139344 */ GIR_EraseRootFromParent_Done, |
| 49628 | /* 139345 */ // Label 2851: @139345 |
| 49629 | /* 139345 */ GIM_Reject, |
| 49630 | /* 139346 */ // Label 2848: @139346 |
| 49631 | /* 139346 */ GIM_Reject, |
| 49632 | /* 139347 */ // Label 81: @139347 |
| 49633 | /* 139347 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2855*/ GIMT_Encode4(139511), |
| 49634 | /* 139358 */ /*GILLT_s16*//*Label 2852*/ GIMT_Encode4(139370), |
| 49635 | /* 139362 */ /*GILLT_s32*//*Label 2853*/ GIMT_Encode4(139417), |
| 49636 | /* 139366 */ /*GILLT_s64*//*Label 2854*/ GIMT_Encode4(139464), |
| 49637 | /* 139370 */ // Label 2852: @139370 |
| 49638 | /* 139370 */ GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(139416), // Rule ID 637 // |
| 49639 | /* 139375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49640 | /* 139378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49641 | /* 139381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 49642 | /* 139384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49643 | /* 139388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49644 | /* 139392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49645 | /* 139396 */ // (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49646 | /* 139396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 49647 | /* 139399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49648 | /* 139401 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49649 | /* 139403 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49650 | /* 139405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49651 | /* 139408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49652 | /* 139414 */ GIR_RootConstrainSelectedInstOperands, |
| 49653 | /* 139415 */ // GIR_Coverage, 637, |
| 49654 | /* 139415 */ GIR_EraseRootFromParent_Done, |
| 49655 | /* 139416 */ // Label 2856: @139416 |
| 49656 | /* 139416 */ GIM_Reject, |
| 49657 | /* 139417 */ // Label 2853: @139417 |
| 49658 | /* 139417 */ GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(139463), // Rule ID 635 // |
| 49659 | /* 139422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 49660 | /* 139425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49661 | /* 139428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49662 | /* 139431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49663 | /* 139435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49664 | /* 139439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49665 | /* 139443 */ // (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49666 | /* 139443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 49667 | /* 139446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49668 | /* 139448 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49669 | /* 139450 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49670 | /* 139452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49671 | /* 139455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49672 | /* 139461 */ GIR_RootConstrainSelectedInstOperands, |
| 49673 | /* 139462 */ // GIR_Coverage, 635, |
| 49674 | /* 139462 */ GIR_EraseRootFromParent_Done, |
| 49675 | /* 139463 */ // Label 2857: @139463 |
| 49676 | /* 139463 */ GIM_Reject, |
| 49677 | /* 139464 */ // Label 2854: @139464 |
| 49678 | /* 139464 */ GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(139510), // Rule ID 633 // |
| 49679 | /* 139469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 49680 | /* 139472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49681 | /* 139475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 49682 | /* 139478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49683 | /* 139482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49684 | /* 139486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49685 | /* 139490 */ // (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 49686 | /* 139490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 49687 | /* 139493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 49688 | /* 139495 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 49689 | /* 139497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 49690 | /* 139499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49691 | /* 139502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49692 | /* 139508 */ GIR_RootConstrainSelectedInstOperands, |
| 49693 | /* 139509 */ // GIR_Coverage, 633, |
| 49694 | /* 139509 */ GIR_EraseRootFromParent_Done, |
| 49695 | /* 139510 */ // Label 2858: @139510 |
| 49696 | /* 139510 */ GIM_Reject, |
| 49697 | /* 139511 */ // Label 2855: @139511 |
| 49698 | /* 139511 */ GIM_Reject, |
| 49699 | /* 139512 */ // Label 82: @139512 |
| 49700 | /* 139512 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2862*/ GIMT_Encode4(139676), |
| 49701 | /* 139523 */ /*GILLT_s16*//*Label 2859*/ GIMT_Encode4(139535), |
| 49702 | /* 139527 */ /*GILLT_s32*//*Label 2860*/ GIMT_Encode4(139582), |
| 49703 | /* 139531 */ /*GILLT_s64*//*Label 2861*/ GIMT_Encode4(139629), |
| 49704 | /* 139535 */ // Label 2859: @139535 |
| 49705 | /* 139535 */ GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(139581), // Rule ID 631 // |
| 49706 | /* 139540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49707 | /* 139543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49708 | /* 139546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 49709 | /* 139549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49710 | /* 139553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49711 | /* 139557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49712 | /* 139561 */ // (strict_fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49713 | /* 139561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 49714 | /* 139564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49715 | /* 139566 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49716 | /* 139568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49717 | /* 139570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49718 | /* 139573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49719 | /* 139579 */ GIR_RootConstrainSelectedInstOperands, |
| 49720 | /* 139580 */ // GIR_Coverage, 631, |
| 49721 | /* 139580 */ GIR_EraseRootFromParent_Done, |
| 49722 | /* 139581 */ // Label 2863: @139581 |
| 49723 | /* 139581 */ GIM_Reject, |
| 49724 | /* 139582 */ // Label 2860: @139582 |
| 49725 | /* 139582 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(139628), // Rule ID 629 // |
| 49726 | /* 139587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 49727 | /* 139590 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49728 | /* 139593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49729 | /* 139596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49730 | /* 139600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49731 | /* 139604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49732 | /* 139608 */ // (strict_fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49733 | /* 139608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 49734 | /* 139611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49735 | /* 139613 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49736 | /* 139615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49737 | /* 139617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49738 | /* 139620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49739 | /* 139626 */ GIR_RootConstrainSelectedInstOperands, |
| 49740 | /* 139627 */ // GIR_Coverage, 629, |
| 49741 | /* 139627 */ GIR_EraseRootFromParent_Done, |
| 49742 | /* 139628 */ // Label 2864: @139628 |
| 49743 | /* 139628 */ GIM_Reject, |
| 49744 | /* 139629 */ // Label 2861: @139629 |
| 49745 | /* 139629 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(139675), // Rule ID 627 // |
| 49746 | /* 139634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 49747 | /* 139637 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49748 | /* 139640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 49749 | /* 139643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49750 | /* 139647 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49751 | /* 139651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 49752 | /* 139655 */ // (strict_fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 49753 | /* 139655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 49754 | /* 139658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 49755 | /* 139660 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 49756 | /* 139662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 49757 | /* 139664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49758 | /* 139667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49759 | /* 139673 */ GIR_RootConstrainSelectedInstOperands, |
| 49760 | /* 139674 */ // GIR_Coverage, 627, |
| 49761 | /* 139674 */ GIR_EraseRootFromParent_Done, |
| 49762 | /* 139675 */ // Label 2865: @139675 |
| 49763 | /* 139675 */ GIM_Reject, |
| 49764 | /* 139676 */ // Label 2862: @139676 |
| 49765 | /* 139676 */ GIM_Reject, |
| 49766 | /* 139677 */ // Label 83: @139677 |
| 49767 | /* 139677 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2869*/ GIMT_Encode4(140861), |
| 49768 | /* 139688 */ /*GILLT_s16*//*Label 2866*/ GIMT_Encode4(139700), |
| 49769 | /* 139692 */ /*GILLT_s32*//*Label 2867*/ GIMT_Encode4(140087), |
| 49770 | /* 139696 */ /*GILLT_s64*//*Label 2868*/ GIMT_Encode4(140474), |
| 49771 | /* 139700 */ // Label 2866: @139700 |
| 49772 | /* 139700 */ GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(140086), |
| 49773 | /* 139705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 49774 | /* 139708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 49775 | /* 139711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 49776 | /* 139714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49777 | /* 139718 */ GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(139792), // Rule ID 2759 // |
| 49778 | /* 139723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49779 | /* 139726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 49780 | /* 139730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49781 | /* 139734 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 49782 | /* 139738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49783 | /* 139743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49784 | /* 139747 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 49785 | /* 139751 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49786 | /* 139755 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 49787 | /* 139759 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49788 | /* 139764 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 49789 | /* 139766 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49790 | /* 139766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 49791 | /* 139769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49792 | /* 139771 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 49793 | /* 139775 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49794 | /* 139779 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49795 | /* 139781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49796 | /* 139784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49797 | /* 139790 */ GIR_RootConstrainSelectedInstOperands, |
| 49798 | /* 139791 */ // GIR_Coverage, 2759, |
| 49799 | /* 139791 */ GIR_EraseRootFromParent_Done, |
| 49800 | /* 139792 */ // Label 2871: @139792 |
| 49801 | /* 139792 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(139866), // Rule ID 6310 // |
| 49802 | /* 139797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49803 | /* 139800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49804 | /* 139804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49805 | /* 139808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49806 | /* 139812 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 49807 | /* 139816 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49808 | /* 139821 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 49809 | /* 139825 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49810 | /* 139829 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 49811 | /* 139833 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49812 | /* 139838 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 49813 | /* 139840 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49814 | /* 139840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 49815 | /* 139843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49816 | /* 139845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 49817 | /* 139849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49818 | /* 139853 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49819 | /* 139855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49820 | /* 139858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49821 | /* 139864 */ GIR_RootConstrainSelectedInstOperands, |
| 49822 | /* 139865 */ // GIR_Coverage, 6310, |
| 49823 | /* 139865 */ GIR_EraseRootFromParent_Done, |
| 49824 | /* 139866 */ // Label 2872: @139866 |
| 49825 | /* 139866 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(139925), // Rule ID 2739 // |
| 49826 | /* 139871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49827 | /* 139874 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 49828 | /* 139878 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49829 | /* 139882 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 49830 | /* 139886 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49831 | /* 139891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49832 | /* 139895 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49833 | /* 139899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49834 | /* 139901 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49835 | /* 139901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 49836 | /* 139904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49837 | /* 139906 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 49838 | /* 139908 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49839 | /* 139912 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49840 | /* 139914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49841 | /* 139917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49842 | /* 139923 */ GIR_RootConstrainSelectedInstOperands, |
| 49843 | /* 139924 */ // GIR_Coverage, 2739, |
| 49844 | /* 139924 */ GIR_EraseRootFromParent_Done, |
| 49845 | /* 139925 */ // Label 2873: @139925 |
| 49846 | /* 139925 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(139984), // Rule ID 6304 // |
| 49847 | /* 139930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49848 | /* 139933 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49849 | /* 139937 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49850 | /* 139941 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49851 | /* 139945 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 49852 | /* 139949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49853 | /* 139954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49854 | /* 139958 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49855 | /* 139960 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49856 | /* 139960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 49857 | /* 139963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49858 | /* 139965 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 49859 | /* 139967 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49860 | /* 139971 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49861 | /* 139973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49862 | /* 139976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49863 | /* 139982 */ GIR_RootConstrainSelectedInstOperands, |
| 49864 | /* 139983 */ // GIR_Coverage, 6304, |
| 49865 | /* 139983 */ GIR_EraseRootFromParent_Done, |
| 49866 | /* 139984 */ // Label 2874: @139984 |
| 49867 | /* 139984 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(140043), // Rule ID 2773 // |
| 49868 | /* 139989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49869 | /* 139992 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49870 | /* 139996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49871 | /* 140000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 49872 | /* 140004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49873 | /* 140008 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 49874 | /* 140012 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49875 | /* 140017 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49876 | /* 140019 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49877 | /* 140019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 49878 | /* 140022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49879 | /* 140024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 49880 | /* 140028 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49881 | /* 140030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49882 | /* 140032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49883 | /* 140035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49884 | /* 140041 */ GIR_RootConstrainSelectedInstOperands, |
| 49885 | /* 140042 */ // GIR_Coverage, 2773, |
| 49886 | /* 140042 */ GIR_EraseRootFromParent_Done, |
| 49887 | /* 140043 */ // Label 2875: @140043 |
| 49888 | /* 140043 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(140085), // Rule ID 2721 // |
| 49889 | /* 140048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 49890 | /* 140051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49891 | /* 140055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49892 | /* 140059 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 49893 | /* 140063 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 49894 | /* 140063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 49895 | /* 140066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49896 | /* 140068 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 49897 | /* 140070 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 49898 | /* 140072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49899 | /* 140074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49900 | /* 140077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49901 | /* 140083 */ GIR_RootConstrainSelectedInstOperands, |
| 49902 | /* 140084 */ // GIR_Coverage, 2721, |
| 49903 | /* 140084 */ GIR_EraseRootFromParent_Done, |
| 49904 | /* 140085 */ // Label 2876: @140085 |
| 49905 | /* 140085 */ GIM_Reject, |
| 49906 | /* 140086 */ // Label 2870: @140086 |
| 49907 | /* 140086 */ GIM_Reject, |
| 49908 | /* 140087 */ // Label 2867: @140087 |
| 49909 | /* 140087 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(140473), |
| 49910 | /* 140092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49911 | /* 140095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49912 | /* 140098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 49913 | /* 140101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49914 | /* 140105 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(140179), // Rule ID 2757 // |
| 49915 | /* 140110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 49916 | /* 140113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 49917 | /* 140117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49918 | /* 140121 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 49919 | /* 140125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49920 | /* 140130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49921 | /* 140134 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 49922 | /* 140138 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49923 | /* 140142 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 49924 | /* 140146 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49925 | /* 140151 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 49926 | /* 140153 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49927 | /* 140153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 49928 | /* 140156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49929 | /* 140158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 49930 | /* 140162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49931 | /* 140166 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49932 | /* 140168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49933 | /* 140171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49934 | /* 140177 */ GIR_RootConstrainSelectedInstOperands, |
| 49935 | /* 140178 */ // GIR_Coverage, 2757, |
| 49936 | /* 140178 */ GIR_EraseRootFromParent_Done, |
| 49937 | /* 140179 */ // Label 2878: @140179 |
| 49938 | /* 140179 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(140253), // Rule ID 6308 // |
| 49939 | /* 140184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 49940 | /* 140187 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49941 | /* 140191 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49942 | /* 140195 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49943 | /* 140199 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 49944 | /* 140203 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49945 | /* 140208 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 49946 | /* 140212 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49947 | /* 140216 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 49948 | /* 140220 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49949 | /* 140225 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 49950 | /* 140227 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49951 | /* 140227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 49952 | /* 140230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49953 | /* 140232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 49954 | /* 140236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49955 | /* 140240 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49956 | /* 140242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49957 | /* 140245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49958 | /* 140251 */ GIR_RootConstrainSelectedInstOperands, |
| 49959 | /* 140252 */ // GIR_Coverage, 6308, |
| 49960 | /* 140252 */ GIR_EraseRootFromParent_Done, |
| 49961 | /* 140253 */ // Label 2879: @140253 |
| 49962 | /* 140253 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(140312), // Rule ID 2737 // |
| 49963 | /* 140258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 49964 | /* 140261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 49965 | /* 140265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49966 | /* 140269 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 49967 | /* 140273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49968 | /* 140278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49969 | /* 140282 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49970 | /* 140286 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49971 | /* 140288 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49972 | /* 140288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 49973 | /* 140291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49974 | /* 140293 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 49975 | /* 140295 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49976 | /* 140299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 49977 | /* 140301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49978 | /* 140304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 49979 | /* 140310 */ GIR_RootConstrainSelectedInstOperands, |
| 49980 | /* 140311 */ // GIR_Coverage, 2737, |
| 49981 | /* 140311 */ GIR_EraseRootFromParent_Done, |
| 49982 | /* 140312 */ // Label 2880: @140312 |
| 49983 | /* 140312 */ GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(140371), // Rule ID 6302 // |
| 49984 | /* 140317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 49985 | /* 140320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49986 | /* 140324 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49987 | /* 140328 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 49988 | /* 140332 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 49989 | /* 140336 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49990 | /* 140341 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 49991 | /* 140345 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49992 | /* 140347 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 49993 | /* 140347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 49994 | /* 140350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 49995 | /* 140352 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 49996 | /* 140354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 49997 | /* 140358 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 49998 | /* 140360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 49999 | /* 140363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50000 | /* 140369 */ GIR_RootConstrainSelectedInstOperands, |
| 50001 | /* 140370 */ // GIR_Coverage, 6302, |
| 50002 | /* 140370 */ GIR_EraseRootFromParent_Done, |
| 50003 | /* 140371 */ // Label 2881: @140371 |
| 50004 | /* 140371 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(140430), // Rule ID 2771 // |
| 50005 | /* 140376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 50006 | /* 140379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50007 | /* 140383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50008 | /* 140387 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 50009 | /* 140391 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50010 | /* 140395 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 50011 | /* 140399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50012 | /* 140404 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50013 | /* 140406 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 50014 | /* 140406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 50015 | /* 140409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 50016 | /* 140411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 50017 | /* 140415 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 50018 | /* 140417 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 50019 | /* 140419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50020 | /* 140422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50021 | /* 140428 */ GIR_RootConstrainSelectedInstOperands, |
| 50022 | /* 140429 */ // GIR_Coverage, 2771, |
| 50023 | /* 140429 */ GIR_EraseRootFromParent_Done, |
| 50024 | /* 140430 */ // Label 2882: @140430 |
| 50025 | /* 140430 */ GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(140472), // Rule ID 2719 // |
| 50026 | /* 140435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 50027 | /* 140438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50028 | /* 140442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50029 | /* 140446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50030 | /* 140450 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 50031 | /* 140450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 50032 | /* 140453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 50033 | /* 140455 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 50034 | /* 140457 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 50035 | /* 140459 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 50036 | /* 140461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50037 | /* 140464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50038 | /* 140470 */ GIR_RootConstrainSelectedInstOperands, |
| 50039 | /* 140471 */ // GIR_Coverage, 2719, |
| 50040 | /* 140471 */ GIR_EraseRootFromParent_Done, |
| 50041 | /* 140472 */ // Label 2883: @140472 |
| 50042 | /* 140472 */ GIM_Reject, |
| 50043 | /* 140473 */ // Label 2877: @140473 |
| 50044 | /* 140473 */ GIM_Reject, |
| 50045 | /* 140474 */ // Label 2868: @140474 |
| 50046 | /* 140474 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(140860), |
| 50047 | /* 140479 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 50048 | /* 140482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 50049 | /* 140485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 50050 | /* 140488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50051 | /* 140492 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(140566), // Rule ID 2755 // |
| 50052 | /* 140497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 50053 | /* 140500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50054 | /* 140504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50055 | /* 140508 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50056 | /* 140512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50057 | /* 140517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50058 | /* 140521 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 50059 | /* 140525 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50060 | /* 140529 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 50061 | /* 140533 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50062 | /* 140538 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 50063 | /* 140540 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 50064 | /* 140540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 50065 | /* 140543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 50066 | /* 140545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 50067 | /* 140549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 50068 | /* 140553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 50069 | /* 140555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50070 | /* 140558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50071 | /* 140564 */ GIR_RootConstrainSelectedInstOperands, |
| 50072 | /* 140565 */ // GIR_Coverage, 2755, |
| 50073 | /* 140565 */ GIR_EraseRootFromParent_Done, |
| 50074 | /* 140566 */ // Label 2885: @140566 |
| 50075 | /* 140566 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(140640), // Rule ID 6306 // |
| 50076 | /* 140571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 50077 | /* 140574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50078 | /* 140578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50079 | /* 140582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50080 | /* 140586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50081 | /* 140590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50082 | /* 140595 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 50083 | /* 140599 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50084 | /* 140603 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 50085 | /* 140607 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50086 | /* 140612 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 50087 | /* 140614 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 50088 | /* 140614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 50089 | /* 140617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 50090 | /* 140619 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 50091 | /* 140623 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 50092 | /* 140627 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 50093 | /* 140629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50094 | /* 140632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50095 | /* 140638 */ GIR_RootConstrainSelectedInstOperands, |
| 50096 | /* 140639 */ // GIR_Coverage, 6306, |
| 50097 | /* 140639 */ GIR_EraseRootFromParent_Done, |
| 50098 | /* 140640 */ // Label 2886: @140640 |
| 50099 | /* 140640 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(140699), // Rule ID 2735 // |
| 50100 | /* 140645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 50101 | /* 140648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50102 | /* 140652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50103 | /* 140656 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50104 | /* 140660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50105 | /* 140665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50106 | /* 140669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50107 | /* 140673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50108 | /* 140675 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 50109 | /* 140675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 50110 | /* 140678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 50111 | /* 140680 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 50112 | /* 140682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 50113 | /* 140686 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 50114 | /* 140688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50115 | /* 140691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50116 | /* 140697 */ GIR_RootConstrainSelectedInstOperands, |
| 50117 | /* 140698 */ // GIR_Coverage, 2735, |
| 50118 | /* 140698 */ GIR_EraseRootFromParent_Done, |
| 50119 | /* 140699 */ // Label 2887: @140699 |
| 50120 | /* 140699 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(140758), // Rule ID 6300 // |
| 50121 | /* 140704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 50122 | /* 140707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50123 | /* 140711 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50124 | /* 140715 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50125 | /* 140719 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50126 | /* 140723 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50127 | /* 140728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50128 | /* 140732 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50129 | /* 140734 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 50130 | /* 140734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 50131 | /* 140737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 50132 | /* 140739 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 50133 | /* 140741 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 50134 | /* 140745 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 50135 | /* 140747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50136 | /* 140750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50137 | /* 140756 */ GIR_RootConstrainSelectedInstOperands, |
| 50138 | /* 140757 */ // GIR_Coverage, 6300, |
| 50139 | /* 140757 */ GIR_EraseRootFromParent_Done, |
| 50140 | /* 140758 */ // Label 2888: @140758 |
| 50141 | /* 140758 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(140817), // Rule ID 2769 // |
| 50142 | /* 140763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 50143 | /* 140766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50144 | /* 140770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50145 | /* 140774 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 50146 | /* 140778 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 50147 | /* 140782 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50148 | /* 140786 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50149 | /* 140791 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50150 | /* 140793 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 50151 | /* 140793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 50152 | /* 140796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 50153 | /* 140798 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 50154 | /* 140802 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 50155 | /* 140804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 50156 | /* 140806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50157 | /* 140809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50158 | /* 140815 */ GIR_RootConstrainSelectedInstOperands, |
| 50159 | /* 140816 */ // GIR_Coverage, 2769, |
| 50160 | /* 140816 */ GIR_EraseRootFromParent_Done, |
| 50161 | /* 140817 */ // Label 2889: @140817 |
| 50162 | /* 140817 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(140859), // Rule ID 2717 // |
| 50163 | /* 140822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 50164 | /* 140825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50165 | /* 140829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50166 | /* 140833 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50167 | /* 140837 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 50168 | /* 140837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 50169 | /* 140840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 50170 | /* 140842 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 50171 | /* 140844 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 50172 | /* 140846 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 50173 | /* 140848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50174 | /* 140851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50175 | /* 140857 */ GIR_RootConstrainSelectedInstOperands, |
| 50176 | /* 140858 */ // GIR_Coverage, 2717, |
| 50177 | /* 140858 */ GIR_EraseRootFromParent_Done, |
| 50178 | /* 140859 */ // Label 2890: @140859 |
| 50179 | /* 140859 */ GIM_Reject, |
| 50180 | /* 140860 */ // Label 2884: @140860 |
| 50181 | /* 140860 */ GIM_Reject, |
| 50182 | /* 140861 */ // Label 2869: @140861 |
| 50183 | /* 140861 */ GIM_Reject, |
| 50184 | /* 140862 */ // Label 84: @140862 |
| 50185 | /* 140862 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2894*/ GIMT_Encode4(140999), |
| 50186 | /* 140873 */ /*GILLT_s16*//*Label 2891*/ GIMT_Encode4(140885), |
| 50187 | /* 140877 */ /*GILLT_s32*//*Label 2892*/ GIMT_Encode4(140923), |
| 50188 | /* 140881 */ /*GILLT_s64*//*Label 2893*/ GIMT_Encode4(140961), |
| 50189 | /* 140885 */ // Label 2891: @140885 |
| 50190 | /* 140885 */ GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(140922), // Rule ID 737 // |
| 50191 | /* 140890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 50192 | /* 140893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 50193 | /* 140896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 50194 | /* 140900 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 50195 | /* 140904 */ // (strict_fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 50196 | /* 140904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 50197 | /* 140907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 50198 | /* 140909 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 50199 | /* 140911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50200 | /* 140914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50201 | /* 140920 */ GIR_RootConstrainSelectedInstOperands, |
| 50202 | /* 140921 */ // GIR_Coverage, 737, |
| 50203 | /* 140921 */ GIR_EraseRootFromParent_Done, |
| 50204 | /* 140922 */ // Label 2895: @140922 |
| 50205 | /* 140922 */ GIM_Reject, |
| 50206 | /* 140923 */ // Label 2892: @140923 |
| 50207 | /* 140923 */ GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(140960), // Rule ID 735 // |
| 50208 | /* 140928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 50209 | /* 140931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 50210 | /* 140934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50211 | /* 140938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 50212 | /* 140942 */ // (strict_fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 50213 | /* 140942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 50214 | /* 140945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 50215 | /* 140947 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 50216 | /* 140949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50217 | /* 140952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50218 | /* 140958 */ GIR_RootConstrainSelectedInstOperands, |
| 50219 | /* 140959 */ // GIR_Coverage, 735, |
| 50220 | /* 140959 */ GIR_EraseRootFromParent_Done, |
| 50221 | /* 140960 */ // Label 2896: @140960 |
| 50222 | /* 140960 */ GIM_Reject, |
| 50223 | /* 140961 */ // Label 2893: @140961 |
| 50224 | /* 140961 */ GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(140998), // Rule ID 733 // |
| 50225 | /* 140966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 50226 | /* 140969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 50227 | /* 140972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50228 | /* 140976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 50229 | /* 140980 */ // (strict_fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 50230 | /* 140980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 50231 | /* 140983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 50232 | /* 140985 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 50233 | /* 140987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 50234 | /* 140990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50235 | /* 140996 */ GIR_RootConstrainSelectedInstOperands, |
| 50236 | /* 140997 */ // GIR_Coverage, 733, |
| 50237 | /* 140997 */ GIR_EraseRootFromParent_Done, |
| 50238 | /* 140998 */ // Label 2897: @140998 |
| 50239 | /* 140998 */ GIM_Reject, |
| 50240 | /* 140999 */ // Label 2894: @140999 |
| 50241 | /* 140999 */ GIM_Reject, |
| 50242 | /* 141000 */ // Label 85: @141000 |
| 50243 | /* 141000 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(141015), // Rule ID 12 // |
| 50244 | /* 141005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 50245 | /* 141008 */ // (trap) => (TRAP) |
| 50246 | /* 141008 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP), |
| 50247 | /* 141013 */ GIR_RootConstrainSelectedInstOperands, |
| 50248 | /* 141014 */ // GIR_Coverage, 12, |
| 50249 | /* 141014 */ GIR_Done, |
| 50250 | /* 141015 */ // Label 2898: @141015 |
| 50251 | /* 141015 */ GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(141030), // Rule ID 284 // |
| 50252 | /* 141020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 50253 | /* 141023 */ // (trap) => (tTRAP) |
| 50254 | /* 141023 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP), |
| 50255 | /* 141028 */ GIR_RootConstrainSelectedInstOperands, |
| 50256 | /* 141029 */ // GIR_Coverage, 284, |
| 50257 | /* 141029 */ GIR_Done, |
| 50258 | /* 141030 */ // Label 2899: @141030 |
| 50259 | /* 141030 */ GIM_Reject, |
| 50260 | /* 141031 */ // Label 86: @141031 |
| 50261 | /* 141031 */ GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(141047), // Rule ID 2023 // |
| 50262 | /* 141036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM), |
| 50263 | /* 141039 */ // (debugtrap) => (BKPT 0:{ *:[i32] }) |
| 50264 | /* 141039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT), |
| 50265 | /* 141042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50266 | /* 141045 */ GIR_RootConstrainSelectedInstOperands, |
| 50267 | /* 141046 */ // GIR_Coverage, 2023, |
| 50268 | /* 141046 */ GIR_EraseRootFromParent_Done, |
| 50269 | /* 141047 */ // Label 2900: @141047 |
| 50270 | /* 141047 */ GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(141074), // Rule ID 2024 // |
| 50271 | /* 141052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV5T), |
| 50272 | /* 141055 */ // (debugtrap) => (UDF 254:{ *:[i32] }) |
| 50273 | /* 141055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 50274 | /* 141058 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 50275 | /* 141068 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50276 | /* 141072 */ GIR_RootConstrainSelectedInstOperands, |
| 50277 | /* 141073 */ // GIR_Coverage, 2024, |
| 50278 | /* 141073 */ GIR_EraseRootFromParent_Done, |
| 50279 | /* 141074 */ // Label 2901: @141074 |
| 50280 | /* 141074 */ GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(141090), // Rule ID 2209 // |
| 50281 | /* 141079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsThumb), |
| 50282 | /* 141082 */ // (debugtrap) => (tBKPT 0:{ *:[i32] }) |
| 50283 | /* 141082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT), |
| 50284 | /* 141085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50285 | /* 141088 */ GIR_RootConstrainSelectedInstOperands, |
| 50286 | /* 141089 */ // GIR_Coverage, 2209, |
| 50287 | /* 141089 */ GIR_EraseRootFromParent_Done, |
| 50288 | /* 141090 */ // Label 2902: @141090 |
| 50289 | /* 141090 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(141117), // Rule ID 2210 // |
| 50290 | /* 141095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_NoV5T), |
| 50291 | /* 141098 */ // (debugtrap) => (tUDF 254:{ *:[i32] }) |
| 50292 | /* 141098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 50293 | /* 141101 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 50294 | /* 141111 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50295 | /* 141115 */ GIR_RootConstrainSelectedInstOperands, |
| 50296 | /* 141116 */ // GIR_Coverage, 2210, |
| 50297 | /* 141116 */ GIR_EraseRootFromParent_Done, |
| 50298 | /* 141117 */ // Label 2903: @141117 |
| 50299 | /* 141117 */ GIM_Reject, |
| 50300 | /* 141118 */ // Label 87: @141118 |
| 50301 | /* 141118 */ GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(141538), |
| 50302 | /* 141123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 50303 | /* 141126 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2908*/ GIMT_Encode4(141424), |
| 50304 | /* 141137 */ /*GILLT_v4s32*//*Label 2905*/ GIMT_Encode4(141169), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50305 | /* 141153 */ /*GILLT_v8s16*//*Label 2906*/ GIMT_Encode4(141240), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50306 | /* 141165 */ /*GILLT_v16s8*//*Label 2907*/ GIMT_Encode4(141311), |
| 50307 | /* 141169 */ // Label 2905: @141169 |
| 50308 | /* 141169 */ GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(141239), // Rule ID 3617 // |
| 50309 | /* 141174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50310 | /* 141177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 50311 | /* 141181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50312 | /* 141185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 50313 | /* 141189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 50314 | /* 141193 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 50315 | /* 141197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50316 | /* 141202 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50317 | /* 141207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50318 | /* 141209 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 50319 | /* 141209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 50320 | /* 141212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50321 | /* 141214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 50322 | /* 141218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 50323 | /* 141222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50324 | /* 141225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50325 | /* 141231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50326 | /* 141237 */ GIR_RootConstrainSelectedInstOperands, |
| 50327 | /* 141238 */ // GIR_Coverage, 3617, |
| 50328 | /* 141238 */ GIR_EraseRootFromParent_Done, |
| 50329 | /* 141239 */ // Label 2909: @141239 |
| 50330 | /* 141239 */ GIM_Reject, |
| 50331 | /* 141240 */ // Label 2906: @141240 |
| 50332 | /* 141240 */ GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(141310), // Rule ID 3618 // |
| 50333 | /* 141245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50334 | /* 141248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 50335 | /* 141252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50336 | /* 141256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 50337 | /* 141260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 50338 | /* 141264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 50339 | /* 141268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50340 | /* 141273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50341 | /* 141278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50342 | /* 141280 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 50343 | /* 141280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 50344 | /* 141283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50345 | /* 141285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 50346 | /* 141289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 50347 | /* 141293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50348 | /* 141296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50349 | /* 141302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50350 | /* 141308 */ GIR_RootConstrainSelectedInstOperands, |
| 50351 | /* 141309 */ // GIR_Coverage, 3618, |
| 50352 | /* 141309 */ GIR_EraseRootFromParent_Done, |
| 50353 | /* 141310 */ // Label 2910: @141310 |
| 50354 | /* 141310 */ GIM_Reject, |
| 50355 | /* 141311 */ // Label 2907: @141311 |
| 50356 | /* 141311 */ GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(141423), |
| 50357 | /* 141316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 50358 | /* 141320 */ GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(141386), // Rule ID 3621 // |
| 50359 | /* 141325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50360 | /* 141328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50361 | /* 141332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 50362 | /* 141336 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 50363 | /* 141340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 50364 | /* 141344 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50365 | /* 141349 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50366 | /* 141354 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50367 | /* 141356 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 50368 | /* 141356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 50369 | /* 141359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50370 | /* 141361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 50371 | /* 141365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 50372 | /* 141369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50373 | /* 141372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50374 | /* 141378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50375 | /* 141384 */ GIR_RootConstrainSelectedInstOperands, |
| 50376 | /* 141385 */ // GIR_Coverage, 3621, |
| 50377 | /* 141385 */ GIR_EraseRootFromParent_Done, |
| 50378 | /* 141386 */ // Label 2912: @141386 |
| 50379 | /* 141386 */ GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(141422), // Rule ID 3425 // |
| 50380 | /* 141391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50381 | /* 141394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50382 | /* 141398 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec) |
| 50383 | /* 141398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc), |
| 50384 | /* 141401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 50385 | /* 141403 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 50386 | /* 141405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50387 | /* 141408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50388 | /* 141414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50389 | /* 141420 */ GIR_RootConstrainSelectedInstOperands, |
| 50390 | /* 141421 */ // GIR_Coverage, 3425, |
| 50391 | /* 141421 */ GIR_EraseRootFromParent_Done, |
| 50392 | /* 141422 */ // Label 2913: @141422 |
| 50393 | /* 141422 */ GIM_Reject, |
| 50394 | /* 141423 */ // Label 2911: @141423 |
| 50395 | /* 141423 */ GIM_Reject, |
| 50396 | /* 141424 */ // Label 2908: @141424 |
| 50397 | /* 141424 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2916*/ GIMT_Encode4(141537), |
| 50398 | /* 141435 */ /*GILLT_v4s32*//*Label 2914*/ GIMT_Encode4(141455), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50399 | /* 141451 */ /*GILLT_v8s16*//*Label 2915*/ GIMT_Encode4(141496), |
| 50400 | /* 141455 */ // Label 2914: @141455 |
| 50401 | /* 141455 */ GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(141495), // Rule ID 3463 // |
| 50402 | /* 141460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50403 | /* 141463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 50404 | /* 141467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50405 | /* 141471 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec) |
| 50406 | /* 141471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc), |
| 50407 | /* 141474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 50408 | /* 141476 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 50409 | /* 141478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50410 | /* 141481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50411 | /* 141487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50412 | /* 141493 */ GIR_RootConstrainSelectedInstOperands, |
| 50413 | /* 141494 */ // GIR_Coverage, 3463, |
| 50414 | /* 141494 */ GIR_EraseRootFromParent_Done, |
| 50415 | /* 141495 */ // Label 2917: @141495 |
| 50416 | /* 141495 */ GIM_Reject, |
| 50417 | /* 141496 */ // Label 2915: @141496 |
| 50418 | /* 141496 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(141536), // Rule ID 3453 // |
| 50419 | /* 141501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50420 | /* 141504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 50421 | /* 141508 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50422 | /* 141512 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec) |
| 50423 | /* 141512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc), |
| 50424 | /* 141515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 50425 | /* 141517 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 50426 | /* 141519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50427 | /* 141522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50428 | /* 141528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50429 | /* 141534 */ GIR_RootConstrainSelectedInstOperands, |
| 50430 | /* 141535 */ // GIR_Coverage, 3453, |
| 50431 | /* 141535 */ GIR_EraseRootFromParent_Done, |
| 50432 | /* 141536 */ // Label 2918: @141536 |
| 50433 | /* 141536 */ GIM_Reject, |
| 50434 | /* 141537 */ // Label 2916: @141537 |
| 50435 | /* 141537 */ GIM_Reject, |
| 50436 | /* 141538 */ // Label 2904: @141538 |
| 50437 | /* 141538 */ GIM_Reject, |
| 50438 | /* 141539 */ // Label 88: @141539 |
| 50439 | /* 141539 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(141818), |
| 50440 | /* 141544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 50441 | /* 141547 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2923*/ GIMT_Encode4(141817), |
| 50442 | /* 141558 */ /*GILLT_v4s32*//*Label 2920*/ GIMT_Encode4(141590), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50443 | /* 141574 */ /*GILLT_v8s16*//*Label 2921*/ GIMT_Encode4(141673), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50444 | /* 141586 */ /*GILLT_v16s8*//*Label 2922*/ GIMT_Encode4(141741), |
| 50445 | /* 141590 */ // Label 2920: @141590 |
| 50446 | /* 141590 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(141672), // Rule ID 3523 // |
| 50447 | /* 141595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50448 | /* 141598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50449 | /* 141602 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50450 | /* 141606 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 50451 | /* 141606 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50452 | /* 141609 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 50453 | /* 141613 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50454 | /* 141618 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u), |
| 50455 | /* 141628 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50456 | /* 141631 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50457 | /* 141637 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50458 | /* 141643 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50459 | /* 141645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 50460 | /* 141648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50461 | /* 141650 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50462 | /* 141653 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50463 | /* 141655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50464 | /* 141658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50465 | /* 141664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50466 | /* 141670 */ GIR_RootConstrainSelectedInstOperands, |
| 50467 | /* 141671 */ // GIR_Coverage, 3523, |
| 50468 | /* 141671 */ GIR_EraseRootFromParent_Done, |
| 50469 | /* 141672 */ // Label 2924: @141672 |
| 50470 | /* 141672 */ GIM_Reject, |
| 50471 | /* 141673 */ // Label 2921: @141673 |
| 50472 | /* 141673 */ GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(141740), // Rule ID 3522 // |
| 50473 | /* 141678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50474 | /* 141681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50475 | /* 141685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50476 | /* 141689 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 50477 | /* 141689 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50478 | /* 141692 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 50479 | /* 141696 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50480 | /* 141701 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u), |
| 50481 | /* 141711 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50482 | /* 141713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 50483 | /* 141716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50484 | /* 141718 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50485 | /* 141721 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50486 | /* 141723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50487 | /* 141726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50488 | /* 141732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50489 | /* 141738 */ GIR_RootConstrainSelectedInstOperands, |
| 50490 | /* 141739 */ // GIR_Coverage, 3522, |
| 50491 | /* 141739 */ GIR_EraseRootFromParent_Done, |
| 50492 | /* 141740 */ // Label 2925: @141740 |
| 50493 | /* 141740 */ GIM_Reject, |
| 50494 | /* 141741 */ // Label 2922: @141741 |
| 50495 | /* 141741 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(141816), // Rule ID 3521 // |
| 50496 | /* 141746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50497 | /* 141749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50498 | /* 141753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50499 | /* 141757 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 50500 | /* 141757 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50501 | /* 141760 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 50502 | /* 141764 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50503 | /* 141769 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 50504 | /* 141772 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50505 | /* 141775 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50506 | /* 141781 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50507 | /* 141787 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50508 | /* 141789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 50509 | /* 141792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50510 | /* 141794 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50511 | /* 141797 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50512 | /* 141799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50513 | /* 141802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50514 | /* 141808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50515 | /* 141814 */ GIR_RootConstrainSelectedInstOperands, |
| 50516 | /* 141815 */ // GIR_Coverage, 3521, |
| 50517 | /* 141815 */ GIR_EraseRootFromParent_Done, |
| 50518 | /* 141816 */ // Label 2926: @141816 |
| 50519 | /* 141816 */ GIM_Reject, |
| 50520 | /* 141817 */ // Label 2923: @141817 |
| 50521 | /* 141817 */ GIM_Reject, |
| 50522 | /* 141818 */ // Label 2919: @141818 |
| 50523 | /* 141818 */ GIM_Reject, |
| 50524 | /* 141819 */ // Label 89: @141819 |
| 50525 | /* 141819 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(142107), |
| 50526 | /* 141824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 50527 | /* 141827 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2931*/ GIMT_Encode4(142106), |
| 50528 | /* 141838 */ /*GILLT_v4s32*//*Label 2928*/ GIMT_Encode4(141870), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50529 | /* 141854 */ /*GILLT_v8s16*//*Label 2929*/ GIMT_Encode4(141953), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50530 | /* 141866 */ /*GILLT_v16s8*//*Label 2930*/ GIMT_Encode4(142030), |
| 50531 | /* 141870 */ // Label 2928: @141870 |
| 50532 | /* 141870 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(141952), // Rule ID 3529 // |
| 50533 | /* 141875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50534 | /* 141878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50535 | /* 141882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50536 | /* 141886 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 50537 | /* 141886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50538 | /* 141889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 50539 | /* 141893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50540 | /* 141898 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u), |
| 50541 | /* 141908 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50542 | /* 141911 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50543 | /* 141917 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50544 | /* 141923 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50545 | /* 141925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 50546 | /* 141928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50547 | /* 141930 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50548 | /* 141933 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50549 | /* 141935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50550 | /* 141938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50551 | /* 141944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50552 | /* 141950 */ GIR_RootConstrainSelectedInstOperands, |
| 50553 | /* 141951 */ // GIR_Coverage, 3529, |
| 50554 | /* 141951 */ GIR_EraseRootFromParent_Done, |
| 50555 | /* 141952 */ // Label 2932: @141952 |
| 50556 | /* 141952 */ GIM_Reject, |
| 50557 | /* 141953 */ // Label 2929: @141953 |
| 50558 | /* 141953 */ GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(142029), // Rule ID 3528 // |
| 50559 | /* 141958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50560 | /* 141961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50561 | /* 141965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50562 | /* 141969 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 50563 | /* 141969 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50564 | /* 141972 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 50565 | /* 141976 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50566 | /* 141981 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 50567 | /* 141991 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50568 | /* 141994 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50569 | /* 142000 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50570 | /* 142002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 50571 | /* 142005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50572 | /* 142007 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50573 | /* 142010 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50574 | /* 142012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50575 | /* 142015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50576 | /* 142021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50577 | /* 142027 */ GIR_RootConstrainSelectedInstOperands, |
| 50578 | /* 142028 */ // GIR_Coverage, 3528, |
| 50579 | /* 142028 */ GIR_EraseRootFromParent_Done, |
| 50580 | /* 142029 */ // Label 2933: @142029 |
| 50581 | /* 142029 */ GIM_Reject, |
| 50582 | /* 142030 */ // Label 2930: @142030 |
| 50583 | /* 142030 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(142105), // Rule ID 3527 // |
| 50584 | /* 142035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50585 | /* 142038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50586 | /* 142042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50587 | /* 142046 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 50588 | /* 142046 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50589 | /* 142049 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 50590 | /* 142053 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50591 | /* 142058 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 50592 | /* 142061 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50593 | /* 142064 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50594 | /* 142070 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50595 | /* 142076 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50596 | /* 142078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 50597 | /* 142081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50598 | /* 142083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50599 | /* 142086 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50600 | /* 142088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50601 | /* 142091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50602 | /* 142097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50603 | /* 142103 */ GIR_RootConstrainSelectedInstOperands, |
| 50604 | /* 142104 */ // GIR_Coverage, 3527, |
| 50605 | /* 142104 */ GIR_EraseRootFromParent_Done, |
| 50606 | /* 142105 */ // Label 2934: @142105 |
| 50607 | /* 142105 */ GIM_Reject, |
| 50608 | /* 142106 */ // Label 2931: @142106 |
| 50609 | /* 142106 */ GIM_Reject, |
| 50610 | /* 142107 */ // Label 2927: @142107 |
| 50611 | /* 142107 */ GIM_Reject, |
| 50612 | /* 142108 */ // Label 90: @142108 |
| 50613 | /* 142108 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(142388), |
| 50614 | /* 142113 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 50615 | /* 142116 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2939*/ GIMT_Encode4(142387), |
| 50616 | /* 142127 */ /*GILLT_v4s32*//*Label 2936*/ GIMT_Encode4(142159), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50617 | /* 142143 */ /*GILLT_v8s16*//*Label 2937*/ GIMT_Encode4(142235), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50618 | /* 142155 */ /*GILLT_v16s8*//*Label 2938*/ GIMT_Encode4(142311), |
| 50619 | /* 142159 */ // Label 2936: @142159 |
| 50620 | /* 142159 */ GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(142234), // Rule ID 3526 // |
| 50621 | /* 142164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50622 | /* 142167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50623 | /* 142171 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50624 | /* 142175 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 50625 | /* 142175 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50626 | /* 142178 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 50627 | /* 142182 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50628 | /* 142187 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 50629 | /* 142190 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50630 | /* 142193 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50631 | /* 142199 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50632 | /* 142205 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50633 | /* 142207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 50634 | /* 142210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50635 | /* 142212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50636 | /* 142215 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50637 | /* 142217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50638 | /* 142220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50639 | /* 142226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50640 | /* 142232 */ GIR_RootConstrainSelectedInstOperands, |
| 50641 | /* 142233 */ // GIR_Coverage, 3526, |
| 50642 | /* 142233 */ GIR_EraseRootFromParent_Done, |
| 50643 | /* 142234 */ // Label 2940: @142234 |
| 50644 | /* 142234 */ GIM_Reject, |
| 50645 | /* 142235 */ // Label 2937: @142235 |
| 50646 | /* 142235 */ GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(142310), // Rule ID 3525 // |
| 50647 | /* 142240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50648 | /* 142243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50649 | /* 142247 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50650 | /* 142251 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 50651 | /* 142251 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50652 | /* 142254 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 50653 | /* 142258 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50654 | /* 142263 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 50655 | /* 142266 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50656 | /* 142269 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50657 | /* 142275 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50658 | /* 142281 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50659 | /* 142283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 50660 | /* 142286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50661 | /* 142288 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50662 | /* 142291 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50663 | /* 142293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50664 | /* 142296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50665 | /* 142302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50666 | /* 142308 */ GIR_RootConstrainSelectedInstOperands, |
| 50667 | /* 142309 */ // GIR_Coverage, 3525, |
| 50668 | /* 142309 */ GIR_EraseRootFromParent_Done, |
| 50669 | /* 142310 */ // Label 2941: @142310 |
| 50670 | /* 142310 */ GIM_Reject, |
| 50671 | /* 142311 */ // Label 2938: @142311 |
| 50672 | /* 142311 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(142386), // Rule ID 3524 // |
| 50673 | /* 142316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50674 | /* 142319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50675 | /* 142323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50676 | /* 142327 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 50677 | /* 142327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50678 | /* 142330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 50679 | /* 142334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50680 | /* 142339 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 50681 | /* 142342 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50682 | /* 142345 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50683 | /* 142351 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50684 | /* 142357 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50685 | /* 142359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 50686 | /* 142362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50687 | /* 142364 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50688 | /* 142367 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50689 | /* 142369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50690 | /* 142372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50691 | /* 142378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50692 | /* 142384 */ GIR_RootConstrainSelectedInstOperands, |
| 50693 | /* 142385 */ // GIR_Coverage, 3524, |
| 50694 | /* 142385 */ GIR_EraseRootFromParent_Done, |
| 50695 | /* 142386 */ // Label 2942: @142386 |
| 50696 | /* 142386 */ GIM_Reject, |
| 50697 | /* 142387 */ // Label 2939: @142387 |
| 50698 | /* 142387 */ GIM_Reject, |
| 50699 | /* 142388 */ // Label 2935: @142388 |
| 50700 | /* 142388 */ GIM_Reject, |
| 50701 | /* 142389 */ // Label 91: @142389 |
| 50702 | /* 142389 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(142684), |
| 50703 | /* 142394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 50704 | /* 142397 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2947*/ GIMT_Encode4(142683), |
| 50705 | /* 142408 */ /*GILLT_v4s32*//*Label 2944*/ GIMT_Encode4(142440), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50706 | /* 142424 */ /*GILLT_v8s16*//*Label 2945*/ GIMT_Encode4(142523), GIMT_Encode4(0), GIMT_Encode4(0), |
| 50707 | /* 142436 */ /*GILLT_v16s8*//*Label 2946*/ GIMT_Encode4(142600), |
| 50708 | /* 142440 */ // Label 2944: @142440 |
| 50709 | /* 142440 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(142522), // Rule ID 3532 // |
| 50710 | /* 142445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50711 | /* 142448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50712 | /* 142452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50713 | /* 142456 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 50714 | /* 142456 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50715 | /* 142459 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 50716 | /* 142463 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50717 | /* 142468 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295), |
| 50718 | /* 142478 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50719 | /* 142481 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50720 | /* 142487 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50721 | /* 142493 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50722 | /* 142495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 50723 | /* 142498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50724 | /* 142500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50725 | /* 142503 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50726 | /* 142505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50727 | /* 142508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50728 | /* 142514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50729 | /* 142520 */ GIR_RootConstrainSelectedInstOperands, |
| 50730 | /* 142521 */ // GIR_Coverage, 3532, |
| 50731 | /* 142521 */ GIR_EraseRootFromParent_Done, |
| 50732 | /* 142522 */ // Label 2948: @142522 |
| 50733 | /* 142522 */ GIM_Reject, |
| 50734 | /* 142523 */ // Label 2945: @142523 |
| 50735 | /* 142523 */ GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(142599), // Rule ID 3531 // |
| 50736 | /* 142528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50737 | /* 142531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50738 | /* 142535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50739 | /* 142539 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 50740 | /* 142539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50741 | /* 142542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 50742 | /* 142546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50743 | /* 142551 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 50744 | /* 142561 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50745 | /* 142564 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50746 | /* 142570 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50747 | /* 142572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 50748 | /* 142575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50749 | /* 142577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50750 | /* 142580 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50751 | /* 142582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50752 | /* 142585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50753 | /* 142591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50754 | /* 142597 */ GIR_RootConstrainSelectedInstOperands, |
| 50755 | /* 142598 */ // GIR_Coverage, 3531, |
| 50756 | /* 142598 */ GIR_EraseRootFromParent_Done, |
| 50757 | /* 142599 */ // Label 2949: @142599 |
| 50758 | /* 142599 */ GIM_Reject, |
| 50759 | /* 142600 */ // Label 2946: @142600 |
| 50760 | /* 142600 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(142682), // Rule ID 3530 // |
| 50761 | /* 142605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 50762 | /* 142608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 50763 | /* 142612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 50764 | /* 142616 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 50765 | /* 142616 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50766 | /* 142619 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 50767 | /* 142623 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 50768 | /* 142628 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255), |
| 50769 | /* 142638 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 50770 | /* 142641 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50771 | /* 142647 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50772 | /* 142653 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50773 | /* 142655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 50774 | /* 142658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 50775 | /* 142660 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50776 | /* 142663 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 50777 | /* 142665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50778 | /* 142668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50779 | /* 142674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 50780 | /* 142680 */ GIR_RootConstrainSelectedInstOperands, |
| 50781 | /* 142681 */ // GIR_Coverage, 3530, |
| 50782 | /* 142681 */ GIR_EraseRootFromParent_Done, |
| 50783 | /* 142682 */ // Label 2950: @142682 |
| 50784 | /* 142682 */ GIM_Reject, |
| 50785 | /* 142683 */ // Label 2947: @142683 |
| 50786 | /* 142683 */ GIM_Reject, |
| 50787 | /* 142684 */ // Label 2943: @142684 |
| 50788 | /* 142684 */ GIM_Reject, |
| 50789 | /* 142685 */ // Label 92: @142685 |
| 50790 | /* 142685 */ GIM_Reject, |
| 50791 | /* 142686 */ }; // Size: 142686 bytes |
| 50792 | return MatchTable0; |
| 50793 | } |
| 50794 | #undef GIMT_Encode2 |
| 50795 | #undef GIMT_Encode4 |
| 50796 | #undef GIMT_Encode8 |
| 50797 | |
| 50798 | |
| 50799 | #endif // GET_GLOBALISEL_IMPL |
| 50800 | |
| 50801 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 50802 | |
| 50803 | PredicateBitset AvailableModuleFeatures; |
| 50804 | mutable PredicateBitset AvailableFunctionFeatures; |
| 50805 | PredicateBitset getAvailableFeatures() const { |
| 50806 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 50807 | } |
| 50808 | PredicateBitset |
| 50809 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const; |
| 50810 | PredicateBitset |
| 50811 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, |
| 50812 | const MachineFunction *MF) const; |
| 50813 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 50814 | |
| 50815 | #endif // GET_GLOBALISEL_PREDICATES_DECL |
| 50816 | |
| 50817 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 50818 | |
| 50819 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 50820 | AvailableFunctionFeatures() |
| 50821 | |
| 50822 | #endif // GET_GLOBALISEL_PREDICATES_INIT |
| 50823 | |
| 50824 |
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