1//===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the InstructionSelector class for ARM.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "ARMRegisterBankInfo.h"
14#include "ARMSubtarget.h"
15#include "ARMTargetMachine.h"
16#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
17#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
18#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22
23#define DEBUG_TYPE "arm-isel"
24
25using namespace llvm;
26
27namespace {
28
29#define GET_GLOBALISEL_PREDICATE_BITSET
30#include "ARMGenGlobalISel.inc"
31#undef GET_GLOBALISEL_PREDICATE_BITSET
32
33class ARMInstructionSelector : public InstructionSelector {
34public:
35 ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
36 const ARMRegisterBankInfo &RBI);
37
38 bool select(MachineInstr &I) override;
39 static const char *getName() { return DEBUG_TYPE; }
40
41private:
42 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
43
44 struct CmpConstants;
45 struct InsertInfo;
46
47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
48 MachineRegisterInfo &MRI) const;
49
50 // Helper for inserting a comparison sequence that sets \p ResReg to either 1
51 // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
52 // \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
53 bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
55 unsigned PrevRes) const;
56
57 // Set \p DestReg to \p Constant.
58 void putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const;
59
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
63
64 // Check if the types match and both operands have the expected size and
65 // register bank.
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
67 unsigned ExpectedSize, unsigned ExpectedRegBankID) const;
68
69 // Check if the register has the expected size and register bank.
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
71 unsigned ExpectedRegBankID) const;
72
73 const ARMBaseInstrInfo &TII;
74 const ARMBaseRegisterInfo &TRI;
75 const ARMBaseTargetMachine &TM;
76 const ARMRegisterBankInfo &RBI;
77 const ARMSubtarget &STI;
78
79 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
80 // uses "STI." in the code generated by TableGen. If we want to reuse some of
81 // the custom C++ predicates written for DAGISel, we need to have both around.
82 const ARMSubtarget *Subtarget = &STI;
83
84 // Store the opcodes that we might need, so we don't have to check what kind
85 // of subtarget (ARM vs Thumb) we have all the time.
86 struct OpcodeCache {
87 unsigned ZEXT16;
88 unsigned SEXT16;
89
90 unsigned ZEXT8;
91 unsigned SEXT8;
92
93 // Used for implementing ZEXT/SEXT from i1
94 unsigned AND;
95 unsigned RSB;
96
97 unsigned STORE32;
98 unsigned LOAD32;
99
100 unsigned STORE16;
101 unsigned LOAD16;
102
103 unsigned STORE8;
104 unsigned LOAD8;
105
106 unsigned ADDrr;
107 unsigned ADDri;
108
109 // Used for G_ICMP
110 unsigned CMPrr;
111 unsigned MOVi;
112 unsigned MOVCCi;
113
114 // Used for G_SELECT
115 unsigned MOVCCr;
116
117 unsigned TSTri;
118 unsigned Bcc;
119
120 // Used for G_GLOBAL_VALUE
121 unsigned MOVi32imm;
122 unsigned ConstPoolLoad;
123 unsigned MOV_ga_pcrel;
124 unsigned LDRLIT_ga_pcrel;
125 unsigned LDRLIT_ga_abs;
126
127 OpcodeCache(const ARMSubtarget &STI);
128 } const Opcodes;
129
130 // Select the opcode for simple extensions (that translate to a single SXT/UXT
131 // instruction). Extension operations more complicated than that should not
132 // invoke this. Returns the original opcode if it doesn't know how to select a
133 // better one.
134 unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) const;
135
136 // Select the opcode for simple loads and stores. Returns the original opcode
137 // if it doesn't know how to select a better one.
138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
139 unsigned Size) const;
140
141 void renderVFPF32Imm(MachineInstrBuilder &New, const MachineInstr &Old,
142 int OpIdx = -1) const;
143 void renderVFPF64Imm(MachineInstrBuilder &New, const MachineInstr &Old,
144 int OpIdx = -1) const;
145 void renderInvertedImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
146 int OpIdx = -1) const;
147
148#define GET_GLOBALISEL_PREDICATES_DECL
149#include "ARMGenGlobalISel.inc"
150#undef GET_GLOBALISEL_PREDICATES_DECL
151
152// We declare the temporaries used by selectImpl() in the class to minimize the
153// cost of constructing placeholder values.
154#define GET_GLOBALISEL_TEMPORARIES_DECL
155#include "ARMGenGlobalISel.inc"
156#undef GET_GLOBALISEL_TEMPORARIES_DECL
157};
158} // end anonymous namespace
159
160namespace llvm {
161InstructionSelector *
162createARMInstructionSelector(const ARMBaseTargetMachine &TM,
163 const ARMSubtarget &STI,
164 const ARMRegisterBankInfo &RBI) {
165 return new ARMInstructionSelector(TM, STI, RBI);
166}
167}
168
169#define GET_GLOBALISEL_IMPL
170#include "ARMGenGlobalISel.inc"
171#undef GET_GLOBALISEL_IMPL
172
173ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
174 const ARMSubtarget &STI,
175 const ARMRegisterBankInfo &RBI)
176 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI),
177 STI(STI), Opcodes(STI),
178#define GET_GLOBALISEL_PREDICATES_INIT
179#include "ARMGenGlobalISel.inc"
180#undef GET_GLOBALISEL_PREDICATES_INIT
181#define GET_GLOBALISEL_TEMPORARIES_INIT
182#include "ARMGenGlobalISel.inc"
183#undef GET_GLOBALISEL_TEMPORARIES_INIT
184{
185}
186
187static const TargetRegisterClass *guessRegClass(unsigned Reg,
188 MachineRegisterInfo &MRI,
189 const TargetRegisterInfo &TRI,
190 const RegisterBankInfo &RBI) {
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
192 assert(RegBank && "Can't get reg bank for virtual register");
193
194 const unsigned Size = MRI.getType(Reg).getSizeInBits();
195 assert((RegBank->getID() == ARM::GPRRegBankID ||
196 RegBank->getID() == ARM::FPRRegBankID) &&
197 "Unsupported reg bank");
198
199 if (RegBank->getID() == ARM::FPRRegBankID) {
200 if (Size == 32)
201 return &ARM::SPRRegClass;
202 else if (Size == 64)
203 return &ARM::DPRRegClass;
204 else if (Size == 128)
205 return &ARM::QPRRegClass;
206 else
207 llvm_unreachable("Unsupported destination size");
208 }
209
210 return &ARM::GPRRegClass;
211}
212
213static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
214 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
215 const RegisterBankInfo &RBI) {
216 Register DstReg = I.getOperand(i: 0).getReg();
217 if (DstReg.isPhysical())
218 return true;
219
220 const TargetRegisterClass *RC = guessRegClass(Reg: DstReg, MRI, TRI, RBI);
221
222 // No need to constrain SrcReg. It will get constrained when
223 // we hit another of its uses or its defs.
224 // Copies do not have constraints.
225 if (!RBI.constrainGenericRegister(Reg: DstReg, RC: *RC, MRI)) {
226 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
227 << " operand\n");
228 return false;
229 }
230 return true;
231}
232
233static bool selectMergeValues(MachineInstrBuilder &MIB,
234 const ARMBaseInstrInfo &TII,
235 MachineRegisterInfo &MRI,
236 const TargetRegisterInfo &TRI,
237 const RegisterBankInfo &RBI) {
238 assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP");
239
240 // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
241 // into one DPR.
242 Register VReg0 = MIB.getReg(Idx: 0);
243 (void)VReg0;
244 assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
246 "Unsupported operand for G_MERGE_VALUES");
247 Register VReg1 = MIB.getReg(Idx: 1);
248 (void)VReg1;
249 assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
251 "Unsupported operand for G_MERGE_VALUES");
252 Register VReg2 = MIB.getReg(Idx: 2);
253 (void)VReg2;
254 assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
256 "Unsupported operand for G_MERGE_VALUES");
257
258 MIB->setDesc(TII.get(Opcode: ARM::VMOVDRR));
259 MIB.add(MOs: predOps(Pred: ARMCC::AL));
260
261 return true;
262}
263
264static bool selectUnmergeValues(MachineInstrBuilder &MIB,
265 const ARMBaseInstrInfo &TII,
266 MachineRegisterInfo &MRI,
267 const TargetRegisterInfo &TRI,
268 const RegisterBankInfo &RBI) {
269 assert(TII.getSubtarget().hasVFP2Base() &&
270 "Can't select unmerge without VFP");
271
272 // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
273 // GPRs.
274 Register VReg0 = MIB.getReg(Idx: 0);
275 (void)VReg0;
276 assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
278 "Unsupported operand for G_UNMERGE_VALUES");
279 Register VReg1 = MIB.getReg(Idx: 1);
280 (void)VReg1;
281 assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
283 "Unsupported operand for G_UNMERGE_VALUES");
284 Register VReg2 = MIB.getReg(Idx: 2);
285 (void)VReg2;
286 assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
288 "Unsupported operand for G_UNMERGE_VALUES");
289
290 MIB->setDesc(TII.get(Opcode: ARM::VMOVRRD));
291 MIB.add(MOs: predOps(Pred: ARMCC::AL));
292
293 return true;
294}
295
296ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {
297 bool isThumb = STI.isThumb();
298
299 using namespace TargetOpcode;
300
301#define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC
302 STORE_OPCODE(SEXT16, SXTH);
303 STORE_OPCODE(ZEXT16, UXTH);
304
305 STORE_OPCODE(SEXT8, SXTB);
306 STORE_OPCODE(ZEXT8, UXTB);
307
308 STORE_OPCODE(AND, ANDri);
309 STORE_OPCODE(RSB, RSBri);
310
311 STORE_OPCODE(STORE32, STRi12);
312 STORE_OPCODE(LOAD32, LDRi12);
313
314 // LDRH/STRH are special...
315 STORE16 = isThumb ? ARM::t2STRHi12 : ARM::STRH;
316 LOAD16 = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
317
318 STORE_OPCODE(STORE8, STRBi12);
319 STORE_OPCODE(LOAD8, LDRBi12);
320
321 STORE_OPCODE(ADDrr, ADDrr);
322 STORE_OPCODE(ADDri, ADDri);
323
324 STORE_OPCODE(CMPrr, CMPrr);
325 STORE_OPCODE(MOVi, MOVi);
326 STORE_OPCODE(MOVCCi, MOVCCi);
327
328 STORE_OPCODE(MOVCCr, MOVCCr);
329
330 STORE_OPCODE(TSTri, TSTri);
331 STORE_OPCODE(Bcc, Bcc);
332
333 STORE_OPCODE(MOVi32imm, MOVi32imm);
334 ConstPoolLoad = isThumb ? ARM::t2LDRpci : ARM::LDRi12;
335 STORE_OPCODE(MOV_ga_pcrel, MOV_ga_pcrel);
336 LDRLIT_ga_pcrel = isThumb ? ARM::tLDRLIT_ga_pcrel : ARM::LDRLIT_ga_pcrel;
337 LDRLIT_ga_abs = isThumb ? ARM::tLDRLIT_ga_abs : ARM::LDRLIT_ga_abs;
338#undef MAP_OPCODE
339}
340
341unsigned ARMInstructionSelector::selectSimpleExtOpc(unsigned Opc,
342 unsigned Size) const {
343 using namespace TargetOpcode;
344
345 if (Size != 8 && Size != 16)
346 return Opc;
347
348 if (Opc == G_SEXT)
349 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
350
351 if (Opc == G_ZEXT)
352 return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
353
354 return Opc;
355}
356
357unsigned ARMInstructionSelector::selectLoadStoreOpCode(unsigned Opc,
358 unsigned RegBank,
359 unsigned Size) const {
360 bool isStore = Opc == TargetOpcode::G_STORE;
361
362 if (RegBank == ARM::GPRRegBankID) {
363 switch (Size) {
364 case 1:
365 case 8:
366 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
367 case 16:
368 return isStore ? Opcodes.STORE16 : Opcodes.LOAD16;
369 case 32:
370 return isStore ? Opcodes.STORE32 : Opcodes.LOAD32;
371 default:
372 return Opc;
373 }
374 }
375
376 if (RegBank == ARM::FPRRegBankID) {
377 switch (Size) {
378 case 32:
379 return isStore ? ARM::VSTRS : ARM::VLDRS;
380 case 64:
381 return isStore ? ARM::VSTRD : ARM::VLDRD;
382 default:
383 return Opc;
384 }
385 }
386
387 return Opc;
388}
389
390// When lowering comparisons, we sometimes need to perform two compares instead
391// of just one. Get the condition codes for both comparisons. If only one is
392// needed, the second member of the pair is ARMCC::AL.
393static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
394getComparePreds(CmpInst::Predicate Pred) {
395 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
396 switch (Pred) {
397 case CmpInst::FCMP_ONE:
398 Preds = {ARMCC::GT, ARMCC::MI};
399 break;
400 case CmpInst::FCMP_UEQ:
401 Preds = {ARMCC::EQ, ARMCC::VS};
402 break;
403 case CmpInst::ICMP_EQ:
404 case CmpInst::FCMP_OEQ:
405 Preds.first = ARMCC::EQ;
406 break;
407 case CmpInst::ICMP_SGT:
408 case CmpInst::FCMP_OGT:
409 Preds.first = ARMCC::GT;
410 break;
411 case CmpInst::ICMP_SGE:
412 case CmpInst::FCMP_OGE:
413 Preds.first = ARMCC::GE;
414 break;
415 case CmpInst::ICMP_UGT:
416 case CmpInst::FCMP_UGT:
417 Preds.first = ARMCC::HI;
418 break;
419 case CmpInst::FCMP_OLT:
420 Preds.first = ARMCC::MI;
421 break;
422 case CmpInst::ICMP_ULE:
423 case CmpInst::FCMP_OLE:
424 Preds.first = ARMCC::LS;
425 break;
426 case CmpInst::FCMP_ORD:
427 Preds.first = ARMCC::VC;
428 break;
429 case CmpInst::FCMP_UNO:
430 Preds.first = ARMCC::VS;
431 break;
432 case CmpInst::FCMP_UGE:
433 Preds.first = ARMCC::PL;
434 break;
435 case CmpInst::ICMP_SLT:
436 case CmpInst::FCMP_ULT:
437 Preds.first = ARMCC::LT;
438 break;
439 case CmpInst::ICMP_SLE:
440 case CmpInst::FCMP_ULE:
441 Preds.first = ARMCC::LE;
442 break;
443 case CmpInst::FCMP_UNE:
444 case CmpInst::ICMP_NE:
445 Preds.first = ARMCC::NE;
446 break;
447 case CmpInst::ICMP_UGE:
448 Preds.first = ARMCC::HS;
449 break;
450 case CmpInst::ICMP_ULT:
451 Preds.first = ARMCC::LO;
452 break;
453 default:
454 break;
455 }
456 assert(Preds.first != ARMCC::AL && "No comparisons needed?");
457 return Preds;
458}
459
460struct ARMInstructionSelector::CmpConstants {
461 CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned SelectOpcode,
462 unsigned OpRegBank, unsigned OpSize)
463 : ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
464 SelectResultOpcode(SelectOpcode), OperandRegBankID(OpRegBank),
465 OperandSize(OpSize) {}
466
467 // The opcode used for performing the comparison.
468 const unsigned ComparisonOpcode;
469
470 // The opcode used for reading the flags set by the comparison. May be
471 // ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
472 const unsigned ReadFlagsOpcode;
473
474 // The opcode used for materializing the result of the comparison.
475 const unsigned SelectResultOpcode;
476
477 // The assumed register bank ID for the operands.
478 const unsigned OperandRegBankID;
479
480 // The assumed size in bits for the operands.
481 const unsigned OperandSize;
482};
483
484struct ARMInstructionSelector::InsertInfo {
485 InsertInfo(MachineInstrBuilder &MIB)
486 : MBB(*MIB->getParent()), InsertBefore(std::next(x: MIB->getIterator())),
487 DbgLoc(MIB->getDebugLoc()) {}
488
489 MachineBasicBlock &MBB;
490 const MachineBasicBlock::instr_iterator InsertBefore;
491 const DebugLoc &DbgLoc;
492};
493
494void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
495 unsigned Constant) const {
496 (void)BuildMI(BB&: I.MBB, I: I.InsertBefore, MIMD: I.DbgLoc, MCID: TII.get(Opcode: Opcodes.MOVi))
497 .addDef(RegNo: DestReg)
498 .addImm(Val: Constant)
499 .add(MOs: predOps(Pred: ARMCC::AL))
500 .add(MO: condCodeOp());
501}
502
503bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
504 unsigned LHSReg, unsigned RHSReg,
505 unsigned ExpectedSize,
506 unsigned ExpectedRegBankID) const {
507 return MRI.getType(Reg: LHSReg) == MRI.getType(Reg: RHSReg) &&
508 validReg(MRI, Reg: LHSReg, ExpectedSize, ExpectedRegBankID) &&
509 validReg(MRI, Reg: RHSReg, ExpectedSize, ExpectedRegBankID);
510}
511
512bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
513 unsigned ExpectedSize,
514 unsigned ExpectedRegBankID) const {
515 if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
516 LLVM_DEBUG(dbgs() << "Unexpected size for register");
517 return false;
518 }
519
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
521 LLVM_DEBUG(dbgs() << "Unexpected register bank for register");
522 return false;
523 }
524
525 return true;
526}
527
528bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
529 MachineInstrBuilder &MIB,
530 MachineRegisterInfo &MRI) const {
531 const InsertInfo I(MIB);
532
533 auto ResReg = MIB.getReg(Idx: 0);
534 if (!validReg(MRI, Reg: ResReg, ExpectedSize: 1, ExpectedRegBankID: ARM::GPRRegBankID))
535 return false;
536
537 auto Cond =
538 static_cast<CmpInst::Predicate>(MIB->getOperand(i: 1).getPredicate());
539 if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
540 putConstant(I, DestReg: ResReg, Constant: Cond == CmpInst::FCMP_TRUE ? 1 : 0);
541 MIB->eraseFromParent();
542 return true;
543 }
544
545 auto LHSReg = MIB.getReg(Idx: 2);
546 auto RHSReg = MIB.getReg(Idx: 3);
547 if (!validOpRegPair(MRI, LHSReg, RHSReg, ExpectedSize: Helper.OperandSize,
548 ExpectedRegBankID: Helper.OperandRegBankID))
549 return false;
550
551 auto ARMConds = getComparePreds(Pred: Cond);
552 auto ZeroReg = MRI.createVirtualRegister(RegClass: &ARM::GPRRegClass);
553 putConstant(I, DestReg: ZeroReg, Constant: 0);
554
555 if (ARMConds.second == ARMCC::AL) {
556 // Simple case, we only need one comparison and we're done.
557 if (!insertComparison(Helper, I, ResReg, Cond: ARMConds.first, LHSReg, RHSReg,
558 PrevRes: ZeroReg))
559 return false;
560 } else {
561 // Not so simple, we need two successive comparisons.
562 auto IntermediateRes = MRI.createVirtualRegister(RegClass: &ARM::GPRRegClass);
563 if (!insertComparison(Helper, I, ResReg: IntermediateRes, Cond: ARMConds.first, LHSReg,
564 RHSReg, PrevRes: ZeroReg))
565 return false;
566 if (!insertComparison(Helper, I, ResReg, Cond: ARMConds.second, LHSReg, RHSReg,
567 PrevRes: IntermediateRes))
568 return false;
569 }
570
571 MIB->eraseFromParent();
572 return true;
573}
574
575bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
576 unsigned ResReg,
577 ARMCC::CondCodes Cond,
578 unsigned LHSReg, unsigned RHSReg,
579 unsigned PrevRes) const {
580 // Perform the comparison.
581 auto CmpI =
582 BuildMI(BB&: I.MBB, I: I.InsertBefore, MIMD: I.DbgLoc, MCID: TII.get(Opcode: Helper.ComparisonOpcode))
583 .addUse(RegNo: LHSReg)
584 .addUse(RegNo: RHSReg)
585 .add(MOs: predOps(Pred: ARMCC::AL));
586 constrainSelectedInstRegOperands(I&: *CmpI, TII, TRI, RBI);
587
588 // Read the comparison flags (if necessary).
589 if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
590 auto ReadI = BuildMI(BB&: I.MBB, I: I.InsertBefore, MIMD: I.DbgLoc,
591 MCID: TII.get(Opcode: Helper.ReadFlagsOpcode))
592 .add(MOs: predOps(Pred: ARMCC::AL));
593 constrainSelectedInstRegOperands(I&: *ReadI, TII, TRI, RBI);
594 }
595
596 // Select either 1 or the previous result based on the value of the flags.
597 auto Mov1I = BuildMI(BB&: I.MBB, I: I.InsertBefore, MIMD: I.DbgLoc,
598 MCID: TII.get(Opcode: Helper.SelectResultOpcode))
599 .addDef(RegNo: ResReg)
600 .addUse(RegNo: PrevRes)
601 .addImm(Val: 1)
602 .add(MOs: predOps(Pred: Cond, PredReg: ARM::CPSR));
603 constrainSelectedInstRegOperands(I&: *Mov1I, TII, TRI, RBI);
604
605 return true;
606}
607
608bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
609 MachineRegisterInfo &MRI) const {
610 if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) {
611 LLVM_DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n");
612 return false;
613 }
614
615 auto GV = MIB->getOperand(i: 1).getGlobal();
616 if (GV->isThreadLocal()) {
617 LLVM_DEBUG(dbgs() << "TLS variables not supported yet\n");
618 return false;
619 }
620
621 auto &MBB = *MIB->getParent();
622 auto &MF = *MBB.getParent();
623
624 bool UseMovt = STI.useMovt();
625
626 LLT PtrTy = MRI.getType(Reg: MIB->getOperand(i: 0).getReg());
627 const Align Alignment(4);
628
629 auto addOpsForConstantPoolLoad = [&MF, Alignment, PtrTy](
630 MachineInstrBuilder &MIB,
631 const GlobalValue *GV, bool IsSBREL) {
632 assert((MIB->getOpcode() == ARM::LDRi12 ||
633 MIB->getOpcode() == ARM::t2LDRpci) &&
634 "Unsupported instruction");
635 auto ConstPool = MF.getConstantPool();
636 auto CPIndex =
637 // For SB relative entries we need a target-specific constant pool.
638 // Otherwise, just use a regular constant pool entry.
639 IsSBREL
640 ? ConstPool->getConstantPoolIndex(
641 V: ARMConstantPoolConstant::Create(GV, Modifier: ARMCP::SBREL), Alignment)
642 : ConstPool->getConstantPoolIndex(C: GV, Alignment);
643 MIB.addConstantPoolIndex(Idx: CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
644 .addMemOperand(MMO: MF.getMachineMemOperand(
645 PtrInfo: MachinePointerInfo::getConstantPool(MF), F: MachineMemOperand::MOLoad,
646 MemTy: PtrTy, BaseAlignment: Alignment));
647 if (MIB->getOpcode() == ARM::LDRi12)
648 MIB.addImm(Val: 0);
649 MIB.add(MOs: predOps(Pred: ARMCC::AL));
650 };
651
652 auto addGOTMemOperand = [&MF, Alignment](MachineInstrBuilder &MIB) {
653 const DataLayout &DL = MF.getDataLayout();
654 MIB.addMemOperand(MMO: MF.getMachineMemOperand(
655 PtrInfo: MachinePointerInfo::getGOT(MF), F: MachineMemOperand::MOLoad,
656 Size: DL.getPointerSize(AS: DL.getProgramAddressSpace()), BaseAlignment: Alignment));
657 };
658
659 if (TM.isPositionIndependent()) {
660 bool Indirect = STI.isGVIndirectSymbol(GV);
661
662 // For ARM mode, we have different pseudoinstructions for direct accesses
663 // and indirect accesses, and the ones for indirect accesses include the
664 // load from GOT. For Thumb mode, we use the same pseudoinstruction for both
665 // direct and indirect accesses, and we need to manually generate the load
666 // from GOT.
667 bool UseOpcodeThatLoads = Indirect && !STI.isThumb();
668
669 // FIXME: Taking advantage of MOVT for ELF is pretty involved, so we don't
670 // support it yet. See PR28229.
671 unsigned Opc =
672 UseMovt && !STI.isTargetELF()
673 ? (UseOpcodeThatLoads ? (unsigned)ARM::MOV_ga_pcrel_ldr
674 : Opcodes.MOV_ga_pcrel)
675 : (UseOpcodeThatLoads ? (unsigned)ARM::LDRLIT_ga_pcrel_ldr
676 : Opcodes.LDRLIT_ga_pcrel);
677 MIB->setDesc(TII.get(Opcode: Opc));
678
679 int TargetFlags = ARMII::MO_NO_FLAG;
680 if (STI.isTargetDarwin())
681 TargetFlags |= ARMII::MO_NONLAZY;
682 if (STI.isGVInGOT(GV))
683 TargetFlags |= ARMII::MO_GOT;
684 MIB->getOperand(i: 1).setTargetFlags(TargetFlags);
685
686 if (Indirect) {
687 if (!UseOpcodeThatLoads) {
688 auto ResultReg = MIB.getReg(Idx: 0);
689 auto AddressReg = MRI.createVirtualRegister(RegClass: &ARM::GPRRegClass);
690
691 MIB->getOperand(i: 0).setReg(AddressReg);
692
693 auto InsertBefore = std::next(x: MIB->getIterator());
694 auto MIBLoad = BuildMI(BB&: MBB, I: InsertBefore, MIMD: MIB->getDebugLoc(),
695 MCID: TII.get(Opcode: Opcodes.LOAD32))
696 .addDef(RegNo: ResultReg)
697 .addReg(RegNo: AddressReg)
698 .addImm(Val: 0)
699 .add(MOs: predOps(Pred: ARMCC::AL));
700 addGOTMemOperand(MIBLoad);
701
702 constrainSelectedInstRegOperands(I&: *MIBLoad, TII, TRI, RBI);
703 } else {
704 addGOTMemOperand(MIB);
705 }
706 }
707
708 constrainSelectedInstRegOperands(I&: *MIB, TII, TRI, RBI);
709 return true;
710 }
711
712 bool isReadOnly = STI.getTargetLowering()->isReadOnly(GV);
713 if (STI.isROPI() && isReadOnly) {
714 unsigned Opc = UseMovt ? Opcodes.MOV_ga_pcrel : Opcodes.LDRLIT_ga_pcrel;
715 MIB->setDesc(TII.get(Opcode: Opc));
716 constrainSelectedInstRegOperands(I&: *MIB, TII, TRI, RBI);
717 return true;
718 }
719 if (STI.isRWPI() && !isReadOnly) {
720 auto Offset = MRI.createVirtualRegister(RegClass: &ARM::GPRRegClass);
721 MachineInstrBuilder OffsetMIB;
722 if (UseMovt) {
723 OffsetMIB = BuildMI(BB&: MBB, I&: *MIB, MIMD: MIB->getDebugLoc(),
724 MCID: TII.get(Opcode: Opcodes.MOVi32imm), DestReg: Offset);
725 OffsetMIB.addGlobalAddress(GV, /*Offset*/ 0, TargetFlags: ARMII::MO_SBREL);
726 } else {
727 // Load the offset from the constant pool.
728 OffsetMIB = BuildMI(BB&: MBB, I&: *MIB, MIMD: MIB->getDebugLoc(),
729 MCID: TII.get(Opcode: Opcodes.ConstPoolLoad), DestReg: Offset);
730 addOpsForConstantPoolLoad(OffsetMIB, GV, /*IsSBREL*/ true);
731 }
732 constrainSelectedInstRegOperands(I&: *OffsetMIB, TII, TRI, RBI);
733
734 // Add the offset to the SB register.
735 MIB->setDesc(TII.get(Opcode: Opcodes.ADDrr));
736 MIB->removeOperand(OpNo: 1);
737 MIB.addReg(RegNo: ARM::R9) // FIXME: don't hardcode R9
738 .addReg(RegNo: Offset)
739 .add(MOs: predOps(Pred: ARMCC::AL))
740 .add(MO: condCodeOp());
741
742 constrainSelectedInstRegOperands(I&: *MIB, TII, TRI, RBI);
743 return true;
744 }
745
746 if (STI.isTargetELF()) {
747 if (UseMovt) {
748 MIB->setDesc(TII.get(Opcode: Opcodes.MOVi32imm));
749 } else {
750 // Load the global's address from the constant pool.
751 MIB->setDesc(TII.get(Opcode: Opcodes.ConstPoolLoad));
752 MIB->removeOperand(OpNo: 1);
753 addOpsForConstantPoolLoad(MIB, GV, /*IsSBREL*/ false);
754 }
755 } else if (STI.isTargetMachO()) {
756 if (UseMovt)
757 MIB->setDesc(TII.get(Opcode: Opcodes.MOVi32imm));
758 else
759 MIB->setDesc(TII.get(Opcode: Opcodes.LDRLIT_ga_abs));
760 } else {
761 LLVM_DEBUG(dbgs() << "Object format not supported yet\n");
762 return false;
763 }
764
765 constrainSelectedInstRegOperands(I&: *MIB, TII, TRI, RBI);
766 return true;
767}
768
769bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
770 MachineRegisterInfo &MRI) const {
771 auto &MBB = *MIB->getParent();
772 auto InsertBefore = std::next(x: MIB->getIterator());
773 auto &DbgLoc = MIB->getDebugLoc();
774
775 // Compare the condition to 1.
776 auto CondReg = MIB.getReg(Idx: 1);
777 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
778 "Unsupported types for select operation");
779 auto CmpI = BuildMI(BB&: MBB, I: InsertBefore, MIMD: DbgLoc, MCID: TII.get(Opcode: Opcodes.TSTri))
780 .addUse(RegNo: CondReg)
781 .addImm(Val: 1)
782 .add(MOs: predOps(Pred: ARMCC::AL));
783 constrainSelectedInstRegOperands(I&: *CmpI, TII, TRI, RBI);
784
785 // Move a value into the result register based on the result of the
786 // comparison.
787 auto ResReg = MIB.getReg(Idx: 0);
788 auto TrueReg = MIB.getReg(Idx: 2);
789 auto FalseReg = MIB.getReg(Idx: 3);
790 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
791 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
792 "Unsupported types for select operation");
793 auto Mov1I = BuildMI(BB&: MBB, I: InsertBefore, MIMD: DbgLoc, MCID: TII.get(Opcode: Opcodes.MOVCCr))
794 .addDef(RegNo: ResReg)
795 .addUse(RegNo: TrueReg)
796 .addUse(RegNo: FalseReg)
797 .add(MOs: predOps(Pred: ARMCC::EQ, PredReg: ARM::CPSR));
798 constrainSelectedInstRegOperands(I&: *Mov1I, TII, TRI, RBI);
799
800 MIB->eraseFromParent();
801 return true;
802}
803
804bool ARMInstructionSelector::selectShift(unsigned ShiftOpc,
805 MachineInstrBuilder &MIB) const {
806 assert(!STI.isThumb() && "Unsupported subtarget");
807 MIB->setDesc(TII.get(Opcode: ARM::MOVsr));
808 MIB.addImm(Val: ShiftOpc);
809 MIB.add(MOs: predOps(Pred: ARMCC::AL)).add(MO: condCodeOp());
810 constrainSelectedInstRegOperands(I&: *MIB, TII, TRI, RBI);
811 return true;
812}
813
814void ARMInstructionSelector::renderVFPF32Imm(
815 MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst,
816 int OpIdx) const {
817 assert(OldInst.getOpcode() == TargetOpcode::G_FCONSTANT &&
818 OpIdx == -1 && "Expected G_FCONSTANT");
819
820 APFloat FPImmValue = OldInst.getOperand(i: 1).getFPImm()->getValueAPF();
821 int FPImmEncoding = ARM_AM::getFP32Imm(FPImm: FPImmValue);
822 assert(FPImmEncoding != -1 && "Invalid immediate value");
823
824 NewInstBuilder.addImm(Val: FPImmEncoding);
825}
826
827void ARMInstructionSelector::renderVFPF64Imm(
828 MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst, int OpIdx) const {
829 assert(OldInst.getOpcode() == TargetOpcode::G_FCONSTANT &&
830 OpIdx == -1 && "Expected G_FCONSTANT");
831
832 APFloat FPImmValue = OldInst.getOperand(i: 1).getFPImm()->getValueAPF();
833 int FPImmEncoding = ARM_AM::getFP64Imm(FPImm: FPImmValue);
834 assert(FPImmEncoding != -1 && "Invalid immediate value");
835
836 NewInstBuilder.addImm(Val: FPImmEncoding);
837}
838
839void ARMInstructionSelector::renderInvertedImm(MachineInstrBuilder &MIB,
840 const MachineInstr &MI,
841 int OpIdx) const {
842 assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
843 "Expected G_CONSTANT");
844 int64_t CVal = MI.getOperand(i: 1).getCImm()->getSExtValue();
845 MIB.addImm(Val: ~CVal);
846}
847
848bool ARMInstructionSelector::select(MachineInstr &I) {
849 assert(I.getParent() && "Instruction should be in a basic block!");
850 assert(I.getParent()->getParent() && "Instruction should be in a function!");
851
852 auto &MBB = *I.getParent();
853 auto &MF = *MBB.getParent();
854 auto &MRI = MF.getRegInfo();
855
856 if (!isPreISelGenericOpcode(Opcode: I.getOpcode())) {
857 if (I.isCopy())
858 return selectCopy(I, TII, MRI, TRI, RBI);
859
860 return true;
861 }
862
863 using namespace TargetOpcode;
864
865 if (selectImpl(I, CoverageInfo&: *CoverageInfo))
866 return true;
867
868 MachineInstrBuilder MIB{MF, I};
869 bool isSExt = false;
870
871 switch (I.getOpcode()) {
872 case G_SEXT:
873 isSExt = true;
874 [[fallthrough]];
875 case G_ZEXT: {
876 assert(MRI.getType(I.getOperand(0).getReg()).getSizeInBits() <= 32 &&
877 "Unsupported destination size for extension");
878
879 LLT SrcTy = MRI.getType(Reg: I.getOperand(i: 1).getReg());
880 unsigned SrcSize = SrcTy.getSizeInBits();
881 switch (SrcSize) {
882 case 1: {
883 // ZExt boils down to & 0x1; for SExt we also subtract that from 0
884 I.setDesc(TII.get(Opcode: Opcodes.AND));
885 MIB.addImm(Val: 1).add(MOs: predOps(Pred: ARMCC::AL)).add(MO: condCodeOp());
886
887 if (isSExt) {
888 Register SExtResult = I.getOperand(i: 0).getReg();
889
890 // Use a new virtual register for the result of the AND
891 Register AndResult = MRI.createVirtualRegister(RegClass: &ARM::GPRRegClass);
892 I.getOperand(i: 0).setReg(AndResult);
893
894 auto InsertBefore = std::next(x: I.getIterator());
895 auto SubI =
896 BuildMI(BB&: MBB, I: InsertBefore, MIMD: I.getDebugLoc(), MCID: TII.get(Opcode: Opcodes.RSB))
897 .addDef(RegNo: SExtResult)
898 .addUse(RegNo: AndResult)
899 .addImm(Val: 0)
900 .add(MOs: predOps(Pred: ARMCC::AL))
901 .add(MO: condCodeOp());
902 constrainSelectedInstRegOperands(I&: *SubI, TII, TRI, RBI);
903 }
904 break;
905 }
906 case 8:
907 case 16: {
908 unsigned NewOpc = selectSimpleExtOpc(Opc: I.getOpcode(), Size: SrcSize);
909 if (NewOpc == I.getOpcode())
910 return false;
911 I.setDesc(TII.get(Opcode: NewOpc));
912 MIB.addImm(Val: 0).add(MOs: predOps(Pred: ARMCC::AL));
913 break;
914 }
915 default:
916 LLVM_DEBUG(dbgs() << "Unsupported source size for extension");
917 return false;
918 }
919 break;
920 }
921 case G_ANYEXT:
922 case G_TRUNC: {
923 // The high bits are undefined, so there's nothing special to do, just
924 // treat it as a copy.
925 auto SrcReg = I.getOperand(i: 1).getReg();
926 auto DstReg = I.getOperand(i: 0).getReg();
927
928 const auto &SrcRegBank = *RBI.getRegBank(Reg: SrcReg, MRI, TRI);
929 const auto &DstRegBank = *RBI.getRegBank(Reg: DstReg, MRI, TRI);
930
931 if (SrcRegBank.getID() == ARM::FPRRegBankID) {
932 // This should only happen in the obscure case where we have put a 64-bit
933 // integer into a D register. Get it out of there and keep only the
934 // interesting part.
935 assert(I.getOpcode() == G_TRUNC && "Unsupported operand for G_ANYEXT");
936 assert(DstRegBank.getID() == ARM::GPRRegBankID &&
937 "Unsupported combination of register banks");
938 assert(MRI.getType(SrcReg).getSizeInBits() == 64 && "Unsupported size");
939 assert(MRI.getType(DstReg).getSizeInBits() <= 32 && "Unsupported size");
940
941 Register IgnoredBits = MRI.createVirtualRegister(RegClass: &ARM::GPRRegClass);
942 auto InsertBefore = std::next(x: I.getIterator());
943 auto MovI =
944 BuildMI(BB&: MBB, I: InsertBefore, MIMD: I.getDebugLoc(), MCID: TII.get(Opcode: ARM::VMOVRRD))
945 .addDef(RegNo: DstReg)
946 .addDef(RegNo: IgnoredBits)
947 .addUse(RegNo: SrcReg)
948 .add(MOs: predOps(Pred: ARMCC::AL));
949 constrainSelectedInstRegOperands(I&: *MovI, TII, TRI, RBI);
950
951 MIB->eraseFromParent();
952 return true;
953 }
954
955 if (SrcRegBank.getID() != DstRegBank.getID()) {
956 LLVM_DEBUG(
957 dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
958 return false;
959 }
960
961 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
962 LLVM_DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
963 return false;
964 }
965
966 I.setDesc(TII.get(Opcode: COPY));
967 return selectCopy(I, TII, MRI, TRI, RBI);
968 }
969 case G_CONSTANT: {
970 if (!MRI.getType(Reg: I.getOperand(i: 0).getReg()).isPointer()) {
971 // Non-pointer constants should be handled by TableGen.
972 LLVM_DEBUG(dbgs() << "Unsupported constant type\n");
973 return false;
974 }
975
976 auto &Val = I.getOperand(i: 1);
977 if (Val.isCImm()) {
978 if (!Val.getCImm()->isZero()) {
979 LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
980 return false;
981 }
982 Val.ChangeToImmediate(ImmVal: 0);
983 } else {
984 assert(Val.isImm() && "Unexpected operand for G_CONSTANT");
985 if (Val.getImm() != 0) {
986 LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
987 return false;
988 }
989 }
990
991 assert(!STI.isThumb() && "Unsupported subtarget");
992 I.setDesc(TII.get(Opcode: ARM::MOVi));
993 MIB.add(MOs: predOps(Pred: ARMCC::AL)).add(MO: condCodeOp());
994 break;
995 }
996 case G_FCONSTANT: {
997 // Load from constant pool
998 unsigned Size = MRI.getType(Reg: I.getOperand(i: 0).getReg()).getSizeInBits() / 8;
999 Align Alignment(Size);
1000
1001 assert((Size == 4 || Size == 8) && "Unsupported FP constant type");
1002 auto LoadOpcode = Size == 4 ? ARM::VLDRS : ARM::VLDRD;
1003
1004 auto ConstPool = MF.getConstantPool();
1005 auto CPIndex =
1006 ConstPool->getConstantPoolIndex(C: I.getOperand(i: 1).getFPImm(), Alignment);
1007 MIB->setDesc(TII.get(Opcode: LoadOpcode));
1008 MIB->removeOperand(OpNo: 1);
1009 MIB.addConstantPoolIndex(Idx: CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
1010 .addMemOperand(
1011 MMO: MF.getMachineMemOperand(PtrInfo: MachinePointerInfo::getConstantPool(MF),
1012 F: MachineMemOperand::MOLoad, Size, BaseAlignment: Alignment))
1013 .addImm(Val: 0)
1014 .add(MOs: predOps(Pred: ARMCC::AL));
1015 break;
1016 }
1017 case G_INTTOPTR:
1018 case G_PTRTOINT: {
1019 auto SrcReg = I.getOperand(i: 1).getReg();
1020 auto DstReg = I.getOperand(i: 0).getReg();
1021
1022 const auto &SrcRegBank = *RBI.getRegBank(Reg: SrcReg, MRI, TRI);
1023 const auto &DstRegBank = *RBI.getRegBank(Reg: DstReg, MRI, TRI);
1024
1025 if (SrcRegBank.getID() != DstRegBank.getID()) {
1026 LLVM_DEBUG(
1027 dbgs()
1028 << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
1029 return false;
1030 }
1031
1032 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
1033 LLVM_DEBUG(
1034 dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
1035 return false;
1036 }
1037
1038 I.setDesc(TII.get(Opcode: COPY));
1039 return selectCopy(I, TII, MRI, TRI, RBI);
1040 }
1041 case G_SELECT:
1042 return selectSelect(MIB, MRI);
1043 case G_ICMP: {
1044 CmpConstants Helper(Opcodes.CMPrr, ARM::INSTRUCTION_LIST_END,
1045 Opcodes.MOVCCi, ARM::GPRRegBankID, 32);
1046 return selectCmp(Helper, MIB, MRI);
1047 }
1048 case G_FCMP: {
1049 assert(STI.hasVFP2Base() && "Can't select fcmp without VFP");
1050
1051 Register OpReg = I.getOperand(i: 2).getReg();
1052 unsigned Size = MRI.getType(Reg: OpReg).getSizeInBits();
1053
1054 if (Size == 64 && !STI.hasFP64()) {
1055 LLVM_DEBUG(dbgs() << "Subtarget only supports single precision");
1056 return false;
1057 }
1058 if (Size != 32 && Size != 64) {
1059 LLVM_DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
1060 return false;
1061 }
1062
1063 CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
1064 Opcodes.MOVCCi, ARM::FPRRegBankID, Size);
1065 return selectCmp(Helper, MIB, MRI);
1066 }
1067 case G_LSHR:
1068 return selectShift(ShiftOpc: ARM_AM::ShiftOpc::lsr, MIB);
1069 case G_ASHR:
1070 return selectShift(ShiftOpc: ARM_AM::ShiftOpc::asr, MIB);
1071 case G_SHL: {
1072 return selectShift(ShiftOpc: ARM_AM::ShiftOpc::lsl, MIB);
1073 }
1074 case G_PTR_ADD:
1075 I.setDesc(TII.get(Opcode: Opcodes.ADDrr));
1076 MIB.add(MOs: predOps(Pred: ARMCC::AL)).add(MO: condCodeOp());
1077 break;
1078 case G_FRAME_INDEX:
1079 // Add 0 to the given frame index and hope it will eventually be folded into
1080 // the user(s).
1081 I.setDesc(TII.get(Opcode: Opcodes.ADDri));
1082 MIB.addImm(Val: 0).add(MOs: predOps(Pred: ARMCC::AL)).add(MO: condCodeOp());
1083 break;
1084 case G_GLOBAL_VALUE:
1085 return selectGlobal(MIB, MRI);
1086 case G_STORE:
1087 case G_LOAD: {
1088 auto &MemOp = **I.memoperands_begin();
1089 if (MemOp.isAtomic()) {
1090 LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
1091 return false;
1092 }
1093
1094 Register Reg = I.getOperand(i: 0).getReg();
1095 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
1096
1097 LLT ValTy = MRI.getType(Reg);
1098 const auto ValSize = ValTy.getSizeInBits();
1099
1100 assert((ValSize != 64 || STI.hasVFP2Base()) &&
1101 "Don't know how to load/store 64-bit value without VFP");
1102
1103 if (auto *LoadMI = dyn_cast<GLoad>(Val: &I)) {
1104 Register PtrReg = LoadMI->getPointerReg();
1105 MachineInstr *Ptr = MRI.getVRegDef(Reg: PtrReg);
1106 if (Ptr->getOpcode() == TargetOpcode::G_CONSTANT_POOL) {
1107 const MachineOperand &Index = Ptr->getOperand(i: 1);
1108 unsigned Opcode = Subtarget->isThumb() ? ARM::tLDRpci : ARM::LDRcp;
1109
1110 auto Instr = BuildMI(BB&: MBB, I, MIMD: I.getDebugLoc(), MCID: TII.get(Opcode))
1111 .addDef(RegNo: Reg)
1112 .add(MO: Index)
1113 .addImm(Val: 0)
1114 .add(MOs: predOps(Pred: ARMCC::AL))
1115 .addMemOperand(MMO: &MemOp);
1116 constrainSelectedInstRegOperands(I&: *Instr, TII, TRI, RBI);
1117 I.eraseFromParent();
1118 return true;
1119 }
1120 }
1121
1122 const auto NewOpc = selectLoadStoreOpCode(Opc: I.getOpcode(), RegBank, Size: ValSize);
1123 if (NewOpc == G_LOAD || NewOpc == G_STORE)
1124 return false;
1125
1126 I.setDesc(TII.get(Opcode: NewOpc));
1127
1128 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
1129 // LDRH has a funny addressing mode (there's already a FIXME for it).
1130 MIB.addReg(RegNo: 0);
1131 MIB.addImm(Val: 0).add(MOs: predOps(Pred: ARMCC::AL));
1132 break;
1133 }
1134 case G_MERGE_VALUES: {
1135 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI))
1136 return false;
1137 break;
1138 }
1139 case G_UNMERGE_VALUES: {
1140 if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI))
1141 return false;
1142 break;
1143 }
1144 case G_BRCOND: {
1145 if (!validReg(MRI, Reg: I.getOperand(i: 0).getReg(), ExpectedSize: 1, ExpectedRegBankID: ARM::GPRRegBankID)) {
1146 LLVM_DEBUG(dbgs() << "Unsupported condition register for G_BRCOND");
1147 return false;
1148 }
1149
1150 // Set the flags.
1151 auto Test =
1152 BuildMI(BB&: *I.getParent(), I, MIMD: I.getDebugLoc(), MCID: TII.get(Opcode: Opcodes.TSTri))
1153 .addReg(RegNo: I.getOperand(i: 0).getReg())
1154 .addImm(Val: 1)
1155 .add(MOs: predOps(Pred: ARMCC::AL));
1156 constrainSelectedInstRegOperands(I&: *Test, TII, TRI, RBI);
1157
1158 // Branch conditionally.
1159 auto Branch =
1160 BuildMI(BB&: *I.getParent(), I, MIMD: I.getDebugLoc(), MCID: TII.get(Opcode: Opcodes.Bcc))
1161 .add(MO: I.getOperand(i: 1))
1162 .add(MOs: predOps(Pred: ARMCC::NE, PredReg: ARM::CPSR));
1163 constrainSelectedInstRegOperands(I&: *Branch, TII, TRI, RBI);
1164 I.eraseFromParent();
1165 return true;
1166 }
1167 case G_PHI: {
1168 I.setDesc(TII.get(Opcode: PHI));
1169
1170 Register DstReg = I.getOperand(i: 0).getReg();
1171 const TargetRegisterClass *RC = guessRegClass(Reg: DstReg, MRI, TRI, RBI);
1172 if (!RBI.constrainGenericRegister(Reg: DstReg, RC: *RC, MRI)) {
1173 break;
1174 }
1175
1176 return true;
1177 }
1178 default:
1179 return false;
1180 }
1181
1182 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1183 return true;
1184}
1185