1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Base ARM implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15
16#include "ARMBaseRegisterInfo.h"
17#include "MCTargetDesc/ARMBaseInfo.h"
18#include "MCTargetDesc/ARMMCTargetDesc.h"
19#include "llvm/ADT/DenseMap.h"
20#include "llvm/ADT/SmallSet.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/Register.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/IR/IntrinsicInst.h"
29#include "llvm/IR/IntrinsicsARM.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <array>
32#include <cstdint>
33
34#define GET_INSTRINFO_HEADER
35#include "ARMGenInstrInfo.inc"
36
37namespace llvm {
38
39class ARMBaseRegisterInfo;
40class ARMSubtarget;
41
42class ARMBaseInstrInfo : public ARMGenInstrInfo {
43 const ARMSubtarget &Subtarget;
44
45protected:
46 // Can be only subclassed.
47 explicit ARMBaseInstrInfo(const ARMSubtarget &STI,
48 const ARMBaseRegisterInfo &TRI);
49
50 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
51 unsigned LoadImmOpc, unsigned LoadOpc) const;
52
53 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
54 /// and \p DefIdx.
55 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
56 /// the list is modeled as <Reg:SubReg, SubIdx>.
57 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
58 /// two elements:
59 /// - %1:sub1, sub0
60 /// - %2<:0>, sub1
61 ///
62 /// \returns true if it is possible to build such an input sequence
63 /// with the pair \p MI, \p DefIdx. False otherwise.
64 ///
65 /// \pre MI.isRegSequenceLike().
66 bool getRegSequenceLikeInputs(
67 const MachineInstr &MI, unsigned DefIdx,
68 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
69
70 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
71 /// and \p DefIdx.
72 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
73 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
74 /// - %1:sub1, sub0
75 ///
76 /// \returns true if it is possible to build such an input sequence
77 /// with the pair \p MI, \p DefIdx. False otherwise.
78 ///
79 /// \pre MI.isExtractSubregLike().
80 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
81 RegSubRegPairAndIdx &InputReg) const override;
82
83 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
84 /// and \p DefIdx.
85 /// \p [out] BaseReg and \p [out] InsertedReg contain
86 /// the equivalent inputs of INSERT_SUBREG.
87 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
88 /// - BaseReg: %0:sub0
89 /// - InsertedReg: %1:sub1, sub3
90 ///
91 /// \returns true if it is possible to build such an input sequence
92 /// with the pair \p MI, \p DefIdx. False otherwise.
93 ///
94 /// \pre MI.isInsertSubregLike().
95 bool
96 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
97 RegSubRegPair &BaseReg,
98 RegSubRegPairAndIdx &InsertedReg) const override;
99
100 /// Commutes the operands in the given instruction.
101 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
102 ///
103 /// Do not call this method for a non-commutable instruction or for
104 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
105 /// Even though the instruction is commutable, the method may still
106 /// fail to commute the operands, null pointer is returned in such cases.
107 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
108 unsigned OpIdx1,
109 unsigned OpIdx2) const override;
110 /// If the specific machine instruction is an instruction that moves/copies
111 /// value from one register to another register return destination and source
112 /// registers as machine operands.
113 std::optional<DestSourcePair>
114 isCopyInstrImpl(const MachineInstr &MI) const override;
115
116 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
117 /// enhance debug entry value descriptions for ARM targets.
118 std::optional<ParamLoadedValue>
119 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
120
121public:
122 // Return whether the target has an explicit NOP encoding.
123 bool hasNOP() const;
124
125 // Return the non-pre/post incrementing version of 'Opc'. Return 0
126 // if there is not such an opcode.
127 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
128
129 const ARMBaseRegisterInfo &getRegisterInfo() const {
130 return static_cast<const ARMBaseRegisterInfo &>(
131 TargetInstrInfo::getRegisterInfo());
132 }
133
134 const ARMSubtarget &getSubtarget() const { return Subtarget; }
135
136 ScheduleHazardRecognizer *
137 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
138 const ScheduleDAG *DAG) const override;
139
140 ScheduleHazardRecognizer *
141 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
142 const ScheduleDAGMI *DAG) const override;
143
144 ScheduleHazardRecognizer *
145 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
146 const ScheduleDAG *DAG) const override;
147
148 // Branch analysis.
149 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
150 MachineBasicBlock *&FBB,
151 SmallVectorImpl<MachineOperand> &Cond,
152 bool AllowModify = false) const override;
153 unsigned removeBranch(MachineBasicBlock &MBB,
154 int *BytesRemoved = nullptr) const override;
155 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
156 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
157 const DebugLoc &DL,
158 int *BytesAdded = nullptr) const override;
159
160 bool
161 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
162
163 // Predication support.
164 bool isPredicated(const MachineInstr &MI) const override;
165
166 // MIR printer helper function to annotate Operands with a comment.
167 std::string
168 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
169 unsigned OpIdx,
170 const TargetRegisterInfo *TRI) const override;
171
172 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
173 int PIdx = MI.findFirstPredOperandIdx();
174 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(i: PIdx).getImm()
175 : ARMCC::AL;
176 }
177
178 bool PredicateInstruction(MachineInstr &MI,
179 ArrayRef<MachineOperand> Pred) const override;
180
181 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
182 ArrayRef<MachineOperand> Pred2) const override;
183
184 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
185 bool SkipDead) const override;
186
187 bool isPredicable(const MachineInstr &MI) const override;
188
189 // CPSR defined in instruction
190 static bool isCPSRDefined(const MachineInstr &MI);
191
192 /// GetInstSize - Returns the size of the specified MachineInstr.
193 ///
194 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
195
196 Register isLoadFromStackSlot(const MachineInstr &MI,
197 int &FrameIndex) const override;
198 Register isStoreToStackSlot(const MachineInstr &MI,
199 int &FrameIndex) const override;
200 Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
201 int &FrameIndex) const override;
202 Register isStoreToStackSlotPostFE(const MachineInstr &MI,
203 int &FrameIndex) const override;
204
205 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
206 MCRegister SrcReg, bool KillSrc,
207 const ARMSubtarget &Subtarget) const;
208 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
209 MCRegister DestReg, bool KillSrc,
210 const ARMSubtarget &Subtarget) const;
211
212 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
213 const DebugLoc &DL, Register DestReg, Register SrcReg,
214 bool KillSrc, bool RenamableDest = false,
215 bool RenamableSrc = false) const override;
216
217 void storeRegToStackSlot(
218 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
219 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
220 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
221
222 void loadRegFromStackSlot(
223 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
224 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
225 Register VReg, unsigned SubReg = 0,
226 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
227
228 bool expandPostRAPseudo(MachineInstr &MI) const override;
229
230 bool shouldSink(const MachineInstr &MI) const override;
231
232 void
233 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
234 Register DestReg, unsigned SubIdx, const MachineInstr &Orig,
235 LaneBitmask UsedLanes = LaneBitmask::getAll()) const override;
236
237 MachineInstr &
238 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
239 const MachineInstr &Orig) const override;
240
241 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
242 unsigned SubIdx, RegState State) const;
243
244 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
245 const MachineRegisterInfo *MRI) const override;
246
247 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
248 /// determine if two loads are loading from the same base address. It should
249 /// only return true if the base pointers are the same and the only
250 /// differences between the two addresses is the offset. It also returns the
251 /// offsets by reference.
252 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
253 int64_t &Offset2) const override;
254
255 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
256 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
257 /// should be scheduled togther. On some targets if two loads are loading from
258 /// addresses in the same cache line, it's better if they are scheduled
259 /// together. This function takes two integers that represent the load offsets
260 /// from the common base address. It returns true if it decides it's desirable
261 /// to schedule the two loads together. "NumLoads" is the number of loads that
262 /// have already been scheduled after Load1.
263 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
264 int64_t Offset1, int64_t Offset2,
265 unsigned NumLoads) const override;
266
267 bool isSchedulingBoundary(const MachineInstr &MI,
268 const MachineBasicBlock *MBB,
269 const MachineFunction &MF) const override;
270
271 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
272 unsigned NumCycles, unsigned ExtraPredCycles,
273 BranchProbability Probability) const override;
274
275 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
276 unsigned ExtraT, MachineBasicBlock &FMBB,
277 unsigned NumF, unsigned ExtraF,
278 BranchProbability Probability) const override;
279
280 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
281 BranchProbability Probability) const override {
282 return NumCycles == 1;
283 }
284
285 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
286 unsigned NumInsts) const override;
287 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
288
289 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
290 MachineBasicBlock &FMBB) const override;
291
292 /// analyzeCompare - For a comparison instruction, return the source registers
293 /// in SrcReg and SrcReg2 if having two register operands, and the value it
294 /// compares against in CmpValue. Return true if the comparison instruction
295 /// can be analyzed.
296 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
297 Register &SrcReg2, int64_t &CmpMask,
298 int64_t &CmpValue) const override;
299
300 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
301 /// that we can remove a "comparison with zero"; Remove a redundant CMP
302 /// instruction if the flags can be updated in the same way by an earlier
303 /// instruction such as SUB.
304 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
305 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
306 const MachineRegisterInfo *MRI) const override;
307
308 MachineInstr *optimizeSelect(MachineInstr &MI,
309 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
310 bool) const override;
311
312 /// foldImmediate - 'Reg' is known to be defined by a move immediate
313 /// instruction, try to fold the immediate into the use instruction.
314 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
315 MachineRegisterInfo *MRI) const override;
316
317 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
318 const MachineInstr &MI) const override;
319
320 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
321 const MachineInstr &DefMI,
322 unsigned DefIdx,
323 const MachineInstr &UseMI,
324 unsigned UseIdx) const override;
325 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
326 SDNode *DefNode, unsigned DefIdx,
327 SDNode *UseNode,
328 unsigned UseIdx) const override;
329
330 /// VFP/NEON execution domains.
331 std::pair<uint16_t, uint16_t>
332 getExecutionDomain(const MachineInstr &MI) const override;
333 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
334
335 unsigned
336 getPartialRegUpdateClearance(const MachineInstr &, unsigned,
337 const TargetRegisterInfo *) const override;
338 void breakPartialRegDependency(MachineInstr &, unsigned,
339 const TargetRegisterInfo *TRI) const override;
340
341 /// Get the number of addresses by LDM or VLDM or zero for unknown.
342 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
343
344 std::pair<unsigned, unsigned>
345 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
346 ArrayRef<std::pair<unsigned, const char *>>
347 getSerializableDirectMachineOperandTargetFlags() const override;
348 ArrayRef<std::pair<unsigned, const char *>>
349 getSerializableBitmaskMachineOperandTargetFlags() const override;
350
351 /// ARM supports the MachineOutliner.
352 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
353 bool OutlineFromLinkOnceODRs) const override;
354 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
355 getOutliningCandidateInfo(
356 const MachineModuleInfo &MMI,
357 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
358 unsigned MinRepeats) const override;
359 void mergeOutliningCandidateAttributes(
360 Function &F, std::vector<outliner::Candidate> &Candidates) const override;
361 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
362 MachineBasicBlock::iterator &MIT,
363 unsigned Flags) const override;
364 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
365 unsigned &Flags) const override;
366 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
367 const outliner::OutlinedFunction &OF) const override;
368 MachineBasicBlock::iterator
369 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
370 MachineBasicBlock::iterator &It, MachineFunction &MF,
371 outliner::Candidate &C) const override;
372
373 /// Enable outlining by default at -Oz.
374 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
375
376 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
377 return MI->getOpcode() == ARM::t2LoopEndDec ||
378 MI->getOpcode() == ARM::t2DoLoopStartTP ||
379 MI->getOpcode() == ARM::t2WhileLoopStartLR ||
380 MI->getOpcode() == ARM::t2WhileLoopStartTP;
381 }
382
383 /// Analyze loop L, which must be a single-basic-block loop, and if the
384 /// conditions can be understood enough produce a PipelinerLoopInfo object.
385 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
386 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
387
388private:
389 /// Returns an unused general-purpose register which can be used for
390 /// constructing an outlined call if one exists. Returns 0 otherwise.
391 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
392
393 /// Adds an instruction which saves the link register on top of the stack into
394 /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true,
395 /// compute and store an authentication code alongiside the link register.
396 /// If \p CFI is true, emit CFI instructions.
397 void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
398 bool CFI, bool Auth) const;
399
400 /// Adds an instruction which restores the link register from the top the
401 /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is
402 /// true, restore an authentication code and authenticate LR.
403 /// If \p CFI is true, emit CFI instructions.
404 void restoreLRFromStack(MachineBasicBlock &MBB,
405 MachineBasicBlock::iterator It, bool CFI,
406 bool Auth) const;
407
408 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
409 /// so that they will be valid post-outlining.
410 ///
411 /// \param MBB A \p MachineBasicBlock in an outlined function.
412 void fixupPostOutline(MachineBasicBlock &MBB) const;
413
414 /// Returns true if the machine instruction offset can handle the stack fixup
415 /// and updates it if requested.
416 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
417 bool Updt) const;
418
419 std::optional<unsigned> getVLDMDefCycle(const InstrItineraryData *ItinData,
420 const MCInstrDesc &DefMCID,
421 unsigned DefClass, unsigned DefIdx,
422 unsigned DefAlign) const;
423 std::optional<unsigned> getLDMDefCycle(const InstrItineraryData *ItinData,
424 const MCInstrDesc &DefMCID,
425 unsigned DefClass, unsigned DefIdx,
426 unsigned DefAlign) const;
427 std::optional<unsigned> getVSTMUseCycle(const InstrItineraryData *ItinData,
428 const MCInstrDesc &UseMCID,
429 unsigned UseClass, unsigned UseIdx,
430 unsigned UseAlign) const;
431 std::optional<unsigned> getSTMUseCycle(const InstrItineraryData *ItinData,
432 const MCInstrDesc &UseMCID,
433 unsigned UseClass, unsigned UseIdx,
434 unsigned UseAlign) const;
435 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
436 const MCInstrDesc &DefMCID,
437 unsigned DefIdx, unsigned DefAlign,
438 const MCInstrDesc &UseMCID,
439 unsigned UseIdx,
440 unsigned UseAlign) const;
441
442 std::optional<unsigned> getOperandLatencyImpl(
443 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
444 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
445 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
446 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
447
448 unsigned getPredicationCost(const MachineInstr &MI) const override;
449
450 unsigned getInstrLatency(const InstrItineraryData *ItinData,
451 const MachineInstr &MI,
452 unsigned *PredCost = nullptr) const override;
453
454 unsigned getInstrLatency(const InstrItineraryData *ItinData,
455 SDNode *Node) const override;
456
457 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
458 const MachineRegisterInfo *MRI,
459 const MachineInstr &DefMI, unsigned DefIdx,
460 const MachineInstr &UseMI,
461 unsigned UseIdx) const override;
462 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
463 const MachineInstr &DefMI,
464 unsigned DefIdx) const override;
465
466 /// verifyInstruction - Perform target specific instruction verification.
467 bool verifyInstruction(const MachineInstr &MI,
468 StringRef &ErrInfo) const override;
469
470 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
471
472 void expandMEMCPY(MachineBasicBlock::iterator) const;
473
474 /// Identify instructions that can be folded into a MOVCC instruction, and
475 /// return the defining instruction.
476 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
477 const TargetInstrInfo *TII) const;
478
479 bool isReMaterializableImpl(const MachineInstr &MI) const override;
480
481private:
482 /// Modeling special VFP / NEON fp MLA / MLS hazards.
483
484 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
485 /// MLx table.
486 DenseMap<unsigned, unsigned> MLxEntryMap;
487
488 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
489 /// stalls when scheduled together with fp MLA / MLS opcodes.
490 SmallSet<unsigned, 16> MLxHazardOpcodes;
491
492public:
493 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
494 /// instruction.
495 bool isFpMLxInstruction(unsigned Opcode) const {
496 return MLxEntryMap.count(Val: Opcode);
497 }
498
499 /// isFpMLxInstruction - This version also returns the multiply opcode and the
500 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
501 /// the MLX instructions with an extra lane operand.
502 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
503 unsigned &AddSubOpc, bool &NegAcc,
504 bool &HasLane) const;
505
506 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
507 /// will cause stalls when scheduled after (within 4-cycle window) a fp
508 /// MLA / MLS instruction.
509 bool canCauseFpMLxStall(unsigned Opcode) const {
510 return MLxHazardOpcodes.count(V: Opcode);
511 }
512
513 /// Returns true if the instruction has a shift by immediate that can be
514 /// executed in one cycle less.
515 bool isSwiftFastImmShift(const MachineInstr *MI) const;
516
517 /// Returns predicate register associated with the given frame instruction.
518 unsigned getFramePred(const MachineInstr &MI) const {
519 assert(isFrameInstr(MI));
520 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
521 // - argument declared in the pattern:
522 // 0 - frame size
523 // 1 - arg of CALLSEQ_START/CALLSEQ_END
524 // 2 - predicate code (like ARMCC::AL)
525 // - added by predOps:
526 // 3 - predicate reg
527 return MI.getOperand(i: 3).getReg();
528 }
529
530 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
531 Register Reg) const override;
532};
533
534/// Get the operands corresponding to the given \p Pred value. By default, the
535/// predicate register is assumed to be 0 (no register), but you can pass in a
536/// \p PredReg if that is not the case.
537static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
538 unsigned PredReg = 0) {
539 return {._M_elems: {MachineOperand::CreateImm(Val: static_cast<int64_t>(Pred)),
540 MachineOperand::CreateReg(Reg: PredReg, isDef: false)}};
541}
542
543/// Get the operand corresponding to the conditional code result. By default,
544/// this is 0 (no register).
545static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
546 return MachineOperand::CreateReg(Reg: CCReg, isDef: false);
547}
548
549/// Get the operand corresponding to the conditional code result for Thumb1.
550/// This operand will always refer to CPSR and it will have the Define flag set.
551/// You can optionally set the Dead flag by means of \p isDead.
552static inline MachineOperand t1CondCodeOp(bool isDead = false) {
553 return MachineOperand::CreateReg(Reg: ARM::CPSR,
554 /*Define*/ isDef: true, /*Implicit*/ isImp: false,
555 /*Kill*/ isKill: false, isDead);
556}
557
558static inline
559bool isUncondBranchOpcode(int Opc) {
560 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
561}
562
563// This table shows the VPT instruction variants, i.e. the different
564// mask field encodings, see also B5.6. Predication/conditional execution in
565// the ArmARM.
566static inline bool isVPTOpcode(int Opc) {
567 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
568 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
569 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
570 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
571 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
572 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
573 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
574 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
575 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
576 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
577 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
578 Opc == ARM::MVE_VPST;
579}
580
581static inline
582unsigned VCMPOpcodeToVPT(unsigned Opcode) {
583 switch (Opcode) {
584 default:
585 return 0;
586 case ARM::MVE_VCMPf32:
587 return ARM::MVE_VPTv4f32;
588 case ARM::MVE_VCMPf16:
589 return ARM::MVE_VPTv8f16;
590 case ARM::MVE_VCMPi8:
591 return ARM::MVE_VPTv16i8;
592 case ARM::MVE_VCMPi16:
593 return ARM::MVE_VPTv8i16;
594 case ARM::MVE_VCMPi32:
595 return ARM::MVE_VPTv4i32;
596 case ARM::MVE_VCMPu8:
597 return ARM::MVE_VPTv16u8;
598 case ARM::MVE_VCMPu16:
599 return ARM::MVE_VPTv8u16;
600 case ARM::MVE_VCMPu32:
601 return ARM::MVE_VPTv4u32;
602 case ARM::MVE_VCMPs8:
603 return ARM::MVE_VPTv16s8;
604 case ARM::MVE_VCMPs16:
605 return ARM::MVE_VPTv8s16;
606 case ARM::MVE_VCMPs32:
607 return ARM::MVE_VPTv4s32;
608
609 case ARM::MVE_VCMPf32r:
610 return ARM::MVE_VPTv4f32r;
611 case ARM::MVE_VCMPf16r:
612 return ARM::MVE_VPTv8f16r;
613 case ARM::MVE_VCMPi8r:
614 return ARM::MVE_VPTv16i8r;
615 case ARM::MVE_VCMPi16r:
616 return ARM::MVE_VPTv8i16r;
617 case ARM::MVE_VCMPi32r:
618 return ARM::MVE_VPTv4i32r;
619 case ARM::MVE_VCMPu8r:
620 return ARM::MVE_VPTv16u8r;
621 case ARM::MVE_VCMPu16r:
622 return ARM::MVE_VPTv8u16r;
623 case ARM::MVE_VCMPu32r:
624 return ARM::MVE_VPTv4u32r;
625 case ARM::MVE_VCMPs8r:
626 return ARM::MVE_VPTv16s8r;
627 case ARM::MVE_VCMPs16r:
628 return ARM::MVE_VPTv8s16r;
629 case ARM::MVE_VCMPs32r:
630 return ARM::MVE_VPTv4s32r;
631 }
632}
633
634static inline
635bool isCondBranchOpcode(int Opc) {
636 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
637}
638
639static inline bool isJumpTableBranchOpcode(int Opc) {
640 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
641 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
642 Opc == ARM::t2BR_JT;
643}
644
645static inline
646bool isIndirectBranchOpcode(int Opc) {
647 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
648}
649
650static inline bool isIndirectCall(const MachineInstr &MI) {
651 int Opc = MI.getOpcode();
652 switch (Opc) {
653 // indirect calls:
654 case ARM::BLX:
655 case ARM::BLX_noip:
656 case ARM::BLX_pred:
657 case ARM::BLX_pred_noip:
658 case ARM::BX_CALL:
659 case ARM::BMOVPCRX_CALL:
660 case ARM::TCRETURNri:
661 case ARM::TCRETURNrinotr12:
662 case ARM::TAILJMPr:
663 case ARM::TAILJMPr4:
664 case ARM::tBLXr:
665 case ARM::tBLXr_noip:
666 case ARM::tBLXNSr:
667 case ARM::tBLXNS_CALL:
668 case ARM::tBX_CALL:
669 case ARM::tTAILJMPr:
670 assert(MI.isCall(MachineInstr::IgnoreBundle));
671 return true;
672 // direct calls:
673 case ARM::BL:
674 case ARM::BL_pred:
675 case ARM::BMOVPCB_CALL:
676 case ARM::BL_PUSHLR:
677 case ARM::BLXi:
678 case ARM::TCRETURNdi:
679 case ARM::TAILJMPd:
680 case ARM::SVC:
681 case ARM::HVC:
682 case ARM::TPsoft:
683 case ARM::tTAILJMPd:
684 case ARM::t2SMC:
685 case ARM::t2HVC:
686 case ARM::tBL:
687 case ARM::tBLXi:
688 case ARM::tBL_PUSHLR:
689 case ARM::tTAILJMPdND:
690 case ARM::tSVC:
691 case ARM::tTPsoft:
692 assert(MI.isCall(MachineInstr::IgnoreBundle));
693 return false;
694 }
695 assert(!MI.isCall(MachineInstr::IgnoreBundle));
696 return false;
697}
698
699static inline bool isIndirectControlFlowNotComingBack(const MachineInstr &MI) {
700 int opc = MI.getOpcode();
701 return MI.isReturn() || isIndirectBranchOpcode(Opc: MI.getOpcode()) ||
702 isJumpTableBranchOpcode(Opc: opc);
703}
704
705static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
706 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
707 Opc == ARM::SpeculationBarrierSBEndBB ||
708 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
709 Opc == ARM::t2SpeculationBarrierSBEndBB;
710}
711
712static inline bool isPopOpcode(int Opc) {
713 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
714 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
715 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
716}
717
718static inline bool isPushOpcode(int Opc) {
719 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
720 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
721}
722
723static inline bool isSubImmOpcode(int Opc) {
724 return Opc == ARM::SUBri ||
725 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
726 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
727 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
728}
729
730static inline bool isMovRegOpcode(int Opc) {
731 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
732}
733/// isValidCoprocessorNumber - decide whether an explicit coprocessor
734/// number is legal in generic instructions like CDP. The answer can
735/// vary with the subtarget.
736static inline bool isValidCoprocessorNumber(unsigned Num,
737 const FeatureBitset& featureBits) {
738 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
739 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
740 // useful for code which is shared with older architectures which do not know
741 // the new VFP/NEON mnemonics.
742
743 // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
744 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
745 return false;
746
747 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
748 // which clash with MVE.
749 if (featureBits[ARM::HasV8_1MMainlineOps] &&
750 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
751 return false;
752
753 return true;
754}
755
756static inline bool isSEHInstruction(const MachineInstr &MI) {
757 unsigned Opc = MI.getOpcode();
758 switch (Opc) {
759 case ARM::SEH_StackAlloc:
760 case ARM::SEH_SaveRegs:
761 case ARM::SEH_SaveRegs_Ret:
762 case ARM::SEH_SaveSP:
763 case ARM::SEH_SaveFRegs:
764 case ARM::SEH_SaveLR:
765 case ARM::SEH_Nop:
766 case ARM::SEH_Nop_Ret:
767 case ARM::SEH_PrologEnd:
768 case ARM::SEH_EpilogStart:
769 case ARM::SEH_EpilogEnd:
770 return true;
771 default:
772 return false;
773 }
774}
775
776/// getInstrPredicate - If instruction is predicated, returns its predicate
777/// condition, otherwise returns AL. It also returns the condition code
778/// register by reference.
779ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
780
781unsigned getMatchingCondBranchOpcode(unsigned Opc);
782
783/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
784/// the instruction is encoded with an 'S' bit is determined by the optional
785/// CPSR def operand.
786unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
787
788/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
789/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
790/// code.
791void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
792 MachineBasicBlock::iterator &MBBI,
793 const DebugLoc &dl, Register DestReg,
794 Register BaseReg, int NumBytes,
795 ARMCC::CondCodes Pred, Register PredReg,
796 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
797
798void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
799 MachineBasicBlock::iterator &MBBI,
800 const DebugLoc &dl, Register DestReg,
801 Register BaseReg, int NumBytes,
802 ARMCC::CondCodes Pred, Register PredReg,
803 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
804void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
805 MachineBasicBlock::iterator &MBBI,
806 const DebugLoc &dl, Register DestReg,
807 Register BaseReg, int NumBytes,
808 const TargetInstrInfo &TII,
809 const ARMBaseRegisterInfo &MRI,
810 unsigned MIFlags = 0);
811
812/// Tries to add registers to the reglist of a given base-updating
813/// push/pop instruction to adjust the stack by an additional
814/// NumBytes. This can save a few bytes per function in code-size, but
815/// obviously generates more memory traffic. As such, it only takes
816/// effect in functions being optimised for size.
817bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
818 MachineFunction &MF, MachineInstr *MI,
819 unsigned NumBytes);
820
821/// rewriteARMFrameIndex / rewriteT2FrameIndex -
822/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
823/// offset could not be handled directly in MI, and return the left-over
824/// portion by reference.
825bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
826 Register FrameReg, int &Offset,
827 const ARMBaseInstrInfo &TII);
828
829bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
830 Register FrameReg, int &Offset,
831 const ARMBaseInstrInfo &TII,
832 const TargetRegisterInfo *TRI);
833
834/// Return true if Reg is defd between From and To
835bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From,
836 MachineBasicBlock::iterator To,
837 const TargetRegisterInfo *TRI);
838
839/// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
840/// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
841MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
842 const TargetRegisterInfo *TRI);
843
844void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
845void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
846
847void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
848void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
849 unsigned Inactive);
850
851/// Returns the number of instructions required to materialize the given
852/// constant in a register, or 3 if a literal pool load is needed.
853/// If ForCodesize is specified, an approximate cost in bytes is returned.
854unsigned ConstantMaterializationCost(unsigned Val,
855 const ARMSubtarget *Subtarget,
856 bool ForCodesize = false);
857
858/// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
859/// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
860/// specified. If the scores are equal, return the comparison for !ForCodesize.
861bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
862 const ARMSubtarget *Subtarget,
863 bool ForCodesize = false);
864
865// Return the immediate if this is ADDri or SUBri, scaled as appropriate.
866// Returns 0 for unknown instructions.
867inline int getAddSubImmediate(MachineInstr &MI) {
868 int Scale = 1;
869 unsigned ImmOp;
870 switch (MI.getOpcode()) {
871 case ARM::t2ADDri:
872 ImmOp = 2;
873 break;
874 case ARM::t2SUBri:
875 case ARM::t2SUBri12:
876 ImmOp = 2;
877 Scale = -1;
878 break;
879 case ARM::tSUBi3:
880 case ARM::tSUBi8:
881 ImmOp = 3;
882 Scale = -1;
883 break;
884 default:
885 return 0;
886 }
887 return Scale * MI.getOperand(i: ImmOp).getImm();
888}
889
890// Given a memory access Opcode, check that the give Imm would be a valid Offset
891// for this instruction using its addressing mode.
892inline bool isLegalAddressImm(unsigned Opcode, int Imm,
893 const TargetInstrInfo *TII) {
894 const MCInstrDesc &Desc = TII->get(Opcode);
895 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
896 switch (AddrMode) {
897 case ARMII::AddrModeT2_i7:
898 return std::abs(x: Imm) < ((1 << 7) * 1);
899 case ARMII::AddrModeT2_i7s2:
900 return std::abs(x: Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
901 case ARMII::AddrModeT2_i7s4:
902 return std::abs(x: Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
903 case ARMII::AddrModeT2_i8:
904 return std::abs(x: Imm) < ((1 << 8) * 1);
905 case ARMII::AddrModeT2_i8pos:
906 return Imm >= 0 && Imm < ((1 << 8) * 1);
907 case ARMII::AddrModeT2_i8neg:
908 return Imm < 0 && -Imm < ((1 << 8) * 1);
909 case ARMII::AddrModeT2_i8s4:
910 return std::abs(x: Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
911 case ARMII::AddrModeT2_i12:
912 return Imm >= 0 && Imm < ((1 << 12) * 1);
913 case ARMII::AddrMode2:
914 return std::abs(x: Imm) < ((1 << 12) * 1);
915 default:
916 llvm_unreachable("Unhandled Addressing mode");
917 }
918}
919
920// Return true if the given intrinsic is a gather
921inline bool isGather(IntrinsicInst *IntInst) {
922 if (IntInst == nullptr)
923 return false;
924 unsigned IntrinsicID = IntInst->getIntrinsicID();
925 return (IntrinsicID == Intrinsic::masked_gather ||
926 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
927 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
928 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
929 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
930 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
931 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
932}
933
934// Return true if the given intrinsic is a scatter
935inline bool isScatter(IntrinsicInst *IntInst) {
936 if (IntInst == nullptr)
937 return false;
938 unsigned IntrinsicID = IntInst->getIntrinsicID();
939 return (IntrinsicID == Intrinsic::masked_scatter ||
940 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
941 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
942 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
943 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
944 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
945 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
946}
947
948// Return true if the given intrinsic is a gather or scatter
949inline bool isGatherScatter(IntrinsicInst *IntInst) {
950 if (IntInst == nullptr)
951 return false;
952 return isGather(IntInst) || isScatter(IntInst);
953}
954
955unsigned getBLXOpcode(const MachineFunction &MF);
956unsigned gettBLXrOpcode(const MachineFunction &MF);
957unsigned getBLXpredOpcode(const MachineFunction &MF);
958
959inline bool isMVEVectorInstruction(const MachineInstr *MI) {
960 // This attempts to remove non-mve instructions (scalar shifts), which
961 // are just DPU CX instruction.
962 switch (MI->getOpcode()) {
963 case ARM::MVE_SQSHL:
964 case ARM::MVE_SRSHR:
965 case ARM::MVE_UQSHL:
966 case ARM::MVE_URSHR:
967 case ARM::MVE_SQRSHR:
968 case ARM::MVE_UQRSHL:
969 case ARM::MVE_ASRLr:
970 case ARM::MVE_ASRLi:
971 case ARM::MVE_LSLLr:
972 case ARM::MVE_LSLLi:
973 case ARM::MVE_LSRL:
974 case ARM::MVE_SQRSHRL:
975 case ARM::MVE_SQSHLL:
976 case ARM::MVE_SRSHRL:
977 case ARM::MVE_UQRSHLL:
978 case ARM::MVE_UQSHLL:
979 case ARM::MVE_URSHRL:
980 return false;
981 }
982 const MCInstrDesc &MCID = MI->getDesc();
983 uint64_t Flags = MCID.TSFlags;
984 return (Flags & ARMII::DomainMask) == ARMII::DomainMVE;
985}
986
987} // end namespace llvm
988
989#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
990