1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Base ARM implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15
16#include "ARMBaseRegisterInfo.h"
17#include "MCTargetDesc/ARMBaseInfo.h"
18#include "MCTargetDesc/ARMMCTargetDesc.h"
19#include "llvm/ADT/DenseMap.h"
20#include "llvm/ADT/SmallSet.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/Register.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/IR/IntrinsicInst.h"
29#include "llvm/IR/IntrinsicsARM.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <array>
32#include <cstdint>
33
34#define GET_INSTRINFO_HEADER
35#include "ARMGenInstrInfo.inc"
36
37namespace llvm {
38
39class ARMBaseRegisterInfo;
40class ARMSubtarget;
41
42class ARMBaseInstrInfo : public ARMGenInstrInfo {
43 const ARMSubtarget &Subtarget;
44
45protected:
46 // Can be only subclassed.
47 explicit ARMBaseInstrInfo(const ARMSubtarget &STI,
48 const ARMBaseRegisterInfo &TRI);
49
50 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
51 unsigned LoadImmOpc, unsigned LoadOpc) const;
52
53 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
54 /// and \p DefIdx.
55 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
56 /// the list is modeled as <Reg:SubReg, SubIdx>.
57 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
58 /// two elements:
59 /// - %1:sub1, sub0
60 /// - %2<:0>, sub1
61 ///
62 /// \returns true if it is possible to build such an input sequence
63 /// with the pair \p MI, \p DefIdx. False otherwise.
64 ///
65 /// \pre MI.isRegSequenceLike().
66 bool getRegSequenceLikeInputs(
67 const MachineInstr &MI, unsigned DefIdx,
68 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
69
70 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
71 /// and \p DefIdx.
72 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
73 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
74 /// - %1:sub1, sub0
75 ///
76 /// \returns true if it is possible to build such an input sequence
77 /// with the pair \p MI, \p DefIdx. False otherwise.
78 ///
79 /// \pre MI.isExtractSubregLike().
80 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
81 RegSubRegPairAndIdx &InputReg) const override;
82
83 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
84 /// and \p DefIdx.
85 /// \p [out] BaseReg and \p [out] InsertedReg contain
86 /// the equivalent inputs of INSERT_SUBREG.
87 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
88 /// - BaseReg: %0:sub0
89 /// - InsertedReg: %1:sub1, sub3
90 ///
91 /// \returns true if it is possible to build such an input sequence
92 /// with the pair \p MI, \p DefIdx. False otherwise.
93 ///
94 /// \pre MI.isInsertSubregLike().
95 bool
96 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
97 RegSubRegPair &BaseReg,
98 RegSubRegPairAndIdx &InsertedReg) const override;
99
100 /// Commutes the operands in the given instruction.
101 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
102 ///
103 /// Do not call this method for a non-commutable instruction or for
104 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
105 /// Even though the instruction is commutable, the method may still
106 /// fail to commute the operands, null pointer is returned in such cases.
107 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
108 unsigned OpIdx1,
109 unsigned OpIdx2) const override;
110 /// If the specific machine instruction is an instruction that moves/copies
111 /// value from one register to another register return destination and source
112 /// registers as machine operands.
113 std::optional<DestSourcePair>
114 isCopyInstrImpl(const MachineInstr &MI) const override;
115
116 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
117 /// enhance debug entry value descriptions for ARM targets.
118 std::optional<ParamLoadedValue>
119 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
120
121public:
122 // Return whether the target has an explicit NOP encoding.
123 bool hasNOP() const;
124
125 // Return the non-pre/post incrementing version of 'Opc'. Return 0
126 // if there is not such an opcode.
127 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
128
129 const ARMBaseRegisterInfo &getRegisterInfo() const {
130 return static_cast<const ARMBaseRegisterInfo &>(
131 TargetInstrInfo::getRegisterInfo());
132 }
133
134 const ARMSubtarget &getSubtarget() const { return Subtarget; }
135
136 ScheduleHazardRecognizer *
137 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
138 const ScheduleDAG *DAG) const override;
139
140 ScheduleHazardRecognizer *
141 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
142 const ScheduleDAGMI *DAG) const override;
143
144 ScheduleHazardRecognizer *
145 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
146 const ScheduleDAG *DAG) const override;
147
148 // Branch analysis.
149 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
150 MachineBasicBlock *&FBB,
151 SmallVectorImpl<MachineOperand> &Cond,
152 bool AllowModify = false) const override;
153 unsigned removeBranch(MachineBasicBlock &MBB,
154 int *BytesRemoved = nullptr) const override;
155 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
156 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
157 const DebugLoc &DL,
158 int *BytesAdded = nullptr) const override;
159
160 bool
161 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
162
163 // Predication support.
164 bool isPredicated(const MachineInstr &MI) const override;
165
166 // MIR printer helper function to annotate Operands with a comment.
167 std::string
168 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
169 unsigned OpIdx,
170 const TargetRegisterInfo *TRI) const override;
171
172 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
173 int PIdx = MI.findFirstPredOperandIdx();
174 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(i: PIdx).getImm()
175 : ARMCC::AL;
176 }
177
178 bool PredicateInstruction(MachineInstr &MI,
179 ArrayRef<MachineOperand> Pred) const override;
180
181 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
182 ArrayRef<MachineOperand> Pred2) const override;
183
184 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
185 bool SkipDead) const override;
186
187 bool isPredicable(const MachineInstr &MI) const override;
188
189 // CPSR defined in instruction
190 static bool isCPSRDefined(const MachineInstr &MI);
191
192 /// GetInstSize - Returns the size of the specified MachineInstr.
193 ///
194 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
195
196 Register isLoadFromStackSlot(const MachineInstr &MI,
197 int &FrameIndex) const override;
198 Register isStoreToStackSlot(const MachineInstr &MI,
199 int &FrameIndex) const override;
200 Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
201 int &FrameIndex) const override;
202 Register isStoreToStackSlotPostFE(const MachineInstr &MI,
203 int &FrameIndex) const override;
204
205 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
206 MCRegister SrcReg, bool KillSrc,
207 const ARMSubtarget &Subtarget) const;
208 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
209 MCRegister DestReg, bool KillSrc,
210 const ARMSubtarget &Subtarget) const;
211
212 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
213 const DebugLoc &DL, Register DestReg, Register SrcReg,
214 bool KillSrc, bool RenamableDest = false,
215 bool RenamableSrc = false) const override;
216
217 void storeRegToStackSlot(
218 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
219 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
220 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
221
222 void loadRegFromStackSlot(
223 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
224 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
225 Register VReg, unsigned SubReg = 0,
226 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
227
228 bool expandPostRAPseudo(MachineInstr &MI) const override;
229
230 bool shouldSink(const MachineInstr &MI) const override;
231
232 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
233 Register DestReg, unsigned SubIdx,
234 const MachineInstr &Orig) const override;
235
236 MachineInstr &
237 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
238 const MachineInstr &Orig) const override;
239
240 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
241 unsigned SubIdx, RegState State) const;
242
243 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
244 const MachineRegisterInfo *MRI) const override;
245
246 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
247 /// determine if two loads are loading from the same base address. It should
248 /// only return true if the base pointers are the same and the only
249 /// differences between the two addresses is the offset. It also returns the
250 /// offsets by reference.
251 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
252 int64_t &Offset2) const override;
253
254 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
255 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
256 /// should be scheduled togther. On some targets if two loads are loading from
257 /// addresses in the same cache line, it's better if they are scheduled
258 /// together. This function takes two integers that represent the load offsets
259 /// from the common base address. It returns true if it decides it's desirable
260 /// to schedule the two loads together. "NumLoads" is the number of loads that
261 /// have already been scheduled after Load1.
262 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
263 int64_t Offset1, int64_t Offset2,
264 unsigned NumLoads) const override;
265
266 bool isSchedulingBoundary(const MachineInstr &MI,
267 const MachineBasicBlock *MBB,
268 const MachineFunction &MF) const override;
269
270 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
271 unsigned NumCycles, unsigned ExtraPredCycles,
272 BranchProbability Probability) const override;
273
274 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
275 unsigned ExtraT, MachineBasicBlock &FMBB,
276 unsigned NumF, unsigned ExtraF,
277 BranchProbability Probability) const override;
278
279 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
280 BranchProbability Probability) const override {
281 return NumCycles == 1;
282 }
283
284 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
285 unsigned NumInsts) const override;
286 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
287
288 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
289 MachineBasicBlock &FMBB) const override;
290
291 /// analyzeCompare - For a comparison instruction, return the source registers
292 /// in SrcReg and SrcReg2 if having two register operands, and the value it
293 /// compares against in CmpValue. Return true if the comparison instruction
294 /// can be analyzed.
295 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
296 Register &SrcReg2, int64_t &CmpMask,
297 int64_t &CmpValue) const override;
298
299 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
300 /// that we can remove a "comparison with zero"; Remove a redundant CMP
301 /// instruction if the flags can be updated in the same way by an earlier
302 /// instruction such as SUB.
303 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
304 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
305 const MachineRegisterInfo *MRI) const override;
306
307 MachineInstr *optimizeSelect(MachineInstr &MI,
308 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
309 bool) const override;
310
311 /// foldImmediate - 'Reg' is known to be defined by a move immediate
312 /// instruction, try to fold the immediate into the use instruction.
313 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
314 MachineRegisterInfo *MRI) const override;
315
316 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
317 const MachineInstr &MI) const override;
318
319 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
320 const MachineInstr &DefMI,
321 unsigned DefIdx,
322 const MachineInstr &UseMI,
323 unsigned UseIdx) const override;
324 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
325 SDNode *DefNode, unsigned DefIdx,
326 SDNode *UseNode,
327 unsigned UseIdx) const override;
328
329 /// VFP/NEON execution domains.
330 std::pair<uint16_t, uint16_t>
331 getExecutionDomain(const MachineInstr &MI) const override;
332 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
333
334 unsigned
335 getPartialRegUpdateClearance(const MachineInstr &, unsigned,
336 const TargetRegisterInfo *) const override;
337 void breakPartialRegDependency(MachineInstr &, unsigned,
338 const TargetRegisterInfo *TRI) const override;
339
340 /// Get the number of addresses by LDM or VLDM or zero for unknown.
341 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
342
343 std::pair<unsigned, unsigned>
344 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
345 ArrayRef<std::pair<unsigned, const char *>>
346 getSerializableDirectMachineOperandTargetFlags() const override;
347 ArrayRef<std::pair<unsigned, const char *>>
348 getSerializableBitmaskMachineOperandTargetFlags() const override;
349
350 /// ARM supports the MachineOutliner.
351 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
352 bool OutlineFromLinkOnceODRs) const override;
353 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
354 getOutliningCandidateInfo(
355 const MachineModuleInfo &MMI,
356 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
357 unsigned MinRepeats) const override;
358 void mergeOutliningCandidateAttributes(
359 Function &F, std::vector<outliner::Candidate> &Candidates) const override;
360 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
361 MachineBasicBlock::iterator &MIT,
362 unsigned Flags) const override;
363 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
364 unsigned &Flags) const override;
365 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
366 const outliner::OutlinedFunction &OF) const override;
367 MachineBasicBlock::iterator
368 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
369 MachineBasicBlock::iterator &It, MachineFunction &MF,
370 outliner::Candidate &C) const override;
371
372 /// Enable outlining by default at -Oz.
373 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
374
375 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
376 return MI->getOpcode() == ARM::t2LoopEndDec ||
377 MI->getOpcode() == ARM::t2DoLoopStartTP ||
378 MI->getOpcode() == ARM::t2WhileLoopStartLR ||
379 MI->getOpcode() == ARM::t2WhileLoopStartTP;
380 }
381
382 /// Analyze loop L, which must be a single-basic-block loop, and if the
383 /// conditions can be understood enough produce a PipelinerLoopInfo object.
384 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
385 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
386
387private:
388 /// Returns an unused general-purpose register which can be used for
389 /// constructing an outlined call if one exists. Returns 0 otherwise.
390 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
391
392 /// Adds an instruction which saves the link register on top of the stack into
393 /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true,
394 /// compute and store an authentication code alongiside the link register.
395 /// If \p CFI is true, emit CFI instructions.
396 void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
397 bool CFI, bool Auth) const;
398
399 /// Adds an instruction which restores the link register from the top the
400 /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is
401 /// true, restore an authentication code and authenticate LR.
402 /// If \p CFI is true, emit CFI instructions.
403 void restoreLRFromStack(MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator It, bool CFI,
405 bool Auth) const;
406
407 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
408 /// so that they will be valid post-outlining.
409 ///
410 /// \param MBB A \p MachineBasicBlock in an outlined function.
411 void fixupPostOutline(MachineBasicBlock &MBB) const;
412
413 /// Returns true if the machine instruction offset can handle the stack fixup
414 /// and updates it if requested.
415 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
416 bool Updt) const;
417
418 unsigned getInstBundleLength(const MachineInstr &MI) const;
419
420 std::optional<unsigned> getVLDMDefCycle(const InstrItineraryData *ItinData,
421 const MCInstrDesc &DefMCID,
422 unsigned DefClass, unsigned DefIdx,
423 unsigned DefAlign) const;
424 std::optional<unsigned> getLDMDefCycle(const InstrItineraryData *ItinData,
425 const MCInstrDesc &DefMCID,
426 unsigned DefClass, unsigned DefIdx,
427 unsigned DefAlign) const;
428 std::optional<unsigned> getVSTMUseCycle(const InstrItineraryData *ItinData,
429 const MCInstrDesc &UseMCID,
430 unsigned UseClass, unsigned UseIdx,
431 unsigned UseAlign) const;
432 std::optional<unsigned> getSTMUseCycle(const InstrItineraryData *ItinData,
433 const MCInstrDesc &UseMCID,
434 unsigned UseClass, unsigned UseIdx,
435 unsigned UseAlign) const;
436 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
437 const MCInstrDesc &DefMCID,
438 unsigned DefIdx, unsigned DefAlign,
439 const MCInstrDesc &UseMCID,
440 unsigned UseIdx,
441 unsigned UseAlign) const;
442
443 std::optional<unsigned> getOperandLatencyImpl(
444 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
445 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
446 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
447 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
448
449 unsigned getPredicationCost(const MachineInstr &MI) const override;
450
451 unsigned getInstrLatency(const InstrItineraryData *ItinData,
452 const MachineInstr &MI,
453 unsigned *PredCost = nullptr) const override;
454
455 unsigned getInstrLatency(const InstrItineraryData *ItinData,
456 SDNode *Node) const override;
457
458 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
459 const MachineRegisterInfo *MRI,
460 const MachineInstr &DefMI, unsigned DefIdx,
461 const MachineInstr &UseMI,
462 unsigned UseIdx) const override;
463 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
464 const MachineInstr &DefMI,
465 unsigned DefIdx) const override;
466
467 /// verifyInstruction - Perform target specific instruction verification.
468 bool verifyInstruction(const MachineInstr &MI,
469 StringRef &ErrInfo) const override;
470
471 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
472
473 void expandMEMCPY(MachineBasicBlock::iterator) const;
474
475 /// Identify instructions that can be folded into a MOVCC instruction, and
476 /// return the defining instruction.
477 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
478 const TargetInstrInfo *TII) const;
479
480 bool isReMaterializableImpl(const MachineInstr &MI) const override;
481
482private:
483 /// Modeling special VFP / NEON fp MLA / MLS hazards.
484
485 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
486 /// MLx table.
487 DenseMap<unsigned, unsigned> MLxEntryMap;
488
489 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
490 /// stalls when scheduled together with fp MLA / MLS opcodes.
491 SmallSet<unsigned, 16> MLxHazardOpcodes;
492
493public:
494 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
495 /// instruction.
496 bool isFpMLxInstruction(unsigned Opcode) const {
497 return MLxEntryMap.count(Val: Opcode);
498 }
499
500 /// isFpMLxInstruction - This version also returns the multiply opcode and the
501 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
502 /// the MLX instructions with an extra lane operand.
503 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
504 unsigned &AddSubOpc, bool &NegAcc,
505 bool &HasLane) const;
506
507 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
508 /// will cause stalls when scheduled after (within 4-cycle window) a fp
509 /// MLA / MLS instruction.
510 bool canCauseFpMLxStall(unsigned Opcode) const {
511 return MLxHazardOpcodes.count(V: Opcode);
512 }
513
514 /// Returns true if the instruction has a shift by immediate that can be
515 /// executed in one cycle less.
516 bool isSwiftFastImmShift(const MachineInstr *MI) const;
517
518 /// Returns predicate register associated with the given frame instruction.
519 unsigned getFramePred(const MachineInstr &MI) const {
520 assert(isFrameInstr(MI));
521 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
522 // - argument declared in the pattern:
523 // 0 - frame size
524 // 1 - arg of CALLSEQ_START/CALLSEQ_END
525 // 2 - predicate code (like ARMCC::AL)
526 // - added by predOps:
527 // 3 - predicate reg
528 return MI.getOperand(i: 3).getReg();
529 }
530
531 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
532 Register Reg) const override;
533};
534
535/// Get the operands corresponding to the given \p Pred value. By default, the
536/// predicate register is assumed to be 0 (no register), but you can pass in a
537/// \p PredReg if that is not the case.
538static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
539 unsigned PredReg = 0) {
540 return {._M_elems: {MachineOperand::CreateImm(Val: static_cast<int64_t>(Pred)),
541 MachineOperand::CreateReg(Reg: PredReg, isDef: false)}};
542}
543
544/// Get the operand corresponding to the conditional code result. By default,
545/// this is 0 (no register).
546static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
547 return MachineOperand::CreateReg(Reg: CCReg, isDef: false);
548}
549
550/// Get the operand corresponding to the conditional code result for Thumb1.
551/// This operand will always refer to CPSR and it will have the Define flag set.
552/// You can optionally set the Dead flag by means of \p isDead.
553static inline MachineOperand t1CondCodeOp(bool isDead = false) {
554 return MachineOperand::CreateReg(Reg: ARM::CPSR,
555 /*Define*/ isDef: true, /*Implicit*/ isImp: false,
556 /*Kill*/ isKill: false, isDead);
557}
558
559static inline
560bool isUncondBranchOpcode(int Opc) {
561 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
562}
563
564// This table shows the VPT instruction variants, i.e. the different
565// mask field encodings, see also B5.6. Predication/conditional execution in
566// the ArmARM.
567static inline bool isVPTOpcode(int Opc) {
568 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
569 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
570 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
571 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
572 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
573 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
574 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
575 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
576 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
577 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
578 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
579 Opc == ARM::MVE_VPST;
580}
581
582static inline
583unsigned VCMPOpcodeToVPT(unsigned Opcode) {
584 switch (Opcode) {
585 default:
586 return 0;
587 case ARM::MVE_VCMPf32:
588 return ARM::MVE_VPTv4f32;
589 case ARM::MVE_VCMPf16:
590 return ARM::MVE_VPTv8f16;
591 case ARM::MVE_VCMPi8:
592 return ARM::MVE_VPTv16i8;
593 case ARM::MVE_VCMPi16:
594 return ARM::MVE_VPTv8i16;
595 case ARM::MVE_VCMPi32:
596 return ARM::MVE_VPTv4i32;
597 case ARM::MVE_VCMPu8:
598 return ARM::MVE_VPTv16u8;
599 case ARM::MVE_VCMPu16:
600 return ARM::MVE_VPTv8u16;
601 case ARM::MVE_VCMPu32:
602 return ARM::MVE_VPTv4u32;
603 case ARM::MVE_VCMPs8:
604 return ARM::MVE_VPTv16s8;
605 case ARM::MVE_VCMPs16:
606 return ARM::MVE_VPTv8s16;
607 case ARM::MVE_VCMPs32:
608 return ARM::MVE_VPTv4s32;
609
610 case ARM::MVE_VCMPf32r:
611 return ARM::MVE_VPTv4f32r;
612 case ARM::MVE_VCMPf16r:
613 return ARM::MVE_VPTv8f16r;
614 case ARM::MVE_VCMPi8r:
615 return ARM::MVE_VPTv16i8r;
616 case ARM::MVE_VCMPi16r:
617 return ARM::MVE_VPTv8i16r;
618 case ARM::MVE_VCMPi32r:
619 return ARM::MVE_VPTv4i32r;
620 case ARM::MVE_VCMPu8r:
621 return ARM::MVE_VPTv16u8r;
622 case ARM::MVE_VCMPu16r:
623 return ARM::MVE_VPTv8u16r;
624 case ARM::MVE_VCMPu32r:
625 return ARM::MVE_VPTv4u32r;
626 case ARM::MVE_VCMPs8r:
627 return ARM::MVE_VPTv16s8r;
628 case ARM::MVE_VCMPs16r:
629 return ARM::MVE_VPTv8s16r;
630 case ARM::MVE_VCMPs32r:
631 return ARM::MVE_VPTv4s32r;
632 }
633}
634
635static inline
636bool isCondBranchOpcode(int Opc) {
637 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
638}
639
640static inline bool isJumpTableBranchOpcode(int Opc) {
641 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
642 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
643 Opc == ARM::t2BR_JT;
644}
645
646static inline
647bool isIndirectBranchOpcode(int Opc) {
648 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
649}
650
651static inline bool isIndirectCall(const MachineInstr &MI) {
652 int Opc = MI.getOpcode();
653 switch (Opc) {
654 // indirect calls:
655 case ARM::BLX:
656 case ARM::BLX_noip:
657 case ARM::BLX_pred:
658 case ARM::BLX_pred_noip:
659 case ARM::BX_CALL:
660 case ARM::BMOVPCRX_CALL:
661 case ARM::TCRETURNri:
662 case ARM::TCRETURNrinotr12:
663 case ARM::TAILJMPr:
664 case ARM::TAILJMPr4:
665 case ARM::tBLXr:
666 case ARM::tBLXr_noip:
667 case ARM::tBLXNSr:
668 case ARM::tBLXNS_CALL:
669 case ARM::tBX_CALL:
670 case ARM::tTAILJMPr:
671 assert(MI.isCall(MachineInstr::IgnoreBundle));
672 return true;
673 // direct calls:
674 case ARM::BL:
675 case ARM::BL_pred:
676 case ARM::BMOVPCB_CALL:
677 case ARM::BL_PUSHLR:
678 case ARM::BLXi:
679 case ARM::TCRETURNdi:
680 case ARM::TAILJMPd:
681 case ARM::SVC:
682 case ARM::HVC:
683 case ARM::TPsoft:
684 case ARM::tTAILJMPd:
685 case ARM::t2SMC:
686 case ARM::t2HVC:
687 case ARM::tBL:
688 case ARM::tBLXi:
689 case ARM::tBL_PUSHLR:
690 case ARM::tTAILJMPdND:
691 case ARM::tSVC:
692 case ARM::tTPsoft:
693 assert(MI.isCall(MachineInstr::IgnoreBundle));
694 return false;
695 }
696 assert(!MI.isCall(MachineInstr::IgnoreBundle));
697 return false;
698}
699
700static inline bool isIndirectControlFlowNotComingBack(const MachineInstr &MI) {
701 int opc = MI.getOpcode();
702 return MI.isReturn() || isIndirectBranchOpcode(Opc: MI.getOpcode()) ||
703 isJumpTableBranchOpcode(Opc: opc);
704}
705
706static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
707 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
708 Opc == ARM::SpeculationBarrierSBEndBB ||
709 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
710 Opc == ARM::t2SpeculationBarrierSBEndBB;
711}
712
713static inline bool isPopOpcode(int Opc) {
714 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
715 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
716 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
717}
718
719static inline bool isPushOpcode(int Opc) {
720 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
721 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
722}
723
724static inline bool isSubImmOpcode(int Opc) {
725 return Opc == ARM::SUBri ||
726 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
727 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
728 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
729}
730
731static inline bool isMovRegOpcode(int Opc) {
732 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
733}
734/// isValidCoprocessorNumber - decide whether an explicit coprocessor
735/// number is legal in generic instructions like CDP. The answer can
736/// vary with the subtarget.
737static inline bool isValidCoprocessorNumber(unsigned Num,
738 const FeatureBitset& featureBits) {
739 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
740 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
741 // useful for code which is shared with older architectures which do not know
742 // the new VFP/NEON mnemonics.
743
744 // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
745 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
746 return false;
747
748 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
749 // which clash with MVE.
750 if (featureBits[ARM::HasV8_1MMainlineOps] &&
751 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
752 return false;
753
754 return true;
755}
756
757static inline bool isSEHInstruction(const MachineInstr &MI) {
758 unsigned Opc = MI.getOpcode();
759 switch (Opc) {
760 case ARM::SEH_StackAlloc:
761 case ARM::SEH_SaveRegs:
762 case ARM::SEH_SaveRegs_Ret:
763 case ARM::SEH_SaveSP:
764 case ARM::SEH_SaveFRegs:
765 case ARM::SEH_SaveLR:
766 case ARM::SEH_Nop:
767 case ARM::SEH_Nop_Ret:
768 case ARM::SEH_PrologEnd:
769 case ARM::SEH_EpilogStart:
770 case ARM::SEH_EpilogEnd:
771 return true;
772 default:
773 return false;
774 }
775}
776
777/// getInstrPredicate - If instruction is predicated, returns its predicate
778/// condition, otherwise returns AL. It also returns the condition code
779/// register by reference.
780ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
781
782unsigned getMatchingCondBranchOpcode(unsigned Opc);
783
784/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
785/// the instruction is encoded with an 'S' bit is determined by the optional
786/// CPSR def operand.
787unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
788
789/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
790/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
791/// code.
792void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
793 MachineBasicBlock::iterator &MBBI,
794 const DebugLoc &dl, Register DestReg,
795 Register BaseReg, int NumBytes,
796 ARMCC::CondCodes Pred, Register PredReg,
797 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
798
799void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
800 MachineBasicBlock::iterator &MBBI,
801 const DebugLoc &dl, Register DestReg,
802 Register BaseReg, int NumBytes,
803 ARMCC::CondCodes Pred, Register PredReg,
804 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
805void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
806 MachineBasicBlock::iterator &MBBI,
807 const DebugLoc &dl, Register DestReg,
808 Register BaseReg, int NumBytes,
809 const TargetInstrInfo &TII,
810 const ARMBaseRegisterInfo &MRI,
811 unsigned MIFlags = 0);
812
813/// Tries to add registers to the reglist of a given base-updating
814/// push/pop instruction to adjust the stack by an additional
815/// NumBytes. This can save a few bytes per function in code-size, but
816/// obviously generates more memory traffic. As such, it only takes
817/// effect in functions being optimised for size.
818bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
819 MachineFunction &MF, MachineInstr *MI,
820 unsigned NumBytes);
821
822/// rewriteARMFrameIndex / rewriteT2FrameIndex -
823/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
824/// offset could not be handled directly in MI, and return the left-over
825/// portion by reference.
826bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
827 Register FrameReg, int &Offset,
828 const ARMBaseInstrInfo &TII);
829
830bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
831 Register FrameReg, int &Offset,
832 const ARMBaseInstrInfo &TII,
833 const TargetRegisterInfo *TRI);
834
835/// Return true if Reg is defd between From and To
836bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From,
837 MachineBasicBlock::iterator To,
838 const TargetRegisterInfo *TRI);
839
840/// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
841/// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
842MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
843 const TargetRegisterInfo *TRI);
844
845void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
846void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
847
848void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
849void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
850 unsigned Inactive);
851
852/// Returns the number of instructions required to materialize the given
853/// constant in a register, or 3 if a literal pool load is needed.
854/// If ForCodesize is specified, an approximate cost in bytes is returned.
855unsigned ConstantMaterializationCost(unsigned Val,
856 const ARMSubtarget *Subtarget,
857 bool ForCodesize = false);
858
859/// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
860/// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
861/// specified. If the scores are equal, return the comparison for !ForCodesize.
862bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
863 const ARMSubtarget *Subtarget,
864 bool ForCodesize = false);
865
866// Return the immediate if this is ADDri or SUBri, scaled as appropriate.
867// Returns 0 for unknown instructions.
868inline int getAddSubImmediate(MachineInstr &MI) {
869 int Scale = 1;
870 unsigned ImmOp;
871 switch (MI.getOpcode()) {
872 case ARM::t2ADDri:
873 ImmOp = 2;
874 break;
875 case ARM::t2SUBri:
876 case ARM::t2SUBri12:
877 ImmOp = 2;
878 Scale = -1;
879 break;
880 case ARM::tSUBi3:
881 case ARM::tSUBi8:
882 ImmOp = 3;
883 Scale = -1;
884 break;
885 default:
886 return 0;
887 }
888 return Scale * MI.getOperand(i: ImmOp).getImm();
889}
890
891// Given a memory access Opcode, check that the give Imm would be a valid Offset
892// for this instruction using its addressing mode.
893inline bool isLegalAddressImm(unsigned Opcode, int Imm,
894 const TargetInstrInfo *TII) {
895 const MCInstrDesc &Desc = TII->get(Opcode);
896 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
897 switch (AddrMode) {
898 case ARMII::AddrModeT2_i7:
899 return std::abs(x: Imm) < ((1 << 7) * 1);
900 case ARMII::AddrModeT2_i7s2:
901 return std::abs(x: Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
902 case ARMII::AddrModeT2_i7s4:
903 return std::abs(x: Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
904 case ARMII::AddrModeT2_i8:
905 return std::abs(x: Imm) < ((1 << 8) * 1);
906 case ARMII::AddrModeT2_i8pos:
907 return Imm >= 0 && Imm < ((1 << 8) * 1);
908 case ARMII::AddrModeT2_i8neg:
909 return Imm < 0 && -Imm < ((1 << 8) * 1);
910 case ARMII::AddrModeT2_i8s4:
911 return std::abs(x: Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
912 case ARMII::AddrModeT2_i12:
913 return Imm >= 0 && Imm < ((1 << 12) * 1);
914 case ARMII::AddrMode2:
915 return std::abs(x: Imm) < ((1 << 12) * 1);
916 default:
917 llvm_unreachable("Unhandled Addressing mode");
918 }
919}
920
921// Return true if the given intrinsic is a gather
922inline bool isGather(IntrinsicInst *IntInst) {
923 if (IntInst == nullptr)
924 return false;
925 unsigned IntrinsicID = IntInst->getIntrinsicID();
926 return (IntrinsicID == Intrinsic::masked_gather ||
927 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
928 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
929 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
930 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
931 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
932 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
933}
934
935// Return true if the given intrinsic is a scatter
936inline bool isScatter(IntrinsicInst *IntInst) {
937 if (IntInst == nullptr)
938 return false;
939 unsigned IntrinsicID = IntInst->getIntrinsicID();
940 return (IntrinsicID == Intrinsic::masked_scatter ||
941 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
942 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
943 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
944 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
945 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
946 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
947}
948
949// Return true if the given intrinsic is a gather or scatter
950inline bool isGatherScatter(IntrinsicInst *IntInst) {
951 if (IntInst == nullptr)
952 return false;
953 return isGather(IntInst) || isScatter(IntInst);
954}
955
956unsigned getBLXOpcode(const MachineFunction &MF);
957unsigned gettBLXrOpcode(const MachineFunction &MF);
958unsigned getBLXpredOpcode(const MachineFunction &MF);
959
960inline bool isMVEVectorInstruction(const MachineInstr *MI) {
961 // This attempts to remove non-mve instructions (scalar shifts), which
962 // are just DPU CX instruction.
963 switch (MI->getOpcode()) {
964 case ARM::MVE_SQSHL:
965 case ARM::MVE_SRSHR:
966 case ARM::MVE_UQSHL:
967 case ARM::MVE_URSHR:
968 case ARM::MVE_SQRSHR:
969 case ARM::MVE_UQRSHL:
970 case ARM::MVE_ASRLr:
971 case ARM::MVE_ASRLi:
972 case ARM::MVE_LSLLr:
973 case ARM::MVE_LSLLi:
974 case ARM::MVE_LSRL:
975 case ARM::MVE_SQRSHRL:
976 case ARM::MVE_SQSHLL:
977 case ARM::MVE_SRSHRL:
978 case ARM::MVE_UQRSHLL:
979 case ARM::MVE_UQSHLL:
980 case ARM::MVE_URSHRL:
981 return false;
982 }
983 const MCInstrDesc &MCID = MI->getDesc();
984 uint64_t Flags = MCID.TSFlags;
985 return (Flags & ARMII::DomainMask) == ARMII::DomainMVE;
986}
987
988} // end namespace llvm
989
990#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
991