1//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the base ARM implementation of TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/MachineInstr.h"
19#include "llvm/CodeGen/TargetRegisterInfo.h"
20#include "llvm/IR/CallingConv.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include <cstdint>
23
24#define GET_REGINFO_HEADER
25#include "ARMGenRegisterInfo.inc"
26
27namespace llvm {
28
29class LiveIntervals;
30
31/// Register allocation hints.
32namespace ARMRI {
33
34 enum {
35 // Used for LDRD register pairs
36 RegPairOdd = 1,
37 RegPairEven = 2,
38 // Used to hint for lr in t2DoLoopStart
39 RegLR = 3
40 };
41
42} // end namespace ARMRI
43
44static inline bool isCalleeSavedRegister(MCRegister Reg,
45 const MCPhysReg *CSRegs) {
46 for (unsigned i = 0; CSRegs[i]; ++i)
47 if (Reg == CSRegs[i])
48 return true;
49 return false;
50}
51
52class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
53protected:
54 /// BasePtr - ARM physical register used as a base ptr in complex stack
55 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
56 /// variable size stack objects.
57 unsigned BasePtr = ARM::R6;
58
59 // Can be only subclassed.
60 explicit ARMBaseRegisterInfo();
61
62public:
63 /// Code Generation virtual methods...
64 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
65 const MCPhysReg *
66 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
67 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
68 CallingConv::ID) const override;
69 const uint32_t *getNoPreservedMask() const override;
70 const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
71 const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
72
73 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
74 /// case that 'returned' is on an i32 first argument if the calling convention
75 /// is one that can (partially) model this attribute with a preserved mask
76 /// (i.e. it is a calling convention that uses the same register for the first
77 /// i32 argument and an i32 return value)
78 ///
79 /// Should return NULL in the case that the calling convention does not have
80 /// this property
81 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
82 CallingConv::ID) const;
83
84 ArrayRef<MCPhysReg>
85 getIntraCallClobberedRegs(const MachineFunction *MF) const override;
86
87 BitVector getReservedRegs(const MachineFunction &MF) const override;
88 bool isAsmClobberable(const MachineFunction &MF,
89 MCRegister PhysReg) const override;
90 bool isInlineAsmReadOnlyReg(const MachineFunction &MF,
91 MCRegister PhysReg) const override;
92
93 const TargetRegisterClass *
94 getPointerRegClass(unsigned Kind = 0) const override;
95 const TargetRegisterClass *
96 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
97
98 const TargetRegisterClass *
99 getLargestLegalSuperClass(const TargetRegisterClass *RC,
100 const MachineFunction &MF) const override;
101
102 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
103 MachineFunction &MF) const override;
104
105 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
106 SmallVectorImpl<MCPhysReg> &Hints,
107 const MachineFunction &MF, const VirtRegMap *VRM,
108 const LiveRegMatrix *Matrix) const override;
109
110 void updateRegAllocHint(Register Reg, Register NewReg,
111 MachineFunction &MF) const override;
112
113 bool hasBasePointer(const MachineFunction &MF) const;
114
115 bool canRealignStack(const MachineFunction &MF) const override;
116 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
117 int Idx) const override;
118 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
119 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
120 int64_t Offset) const override;
121 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
122 int64_t Offset) const override;
123 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
124 int64_t Offset) const override;
125
126 bool cannotEliminateFrame(const MachineFunction &MF) const;
127
128 // Debug information queries.
129 Register getFrameRegister(const MachineFunction &MF) const override;
130 Register getBaseRegister() const { return BasePtr; }
131
132 /// emitLoadConstPool - Emits a load from constpool to materialize the
133 /// specified immediate.
134 virtual void
135 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
136 const DebugLoc &dl, Register DestReg, unsigned SubIdx,
137 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
138 Register PredReg = Register(),
139 unsigned MIFlags = MachineInstr::NoFlags) const;
140
141 /// Code Generation virtual methods...
142 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
143
144 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
145
146 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
147
148 bool eliminateFrameIndex(MachineBasicBlock::iterator II,
149 int SPAdj, unsigned FIOperandNum,
150 RegScavenger *RS = nullptr) const override;
151
152 /// SrcRC and DstRC will be morphed into NewRC if this returns true
153 bool shouldCoalesce(MachineInstr *MI,
154 const TargetRegisterClass *SrcRC,
155 unsigned SubReg,
156 const TargetRegisterClass *DstRC,
157 unsigned DstSubReg,
158 const TargetRegisterClass *NewRC,
159 LiveIntervals &LIS) const override;
160
161 int getSEHRegNum(unsigned i) const { return getEncodingValue(Reg: i); }
162};
163
164} // end namespace llvm
165
166#endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
167