1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the ARM specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMFrameLowering.h"
20#include "ARMISelLowering.h"
21#include "ARMMachineFunctionInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "llvm/Analysis/TargetTransformInfo.h"
24#include "llvm/CodeGen/GlobalISel/CallLowering.h"
25#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
26#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/RegisterBankInfo.h"
29#include "llvm/CodeGen/TargetSubtargetInfo.h"
30#include "llvm/MC/MCInstrItineraries.h"
31#include "llvm/MC/MCSchedule.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/Target/TargetOptions.h"
34#include "llvm/TargetParser/ARMTargetParser.h"
35#include "llvm/TargetParser/Triple.h"
36#include <bitset>
37#include <memory>
38#include <string>
39
40#define GET_SUBTARGETINFO_HEADER
41#include "ARMGenSubtargetInfo.inc"
42
43namespace llvm {
44
45class ARMBaseTargetMachine;
46class GlobalValue;
47class StringRef;
48
49class ARMSubtarget : public ARMGenSubtargetInfo {
50protected:
51 enum ARMProcFamilyEnum {
52 Others,
53#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
54#include "llvm/TargetParser/ARMTargetParserDef.inc"
55#undef ARM_PROCESSOR_FAMILY
56 };
57 enum ARMProcClassEnum {
58 None,
59
60 AClass,
61 MClass,
62 RClass
63 };
64 enum ARMArchEnum {
65#define ARM_ARCHITECTURE(ENUM) ENUM,
66#include "llvm/TargetParser/ARMTargetParserDef.inc"
67#undef ARM_ARCHITECTURE
68 };
69
70public:
71 /// What kind of timing do load multiple/store multiple instructions have.
72 enum ARMLdStMultipleTiming {
73 /// Can load/store 2 registers/cycle.
74 DoubleIssue,
75 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
76 /// is not 64-bit aligned.
77 DoubleIssueCheckUnalignedAccess,
78 /// Can load/store 1 register/cycle.
79 SingleIssue,
80 /// Can load/store 1 register/cycle, but needs an extra cycle for address
81 /// computation and potentially also for register writeback.
82 SingleIssuePlusExtras,
83 };
84
85 /// How the push and pop instructions of callee saved general-purpose
86 /// registers should be split.
87 enum PushPopSplitVariation {
88 /// All GPRs can be pushed in a single instruction.
89 /// push {r0-r12, lr}
90 /// vpush {d8-d15}
91 NoSplit,
92
93 /// R7 and LR must be adjacent, because R7 is the frame pointer, and must
94 /// point to a frame record consisting of the previous frame pointer and the
95 /// return address.
96 /// push {r0-r7, lr}
97 /// push {r8-r12}
98 /// vpush {d8-d15}
99 /// Note that Thumb1 changes this layout when the frame pointer is R11,
100 /// using a longer sequence of instructions because R11 can't be used by a
101 /// Thumb1 push instruction. This doesn't currently have a separate enum
102 /// value, and is handled entriely within Thumb1FrameLowering::emitPrologue.
103 SplitR7,
104
105 /// When the stack frame size is not known (because of variable-sized
106 /// objects or realignment), Windows SEH requires the callee-saved registers
107 /// to be stored in three regions, with R11 and LR below the floating-point
108 /// registers.
109 /// push {r0-r10, r12}
110 /// vpush {d8-d15}
111 /// push {r11, lr}
112 SplitR11WindowsSEH,
113
114 /// When generating AAPCS-compilant frame chains, R11 is the frame pointer,
115 /// and must be pushed adjacent to the return address (LR). Normally this
116 /// isn't a problem, because the only register between them is r12, which is
117 /// the intra-procedure-call scratch register, so doesn't need to be saved.
118 /// However, when PACBTI is in use, r12 contains the authentication code, so
119 /// does need to be saved. This means that we need a separate push for R11
120 /// and LR.
121 /// push {r0-r10, r12}
122 /// push {r11, lr}
123 /// vpush {d8-d15}
124 SplitR11AAPCSSignRA,
125 };
126
127protected:
128// Bool members corresponding to the SubtargetFeatures defined in tablegen
129#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
130 bool ATTRIBUTE = DEFAULT;
131#include "ARMGenSubtargetInfo.inc"
132
133 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
134 ARMProcFamilyEnum ARMProcFamily = Others;
135
136 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
137 ARMProcClassEnum ARMProcClass = None;
138
139 /// ARMArch - ARM architecture
140 ARMArchEnum ARMArch = ARMv4t;
141
142 /// UseMulOps - True if non-microcoded fused integer multiply-add and
143 /// multiply-subtract instructions should be used.
144 bool UseMulOps = false;
145
146 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
147 /// must be able to synthesize call stubs for interworking between ARM and
148 /// Thumb.
149 bool SupportsTailCall = false;
150
151 /// RestrictIT - If true, the subtarget disallows generation of complex IT
152 /// blocks.
153 bool RestrictIT = false;
154
155 /// stackAlignment - The minimum alignment known to hold of the stack frame on
156 /// entry to the function and which must be maintained by every function.
157 Align stackAlignment = Align(4);
158
159 /// CPUString - String name of used CPU.
160 std::string CPUString;
161
162 unsigned MaxInterleaveFactor = 1;
163
164 /// Clearance before partial register updates (in number of instructions)
165 unsigned PartialUpdateClearance = 0;
166
167 /// What kind of timing do load multiple/store multiple have (double issue,
168 /// single issue etc).
169 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
170
171 /// The adjustment that we need to apply to get the operand latency from the
172 /// operand cycle returned by the itinerary data for pre-ISel operands.
173 int PreISelOperandLatencyAdjustment = 2;
174
175 /// What alignment is preferred for loop bodies and functions, in log2(bytes).
176 unsigned PreferBranchLogAlignment = 0;
177
178 /// The cost factor for MVE instructions, representing the multiple beats an
179 // instruction can take. The default is 2, (set in initSubtargetFeatures so
180 // that we can use subtarget features less than 2).
181 unsigned MVEVectorCostFactor = 0;
182
183 /// OptMinSize - True if we're optimising for minimum code size, equal to
184 /// the function attribute.
185 bool OptMinSize = false;
186
187 /// IsLittle - The target is Little Endian
188 bool IsLittle;
189
190 /// DM - Denormal mode
191 /// NEON and VFP RunFast mode are not IEEE 754 compliant,
192 /// use this field to determine whether to generate NEON/VFP
193 /// instructions in related function.
194 DenormalMode DM;
195
196 /// TargetTriple - What processor and OS we're targeting.
197 Triple TargetTriple;
198
199 /// SchedModel - Processor specific instruction costs.
200 MCSchedModel SchedModel;
201
202 /// Selected instruction itineraries (one entry per itinerary class.)
203 InstrItineraryData InstrItins;
204
205 /// Options passed via command line that could influence the target
206 const TargetOptions &Options;
207
208 const ARMBaseTargetMachine &TM;
209
210 /// The floating-point ABI in effect for this subtarget.
211 FloatABI::ABIType FloatABIType;
212
213 /// The ABI in effect.
214 const ARM::ARMABI ABI;
215
216public:
217 /// This constructor initializes the data members to match that
218 /// of the specified triple.
219 ///
220 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
221 const ARMBaseTargetMachine &TM, bool IsLittle,
222 FloatABI::ABIType FloatABI, ARM::ARMABI ABI,
223 bool MinSize = false, DenormalMode DM = DenormalMode::getIEEE());
224
225 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
226 /// that still makes it profitable to inline the call.
227 unsigned getMaxInlineSizeThreshold() const {
228 return 64;
229 }
230
231 /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
232 /// that still makes it profitable to inline a llvm.memcpy as a Tail
233 /// Predicated loop.
234 /// This threshold should only be used for constant size inputs.
235 unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
236
237 /// ParseSubtargetFeatures - Parses features string setting specified
238 /// subtarget options. Definition of function is auto generated by tblgen.
239 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
240
241 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
242 /// so that we can use initializer lists for subtarget initialization.
243 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
244
245 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
246 return &TSInfo;
247 }
248
249 const ARMBaseInstrInfo *getInstrInfo() const override {
250 return InstrInfo.get();
251 }
252
253 const ARMTargetLowering *getTargetLowering() const override {
254 return &TLInfo;
255 }
256
257 const ARMFrameLowering *getFrameLowering() const override {
258 return FrameLowering.get();
259 }
260
261 const ARMBaseRegisterInfo *getRegisterInfo() const override {
262 return &InstrInfo->getRegisterInfo();
263 }
264
265 const CallLowering *getCallLowering() const override;
266 InstructionSelector *getInstructionSelector() const override;
267 const LegalizerInfo *getLegalizerInfo() const override;
268 const RegisterBankInfo *getRegBankInfo() const override;
269 void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;
270
271private:
272 ARMSelectionDAGInfo TSInfo;
273 // Either Thumb1FrameLowering or ARMFrameLowering.
274 std::unique_ptr<ARMFrameLowering> FrameLowering;
275 // Either Thumb1InstrInfo or Thumb2InstrInfo.
276 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
277 ARMTargetLowering TLInfo;
278
279 /// GlobalISel related APIs.
280 std::unique_ptr<CallLowering> CallLoweringInfo;
281 std::unique_ptr<InstructionSelector> InstSelector;
282 std::unique_ptr<LegalizerInfo> Legalizer;
283 std::unique_ptr<RegisterBankInfo> RegBankInfo;
284
285 void initSubtargetFeatures(StringRef CPU, StringRef FS);
286 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
287
288 std::bitset<8> CoprocCDE = {};
289public:
290// Getters for SubtargetFeatures defined in tablegen
291#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
292 bool GETTER() const { return ATTRIBUTE; }
293#include "ARMGenSubtargetInfo.inc"
294
295 /// @{
296 /// These functions are obsolete, please consider adding subtarget features
297 /// or properties instead of calling them.
298 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
299 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
300 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
301 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
302 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
303 bool isSwift() const { return ARMProcFamily == Swift; }
304 bool isCortexM3() const { return ARMProcFamily == CortexM3; }
305 bool isCortexM55() const { return ARMProcFamily == CortexM55; }
306 bool isCortexM7() const { return ARMProcFamily == CortexM7; }
307 bool isCortexM85() const { return ARMProcFamily == CortexM85; }
308 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
309 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
310 bool isKrait() const { return ARMProcFamily == Krait; }
311 /// @}
312
313 bool hasARMOps() const { return !NoARM; }
314
315 bool useNEONForSinglePrecisionFP() const {
316 return hasNEON() && hasNEONForFP();
317 }
318
319 bool hasVFP2Base() const { return hasVFPv2SP(); }
320 bool hasVFP3Base() const { return hasVFPv3D16SP(); }
321 bool hasVFP4Base() const { return hasVFPv4D16SP(); }
322 bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); }
323
324 bool hasAnyDataBarrier() const {
325 return HasDataBarrier || (hasV6Ops() && !isThumb());
326 }
327
328 bool useMulOps() const { return UseMulOps; }
329 bool useFPVMLx() const { return !SlowFPVMLx; }
330 bool useFPVFMx() const {
331 return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
332 }
333 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
334 bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
335 bool hasBaseDSP() const {
336 if (isThumb())
337 return hasThumb2() && hasDSP();
338 else
339 return hasV5TEOps();
340 }
341
342 /// Return true if the CPU supports any kind of instruction fusion.
343 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
344
345 const Triple &getTargetTriple() const { return TargetTriple; }
346
347 /// @{
348 /// These properties are per-module, please use the TargetMachine
349 /// TargetTriple.
350 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
351 bool isTargetIOS() const { return TargetTriple.isiOS(); }
352 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
353 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
354 bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }
355 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
356 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
357 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
358 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
359
360 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
361 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
362 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
363
364 bool isTargetAEABI() const { return TargetTriple.isTargetAEABI(); }
365
366 bool isTargetGNUAEABI() const { return TargetTriple.isTargetGNUAEABI(); }
367
368 bool isTargetMuslAEABI() const { return TargetTriple.isTargetMuslAEABI(); }
369
370 // ARM Targets that support EHABI exception handling standard
371 // Darwin uses SjLj. Other targets might need more checks.
372 bool isTargetEHABICompatible() const {
373 return TargetTriple.isTargetEHABICompatible();
374 }
375 /// @}
376
377 /// Returns the floating-point ABI in effect for this subtarget.
378 FloatABI::ABIType getFloatABI() const { return FloatABIType; }
379
380 /// Returns true if the subtarget uses the hard floating-point ABI.
381 bool isTargetHardFloat() const { return FloatABIType == FloatABI::Hard; }
382
383 bool isAPCS_ABI() const { return ABI == ARM::ARM_ABI_APCS; }
384 bool isAAPCS_ABI() const {
385 return ABI == ARM::ARM_ABI_AAPCS || ABI == ARM::ARM_ABI_AAPCS16;
386 }
387 bool isAAPCS16_ABI() const { return ABI == ARM::ARM_ABI_AAPCS16; }
388
389 bool isReadTPSoft() const {
390 return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW());
391 }
392
393 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
394
395 bool isXRaySupported() const override;
396
397 bool isROPI() const;
398 bool isRWPI() const;
399
400 bool useMachineScheduler() const { return UseMISched; }
401 bool useMachinePipeliner() const { return UseMIPipeliner; }
402 bool hasMinSize() const { return OptMinSize; }
403 bool isThumb1Only() const { return isThumb() && !hasThumb2(); }
404 bool isThumb2() const { return isThumb() && hasThumb2(); }
405 bool isMClass() const { return ARMProcClass == MClass; }
406 bool isRClass() const { return ARMProcClass == RClass; }
407 bool isAClass() const { return ARMProcClass == AClass; }
408
409 bool isR9Reserved() const {
410 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
411 }
412
413 MCPhysReg getFramePointerReg() const {
414 if (isTargetDarwin() ||
415 (!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))
416 return ARM::R7;
417 return ARM::R11;
418 }
419
420 enum PushPopSplitVariation
421 getPushPopSplitVariation(const MachineFunction &MF) const;
422
423 bool useStride4VFPs() const;
424
425 bool useMovt() const;
426
427 bool supportsTailCall() const { return SupportsTailCall; }
428
429 bool allowsUnalignedMem() const { return !StrictAlign; }
430
431 bool restrictIT() const { return RestrictIT; }
432
433 const std::string & getCPUString() const { return CPUString; }
434
435 bool isLittle() const { return IsLittle; }
436
437 /// Returns true if machine scheduler should be enabled.
438 bool enableMachineScheduler() const override;
439
440 /// Returns true if machine pipeliner should be enabled.
441 bool enableMachinePipeliner() const override;
442 bool useDFAforSMS() const override;
443
444 /// True for some subtargets at > -O0.
445 bool enablePostRAScheduler() const override;
446
447 /// True for some subtargets at > -O0.
448 bool enablePostRAMachineScheduler() const override;
449
450 /// Check whether this subtarget wants to use subregister liveness.
451 bool enableSubRegLiveness() const override;
452
453 /// Enable use of alias analysis during code generation (during MI
454 /// scheduling, DAGCombine, etc.).
455 bool useAA() const override { return true; }
456
457 /// getInstrItins - Return the instruction itineraries based on subtarget
458 /// selection.
459 const InstrItineraryData *getInstrItineraryData() const override {
460 return &InstrItins;
461 }
462
463 /// getStackAlignment - Returns the minimum alignment known to hold of the
464 /// stack frame on entry to the function and which must be maintained by every
465 /// function for this subtarget.
466 Align getStackAlignment() const { return stackAlignment; }
467
468 // Returns the required alignment for LDRD/STRD instructions
469 Align getDualLoadStoreAlignment() const {
470 return Align(hasV7Ops() || allowsUnalignedMem() ? 4 : 8);
471 }
472
473 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
474
475 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
476
477 ARMLdStMultipleTiming getLdStMultipleTiming() const {
478 return LdStMultipleTiming;
479 }
480
481 int getPreISelOperandLatencyAdjustment() const {
482 return PreISelOperandLatencyAdjustment;
483 }
484
485 /// True if the GV will be accessed via an indirect symbol.
486 bool isGVIndirectSymbol(const GlobalValue *GV) const;
487
488 /// Returns the constant pool modifier needed to access the GV.
489 bool isGVInGOT(const GlobalValue *GV) const;
490
491 /// True if fast-isel is used.
492 bool useFastISel() const;
493
494 /// Returns the correct return opcode for the current feature set.
495 /// Use BX if available to allow mixing thumb/arm code, but fall back
496 /// to plain mov pc,lr on ARMv4.
497 unsigned getReturnOpcode() const {
498 if (isThumb())
499 return ARM::tBX_RET;
500 if (hasV4TOps())
501 return ARM::BX_RET;
502 return ARM::MOVPCLR;
503 }
504
505 /// Allow movt+movw for PIC global address calculation.
506 /// ELF does not have GOT relocations for movt+movw.
507 /// ROPI does not use GOT.
508 bool allowPositionIndependentMovt() const {
509 return isROPI() || !isTargetELF();
510 }
511
512 unsigned getPreferBranchLogAlignment() const {
513 return PreferBranchLogAlignment;
514 }
515
516 unsigned
517 getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const {
518 if (CostKind == TargetTransformInfo::TCK_CodeSize)
519 return 1;
520 return MVEVectorCostFactor;
521 }
522
523 void getCSRAllocationOrderMask(const MachineFunction &MF,
524 BitVector &Mask) const override;
525 unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
526};
527
528} // end namespace llvm
529
530#endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
531