1//===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in the LLVM
10// ARM back-end.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_ARM_ARM_H
15#define LLVM_LIB_TARGET_ARM_ARM_H
16
17#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
18#include "llvm/IR/LegacyPassManager.h"
19#include "llvm/Support/CodeGen.h"
20#include <functional>
21
22namespace llvm {
23
24class ARMAsmPrinter;
25class ARMBaseTargetMachine;
26class ARMRegisterBankInfo;
27class ARMSubtarget;
28class Function;
29class FunctionPass;
30class InstructionSelector;
31class MCInst;
32class MachineInstr;
33class PassRegistry;
34
35Pass *createMVETailPredicationPass();
36FunctionPass *createARMLowOverheadLoopsPass();
37FunctionPass *createARMBlockPlacementPass();
38Pass *createARMParallelDSPPass();
39FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
40 CodeGenOptLevel OptLevel);
41FunctionPass *createA15SDOptimizerPass();
42FunctionPass *createARMLoadStoreOptLegacyPass(bool PreAlloc = false);
43FunctionPass *createARMExpandPseudoPass();
44FunctionPass *createARMBranchTargetsPass();
45FunctionPass *createARMConstantIslandPass();
46FunctionPass *createMLxExpansionPass();
47FunctionPass *createThumb2ITBlockPass();
48FunctionPass *createMVEVPTBlockPass();
49FunctionPass *createMVETPAndVPTOptimisationsPass();
50FunctionPass *createARMOptimizeBarriersPass();
51FunctionPass *createThumb2SizeReductionPass(
52 std::function<bool(const Function &)> Ftor = nullptr);
53InstructionSelector *
54createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
55 const ARMRegisterBankInfo &RBI);
56Pass *createMVEGatherScatterLoweringPass();
57FunctionPass *createARMSLSHardeningPass();
58FunctionPass *createARMIndirectThunks();
59Pass *createMVELaneInterleavingPass();
60FunctionPass *createARMFixCortexA57AES1742098Pass();
61
62void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
63 ARMAsmPrinter &AP);
64
65void initializeARMAsmPrinterPass(PassRegistry &);
66void initializeARMBlockPlacementPass(PassRegistry &);
67void initializeARMBranchTargetsPass(PassRegistry &);
68void initializeARMConstantIslandsPass(PassRegistry &);
69void initializeARMDAGToDAGISelLegacyPass(PassRegistry &);
70void initializeARMExpandPseudoPass(PassRegistry &);
71void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
72void initializeARMLoadStoreOptLegacyPass(PassRegistry &);
73void initializeARMLowOverheadLoopsPass(PassRegistry &);
74void initializeARMParallelDSPPass(PassRegistry &);
75void initializeARMPreAllocLoadStoreOptLegacyPass(PassRegistry &);
76void initializeARMSLSHardeningPass(PassRegistry &);
77void initializeMVEGatherScatterLoweringPass(PassRegistry &);
78void initializeMVELaneInterleavingPass(PassRegistry &);
79void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
80void initializeMVETailPredicationPass(PassRegistry &);
81void initializeMVEVPTBlockPass(PassRegistry &);
82void initializeThumb2ITBlockPass(PassRegistry &);
83void initializeThumb2SizeReducePass(PassRegistry &);
84
85class ARMPreAllocLoadStoreOptPass
86 : public PassInfoMixin<ARMPreAllocLoadStoreOptPass> {
87public:
88 PreservedAnalyses run(MachineFunction &MF,
89 MachineFunctionAnalysisManager &MFAM);
90};
91
92class ARMLoadStoreOptPass : public PassInfoMixin<ARMLoadStoreOptPass> {
93public:
94 PreservedAnalyses run(MachineFunction &MF,
95 MachineFunctionAnalysisManager &MFAM);
96};
97
98} // end namespace llvm
99
100#endif // LLVM_LIB_TARGET_ARM_ARM_H
101