1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::ARM {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 FPRRegBankID = 0,
17 GPRRegBankID = 1,
18 NumRegisterBanks,
19};
20
21} // namespace llvm::ARM
22
23#endif // GET_REGBANK_DECLARATIONS
24
25#ifdef GET_TARGET_REGBANK_CLASS
26#undef GET_TARGET_REGBANK_CLASS
27
28private:
29 static const RegisterBank *RegBanks[];
30 static const unsigned Sizes[];
31
32public:
33 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
34protected:
35 ARMGenRegisterBankInfo(unsigned HwMode = 0);
36
37
38#endif // GET_TARGET_REGBANK_CLASS
39
40#ifdef GET_TARGET_REGBANK_IMPL
41#undef GET_TARGET_REGBANK_IMPL
42
43namespace llvm {
44
45namespace ARM {
46
47const uint32_t FPRRegBankCoverageData[] = {
48 // 0-31
49 (1u << (ARM::HPRRegClassID - 0)) |
50 (1u << (ARM::SPRRegClassID - 0)) |
51 (1u << (ARM::SPR_8RegClassID - 0)) |
52 (1u << (ARM::FPWithVPRRegClassID - 0)) |
53 (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
54 (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
55 0,
56 // 32-63
57 (1u << (ARM::DPRRegClassID - 32)) |
58 (1u << (ARM::DPR_VFP2RegClassID - 32)) |
59 (1u << (ARM::DPR_8RegClassID - 32)) |
60 0,
61 // 64-95
62 (1u << (ARM::QPRRegClassID - 64)) |
63 (1u << (ARM::MQPRRegClassID - 64)) |
64 (1u << (ARM::QPR_VFP2RegClassID - 64)) |
65 (1u << (ARM::QPR_8RegClassID - 64)) |
66 0,
67 // 96-127
68 0,
69 // 128-159
70 0,
71};
72const uint32_t GPRRegBankCoverageData[] = {
73 // 0-31
74 (1u << (ARM::GPRRegClassID - 0)) |
75 (1u << (ARM::GPRnopcRegClassID - 0)) |
76 (1u << (ARM::rGPRRegClassID - 0)) |
77 (1u << (ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID - 0)) |
78 (1u << (ARM::tGPRRegClassID - 0)) |
79 (1u << (ARM::GPRnoip_and_tGPREvenRegClassID - 0)) |
80 (1u << (ARM::tGPROddRegClassID - 0)) |
81 (1u << (ARM::tGPREvenRegClassID - 0)) |
82 (1u << (ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID - 0)) |
83 (1u << (ARM::tcGPRRegClassID - 0)) |
84 (1u << (ARM::GPRnoip_and_GPRnopcRegClassID - 0)) |
85 (1u << (ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID - 0)) |
86 (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
87 (1u << (ARM::GPRnospRegClassID - 0)) |
88 (1u << (ARM::GPRnoip_and_GPRnospRegClassID - 0)) |
89 (1u << (ARM::tGPRwithpcRegClassID - 0)) |
90 (1u << (ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID - 0)) |
91 (1u << (ARM::GPRnosp_and_hGPRRegClassID - 0)) |
92 (1u << (ARM::GPRnoipRegClassID - 0)) |
93 (1u << (ARM::GPRnoip_and_hGPRRegClassID - 0)) |
94 (1u << (ARM::hGPRRegClassID - 0)) |
95 (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
96 (1u << (ARM::GPRwithAPSR_NZCVnospRegClassID - 0)) |
97 0,
98 // 32-63
99 (1u << (ARM::tGPR_and_tGPREvenRegClassID - 32)) |
100 (1u << (ARM::tGPREven_and_tcGPRnotr12RegClassID - 32)) |
101 (1u << (ARM::tGPR_and_tGPROddRegClassID - 32)) |
102 (1u << (ARM::tGPROdd_and_tcGPRRegClassID - 32)) |
103 (1u << (ARM::tcGPRnotr12RegClassID - 32)) |
104 (1u << (ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID - 32)) |
105 (1u << (ARM::hGPR_and_tGPROddRegClassID - 32)) |
106 (1u << (ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID - 32)) |
107 (1u << (ARM::hGPR_and_tGPREvenRegClassID - 32)) |
108 (1u << (ARM::GPRlrRegClassID - 32)) |
109 (1u << (ARM::hGPR_and_tcGPRRegClassID - 32)) |
110 (1u << (ARM::tGPREven_and_tcGPRRegClassID - 32)) |
111 (1u << (ARM::GPRspRegClassID - 32)) |
112 (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 32)) |
113 0,
114 // 64-95
115 0,
116 // 96-127
117 0,
118 // 128-159
119 0,
120};
121
122constexpr RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 137);
123constexpr RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 137);
124
125} // namespace ARM
126
127const RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
128 &ARM::FPRRegBank,
129 &ARM::GPRRegBank,
130};
131
132const unsigned ARMGenRegisterBankInfo::Sizes[] = {
133 // Mode = 0 (Default)
134 128,
135 32,
136 // Mode = 1 (Thumb1OnlyMode)
137 128,
138 32,
139};
140
141ARMGenRegisterBankInfo::ARMGenRegisterBankInfo(unsigned HwMode)
142 : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks, Sizes, HwMode) {
143 // Assert that RegBank indices match their ID's
144#ifndef NDEBUG
145 for (auto RB : enumerate(RegBanks))
146 assert(RB.index() == RB.value()->getID() && "Index != ID");
147#endif // NDEBUG
148}
149
150const RegisterBank &
151ARMGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
152 constexpr uint32_t InvalidRegBankID = uint32_t(ARM::InvalidRegBankID) & 3;
153 static const uint32_t RegClass2RegBank[5] = {
154 (uint32_t(ARM::FPRRegBankID) << 0) | // HPRRegClassID
155 (uint32_t(ARM::FPRRegBankID) << 2) | // FPWithVPRRegClassID
156 (uint32_t(ARM::FPRRegBankID) << 4) | // SPRRegClassID
157 (uint32_t(ARM::FPRRegBankID) << 6) | // FPWithVPR_with_ssub_0RegClassID
158 (uint32_t(ARM::GPRRegBankID) << 8) | // GPRRegClassID
159 (uint32_t(ARM::GPRRegBankID) << 10) | // GPRwithAPSRRegClassID
160 (uint32_t(InvalidRegBankID) << 12) |
161 (uint32_t(ARM::FPRRegBankID) << 14) | // SPR_8RegClassID
162 (uint32_t(ARM::GPRRegBankID) << 16) | // GPRnopcRegClassID
163 (uint32_t(ARM::GPRRegBankID) << 18) | // GPRnospRegClassID
164 (uint32_t(ARM::GPRRegBankID) << 20) | // GPRwithAPSR_NZCVnospRegClassID
165 (uint32_t(InvalidRegBankID) << 22) |
166 (uint32_t(InvalidRegBankID) << 24) |
167 (uint32_t(ARM::GPRRegBankID) << 26) | // GPRnoipRegClassID
168 (uint32_t(ARM::GPRRegBankID) << 28) | // rGPRRegClassID
169 (uint32_t(ARM::GPRRegBankID) << 30), // GPRnoip_and_GPRnopcRegClassID
170 (uint32_t(ARM::GPRRegBankID) << 0) | // GPRnoip_and_GPRnospRegClassID
171 (uint32_t(ARM::GPRRegBankID) << 2) | // GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID
172 (uint32_t(ARM::GPRRegBankID) << 4) | // tGPRwithpcRegClassID
173 (uint32_t(ARM::FPRRegBankID) << 6) | // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID
174 (uint32_t(ARM::GPRRegBankID) << 8) | // hGPRRegClassID
175 (uint32_t(ARM::GPRRegBankID) << 10) | // tGPRRegClassID
176 (uint32_t(ARM::GPRRegBankID) << 12) | // tGPREvenRegClassID
177 (uint32_t(ARM::GPRRegBankID) << 14) | // GPRnopc_and_hGPRRegClassID
178 (uint32_t(ARM::GPRRegBankID) << 16) | // GPRnosp_and_hGPRRegClassID
179 (uint32_t(ARM::GPRRegBankID) << 18) | // GPRnoip_and_hGPRRegClassID
180 (uint32_t(ARM::GPRRegBankID) << 20) | // GPRnoip_and_tGPREvenRegClassID
181 (uint32_t(ARM::GPRRegBankID) << 22) | // GPRnosp_and_GPRnopc_and_hGPRRegClassID
182 (uint32_t(ARM::GPRRegBankID) << 24) | // tGPROddRegClassID
183 (uint32_t(ARM::GPRRegBankID) << 26) | // GPRnopc_and_GPRnoip_and_hGPRRegClassID
184 (uint32_t(ARM::GPRRegBankID) << 28) | // GPRnosp_and_GPRnoip_and_hGPRRegClassID
185 (uint32_t(ARM::GPRRegBankID) << 30), // tcGPRRegClassID
186 (uint32_t(ARM::GPRRegBankID) << 0) | // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID
187 (uint32_t(ARM::GPRRegBankID) << 2) | // hGPR_and_tGPREvenRegClassID
188 (uint32_t(ARM::GPRRegBankID) << 4) | // tGPR_and_tGPREvenRegClassID
189 (uint32_t(ARM::GPRRegBankID) << 6) | // tGPR_and_tGPROddRegClassID
190 (uint32_t(ARM::GPRRegBankID) << 8) | // tcGPRnotr12RegClassID
191 (uint32_t(ARM::GPRRegBankID) << 10) | // tGPREven_and_tcGPRRegClassID
192 (uint32_t(InvalidRegBankID) << 12) |
193 (uint32_t(ARM::GPRRegBankID) << 14) | // hGPR_and_GPRnoip_and_tGPREvenRegClassID
194 (uint32_t(ARM::GPRRegBankID) << 16) | // hGPR_and_tGPROddRegClassID
195 (uint32_t(ARM::GPRRegBankID) << 18) | // tGPREven_and_tcGPRnotr12RegClassID
196 (uint32_t(ARM::GPRRegBankID) << 20) | // tGPROdd_and_tcGPRRegClassID
197 (uint32_t(InvalidRegBankID) << 22) |
198 (uint32_t(InvalidRegBankID) << 24) |
199 (uint32_t(ARM::GPRRegBankID) << 26) | // GPRlrRegClassID
200 (uint32_t(ARM::GPRRegBankID) << 28) | // GPRspRegClassID
201 (uint32_t(InvalidRegBankID) << 30),
202 (uint32_t(InvalidRegBankID) << 0) |
203 (uint32_t(ARM::GPRRegBankID) << 2) | // hGPR_and_tGPRwithpcRegClassID
204 (uint32_t(ARM::GPRRegBankID) << 4) | // hGPR_and_tcGPRRegClassID
205 (uint32_t(ARM::FPRRegBankID) << 6) | // DPRRegClassID
206 (uint32_t(ARM::FPRRegBankID) << 8) | // DPR_VFP2RegClassID
207 (uint32_t(ARM::FPRRegBankID) << 10) | // DPR_8RegClassID
208 (uint32_t(InvalidRegBankID) << 12) |
209 (uint32_t(InvalidRegBankID) << 14) |
210 (uint32_t(InvalidRegBankID) << 16) |
211 (uint32_t(InvalidRegBankID) << 18) |
212 (uint32_t(InvalidRegBankID) << 20) |
213 (uint32_t(InvalidRegBankID) << 22) |
214 (uint32_t(InvalidRegBankID) << 24) |
215 (uint32_t(InvalidRegBankID) << 26) |
216 (uint32_t(InvalidRegBankID) << 28) |
217 (uint32_t(InvalidRegBankID) << 30),
218 (uint32_t(InvalidRegBankID) << 0) |
219 (uint32_t(InvalidRegBankID) << 2) |
220 (uint32_t(InvalidRegBankID) << 4) |
221 (uint32_t(InvalidRegBankID) << 6) |
222 (uint32_t(InvalidRegBankID) << 8) |
223 (uint32_t(ARM::FPRRegBankID) << 10) | // QPRRegClassID
224 (uint32_t(InvalidRegBankID) << 12) |
225 (uint32_t(InvalidRegBankID) << 14) |
226 (uint32_t(ARM::FPRRegBankID) << 16) | // MQPRRegClassID
227 (uint32_t(ARM::FPRRegBankID) << 18) | // QPR_VFP2RegClassID
228 (uint32_t(InvalidRegBankID) << 20) |
229 (uint32_t(ARM::FPRRegBankID) << 22) // QPR_8RegClassID
230 };
231 const unsigned RegClassID = RC.getID();
232 if (LLVM_LIKELY(RegClassID < 76)) {
233 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
234 if (RegBankID != InvalidRegBankID)
235 return getRegBank(RegBankID);
236 }
237 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
238}
239
240} // namespace llvm
241
242#endif // GET_TARGET_REGBANK_IMPL
243
244