1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the ARM specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
14#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15
16#include "ARMSubtarget.h"
17#include "llvm/ADT/StringMap.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/TargetTransformInfo.h"
20#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
21#include "llvm/Support/CodeGen.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/TargetParser/ARMTargetParser.h"
24#include <memory>
25#include <optional>
26
27namespace llvm {
28
29class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
30protected:
31 std::unique_ptr<TargetLoweringObjectFile> TLOF;
32 bool isLittle;
33 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
34
35 /// Reset internal state.
36 void reset() override;
37
38public:
39 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
40 StringRef FS, const TargetOptions &Options,
41 std::optional<Reloc::Model> RM,
42 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
43 ~ARMBaseTargetMachine() override;
44
45 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
46 // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
47 // subtargets are per-function entities based on the target-specific
48 // attributes of each function.
49 const ARMSubtarget *getSubtargetImpl() const = delete;
50 bool isLittleEndian() const { return isLittle; }
51
52 /// Returns the floating-point ABI in effect for \p M: the "float-abi" module
53 /// flag if present, otherwise the ABI implied by the target triple. An
54 /// explicit -target-abi=aapcs16 forces the hard-float ABI.
55 FloatABI::ABIType getFloatABI(const Module &M) const;
56
57 /// Returns the ABI in effect for \p M: the "target-abi" module flag if
58 /// present, otherwise the legacy -target-abi option; falling back to the
59 /// TargetMachine-level ABI computed at construction.
60 ARM::ARMABI getEffectiveABI(const Module &M) const;
61
62 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
63
64 // Pass Pipeline Configuration
65 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
66
67 void registerPassBuilderCallbacks(PassBuilder &PB) override;
68
69 TargetLoweringObjectFile *getObjFileLowering() const override {
70 return TLOF.get();
71 }
72
73 bool targetSchedulesPostRAScheduling() const override { return true; };
74
75 MachineFunctionInfo *
76 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
77 const TargetSubtargetInfo *STI) const override;
78
79 /// Returns true if a cast between SrcAS and DestAS is a noop.
80 bool isNoopAddrSpaceCast(const DataLayout &, unsigned SrcAS,
81 unsigned DestAS) const override {
82 // Addrspacecasts are always noops.
83 return true;
84 }
85
86 bool isGVIndirectSymbol(const GlobalValue *GV) const {
87 if (!shouldAssumeDSOLocal(GV))
88 return true;
89
90 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
91 // the section that is being relocated. This means we have to use o load
92 // even for GVs that are known to be local to the dso.
93 if (getTargetTriple().isOSBinFormatMachO() && isPositionIndependent() &&
94 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
95 return true;
96
97 return false;
98 }
99
100 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
101 yaml::MachineFunctionInfo *
102 convertFuncInfoToYAML(const MachineFunction &MF) const override;
103 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
104 PerFunctionMIParsingState &PFS,
105 SMDiagnostic &Error,
106 SMRange &SourceRange) const override;
107 ScheduleDAGInstrs *
108 createMachineScheduler(MachineSchedContext *C) const override;
109 ScheduleDAGInstrs *
110 createPostMachineScheduler(MachineSchedContext *C) const override;
111};
112
113/// ARM/Thumb little endian target machine.
114///
115class ARMLETargetMachine : public ARMBaseTargetMachine {
116public:
117 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
118 StringRef FS, const TargetOptions &Options,
119 std::optional<Reloc::Model> RM,
120 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
121 bool JIT);
122};
123
124/// ARM/Thumb big endian target machine.
125///
126class ARMBETargetMachine : public ARMBaseTargetMachine {
127public:
128 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
129 StringRef FS, const TargetOptions &Options,
130 std::optional<Reloc::Model> RM,
131 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
132 bool JIT);
133};
134
135} // end namespace llvm
136
137#endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
138