1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format ARM assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMAsmPrinter.h"
15#include "ARM.h"
16#include "ARMConstantPoolValue.h"
17#include "ARMMachineFunctionInfo.h"
18#include "ARMTargetMachine.h"
19#include "ARMTargetObjectFile.h"
20#include "MCTargetDesc/ARMInstPrinter.h"
21#include "MCTargetDesc/ARMMCAsmInfo.h"
22#include "TargetInfo/ARMTargetInfo.h"
23#include "llvm/ADT/SmallString.h"
24#include "llvm/BinaryFormat/COFF.h"
25#include "llvm/CodeGen/MachineJumpTableInfo.h"
26#include "llvm/CodeGen/MachineModuleInfoImpls.h"
27#include "llvm/IR/Constants.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/IR/Mangler.h"
30#include "llvm/IR/Module.h"
31#include "llvm/IR/Type.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/MC/MCAssembler.h"
34#include "llvm/MC/MCContext.h"
35#include "llvm/MC/MCELFStreamer.h"
36#include "llvm/MC/MCInst.h"
37#include "llvm/MC/MCInstBuilder.h"
38#include "llvm/MC/MCObjectStreamer.h"
39#include "llvm/MC/MCStreamer.h"
40#include "llvm/MC/MCSymbol.h"
41#include "llvm/MC/TargetRegistry.h"
42#include "llvm/Support/ARMBuildAttributes.h"
43#include "llvm/Support/Compiler.h"
44#include "llvm/Support/Debug.h"
45#include "llvm/Support/ErrorHandling.h"
46#include "llvm/Support/raw_ostream.h"
47#include "llvm/Target/TargetMachine.h"
48using namespace llvm;
49
50#define DEBUG_TYPE "asm-printer"
51
52ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
53 std::unique_ptr<MCStreamer> Streamer)
54 : AsmPrinter(TM, std::move(Streamer), ID), AFI(nullptr), MCP(nullptr),
55 InConstantPool(false), OptimizationGoals(-1) {}
56
57const ARMBaseTargetMachine &ARMAsmPrinter::getTM() const {
58 return static_cast<const ARMBaseTargetMachine &>(TM);
59}
60
61void ARMAsmPrinter::emitFunctionBodyEnd() {
62 // Make sure to terminate any constant pools that were at the end
63 // of the function.
64 if (!InConstantPool)
65 return;
66 InConstantPool = false;
67 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
68}
69
70void ARMAsmPrinter::emitFunctionEntryLabel() {
71 auto &TS =
72 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
73 if (AFI->isThumbFunction()) {
74 TS.emitCode16();
75 TS.emitThumbFunc(Symbol: CurrentFnSym);
76 } else {
77 TS.emitCode32();
78 }
79
80 // Emit symbol for CMSE non-secure entry point
81 if (AFI->isCmseNSEntryFunction()) {
82 MCSymbol *S =
83 OutContext.getOrCreateSymbol(Name: "__acle_se_" + CurrentFnSym->getName());
84 emitLinkage(GV: &MF->getFunction(), GVSym: S);
85 OutStreamer->emitSymbolAttribute(Symbol: S, Attribute: MCSA_ELF_TypeFunction);
86 OutStreamer->emitLabel(Symbol: S);
87 }
88 AsmPrinter::emitFunctionEntryLabel();
89}
90
91void ARMAsmPrinter::emitXXStructor(const DataLayout &DL, const Constant *CV) {
92 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: CV->getType());
93 assert(Size && "C++ constructor pointer had zero size!");
94
95 const GlobalValue *GV = dyn_cast<GlobalValue>(Val: CV->stripPointerCasts());
96 assert(GV && "C++ constructor pointer was not a GlobalValue!");
97
98 const MCExpr *E = MCSymbolRefExpr::create(
99 Symbol: GetARMGVSymbol(GV, TargetFlags: ARMII::MO_NO_FLAG),
100 specifier: (TM.getTargetTriple().isOSBinFormatELF() ? ARM::S_TARGET1 : ARM::S_None),
101 Ctx&: OutContext);
102
103 OutStreamer->emitValue(Value: E, Size);
104}
105
106// An alias to a cmse entry function should also emit a `__acle_se_` symbol.
107void ARMAsmPrinter::emitCMSEVeneerAlias(const GlobalAlias &GA) {
108 const Function *BaseFn = dyn_cast_or_null<Function>(Val: GA.getAliaseeObject());
109 if (!BaseFn || !BaseFn->hasFnAttribute(Kind: "cmse_nonsecure_entry"))
110 return;
111
112 MCSymbol *AliasSym = getSymbol(GV: &GA);
113 MCSymbol *FnSym = getSymbol(GV: BaseFn);
114
115 MCSymbol *SEAliasSym =
116 OutContext.getOrCreateSymbol(Name: Twine("__acle_se_") + AliasSym->getName());
117 MCSymbol *SEBaseSym =
118 OutContext.getOrCreateSymbol(Name: Twine("__acle_se_") + FnSym->getName());
119
120 // Mirror alias linkage/visibility onto the veneer-alias symbol.
121 emitLinkage(GV: &GA, GVSym: SEAliasSym);
122 OutStreamer->emitSymbolAttribute(Symbol: SEAliasSym, Attribute: MCSA_ELF_TypeFunction);
123 emitVisibility(Sym: SEAliasSym, Visibility: GA.getVisibility());
124
125 // emit "__acle_se_<alias> = __acle_se_<aliasee>"
126 const MCExpr *SEExpr = MCSymbolRefExpr::create(Symbol: SEBaseSym, Ctx&: OutContext);
127 OutStreamer->emitAssignment(Symbol: SEAliasSym, Value: SEExpr);
128}
129
130void ARMAsmPrinter::emitGlobalAlias(const Module &M, const GlobalAlias &GA) {
131 AsmPrinter::emitGlobalAlias(M, GA);
132 emitCMSEVeneerAlias(GA);
133}
134
135void ARMAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
136 if (PromotedGlobals.count(Ptr: GV))
137 // The global was promoted into a constant pool. It should not be emitted.
138 return;
139 AsmPrinter::emitGlobalVariable(GV);
140}
141
142/// runOnMachineFunction - This uses the emitInstruction()
143/// method to print assembly for each instruction.
144///
145bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
146 AFI = MF.getInfo<ARMFunctionInfo>();
147 MCP = MF.getConstantPool();
148
149 SetupMachineFunction(MF);
150 const Function &F = MF.getFunction();
151 const TargetMachine& TM = MF.getTarget();
152
153 // Collect all globals that had their storage promoted to a constant pool.
154 // Functions are emitted before variables, so this accumulates promoted
155 // globals from all functions in PromotedGlobals.
156 PromotedGlobals.insert_range(R&: AFI->getGlobalsPromotedToConstantPool());
157
158 // Calculate this function's optimization goal.
159 unsigned OptimizationGoal;
160 if (F.hasOptNone())
161 // For best debugging illusion, speed and small size sacrificed
162 OptimizationGoal = 6;
163 else if (F.hasMinSize())
164 // Aggressively for small size, speed and debug illusion sacrificed
165 OptimizationGoal = 4;
166 else if (F.hasOptSize())
167 // For small size, but speed and debugging illusion preserved
168 OptimizationGoal = 3;
169 else if (TM.getOptLevel() == CodeGenOptLevel::Aggressive)
170 // Aggressively for speed, small size and debug illusion sacrificed
171 OptimizationGoal = 2;
172 else if (TM.getOptLevel() > CodeGenOptLevel::None)
173 // For speed, but small size and good debug illusion preserved
174 OptimizationGoal = 1;
175 else // TM.getOptLevel() == CodeGenOptLevel::None
176 // For good debugging, but speed and small size preserved
177 OptimizationGoal = 5;
178
179 // Combine a new optimization goal with existing ones.
180 if (OptimizationGoals == -1) // uninitialized goals
181 OptimizationGoals = OptimizationGoal;
182 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
183 OptimizationGoals = 0;
184
185 if (TM.getTargetTriple().isOSBinFormatCOFF()) {
186 bool Local = F.hasLocalLinkage();
187 COFF::SymbolStorageClass Scl =
188 Local ? COFF::IMAGE_SYM_CLASS_STATIC : COFF::IMAGE_SYM_CLASS_EXTERNAL;
189 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
190
191 OutStreamer->beginCOFFSymbolDef(Symbol: CurrentFnSym);
192 OutStreamer->emitCOFFSymbolStorageClass(StorageClass: Scl);
193 OutStreamer->emitCOFFSymbolType(Type);
194 OutStreamer->endCOFFSymbolDef();
195 }
196
197 // Emit the rest of the function body.
198 emitFunctionBody();
199
200 // Emit the XRay table for this function.
201 emitXRayTable();
202
203 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
204 // These are created per function, rather than per TU, since it's
205 // relatively easy to exceed the thumb branch range within a TU.
206 if (! ThumbIndirectPads.empty()) {
207 auto &TS =
208 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
209 TS.emitCode16();
210 emitAlignment(Alignment: Align(2));
211 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
212 OutStreamer->emitLabel(Symbol: TIP.second);
213 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBX)
214 .addReg(Reg: TIP.first)
215 // Add predicate operands.
216 .addImm(Val: ARMCC::AL)
217 .addReg(Reg: 0));
218 }
219 ThumbIndirectPads.clear();
220 }
221
222 // We didn't modify anything.
223 return false;
224}
225
226void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
227 raw_ostream &O) {
228 assert(MO.isGlobal() && "caller should check MO.isGlobal");
229 unsigned TF = MO.getTargetFlags();
230 if (TF & ARMII::MO_LO16)
231 O << ":lower16:";
232 else if (TF & ARMII::MO_HI16)
233 O << ":upper16:";
234 else if (TF & ARMII::MO_LO_0_7)
235 O << ":lower0_7:";
236 else if (TF & ARMII::MO_LO_8_15)
237 O << ":lower8_15:";
238 else if (TF & ARMII::MO_HI_0_7)
239 O << ":upper0_7:";
240 else if (TF & ARMII::MO_HI_8_15)
241 O << ":upper8_15:";
242
243 GetARMGVSymbol(GV: MO.getGlobal(), TargetFlags: TF)->print(OS&: O, MAI);
244 printOffset(Offset: MO.getOffset(), OS&: O);
245}
246
247void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
248 raw_ostream &O) {
249 const MachineOperand &MO = MI->getOperand(i: OpNum);
250
251 switch (MO.getType()) {
252 default: llvm_unreachable("<unknown operand type>");
253 case MachineOperand::MO_Register: {
254 Register Reg = MO.getReg();
255 assert(Reg.isPhysical());
256 assert(!MO.getSubReg() && "Subregs should be eliminated!");
257 if(ARM::GPRPairRegClass.contains(Reg)) {
258 const MachineFunction &MF = *MI->getParent()->getParent();
259 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
260 Reg = TRI->getSubReg(Reg, Idx: ARM::gsub_0);
261 }
262 O << ARMInstPrinter::getRegisterName(Reg);
263 break;
264 }
265 case MachineOperand::MO_Immediate: {
266 O << '#';
267 unsigned TF = MO.getTargetFlags();
268 if (TF == ARMII::MO_LO16)
269 O << ":lower16:";
270 else if (TF == ARMII::MO_HI16)
271 O << ":upper16:";
272 else if (TF == ARMII::MO_LO_0_7)
273 O << ":lower0_7:";
274 else if (TF == ARMII::MO_LO_8_15)
275 O << ":lower8_15:";
276 else if (TF == ARMII::MO_HI_0_7)
277 O << ":upper0_7:";
278 else if (TF == ARMII::MO_HI_8_15)
279 O << ":upper8_15:";
280 O << MO.getImm();
281 break;
282 }
283 case MachineOperand::MO_MachineBasicBlock:
284 MO.getMBB()->getSymbol()->print(OS&: O, MAI);
285 return;
286 case MachineOperand::MO_GlobalAddress: {
287 PrintSymbolOperand(MO, O);
288 break;
289 }
290 case MachineOperand::MO_ConstantPoolIndex:
291 assert(!MF->getSubtarget<ARMSubtarget>().genExecuteOnly() &&
292 "execute-only should not generate constant pools");
293 GetCPISymbol(CPID: MO.getIndex())->print(OS&: O, MAI);
294 break;
295 }
296}
297
298MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
299 // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
300 // indexes in MachineConstantPool, which isn't in sync with indexes used here.
301 const DataLayout &DL = getDataLayout();
302 return OutContext.getOrCreateSymbol(Name: Twine(DL.getPrivateGlobalPrefix()) +
303 "CPI" + Twine(getFunctionNumber()) + "_" +
304 Twine(CPID));
305}
306
307//===--------------------------------------------------------------------===//
308
309MCSymbol *ARMAsmPrinter::
310GetARMJTIPICJumpTableLabel(unsigned uid) const {
311 const DataLayout &DL = getDataLayout();
312 SmallString<60> Name;
313 raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
314 << getFunctionNumber() << '_' << uid;
315 return OutContext.getOrCreateSymbol(Name);
316}
317
318bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
319 const char *ExtraCode, raw_ostream &O) {
320 // Does this asm operand have a single letter operand modifier?
321 if (ExtraCode && ExtraCode[0]) {
322 if (ExtraCode[1] != 0) return true; // Unknown modifier.
323
324 switch (ExtraCode[0]) {
325 default:
326 // See if this is a generic print operand
327 return AsmPrinter::PrintAsmOperand(MI, OpNo: OpNum, ExtraCode, OS&: O);
328 case 'P': // Print a VFP double precision register.
329 case 'q': // Print a NEON quad precision register.
330 printOperand(MI, OpNum, O);
331 return false;
332 case 'y': // Print a VFP single precision register as indexed double.
333 if (MI->getOperand(i: OpNum).isReg()) {
334 MCRegister Reg = MI->getOperand(i: OpNum).getReg().asMCReg();
335 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
336 // Find the 'd' register that has this 's' register as a sub-register,
337 // and determine the lane number.
338 for (MCPhysReg SR : TRI->superregs(Reg)) {
339 if (!ARM::DPRRegClass.contains(Reg: SR))
340 continue;
341 bool Lane0 = TRI->getSubReg(Reg: SR, Idx: ARM::ssub_0) == Reg;
342 O << ARMInstPrinter::getRegisterName(Reg: SR) << (Lane0 ? "[0]" : "[1]");
343 return false;
344 }
345 }
346 return true;
347 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
348 if (!MI->getOperand(i: OpNum).isImm())
349 return true;
350 O << ~(MI->getOperand(i: OpNum).getImm());
351 return false;
352 case 'L': // The low 16 bits of an immediate constant.
353 if (!MI->getOperand(i: OpNum).isImm())
354 return true;
355 O << (MI->getOperand(i: OpNum).getImm() & 0xffff);
356 return false;
357 case 'M': { // A register range suitable for LDM/STM.
358 if (!MI->getOperand(i: OpNum).isReg())
359 return true;
360 const MachineOperand &MO = MI->getOperand(i: OpNum);
361 Register RegBegin = MO.getReg();
362 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
363 // already got the operands in registers that are operands to the
364 // inline asm statement.
365 O << "{";
366 if (ARM::GPRPairRegClass.contains(Reg: RegBegin)) {
367 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
368 Register Reg0 = TRI->getSubReg(Reg: RegBegin, Idx: ARM::gsub_0);
369 O << ARMInstPrinter::getRegisterName(Reg: Reg0) << ", ";
370 RegBegin = TRI->getSubReg(Reg: RegBegin, Idx: ARM::gsub_1);
371 }
372 O << ARMInstPrinter::getRegisterName(Reg: RegBegin);
373
374 // FIXME: The register allocator not only may not have given us the
375 // registers in sequence, but may not be in ascending registers. This
376 // will require changes in the register allocator that'll need to be
377 // propagated down here if the operands change.
378 unsigned RegOps = OpNum + 1;
379 while (MI->getOperand(i: RegOps).isReg()) {
380 O << ", "
381 << ARMInstPrinter::getRegisterName(Reg: MI->getOperand(i: RegOps).getReg());
382 RegOps++;
383 }
384
385 O << "}";
386
387 return false;
388 }
389 case 'R': // The most significant register of a pair.
390 case 'Q': { // The least significant register of a pair.
391 if (OpNum == 0)
392 return true;
393 const MachineOperand &FlagsOP = MI->getOperand(i: OpNum - 1);
394 if (!FlagsOP.isImm())
395 return true;
396 InlineAsm::Flag F(FlagsOP.getImm());
397
398 // This operand may not be the one that actually provides the register. If
399 // it's tied to a previous one then we should refer instead to that one
400 // for registers and their classes.
401 unsigned TiedIdx;
402 if (F.isUseOperandTiedToDef(Idx&: TiedIdx)) {
403 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
404 unsigned OpFlags = MI->getOperand(i: OpNum).getImm();
405 const InlineAsm::Flag F(OpFlags);
406 OpNum += F.getNumOperandRegisters() + 1;
407 }
408 F = InlineAsm::Flag(MI->getOperand(i: OpNum).getImm());
409
410 // Later code expects OpNum to be pointing at the register rather than
411 // the flags.
412 OpNum += 1;
413 }
414
415 const unsigned NumVals = F.getNumOperandRegisters();
416 unsigned RC;
417 bool FirstHalf;
418 const ARMBaseTargetMachine &ATM =
419 static_cast<const ARMBaseTargetMachine &>(TM);
420
421 // 'Q' should correspond to the low order register and 'R' to the high
422 // order register. Whether this corresponds to the upper or lower half
423 // depends on the endianess mode.
424 if (ExtraCode[0] == 'Q')
425 FirstHalf = ATM.isLittleEndian();
426 else
427 // ExtraCode[0] == 'R'.
428 FirstHalf = !ATM.isLittleEndian();
429 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
430 if (F.hasRegClassConstraint(RC) &&
431 ARM::GPRPairRegClass.hasSubClassEq(RC: TRI->getRegClass(i: RC))) {
432 if (NumVals != 1)
433 return true;
434 const MachineOperand &MO = MI->getOperand(i: OpNum);
435 if (!MO.isReg())
436 return true;
437 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
438 Register Reg =
439 TRI->getSubReg(Reg: MO.getReg(), Idx: FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
440 O << ARMInstPrinter::getRegisterName(Reg);
441 return false;
442 }
443 if (NumVals != 2)
444 return true;
445 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
446 if (RegOp >= MI->getNumOperands())
447 return true;
448 const MachineOperand &MO = MI->getOperand(i: RegOp);
449 if (!MO.isReg())
450 return true;
451 Register Reg = MO.getReg();
452 O << ARMInstPrinter::getRegisterName(Reg);
453 return false;
454 }
455
456 case 'e': // The low doubleword register of a NEON quad register.
457 case 'f': { // The high doubleword register of a NEON quad register.
458 if (!MI->getOperand(i: OpNum).isReg())
459 return true;
460 Register Reg = MI->getOperand(i: OpNum).getReg();
461 if (!ARM::QPRRegClass.contains(Reg))
462 return true;
463 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
464 Register SubReg =
465 TRI->getSubReg(Reg, Idx: ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
466 O << ARMInstPrinter::getRegisterName(Reg: SubReg);
467 return false;
468 }
469
470 // This modifier is not yet supported.
471 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
472 return true;
473 case 'H': { // The highest-numbered register of a pair.
474 const MachineOperand &MO = MI->getOperand(i: OpNum);
475 if (!MO.isReg())
476 return true;
477 const MachineFunction &MF = *MI->getParent()->getParent();
478 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
479 Register Reg = MO.getReg();
480 if(!ARM::GPRPairRegClass.contains(Reg))
481 return false;
482 Reg = TRI->getSubReg(Reg, Idx: ARM::gsub_1);
483 O << ARMInstPrinter::getRegisterName(Reg);
484 return false;
485 }
486 }
487 }
488
489 printOperand(MI, OpNum, O);
490 return false;
491}
492
493bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
494 unsigned OpNum, const char *ExtraCode,
495 raw_ostream &O) {
496 // Does this asm operand have a single letter operand modifier?
497 if (ExtraCode && ExtraCode[0]) {
498 if (ExtraCode[1] != 0) return true; // Unknown modifier.
499
500 switch (ExtraCode[0]) {
501 case 'A': // A memory operand for a VLD1/VST1 instruction.
502 default: return true; // Unknown modifier.
503 case 'm': // The base register of a memory operand.
504 if (!MI->getOperand(i: OpNum).isReg())
505 return true;
506 O << ARMInstPrinter::getRegisterName(Reg: MI->getOperand(i: OpNum).getReg());
507 return false;
508 }
509 }
510
511 const MachineOperand &MO = MI->getOperand(i: OpNum);
512 assert(MO.isReg() && "unexpected inline asm memory operand");
513 O << "[" << ARMInstPrinter::getRegisterName(Reg: MO.getReg()) << "]";
514 return false;
515}
516
517static bool isThumb(const MCSubtargetInfo& STI) {
518 return STI.hasFeature(Feature: ARM::ModeThumb);
519}
520
521void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
522 const MCSubtargetInfo *EndInfo,
523 const MachineInstr *MI) {
524 // If either end mode is unknown (EndInfo == NULL) or different than
525 // the start mode, then restore the start mode.
526 const bool WasThumb = isThumb(STI: StartInfo);
527 if (!EndInfo || WasThumb != isThumb(STI: *EndInfo)) {
528 auto &TS =
529 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
530 if (WasThumb)
531 TS.emitCode16();
532 else
533 TS.emitCode32();
534 }
535}
536
537void ARMAsmPrinter::emitStartOfAsmFile(Module &M) {
538 const Triple &TT = TM.getTargetTriple();
539 auto &TS =
540 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
541 // Use unified assembler syntax.
542 TS.emitSyntaxUnified();
543
544 // Emit ARM Build Attributes
545 if (TT.isOSBinFormatELF())
546 emitAttributes();
547
548 // Use the triple's architecture and subarchitecture to determine
549 // if we're thumb for the purposes of the top level code16 state.
550 if (!M.getModuleInlineAsm().empty() && TT.isThumb())
551 TS.emitCode16();
552}
553
554static void
555emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
556 MachineModuleInfoImpl::StubValueTy &MCSym) {
557 // L_foo$stub:
558 OutStreamer.emitLabel(Symbol: StubLabel);
559 // .indirect_symbol _foo
560 OutStreamer.emitSymbolAttribute(Symbol: MCSym.getPointer(), Attribute: MCSA_IndirectSymbol);
561
562 if (MCSym.getInt())
563 // External to current translation unit.
564 OutStreamer.emitIntValue(Value: 0, Size: 4/*size*/);
565 else
566 // Internal to current translation unit.
567 //
568 // When we place the LSDA into the TEXT section, the type info
569 // pointers need to be indirect and pc-rel. We accomplish this by
570 // using NLPs; however, sometimes the types are local to the file.
571 // We need to fill in the value for the NLP in those cases.
572 OutStreamer.emitValue(
573 Value: MCSymbolRefExpr::create(Symbol: MCSym.getPointer(), Ctx&: OutStreamer.getContext()),
574 Size: 4 /*size*/);
575}
576
577
578void ARMAsmPrinter::emitEndOfAsmFile(Module &M) {
579 const Triple &TT = TM.getTargetTriple();
580 if (TT.isOSBinFormatMachO()) {
581 // All darwin targets use mach-o.
582 const TargetLoweringObjectFileMachO &TLOFMacho =
583 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
584 MachineModuleInfoMachO &MMIMacho =
585 MMI->getObjFileInfo<MachineModuleInfoMachO>();
586
587 // Output non-lazy-pointers for external and common global variables.
588 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
589
590 if (!Stubs.empty()) {
591 // Switch with ".non_lazy_symbol_pointer" directive.
592 OutStreamer->switchSection(Section: TLOFMacho.getNonLazySymbolPointerSection());
593 emitAlignment(Alignment: Align(4));
594
595 for (auto &Stub : Stubs)
596 emitNonLazySymbolPointer(OutStreamer&: *OutStreamer, StubLabel: Stub.first, MCSym&: Stub.second);
597
598 Stubs.clear();
599 OutStreamer->addBlankLine();
600 }
601
602 Stubs = MMIMacho.GetThreadLocalGVStubList();
603 if (!Stubs.empty()) {
604 // Switch with ".non_lazy_symbol_pointer" directive.
605 OutStreamer->switchSection(Section: TLOFMacho.getThreadLocalPointerSection());
606 emitAlignment(Alignment: Align(4));
607
608 for (auto &Stub : Stubs)
609 emitNonLazySymbolPointer(OutStreamer&: *OutStreamer, StubLabel: Stub.first, MCSym&: Stub.second);
610
611 Stubs.clear();
612 OutStreamer->addBlankLine();
613 }
614
615 // Funny Darwin hack: This flag tells the linker that no global symbols
616 // contain code that falls through to other global symbols (e.g. the obvious
617 // implementation of multiple entry points). If this doesn't occur, the
618 // linker can safely perform dead code stripping. Since LLVM never
619 // generates code that does this, it is always safe to set.
620 OutStreamer->emitSubsectionsViaSymbols();
621 }
622
623 // The last attribute to be emitted is ABI_optimization_goals
624 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
625 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
626
627 if (OptimizationGoals > 0 &&
628 (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI()))
629 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_optimization_goals, Value: OptimizationGoals);
630 OptimizationGoals = -1;
631
632 ATS.finishAttributeSection();
633}
634
635//===----------------------------------------------------------------------===//
636// Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
637// FIXME:
638// The following seem like one-off assembler flags, but they actually need
639// to appear in the .ARM.attributes section in ELF.
640// Instead of subclassing the MCELFStreamer, we do the work here.
641
642// Returns true if all function definitions have the same function attribute
643// value. It also returns true when the module has no functions.
644static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
645 StringRef Value) {
646 return !any_of(Range: M, P: [&](const Function &F) {
647 if (F.isDeclaration())
648 return false;
649 return F.getFnAttribute(Kind: Attr).getValueAsString() != Value;
650 });
651}
652// Returns true if all functions definitions have the same denormal mode.
653// It also returns true when the module has no functions.
654static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr,
655 DenormalMode Value) {
656 return !any_of(Range: M, P: [&](const Function &F) {
657 if (F.isDeclaration())
658 return false;
659 StringRef AttrVal = F.getFnAttribute(Kind: Attr).getValueAsString();
660 return parseDenormalFPAttribute(Str: AttrVal) != Value;
661 });
662}
663
664// Returns true if all functions have different denormal modes.
665static bool checkDenormalAttributeInconsistency(const Module &M) {
666 auto F = M.functions().begin();
667 auto E = M.functions().end();
668 if (F == E)
669 return false;
670 DenormalMode Value = F->getDenormalModeRaw();
671 ++F;
672 return std::any_of(first: F, last: E, pred: [&](const Function &F) {
673 return !F.isDeclaration() && F.getDenormalModeRaw() != Value;
674 });
675}
676
677void ARMAsmPrinter::emitAttributes() {
678 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
679 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
680
681 ATS.emitTextAttribute(Attribute: ARMBuildAttrs::conformance, String: "2.09");
682
683 ATS.switchVendor(Vendor: "aeabi");
684
685 // Compute ARM ELF Attributes based on the default subtarget that
686 // we'd have constructed. The existing ARM behavior isn't LTO clean
687 // anyhow.
688 // FIXME: For ifunc related functions we could iterate over and look
689 // for a feature string that doesn't match the default one.
690 const Triple &TT = TM.getTargetTriple();
691 StringRef CPU = TM.getTargetCPU();
692 StringRef FS = TM.getTargetFeatureString();
693 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
694 if (!FS.empty()) {
695 if (!ArchFS.empty())
696 ArchFS = (Twine(ArchFS) + "," + FS).str();
697 else
698 ArchFS = std::string(FS);
699 }
700 const ARMBaseTargetMachine &ATM =
701 static_cast<const ARMBaseTargetMachine &>(TM);
702 const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
703 ATM.isLittleEndian());
704
705 // Emit build attributes for the available hardware.
706 ATS.emitTargetAttributes(STI);
707
708 // RW data addressing.
709 if (isPositionIndependent()) {
710 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RW_data,
711 Value: ARMBuildAttrs::AddressRWPCRel);
712 } else if (STI.isRWPI()) {
713 // RWPI specific attributes.
714 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RW_data,
715 Value: ARMBuildAttrs::AddressRWSBRel);
716 }
717
718 // RO data addressing.
719 if (isPositionIndependent() || STI.isROPI()) {
720 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RO_data,
721 Value: ARMBuildAttrs::AddressROPCRel);
722 }
723
724 // GOT use.
725 if (isPositionIndependent()) {
726 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_GOT_use,
727 Value: ARMBuildAttrs::AddressGOT);
728 } else {
729 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_GOT_use,
730 Value: ARMBuildAttrs::AddressDirect);
731 }
732
733 // Set FP Denormals.
734 if (checkDenormalAttributeConsistency(M: *MMI->getModule(), Attr: "denormal-fp-math",
735 Value: DenormalMode::getPreserveSign()))
736 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
737 Value: ARMBuildAttrs::PreserveFPSign);
738 else if (checkDenormalAttributeConsistency(M: *MMI->getModule(),
739 Attr: "denormal-fp-math",
740 Value: DenormalMode::getPositiveZero()))
741 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
742 Value: ARMBuildAttrs::PositiveZero);
743 else if (checkDenormalAttributeInconsistency(M: *MMI->getModule()) ||
744 checkDenormalAttributeConsistency(
745 M: *MMI->getModule(), Attr: "denormal-fp-math", Value: DenormalMode::getIEEE()))
746 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
747 Value: ARMBuildAttrs::IEEEDenormals);
748 else {
749 if (!STI.hasVFP2Base()) {
750 // When the target doesn't have an FPU (by design or
751 // intention), the assumptions made on the software support
752 // mirror that of the equivalent hardware support *if it
753 // existed*. For v7 and better we indicate that denormals are
754 // flushed preserving sign, and for V6 we indicate that
755 // denormals are flushed to positive zero.
756 if (STI.hasV7Ops())
757 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
758 Value: ARMBuildAttrs::PreserveFPSign);
759 } else if (STI.hasVFP3Base()) {
760 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
761 // the sign bit of the zero matches the sign bit of the input or
762 // result that is being flushed to zero.
763 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
764 Value: ARMBuildAttrs::PreserveFPSign);
765 }
766 // For VFPv2 implementations it is implementation defined as
767 // to whether denormals are flushed to positive zero or to
768 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
769 // LLVM has chosen to flush this to positive zero (most likely for
770 // GCC compatibility), so that's the chosen value here (the
771 // absence of its emission implies zero).
772 }
773
774 // Set FP exceptions and rounding
775 if (checkFunctionsAttributeConsistency(M: *MMI->getModule(),
776 Attr: "no-trapping-math", Value: "true") ||
777 TM.Options.NoTrappingFPMath)
778 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions,
779 Value: ARMBuildAttrs::Not_Allowed);
780 else {
781 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions, Value: ARMBuildAttrs::Allowed);
782
783 // If the user has permitted this code to choose the IEEE 754
784 // rounding at run-time, emit the rounding attribute.
785 if (TM.Options.HonorSignDependentRoundingFPMathOption)
786 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_rounding, Value: ARMBuildAttrs::Allowed);
787 }
788
789 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
790 // equivalent of GCC's -ffinite-math-only flag.
791 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
792 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_number_model,
793 Value: ARMBuildAttrs::Allowed);
794 else
795 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_number_model,
796 Value: ARMBuildAttrs::AllowIEEE754);
797
798 // FIXME: add more flags to ARMBuildAttributes.h
799 // 8-bytes alignment stuff.
800 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_align_needed, Value: 1);
801 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_align_preserved, Value: 1);
802
803 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
804 if (getTM().isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
805 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_VFP_args, Value: ARMBuildAttrs::HardFPAAPCS);
806
807 // FIXME: To support emitting this build attribute as GCC does, the
808 // -mfp16-format option and associated plumbing must be
809 // supported. For now the __fp16 type is exposed by default, so this
810 // attribute should be emitted with value 1.
811 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_16bit_format,
812 Value: ARMBuildAttrs::FP16FormatIEEE);
813
814 if (const Module *SourceModule = MMI->getModule()) {
815 // ABI_PCS_wchar_t to indicate wchar_t width
816 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
817 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
818 MD: SourceModule->getModuleFlag(Key: "wchar_size"))) {
819 int WCharWidth = WCharWidthValue->getZExtValue();
820 assert((WCharWidth == 2 || WCharWidth == 4) &&
821 "wchar_t width must be 2 or 4 bytes");
822 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_wchar_t, Value: WCharWidth);
823 }
824
825 // ABI_enum_size to indicate enum width
826 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
827 // (all enums contain a value needing 32 bits to encode).
828 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
829 MD: SourceModule->getModuleFlag(Key: "min_enum_size"))) {
830 int EnumWidth = EnumWidthValue->getZExtValue();
831 assert((EnumWidth == 1 || EnumWidth == 4) &&
832 "Minimum enum width must be 1 or 4 bytes");
833 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
834 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_enum_size, Value: EnumBuildAttr);
835 }
836
837 auto *PACValue = mdconst::extract_or_null<ConstantInt>(
838 MD: SourceModule->getModuleFlag(Key: "sign-return-address"));
839 if (PACValue && PACValue->isOne()) {
840 // If "+pacbti" is used as an architecture extension,
841 // Tag_PAC_extension is emitted in
842 // ARMTargetStreamer::emitTargetAttributes().
843 if (!STI.hasPACBTI()) {
844 ATS.emitAttribute(Attribute: ARMBuildAttrs::PAC_extension,
845 Value: ARMBuildAttrs::AllowPACInNOPSpace);
846 }
847 ATS.emitAttribute(Attribute: ARMBuildAttrs::PACRET_use, Value: ARMBuildAttrs::PACRETUsed);
848 }
849
850 auto *BTIValue = mdconst::extract_or_null<ConstantInt>(
851 MD: SourceModule->getModuleFlag(Key: "branch-target-enforcement"));
852 if (BTIValue && !BTIValue->isZero()) {
853 // If "+pacbti" is used as an architecture extension,
854 // Tag_BTI_extension is emitted in
855 // ARMTargetStreamer::emitTargetAttributes().
856 if (!STI.hasPACBTI()) {
857 ATS.emitAttribute(Attribute: ARMBuildAttrs::BTI_extension,
858 Value: ARMBuildAttrs::AllowBTIInNOPSpace);
859 }
860 ATS.emitAttribute(Attribute: ARMBuildAttrs::BTI_use, Value: ARMBuildAttrs::BTIUsed);
861 }
862 }
863
864 // We currently do not support using R9 as the TLS pointer.
865 if (STI.isRWPI())
866 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
867 Value: ARMBuildAttrs::R9IsSB);
868 else if (STI.isR9Reserved())
869 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
870 Value: ARMBuildAttrs::R9Reserved);
871 else
872 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
873 Value: ARMBuildAttrs::R9IsGPR);
874}
875
876//===----------------------------------------------------------------------===//
877
878static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
879 unsigned LabelId, MCContext &Ctx) {
880
881 MCSymbol *Label = Ctx.getOrCreateSymbol(Name: Twine(Prefix)
882 + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
883 return Label;
884}
885
886static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
887 unsigned LabelId, MCContext &Ctx) {
888
889 MCSymbol *Label = Ctx.getOrCreateSymbol(Name: Twine(Prefix)
890 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
891 return Label;
892}
893
894static uint8_t getModifierSpecifier(ARMCP::ARMCPModifier Modifier) {
895 switch (Modifier) {
896 case ARMCP::no_modifier:
897 return ARM::S_None;
898 case ARMCP::TLSGD:
899 return ARM::S_TLSGD;
900 case ARMCP::TPOFF:
901 return ARM::S_TPOFF;
902 case ARMCP::GOTTPOFF:
903 return ARM::S_GOTTPOFF;
904 case ARMCP::SBREL:
905 return ARM::S_SBREL;
906 case ARMCP::GOT_PREL:
907 return ARM::S_GOT_PREL;
908 case ARMCP::SECREL:
909 return ARM::S_COFF_SECREL;
910 }
911 llvm_unreachable("Invalid ARMCPModifier!");
912}
913
914MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
915 unsigned char TargetFlags) {
916 const Triple &TT = TM.getTargetTriple();
917 if (TT.isOSBinFormatMachO()) {
918 bool IsIndirect =
919 (TargetFlags & ARMII::MO_NONLAZY) && getTM().isGVIndirectSymbol(GV);
920
921 if (!IsIndirect)
922 return getSymbol(GV);
923
924 // FIXME: Remove this when Darwin transition to @GOT like syntax.
925 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, Suffix: "$non_lazy_ptr");
926 MachineModuleInfoMachO &MMIMachO =
927 MMI->getObjFileInfo<MachineModuleInfoMachO>();
928 MachineModuleInfoImpl::StubValueTy &StubSym =
929 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(Sym: MCSym)
930 : MMIMachO.getGVStubEntry(Sym: MCSym);
931
932 if (!StubSym.getPointer())
933 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
934 !GV->hasInternalLinkage());
935 return MCSym;
936 } else if (TT.isOSBinFormatCOFF()) {
937 assert(TT.isOSWindows() && "Windows is the only supported COFF target");
938
939 bool IsIndirect =
940 (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
941 if (!IsIndirect)
942 return getSymbol(GV);
943
944 SmallString<128> Name;
945 if (TargetFlags & ARMII::MO_DLLIMPORT)
946 Name = "__imp_";
947 else if (TargetFlags & ARMII::MO_COFFSTUB)
948 Name = ".refptr.";
949 getNameWithPrefix(Name, GV);
950
951 MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
952
953 if (TargetFlags & ARMII::MO_COFFSTUB) {
954 MachineModuleInfoCOFF &MMICOFF =
955 MMI->getObjFileInfo<MachineModuleInfoCOFF>();
956 MachineModuleInfoImpl::StubValueTy &StubSym =
957 MMICOFF.getGVStubEntry(Sym: MCSym);
958
959 if (!StubSym.getPointer())
960 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
961 }
962
963 return MCSym;
964 } else if (TT.isOSBinFormatELF()) {
965 return getSymbolPreferLocal(GV: *GV);
966 }
967 llvm_unreachable("unexpected target");
968}
969
970void ARMAsmPrinter::emitMachineConstantPoolValue(
971 MachineConstantPoolValue *MCPV) {
972 const DataLayout &DL = getDataLayout();
973 int Size = DL.getTypeAllocSize(Ty: MCPV->getType());
974
975 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
976
977 if (ACPV->isPromotedGlobal()) {
978 // This constant pool entry is actually a global whose storage has been
979 // promoted into the constant pool. This global may be referenced still
980 // by debug information, and due to the way AsmPrinter is set up, the debug
981 // info is immutable by the time we decide to promote globals to constant
982 // pools. Because of this, we need to ensure we emit a symbol for the global
983 // with private linkage (the default) so debug info can refer to it.
984 //
985 // However, if this global is promoted into several functions we must ensure
986 // we don't try and emit duplicate symbols!
987 auto *ACPC = cast<ARMConstantPoolConstant>(Val: ACPV);
988 for (const auto *GV : ACPC->promotedGlobals()) {
989 if (!EmittedPromotedGlobalLabels.count(Ptr: GV)) {
990 MCSymbol *GVSym = getSymbol(GV);
991 OutStreamer->emitLabel(Symbol: GVSym);
992 EmittedPromotedGlobalLabels.insert(Ptr: GV);
993 }
994 }
995 return emitGlobalConstant(DL, CV: ACPC->getPromotedGlobalInit());
996 }
997
998 MCSymbol *MCSym;
999 if (ACPV->isLSDA()) {
1000 MCSym = getMBBExceptionSym(MBB: MF->front());
1001 } else if (ACPV->isBlockAddress()) {
1002 const BlockAddress *BA =
1003 cast<ARMConstantPoolConstant>(Val: ACPV)->getBlockAddress();
1004 MCSym = GetBlockAddressSymbol(BA);
1005 } else if (ACPV->isGlobalValue()) {
1006 const GlobalValue *GV = cast<ARMConstantPoolConstant>(Val: ACPV)->getGV();
1007
1008 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
1009 // flag the global as MO_NONLAZY.
1010 unsigned char TF =
1011 TM.getTargetTriple().isOSBinFormatMachO() ? ARMII::MO_NONLAZY : 0;
1012 MCSym = GetARMGVSymbol(GV, TargetFlags: TF);
1013 } else if (ACPV->isMachineBasicBlock()) {
1014 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(Val: ACPV)->getMBB();
1015 MCSym = MBB->getSymbol();
1016 } else {
1017 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
1018 auto Sym = cast<ARMConstantPoolSymbol>(Val: ACPV)->getSymbol();
1019 MCSym = GetExternalSymbolSymbol(Sym);
1020 }
1021
1022 // Create an MCSymbol for the reference.
1023 const MCExpr *Expr = MCSymbolRefExpr::create(
1024 Symbol: MCSym, specifier: getModifierSpecifier(Modifier: ACPV->getModifier()), Ctx&: OutContext);
1025
1026 if (ACPV->getPCAdjustment()) {
1027 MCSymbol *PCLabel =
1028 getPICLabel(Prefix: DL.getPrivateGlobalPrefix(), FunctionNumber: getFunctionNumber(),
1029 LabelId: ACPV->getLabelId(), Ctx&: OutContext);
1030 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(Symbol: PCLabel, Ctx&: OutContext);
1031 PCRelExpr =
1032 MCBinaryExpr::createAdd(LHS: PCRelExpr,
1033 RHS: MCConstantExpr::create(Value: ACPV->getPCAdjustment(),
1034 Ctx&: OutContext),
1035 Ctx&: OutContext);
1036 if (ACPV->mustAddCurrentAddress()) {
1037 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
1038 // label, so just emit a local label end reference that instead.
1039 MCSymbol *DotSym = OutContext.createTempSymbol();
1040 OutStreamer->emitLabel(Symbol: DotSym);
1041 const MCExpr *DotExpr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
1042 PCRelExpr = MCBinaryExpr::createSub(LHS: PCRelExpr, RHS: DotExpr, Ctx&: OutContext);
1043 }
1044 Expr = MCBinaryExpr::createSub(LHS: Expr, RHS: PCRelExpr, Ctx&: OutContext);
1045 }
1046 OutStreamer->emitValue(Value: Expr, Size);
1047}
1048
1049void ARMAsmPrinter::emitJumpTableAddrs(const MachineInstr *MI) {
1050 const MachineOperand &MO1 = MI->getOperand(i: 1);
1051 unsigned JTI = MO1.getIndex();
1052
1053 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1054 // ARM mode tables.
1055 emitAlignment(Alignment: Align(4));
1056
1057 // Emit a label for the jump table.
1058 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1059 OutStreamer->emitLabel(Symbol: JTISymbol);
1060
1061 // Mark the jump table as data-in-code.
1062 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionJT32);
1063
1064 // Emit each entry of the table.
1065 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1066 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1067 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1068
1069 for (MachineBasicBlock *MBB : JTBBs) {
1070 // Construct an MCExpr for the entry. We want a value of the form:
1071 // (BasicBlockAddr - TableBeginAddr)
1072 //
1073 // For example, a table with entries jumping to basic blocks BB0 and BB1
1074 // would look like:
1075 // LJTI_0_0:
1076 // .word (LBB0 - LJTI_0_0)
1077 // .word (LBB1 - LJTI_0_0)
1078 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(), Ctx&: OutContext);
1079
1080 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1081 if (isPositionIndependent() || STI.isROPI())
1082 Expr = MCBinaryExpr::createSub(LHS: Expr, RHS: MCSymbolRefExpr::create(Symbol: JTISymbol,
1083 Ctx&: OutContext),
1084 Ctx&: OutContext);
1085 // If we're generating a table of Thumb addresses in static relocation
1086 // model, we need to add one to keep interworking correctly.
1087 else if (AFI->isThumbFunction())
1088 Expr = MCBinaryExpr::createAdd(LHS: Expr, RHS: MCConstantExpr::create(Value: 1,Ctx&: OutContext),
1089 Ctx&: OutContext);
1090 OutStreamer->emitValue(Value: Expr, Size: 4);
1091 }
1092 // Mark the end of jump table data-in-code region.
1093 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1094}
1095
1096void ARMAsmPrinter::emitJumpTableInsts(const MachineInstr *MI) {
1097 const MachineOperand &MO1 = MI->getOperand(i: 1);
1098 unsigned JTI = MO1.getIndex();
1099
1100 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1101 // ARM mode tables.
1102 emitAlignment(Alignment: Align(4));
1103
1104 // Emit a label for the jump table.
1105 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1106 OutStreamer->emitLabel(Symbol: JTISymbol);
1107
1108 // Emit each entry of the table.
1109 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1110 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1111 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1112
1113 for (MachineBasicBlock *MBB : JTBBs) {
1114 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(),
1115 Ctx&: OutContext);
1116 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1117 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2B)
1118 .addExpr(Val: MBBSymbolExpr)
1119 .addImm(Val: ARMCC::AL)
1120 .addReg(Reg: 0));
1121 }
1122}
1123
1124void ARMAsmPrinter::emitJumpTableTBInst(const MachineInstr *MI,
1125 unsigned OffsetWidth) {
1126 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1127 const MachineOperand &MO1 = MI->getOperand(i: 1);
1128 unsigned JTI = MO1.getIndex();
1129
1130 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1131 if (STI.isThumb1Only())
1132 emitAlignment(Alignment: Align(4));
1133
1134 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1135 OutStreamer->emitLabel(Symbol: JTISymbol);
1136
1137 // Emit each entry of the table.
1138 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1139 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1140 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1141
1142 // Mark the jump table as data-in-code.
1143 OutStreamer->emitDataRegion(Kind: OffsetWidth == 1 ? MCDR_DataRegionJT8
1144 : MCDR_DataRegionJT16);
1145
1146 for (auto *MBB : JTBBs) {
1147 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(),
1148 Ctx&: OutContext);
1149 // Otherwise it's an offset from the dispatch instruction. Construct an
1150 // MCExpr for the entry. We want a value of the form:
1151 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1152 //
1153 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1154 // would look like:
1155 // LJTI_0_0:
1156 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1157 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1158 // where LCPI0_0 is a label defined just before the TBB instruction using
1159 // this table.
1160 MCSymbol *TBInstPC = GetCPISymbol(CPID: MI->getOperand(i: 0).getImm());
1161 const MCExpr *Expr = MCBinaryExpr::createAdd(
1162 LHS: MCSymbolRefExpr::create(Symbol: TBInstPC, Ctx&: OutContext),
1163 RHS: MCConstantExpr::create(Value: 4, Ctx&: OutContext), Ctx&: OutContext);
1164 Expr = MCBinaryExpr::createSub(LHS: MBBSymbolExpr, RHS: Expr, Ctx&: OutContext);
1165 Expr = MCBinaryExpr::createDiv(LHS: Expr, RHS: MCConstantExpr::create(Value: 2, Ctx&: OutContext),
1166 Ctx&: OutContext);
1167 OutStreamer->emitValue(Value: Expr, Size: OffsetWidth);
1168 }
1169 // Mark the end of jump table data-in-code region. 32-bit offsets use
1170 // actual branch instructions here, so we don't mark those as a data-region
1171 // at all.
1172 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1173
1174 // Make sure the next instruction is 2-byte aligned.
1175 emitAlignment(Alignment: Align(2));
1176}
1177
1178std::tuple<const MCSymbol *, uint64_t, const MCSymbol *,
1179 codeview::JumpTableEntrySize>
1180ARMAsmPrinter::getCodeViewJumpTableInfo(int JTI,
1181 const MachineInstr *BranchInstr,
1182 const MCSymbol *BranchLabel) const {
1183 codeview::JumpTableEntrySize EntrySize;
1184 const MCSymbol *BaseLabel;
1185 uint64_t BaseOffset = 0;
1186 switch (BranchInstr->getOpcode()) {
1187 case ARM::BR_JTadd:
1188 case ARM::BR_JTr:
1189 case ARM::tBR_JTr:
1190 // Word relative to the jump table address.
1191 EntrySize = codeview::JumpTableEntrySize::UInt32;
1192 BaseLabel = GetARMJTIPICJumpTableLabel(uid: JTI);
1193 break;
1194 case ARM::tTBH_JT:
1195 case ARM::t2TBH_JT:
1196 // half-word shifted left, relative to *after* the branch instruction.
1197 EntrySize = codeview::JumpTableEntrySize::UInt16ShiftLeft;
1198 BranchLabel = GetCPISymbol(CPID: BranchInstr->getOperand(i: 3).getImm());
1199 BaseLabel = BranchLabel;
1200 BaseOffset = 4;
1201 break;
1202 case ARM::tTBB_JT:
1203 case ARM::t2TBB_JT:
1204 // byte shifted left, relative to *after* the branch instruction.
1205 EntrySize = codeview::JumpTableEntrySize::UInt8ShiftLeft;
1206 BranchLabel = GetCPISymbol(CPID: BranchInstr->getOperand(i: 3).getImm());
1207 BaseLabel = BranchLabel;
1208 BaseOffset = 4;
1209 break;
1210 case ARM::t2BR_JT:
1211 // Direct jump.
1212 BaseLabel = nullptr;
1213 EntrySize = codeview::JumpTableEntrySize::Pointer;
1214 break;
1215 default:
1216 llvm_unreachable("Unknown jump table instruction");
1217 }
1218
1219 return std::make_tuple(args&: BaseLabel, args&: BaseOffset, args&: BranchLabel, args&: EntrySize);
1220}
1221
1222void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1223 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1224 "Only instruction which are involved into frame setup code are allowed");
1225
1226 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1227 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1228 const MachineFunction &MF = *MI->getParent()->getParent();
1229 const TargetRegisterInfo *TargetRegInfo =
1230 MF.getSubtarget().getRegisterInfo();
1231 const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1232
1233 Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1234 unsigned Opc = MI->getOpcode();
1235 unsigned SrcReg, DstReg;
1236
1237 switch (Opc) {
1238 case ARM::tPUSH:
1239 // special case: tPUSH does not have src/dst regs.
1240 SrcReg = DstReg = ARM::SP;
1241 break;
1242 case ARM::tLDRpci:
1243 case ARM::t2MOVi16:
1244 case ARM::t2MOVTi16:
1245 case ARM::tMOVi8:
1246 case ARM::tADDi8:
1247 case ARM::tLSLri:
1248 // special cases:
1249 // 1) for Thumb1 code we sometimes materialize the constant via constpool
1250 // load.
1251 // 2) for Thumb1 execute only code we materialize the constant via the
1252 // following pattern:
1253 // movs r3, #:upper8_15:<const>
1254 // lsls r3, #8
1255 // adds r3, #:upper0_7:<const>
1256 // lsls r3, #8
1257 // adds r3, #:lower8_15:<const>
1258 // lsls r3, #8
1259 // adds r3, #:lower0_7:<const>
1260 // So we need to special-case MOVS, ADDS and LSLS, and keep track of
1261 // where we are in the sequence with the simplest of state machines.
1262 // 3) for Thumb2 execute only code we materialize the constant via
1263 // immediate constants in 2 separate instructions (MOVW/MOVT).
1264 SrcReg = ~0U;
1265 DstReg = MI->getOperand(i: 0).getReg();
1266 break;
1267 case ARM::VMRS:
1268 SrcReg = ARM::FPSCR;
1269 DstReg = MI->getOperand(i: 0).getReg();
1270 break;
1271 case ARM::VMRS_FPEXC:
1272 SrcReg = ARM::FPEXC;
1273 DstReg = MI->getOperand(i: 0).getReg();
1274 break;
1275 default:
1276 SrcReg = MI->getOperand(i: 1).getReg();
1277 DstReg = MI->getOperand(i: 0).getReg();
1278 break;
1279 }
1280
1281 // Try to figure out the unwinding opcode out of src / dst regs.
1282 if (MI->mayStore()) {
1283 // Register saves.
1284 assert(DstReg == ARM::SP &&
1285 "Only stack pointer as a destination reg is supported");
1286
1287 SmallVector<MCRegister, 4> RegList;
1288 // Skip src & dst reg, and pred ops.
1289 unsigned StartOp = 2 + 2;
1290 // Use all the operands.
1291 unsigned NumOffset = 0;
1292 // Amount of SP adjustment folded into a push, before the
1293 // registers are stored (pad at higher addresses).
1294 unsigned PadBefore = 0;
1295 // Amount of SP adjustment folded into a push, after the
1296 // registers are stored (pad at lower addresses).
1297 unsigned PadAfter = 0;
1298
1299 switch (Opc) {
1300 default:
1301 MI->print(OS&: errs());
1302 llvm_unreachable("Unsupported opcode for unwinding information");
1303 case ARM::tPUSH:
1304 // Special case here: no src & dst reg, but two extra imp ops.
1305 StartOp = 2; NumOffset = 2;
1306 [[fallthrough]];
1307 case ARM::STMDB_UPD:
1308 case ARM::t2STMDB_UPD:
1309 case ARM::VSTMDDB_UPD:
1310 assert(SrcReg == ARM::SP &&
1311 "Only stack pointer as a source reg is supported");
1312 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1313 i != NumOps; ++i) {
1314 const MachineOperand &MO = MI->getOperand(i);
1315 // Actually, there should never be any impdef stuff here. Skip it
1316 // temporary to workaround PR11902.
1317 if (MO.isImplicit())
1318 continue;
1319 // Registers, pushed as a part of folding an SP update into the
1320 // push instruction are marked as undef and should not be
1321 // restored when unwinding, because the function can modify the
1322 // corresponding stack slots.
1323 if (MO.isUndef()) {
1324 assert(RegList.empty() &&
1325 "Pad registers must come before restored ones");
1326 unsigned Width =
1327 TargetRegInfo->getRegSizeInBits(Reg: MO.getReg(), MRI: MachineRegInfo) / 8;
1328 PadAfter += Width;
1329 continue;
1330 }
1331 // Check for registers that are remapped (for a Thumb1 prologue that
1332 // saves high registers).
1333 Register Reg = MO.getReg();
1334 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: Reg))
1335 Reg = RemappedReg;
1336 RegList.push_back(Elt: Reg);
1337 }
1338 break;
1339 case ARM::STR_PRE_IMM:
1340 case ARM::STR_PRE_REG:
1341 case ARM::t2STR_PRE:
1342 assert(MI->getOperand(2).getReg() == ARM::SP &&
1343 "Only stack pointer as a source reg is supported");
1344 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1345 SrcReg = RemappedReg;
1346
1347 RegList.push_back(Elt: SrcReg);
1348 break;
1349 case ARM::t2STRD_PRE:
1350 assert(MI->getOperand(3).getReg() == ARM::SP &&
1351 "Only stack pointer as a source reg is supported");
1352 SrcReg = MI->getOperand(i: 1).getReg();
1353 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1354 SrcReg = RemappedReg;
1355 RegList.push_back(Elt: SrcReg);
1356 SrcReg = MI->getOperand(i: 2).getReg();
1357 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1358 SrcReg = RemappedReg;
1359 RegList.push_back(Elt: SrcReg);
1360 PadBefore = -MI->getOperand(i: 4).getImm() - 8;
1361 break;
1362 }
1363 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1364 if (PadBefore)
1365 ATS.emitPad(Offset: PadBefore);
1366 ATS.emitRegSave(RegList, isVector: Opc == ARM::VSTMDDB_UPD);
1367 // Account for the SP adjustment, folded into the push.
1368 if (PadAfter)
1369 ATS.emitPad(Offset: PadAfter);
1370 }
1371 } else {
1372 // Changes of stack / frame pointer.
1373 if (SrcReg == ARM::SP) {
1374 int64_t Offset = 0;
1375 switch (Opc) {
1376 default:
1377 MI->print(OS&: errs());
1378 llvm_unreachable("Unsupported opcode for unwinding information");
1379 case ARM::tLDRspi:
1380 // Used to restore LR in a prologue which uses it as a temporary, has
1381 // no effect on unwind tables.
1382 return;
1383 case ARM::MOVr:
1384 case ARM::tMOVr:
1385 Offset = 0;
1386 break;
1387 case ARM::ADDri:
1388 case ARM::t2ADDri:
1389 case ARM::t2ADDri12:
1390 case ARM::t2ADDspImm:
1391 case ARM::t2ADDspImm12:
1392 Offset = -MI->getOperand(i: 2).getImm();
1393 break;
1394 case ARM::SUBri:
1395 case ARM::t2SUBri:
1396 case ARM::t2SUBri12:
1397 case ARM::t2SUBspImm:
1398 case ARM::t2SUBspImm12:
1399 Offset = MI->getOperand(i: 2).getImm();
1400 break;
1401 case ARM::tSUBspi:
1402 Offset = MI->getOperand(i: 2).getImm()*4;
1403 break;
1404 case ARM::tADDspi:
1405 case ARM::tADDrSPi:
1406 Offset = -MI->getOperand(i: 2).getImm()*4;
1407 break;
1408 case ARM::tADDhirr:
1409 Offset =
1410 -AFI->EHPrologueOffsetInRegs.lookup(Val: MI->getOperand(i: 2).getReg());
1411 break;
1412 }
1413
1414 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1415 if (DstReg == FramePtr && FramePtr != ARM::SP)
1416 // Set-up of the frame pointer. Positive values correspond to "add"
1417 // instruction.
1418 ATS.emitSetFP(FpReg: FramePtr, SpReg: ARM::SP, Offset: -Offset);
1419 else if (DstReg == ARM::SP) {
1420 // Change of SP by an offset. Positive values correspond to "sub"
1421 // instruction.
1422 ATS.emitPad(Offset);
1423 } else {
1424 // Move of SP to a register. Positive values correspond to an "add"
1425 // instruction.
1426 ATS.emitMovSP(Reg: DstReg, Offset: -Offset);
1427 }
1428 }
1429 } else if (DstReg == ARM::SP) {
1430 MI->print(OS&: errs());
1431 llvm_unreachable("Unsupported opcode for unwinding information");
1432 } else {
1433 int64_t Offset = 0;
1434 switch (Opc) {
1435 case ARM::tMOVr:
1436 // If a Thumb1 function spills r8-r11, we copy the values to low
1437 // registers before pushing them. Record the copy so we can emit the
1438 // correct ".save" later.
1439 AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1440 break;
1441 case ARM::VMRS:
1442 case ARM::VMRS_FPEXC:
1443 // If a function spills FPSCR or FPEXC, we copy the values to low
1444 // registers before pushing them. However, we can't issue annotations
1445 // for FP status registers because ".save" requires GPR registers, and
1446 // ".vsave" requires DPR registers, so don't record the copy and simply
1447 // emit annotations for the source registers used for the store.
1448 break;
1449 case ARM::tLDRpci: {
1450 // Grab the constpool index and check, whether it corresponds to
1451 // original or cloned constpool entry.
1452 unsigned CPI = MI->getOperand(i: 1).getIndex();
1453 const MachineConstantPool *MCP = MF.getConstantPool();
1454 if (CPI >= MCP->getConstants().size())
1455 CPI = AFI->getOriginalCPIdx(CloneIdx: CPI);
1456 assert(CPI != -1U && "Invalid constpool index");
1457
1458 // Derive the actual offset.
1459 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1460 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1461 Offset = cast<ConstantInt>(Val: CPE.Val.ConstVal)->getSExtValue();
1462 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1463 break;
1464 }
1465 case ARM::t2MOVi16:
1466 Offset = MI->getOperand(i: 1).getImm();
1467 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1468 break;
1469 case ARM::t2MOVTi16:
1470 Offset = MI->getOperand(i: 2).getImm();
1471 AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1472 break;
1473 case ARM::tMOVi8:
1474 Offset = MI->getOperand(i: 2).getImm();
1475 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1476 break;
1477 case ARM::tLSLri:
1478 assert(MI->getOperand(3).getImm() == 8 &&
1479 "The shift amount is not equal to 8");
1480 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1481 "The source register is not equal to the destination register");
1482 AFI->EHPrologueOffsetInRegs[DstReg] <<= 8;
1483 break;
1484 case ARM::tADDi8:
1485 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1486 "The source register is not equal to the destination register");
1487 Offset = MI->getOperand(i: 3).getImm();
1488 AFI->EHPrologueOffsetInRegs[DstReg] += Offset;
1489 break;
1490 case ARM::t2PAC:
1491 case ARM::t2PACBTI:
1492 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1493 break;
1494 default:
1495 MI->print(OS&: errs());
1496 llvm_unreachable("Unsupported opcode for unwinding information");
1497 }
1498 }
1499 }
1500}
1501
1502// Simple pseudo-instructions have their lowering (with expansion to real
1503// instructions) auto-generated.
1504#include "ARMGenMCPseudoLowering.inc"
1505
1506// Helper function to check if a register is live (used as an implicit operand)
1507// in the given call instruction.
1508static bool isRegisterLiveInCall(const MachineInstr &Call, MCRegister Reg) {
1509 for (const MachineOperand &MO : Call.implicit_operands()) {
1510 if (MO.isReg() && MO.getReg() == Reg && MO.isUse()) {
1511 return true;
1512 }
1513 }
1514 return false;
1515}
1516
1517void ARMAsmPrinter::EmitKCFI_CHECK_ARM32(Register AddrReg, int64_t Type,
1518 const MachineInstr &Call,
1519 int64_t PrefixNops) {
1520 // Choose scratch register: r12 primary, r3 if target is r12.
1521 unsigned ScratchReg = ARM::R12;
1522 if (AddrReg == ARM::R12) {
1523 ScratchReg = ARM::R3;
1524 }
1525
1526 // Calculate ESR for ARM mode (16-bit): 0x8000 | (scratch_reg << 5) | addr_reg
1527 // Note: scratch_reg is always 0x1F since the EOR sequence clobbers it.
1528 const ARMBaseRegisterInfo *TRI = static_cast<const ARMBaseRegisterInfo *>(
1529 MF->getSubtarget().getRegisterInfo());
1530 unsigned AddrIndex = TRI->getEncodingValue(Reg: AddrReg);
1531 unsigned ESR = 0x8000 | (31 << 5) | (AddrIndex & 31);
1532
1533 // Check if r3 is live and needs to be spilled.
1534 bool NeedSpillR3 =
1535 (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, Reg: ARM::R3);
1536
1537 // If we need to spill r3, push it first.
1538 if (NeedSpillR3) {
1539 // push {r3}
1540 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::STMDB_UPD)
1541 .addReg(Reg: ARM::SP)
1542 .addReg(Reg: ARM::SP)
1543 .addImm(Val: ARMCC::AL)
1544 .addReg(Reg: 0)
1545 .addReg(Reg: ARM::R3));
1546 }
1547
1548 // Clear bit 0 of target address to handle Thumb function pointers.
1549 // In 32-bit ARM, function pointers may have the low bit set to indicate
1550 // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later).
1551 // We need to clear it to avoid an alignment fault when loading.
1552 // bic scratch, target, #1
1553 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::BICri)
1554 .addReg(Reg: ScratchReg)
1555 .addReg(Reg: AddrReg)
1556 .addImm(Val: 1)
1557 .addImm(Val: ARMCC::AL)
1558 .addReg(Reg: 0)
1559 .addReg(Reg: 0));
1560
1561 // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)]
1562 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
1563 .addReg(Reg: ScratchReg)
1564 .addReg(Reg: ScratchReg)
1565 .addImm(Val: -(PrefixNops * 4 + 4))
1566 .addImm(Val: ARMCC::AL)
1567 .addReg(Reg: 0));
1568
1569 // Each EOR instruction XORs one byte of the type, shifted to its position.
1570 for (int i = 0; i < 4; i++) {
1571 uint8_t byte = (Type >> (i * 8)) & 0xFF;
1572 uint32_t imm = byte << (i * 8);
1573 bool isLast = (i == 3);
1574
1575 // Encode as ARM modified immediate.
1576 int SOImmVal = ARM_AM::getSOImmVal(Arg: imm);
1577 assert(SOImmVal != -1 &&
1578 "Cannot encode immediate as ARM modified immediate");
1579
1580 // eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
1581 EmitToStreamer(S&: *OutStreamer,
1582 Inst: MCInstBuilder(ARM::EORri)
1583 .addReg(Reg: ScratchReg)
1584 .addReg(Reg: ScratchReg)
1585 .addImm(Val: SOImmVal)
1586 .addImm(Val: ARMCC::AL)
1587 .addReg(Reg: 0)
1588 .addReg(Reg: isLast ? ARM::CPSR : ARM::NoRegister));
1589 }
1590
1591 // If we spilled r3, restore it immediately after the comparison.
1592 // This must happen before the branch so r3 is valid on both paths.
1593 if (NeedSpillR3) {
1594 // pop {r3}
1595 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDMIA_UPD)
1596 .addReg(Reg: ARM::SP)
1597 .addReg(Reg: ARM::SP)
1598 .addImm(Val: ARMCC::AL)
1599 .addReg(Reg: 0)
1600 .addReg(Reg: ARM::R3));
1601 }
1602
1603 // beq .Lpass (branch if types match, i.e., scratch is zero)
1604 MCSymbol *Pass = OutContext.createTempSymbol();
1605 EmitToStreamer(S&: *OutStreamer,
1606 Inst: MCInstBuilder(ARM::Bcc)
1607 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1608 .addImm(Val: ARMCC::EQ)
1609 .addReg(Reg: ARM::CPSR));
1610
1611 // udf #ESR (trap with encoded diagnostic)
1612 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::UDF).addImm(Val: ESR));
1613
1614 OutStreamer->emitLabel(Symbol: Pass);
1615}
1616
1617void ARMAsmPrinter::EmitKCFI_CHECK_Thumb2(Register AddrReg, int64_t Type,
1618 const MachineInstr &Call,
1619 int64_t PrefixNops) {
1620 // Choose scratch register: r12 primary, r3 if target is r12.
1621 unsigned ScratchReg = ARM::R12;
1622 if (AddrReg == ARM::R12) {
1623 ScratchReg = ARM::R3;
1624 }
1625
1626 // Calculate ESR for Thumb mode (8-bit): 0x80 | addr_reg
1627 // Bit 7: KCFI trap indicator
1628 // Bits 6-5: Reserved
1629 // Bits 4-0: Address register encoding
1630 const ARMBaseRegisterInfo *TRI = static_cast<const ARMBaseRegisterInfo *>(
1631 MF->getSubtarget().getRegisterInfo());
1632 unsigned AddrIndex = TRI->getEncodingValue(Reg: AddrReg);
1633 unsigned ESR = 0x80 | (AddrIndex & 0x1F);
1634
1635 // Check if r3 is live and needs to be spilled.
1636 bool NeedSpillR3 =
1637 (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, Reg: ARM::R3);
1638
1639 // If we need to spill r3, push it first.
1640 if (NeedSpillR3) {
1641 // push {r3}
1642 EmitToStreamer(
1643 S&: *OutStreamer,
1644 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1645 }
1646
1647 // Clear bit 0 of target address to handle Thumb function pointers.
1648 // In 32-bit ARM, function pointers may have the low bit set to indicate
1649 // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later).
1650 // We need to clear it to avoid an alignment fault when loading.
1651 // bic scratch, target, #1
1652 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2BICri)
1653 .addReg(Reg: ScratchReg)
1654 .addReg(Reg: AddrReg)
1655 .addImm(Val: 1)
1656 .addImm(Val: ARMCC::AL)
1657 .addReg(Reg: 0)
1658 .addReg(Reg: 0));
1659
1660 // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)]
1661 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi8)
1662 .addReg(Reg: ScratchReg)
1663 .addReg(Reg: ScratchReg)
1664 .addImm(Val: -(PrefixNops * 4 + 4))
1665 .addImm(Val: ARMCC::AL)
1666 .addReg(Reg: 0));
1667
1668 // Each EOR instruction XORs one byte of the type, shifted to its position.
1669 for (int i = 0; i < 4; i++) {
1670 uint8_t byte = (Type >> (i * 8)) & 0xFF;
1671 uint32_t imm = byte << (i * 8);
1672 bool isLast = (i == 3);
1673
1674 // Verify the immediate can be encoded as Thumb2 modified immediate.
1675 assert(ARM_AM::getT2SOImmVal(imm) != -1 &&
1676 "Cannot encode immediate as Thumb2 modified immediate");
1677
1678 // eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
1679 EmitToStreamer(S&: *OutStreamer,
1680 Inst: MCInstBuilder(ARM::t2EORri)
1681 .addReg(Reg: ScratchReg)
1682 .addReg(Reg: ScratchReg)
1683 .addImm(Val: imm)
1684 .addImm(Val: ARMCC::AL)
1685 .addReg(Reg: 0)
1686 .addReg(Reg: isLast ? ARM::CPSR : ARM::NoRegister));
1687 }
1688
1689 // If we spilled r3, restore it immediately after the comparison.
1690 // This must happen before the branch so r3 is valid on both paths.
1691 if (NeedSpillR3) {
1692 // pop {r3}
1693 EmitToStreamer(
1694 S&: *OutStreamer,
1695 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1696 }
1697
1698 // beq .Lpass (branch if types match, i.e., scratch is zero)
1699 MCSymbol *Pass = OutContext.createTempSymbol();
1700 EmitToStreamer(S&: *OutStreamer,
1701 Inst: MCInstBuilder(ARM::t2Bcc)
1702 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1703 .addImm(Val: ARMCC::EQ)
1704 .addReg(Reg: ARM::CPSR));
1705
1706 // udf #ESR (trap with encoded diagnostic)
1707 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tUDF).addImm(Val: ESR));
1708
1709 OutStreamer->emitLabel(Symbol: Pass);
1710}
1711
1712void ARMAsmPrinter::EmitKCFI_CHECK_Thumb1(Register AddrReg, int64_t Type,
1713 const MachineInstr &Call,
1714 int64_t PrefixNops) {
1715 // For Thumb1, use R2 unconditionally as scratch register (a low register
1716 // required for tLDRi). R3 is used for building the type hash.
1717 unsigned ScratchReg = ARM::R2;
1718 unsigned TempReg = ARM::R3;
1719
1720 // Check if r3 is live and needs to be spilled.
1721 bool NeedSpillR3 = isRegisterLiveInCall(Call, Reg: ARM::R3);
1722
1723 // Spill r3 if needed
1724 if (NeedSpillR3) {
1725 EmitToStreamer(
1726 S&: *OutStreamer,
1727 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1728 }
1729
1730 // Check if r2 is live and needs to be spilled.
1731 bool NeedSpillR2 = isRegisterLiveInCall(Call, Reg: ARM::R2);
1732
1733 // Push R2 if it's live
1734 if (NeedSpillR2) {
1735 EmitToStreamer(
1736 S&: *OutStreamer,
1737 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R2));
1738 }
1739
1740 // Clear bit 0 from target address
1741 // TempReg (R3) is used first as helper for BIC, then later for building type
1742 // hash.
1743
1744 // movs temp, #1
1745 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
1746 .addReg(Reg: TempReg)
1747 .addReg(Reg: ARM::CPSR)
1748 .addImm(Val: 1)
1749 .addImm(Val: ARMCC::AL)
1750 .addReg(Reg: 0));
1751
1752 // mov scratch, target
1753 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
1754 .addReg(Reg: ScratchReg)
1755 .addReg(Reg: AddrReg)
1756 .addImm(Val: ARMCC::AL));
1757
1758 // bics scratch, temp (scratch = scratch & ~temp)
1759 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBIC)
1760 .addReg(Reg: ScratchReg)
1761 .addReg(Reg: ARM::CPSR)
1762 .addReg(Reg: ScratchReg)
1763 .addReg(Reg: TempReg)
1764 .addImm(Val: ARMCC::AL)
1765 .addReg(Reg: 0));
1766
1767 // Load type hash. Thumb1 doesn't support negative offsets, so subtract.
1768 int offset = PrefixNops * 4 + 4;
1769
1770 // subs scratch, #offset
1771 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tSUBi8)
1772 .addReg(Reg: ScratchReg)
1773 .addReg(Reg: ARM::CPSR)
1774 .addReg(Reg: ScratchReg)
1775 .addImm(Val: offset)
1776 .addImm(Val: ARMCC::AL)
1777 .addReg(Reg: 0));
1778
1779 // ldr scratch, [scratch, #0]
1780 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
1781 .addReg(Reg: ScratchReg)
1782 .addReg(Reg: ScratchReg)
1783 .addImm(Val: 0)
1784 .addImm(Val: ARMCC::AL)
1785 .addReg(Reg: 0));
1786
1787 // Load expected type inline (instead of EOR sequence)
1788 //
1789 // This creates the 32-bit value byte-by-byte in the temp register:
1790 // movs temp, #byte3 (high byte)
1791 // lsls temp, temp, #8
1792 // adds temp, #byte2
1793 // lsls temp, temp, #8
1794 // adds temp, #byte1
1795 // lsls temp, temp, #8
1796 // adds temp, #byte0 (low byte)
1797
1798 uint8_t byte0 = (Type >> 0) & 0xFF;
1799 uint8_t byte1 = (Type >> 8) & 0xFF;
1800 uint8_t byte2 = (Type >> 16) & 0xFF;
1801 uint8_t byte3 = (Type >> 24) & 0xFF;
1802
1803 // movs temp, #byte3 (start with high byte)
1804 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
1805 .addReg(Reg: TempReg)
1806 .addReg(Reg: ARM::CPSR)
1807 .addImm(Val: byte3)
1808 .addImm(Val: ARMCC::AL)
1809 .addReg(Reg: 0));
1810
1811 // lsls temp, temp, #8
1812 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1813 .addReg(Reg: TempReg)
1814 .addReg(Reg: ARM::CPSR)
1815 .addReg(Reg: TempReg)
1816 .addImm(Val: 8)
1817 .addImm(Val: ARMCC::AL)
1818 .addReg(Reg: 0));
1819
1820 // adds temp, #byte2
1821 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1822 .addReg(Reg: TempReg)
1823 .addReg(Reg: ARM::CPSR)
1824 .addReg(Reg: TempReg)
1825 .addImm(Val: byte2)
1826 .addImm(Val: ARMCC::AL)
1827 .addReg(Reg: 0));
1828
1829 // lsls temp, temp, #8
1830 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1831 .addReg(Reg: TempReg)
1832 .addReg(Reg: ARM::CPSR)
1833 .addReg(Reg: TempReg)
1834 .addImm(Val: 8)
1835 .addImm(Val: ARMCC::AL)
1836 .addReg(Reg: 0));
1837
1838 // adds temp, #byte1
1839 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1840 .addReg(Reg: TempReg)
1841 .addReg(Reg: ARM::CPSR)
1842 .addReg(Reg: TempReg)
1843 .addImm(Val: byte1)
1844 .addImm(Val: ARMCC::AL)
1845 .addReg(Reg: 0));
1846
1847 // lsls temp, temp, #8
1848 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1849 .addReg(Reg: TempReg)
1850 .addReg(Reg: ARM::CPSR)
1851 .addReg(Reg: TempReg)
1852 .addImm(Val: 8)
1853 .addImm(Val: ARMCC::AL)
1854 .addReg(Reg: 0));
1855
1856 // adds temp, #byte0 (low byte)
1857 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1858 .addReg(Reg: TempReg)
1859 .addReg(Reg: ARM::CPSR)
1860 .addReg(Reg: TempReg)
1861 .addImm(Val: byte0)
1862 .addImm(Val: ARMCC::AL)
1863 .addReg(Reg: 0));
1864
1865 // cmp scratch, temp
1866 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tCMPr)
1867 .addReg(Reg: ScratchReg)
1868 .addReg(Reg: TempReg)
1869 .addImm(Val: ARMCC::AL)
1870 .addReg(Reg: 0));
1871
1872 // Restore registers if spilled (pop in reverse order of push: R2, then R3)
1873 if (NeedSpillR2) {
1874 // pop {r2}
1875 EmitToStreamer(
1876 S&: *OutStreamer,
1877 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R2));
1878 }
1879
1880 // Restore r3 if spilled
1881 if (NeedSpillR3) {
1882 // pop {r3}
1883 EmitToStreamer(
1884 S&: *OutStreamer,
1885 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1886 }
1887
1888 // beq .Lpass (branch if types match, i.e., scratch == temp)
1889 MCSymbol *Pass = OutContext.createTempSymbol();
1890 EmitToStreamer(S&: *OutStreamer,
1891 Inst: MCInstBuilder(ARM::tBcc)
1892 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1893 .addImm(Val: ARMCC::EQ)
1894 .addReg(Reg: ARM::CPSR));
1895
1896 // bkpt #0 (trap with encoded diagnostic)
1897 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBKPT).addImm(Val: 0));
1898
1899 OutStreamer->emitLabel(Symbol: Pass);
1900}
1901
1902void ARMAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
1903 Register AddrReg = MI.getOperand(i: 0).getReg();
1904 const int64_t Type = MI.getOperand(i: 1).getImm();
1905
1906 // Get the call instruction that follows this KCFI_CHECK.
1907 assert(std::next(MI.getIterator())->isCall() &&
1908 "KCFI_CHECK not followed by a call instruction");
1909 const MachineInstr &Call = *std::next(x: MI.getIterator());
1910
1911 // Adjust the offset for patchable-function-prefix.
1912 int64_t PrefixNops = 0;
1913 MI.getMF()
1914 ->getFunction()
1915 .getFnAttribute(Kind: "patchable-function-prefix")
1916 .getValueAsString()
1917 .getAsInteger(Radix: 10, Result&: PrefixNops);
1918
1919 // Emit the appropriate instruction sequence based on the opcode variant.
1920 switch (MI.getOpcode()) {
1921 case ARM::KCFI_CHECK_ARM:
1922 EmitKCFI_CHECK_ARM32(AddrReg, Type, Call, PrefixNops);
1923 break;
1924 case ARM::KCFI_CHECK_Thumb2:
1925 EmitKCFI_CHECK_Thumb2(AddrReg, Type, Call, PrefixNops);
1926 break;
1927 case ARM::KCFI_CHECK_Thumb1:
1928 EmitKCFI_CHECK_Thumb1(AddrReg, Type, Call, PrefixNops);
1929 break;
1930 default:
1931 llvm_unreachable("Unexpected KCFI_CHECK opcode");
1932 }
1933}
1934
1935void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
1936 ARM_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
1937 Features: getSubtargetInfo().getFeatureBits());
1938
1939 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1940 const DataLayout &DL = getDataLayout();
1941 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1942 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1943
1944 // If we just ended a constant pool, mark it as such.
1945 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1946 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1947 InConstantPool = false;
1948 }
1949
1950 // Emit unwinding stuff for frame-related instructions
1951 if (TM.getTargetTriple().isTargetEHABICompatible() &&
1952 MI->getFlag(Flag: MachineInstr::FrameSetup))
1953 EmitUnwindingInstruction(MI);
1954
1955 // Do any auto-generated pseudo lowerings.
1956 if (MCInst OutInst; lowerPseudoInstExpansion(MI, Inst&: OutInst)) {
1957 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
1958 return;
1959 }
1960
1961 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1962 "Pseudo flag setting opcode should be expanded early");
1963
1964 // Check for manual lowerings.
1965 unsigned Opc = MI->getOpcode();
1966 switch (Opc) {
1967 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1968 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1969 case ARM::KCFI_CHECK_ARM:
1970 case ARM::KCFI_CHECK_Thumb2:
1971 case ARM::KCFI_CHECK_Thumb1:
1972 LowerKCFI_CHECK(MI: *MI);
1973 return;
1974 case ARM::LEApcrel:
1975 case ARM::tLEApcrel:
1976 case ARM::t2LEApcrel: {
1977 // FIXME: Need to also handle globals and externals
1978 MCSymbol *CPISymbol = GetCPISymbol(CPID: MI->getOperand(i: 1).getIndex());
1979 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(MI->getOpcode() ==
1980 ARM::t2LEApcrel ? ARM::t2ADR
1981 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1982 : ARM::ADR))
1983 .addReg(Reg: MI->getOperand(i: 0).getReg())
1984 .addExpr(Val: MCSymbolRefExpr::create(Symbol: CPISymbol, Ctx&: OutContext))
1985 // Add predicate operands.
1986 .addImm(Val: MI->getOperand(i: 2).getImm())
1987 .addReg(Reg: MI->getOperand(i: 3).getReg()));
1988 return;
1989 }
1990 case ARM::LEApcrelJT:
1991 case ARM::tLEApcrelJT:
1992 case ARM::t2LEApcrelJT: {
1993 MCSymbol *JTIPICSymbol =
1994 GetARMJTIPICJumpTableLabel(uid: MI->getOperand(i: 1).getIndex());
1995 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(MI->getOpcode() ==
1996 ARM::t2LEApcrelJT ? ARM::t2ADR
1997 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1998 : ARM::ADR))
1999 .addReg(Reg: MI->getOperand(i: 0).getReg())
2000 .addExpr(Val: MCSymbolRefExpr::create(Symbol: JTIPICSymbol, Ctx&: OutContext))
2001 // Add predicate operands.
2002 .addImm(Val: MI->getOperand(i: 2).getImm())
2003 .addReg(Reg: MI->getOperand(i: 3).getReg()));
2004 return;
2005 }
2006 // Darwin call instructions are just normal call instructions with different
2007 // clobber semantics (they clobber R9).
2008 case ARM::BX_CALL: {
2009 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2010 .addReg(Reg: ARM::LR)
2011 .addReg(Reg: ARM::PC)
2012 // Add predicate operands.
2013 .addImm(Val: ARMCC::AL)
2014 .addReg(Reg: 0)
2015 // Add 's' bit operand (always reg0 for this)
2016 .addReg(Reg: 0));
2017
2018 assert(STI.hasV4TOps() && "Expected V4TOps for BX call");
2019 EmitToStreamer(S&: *OutStreamer,
2020 Inst: MCInstBuilder(ARM::BX).addReg(Reg: MI->getOperand(i: 0).getReg()));
2021 return;
2022 }
2023 case ARM::tBX_CALL: {
2024 assert(!STI.hasV5TOps() && "Expected BLX to be selected for v5t+");
2025
2026 // On ARM v4t, when doing a call from thumb mode, we need to ensure
2027 // that the saved lr has its LSB set correctly (the arch doesn't
2028 // have blx).
2029 // So here we generate a bl to a small jump pad that does bx rN.
2030 // The jump pads are emitted after the function body.
2031
2032 Register TReg = MI->getOperand(i: 0).getReg();
2033 MCSymbol *TRegSym = nullptr;
2034 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
2035 if (TIP.first == TReg) {
2036 TRegSym = TIP.second;
2037 break;
2038 }
2039 }
2040
2041 if (!TRegSym) {
2042 TRegSym = OutContext.createTempSymbol();
2043 ThumbIndirectPads.push_back(Elt: std::make_pair(x&: TReg, y&: TRegSym));
2044 }
2045
2046 // Create a link-saving branch to the Reg Indirect Jump Pad.
2047 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBL)
2048 // Predicate comes first here.
2049 .addImm(Val: ARMCC::AL).addReg(Reg: 0)
2050 .addExpr(Val: MCSymbolRefExpr::create(Symbol: TRegSym, Ctx&: OutContext)));
2051 return;
2052 }
2053 case ARM::BMOVPCRX_CALL: {
2054 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2055 .addReg(Reg: ARM::LR)
2056 .addReg(Reg: ARM::PC)
2057 // Add predicate operands.
2058 .addImm(Val: ARMCC::AL)
2059 .addReg(Reg: 0)
2060 // Add 's' bit operand (always reg0 for this)
2061 .addReg(Reg: 0));
2062
2063 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2064 .addReg(Reg: ARM::PC)
2065 .addReg(Reg: MI->getOperand(i: 0).getReg())
2066 // Add predicate operands.
2067 .addImm(Val: ARMCC::AL)
2068 .addReg(Reg: 0)
2069 // Add 's' bit operand (always reg0 for this)
2070 .addReg(Reg: 0));
2071 return;
2072 }
2073 case ARM::BMOVPCB_CALL: {
2074 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2075 .addReg(Reg: ARM::LR)
2076 .addReg(Reg: ARM::PC)
2077 // Add predicate operands.
2078 .addImm(Val: ARMCC::AL)
2079 .addReg(Reg: 0)
2080 // Add 's' bit operand (always reg0 for this)
2081 .addReg(Reg: 0));
2082
2083 const MachineOperand &Op = MI->getOperand(i: 0);
2084 const GlobalValue *GV = Op.getGlobal();
2085 const unsigned TF = Op.getTargetFlags();
2086 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2087 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2088 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::Bcc)
2089 .addExpr(Val: GVSymExpr)
2090 // Add predicate operands.
2091 .addImm(Val: ARMCC::AL)
2092 .addReg(Reg: 0));
2093 return;
2094 }
2095 case ARM::MOVi16_ga_pcrel:
2096 case ARM::t2MOVi16_ga_pcrel: {
2097 MCInst TmpInst;
2098 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
2099 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2100
2101 unsigned TF = MI->getOperand(i: 1).getTargetFlags();
2102 const GlobalValue *GV = MI->getOperand(i: 1).getGlobal();
2103 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2104 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2105
2106 MCSymbol *LabelSym =
2107 getPICLabel(Prefix: DL.getPrivateGlobalPrefix(), FunctionNumber: getFunctionNumber(),
2108 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext);
2109 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(Symbol: LabelSym, Ctx&: OutContext);
2110 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
2111 const MCExpr *PCRelExpr = ARM::createLower16(
2112 Expr: MCBinaryExpr::createSub(
2113 LHS: GVSymExpr,
2114 RHS: MCBinaryExpr::createAdd(LHS: LabelSymExpr,
2115 RHS: MCConstantExpr::create(Value: PCAdj, Ctx&: OutContext),
2116 Ctx&: OutContext),
2117 Ctx&: OutContext),
2118 Ctx&: OutContext);
2119 TmpInst.addOperand(Op: MCOperand::createExpr(Val: PCRelExpr));
2120
2121 // Add predicate operands.
2122 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2123 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2124 // Add 's' bit operand (always reg0 for this)
2125 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2126 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2127 return;
2128 }
2129 case ARM::MOVTi16_ga_pcrel:
2130 case ARM::t2MOVTi16_ga_pcrel: {
2131 MCInst TmpInst;
2132 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
2133 ? ARM::MOVTi16 : ARM::t2MOVTi16);
2134 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2135 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 1).getReg()));
2136
2137 unsigned TF = MI->getOperand(i: 2).getTargetFlags();
2138 const GlobalValue *GV = MI->getOperand(i: 2).getGlobal();
2139 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2140 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2141
2142 MCSymbol *LabelSym =
2143 getPICLabel(Prefix: DL.getPrivateGlobalPrefix(), FunctionNumber: getFunctionNumber(),
2144 LabelId: MI->getOperand(i: 3).getImm(), Ctx&: OutContext);
2145 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(Symbol: LabelSym, Ctx&: OutContext);
2146 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
2147 const MCExpr *PCRelExpr = ARM::createUpper16(
2148 Expr: MCBinaryExpr::createSub(
2149 LHS: GVSymExpr,
2150 RHS: MCBinaryExpr::createAdd(LHS: LabelSymExpr,
2151 RHS: MCConstantExpr::create(Value: PCAdj, Ctx&: OutContext),
2152 Ctx&: OutContext),
2153 Ctx&: OutContext),
2154 Ctx&: OutContext);
2155 TmpInst.addOperand(Op: MCOperand::createExpr(Val: PCRelExpr));
2156 // Add predicate operands.
2157 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2158 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2159 // Add 's' bit operand (always reg0 for this)
2160 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2161 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2162 return;
2163 }
2164 case ARM::t2BFi:
2165 case ARM::t2BFic:
2166 case ARM::t2BFLi:
2167 case ARM::t2BFr:
2168 case ARM::t2BFLr: {
2169 // This is a Branch Future instruction.
2170
2171 const MCExpr *BranchLabel = MCSymbolRefExpr::create(
2172 Symbol: getBFLabel(Prefix: DL.getPrivateGlobalPrefix(), FunctionNumber: getFunctionNumber(),
2173 LabelId: MI->getOperand(i: 0).getIndex(), Ctx&: OutContext),
2174 Ctx&: OutContext);
2175
2176 auto MCInst = MCInstBuilder(Opc).addExpr(Val: BranchLabel);
2177 if (MI->getOperand(i: 1).isReg()) {
2178 // For BFr/BFLr
2179 MCInst.addReg(Reg: MI->getOperand(i: 1).getReg());
2180 } else {
2181 // For BFi/BFLi/BFic
2182 const MCExpr *BranchTarget;
2183 if (MI->getOperand(i: 1).isMBB())
2184 BranchTarget = MCSymbolRefExpr::create(
2185 Symbol: MI->getOperand(i: 1).getMBB()->getSymbol(), Ctx&: OutContext);
2186 else if (MI->getOperand(i: 1).isGlobal()) {
2187 const GlobalValue *GV = MI->getOperand(i: 1).getGlobal();
2188 BranchTarget = MCSymbolRefExpr::create(
2189 Symbol: GetARMGVSymbol(GV, TargetFlags: MI->getOperand(i: 1).getTargetFlags()), Ctx&: OutContext);
2190 } else if (MI->getOperand(i: 1).isSymbol()) {
2191 BranchTarget = MCSymbolRefExpr::create(
2192 Symbol: GetExternalSymbolSymbol(Sym: MI->getOperand(i: 1).getSymbolName()),
2193 Ctx&: OutContext);
2194 } else
2195 llvm_unreachable("Unhandled operand kind in Branch Future instruction");
2196
2197 MCInst.addExpr(Val: BranchTarget);
2198 }
2199
2200 if (Opc == ARM::t2BFic) {
2201 const MCExpr *ElseLabel = MCSymbolRefExpr::create(
2202 Symbol: getBFLabel(Prefix: DL.getPrivateGlobalPrefix(), FunctionNumber: getFunctionNumber(),
2203 LabelId: MI->getOperand(i: 2).getIndex(), Ctx&: OutContext),
2204 Ctx&: OutContext);
2205 MCInst.addExpr(Val: ElseLabel);
2206 MCInst.addImm(Val: MI->getOperand(i: 3).getImm());
2207 } else {
2208 MCInst.addImm(Val: MI->getOperand(i: 2).getImm())
2209 .addReg(Reg: MI->getOperand(i: 3).getReg());
2210 }
2211
2212 EmitToStreamer(S&: *OutStreamer, Inst: MCInst);
2213 return;
2214 }
2215 case ARM::t2BF_LabelPseudo: {
2216 // This is a pseudo op for a label used by a branch future instruction
2217
2218 // Emit the label.
2219 OutStreamer->emitLabel(Symbol: getBFLabel(Prefix: DL.getPrivateGlobalPrefix(),
2220 FunctionNumber: getFunctionNumber(),
2221 LabelId: MI->getOperand(i: 0).getIndex(), Ctx&: OutContext));
2222 return;
2223 }
2224 case ARM::tPICADD: {
2225 // This is a pseudo op for a label + instruction sequence, which looks like:
2226 // LPC0:
2227 // add r0, pc
2228 // This adds the address of LPC0 to r0.
2229
2230 // Emit the label.
2231 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getPrivateGlobalPrefix(),
2232 FunctionNumber: getFunctionNumber(),
2233 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2234
2235 // Form and emit the add.
2236 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2237 .addReg(Reg: MI->getOperand(i: 0).getReg())
2238 .addReg(Reg: MI->getOperand(i: 0).getReg())
2239 .addReg(Reg: ARM::PC)
2240 // Add predicate operands.
2241 .addImm(Val: ARMCC::AL)
2242 .addReg(Reg: 0));
2243 return;
2244 }
2245 case ARM::PICADD: {
2246 // This is a pseudo op for a label + instruction sequence, which looks like:
2247 // LPC0:
2248 // add r0, pc, r0
2249 // This adds the address of LPC0 to r0.
2250
2251 // Emit the label.
2252 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getPrivateGlobalPrefix(),
2253 FunctionNumber: getFunctionNumber(),
2254 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2255
2256 // Form and emit the add.
2257 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDrr)
2258 .addReg(Reg: MI->getOperand(i: 0).getReg())
2259 .addReg(Reg: ARM::PC)
2260 .addReg(Reg: MI->getOperand(i: 1).getReg())
2261 // Add predicate operands.
2262 .addImm(Val: MI->getOperand(i: 3).getImm())
2263 .addReg(Reg: MI->getOperand(i: 4).getReg())
2264 // Add 's' bit operand (always reg0 for this)
2265 .addReg(Reg: 0));
2266 return;
2267 }
2268 case ARM::PICSTR:
2269 case ARM::PICSTRB:
2270 case ARM::PICSTRH:
2271 case ARM::PICLDR:
2272 case ARM::PICLDRB:
2273 case ARM::PICLDRH:
2274 case ARM::PICLDRSB:
2275 case ARM::PICLDRSH: {
2276 // This is a pseudo op for a label + instruction sequence, which looks like:
2277 // LPC0:
2278 // OP r0, [pc, r0]
2279 // The LCP0 label is referenced by a constant pool entry in order to get
2280 // a PC-relative address at the ldr instruction.
2281
2282 // Emit the label.
2283 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getPrivateGlobalPrefix(),
2284 FunctionNumber: getFunctionNumber(),
2285 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2286
2287 // Form and emit the load
2288 unsigned Opcode;
2289 switch (MI->getOpcode()) {
2290 default:
2291 llvm_unreachable("Unexpected opcode!");
2292 case ARM::PICSTR: Opcode = ARM::STRrs; break;
2293 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
2294 case ARM::PICSTRH: Opcode = ARM::STRH; break;
2295 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
2296 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
2297 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
2298 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
2299 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
2300 }
2301 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opcode)
2302 .addReg(Reg: MI->getOperand(i: 0).getReg())
2303 .addReg(Reg: ARM::PC)
2304 .addReg(Reg: MI->getOperand(i: 1).getReg())
2305 .addImm(Val: 0)
2306 // Add predicate operands.
2307 .addImm(Val: MI->getOperand(i: 3).getImm())
2308 .addReg(Reg: MI->getOperand(i: 4).getReg()));
2309
2310 return;
2311 }
2312 case ARM::CONSTPOOL_ENTRY: {
2313 assert(!STI.genExecuteOnly() &&
2314 "execute-only should not generate constant pools");
2315
2316 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
2317 /// in the function. The first operand is the ID# for this instruction, the
2318 /// second is the index into the MachineConstantPool that this is, the third
2319 /// is the size in bytes of this constant pool entry.
2320 /// The required alignment is specified on the basic block holding this MI.
2321 unsigned LabelId = (unsigned)MI->getOperand(i: 0).getImm();
2322 unsigned CPIdx = (unsigned)MI->getOperand(i: 1).getIndex();
2323
2324 // If this is the first entry of the pool, mark it.
2325 if (!InConstantPool) {
2326 OutStreamer->emitDataRegion(Kind: MCDR_DataRegion);
2327 InConstantPool = true;
2328 }
2329
2330 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: LabelId));
2331
2332 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
2333 if (MCPE.isMachineConstantPoolEntry())
2334 emitMachineConstantPoolValue(MCPV: MCPE.Val.MachineCPVal);
2335 else
2336 emitGlobalConstant(DL, CV: MCPE.Val.ConstVal);
2337 return;
2338 }
2339 case ARM::JUMPTABLE_ADDRS:
2340 emitJumpTableAddrs(MI);
2341 return;
2342 case ARM::JUMPTABLE_INSTS:
2343 emitJumpTableInsts(MI);
2344 return;
2345 case ARM::JUMPTABLE_TBB:
2346 case ARM::JUMPTABLE_TBH:
2347 emitJumpTableTBInst(MI, OffsetWidth: MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
2348 return;
2349 case ARM::t2BR_JT: {
2350 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2351 .addReg(Reg: ARM::PC)
2352 .addReg(Reg: MI->getOperand(i: 0).getReg())
2353 // Add predicate operands.
2354 .addImm(Val: ARMCC::AL)
2355 .addReg(Reg: 0));
2356 return;
2357 }
2358 case ARM::t2TBB_JT:
2359 case ARM::t2TBH_JT: {
2360 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
2361 // Lower and emit the PC label, then the instruction itself.
2362 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: MI->getOperand(i: 3).getImm()));
2363 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2364 .addReg(Reg: MI->getOperand(i: 0).getReg())
2365 .addReg(Reg: MI->getOperand(i: 1).getReg())
2366 // Add predicate operands.
2367 .addImm(Val: ARMCC::AL)
2368 .addReg(Reg: 0));
2369 return;
2370 }
2371 case ARM::tTBB_JT:
2372 case ARM::tTBH_JT: {
2373
2374 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
2375 Register Base = MI->getOperand(i: 0).getReg();
2376 Register Idx = MI->getOperand(i: 1).getReg();
2377 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
2378
2379 // Multiply up idx if necessary.
2380 if (!Is8Bit)
2381 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
2382 .addReg(Reg: Idx)
2383 .addReg(Reg: ARM::CPSR)
2384 .addReg(Reg: Idx)
2385 .addImm(Val: 1)
2386 // Add predicate operands.
2387 .addImm(Val: ARMCC::AL)
2388 .addReg(Reg: 0));
2389
2390 if (Base == ARM::PC) {
2391 // TBB [base, idx] =
2392 // ADDS idx, idx, base
2393 // LDRB idx, [idx, #4] ; or LDRH if TBH
2394 // LSLS idx, #1
2395 // ADDS pc, pc, idx
2396
2397 // When using PC as the base, it's important that there is no padding
2398 // between the last ADDS and the start of the jump table. The jump table
2399 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
2400 //
2401 // FIXME: Ideally we could vary the LDRB index based on the padding
2402 // between the sequence and jump table, however that relies on MCExprs
2403 // for load indexes which are currently not supported.
2404 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: &getSubtargetInfo());
2405 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2406 .addReg(Reg: Idx)
2407 .addReg(Reg: Idx)
2408 .addReg(Reg: Base)
2409 // Add predicate operands.
2410 .addImm(Val: ARMCC::AL)
2411 .addReg(Reg: 0));
2412
2413 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
2414 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2415 .addReg(Reg: Idx)
2416 .addReg(Reg: Idx)
2417 .addImm(Val: Is8Bit ? 4 : 2)
2418 // Add predicate operands.
2419 .addImm(Val: ARMCC::AL)
2420 .addReg(Reg: 0));
2421 } else {
2422 // TBB [base, idx] =
2423 // LDRB idx, [base, idx] ; or LDRH if TBH
2424 // LSLS idx, #1
2425 // ADDS pc, pc, idx
2426
2427 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
2428 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2429 .addReg(Reg: Idx)
2430 .addReg(Reg: Base)
2431 .addReg(Reg: Idx)
2432 // Add predicate operands.
2433 .addImm(Val: ARMCC::AL)
2434 .addReg(Reg: 0));
2435 }
2436
2437 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
2438 .addReg(Reg: Idx)
2439 .addReg(Reg: ARM::CPSR)
2440 .addReg(Reg: Idx)
2441 .addImm(Val: 1)
2442 // Add predicate operands.
2443 .addImm(Val: ARMCC::AL)
2444 .addReg(Reg: 0));
2445
2446 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: MI->getOperand(i: 3).getImm()));
2447 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2448 .addReg(Reg: ARM::PC)
2449 .addReg(Reg: ARM::PC)
2450 .addReg(Reg: Idx)
2451 // Add predicate operands.
2452 .addImm(Val: ARMCC::AL)
2453 .addReg(Reg: 0));
2454 return;
2455 }
2456 case ARM::tBR_JTr:
2457 case ARM::BR_JTr: {
2458 // mov pc, target
2459 MCInst TmpInst;
2460 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
2461 ARM::MOVr : ARM::tMOVr;
2462 TmpInst.setOpcode(Opc);
2463 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2464 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2465 // Add predicate operands.
2466 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2467 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2468 // Add 's' bit operand (always reg0 for this)
2469 if (Opc == ARM::MOVr)
2470 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2471 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2472 return;
2473 }
2474 case ARM::BR_JTm_i12: {
2475 // ldr pc, target
2476 MCInst TmpInst;
2477 TmpInst.setOpcode(ARM::LDRi12);
2478 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2479 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2480 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI->getOperand(i: 2).getImm()));
2481 // Add predicate operands.
2482 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2483 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2484 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2485 return;
2486 }
2487 case ARM::BR_JTm_rs: {
2488 // ldr pc, target
2489 MCInst TmpInst;
2490 TmpInst.setOpcode(ARM::LDRrs);
2491 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2492 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2493 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 1).getReg()));
2494 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI->getOperand(i: 2).getImm()));
2495 // Add predicate operands.
2496 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2497 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2498 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2499 return;
2500 }
2501 case ARM::BR_JTadd: {
2502 // add pc, target, idx
2503 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDrr)
2504 .addReg(Reg: ARM::PC)
2505 .addReg(Reg: MI->getOperand(i: 0).getReg())
2506 .addReg(Reg: MI->getOperand(i: 1).getReg())
2507 // Add predicate operands.
2508 .addImm(Val: ARMCC::AL)
2509 .addReg(Reg: 0)
2510 // Add 's' bit operand (always reg0 for this)
2511 .addReg(Reg: 0));
2512 return;
2513 }
2514 case ARM::SPACE:
2515 OutStreamer->emitZeros(NumBytes: MI->getOperand(i: 1).getImm());
2516 return;
2517 case ARM::TRAP: {
2518 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2519 // FIXME: Remove this special case when they do.
2520 if (!TM.getTargetTriple().isOSBinFormatMachO()) {
2521 uint32_t Val = 0xe7ffdefeUL;
2522 OutStreamer->AddComment(T: "trap");
2523 ATS.emitInst(Inst: Val);
2524 return;
2525 }
2526 break;
2527 }
2528 case ARM::tTRAP: {
2529 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2530 // FIXME: Remove this special case when they do.
2531 if (!TM.getTargetTriple().isOSBinFormatMachO()) {
2532 uint16_t Val = 0xdefe;
2533 OutStreamer->AddComment(T: "trap");
2534 ATS.emitInst(Inst: Val, Suffix: 'n');
2535 return;
2536 }
2537 break;
2538 }
2539 case ARM::t2Int_eh_sjlj_setjmp:
2540 case ARM::t2Int_eh_sjlj_setjmp_nofp:
2541 case ARM::tInt_eh_sjlj_setjmp: {
2542 // Two incoming args: GPR:$src, GPR:$val
2543 // mov $val, pc
2544 // adds $val, #7
2545 // str $val, [$src, #4]
2546 // movs r0, #0
2547 // b LSJLJEH
2548 // movs r0, #1
2549 // LSJLJEH:
2550 Register SrcReg = MI->getOperand(i: 0).getReg();
2551 Register ValReg = MI->getOperand(i: 1).getReg();
2552 MCSymbol *Label = OutContext.createTempSymbol(Name: "SJLJEH");
2553 OutStreamer->AddComment(T: "eh_setjmp begin");
2554 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2555 .addReg(Reg: ValReg)
2556 .addReg(Reg: ARM::PC)
2557 // Predicate.
2558 .addImm(Val: ARMCC::AL)
2559 .addReg(Reg: 0));
2560
2561 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi3)
2562 .addReg(Reg: ValReg)
2563 // 's' bit operand
2564 .addReg(Reg: ARM::CPSR)
2565 .addReg(Reg: ValReg)
2566 .addImm(Val: 7)
2567 // Predicate.
2568 .addImm(Val: ARMCC::AL)
2569 .addReg(Reg: 0));
2570
2571 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tSTRi)
2572 .addReg(Reg: ValReg)
2573 .addReg(Reg: SrcReg)
2574 // The offset immediate is #4. The operand value is scaled by 4 for the
2575 // tSTR instruction.
2576 .addImm(Val: 1)
2577 // Predicate.
2578 .addImm(Val: ARMCC::AL)
2579 .addReg(Reg: 0));
2580
2581 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
2582 .addReg(Reg: ARM::R0)
2583 .addReg(Reg: ARM::CPSR)
2584 .addImm(Val: 0)
2585 // Predicate.
2586 .addImm(Val: ARMCC::AL)
2587 .addReg(Reg: 0));
2588
2589 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Symbol: Label, Ctx&: OutContext);
2590 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tB)
2591 .addExpr(Val: SymbolExpr)
2592 .addImm(Val: ARMCC::AL)
2593 .addReg(Reg: 0));
2594
2595 OutStreamer->AddComment(T: "eh_setjmp end");
2596 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
2597 .addReg(Reg: ARM::R0)
2598 .addReg(Reg: ARM::CPSR)
2599 .addImm(Val: 1)
2600 // Predicate.
2601 .addImm(Val: ARMCC::AL)
2602 .addReg(Reg: 0));
2603
2604 OutStreamer->emitLabel(Symbol: Label);
2605 return;
2606 }
2607
2608 case ARM::Int_eh_sjlj_setjmp_nofp:
2609 case ARM::Int_eh_sjlj_setjmp: {
2610 // Two incoming args: GPR:$src, GPR:$val
2611 // add $val, pc, #8
2612 // str $val, [$src, #+4]
2613 // mov r0, #0
2614 // add pc, pc, #0
2615 // mov r0, #1
2616 Register SrcReg = MI->getOperand(i: 0).getReg();
2617 Register ValReg = MI->getOperand(i: 1).getReg();
2618
2619 OutStreamer->AddComment(T: "eh_setjmp begin");
2620 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDri)
2621 .addReg(Reg: ValReg)
2622 .addReg(Reg: ARM::PC)
2623 .addImm(Val: 8)
2624 // Predicate.
2625 .addImm(Val: ARMCC::AL)
2626 .addReg(Reg: 0)
2627 // 's' bit operand (always reg0 for this).
2628 .addReg(Reg: 0));
2629
2630 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::STRi12)
2631 .addReg(Reg: ValReg)
2632 .addReg(Reg: SrcReg)
2633 .addImm(Val: 4)
2634 // Predicate.
2635 .addImm(Val: ARMCC::AL)
2636 .addReg(Reg: 0));
2637
2638 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVi)
2639 .addReg(Reg: ARM::R0)
2640 .addImm(Val: 0)
2641 // Predicate.
2642 .addImm(Val: ARMCC::AL)
2643 .addReg(Reg: 0)
2644 // 's' bit operand (always reg0 for this).
2645 .addReg(Reg: 0));
2646
2647 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDri)
2648 .addReg(Reg: ARM::PC)
2649 .addReg(Reg: ARM::PC)
2650 .addImm(Val: 0)
2651 // Predicate.
2652 .addImm(Val: ARMCC::AL)
2653 .addReg(Reg: 0)
2654 // 's' bit operand (always reg0 for this).
2655 .addReg(Reg: 0));
2656
2657 OutStreamer->AddComment(T: "eh_setjmp end");
2658 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVi)
2659 .addReg(Reg: ARM::R0)
2660 .addImm(Val: 1)
2661 // Predicate.
2662 .addImm(Val: ARMCC::AL)
2663 .addReg(Reg: 0)
2664 // 's' bit operand (always reg0 for this).
2665 .addReg(Reg: 0));
2666 return;
2667 }
2668 case ARM::Int_eh_sjlj_longjmp: {
2669 // ldr sp, [$src, #8]
2670 // ldr $scratch, [$src, #4]
2671 // ldr r7, [$src]
2672 // bx $scratch
2673 Register SrcReg = MI->getOperand(i: 0).getReg();
2674 Register ScratchReg = MI->getOperand(i: 1).getReg();
2675 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2676 .addReg(Reg: ARM::SP)
2677 .addReg(Reg: SrcReg)
2678 .addImm(Val: 8)
2679 // Predicate.
2680 .addImm(Val: ARMCC::AL)
2681 .addReg(Reg: 0));
2682
2683 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2684 .addReg(Reg: ScratchReg)
2685 .addReg(Reg: SrcReg)
2686 .addImm(Val: 4)
2687 // Predicate.
2688 .addImm(Val: ARMCC::AL)
2689 .addReg(Reg: 0));
2690
2691 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2692 // These platforms always use the same frame register
2693 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2694 .addReg(Reg: STI.getFramePointerReg())
2695 .addReg(Reg: SrcReg)
2696 .addImm(Val: 0)
2697 // Predicate.
2698 .addImm(Val: ARMCC::AL)
2699 .addReg(Reg: 0));
2700 } else {
2701 // If the calling code might use either R7 or R11 as
2702 // frame pointer register, restore it into both.
2703 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2704 .addReg(Reg: ARM::R7)
2705 .addReg(Reg: SrcReg)
2706 .addImm(Val: 0)
2707 // Predicate.
2708 .addImm(Val: ARMCC::AL)
2709 .addReg(Reg: 0));
2710 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2711 .addReg(Reg: ARM::R11)
2712 .addReg(Reg: SrcReg)
2713 .addImm(Val: 0)
2714 // Predicate.
2715 .addImm(Val: ARMCC::AL)
2716 .addReg(Reg: 0));
2717 }
2718
2719 assert(STI.hasV4TOps());
2720 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::BX)
2721 .addReg(Reg: ScratchReg)
2722 // Predicate.
2723 .addImm(Val: ARMCC::AL)
2724 .addReg(Reg: 0));
2725 return;
2726 }
2727 case ARM::tInt_eh_sjlj_longjmp: {
2728 // ldr $scratch, [$src, #8]
2729 // mov sp, $scratch
2730 // ldr $scratch, [$src, #4]
2731 // ldr r7, [$src]
2732 // bx $scratch
2733 Register SrcReg = MI->getOperand(i: 0).getReg();
2734 Register ScratchReg = MI->getOperand(i: 1).getReg();
2735
2736 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2737 .addReg(Reg: ScratchReg)
2738 .addReg(Reg: SrcReg)
2739 // The offset immediate is #8. The operand value is scaled by 4 for the
2740 // tLDR instruction.
2741 .addImm(Val: 2)
2742 // Predicate.
2743 .addImm(Val: ARMCC::AL)
2744 .addReg(Reg: 0));
2745
2746 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2747 .addReg(Reg: ARM::SP)
2748 .addReg(Reg: ScratchReg)
2749 // Predicate.
2750 .addImm(Val: ARMCC::AL)
2751 .addReg(Reg: 0));
2752
2753 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2754 .addReg(Reg: ScratchReg)
2755 .addReg(Reg: SrcReg)
2756 .addImm(Val: 1)
2757 // Predicate.
2758 .addImm(Val: ARMCC::AL)
2759 .addReg(Reg: 0));
2760
2761 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2762 // These platforms always use the same frame register
2763 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2764 .addReg(Reg: STI.getFramePointerReg())
2765 .addReg(Reg: SrcReg)
2766 .addImm(Val: 0)
2767 // Predicate.
2768 .addImm(Val: ARMCC::AL)
2769 .addReg(Reg: 0));
2770 } else {
2771 // If the calling code might use either R7 or R11 as
2772 // frame pointer register, restore it into both.
2773 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2774 .addReg(Reg: ARM::R7)
2775 .addReg(Reg: SrcReg)
2776 .addImm(Val: 0)
2777 // Predicate.
2778 .addImm(Val: ARMCC::AL)
2779 .addReg(Reg: 0));
2780 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2781 .addReg(Reg: ARM::R11)
2782 .addReg(Reg: SrcReg)
2783 .addImm(Val: 0)
2784 // Predicate.
2785 .addImm(Val: ARMCC::AL)
2786 .addReg(Reg: 0));
2787 }
2788
2789 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBX)
2790 .addReg(Reg: ScratchReg)
2791 // Predicate.
2792 .addImm(Val: ARMCC::AL)
2793 .addReg(Reg: 0));
2794 return;
2795 }
2796 case ARM::tInt_WIN_eh_sjlj_longjmp: {
2797 // ldr.w r11, [$src, #0]
2798 // ldr.w sp, [$src, #8]
2799 // ldr.w pc, [$src, #4]
2800
2801 Register SrcReg = MI->getOperand(i: 0).getReg();
2802
2803 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2804 .addReg(Reg: ARM::R11)
2805 .addReg(Reg: SrcReg)
2806 .addImm(Val: 0)
2807 // Predicate
2808 .addImm(Val: ARMCC::AL)
2809 .addReg(Reg: 0));
2810 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2811 .addReg(Reg: ARM::SP)
2812 .addReg(Reg: SrcReg)
2813 .addImm(Val: 8)
2814 // Predicate
2815 .addImm(Val: ARMCC::AL)
2816 .addReg(Reg: 0));
2817 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2818 .addReg(Reg: ARM::PC)
2819 .addReg(Reg: SrcReg)
2820 .addImm(Val: 4)
2821 // Predicate
2822 .addImm(Val: ARMCC::AL)
2823 .addReg(Reg: 0));
2824 return;
2825 }
2826 case ARM::PATCHABLE_FUNCTION_ENTER:
2827 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI);
2828 return;
2829 case ARM::PATCHABLE_FUNCTION_EXIT:
2830 LowerPATCHABLE_FUNCTION_EXIT(MI: *MI);
2831 return;
2832 case ARM::PATCHABLE_TAIL_CALL:
2833 LowerPATCHABLE_TAIL_CALL(MI: *MI);
2834 return;
2835 case ARM::SpeculationBarrierISBDSBEndBB: {
2836 // Print DSB SYS + ISB
2837 MCInst TmpInstDSB;
2838 TmpInstDSB.setOpcode(ARM::DSB);
2839 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2840 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstDSB);
2841 MCInst TmpInstISB;
2842 TmpInstISB.setOpcode(ARM::ISB);
2843 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2844 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstISB);
2845 return;
2846 }
2847 case ARM::t2SpeculationBarrierISBDSBEndBB: {
2848 // Print DSB SYS + ISB
2849 MCInst TmpInstDSB;
2850 TmpInstDSB.setOpcode(ARM::t2DSB);
2851 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2852 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2853 TmpInstDSB.addOperand(Op: MCOperand::createReg(Reg: 0));
2854 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstDSB);
2855 MCInst TmpInstISB;
2856 TmpInstISB.setOpcode(ARM::t2ISB);
2857 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2858 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2859 TmpInstISB.addOperand(Op: MCOperand::createReg(Reg: 0));
2860 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstISB);
2861 return;
2862 }
2863 case ARM::SpeculationBarrierSBEndBB: {
2864 // Print SB
2865 MCInst TmpInstSB;
2866 TmpInstSB.setOpcode(ARM::SB);
2867 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstSB);
2868 return;
2869 }
2870 case ARM::t2SpeculationBarrierSBEndBB: {
2871 // Print SB
2872 MCInst TmpInstSB;
2873 TmpInstSB.setOpcode(ARM::t2SB);
2874 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstSB);
2875 return;
2876 }
2877
2878 case ARM::SEH_StackAlloc:
2879 ATS.emitARMWinCFIAllocStack(Size: MI->getOperand(i: 0).getImm(),
2880 Wide: MI->getOperand(i: 1).getImm());
2881 return;
2882
2883 case ARM::SEH_SaveRegs:
2884 case ARM::SEH_SaveRegs_Ret:
2885 ATS.emitARMWinCFISaveRegMask(Mask: MI->getOperand(i: 0).getImm(),
2886 Wide: MI->getOperand(i: 1).getImm());
2887 return;
2888
2889 case ARM::SEH_SaveSP:
2890 ATS.emitARMWinCFISaveSP(Reg: MI->getOperand(i: 0).getImm());
2891 return;
2892
2893 case ARM::SEH_SaveFRegs:
2894 ATS.emitARMWinCFISaveFRegs(First: MI->getOperand(i: 0).getImm(),
2895 Last: MI->getOperand(i: 1).getImm());
2896 return;
2897
2898 case ARM::SEH_SaveLR:
2899 ATS.emitARMWinCFISaveLR(Offset: MI->getOperand(i: 0).getImm());
2900 return;
2901
2902 case ARM::SEH_Nop:
2903 case ARM::SEH_Nop_Ret:
2904 ATS.emitARMWinCFINop(Wide: MI->getOperand(i: 0).getImm());
2905 return;
2906
2907 case ARM::SEH_PrologEnd:
2908 ATS.emitARMWinCFIPrologEnd(/*Fragment=*/false);
2909 return;
2910
2911 case ARM::SEH_EpilogStart:
2912 ATS.emitARMWinCFIEpilogStart(Condition: ARMCC::AL);
2913 return;
2914
2915 case ARM::SEH_EpilogEnd:
2916 ATS.emitARMWinCFIEpilogEnd();
2917 return;
2918 }
2919
2920 MCInst TmpInst;
2921 LowerARMMachineInstrToMCInst(MI, OutMI&: TmpInst, AP&: *this);
2922
2923 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2924}
2925
2926char ARMAsmPrinter::ID = 0;
2927
2928INITIALIZE_PASS(ARMAsmPrinter, "arm-asm-printer", "ARM Assembly Printer", false,
2929 false)
2930
2931//===----------------------------------------------------------------------===//
2932// Target Registry Stuff
2933//===----------------------------------------------------------------------===//
2934
2935// Force static initialization.
2936extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
2937LLVMInitializeARMAsmPrinter() {
2938 RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
2939 RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
2940 RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
2941 RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
2942}
2943