1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format ARM assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMAsmPrinter.h"
15#include "ARM.h"
16#include "ARMConstantPoolValue.h"
17#include "ARMMachineFunctionInfo.h"
18#include "ARMTargetMachine.h"
19#include "ARMTargetObjectFile.h"
20#include "MCTargetDesc/ARMInstPrinter.h"
21#include "MCTargetDesc/ARMMCAsmInfo.h"
22#include "TargetInfo/ARMTargetInfo.h"
23#include "llvm/ADT/SmallString.h"
24#include "llvm/BinaryFormat/COFF.h"
25#include "llvm/CodeGen/MachineJumpTableInfo.h"
26#include "llvm/CodeGen/MachineModuleInfoImpls.h"
27#include "llvm/IR/Constants.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/IR/Mangler.h"
30#include "llvm/IR/Module.h"
31#include "llvm/IR/Type.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/MC/MCAssembler.h"
34#include "llvm/MC/MCContext.h"
35#include "llvm/MC/MCELFStreamer.h"
36#include "llvm/MC/MCInst.h"
37#include "llvm/MC/MCInstBuilder.h"
38#include "llvm/MC/MCObjectStreamer.h"
39#include "llvm/MC/MCStreamer.h"
40#include "llvm/MC/MCSymbol.h"
41#include "llvm/MC/TargetRegistry.h"
42#include "llvm/Support/ARMBuildAttributes.h"
43#include "llvm/Support/Compiler.h"
44#include "llvm/Support/Debug.h"
45#include "llvm/Support/ErrorHandling.h"
46#include "llvm/Support/raw_ostream.h"
47#include "llvm/Target/TargetMachine.h"
48using namespace llvm;
49
50#define DEBUG_TYPE "asm-printer"
51
52ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
53 std::unique_ptr<MCStreamer> Streamer)
54 : AsmPrinter(TM, std::move(Streamer), ID), AFI(nullptr), MCP(nullptr),
55 InConstantPool(false), OptimizationGoals(-1) {}
56
57const ARMBaseTargetMachine &ARMAsmPrinter::getTM() const {
58 return static_cast<const ARMBaseTargetMachine &>(TM);
59}
60
61void ARMAsmPrinter::emitFunctionBodyEnd() {
62 // Make sure to terminate any constant pools that were at the end
63 // of the function.
64 if (!InConstantPool)
65 return;
66 InConstantPool = false;
67 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
68}
69
70void ARMAsmPrinter::emitFunctionEntryLabel() {
71 auto &TS =
72 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
73 if (AFI->isThumbFunction()) {
74 TS.emitCode16();
75 TS.emitThumbFunc(Symbol: CurrentFnSym);
76 } else {
77 TS.emitCode32();
78 }
79
80 // Emit symbol for CMSE non-secure entry point
81 if (AFI->isCmseNSEntryFunction()) {
82 MCSymbol *S =
83 OutContext.getOrCreateSymbol(Name: "__acle_se_" + CurrentFnSym->getName());
84 emitLinkage(GV: &MF->getFunction(), GVSym: S);
85 OutStreamer->emitSymbolAttribute(Symbol: S, Attribute: MCSA_ELF_TypeFunction);
86 OutStreamer->emitLabel(Symbol: S);
87 }
88 AsmPrinter::emitFunctionEntryLabel();
89}
90
91void ARMAsmPrinter::emitXXStructor(const DataLayout &DL, const Constant *CV) {
92 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: CV->getType());
93 assert(Size && "C++ constructor pointer had zero size!");
94
95 const GlobalValue *GV = dyn_cast<GlobalValue>(Val: CV->stripPointerCasts());
96 assert(GV && "C++ constructor pointer was not a GlobalValue!");
97
98 const MCExpr *E = MCSymbolRefExpr::create(
99 Symbol: GetARMGVSymbol(GV, TargetFlags: ARMII::MO_NO_FLAG),
100 specifier: (TM.getTargetTriple().isOSBinFormatELF() ? ARM::S_TARGET1 : ARM::S_None),
101 Ctx&: OutContext);
102
103 OutStreamer->emitValue(Value: E, Size);
104}
105
106// An alias to a cmse entry function should also emit a `__acle_se_` symbol.
107void ARMAsmPrinter::emitCMSEVeneerAlias(const GlobalAlias &GA) {
108 const Function *BaseFn = dyn_cast_or_null<Function>(Val: GA.getAliaseeObject());
109 if (!BaseFn || !BaseFn->hasFnAttribute(Kind: "cmse_nonsecure_entry"))
110 return;
111
112 MCSymbol *AliasSym = getSymbol(GV: &GA);
113 MCSymbol *FnSym = getSymbol(GV: BaseFn);
114
115 MCSymbol *SEAliasSym =
116 OutContext.getOrCreateSymbol(Name: Twine("__acle_se_") + AliasSym->getName());
117 MCSymbol *SEBaseSym =
118 OutContext.getOrCreateSymbol(Name: Twine("__acle_se_") + FnSym->getName());
119
120 // Mirror alias linkage/visibility onto the veneer-alias symbol.
121 emitLinkage(GV: &GA, GVSym: SEAliasSym);
122 OutStreamer->emitSymbolAttribute(Symbol: SEAliasSym, Attribute: MCSA_ELF_TypeFunction);
123 emitVisibility(Sym: SEAliasSym, Visibility: GA.getVisibility());
124
125 // emit "__acle_se_<alias> = __acle_se_<aliasee>"
126 const MCExpr *SEExpr = MCSymbolRefExpr::create(Symbol: SEBaseSym, Ctx&: OutContext);
127 OutStreamer->emitAssignment(Symbol: SEAliasSym, Value: SEExpr);
128}
129
130void ARMAsmPrinter::emitGlobalAlias(const Module &M, const GlobalAlias &GA) {
131 AsmPrinter::emitGlobalAlias(M, GA);
132 emitCMSEVeneerAlias(GA);
133}
134
135void ARMAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
136 if (PromotedGlobals.count(Ptr: GV))
137 // The global was promoted into a constant pool. It should not be emitted.
138 return;
139 AsmPrinter::emitGlobalVariable(GV);
140}
141
142/// runOnMachineFunction - This uses the emitInstruction()
143/// method to print assembly for each instruction.
144///
145bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
146 AFI = MF.getInfo<ARMFunctionInfo>();
147 MCP = MF.getConstantPool();
148
149 SetupMachineFunction(MF);
150 const Function &F = MF.getFunction();
151 const TargetMachine& TM = MF.getTarget();
152
153 // Collect all globals that had their storage promoted to a constant pool.
154 // Functions are emitted before variables, so this accumulates promoted
155 // globals from all functions in PromotedGlobals.
156 PromotedGlobals.insert_range(R&: AFI->getGlobalsPromotedToConstantPool());
157
158 // Calculate this function's optimization goal.
159 unsigned OptimizationGoal;
160 if (F.hasOptNone())
161 // For best debugging illusion, speed and small size sacrificed
162 OptimizationGoal = 6;
163 else if (F.hasMinSize())
164 // Aggressively for small size, speed and debug illusion sacrificed
165 OptimizationGoal = 4;
166 else if (F.hasOptSize())
167 // For small size, but speed and debugging illusion preserved
168 OptimizationGoal = 3;
169 else if (TM.getOptLevel() == CodeGenOptLevel::Aggressive)
170 // Aggressively for speed, small size and debug illusion sacrificed
171 OptimizationGoal = 2;
172 else if (TM.getOptLevel() > CodeGenOptLevel::None)
173 // For speed, but small size and good debug illusion preserved
174 OptimizationGoal = 1;
175 else // TM.getOptLevel() == CodeGenOptLevel::None
176 // For good debugging, but speed and small size preserved
177 OptimizationGoal = 5;
178
179 // Combine a new optimization goal with existing ones.
180 if (OptimizationGoals == -1) // uninitialized goals
181 OptimizationGoals = OptimizationGoal;
182 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
183 OptimizationGoals = 0;
184
185 if (TM.getTargetTriple().isOSBinFormatCOFF()) {
186 bool Local = F.hasLocalLinkage();
187 COFF::SymbolStorageClass Scl =
188 Local ? COFF::IMAGE_SYM_CLASS_STATIC : COFF::IMAGE_SYM_CLASS_EXTERNAL;
189 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
190
191 OutStreamer->beginCOFFSymbolDef(Symbol: CurrentFnSym);
192 OutStreamer->emitCOFFSymbolStorageClass(StorageClass: Scl);
193 OutStreamer->emitCOFFSymbolType(Type);
194 OutStreamer->endCOFFSymbolDef();
195 }
196
197 // Emit the rest of the function body.
198 emitFunctionBody();
199
200 // Emit the XRay table for this function.
201 emitXRayTable();
202
203 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
204 // These are created per function, rather than per TU, since it's
205 // relatively easy to exceed the thumb branch range within a TU.
206 if (! ThumbIndirectPads.empty()) {
207 auto &TS =
208 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
209 TS.emitCode16();
210 emitAlignment(Alignment: Align(2));
211 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
212 OutStreamer->emitLabel(Symbol: TIP.second);
213 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBX)
214 .addReg(Reg: TIP.first)
215 // Add predicate operands.
216 .addImm(Val: ARMCC::AL)
217 .addReg(Reg: 0));
218 }
219 ThumbIndirectPads.clear();
220 }
221
222 // We didn't modify anything.
223 return false;
224}
225
226void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
227 raw_ostream &O) {
228 assert(MO.isGlobal() && "caller should check MO.isGlobal");
229 unsigned TF = MO.getTargetFlags();
230 if (TF & ARMII::MO_LO16)
231 O << ":lower16:";
232 else if (TF & ARMII::MO_HI16)
233 O << ":upper16:";
234 else if (TF & ARMII::MO_LO_0_7)
235 O << ":lower0_7:";
236 else if (TF & ARMII::MO_LO_8_15)
237 O << ":lower8_15:";
238 else if (TF & ARMII::MO_HI_0_7)
239 O << ":upper0_7:";
240 else if (TF & ARMII::MO_HI_8_15)
241 O << ":upper8_15:";
242
243 GetARMGVSymbol(GV: MO.getGlobal(), TargetFlags: TF)->print(OS&: O, MAI);
244 printOffset(Offset: MO.getOffset(), OS&: O);
245}
246
247void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
248 raw_ostream &O) {
249 const MachineOperand &MO = MI->getOperand(i: OpNum);
250
251 switch (MO.getType()) {
252 default: llvm_unreachable("<unknown operand type>");
253 case MachineOperand::MO_Register: {
254 Register Reg = MO.getReg();
255 assert(Reg.isPhysical());
256 assert(!MO.getSubReg() && "Subregs should be eliminated!");
257 if(ARM::GPRPairRegClass.contains(Reg)) {
258 const MachineFunction &MF = *MI->getParent()->getParent();
259 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
260 Reg = TRI->getSubReg(Reg, Idx: ARM::gsub_0);
261 }
262 O << ARMInstPrinter::getRegisterName(Reg);
263 break;
264 }
265 case MachineOperand::MO_Immediate: {
266 O << '#';
267 unsigned TF = MO.getTargetFlags();
268 if (TF == ARMII::MO_LO16)
269 O << ":lower16:";
270 else if (TF == ARMII::MO_HI16)
271 O << ":upper16:";
272 else if (TF == ARMII::MO_LO_0_7)
273 O << ":lower0_7:";
274 else if (TF == ARMII::MO_LO_8_15)
275 O << ":lower8_15:";
276 else if (TF == ARMII::MO_HI_0_7)
277 O << ":upper0_7:";
278 else if (TF == ARMII::MO_HI_8_15)
279 O << ":upper8_15:";
280 O << MO.getImm();
281 break;
282 }
283 case MachineOperand::MO_MachineBasicBlock:
284 MO.getMBB()->getSymbol()->print(OS&: O, MAI);
285 return;
286 case MachineOperand::MO_GlobalAddress: {
287 PrintSymbolOperand(MO, O);
288 break;
289 }
290 case MachineOperand::MO_ConstantPoolIndex:
291 assert(!MF->getSubtarget<ARMSubtarget>().genExecuteOnly() &&
292 "execute-only should not generate constant pools");
293 GetCPISymbol(CPID: MO.getIndex())->print(OS&: O, MAI);
294 break;
295 }
296}
297
298MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
299 // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
300 // indexes in MachineConstantPool, which isn't in sync with indexes used here.
301 const DataLayout &DL = getDataLayout();
302 return OutContext.getOrCreateSymbol(Name: Twine(DL.getInternalSymbolPrefix()) +
303 "CPI" + Twine(getFunctionNumber()) + "_" +
304 Twine(CPID));
305}
306
307//===--------------------------------------------------------------------===//
308
309MCSymbol *ARMAsmPrinter::
310GetARMJTIPICJumpTableLabel(unsigned uid) const {
311 const DataLayout &DL = getDataLayout();
312 SmallString<60> Name;
313 raw_svector_ostream(Name) << DL.getInternalSymbolPrefix() << "JTI"
314 << getFunctionNumber() << '_' << uid;
315 return OutContext.getOrCreateSymbol(Name);
316}
317
318bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
319 const char *ExtraCode, raw_ostream &O) {
320 // Does this asm operand have a single letter operand modifier?
321 if (ExtraCode && ExtraCode[0]) {
322 if (ExtraCode[1] != 0) return true; // Unknown modifier.
323
324 switch (ExtraCode[0]) {
325 default:
326 // See if this is a generic print operand
327 return AsmPrinter::PrintAsmOperand(MI, OpNo: OpNum, ExtraCode, OS&: O);
328 case 'P': // Print a VFP double precision register.
329 case 'q': // Print a NEON quad precision register.
330 printOperand(MI, OpNum, O);
331 return false;
332 case 'y': // Print a VFP single precision register as indexed double.
333 if (MI->getOperand(i: OpNum).isReg()) {
334 MCRegister Reg = MI->getOperand(i: OpNum).getReg().asMCReg();
335 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
336 // Find the 'd' register that has this 's' register as a sub-register,
337 // and determine the lane number.
338 for (MCPhysReg SR : TRI->superregs(Reg)) {
339 if (!ARM::DPRRegClass.contains(Reg: SR))
340 continue;
341 bool Lane0 = TRI->getSubReg(Reg: SR, Idx: ARM::ssub_0) == Reg;
342 O << ARMInstPrinter::getRegisterName(Reg: SR) << (Lane0 ? "[0]" : "[1]");
343 return false;
344 }
345 }
346 return true;
347 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
348 if (!MI->getOperand(i: OpNum).isImm())
349 return true;
350 O << ~(MI->getOperand(i: OpNum).getImm());
351 return false;
352 case 'L': // The low 16 bits of an immediate constant.
353 if (!MI->getOperand(i: OpNum).isImm())
354 return true;
355 O << (MI->getOperand(i: OpNum).getImm() & 0xffff);
356 return false;
357 case 'M': { // A register range suitable for LDM/STM.
358 if (!MI->getOperand(i: OpNum).isReg())
359 return true;
360 const MachineOperand &MO = MI->getOperand(i: OpNum);
361 Register RegBegin = MO.getReg();
362 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
363 // already got the operands in registers that are operands to the
364 // inline asm statement.
365 O << "{";
366 if (ARM::GPRPairRegClass.contains(Reg: RegBegin)) {
367 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
368 Register Reg0 = TRI->getSubReg(Reg: RegBegin, Idx: ARM::gsub_0);
369 O << ARMInstPrinter::getRegisterName(Reg: Reg0) << ", ";
370 RegBegin = TRI->getSubReg(Reg: RegBegin, Idx: ARM::gsub_1);
371 }
372 O << ARMInstPrinter::getRegisterName(Reg: RegBegin);
373
374 // FIXME: The register allocator not only may not have given us the
375 // registers in sequence, but may not be in ascending registers. This
376 // will require changes in the register allocator that'll need to be
377 // propagated down here if the operands change.
378 unsigned RegOps = OpNum + 1;
379 while (MI->getOperand(i: RegOps).isReg()) {
380 O << ", "
381 << ARMInstPrinter::getRegisterName(Reg: MI->getOperand(i: RegOps).getReg());
382 RegOps++;
383 }
384
385 O << "}";
386
387 return false;
388 }
389 case 'R': // The most significant register of a pair.
390 case 'Q': { // The least significant register of a pair.
391 if (OpNum == 0)
392 return true;
393 const MachineOperand &FlagsOP = MI->getOperand(i: OpNum - 1);
394 if (!FlagsOP.isImm())
395 return true;
396 InlineAsm::Flag F(FlagsOP.getImm());
397
398 // This operand may not be the one that actually provides the register. If
399 // it's tied to a previous one then we should refer instead to that one
400 // for registers and their classes.
401 unsigned TiedIdx;
402 if (F.isUseOperandTiedToDef(Idx&: TiedIdx)) {
403 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
404 unsigned OpFlags = MI->getOperand(i: OpNum).getImm();
405 const InlineAsm::Flag F(OpFlags);
406 OpNum += F.getNumOperandRegisters() + 1;
407 }
408 F = InlineAsm::Flag(MI->getOperand(i: OpNum).getImm());
409
410 // Later code expects OpNum to be pointing at the register rather than
411 // the flags.
412 OpNum += 1;
413 }
414
415 const unsigned NumVals = F.getNumOperandRegisters();
416 unsigned RC;
417 bool FirstHalf;
418 const ARMBaseTargetMachine &ATM =
419 static_cast<const ARMBaseTargetMachine &>(TM);
420
421 // 'Q' should correspond to the low order register and 'R' to the high
422 // order register. Whether this corresponds to the upper or lower half
423 // depends on the endianness mode.
424 if (ExtraCode[0] == 'Q')
425 FirstHalf = ATM.isLittleEndian();
426 else
427 // ExtraCode[0] == 'R'.
428 FirstHalf = !ATM.isLittleEndian();
429 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
430 if (F.hasRegClassConstraint(RC) &&
431 ARM::GPRPairRegClass.hasSubClassEq(RC: TRI->getRegClass(i: RC))) {
432 if (NumVals != 1)
433 return true;
434 const MachineOperand &MO = MI->getOperand(i: OpNum);
435 if (!MO.isReg())
436 return true;
437 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
438 Register Reg =
439 TRI->getSubReg(Reg: MO.getReg(), Idx: FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
440 O << ARMInstPrinter::getRegisterName(Reg);
441 return false;
442 }
443 if (NumVals != 2)
444 return true;
445 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
446 if (RegOp >= MI->getNumOperands())
447 return true;
448 const MachineOperand &MO = MI->getOperand(i: RegOp);
449 if (!MO.isReg())
450 return true;
451 Register Reg = MO.getReg();
452 O << ARMInstPrinter::getRegisterName(Reg);
453 return false;
454 }
455
456 case 'e': // The low doubleword register of a NEON quad register.
457 case 'f': { // The high doubleword register of a NEON quad register.
458 if (!MI->getOperand(i: OpNum).isReg())
459 return true;
460 Register Reg = MI->getOperand(i: OpNum).getReg();
461 if (!ARM::QPRRegClass.contains(Reg))
462 return true;
463 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
464 Register SubReg =
465 TRI->getSubReg(Reg, Idx: ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
466 O << ARMInstPrinter::getRegisterName(Reg: SubReg);
467 return false;
468 }
469
470 // This modifier is not yet supported.
471 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
472 return true;
473 case 'H': { // The highest-numbered register of a pair.
474 const MachineOperand &MO = MI->getOperand(i: OpNum);
475 if (!MO.isReg())
476 return true;
477 const MachineFunction &MF = *MI->getParent()->getParent();
478 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
479 Register Reg = MO.getReg();
480 if(!ARM::GPRPairRegClass.contains(Reg))
481 return false;
482 Reg = TRI->getSubReg(Reg, Idx: ARM::gsub_1);
483 O << ARMInstPrinter::getRegisterName(Reg);
484 return false;
485 }
486 }
487 }
488
489 printOperand(MI, OpNum, O);
490 return false;
491}
492
493bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
494 unsigned OpNum, const char *ExtraCode,
495 raw_ostream &O) {
496 // Does this asm operand have a single letter operand modifier?
497 if (ExtraCode && ExtraCode[0]) {
498 if (ExtraCode[1] != 0) return true; // Unknown modifier.
499
500 switch (ExtraCode[0]) {
501 case 'A': // A memory operand for a VLD1/VST1 instruction.
502 default: return true; // Unknown modifier.
503 case 'm': // The base register of a memory operand.
504 if (!MI->getOperand(i: OpNum).isReg())
505 return true;
506 O << ARMInstPrinter::getRegisterName(Reg: MI->getOperand(i: OpNum).getReg());
507 return false;
508 }
509 }
510
511 const MachineOperand &MO = MI->getOperand(i: OpNum);
512 assert(MO.isReg() && "unexpected inline asm memory operand");
513 O << "[" << ARMInstPrinter::getRegisterName(Reg: MO.getReg()) << "]";
514 return false;
515}
516
517static bool isThumb(const MCSubtargetInfo& STI) {
518 return STI.hasFeature(Feature: ARM::ModeThumb);
519}
520
521void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
522 const MCSubtargetInfo *EndInfo,
523 const MachineInstr *MI) {
524 // If either end mode is unknown (EndInfo == NULL) or different than
525 // the start mode, then restore the start mode.
526 const bool WasThumb = isThumb(STI: StartInfo);
527 if (!EndInfo || WasThumb != isThumb(STI: *EndInfo)) {
528 auto &TS =
529 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
530 if (WasThumb)
531 TS.emitCode16();
532 else
533 TS.emitCode32();
534 }
535}
536
537void ARMAsmPrinter::emitStartOfAsmFile(Module &M) {
538 const Triple &TT = M.getTargetTriple();
539 auto &TS =
540 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
541 // Use unified assembler syntax.
542 TS.emitSyntaxUnified();
543
544 // Emit ARM Build Attributes
545 if (TT.isOSBinFormatELF())
546 emitAttributes();
547
548 // Use the triple's architecture and subarchitecture to determine
549 // if we're thumb for the purposes of the top level code16 state.
550 if (!M.getModuleInlineAsm().empty() && TT.isThumb())
551 TS.emitCode16();
552}
553
554static void
555emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
556 MachineModuleInfoImpl::StubValueTy &MCSym) {
557 // L_foo$stub:
558 OutStreamer.emitLabel(Symbol: StubLabel);
559 // .indirect_symbol _foo
560 OutStreamer.emitSymbolAttribute(Symbol: MCSym.getPointer(), Attribute: MCSA_IndirectSymbol);
561
562 if (MCSym.getInt())
563 // External to current translation unit.
564 OutStreamer.emitIntValue(Value: 0, Size: 4/*size*/);
565 else
566 // Internal to current translation unit.
567 //
568 // When we place the LSDA into the TEXT section, the type info
569 // pointers need to be indirect and pc-rel. We accomplish this by
570 // using NLPs; however, sometimes the types are local to the file.
571 // We need to fill in the value for the NLP in those cases.
572 OutStreamer.emitValue(
573 Value: MCSymbolRefExpr::create(Symbol: MCSym.getPointer(), Ctx&: OutStreamer.getContext()),
574 Size: 4 /*size*/);
575}
576
577
578void ARMAsmPrinter::emitEndOfAsmFile(Module &M) {
579 const Triple &TT = M.getTargetTriple();
580 if (TT.isOSBinFormatMachO()) {
581 // All darwin targets use mach-o.
582 const TargetLoweringObjectFileMachO &TLOFMacho =
583 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
584 MachineModuleInfoMachO &MMIMacho =
585 MMI->getObjFileInfo<MachineModuleInfoMachO>();
586
587 // Output non-lazy-pointers for external and common global variables.
588 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
589
590 if (!Stubs.empty()) {
591 // Switch with ".non_lazy_symbol_pointer" directive.
592 OutStreamer->switchSection(Section: TLOFMacho.getNonLazySymbolPointerSection());
593 emitAlignment(Alignment: Align(4));
594
595 for (auto &Stub : Stubs)
596 emitNonLazySymbolPointer(OutStreamer&: *OutStreamer, StubLabel: Stub.first, MCSym&: Stub.second);
597
598 Stubs.clear();
599 OutStreamer->addBlankLine();
600 }
601
602 Stubs = MMIMacho.GetThreadLocalGVStubList();
603 if (!Stubs.empty()) {
604 // Switch with ".non_lazy_symbol_pointer" directive.
605 OutStreamer->switchSection(Section: TLOFMacho.getThreadLocalPointerSection());
606 emitAlignment(Alignment: Align(4));
607
608 for (auto &Stub : Stubs)
609 emitNonLazySymbolPointer(OutStreamer&: *OutStreamer, StubLabel: Stub.first, MCSym&: Stub.second);
610
611 Stubs.clear();
612 OutStreamer->addBlankLine();
613 }
614
615 // Funny Darwin hack: This flag tells the linker that no global symbols
616 // contain code that falls through to other global symbols (e.g. the obvious
617 // implementation of multiple entry points). If this doesn't occur, the
618 // linker can safely perform dead code stripping. Since LLVM never
619 // generates code that does this, it is always safe to set.
620 OutStreamer->emitSubsectionsViaSymbols();
621 }
622
623 // The last attribute to be emitted is ABI_optimization_goals
624 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
625 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
626
627 if (OptimizationGoals > 0 &&
628 (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI()))
629 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_optimization_goals, Value: OptimizationGoals);
630 OptimizationGoals = -1;
631
632 ATS.finishAttributeSection();
633}
634
635//===----------------------------------------------------------------------===//
636// Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
637// FIXME:
638// The following seem like one-off assembler flags, but they actually need
639// to appear in the .ARM.attributes section in ELF.
640// Instead of subclassing the MCELFStreamer, we do the work here.
641
642// Returns true if all function definitions have the same function attribute
643// value. It also returns true when the module has no functions.
644static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
645 StringRef Value) {
646 return !any_of(Range: M, P: [&](const Function &F) {
647 if (F.isDeclaration())
648 return false;
649 return F.getFnAttribute(Kind: Attr).getValueAsString() != Value;
650 });
651}
652// Returns true if all functions definitions have the same denormal mode.
653// It also returns true when the module has no functions.
654static bool checkDenormalAttributeConsistency(const Module &M,
655 DenormalFPEnv Value) {
656 return !any_of(Range: M, P: [&](const Function &F) {
657 if (F.isDeclaration())
658 return false;
659 return F.getDenormalFPEnv() != Value;
660 });
661}
662
663// Returns true if any function definition in the module has the strictfp
664// attribute, which taints the whole module: such code may change the FP
665// rounding mode at run time.
666static bool checkModuleHasStrictFP(const Module &M) {
667 return any_of(Range: M, P: [](const Function &F) {
668 return !F.isDeclaration() && F.isStrictFP();
669 });
670}
671
672// Returns true if all functions have different denormal modes.
673static bool checkDenormalAttributeInconsistency(const Module &M) {
674 auto F = M.functions().begin();
675 auto E = M.functions().end();
676 if (F == E)
677 return false;
678 DenormalFPEnv Value = F->getDenormalFPEnv();
679 ++F;
680 return std::any_of(first: F, last: E, pred: [&](const Function &F) {
681 return !F.isDeclaration() && F.getDenormalFPEnv() != Value;
682 });
683}
684
685void ARMAsmPrinter::emitAttributes() {
686 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
687 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
688
689 ATS.emitTextAttribute(Attribute: ARMBuildAttrs::conformance, String: "2.09");
690
691 ATS.switchVendor(Vendor: "aeabi");
692
693 // Compute ARM ELF Attributes based on the default subtarget that
694 // we'd have constructed. The existing ARM behavior isn't LTO clean
695 // anyhow.
696 // FIXME: For ifunc related functions we could iterate over and look
697 // for a feature string that doesn't match the default one.
698 const Triple &TT = TM.getTargetTriple();
699 StringRef CPU = TM.getTargetCPU();
700 StringRef FS = TM.getTargetFeatureString();
701 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
702 if (!FS.empty()) {
703 if (!ArchFS.empty())
704 ArchFS = (Twine(ArchFS) + "," + FS).str();
705 else
706 ArchFS = std::string(FS);
707 }
708 const ARMBaseTargetMachine &ATM =
709 static_cast<const ARMBaseTargetMachine &>(TM);
710 FloatABI::ABIType FloatABI = ATM.getFloatABI(M: *MMI->getModule());
711 ARM::ARMABI ABI = ATM.getEffectiveABI(M: *MMI->getModule());
712 const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
713 ATM.isLittleEndian(), FloatABI, ABI);
714
715 // Emit build attributes for the available hardware.
716 ATS.emitTargetAttributes(STI);
717
718 // RW data addressing.
719 if (isPositionIndependent()) {
720 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RW_data,
721 Value: ARMBuildAttrs::AddressRWPCRel);
722 } else if (STI.isRWPI()) {
723 // RWPI specific attributes.
724 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RW_data,
725 Value: ARMBuildAttrs::AddressRWSBRel);
726 }
727
728 // RO data addressing.
729 if (isPositionIndependent() || STI.isROPI()) {
730 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RO_data,
731 Value: ARMBuildAttrs::AddressROPCRel);
732 }
733
734 // GOT use.
735 if (isPositionIndependent()) {
736 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_GOT_use,
737 Value: ARMBuildAttrs::AddressGOT);
738 } else {
739 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_GOT_use,
740 Value: ARMBuildAttrs::AddressDirect);
741 }
742
743 // Set FP Denormals.
744 if (auto *DM = mdconst::extract_or_null<ConstantInt>(
745 MD: MMI->getModule()->getModuleFlag(Key: "arm-eabi-fp-denormal"))) {
746 if (unsigned TagVal = DM->getZExtValue())
747 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal, Value: TagVal);
748 } else if (checkDenormalAttributeConsistency(M: *MMI->getModule(),
749 Value: DenormalMode::getPreserveSign()))
750 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
751 Value: ARMBuildAttrs::PreserveFPSign);
752 else if (checkDenormalAttributeConsistency(M: *MMI->getModule(),
753 Value: DenormalMode::getPositiveZero()))
754 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
755 Value: ARMBuildAttrs::PositiveZero);
756 else if (checkDenormalAttributeInconsistency(M: *MMI->getModule()) ||
757 checkDenormalAttributeConsistency(M: *MMI->getModule(),
758 Value: DenormalMode::getIEEE()))
759 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
760 Value: ARMBuildAttrs::IEEEDenormals);
761 else {
762 if (!STI.hasVFP2Base()) {
763 // When the target doesn't have an FPU (by design or
764 // intention), the assumptions made on the software support
765 // mirror that of the equivalent hardware support *if it
766 // existed*. For v7 and better we indicate that denormals are
767 // flushed preserving sign, and for V6 we indicate that
768 // denormals are flushed to positive zero.
769 if (STI.hasV7Ops())
770 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
771 Value: ARMBuildAttrs::PreserveFPSign);
772 } else if (STI.hasVFP3Base()) {
773 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
774 // the sign bit of the zero matches the sign bit of the input or
775 // result that is being flushed to zero.
776 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
777 Value: ARMBuildAttrs::PreserveFPSign);
778 }
779 // For VFPv2 implementations it is implementation defined as
780 // to whether denormals are flushed to positive zero or to
781 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
782 // LLVM has chosen to flush this to positive zero (most likely for
783 // GCC compatibility), so that's the chosen value here (the
784 // absence of its emission implies zero).
785 }
786
787 // Set FP exceptions and rounding
788 if (auto *Ex = mdconst::extract_or_null<ConstantInt>(
789 MD: MMI->getModule()->getModuleFlag(Key: "arm-eabi-fp-exceptions"))) {
790 if (unsigned TagVal = Ex->getZExtValue())
791 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions, Value: TagVal);
792 } else if (checkFunctionsAttributeConsistency(M: *MMI->getModule(),
793 Attr: "no-trapping-math", Value: "true"))
794 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions,
795 Value: ARMBuildAttrs::Not_Allowed);
796 else {
797 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions, Value: ARMBuildAttrs::Allowed);
798
799 // If any function may change the FP rounding mode at run time the code
800 // cannot assume the default rounding, so emit the rounding attribute.
801 if (checkModuleHasStrictFP(M: *MMI->getModule()))
802 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_rounding, Value: ARMBuildAttrs::Allowed);
803 }
804
805 // Generate ABI tags from module flags.
806 if (auto *NumModel = mdconst::extract_or_null<ConstantInt>(
807 MD: MMI->getModule()->getModuleFlag(Key: "arm-eabi-fp-number-model"))) {
808 if (unsigned TagVal = NumModel->getZExtValue())
809 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_number_model, Value: TagVal);
810 } else
811 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_number_model,
812 Value: ARMBuildAttrs::AllowIEEE754);
813
814 // FIXME: add more flags to ARMBuildAttributes.h
815 // 8-bytes alignment stuff.
816 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_align_needed, Value: 1);
817 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_align_preserved, Value: 1);
818
819 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
820 if (STI.isAAPCS_ABI() && STI.isTargetHardFloat())
821 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_VFP_args, Value: ARMBuildAttrs::HardFPAAPCS);
822
823 // FIXME: To support emitting this build attribute as GCC does, the
824 // -mfp16-format option and associated plumbing must be
825 // supported. For now the __fp16 type is exposed by default, so this
826 // attribute should be emitted with value 1.
827 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_16bit_format,
828 Value: ARMBuildAttrs::FP16FormatIEEE);
829
830 if (const Module *SourceModule = MMI->getModule()) {
831 // ABI_PCS_wchar_t to indicate wchar_t width
832 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
833 int WCharWidth = SourceModule->getTargetTriple().getDefaultWCharSize();
834 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
835 MD: SourceModule->getModuleFlag(Key: "wchar_size")))
836 WCharWidth = WCharWidthValue->getZExtValue();
837 assert((WCharWidth == 2 || WCharWidth == 4) &&
838 "wchar_t width must be 2 or 4 bytes");
839 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_wchar_t, Value: WCharWidth);
840
841 // ABI_enum_size to indicate enum width
842 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
843 // (all enums contain a value needing 32 bits to encode).
844 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
845 MD: SourceModule->getModuleFlag(Key: "min_enum_size"))) {
846 int EnumWidth = EnumWidthValue->getZExtValue();
847 assert((EnumWidth == 1 || EnumWidth == 4) &&
848 "Minimum enum width must be 1 or 4 bytes");
849 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
850 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_enum_size, Value: EnumBuildAttr);
851 }
852
853 auto *PACValue = mdconst::extract_or_null<ConstantInt>(
854 MD: SourceModule->getModuleFlag(Key: "sign-return-address"));
855 if (PACValue && PACValue->isOne()) {
856 // If "+pacbti" is used as an architecture extension,
857 // Tag_PAC_extension is emitted in
858 // ARMTargetStreamer::emitTargetAttributes().
859 if (!STI.hasPACBTI()) {
860 ATS.emitAttribute(Attribute: ARMBuildAttrs::PAC_extension,
861 Value: ARMBuildAttrs::AllowPACInNOPSpace);
862 }
863 ATS.emitAttribute(Attribute: ARMBuildAttrs::PACRET_use, Value: ARMBuildAttrs::PACRETUsed);
864 }
865
866 auto *BTIValue = mdconst::extract_or_null<ConstantInt>(
867 MD: SourceModule->getModuleFlag(Key: "branch-target-enforcement"));
868 if (BTIValue && !BTIValue->isZero()) {
869 // If "+pacbti" is used as an architecture extension,
870 // Tag_BTI_extension is emitted in
871 // ARMTargetStreamer::emitTargetAttributes().
872 if (!STI.hasPACBTI()) {
873 ATS.emitAttribute(Attribute: ARMBuildAttrs::BTI_extension,
874 Value: ARMBuildAttrs::AllowBTIInNOPSpace);
875 }
876 ATS.emitAttribute(Attribute: ARMBuildAttrs::BTI_use, Value: ARMBuildAttrs::BTIUsed);
877 }
878 }
879
880 // We currently do not support using R9 as the TLS pointer.
881 if (STI.isRWPI())
882 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
883 Value: ARMBuildAttrs::R9IsSB);
884 else if (STI.isR9Reserved())
885 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
886 Value: ARMBuildAttrs::R9Reserved);
887 else
888 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
889 Value: ARMBuildAttrs::R9IsGPR);
890}
891
892//===----------------------------------------------------------------------===//
893
894static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
895 unsigned LabelId, MCContext &Ctx) {
896
897 MCSymbol *Label = Ctx.getOrCreateSymbol(Name: Twine(Prefix)
898 + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
899 return Label;
900}
901
902static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
903 unsigned LabelId, MCContext &Ctx) {
904
905 MCSymbol *Label = Ctx.getOrCreateSymbol(Name: Twine(Prefix)
906 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
907 return Label;
908}
909
910static uint8_t getModifierSpecifier(ARMCP::ARMCPModifier Modifier) {
911 switch (Modifier) {
912 case ARMCP::no_modifier:
913 return ARM::S_None;
914 case ARMCP::TLSGD:
915 return ARM::S_TLSGD;
916 case ARMCP::TPOFF:
917 return ARM::S_TPOFF;
918 case ARMCP::GOTTPOFF:
919 return ARM::S_GOTTPOFF;
920 case ARMCP::SBREL:
921 return ARM::S_SBREL;
922 case ARMCP::GOT_PREL:
923 return ARM::S_GOT_PREL;
924 case ARMCP::SECREL:
925 return ARM::S_COFF_SECREL;
926 }
927 llvm_unreachable("Invalid ARMCPModifier!");
928}
929
930MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
931 unsigned char TargetFlags) {
932 const Triple &TT = GV->getParent()->getTargetTriple();
933 if (TT.isOSBinFormatMachO()) {
934 bool IsIndirect =
935 (TargetFlags & ARMII::MO_NONLAZY) && getTM().isGVIndirectSymbol(GV);
936
937 if (!IsIndirect)
938 return getSymbol(GV);
939
940 // FIXME: Remove this when Darwin transition to @GOT like syntax.
941 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, Suffix: "$non_lazy_ptr");
942 MachineModuleInfoMachO &MMIMachO =
943 MMI->getObjFileInfo<MachineModuleInfoMachO>();
944 MachineModuleInfoImpl::StubValueTy &StubSym =
945 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(Sym: MCSym)
946 : MMIMachO.getGVStubEntry(Sym: MCSym);
947
948 if (!StubSym.getPointer())
949 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
950 !GV->hasInternalLinkage());
951 return MCSym;
952 } else if (TT.isOSBinFormatCOFF()) {
953 assert(TT.isOSWindows() && "Windows is the only supported COFF target");
954
955 bool IsIndirect =
956 (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
957 if (!IsIndirect)
958 return getSymbol(GV);
959
960 SmallString<128> Name;
961 if (TargetFlags & ARMII::MO_DLLIMPORT)
962 Name = "__imp_";
963 else if (TargetFlags & ARMII::MO_COFFSTUB)
964 Name = ".refptr.";
965 getNameWithPrefix(Name, GV);
966
967 MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
968
969 if (TargetFlags & ARMII::MO_COFFSTUB) {
970 MachineModuleInfoCOFF &MMICOFF =
971 MMI->getObjFileInfo<MachineModuleInfoCOFF>();
972 MachineModuleInfoImpl::StubValueTy &StubSym =
973 MMICOFF.getGVStubEntry(Sym: MCSym);
974
975 if (!StubSym.getPointer())
976 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
977 }
978
979 return MCSym;
980 } else if (TT.isOSBinFormatELF()) {
981 return getSymbolPreferLocal(GV: *GV);
982 }
983 llvm_unreachable("unexpected target");
984}
985
986void ARMAsmPrinter::emitMachineConstantPoolValue(
987 MachineConstantPoolValue *MCPV) {
988 const DataLayout &DL = getDataLayout();
989 int Size = DL.getTypeAllocSize(Ty: MCPV->getType());
990
991 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
992
993 if (ACPV->isPromotedGlobal()) {
994 // This constant pool entry is actually a global whose storage has been
995 // promoted into the constant pool. This global may be referenced still
996 // by debug information, and due to the way AsmPrinter is set up, the debug
997 // info is immutable by the time we decide to promote globals to constant
998 // pools. Because of this, we need to ensure we emit a symbol for the global
999 // with private linkage (the default) so debug info can refer to it.
1000 //
1001 // However, if this global is promoted into several functions we must ensure
1002 // we don't try and emit duplicate symbols!
1003 auto *ACPC = cast<ARMConstantPoolConstant>(Val: ACPV);
1004 for (const auto *GV : ACPC->promotedGlobals()) {
1005 if (!EmittedPromotedGlobalLabels.count(Ptr: GV)) {
1006 MCSymbol *GVSym = getSymbol(GV);
1007 OutStreamer->emitLabel(Symbol: GVSym);
1008 EmittedPromotedGlobalLabels.insert(Ptr: GV);
1009 }
1010 }
1011 return emitGlobalConstant(DL, CV: ACPC->getPromotedGlobalInit());
1012 }
1013
1014 MCSymbol *MCSym;
1015 if (ACPV->isLSDA()) {
1016 MCSym = getMBBExceptionSym(MBB: MF->front());
1017 } else if (ACPV->isBlockAddress()) {
1018 const BlockAddress *BA =
1019 cast<ARMConstantPoolConstant>(Val: ACPV)->getBlockAddress();
1020 MCSym = GetBlockAddressSymbol(BA);
1021 } else if (ACPV->isGlobalValue()) {
1022 const GlobalValue *GV = cast<ARMConstantPoolConstant>(Val: ACPV)->getGV();
1023
1024 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
1025 // flag the global as MO_NONLAZY.
1026 unsigned char TF =
1027 TM.getTargetTriple().isOSBinFormatMachO() ? ARMII::MO_NONLAZY : 0;
1028 MCSym = GetARMGVSymbol(GV, TargetFlags: TF);
1029
1030 // For dso_local weak symbols in ELF PIC mode, the assembler would eagerly
1031 // resolve a PC-relative expression like sym-(LPC+8) when the symbol and
1032 // reference are in the same section, preventing the linker from overriding
1033 // a weak definition with a non-weak definition from another section. Use a
1034 // .reloc directive rather than a fixup to force the generation of a
1035 // relocation (R_ARM_REL32) so the linker can perform the override. This is
1036 // restricted to dso_local, non-TLS symbols: a preemptible/external weak
1037 // symbol (e.g. an extern_weak reference) must use the GOT, as R_ARM_REL32
1038 // against an external symbol cannot be used when making a shared object;
1039 // and TLS symbols require TLS-specific relocations, not R_ARM_REL32.
1040 if (GV->isWeakForLinker() && GV->isDSOLocal() && !GV->isThreadLocal() &&
1041 TM.getTargetTriple().isOSBinFormatELF() && TM.isPositionIndependent() &&
1042 ACPV->getPCAdjustment() != 0) {
1043 MCSymbol *CPILabel = OutContext.createTempSymbol();
1044 OutStreamer->emitLabel(Symbol: CPILabel);
1045 // Emit local-only expression: CPILabel - (LPC+PCAdj)
1046 const MCExpr *LocalExpr = MCSymbolRefExpr::create(Symbol: CPILabel, Ctx&: OutContext);
1047 MCSymbol *PCLabel =
1048 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
1049 LabelId: ACPV->getLabelId(), Ctx&: OutContext);
1050 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(Symbol: PCLabel, Ctx&: OutContext);
1051 PCRelExpr = MCBinaryExpr::createAdd(
1052 LHS: PCRelExpr,
1053 RHS: MCConstantExpr::create(Value: ACPV->getPCAdjustment(), Ctx&: OutContext),
1054 Ctx&: OutContext);
1055 LocalExpr = MCBinaryExpr::createSub(LHS: LocalExpr, RHS: PCRelExpr, Ctx&: OutContext);
1056 OutStreamer->emitValue(Value: LocalExpr, Size);
1057 // Emit .reloc to force linker resolution of the weak symbol.
1058 const MCExpr *CPIExpr = MCSymbolRefExpr::create(Symbol: CPILabel, Ctx&: OutContext);
1059 const MCExpr *SymExpr = MCSymbolRefExpr::create(Symbol: MCSym, Ctx&: OutContext);
1060 OutStreamer->emitRelocDirective(Offset: *CPIExpr, Name: "R_ARM_REL32", Expr: SymExpr,
1061 Loc: SMLoc());
1062 return;
1063 }
1064 } else if (ACPV->isMachineBasicBlock()) {
1065 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(Val: ACPV)->getMBB();
1066 MCSym = MBB->getSymbol();
1067 } else {
1068 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
1069 auto Sym = cast<ARMConstantPoolSymbol>(Val: ACPV)->getSymbol();
1070 MCSym = GetExternalSymbolSymbol(Sym);
1071 }
1072
1073 // Create an MCSymbol for the reference.
1074 const MCExpr *Expr = MCSymbolRefExpr::create(
1075 Symbol: MCSym, specifier: getModifierSpecifier(Modifier: ACPV->getModifier()), Ctx&: OutContext);
1076
1077 if (ACPV->getPCAdjustment()) {
1078 MCSymbol *PCLabel =
1079 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
1080 LabelId: ACPV->getLabelId(), Ctx&: OutContext);
1081 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(Symbol: PCLabel, Ctx&: OutContext);
1082 PCRelExpr =
1083 MCBinaryExpr::createAdd(LHS: PCRelExpr,
1084 RHS: MCConstantExpr::create(Value: ACPV->getPCAdjustment(),
1085 Ctx&: OutContext),
1086 Ctx&: OutContext);
1087 if (ACPV->mustAddCurrentAddress()) {
1088 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
1089 // label, so just emit a local label end reference that instead.
1090 MCSymbol *DotSym = OutContext.createTempSymbol();
1091 OutStreamer->emitLabel(Symbol: DotSym);
1092 const MCExpr *DotExpr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
1093 PCRelExpr = MCBinaryExpr::createSub(LHS: PCRelExpr, RHS: DotExpr, Ctx&: OutContext);
1094 }
1095 Expr = MCBinaryExpr::createSub(LHS: Expr, RHS: PCRelExpr, Ctx&: OutContext);
1096 }
1097 OutStreamer->emitValue(Value: Expr, Size);
1098}
1099
1100void ARMAsmPrinter::emitJumpTableAddrs(const MachineInstr *MI) {
1101 const MachineOperand &MO1 = MI->getOperand(i: 1);
1102 unsigned JTI = MO1.getIndex();
1103
1104 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1105 // ARM mode tables.
1106 emitAlignment(Alignment: Align(4));
1107
1108 // Emit a label for the jump table.
1109 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1110 OutStreamer->emitLabel(Symbol: JTISymbol);
1111
1112 // Mark the jump table as data-in-code.
1113 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionJT32);
1114
1115 // Emit each entry of the table.
1116 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1117 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1118 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1119
1120 for (MachineBasicBlock *MBB : JTBBs) {
1121 // Construct an MCExpr for the entry. We want a value of the form:
1122 // (BasicBlockAddr - TableBeginAddr)
1123 //
1124 // For example, a table with entries jumping to basic blocks BB0 and BB1
1125 // would look like:
1126 // LJTI_0_0:
1127 // .word (LBB0 - LJTI_0_0)
1128 // .word (LBB1 - LJTI_0_0)
1129 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(), Ctx&: OutContext);
1130
1131 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1132 if (isPositionIndependent() || STI.isROPI())
1133 Expr = MCBinaryExpr::createSub(LHS: Expr, RHS: MCSymbolRefExpr::create(Symbol: JTISymbol,
1134 Ctx&: OutContext),
1135 Ctx&: OutContext);
1136 // If we're generating a table of Thumb addresses in static relocation
1137 // model, we need to add one to keep interworking correctly.
1138 else if (AFI->isThumbFunction())
1139 Expr = MCBinaryExpr::createAdd(LHS: Expr, RHS: MCConstantExpr::create(Value: 1,Ctx&: OutContext),
1140 Ctx&: OutContext);
1141 OutStreamer->emitValue(Value: Expr, Size: 4);
1142 }
1143 // Mark the end of jump table data-in-code region.
1144 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1145}
1146
1147void ARMAsmPrinter::emitJumpTableInsts(const MachineInstr *MI) {
1148 const MachineOperand &MO1 = MI->getOperand(i: 1);
1149 unsigned JTI = MO1.getIndex();
1150
1151 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1152 // ARM mode tables.
1153 emitAlignment(Alignment: Align(4));
1154
1155 // Emit a label for the jump table.
1156 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1157 OutStreamer->emitLabel(Symbol: JTISymbol);
1158
1159 // Emit each entry of the table.
1160 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1161 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1162 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1163
1164 for (MachineBasicBlock *MBB : JTBBs) {
1165 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(),
1166 Ctx&: OutContext);
1167 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1168 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2B)
1169 .addExpr(Val: MBBSymbolExpr)
1170 .addImm(Val: ARMCC::AL)
1171 .addReg(Reg: 0));
1172 }
1173}
1174
1175void ARMAsmPrinter::emitJumpTableTBInst(const MachineInstr *MI,
1176 unsigned OffsetWidth) {
1177 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1178 const MachineOperand &MO1 = MI->getOperand(i: 1);
1179 unsigned JTI = MO1.getIndex();
1180
1181 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1182 if (STI.isThumb1Only())
1183 emitAlignment(Alignment: Align(4));
1184
1185 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1186 OutStreamer->emitLabel(Symbol: JTISymbol);
1187
1188 // Emit each entry of the table.
1189 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1190 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1191 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1192
1193 // Mark the jump table as data-in-code.
1194 OutStreamer->emitDataRegion(Kind: OffsetWidth == 1 ? MCDR_DataRegionJT8
1195 : MCDR_DataRegionJT16);
1196
1197 for (auto *MBB : JTBBs) {
1198 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(),
1199 Ctx&: OutContext);
1200 // Otherwise it's an offset from the dispatch instruction. Construct an
1201 // MCExpr for the entry. We want a value of the form:
1202 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1203 //
1204 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1205 // would look like:
1206 // LJTI_0_0:
1207 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1208 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1209 // where LCPI0_0 is a label defined just before the TBB instruction using
1210 // this table.
1211 MCSymbol *TBInstPC = GetCPISymbol(CPID: MI->getOperand(i: 0).getImm());
1212 const MCExpr *Expr = MCBinaryExpr::createAdd(
1213 LHS: MCSymbolRefExpr::create(Symbol: TBInstPC, Ctx&: OutContext),
1214 RHS: MCConstantExpr::create(Value: 4, Ctx&: OutContext), Ctx&: OutContext);
1215 Expr = MCBinaryExpr::createSub(LHS: MBBSymbolExpr, RHS: Expr, Ctx&: OutContext);
1216 Expr = MCBinaryExpr::createDiv(LHS: Expr, RHS: MCConstantExpr::create(Value: 2, Ctx&: OutContext),
1217 Ctx&: OutContext);
1218 OutStreamer->emitValue(Value: Expr, Size: OffsetWidth);
1219 }
1220 // Mark the end of jump table data-in-code region. 32-bit offsets use
1221 // actual branch instructions here, so we don't mark those as a data-region
1222 // at all.
1223 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1224
1225 // Make sure the next instruction is 2-byte aligned.
1226 emitAlignment(Alignment: Align(2));
1227}
1228
1229std::tuple<const MCSymbol *, uint64_t, const MCSymbol *,
1230 codeview::JumpTableEntrySize>
1231ARMAsmPrinter::getCodeViewJumpTableInfo(int JTI,
1232 const MachineInstr *BranchInstr,
1233 const MCSymbol *BranchLabel) const {
1234 codeview::JumpTableEntrySize EntrySize;
1235 const MCSymbol *BaseLabel;
1236 uint64_t BaseOffset = 0;
1237 switch (BranchInstr->getOpcode()) {
1238 case ARM::BR_JTadd:
1239 case ARM::BR_JTr:
1240 case ARM::tBR_JTr:
1241 // Word relative to the jump table address.
1242 EntrySize = codeview::JumpTableEntrySize::UInt32;
1243 BaseLabel = GetARMJTIPICJumpTableLabel(uid: JTI);
1244 break;
1245 case ARM::tTBH_JT:
1246 case ARM::t2TBH_JT:
1247 // half-word shifted left, relative to *after* the branch instruction.
1248 EntrySize = codeview::JumpTableEntrySize::UInt16ShiftLeft;
1249 BranchLabel = GetCPISymbol(CPID: BranchInstr->getOperand(i: 3).getImm());
1250 BaseLabel = BranchLabel;
1251 BaseOffset = 4;
1252 break;
1253 case ARM::tTBB_JT:
1254 case ARM::t2TBB_JT:
1255 // byte shifted left, relative to *after* the branch instruction.
1256 EntrySize = codeview::JumpTableEntrySize::UInt8ShiftLeft;
1257 BranchLabel = GetCPISymbol(CPID: BranchInstr->getOperand(i: 3).getImm());
1258 BaseLabel = BranchLabel;
1259 BaseOffset = 4;
1260 break;
1261 case ARM::t2BR_JT:
1262 // Direct jump.
1263 BaseLabel = nullptr;
1264 EntrySize = codeview::JumpTableEntrySize::Pointer;
1265 break;
1266 default:
1267 llvm_unreachable("Unknown jump table instruction");
1268 }
1269
1270 return std::make_tuple(args&: BaseLabel, args&: BaseOffset, args&: BranchLabel, args&: EntrySize);
1271}
1272
1273void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1274 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1275 "Only instruction which are involved into frame setup code are allowed");
1276
1277 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1278 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1279 const MachineFunction &MF = *MI->getParent()->getParent();
1280 const TargetRegisterInfo *TargetRegInfo =
1281 MF.getSubtarget().getRegisterInfo();
1282 const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1283
1284 Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1285 unsigned Opc = MI->getOpcode();
1286 unsigned SrcReg, DstReg;
1287
1288 switch (Opc) {
1289 case ARM::tPUSH:
1290 // special case: tPUSH does not have src/dst regs.
1291 SrcReg = DstReg = ARM::SP;
1292 break;
1293 case ARM::tLDRpci:
1294 case ARM::t2MOVi16:
1295 case ARM::t2MOVTi16:
1296 case ARM::tMOVi8:
1297 case ARM::tADDi8:
1298 case ARM::tLSLri:
1299 // special cases:
1300 // 1) for Thumb1 code we sometimes materialize the constant via constpool
1301 // load.
1302 // 2) for Thumb1 execute only code we materialize the constant via the
1303 // following pattern:
1304 // movs r3, #:upper8_15:<const>
1305 // lsls r3, #8
1306 // adds r3, #:upper0_7:<const>
1307 // lsls r3, #8
1308 // adds r3, #:lower8_15:<const>
1309 // lsls r3, #8
1310 // adds r3, #:lower0_7:<const>
1311 // So we need to special-case MOVS, ADDS and LSLS, and keep track of
1312 // where we are in the sequence with the simplest of state machines.
1313 // 3) for Thumb2 execute only code we materialize the constant via
1314 // immediate constants in 2 separate instructions (MOVW/MOVT).
1315 SrcReg = ~0U;
1316 DstReg = MI->getOperand(i: 0).getReg();
1317 break;
1318 case ARM::VMRS:
1319 SrcReg = ARM::FPSCR;
1320 DstReg = MI->getOperand(i: 0).getReg();
1321 break;
1322 case ARM::VMRS_FPEXC:
1323 SrcReg = ARM::FPEXC;
1324 DstReg = MI->getOperand(i: 0).getReg();
1325 break;
1326 default:
1327 SrcReg = MI->getOperand(i: 1).getReg();
1328 DstReg = MI->getOperand(i: 0).getReg();
1329 break;
1330 }
1331
1332 // Try to figure out the unwinding opcode out of src / dst regs.
1333 if (MI->mayStore()) {
1334 // Register saves.
1335 assert(DstReg == ARM::SP &&
1336 "Only stack pointer as a destination reg is supported");
1337
1338 SmallVector<MCRegister, 4> RegList;
1339 // Skip src & dst reg, and pred ops.
1340 unsigned StartOp = 2 + 2;
1341 // Use all the operands.
1342 unsigned NumOffset = 0;
1343 // Amount of SP adjustment folded into a push, before the
1344 // registers are stored (pad at higher addresses).
1345 unsigned PadBefore = 0;
1346 // Amount of SP adjustment folded into a push, after the
1347 // registers are stored (pad at lower addresses).
1348 unsigned PadAfter = 0;
1349
1350 switch (Opc) {
1351 default:
1352 MI->print(OS&: errs());
1353 llvm_unreachable("Unsupported opcode for unwinding information");
1354 case ARM::tPUSH:
1355 // Special case here: no src & dst reg, but two extra imp ops.
1356 StartOp = 2; NumOffset = 2;
1357 [[fallthrough]];
1358 case ARM::STMDB_UPD:
1359 case ARM::t2STMDB_UPD:
1360 case ARM::VSTMDDB_UPD:
1361 assert(SrcReg == ARM::SP &&
1362 "Only stack pointer as a source reg is supported");
1363 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1364 i != NumOps; ++i) {
1365 const MachineOperand &MO = MI->getOperand(i);
1366 // Actually, there should never be any impdef stuff here. Skip it
1367 // temporary to workaround PR11902.
1368 if (MO.isImplicit())
1369 continue;
1370 // Registers, pushed as a part of folding an SP update into the
1371 // push instruction are marked as undef and should not be
1372 // restored when unwinding, because the function can modify the
1373 // corresponding stack slots.
1374 if (MO.isUndef()) {
1375 assert(RegList.empty() &&
1376 "Pad registers must come before restored ones");
1377 unsigned Width =
1378 TargetRegInfo->getRegSizeInBits(Reg: MO.getReg(), MRI: MachineRegInfo) / 8;
1379 PadAfter += Width;
1380 continue;
1381 }
1382 // Check for registers that are remapped (for a Thumb1 prologue that
1383 // saves high registers).
1384 Register Reg = MO.getReg();
1385 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: Reg))
1386 Reg = RemappedReg;
1387 RegList.push_back(Elt: Reg);
1388 }
1389 break;
1390 case ARM::STR_PRE_IMM:
1391 case ARM::STR_PRE_REG:
1392 case ARM::t2STR_PRE:
1393 assert(MI->getOperand(2).getReg() == ARM::SP &&
1394 "Only stack pointer as a source reg is supported");
1395 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1396 SrcReg = RemappedReg;
1397
1398 RegList.push_back(Elt: SrcReg);
1399 break;
1400 case ARM::t2STRD_PRE:
1401 assert(MI->getOperand(3).getReg() == ARM::SP &&
1402 "Only stack pointer as a source reg is supported");
1403 SrcReg = MI->getOperand(i: 1).getReg();
1404 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1405 SrcReg = RemappedReg;
1406 RegList.push_back(Elt: SrcReg);
1407 SrcReg = MI->getOperand(i: 2).getReg();
1408 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1409 SrcReg = RemappedReg;
1410 RegList.push_back(Elt: SrcReg);
1411 PadBefore = -MI->getOperand(i: 4).getImm() - 8;
1412 break;
1413 }
1414 if (MAI.getExceptionHandlingType() == ExceptionHandling::ARM) {
1415 if (PadBefore)
1416 ATS.emitPad(Offset: PadBefore);
1417 ATS.emitRegSave(RegList, isVector: Opc == ARM::VSTMDDB_UPD);
1418 // Account for the SP adjustment, folded into the push.
1419 if (PadAfter)
1420 ATS.emitPad(Offset: PadAfter);
1421 }
1422 } else {
1423 // Changes of stack / frame pointer.
1424 if (SrcReg == ARM::SP) {
1425 int64_t Offset = 0;
1426 switch (Opc) {
1427 default:
1428 MI->print(OS&: errs());
1429 llvm_unreachable("Unsupported opcode for unwinding information");
1430 case ARM::tLDRspi:
1431 // Used to restore LR in a prologue which uses it as a temporary, has
1432 // no effect on unwind tables.
1433 return;
1434 case ARM::MOVr:
1435 case ARM::tMOVr:
1436 Offset = 0;
1437 break;
1438 case ARM::ADDri:
1439 case ARM::t2ADDri:
1440 case ARM::t2ADDri12:
1441 case ARM::t2ADDspImm:
1442 case ARM::t2ADDspImm12:
1443 Offset = -MI->getOperand(i: 2).getImm();
1444 break;
1445 case ARM::SUBri:
1446 case ARM::t2SUBri:
1447 case ARM::t2SUBri12:
1448 case ARM::t2SUBspImm:
1449 case ARM::t2SUBspImm12:
1450 Offset = MI->getOperand(i: 2).getImm();
1451 break;
1452 case ARM::tSUBspi:
1453 Offset = MI->getOperand(i: 2).getImm()*4;
1454 break;
1455 case ARM::tADDspi:
1456 case ARM::tADDrSPi:
1457 Offset = -MI->getOperand(i: 2).getImm()*4;
1458 break;
1459 case ARM::tADDhirr:
1460 Offset =
1461 -AFI->EHPrologueOffsetInRegs.lookup(Val: MI->getOperand(i: 2).getReg());
1462 break;
1463 }
1464
1465 if (MAI.getExceptionHandlingType() == ExceptionHandling::ARM) {
1466 if (DstReg == FramePtr && FramePtr != ARM::SP)
1467 // Set-up of the frame pointer. Positive values correspond to "add"
1468 // instruction.
1469 ATS.emitSetFP(FpReg: FramePtr, SpReg: ARM::SP, Offset: -Offset);
1470 else if (DstReg == ARM::SP) {
1471 // Change of SP by an offset. Positive values correspond to "sub"
1472 // instruction.
1473 ATS.emitPad(Offset);
1474 } else {
1475 // Move of SP to a register. Positive values correspond to an "add"
1476 // instruction.
1477 ATS.emitMovSP(Reg: DstReg, Offset: -Offset);
1478 }
1479 }
1480 } else if (DstReg == ARM::SP) {
1481 MI->print(OS&: errs());
1482 llvm_unreachable("Unsupported opcode for unwinding information");
1483 } else {
1484 int64_t Offset = 0;
1485 switch (Opc) {
1486 case ARM::tMOVr:
1487 // If a Thumb1 function spills r8-r11, we copy the values to low
1488 // registers before pushing them. Record the copy so we can emit the
1489 // correct ".save" later.
1490 AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1491 break;
1492 case ARM::VMRS:
1493 case ARM::VMRS_FPEXC:
1494 // If a function spills FPSCR or FPEXC, we copy the values to low
1495 // registers before pushing them. However, we can't issue annotations
1496 // for FP status registers because ".save" requires GPR registers, and
1497 // ".vsave" requires DPR registers, so don't record the copy and simply
1498 // emit annotations for the source registers used for the store.
1499 break;
1500 case ARM::tLDRpci: {
1501 // Grab the constpool index and check, whether it corresponds to
1502 // original or cloned constpool entry.
1503 unsigned CPI = MI->getOperand(i: 1).getIndex();
1504 const MachineConstantPool *MCP = MF.getConstantPool();
1505 if (CPI >= MCP->getConstants().size())
1506 CPI = AFI->getOriginalCPIdx(CloneIdx: CPI);
1507 assert(CPI != -1U && "Invalid constpool index");
1508
1509 // Derive the actual offset.
1510 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1511 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1512 Offset = cast<ConstantInt>(Val: CPE.Val.ConstVal)->getSExtValue();
1513 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1514 break;
1515 }
1516 case ARM::t2MOVi16:
1517 Offset = MI->getOperand(i: 1).getImm();
1518 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1519 break;
1520 case ARM::t2MOVTi16:
1521 Offset = MI->getOperand(i: 2).getImm();
1522 AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1523 break;
1524 case ARM::tMOVi8:
1525 Offset = MI->getOperand(i: 2).getImm();
1526 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1527 break;
1528 case ARM::tLSLri:
1529 assert(MI->getOperand(3).getImm() == 8 &&
1530 "The shift amount is not equal to 8");
1531 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1532 "The source register is not equal to the destination register");
1533 AFI->EHPrologueOffsetInRegs[DstReg] <<= 8;
1534 break;
1535 case ARM::tADDi8:
1536 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1537 "The source register is not equal to the destination register");
1538 Offset = MI->getOperand(i: 3).getImm();
1539 AFI->EHPrologueOffsetInRegs[DstReg] += Offset;
1540 break;
1541 case ARM::t2PAC:
1542 case ARM::t2PACBTI:
1543 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1544 break;
1545 default:
1546 MI->print(OS&: errs());
1547 llvm_unreachable("Unsupported opcode for unwinding information");
1548 }
1549 }
1550 }
1551}
1552
1553// Simple pseudo-instructions have their lowering (with expansion to real
1554// instructions) auto-generated.
1555#include "ARMGenMCPseudoLowering.inc"
1556
1557// Helper function to check if a register is live (used as an implicit operand)
1558// in the given call instruction.
1559static bool isRegisterLiveInCall(const MachineInstr &Call, MCRegister Reg) {
1560 for (const MachineOperand &MO : Call.implicit_operands()) {
1561 if (MO.isReg() && MO.getReg() == Reg && MO.isUse()) {
1562 return true;
1563 }
1564 }
1565 return false;
1566}
1567
1568void ARMAsmPrinter::EmitKCFI_CHECK_ARM32(Register AddrReg, int64_t Type,
1569 const MachineInstr &Call,
1570 int64_t PrefixNops) {
1571 // Choose scratch register: r12 primary, r3 if target is r12.
1572 unsigned ScratchReg = ARM::R12;
1573 if (AddrReg == ARM::R12) {
1574 ScratchReg = ARM::R3;
1575 }
1576
1577 // Calculate ESR for ARM mode (16-bit): 0x8000 | (scratch_reg << 5) | addr_reg
1578 // Note: scratch_reg is always 0x1F since the EOR sequence clobbers it.
1579 const ARMBaseRegisterInfo *TRI = static_cast<const ARMBaseRegisterInfo *>(
1580 MF->getSubtarget().getRegisterInfo());
1581 unsigned AddrIndex = TRI->getEncodingValue(Reg: AddrReg);
1582 unsigned ESR = 0x8000 | (31 << 5) | (AddrIndex & 31);
1583
1584 // Check if r3 is live and needs to be spilled.
1585 bool NeedSpillR3 =
1586 (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, Reg: ARM::R3);
1587
1588 // If we need to spill r3, push it first.
1589 if (NeedSpillR3) {
1590 // push {r3}
1591 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::STMDB_UPD)
1592 .addReg(Reg: ARM::SP)
1593 .addReg(Reg: ARM::SP)
1594 .addImm(Val: ARMCC::AL)
1595 .addReg(Reg: 0)
1596 .addReg(Reg: ARM::R3));
1597 }
1598
1599 // Clear bit 0 of target address to handle Thumb function pointers.
1600 // In 32-bit ARM, function pointers may have the low bit set to indicate
1601 // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later).
1602 // We need to clear it to avoid an alignment fault when loading.
1603 // bic scratch, target, #1
1604 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::BICri)
1605 .addReg(Reg: ScratchReg)
1606 .addReg(Reg: AddrReg)
1607 .addImm(Val: 1)
1608 .addImm(Val: ARMCC::AL)
1609 .addReg(Reg: 0)
1610 .addReg(Reg: 0));
1611
1612 // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)]
1613 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
1614 .addReg(Reg: ScratchReg)
1615 .addReg(Reg: ScratchReg)
1616 .addImm(Val: -(PrefixNops * 4 + 4))
1617 .addImm(Val: ARMCC::AL)
1618 .addReg(Reg: 0));
1619
1620 // Each EOR instruction XORs one byte of the type, shifted to its position.
1621 for (int i = 0; i < 4; i++) {
1622 uint8_t byte = (Type >> (i * 8)) & 0xFF;
1623 uint32_t imm = byte << (i * 8);
1624 bool isLast = (i == 3);
1625
1626 // Encode as ARM modified immediate.
1627 int SOImmVal = ARM_AM::getSOImmVal(Arg: imm);
1628 assert(SOImmVal != -1 &&
1629 "Cannot encode immediate as ARM modified immediate");
1630
1631 // eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
1632 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::EORri)
1633 .addReg(Reg: ScratchReg)
1634 .addReg(Reg: ScratchReg)
1635 .addImm(Val: SOImmVal)
1636 .addImm(Val: ARMCC::AL)
1637 .addReg(Reg: 0)
1638 .addReg(Reg: isLast ? ARM::CPSR : Register()));
1639 }
1640
1641 // If we spilled r3, restore it immediately after the comparison.
1642 // This must happen before the branch so r3 is valid on both paths.
1643 if (NeedSpillR3) {
1644 // pop {r3}
1645 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDMIA_UPD)
1646 .addReg(Reg: ARM::SP)
1647 .addReg(Reg: ARM::SP)
1648 .addImm(Val: ARMCC::AL)
1649 .addReg(Reg: 0)
1650 .addReg(Reg: ARM::R3));
1651 }
1652
1653 // beq .Lpass (branch if types match, i.e., scratch is zero)
1654 MCSymbol *Pass = OutContext.createTempSymbol();
1655 EmitToStreamer(S&: *OutStreamer,
1656 Inst: MCInstBuilder(ARM::Bcc)
1657 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1658 .addImm(Val: ARMCC::EQ)
1659 .addReg(Reg: ARM::CPSR));
1660
1661 // udf #ESR (trap with encoded diagnostic)
1662 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::UDF).addImm(Val: ESR));
1663
1664 OutStreamer->emitLabel(Symbol: Pass);
1665}
1666
1667void ARMAsmPrinter::EmitKCFI_CHECK_Thumb2(Register AddrReg, int64_t Type,
1668 const MachineInstr &Call,
1669 int64_t PrefixNops) {
1670 // Choose scratch register: r12 primary, r3 if target is r12.
1671 unsigned ScratchReg = ARM::R12;
1672 if (AddrReg == ARM::R12) {
1673 ScratchReg = ARM::R3;
1674 }
1675
1676 // Calculate ESR for Thumb mode (8-bit): 0x80 | addr_reg
1677 // Bit 7: KCFI trap indicator
1678 // Bits 6-5: Reserved
1679 // Bits 4-0: Address register encoding
1680 const ARMBaseRegisterInfo *TRI = static_cast<const ARMBaseRegisterInfo *>(
1681 MF->getSubtarget().getRegisterInfo());
1682 unsigned AddrIndex = TRI->getEncodingValue(Reg: AddrReg);
1683 unsigned ESR = 0x80 | (AddrIndex & 0x1F);
1684
1685 // Check if r3 is live and needs to be spilled.
1686 bool NeedSpillR3 =
1687 (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, Reg: ARM::R3);
1688
1689 // If we need to spill r3, push it first.
1690 if (NeedSpillR3) {
1691 // push {r3}
1692 EmitToStreamer(
1693 S&: *OutStreamer,
1694 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1695 }
1696
1697 // Clear bit 0 of target address to handle Thumb function pointers.
1698 // In 32-bit ARM, function pointers may have the low bit set to indicate
1699 // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later).
1700 // We need to clear it to avoid an alignment fault when loading.
1701 // bic scratch, target, #1
1702 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2BICri)
1703 .addReg(Reg: ScratchReg)
1704 .addReg(Reg: AddrReg)
1705 .addImm(Val: 1)
1706 .addImm(Val: ARMCC::AL)
1707 .addReg(Reg: 0)
1708 .addReg(Reg: 0));
1709
1710 // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)]
1711 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi8)
1712 .addReg(Reg: ScratchReg)
1713 .addReg(Reg: ScratchReg)
1714 .addImm(Val: -(PrefixNops * 4 + 4))
1715 .addImm(Val: ARMCC::AL)
1716 .addReg(Reg: 0));
1717
1718 // Each EOR instruction XORs one byte of the type, shifted to its position.
1719 for (int i = 0; i < 4; i++) {
1720 uint8_t byte = (Type >> (i * 8)) & 0xFF;
1721 uint32_t imm = byte << (i * 8);
1722 bool isLast = (i == 3);
1723
1724 // Verify the immediate can be encoded as Thumb2 modified immediate.
1725 assert(ARM_AM::getT2SOImmVal(imm) != -1 &&
1726 "Cannot encode immediate as Thumb2 modified immediate");
1727
1728 // eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
1729 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2EORri)
1730 .addReg(Reg: ScratchReg)
1731 .addReg(Reg: ScratchReg)
1732 .addImm(Val: imm)
1733 .addImm(Val: ARMCC::AL)
1734 .addReg(Reg: 0)
1735 .addReg(Reg: isLast ? ARM::CPSR : Register()));
1736 }
1737
1738 // If we spilled r3, restore it immediately after the comparison.
1739 // This must happen before the branch so r3 is valid on both paths.
1740 if (NeedSpillR3) {
1741 // pop {r3}
1742 EmitToStreamer(
1743 S&: *OutStreamer,
1744 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1745 }
1746
1747 // beq .Lpass (branch if types match, i.e., scratch is zero)
1748 MCSymbol *Pass = OutContext.createTempSymbol();
1749 EmitToStreamer(S&: *OutStreamer,
1750 Inst: MCInstBuilder(ARM::t2Bcc)
1751 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1752 .addImm(Val: ARMCC::EQ)
1753 .addReg(Reg: ARM::CPSR));
1754
1755 // udf #ESR (trap with encoded diagnostic)
1756 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tUDF).addImm(Val: ESR));
1757
1758 OutStreamer->emitLabel(Symbol: Pass);
1759}
1760
1761void ARMAsmPrinter::EmitKCFI_CHECK_Thumb1(Register AddrReg, int64_t Type,
1762 const MachineInstr &Call,
1763 int64_t PrefixNops) {
1764 // For Thumb1, use R2 unconditionally as scratch register (a low register
1765 // required for tLDRi). R3 is used for building the type hash.
1766 unsigned ScratchReg = ARM::R2;
1767 unsigned TempReg = ARM::R3;
1768
1769 // Check if r3 is live and needs to be spilled.
1770 bool NeedSpillR3 = isRegisterLiveInCall(Call, Reg: ARM::R3);
1771
1772 // Spill r3 if needed
1773 if (NeedSpillR3) {
1774 EmitToStreamer(
1775 S&: *OutStreamer,
1776 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1777 }
1778
1779 // Check if r2 is live and needs to be spilled.
1780 bool NeedSpillR2 = isRegisterLiveInCall(Call, Reg: ARM::R2);
1781
1782 // Push R2 if it's live
1783 if (NeedSpillR2) {
1784 EmitToStreamer(
1785 S&: *OutStreamer,
1786 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R2));
1787 }
1788
1789 // Clear bit 0 from target address
1790 // TempReg (R3) is used first as helper for BIC, then later for building type
1791 // hash.
1792
1793 // movs temp, #1
1794 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
1795 .addReg(Reg: TempReg)
1796 .addReg(Reg: ARM::CPSR)
1797 .addImm(Val: 1)
1798 .addImm(Val: ARMCC::AL)
1799 .addReg(Reg: 0));
1800
1801 // mov scratch, target
1802 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
1803 .addReg(Reg: ScratchReg)
1804 .addReg(Reg: AddrReg)
1805 .addImm(Val: ARMCC::AL));
1806
1807 // bics scratch, temp (scratch = scratch & ~temp)
1808 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBIC)
1809 .addReg(Reg: ScratchReg)
1810 .addReg(Reg: ARM::CPSR)
1811 .addReg(Reg: ScratchReg)
1812 .addReg(Reg: TempReg)
1813 .addImm(Val: ARMCC::AL)
1814 .addReg(Reg: 0));
1815
1816 // Load type hash. Thumb1 doesn't support negative offsets, so subtract.
1817 int offset = PrefixNops * 4 + 4;
1818
1819 // subs scratch, #offset
1820 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tSUBi8)
1821 .addReg(Reg: ScratchReg)
1822 .addReg(Reg: ARM::CPSR)
1823 .addReg(Reg: ScratchReg)
1824 .addImm(Val: offset)
1825 .addImm(Val: ARMCC::AL)
1826 .addReg(Reg: 0));
1827
1828 // ldr scratch, [scratch, #0]
1829 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
1830 .addReg(Reg: ScratchReg)
1831 .addReg(Reg: ScratchReg)
1832 .addImm(Val: 0)
1833 .addImm(Val: ARMCC::AL)
1834 .addReg(Reg: 0));
1835
1836 // Load expected type inline (instead of EOR sequence)
1837 //
1838 // This creates the 32-bit value byte-by-byte in the temp register:
1839 // movs temp, #byte3 (high byte)
1840 // lsls temp, temp, #8
1841 // adds temp, #byte2
1842 // lsls temp, temp, #8
1843 // adds temp, #byte1
1844 // lsls temp, temp, #8
1845 // adds temp, #byte0 (low byte)
1846
1847 uint8_t byte0 = (Type >> 0) & 0xFF;
1848 uint8_t byte1 = (Type >> 8) & 0xFF;
1849 uint8_t byte2 = (Type >> 16) & 0xFF;
1850 uint8_t byte3 = (Type >> 24) & 0xFF;
1851
1852 // movs temp, #byte3 (start with high byte)
1853 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
1854 .addReg(Reg: TempReg)
1855 .addReg(Reg: ARM::CPSR)
1856 .addImm(Val: byte3)
1857 .addImm(Val: ARMCC::AL)
1858 .addReg(Reg: 0));
1859
1860 // lsls temp, temp, #8
1861 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1862 .addReg(Reg: TempReg)
1863 .addReg(Reg: ARM::CPSR)
1864 .addReg(Reg: TempReg)
1865 .addImm(Val: 8)
1866 .addImm(Val: ARMCC::AL)
1867 .addReg(Reg: 0));
1868
1869 // adds temp, #byte2
1870 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1871 .addReg(Reg: TempReg)
1872 .addReg(Reg: ARM::CPSR)
1873 .addReg(Reg: TempReg)
1874 .addImm(Val: byte2)
1875 .addImm(Val: ARMCC::AL)
1876 .addReg(Reg: 0));
1877
1878 // lsls temp, temp, #8
1879 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1880 .addReg(Reg: TempReg)
1881 .addReg(Reg: ARM::CPSR)
1882 .addReg(Reg: TempReg)
1883 .addImm(Val: 8)
1884 .addImm(Val: ARMCC::AL)
1885 .addReg(Reg: 0));
1886
1887 // adds temp, #byte1
1888 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1889 .addReg(Reg: TempReg)
1890 .addReg(Reg: ARM::CPSR)
1891 .addReg(Reg: TempReg)
1892 .addImm(Val: byte1)
1893 .addImm(Val: ARMCC::AL)
1894 .addReg(Reg: 0));
1895
1896 // lsls temp, temp, #8
1897 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1898 .addReg(Reg: TempReg)
1899 .addReg(Reg: ARM::CPSR)
1900 .addReg(Reg: TempReg)
1901 .addImm(Val: 8)
1902 .addImm(Val: ARMCC::AL)
1903 .addReg(Reg: 0));
1904
1905 // adds temp, #byte0 (low byte)
1906 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1907 .addReg(Reg: TempReg)
1908 .addReg(Reg: ARM::CPSR)
1909 .addReg(Reg: TempReg)
1910 .addImm(Val: byte0)
1911 .addImm(Val: ARMCC::AL)
1912 .addReg(Reg: 0));
1913
1914 // cmp scratch, temp
1915 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tCMPr)
1916 .addReg(Reg: ScratchReg)
1917 .addReg(Reg: TempReg)
1918 .addImm(Val: ARMCC::AL)
1919 .addReg(Reg: 0));
1920
1921 // Restore registers if spilled (pop in reverse order of push: R2, then R3)
1922 if (NeedSpillR2) {
1923 // pop {r2}
1924 EmitToStreamer(
1925 S&: *OutStreamer,
1926 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R2));
1927 }
1928
1929 // Restore r3 if spilled
1930 if (NeedSpillR3) {
1931 // pop {r3}
1932 EmitToStreamer(
1933 S&: *OutStreamer,
1934 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1935 }
1936
1937 // beq .Lpass (branch if types match, i.e., scratch == temp)
1938 MCSymbol *Pass = OutContext.createTempSymbol();
1939 EmitToStreamer(S&: *OutStreamer,
1940 Inst: MCInstBuilder(ARM::tBcc)
1941 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1942 .addImm(Val: ARMCC::EQ)
1943 .addReg(Reg: ARM::CPSR));
1944
1945 // bkpt #0 (trap with encoded diagnostic)
1946 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBKPT).addImm(Val: 0));
1947
1948 OutStreamer->emitLabel(Symbol: Pass);
1949}
1950
1951void ARMAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
1952 Register AddrReg = MI.getOperand(i: 0).getReg();
1953 const int64_t Type = MI.getOperand(i: 1).getImm();
1954
1955 // Get the call instruction that follows this KCFI_CHECK.
1956 assert(std::next(MI.getIterator())->isCall() &&
1957 "KCFI_CHECK not followed by a call instruction");
1958 const MachineInstr &Call = *std::next(x: MI.getIterator());
1959
1960 // Adjust the offset for patchable-function-prefix.
1961 int64_t PrefixNops = MI.getMF()->getFunction().getFnAttributeAsParsedInteger(
1962 Kind: "patchable-function-prefix");
1963
1964 // Emit the appropriate instruction sequence based on the opcode variant.
1965 switch (MI.getOpcode()) {
1966 case ARM::KCFI_CHECK_ARM:
1967 EmitKCFI_CHECK_ARM32(AddrReg, Type, Call, PrefixNops);
1968 break;
1969 case ARM::KCFI_CHECK_Thumb2:
1970 EmitKCFI_CHECK_Thumb2(AddrReg, Type, Call, PrefixNops);
1971 break;
1972 case ARM::KCFI_CHECK_Thumb1:
1973 EmitKCFI_CHECK_Thumb1(AddrReg, Type, Call, PrefixNops);
1974 break;
1975 default:
1976 llvm_unreachable("Unexpected KCFI_CHECK opcode");
1977 }
1978}
1979
1980void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
1981 ARM_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
1982 Features: getSubtargetInfo().getFeatureBits());
1983
1984 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1985 const DataLayout &DL = getDataLayout();
1986 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1987 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1988
1989 // If we just ended a constant pool, mark it as such.
1990 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1991 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1992 InConstantPool = false;
1993 }
1994
1995 // Emit unwinding stuff for frame-related instructions
1996 if (TM.getTargetTriple().isTargetEHABICompatible() &&
1997 MI->getFlag(Flag: MachineInstr::FrameSetup))
1998 EmitUnwindingInstruction(MI);
1999
2000 // Do any auto-generated pseudo lowerings.
2001 if (MCInst OutInst; lowerPseudoInstExpansion(MI, Inst&: OutInst)) {
2002 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
2003 return;
2004 }
2005
2006 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
2007 "Pseudo flag setting opcode should be expanded early");
2008
2009 // Check for manual lowerings.
2010 unsigned Opc = MI->getOpcode();
2011 switch (Opc) {
2012 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
2013 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
2014 case ARM::KCFI_CHECK_ARM:
2015 case ARM::KCFI_CHECK_Thumb2:
2016 case ARM::KCFI_CHECK_Thumb1:
2017 LowerKCFI_CHECK(MI: *MI);
2018 return;
2019 case ARM::LEApcrel:
2020 case ARM::tLEApcrel:
2021 case ARM::t2LEApcrel: {
2022 // FIXME: Need to also handle globals and externals
2023 MCSymbol *CPISymbol = GetCPISymbol(CPID: MI->getOperand(i: 1).getIndex());
2024 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(MI->getOpcode() ==
2025 ARM::t2LEApcrel ? ARM::t2ADR
2026 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
2027 : ARM::ADR))
2028 .addReg(Reg: MI->getOperand(i: 0).getReg())
2029 .addExpr(Val: MCSymbolRefExpr::create(Symbol: CPISymbol, Ctx&: OutContext))
2030 // Add predicate operands.
2031 .addImm(Val: MI->getOperand(i: 2).getImm())
2032 .addReg(Reg: MI->getOperand(i: 3).getReg()));
2033 return;
2034 }
2035 case ARM::LEApcrelJT:
2036 case ARM::tLEApcrelJT:
2037 case ARM::t2LEApcrelJT: {
2038 MCSymbol *JTIPICSymbol =
2039 GetARMJTIPICJumpTableLabel(uid: MI->getOperand(i: 1).getIndex());
2040 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(MI->getOpcode() ==
2041 ARM::t2LEApcrelJT ? ARM::t2ADR
2042 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
2043 : ARM::ADR))
2044 .addReg(Reg: MI->getOperand(i: 0).getReg())
2045 .addExpr(Val: MCSymbolRefExpr::create(Symbol: JTIPICSymbol, Ctx&: OutContext))
2046 // Add predicate operands.
2047 .addImm(Val: MI->getOperand(i: 2).getImm())
2048 .addReg(Reg: MI->getOperand(i: 3).getReg()));
2049 return;
2050 }
2051 // Darwin call instructions are just normal call instructions with different
2052 // clobber semantics (they clobber R9).
2053 case ARM::BX_CALL: {
2054 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2055 .addReg(Reg: ARM::LR)
2056 .addReg(Reg: ARM::PC)
2057 // Add predicate operands.
2058 .addImm(Val: ARMCC::AL)
2059 .addReg(Reg: 0)
2060 // Add 's' bit operand (always reg0 for this)
2061 .addReg(Reg: 0));
2062
2063 assert(STI.hasV4TOps() && "Expected V4TOps for BX call");
2064 EmitToStreamer(S&: *OutStreamer,
2065 Inst: MCInstBuilder(ARM::BX).addReg(Reg: MI->getOperand(i: 0).getReg()));
2066 return;
2067 }
2068 case ARM::tBX_CALL: {
2069 assert(!STI.hasV5TOps() && "Expected BLX to be selected for v5t+");
2070
2071 // On ARM v4t, when doing a call from thumb mode, we need to ensure
2072 // that the saved lr has its LSB set correctly (the arch doesn't
2073 // have blx).
2074 // So here we generate a bl to a small jump pad that does bx rN.
2075 // The jump pads are emitted after the function body.
2076
2077 Register TReg = MI->getOperand(i: 0).getReg();
2078 MCSymbol *TRegSym = nullptr;
2079 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
2080 if (TIP.first == TReg) {
2081 TRegSym = TIP.second;
2082 break;
2083 }
2084 }
2085
2086 if (!TRegSym) {
2087 TRegSym = OutContext.createTempSymbol();
2088 ThumbIndirectPads.push_back(Elt: std::make_pair(x&: TReg, y&: TRegSym));
2089 }
2090
2091 // Create a link-saving branch to the Reg Indirect Jump Pad.
2092 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBL)
2093 // Predicate comes first here.
2094 .addImm(Val: ARMCC::AL).addReg(Reg: 0)
2095 .addExpr(Val: MCSymbolRefExpr::create(Symbol: TRegSym, Ctx&: OutContext)));
2096 return;
2097 }
2098 case ARM::BMOVPCRX_CALL: {
2099 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2100 .addReg(Reg: ARM::LR)
2101 .addReg(Reg: ARM::PC)
2102 // Add predicate operands.
2103 .addImm(Val: ARMCC::AL)
2104 .addReg(Reg: 0)
2105 // Add 's' bit operand (always reg0 for this)
2106 .addReg(Reg: 0));
2107
2108 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2109 .addReg(Reg: ARM::PC)
2110 .addReg(Reg: MI->getOperand(i: 0).getReg())
2111 // Add predicate operands.
2112 .addImm(Val: ARMCC::AL)
2113 .addReg(Reg: 0)
2114 // Add 's' bit operand (always reg0 for this)
2115 .addReg(Reg: 0));
2116 return;
2117 }
2118 case ARM::BMOVPCB_CALL: {
2119 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2120 .addReg(Reg: ARM::LR)
2121 .addReg(Reg: ARM::PC)
2122 // Add predicate operands.
2123 .addImm(Val: ARMCC::AL)
2124 .addReg(Reg: 0)
2125 // Add 's' bit operand (always reg0 for this)
2126 .addReg(Reg: 0));
2127
2128 const MachineOperand &Op = MI->getOperand(i: 0);
2129 const GlobalValue *GV = Op.getGlobal();
2130 const unsigned TF = Op.getTargetFlags();
2131 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2132 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2133 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::Bcc)
2134 .addExpr(Val: GVSymExpr)
2135 // Add predicate operands.
2136 .addImm(Val: ARMCC::AL)
2137 .addReg(Reg: 0));
2138 return;
2139 }
2140 case ARM::MOVi16_ga_pcrel:
2141 case ARM::t2MOVi16_ga_pcrel: {
2142 MCInst TmpInst;
2143 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
2144 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2145
2146 unsigned TF = MI->getOperand(i: 1).getTargetFlags();
2147 const GlobalValue *GV = MI->getOperand(i: 1).getGlobal();
2148 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2149 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2150
2151 MCSymbol *LabelSym =
2152 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2153 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext);
2154 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(Symbol: LabelSym, Ctx&: OutContext);
2155 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
2156 const MCExpr *PCRelExpr = ARM::createLower16(
2157 Expr: MCBinaryExpr::createSub(
2158 LHS: GVSymExpr,
2159 RHS: MCBinaryExpr::createAdd(LHS: LabelSymExpr,
2160 RHS: MCConstantExpr::create(Value: PCAdj, Ctx&: OutContext),
2161 Ctx&: OutContext),
2162 Ctx&: OutContext),
2163 Ctx&: OutContext);
2164 TmpInst.addOperand(Op: MCOperand::createExpr(Val: PCRelExpr));
2165
2166 // Add predicate operands.
2167 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2168 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2169 // Add 's' bit operand (always reg0 for this)
2170 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2171 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2172 return;
2173 }
2174 case ARM::MOVTi16_ga_pcrel:
2175 case ARM::t2MOVTi16_ga_pcrel: {
2176 MCInst TmpInst;
2177 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
2178 ? ARM::MOVTi16 : ARM::t2MOVTi16);
2179 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2180 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 1).getReg()));
2181
2182 unsigned TF = MI->getOperand(i: 2).getTargetFlags();
2183 const GlobalValue *GV = MI->getOperand(i: 2).getGlobal();
2184 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2185 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2186
2187 MCSymbol *LabelSym =
2188 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2189 LabelId: MI->getOperand(i: 3).getImm(), Ctx&: OutContext);
2190 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(Symbol: LabelSym, Ctx&: OutContext);
2191 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
2192 const MCExpr *PCRelExpr = ARM::createUpper16(
2193 Expr: MCBinaryExpr::createSub(
2194 LHS: GVSymExpr,
2195 RHS: MCBinaryExpr::createAdd(LHS: LabelSymExpr,
2196 RHS: MCConstantExpr::create(Value: PCAdj, Ctx&: OutContext),
2197 Ctx&: OutContext),
2198 Ctx&: OutContext),
2199 Ctx&: OutContext);
2200 TmpInst.addOperand(Op: MCOperand::createExpr(Val: PCRelExpr));
2201 // Add predicate operands.
2202 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2203 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2204 // Add 's' bit operand (always reg0 for this)
2205 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2206 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2207 return;
2208 }
2209 case ARM::t2BFi:
2210 case ARM::t2BFic:
2211 case ARM::t2BFLi:
2212 case ARM::t2BFr:
2213 case ARM::t2BFLr: {
2214 // This is a Branch Future instruction.
2215
2216 const MCExpr *BranchLabel = MCSymbolRefExpr::create(
2217 Symbol: getBFLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2218 LabelId: MI->getOperand(i: 0).getIndex(), Ctx&: OutContext),
2219 Ctx&: OutContext);
2220
2221 auto MCInst = MCInstBuilder(Opc).addExpr(Val: BranchLabel);
2222 if (MI->getOperand(i: 1).isReg()) {
2223 // For BFr/BFLr
2224 MCInst.addReg(Reg: MI->getOperand(i: 1).getReg());
2225 } else {
2226 // For BFi/BFLi/BFic
2227 const MCExpr *BranchTarget;
2228 if (MI->getOperand(i: 1).isMBB())
2229 BranchTarget = MCSymbolRefExpr::create(
2230 Symbol: MI->getOperand(i: 1).getMBB()->getSymbol(), Ctx&: OutContext);
2231 else if (MI->getOperand(i: 1).isGlobal()) {
2232 const GlobalValue *GV = MI->getOperand(i: 1).getGlobal();
2233 BranchTarget = MCSymbolRefExpr::create(
2234 Symbol: GetARMGVSymbol(GV, TargetFlags: MI->getOperand(i: 1).getTargetFlags()), Ctx&: OutContext);
2235 } else if (MI->getOperand(i: 1).isSymbol()) {
2236 BranchTarget = MCSymbolRefExpr::create(
2237 Symbol: GetExternalSymbolSymbol(Sym: MI->getOperand(i: 1).getSymbolName()),
2238 Ctx&: OutContext);
2239 } else
2240 llvm_unreachable("Unhandled operand kind in Branch Future instruction");
2241
2242 MCInst.addExpr(Val: BranchTarget);
2243 }
2244
2245 if (Opc == ARM::t2BFic) {
2246 const MCExpr *ElseLabel = MCSymbolRefExpr::create(
2247 Symbol: getBFLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2248 LabelId: MI->getOperand(i: 2).getIndex(), Ctx&: OutContext),
2249 Ctx&: OutContext);
2250 MCInst.addExpr(Val: ElseLabel);
2251 MCInst.addImm(Val: MI->getOperand(i: 3).getImm());
2252 } else {
2253 MCInst.addImm(Val: MI->getOperand(i: 2).getImm())
2254 .addReg(Reg: MI->getOperand(i: 3).getReg());
2255 }
2256
2257 EmitToStreamer(S&: *OutStreamer, Inst: MCInst);
2258 return;
2259 }
2260 case ARM::t2BF_LabelPseudo: {
2261 // This is a pseudo op for a label used by a branch future instruction
2262
2263 // Emit the label.
2264 OutStreamer->emitLabel(
2265 Symbol: getBFLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2266 LabelId: MI->getOperand(i: 0).getIndex(), Ctx&: OutContext));
2267 return;
2268 }
2269 case ARM::tPICADD: {
2270 // This is a pseudo op for a label + instruction sequence, which looks like:
2271 // LPC0:
2272 // add r0, pc
2273 // This adds the address of LPC0 to r0.
2274
2275 // Emit the label.
2276 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getInternalSymbolPrefix(),
2277 FunctionNumber: getFunctionNumber(),
2278 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2279
2280 // Form and emit the add.
2281 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2282 .addReg(Reg: MI->getOperand(i: 0).getReg())
2283 .addReg(Reg: MI->getOperand(i: 0).getReg())
2284 .addReg(Reg: ARM::PC)
2285 // Add predicate operands.
2286 .addImm(Val: ARMCC::AL)
2287 .addReg(Reg: 0));
2288 return;
2289 }
2290 case ARM::PICADD: {
2291 // This is a pseudo op for a label + instruction sequence, which looks like:
2292 // LPC0:
2293 // add r0, pc, r0
2294 // This adds the address of LPC0 to r0.
2295
2296 // Emit the label.
2297 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getInternalSymbolPrefix(),
2298 FunctionNumber: getFunctionNumber(),
2299 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2300
2301 // Form and emit the add.
2302 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDrr)
2303 .addReg(Reg: MI->getOperand(i: 0).getReg())
2304 .addReg(Reg: ARM::PC)
2305 .addReg(Reg: MI->getOperand(i: 1).getReg())
2306 // Add predicate operands.
2307 .addImm(Val: MI->getOperand(i: 3).getImm())
2308 .addReg(Reg: MI->getOperand(i: 4).getReg())
2309 // Add 's' bit operand (always reg0 for this)
2310 .addReg(Reg: 0));
2311 return;
2312 }
2313 case ARM::PICSTR:
2314 case ARM::PICSTRB:
2315 case ARM::PICSTRH:
2316 case ARM::PICLDR:
2317 case ARM::PICLDRB:
2318 case ARM::PICLDRH:
2319 case ARM::PICLDRSB:
2320 case ARM::PICLDRSH: {
2321 // This is a pseudo op for a label + instruction sequence, which looks like:
2322 // LPC0:
2323 // OP r0, [pc, r0]
2324 // The LCP0 label is referenced by a constant pool entry in order to get
2325 // a PC-relative address at the ldr instruction.
2326
2327 // Emit the label.
2328 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getInternalSymbolPrefix(),
2329 FunctionNumber: getFunctionNumber(),
2330 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2331
2332 // Form and emit the load
2333 unsigned Opcode;
2334 switch (MI->getOpcode()) {
2335 default:
2336 llvm_unreachable("Unexpected opcode!");
2337 case ARM::PICSTR: Opcode = ARM::STRrs; break;
2338 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
2339 case ARM::PICSTRH: Opcode = ARM::STRH; break;
2340 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
2341 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
2342 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
2343 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
2344 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
2345 }
2346 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opcode)
2347 .addReg(Reg: MI->getOperand(i: 0).getReg())
2348 .addReg(Reg: ARM::PC)
2349 .addReg(Reg: MI->getOperand(i: 1).getReg())
2350 .addImm(Val: 0)
2351 // Add predicate operands.
2352 .addImm(Val: MI->getOperand(i: 3).getImm())
2353 .addReg(Reg: MI->getOperand(i: 4).getReg()));
2354
2355 return;
2356 }
2357 case ARM::CONSTPOOL_ENTRY: {
2358 assert(!STI.genExecuteOnly() &&
2359 "execute-only should not generate constant pools");
2360
2361 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
2362 /// in the function. The first operand is the ID# for this instruction, the
2363 /// second is the index into the MachineConstantPool that this is, the third
2364 /// is the size in bytes of this constant pool entry.
2365 /// The required alignment is specified on the basic block holding this MI.
2366 unsigned LabelId = (unsigned)MI->getOperand(i: 0).getImm();
2367 unsigned CPIdx = (unsigned)MI->getOperand(i: 1).getIndex();
2368
2369 // If this is the first entry of the pool, mark it.
2370 if (!InConstantPool) {
2371 OutStreamer->emitDataRegion(Kind: MCDR_DataRegion);
2372 InConstantPool = true;
2373 }
2374
2375 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: LabelId));
2376
2377 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
2378 if (MCPE.isMachineConstantPoolEntry())
2379 emitMachineConstantPoolValue(MCPV: MCPE.Val.MachineCPVal);
2380 else
2381 emitGlobalConstant(DL, CV: MCPE.Val.ConstVal);
2382 return;
2383 }
2384 case ARM::JUMPTABLE_ADDRS:
2385 emitJumpTableAddrs(MI);
2386 return;
2387 case ARM::JUMPTABLE_INSTS:
2388 emitJumpTableInsts(MI);
2389 return;
2390 case ARM::JUMPTABLE_TBB:
2391 case ARM::JUMPTABLE_TBH:
2392 emitJumpTableTBInst(MI, OffsetWidth: MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
2393 return;
2394 case ARM::t2BR_JT: {
2395 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2396 .addReg(Reg: ARM::PC)
2397 .addReg(Reg: MI->getOperand(i: 0).getReg())
2398 // Add predicate operands.
2399 .addImm(Val: ARMCC::AL)
2400 .addReg(Reg: 0));
2401 return;
2402 }
2403 case ARM::t2TBB_JT:
2404 case ARM::t2TBH_JT: {
2405 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
2406 // Lower and emit the PC label, then the instruction itself.
2407 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: MI->getOperand(i: 3).getImm()));
2408 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2409 .addReg(Reg: MI->getOperand(i: 0).getReg())
2410 .addReg(Reg: MI->getOperand(i: 1).getReg())
2411 // Add predicate operands.
2412 .addImm(Val: ARMCC::AL)
2413 .addReg(Reg: 0));
2414 return;
2415 }
2416 case ARM::tTBB_JT:
2417 case ARM::tTBH_JT: {
2418
2419 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
2420 Register Base = MI->getOperand(i: 0).getReg();
2421 Register Idx = MI->getOperand(i: 1).getReg();
2422 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
2423
2424 // Multiply up idx if necessary.
2425 if (!Is8Bit)
2426 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
2427 .addReg(Reg: Idx)
2428 .addReg(Reg: ARM::CPSR)
2429 .addReg(Reg: Idx)
2430 .addImm(Val: 1)
2431 // Add predicate operands.
2432 .addImm(Val: ARMCC::AL)
2433 .addReg(Reg: 0));
2434
2435 if (Base == ARM::PC) {
2436 // TBB [base, idx] =
2437 // ADDS idx, idx, base
2438 // LDRB idx, [idx, #4] ; or LDRH if TBH
2439 // LSLS idx, #1
2440 // ADDS pc, pc, idx
2441
2442 // When using PC as the base, it's important that there is no padding
2443 // between the last ADDS and the start of the jump table. The jump table
2444 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
2445 //
2446 // FIXME: Ideally we could vary the LDRB index based on the padding
2447 // between the sequence and jump table, however that relies on MCExprs
2448 // for load indexes which are currently not supported.
2449 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: getSubtargetInfo());
2450 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2451 .addReg(Reg: Idx)
2452 .addReg(Reg: Idx)
2453 .addReg(Reg: Base)
2454 // Add predicate operands.
2455 .addImm(Val: ARMCC::AL)
2456 .addReg(Reg: 0));
2457
2458 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
2459 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2460 .addReg(Reg: Idx)
2461 .addReg(Reg: Idx)
2462 .addImm(Val: Is8Bit ? 4 : 2)
2463 // Add predicate operands.
2464 .addImm(Val: ARMCC::AL)
2465 .addReg(Reg: 0));
2466 } else {
2467 // TBB [base, idx] =
2468 // LDRB idx, [base, idx] ; or LDRH if TBH
2469 // LSLS idx, #1
2470 // ADDS pc, pc, idx
2471
2472 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
2473 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2474 .addReg(Reg: Idx)
2475 .addReg(Reg: Base)
2476 .addReg(Reg: Idx)
2477 // Add predicate operands.
2478 .addImm(Val: ARMCC::AL)
2479 .addReg(Reg: 0));
2480 }
2481
2482 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
2483 .addReg(Reg: Idx)
2484 .addReg(Reg: ARM::CPSR)
2485 .addReg(Reg: Idx)
2486 .addImm(Val: 1)
2487 // Add predicate operands.
2488 .addImm(Val: ARMCC::AL)
2489 .addReg(Reg: 0));
2490
2491 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: MI->getOperand(i: 3).getImm()));
2492 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2493 .addReg(Reg: ARM::PC)
2494 .addReg(Reg: ARM::PC)
2495 .addReg(Reg: Idx)
2496 // Add predicate operands.
2497 .addImm(Val: ARMCC::AL)
2498 .addReg(Reg: 0));
2499 return;
2500 }
2501 case ARM::tBR_JTr:
2502 case ARM::BR_JTr: {
2503 // mov pc, target
2504 MCInst TmpInst;
2505 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
2506 ARM::MOVr : ARM::tMOVr;
2507 TmpInst.setOpcode(Opc);
2508 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2509 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2510 // Add predicate operands.
2511 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2512 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2513 // Add 's' bit operand (always reg0 for this)
2514 if (Opc == ARM::MOVr)
2515 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2516 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2517 return;
2518 }
2519 case ARM::BR_JTm_i12: {
2520 // ldr pc, target
2521 MCInst TmpInst;
2522 TmpInst.setOpcode(ARM::LDRi12);
2523 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2524 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2525 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI->getOperand(i: 2).getImm()));
2526 // Add predicate operands.
2527 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2528 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2529 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2530 return;
2531 }
2532 case ARM::BR_JTm_rs: {
2533 // ldr pc, target
2534 MCInst TmpInst;
2535 TmpInst.setOpcode(ARM::LDRrs);
2536 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2537 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2538 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 1).getReg()));
2539 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI->getOperand(i: 2).getImm()));
2540 // Add predicate operands.
2541 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2542 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2543 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2544 return;
2545 }
2546 case ARM::BR_JTadd: {
2547 // add pc, target, idx
2548 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDrr)
2549 .addReg(Reg: ARM::PC)
2550 .addReg(Reg: MI->getOperand(i: 0).getReg())
2551 .addReg(Reg: MI->getOperand(i: 1).getReg())
2552 // Add predicate operands.
2553 .addImm(Val: ARMCC::AL)
2554 .addReg(Reg: 0)
2555 // Add 's' bit operand (always reg0 for this)
2556 .addReg(Reg: 0));
2557 return;
2558 }
2559 case ARM::SPACE:
2560 OutStreamer->emitZeros(NumBytes: MI->getOperand(i: 1).getImm());
2561 return;
2562 case ARM::TRAP: {
2563 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2564 // FIXME: Remove this special case when they do.
2565 if (!TM.getTargetTriple().isOSBinFormatMachO()) {
2566 uint32_t Val = 0xe7ffdefeUL;
2567 OutStreamer->AddComment(T: "trap");
2568 ATS.emitInst(Inst: Val);
2569 return;
2570 }
2571 break;
2572 }
2573 case ARM::tTRAP: {
2574 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2575 // FIXME: Remove this special case when they do.
2576 if (!TM.getTargetTriple().isOSBinFormatMachO()) {
2577 uint16_t Val = 0xdefe;
2578 OutStreamer->AddComment(T: "trap");
2579 ATS.emitInst(Inst: Val, Suffix: 'n');
2580 return;
2581 }
2582 break;
2583 }
2584 case ARM::t2Int_eh_sjlj_setjmp:
2585 case ARM::t2Int_eh_sjlj_setjmp_nofp:
2586 case ARM::tInt_eh_sjlj_setjmp: {
2587 // Two incoming args: GPR:$src, GPR:$val
2588 // mov $val, pc
2589 // adds $val, #7
2590 // str $val, [$src, #4]
2591 // movs r0, #0
2592 // b LSJLJEH
2593 // movs r0, #1
2594 // LSJLJEH:
2595 Register SrcReg = MI->getOperand(i: 0).getReg();
2596 Register ValReg = MI->getOperand(i: 1).getReg();
2597 MCSymbol *Label = OutContext.createTempSymbol(Name: "SJLJEH");
2598 OutStreamer->AddComment(T: "eh_setjmp begin");
2599 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2600 .addReg(Reg: ValReg)
2601 .addReg(Reg: ARM::PC)
2602 // Predicate.
2603 .addImm(Val: ARMCC::AL)
2604 .addReg(Reg: 0));
2605
2606 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi3)
2607 .addReg(Reg: ValReg)
2608 // 's' bit operand
2609 .addReg(Reg: ARM::CPSR)
2610 .addReg(Reg: ValReg)
2611 .addImm(Val: 7)
2612 // Predicate.
2613 .addImm(Val: ARMCC::AL)
2614 .addReg(Reg: 0));
2615
2616 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tSTRi)
2617 .addReg(Reg: ValReg)
2618 .addReg(Reg: SrcReg)
2619 // The offset immediate is #4. The operand value is scaled by 4 for the
2620 // tSTR instruction.
2621 .addImm(Val: 1)
2622 // Predicate.
2623 .addImm(Val: ARMCC::AL)
2624 .addReg(Reg: 0));
2625
2626 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
2627 .addReg(Reg: ARM::R0)
2628 .addReg(Reg: ARM::CPSR)
2629 .addImm(Val: 0)
2630 // Predicate.
2631 .addImm(Val: ARMCC::AL)
2632 .addReg(Reg: 0));
2633
2634 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Symbol: Label, Ctx&: OutContext);
2635 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tB)
2636 .addExpr(Val: SymbolExpr)
2637 .addImm(Val: ARMCC::AL)
2638 .addReg(Reg: 0));
2639
2640 OutStreamer->AddComment(T: "eh_setjmp end");
2641 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
2642 .addReg(Reg: ARM::R0)
2643 .addReg(Reg: ARM::CPSR)
2644 .addImm(Val: 1)
2645 // Predicate.
2646 .addImm(Val: ARMCC::AL)
2647 .addReg(Reg: 0));
2648
2649 OutStreamer->emitLabel(Symbol: Label);
2650 return;
2651 }
2652
2653 case ARM::Int_eh_sjlj_setjmp_nofp:
2654 case ARM::Int_eh_sjlj_setjmp: {
2655 // Two incoming args: GPR:$src, GPR:$val
2656 // add $val, pc, #8
2657 // str $val, [$src, #+4]
2658 // mov r0, #0
2659 // add pc, pc, #0
2660 // mov r0, #1
2661 Register SrcReg = MI->getOperand(i: 0).getReg();
2662 Register ValReg = MI->getOperand(i: 1).getReg();
2663
2664 OutStreamer->AddComment(T: "eh_setjmp begin");
2665 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDri)
2666 .addReg(Reg: ValReg)
2667 .addReg(Reg: ARM::PC)
2668 .addImm(Val: 8)
2669 // Predicate.
2670 .addImm(Val: ARMCC::AL)
2671 .addReg(Reg: 0)
2672 // 's' bit operand (always reg0 for this).
2673 .addReg(Reg: 0));
2674
2675 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::STRi12)
2676 .addReg(Reg: ValReg)
2677 .addReg(Reg: SrcReg)
2678 .addImm(Val: 4)
2679 // Predicate.
2680 .addImm(Val: ARMCC::AL)
2681 .addReg(Reg: 0));
2682
2683 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVi)
2684 .addReg(Reg: ARM::R0)
2685 .addImm(Val: 0)
2686 // Predicate.
2687 .addImm(Val: ARMCC::AL)
2688 .addReg(Reg: 0)
2689 // 's' bit operand (always reg0 for this).
2690 .addReg(Reg: 0));
2691
2692 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDri)
2693 .addReg(Reg: ARM::PC)
2694 .addReg(Reg: ARM::PC)
2695 .addImm(Val: 0)
2696 // Predicate.
2697 .addImm(Val: ARMCC::AL)
2698 .addReg(Reg: 0)
2699 // 's' bit operand (always reg0 for this).
2700 .addReg(Reg: 0));
2701
2702 OutStreamer->AddComment(T: "eh_setjmp end");
2703 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVi)
2704 .addReg(Reg: ARM::R0)
2705 .addImm(Val: 1)
2706 // Predicate.
2707 .addImm(Val: ARMCC::AL)
2708 .addReg(Reg: 0)
2709 // 's' bit operand (always reg0 for this).
2710 .addReg(Reg: 0));
2711 return;
2712 }
2713 case ARM::Int_eh_sjlj_longjmp: {
2714 // ldr sp, [$src, #8]
2715 // ldr $scratch, [$src, #4]
2716 // ldr r7, [$src]
2717 // bx $scratch
2718 Register SrcReg = MI->getOperand(i: 0).getReg();
2719 Register ScratchReg = MI->getOperand(i: 1).getReg();
2720 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2721 .addReg(Reg: ARM::SP)
2722 .addReg(Reg: SrcReg)
2723 .addImm(Val: 8)
2724 // Predicate.
2725 .addImm(Val: ARMCC::AL)
2726 .addReg(Reg: 0));
2727
2728 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2729 .addReg(Reg: ScratchReg)
2730 .addReg(Reg: SrcReg)
2731 .addImm(Val: 4)
2732 // Predicate.
2733 .addImm(Val: ARMCC::AL)
2734 .addReg(Reg: 0));
2735
2736 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2737 // These platforms always use the same frame register
2738 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2739 .addReg(Reg: STI.getFramePointerReg())
2740 .addReg(Reg: SrcReg)
2741 .addImm(Val: 0)
2742 // Predicate.
2743 .addImm(Val: ARMCC::AL)
2744 .addReg(Reg: 0));
2745 } else {
2746 // If the calling code might use either R7 or R11 as
2747 // frame pointer register, restore it into both.
2748 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2749 .addReg(Reg: ARM::R7)
2750 .addReg(Reg: SrcReg)
2751 .addImm(Val: 0)
2752 // Predicate.
2753 .addImm(Val: ARMCC::AL)
2754 .addReg(Reg: 0));
2755 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2756 .addReg(Reg: ARM::R11)
2757 .addReg(Reg: SrcReg)
2758 .addImm(Val: 0)
2759 // Predicate.
2760 .addImm(Val: ARMCC::AL)
2761 .addReg(Reg: 0));
2762 }
2763
2764 assert(STI.hasV4TOps());
2765 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::BX)
2766 .addReg(Reg: ScratchReg)
2767 // Predicate.
2768 .addImm(Val: ARMCC::AL)
2769 .addReg(Reg: 0));
2770 return;
2771 }
2772 case ARM::tInt_eh_sjlj_longjmp: {
2773 // ldr $scratch, [$src, #8]
2774 // mov sp, $scratch
2775 // ldr $scratch, [$src, #4]
2776 // ldr r7, [$src]
2777 // bx $scratch
2778 Register SrcReg = MI->getOperand(i: 0).getReg();
2779 Register ScratchReg = MI->getOperand(i: 1).getReg();
2780
2781 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2782 .addReg(Reg: ScratchReg)
2783 .addReg(Reg: SrcReg)
2784 // The offset immediate is #8. The operand value is scaled by 4 for the
2785 // tLDR instruction.
2786 .addImm(Val: 2)
2787 // Predicate.
2788 .addImm(Val: ARMCC::AL)
2789 .addReg(Reg: 0));
2790
2791 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2792 .addReg(Reg: ARM::SP)
2793 .addReg(Reg: ScratchReg)
2794 // Predicate.
2795 .addImm(Val: ARMCC::AL)
2796 .addReg(Reg: 0));
2797
2798 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2799 .addReg(Reg: ScratchReg)
2800 .addReg(Reg: SrcReg)
2801 .addImm(Val: 1)
2802 // Predicate.
2803 .addImm(Val: ARMCC::AL)
2804 .addReg(Reg: 0));
2805
2806 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2807 // These platforms always use the same frame register
2808 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2809 .addReg(Reg: STI.getFramePointerReg())
2810 .addReg(Reg: SrcReg)
2811 .addImm(Val: 0)
2812 // Predicate.
2813 .addImm(Val: ARMCC::AL)
2814 .addReg(Reg: 0));
2815 } else {
2816 // If the calling code might use either R7 or R11 as
2817 // frame pointer register, restore it into both.
2818 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2819 .addReg(Reg: ARM::R7)
2820 .addReg(Reg: SrcReg)
2821 .addImm(Val: 0)
2822 // Predicate.
2823 .addImm(Val: ARMCC::AL)
2824 .addReg(Reg: 0));
2825 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2826 .addReg(Reg: ARM::R11)
2827 .addReg(Reg: SrcReg)
2828 .addImm(Val: 0)
2829 // Predicate.
2830 .addImm(Val: ARMCC::AL)
2831 .addReg(Reg: 0));
2832 }
2833
2834 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBX)
2835 .addReg(Reg: ScratchReg)
2836 // Predicate.
2837 .addImm(Val: ARMCC::AL)
2838 .addReg(Reg: 0));
2839 return;
2840 }
2841 case ARM::tInt_WIN_eh_sjlj_longjmp: {
2842 // ldr.w r11, [$src, #0]
2843 // ldr.w sp, [$src, #8]
2844 // ldr.w pc, [$src, #4]
2845
2846 Register SrcReg = MI->getOperand(i: 0).getReg();
2847
2848 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2849 .addReg(Reg: ARM::R11)
2850 .addReg(Reg: SrcReg)
2851 .addImm(Val: 0)
2852 // Predicate
2853 .addImm(Val: ARMCC::AL)
2854 .addReg(Reg: 0));
2855 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2856 .addReg(Reg: ARM::SP)
2857 .addReg(Reg: SrcReg)
2858 .addImm(Val: 8)
2859 // Predicate
2860 .addImm(Val: ARMCC::AL)
2861 .addReg(Reg: 0));
2862 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2863 .addReg(Reg: ARM::PC)
2864 .addReg(Reg: SrcReg)
2865 .addImm(Val: 4)
2866 // Predicate
2867 .addImm(Val: ARMCC::AL)
2868 .addReg(Reg: 0));
2869 return;
2870 }
2871 case ARM::PATCHABLE_FUNCTION_ENTER:
2872 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI);
2873 return;
2874 case ARM::PATCHABLE_FUNCTION_EXIT:
2875 LowerPATCHABLE_FUNCTION_EXIT(MI: *MI);
2876 return;
2877 case ARM::PATCHABLE_TAIL_CALL:
2878 LowerPATCHABLE_TAIL_CALL(MI: *MI);
2879 return;
2880 case ARM::SpeculationBarrierISBDSBEndBB: {
2881 // Print DSB SYS + ISB
2882 MCInst TmpInstDSB;
2883 TmpInstDSB.setOpcode(ARM::DSB);
2884 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2885 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstDSB);
2886 MCInst TmpInstISB;
2887 TmpInstISB.setOpcode(ARM::ISB);
2888 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2889 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstISB);
2890 return;
2891 }
2892 case ARM::t2SpeculationBarrierISBDSBEndBB: {
2893 // Print DSB SYS + ISB
2894 MCInst TmpInstDSB;
2895 TmpInstDSB.setOpcode(ARM::t2DSB);
2896 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2897 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2898 TmpInstDSB.addOperand(Op: MCOperand::createReg(Reg: 0));
2899 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstDSB);
2900 MCInst TmpInstISB;
2901 TmpInstISB.setOpcode(ARM::t2ISB);
2902 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2903 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2904 TmpInstISB.addOperand(Op: MCOperand::createReg(Reg: 0));
2905 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstISB);
2906 return;
2907 }
2908 case ARM::SpeculationBarrierSBEndBB: {
2909 // Print SB
2910 MCInst TmpInstSB;
2911 TmpInstSB.setOpcode(ARM::SB);
2912 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstSB);
2913 return;
2914 }
2915 case ARM::t2SpeculationBarrierSBEndBB: {
2916 // Print SB
2917 MCInst TmpInstSB;
2918 TmpInstSB.setOpcode(ARM::t2SB);
2919 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstSB);
2920 return;
2921 }
2922
2923 case ARM::SEH_StackAlloc:
2924 ATS.emitARMWinCFIAllocStack(Size: MI->getOperand(i: 0).getImm(),
2925 Wide: MI->getOperand(i: 1).getImm());
2926 return;
2927
2928 case ARM::SEH_SaveRegs:
2929 case ARM::SEH_SaveRegs_Ret:
2930 ATS.emitARMWinCFISaveRegMask(Mask: MI->getOperand(i: 0).getImm(),
2931 Wide: MI->getOperand(i: 1).getImm());
2932 return;
2933
2934 case ARM::SEH_SaveSP:
2935 ATS.emitARMWinCFISaveSP(Reg: MI->getOperand(i: 0).getImm());
2936 return;
2937
2938 case ARM::SEH_SaveFRegs:
2939 ATS.emitARMWinCFISaveFRegs(First: MI->getOperand(i: 0).getImm(),
2940 Last: MI->getOperand(i: 1).getImm());
2941 return;
2942
2943 case ARM::SEH_SaveLR:
2944 ATS.emitARMWinCFISaveLR(Offset: MI->getOperand(i: 0).getImm());
2945 return;
2946
2947 case ARM::SEH_Nop:
2948 case ARM::SEH_Nop_Ret:
2949 ATS.emitARMWinCFINop(Wide: MI->getOperand(i: 0).getImm());
2950 return;
2951
2952 case ARM::SEH_PrologEnd:
2953 ATS.emitARMWinCFIPrologEnd(/*Fragment=*/false);
2954 return;
2955
2956 case ARM::SEH_EpilogStart:
2957 ATS.emitARMWinCFIEpilogStart(Condition: ARMCC::AL);
2958 return;
2959
2960 case ARM::SEH_EpilogEnd:
2961 ATS.emitARMWinCFIEpilogEnd();
2962 return;
2963 }
2964
2965 MCInst TmpInst;
2966 LowerARMMachineInstrToMCInst(MI, OutMI&: TmpInst, AP&: *this);
2967
2968 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2969}
2970
2971char ARMAsmPrinter::ID = 0;
2972
2973INITIALIZE_PASS(ARMAsmPrinter, "arm-asm-printer", "ARM Assembly Printer", false,
2974 false)
2975
2976//===----------------------------------------------------------------------===//
2977// Target Registry Stuff
2978//===----------------------------------------------------------------------===//
2979
2980// Force static initialization.
2981extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
2982LLVMInitializeARMAsmPrinter() {
2983 RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
2984 RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
2985 RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
2986 RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
2987}
2988