1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format ARM assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMAsmPrinter.h"
15#include "ARM.h"
16#include "ARMConstantPoolValue.h"
17#include "ARMMachineFunctionInfo.h"
18#include "ARMTargetMachine.h"
19#include "ARMTargetObjectFile.h"
20#include "MCTargetDesc/ARMInstPrinter.h"
21#include "MCTargetDesc/ARMMCAsmInfo.h"
22#include "TargetInfo/ARMTargetInfo.h"
23#include "llvm/ADT/SmallString.h"
24#include "llvm/BinaryFormat/COFF.h"
25#include "llvm/CodeGen/MachineJumpTableInfo.h"
26#include "llvm/CodeGen/MachineModuleInfoImpls.h"
27#include "llvm/IR/Constants.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/IR/Mangler.h"
30#include "llvm/IR/Module.h"
31#include "llvm/IR/Type.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/MC/MCAssembler.h"
34#include "llvm/MC/MCContext.h"
35#include "llvm/MC/MCELFStreamer.h"
36#include "llvm/MC/MCInst.h"
37#include "llvm/MC/MCInstBuilder.h"
38#include "llvm/MC/MCObjectStreamer.h"
39#include "llvm/MC/MCStreamer.h"
40#include "llvm/MC/MCSymbol.h"
41#include "llvm/MC/TargetRegistry.h"
42#include "llvm/Support/ARMBuildAttributes.h"
43#include "llvm/Support/Compiler.h"
44#include "llvm/Support/Debug.h"
45#include "llvm/Support/ErrorHandling.h"
46#include "llvm/Support/raw_ostream.h"
47#include "llvm/Target/TargetMachine.h"
48using namespace llvm;
49
50#define DEBUG_TYPE "asm-printer"
51
52ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
53 std::unique_ptr<MCStreamer> Streamer)
54 : AsmPrinter(TM, std::move(Streamer), ID), AFI(nullptr), MCP(nullptr),
55 InConstantPool(false), OptimizationGoals(-1) {}
56
57const ARMBaseTargetMachine &ARMAsmPrinter::getTM() const {
58 return static_cast<const ARMBaseTargetMachine &>(TM);
59}
60
61void ARMAsmPrinter::emitFunctionBodyEnd() {
62 // Make sure to terminate any constant pools that were at the end
63 // of the function.
64 if (!InConstantPool)
65 return;
66 InConstantPool = false;
67 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
68}
69
70void ARMAsmPrinter::emitFunctionEntryLabel() {
71 auto &TS =
72 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
73 if (AFI->isThumbFunction()) {
74 TS.emitCode16();
75 TS.emitThumbFunc(Symbol: CurrentFnSym);
76 } else {
77 TS.emitCode32();
78 }
79
80 // Emit symbol for CMSE non-secure entry point
81 if (AFI->isCmseNSEntryFunction()) {
82 MCSymbol *S =
83 OutContext.getOrCreateSymbol(Name: "__acle_se_" + CurrentFnSym->getName());
84 emitLinkage(GV: &MF->getFunction(), GVSym: S);
85 OutStreamer->emitSymbolAttribute(Symbol: S, Attribute: MCSA_ELF_TypeFunction);
86 OutStreamer->emitLabel(Symbol: S);
87 }
88 AsmPrinter::emitFunctionEntryLabel();
89}
90
91void ARMAsmPrinter::emitXXStructor(const DataLayout &DL, const Constant *CV) {
92 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: CV->getType());
93 assert(Size && "C++ constructor pointer had zero size!");
94
95 const GlobalValue *GV = dyn_cast<GlobalValue>(Val: CV->stripPointerCasts());
96 assert(GV && "C++ constructor pointer was not a GlobalValue!");
97
98 const MCExpr *E = MCSymbolRefExpr::create(
99 Symbol: GetARMGVSymbol(GV, TargetFlags: ARMII::MO_NO_FLAG),
100 specifier: (TM.getTargetTriple().isOSBinFormatELF() ? ARM::S_TARGET1 : ARM::S_None),
101 Ctx&: OutContext);
102
103 OutStreamer->emitValue(Value: E, Size);
104}
105
106// An alias to a cmse entry function should also emit a `__acle_se_` symbol.
107void ARMAsmPrinter::emitCMSEVeneerAlias(const GlobalAlias &GA) {
108 const Function *BaseFn = dyn_cast_or_null<Function>(Val: GA.getAliaseeObject());
109 if (!BaseFn || !BaseFn->hasFnAttribute(Kind: "cmse_nonsecure_entry"))
110 return;
111
112 MCSymbol *AliasSym = getSymbol(GV: &GA);
113 MCSymbol *FnSym = getSymbol(GV: BaseFn);
114
115 MCSymbol *SEAliasSym =
116 OutContext.getOrCreateSymbol(Name: Twine("__acle_se_") + AliasSym->getName());
117 MCSymbol *SEBaseSym =
118 OutContext.getOrCreateSymbol(Name: Twine("__acle_se_") + FnSym->getName());
119
120 // Mirror alias linkage/visibility onto the veneer-alias symbol.
121 emitLinkage(GV: &GA, GVSym: SEAliasSym);
122 OutStreamer->emitSymbolAttribute(Symbol: SEAliasSym, Attribute: MCSA_ELF_TypeFunction);
123 emitVisibility(Sym: SEAliasSym, Visibility: GA.getVisibility());
124
125 // emit "__acle_se_<alias> = __acle_se_<aliasee>"
126 const MCExpr *SEExpr = MCSymbolRefExpr::create(Symbol: SEBaseSym, Ctx&: OutContext);
127 OutStreamer->emitAssignment(Symbol: SEAliasSym, Value: SEExpr);
128}
129
130void ARMAsmPrinter::emitGlobalAlias(const Module &M, const GlobalAlias &GA) {
131 AsmPrinter::emitGlobalAlias(M, GA);
132 emitCMSEVeneerAlias(GA);
133}
134
135void ARMAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
136 if (PromotedGlobals.count(Ptr: GV))
137 // The global was promoted into a constant pool. It should not be emitted.
138 return;
139 AsmPrinter::emitGlobalVariable(GV);
140}
141
142/// runOnMachineFunction - This uses the emitInstruction()
143/// method to print assembly for each instruction.
144///
145bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
146 AFI = MF.getInfo<ARMFunctionInfo>();
147 MCP = MF.getConstantPool();
148
149 SetupMachineFunction(MF);
150 const Function &F = MF.getFunction();
151 const TargetMachine& TM = MF.getTarget();
152
153 // Collect all globals that had their storage promoted to a constant pool.
154 // Functions are emitted before variables, so this accumulates promoted
155 // globals from all functions in PromotedGlobals.
156 PromotedGlobals.insert_range(R&: AFI->getGlobalsPromotedToConstantPool());
157
158 // Calculate this function's optimization goal.
159 unsigned OptimizationGoal;
160 if (F.hasOptNone())
161 // For best debugging illusion, speed and small size sacrificed
162 OptimizationGoal = 6;
163 else if (F.hasMinSize())
164 // Aggressively for small size, speed and debug illusion sacrificed
165 OptimizationGoal = 4;
166 else if (F.hasOptSize())
167 // For small size, but speed and debugging illusion preserved
168 OptimizationGoal = 3;
169 else if (TM.getOptLevel() == CodeGenOptLevel::Aggressive)
170 // Aggressively for speed, small size and debug illusion sacrificed
171 OptimizationGoal = 2;
172 else if (TM.getOptLevel() > CodeGenOptLevel::None)
173 // For speed, but small size and good debug illusion preserved
174 OptimizationGoal = 1;
175 else // TM.getOptLevel() == CodeGenOptLevel::None
176 // For good debugging, but speed and small size preserved
177 OptimizationGoal = 5;
178
179 // Combine a new optimization goal with existing ones.
180 if (OptimizationGoals == -1) // uninitialized goals
181 OptimizationGoals = OptimizationGoal;
182 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
183 OptimizationGoals = 0;
184
185 if (TM.getTargetTriple().isOSBinFormatCOFF()) {
186 bool Local = F.hasLocalLinkage();
187 COFF::SymbolStorageClass Scl =
188 Local ? COFF::IMAGE_SYM_CLASS_STATIC : COFF::IMAGE_SYM_CLASS_EXTERNAL;
189 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
190
191 OutStreamer->beginCOFFSymbolDef(Symbol: CurrentFnSym);
192 OutStreamer->emitCOFFSymbolStorageClass(StorageClass: Scl);
193 OutStreamer->emitCOFFSymbolType(Type);
194 OutStreamer->endCOFFSymbolDef();
195 }
196
197 // Emit the rest of the function body.
198 emitFunctionBody();
199
200 // Emit the XRay table for this function.
201 emitXRayTable();
202
203 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
204 // These are created per function, rather than per TU, since it's
205 // relatively easy to exceed the thumb branch range within a TU.
206 if (! ThumbIndirectPads.empty()) {
207 auto &TS =
208 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
209 TS.emitCode16();
210 emitAlignment(Alignment: Align(2));
211 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
212 OutStreamer->emitLabel(Symbol: TIP.second);
213 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBX)
214 .addReg(Reg: TIP.first)
215 // Add predicate operands.
216 .addImm(Val: ARMCC::AL)
217 .addReg(Reg: 0));
218 }
219 ThumbIndirectPads.clear();
220 }
221
222 // We didn't modify anything.
223 return false;
224}
225
226void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
227 raw_ostream &O) {
228 assert(MO.isGlobal() && "caller should check MO.isGlobal");
229 unsigned TF = MO.getTargetFlags();
230 if (TF & ARMII::MO_LO16)
231 O << ":lower16:";
232 else if (TF & ARMII::MO_HI16)
233 O << ":upper16:";
234 else if (TF & ARMII::MO_LO_0_7)
235 O << ":lower0_7:";
236 else if (TF & ARMII::MO_LO_8_15)
237 O << ":lower8_15:";
238 else if (TF & ARMII::MO_HI_0_7)
239 O << ":upper0_7:";
240 else if (TF & ARMII::MO_HI_8_15)
241 O << ":upper8_15:";
242
243 GetARMGVSymbol(GV: MO.getGlobal(), TargetFlags: TF)->print(OS&: O, MAI);
244 printOffset(Offset: MO.getOffset(), OS&: O);
245}
246
247void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
248 raw_ostream &O) {
249 const MachineOperand &MO = MI->getOperand(i: OpNum);
250
251 switch (MO.getType()) {
252 default: llvm_unreachable("<unknown operand type>");
253 case MachineOperand::MO_Register: {
254 Register Reg = MO.getReg();
255 assert(Reg.isPhysical());
256 assert(!MO.getSubReg() && "Subregs should be eliminated!");
257 if(ARM::GPRPairRegClass.contains(Reg)) {
258 const MachineFunction &MF = *MI->getParent()->getParent();
259 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
260 Reg = TRI->getSubReg(Reg, Idx: ARM::gsub_0);
261 }
262 O << ARMInstPrinter::getRegisterName(Reg);
263 break;
264 }
265 case MachineOperand::MO_Immediate: {
266 O << '#';
267 unsigned TF = MO.getTargetFlags();
268 if (TF == ARMII::MO_LO16)
269 O << ":lower16:";
270 else if (TF == ARMII::MO_HI16)
271 O << ":upper16:";
272 else if (TF == ARMII::MO_LO_0_7)
273 O << ":lower0_7:";
274 else if (TF == ARMII::MO_LO_8_15)
275 O << ":lower8_15:";
276 else if (TF == ARMII::MO_HI_0_7)
277 O << ":upper0_7:";
278 else if (TF == ARMII::MO_HI_8_15)
279 O << ":upper8_15:";
280 O << MO.getImm();
281 break;
282 }
283 case MachineOperand::MO_MachineBasicBlock:
284 MO.getMBB()->getSymbol()->print(OS&: O, MAI);
285 return;
286 case MachineOperand::MO_GlobalAddress: {
287 PrintSymbolOperand(MO, O);
288 break;
289 }
290 case MachineOperand::MO_ConstantPoolIndex:
291 assert(!MF->getSubtarget<ARMSubtarget>().genExecuteOnly() &&
292 "execute-only should not generate constant pools");
293 GetCPISymbol(CPID: MO.getIndex())->print(OS&: O, MAI);
294 break;
295 }
296}
297
298MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
299 // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
300 // indexes in MachineConstantPool, which isn't in sync with indexes used here.
301 const DataLayout &DL = getDataLayout();
302 return OutContext.getOrCreateSymbol(Name: Twine(DL.getInternalSymbolPrefix()) +
303 "CPI" + Twine(getFunctionNumber()) + "_" +
304 Twine(CPID));
305}
306
307//===--------------------------------------------------------------------===//
308
309MCSymbol *ARMAsmPrinter::
310GetARMJTIPICJumpTableLabel(unsigned uid) const {
311 const DataLayout &DL = getDataLayout();
312 SmallString<60> Name;
313 raw_svector_ostream(Name) << DL.getInternalSymbolPrefix() << "JTI"
314 << getFunctionNumber() << '_' << uid;
315 return OutContext.getOrCreateSymbol(Name);
316}
317
318bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
319 const char *ExtraCode, raw_ostream &O) {
320 // Does this asm operand have a single letter operand modifier?
321 if (ExtraCode && ExtraCode[0]) {
322 if (ExtraCode[1] != 0) return true; // Unknown modifier.
323
324 switch (ExtraCode[0]) {
325 default:
326 // See if this is a generic print operand
327 return AsmPrinter::PrintAsmOperand(MI, OpNo: OpNum, ExtraCode, OS&: O);
328 case 'P': // Print a VFP double precision register.
329 case 'q': // Print a NEON quad precision register.
330 printOperand(MI, OpNum, O);
331 return false;
332 case 'y': // Print a VFP single precision register as indexed double.
333 if (MI->getOperand(i: OpNum).isReg()) {
334 MCRegister Reg = MI->getOperand(i: OpNum).getReg().asMCReg();
335 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
336 // Find the 'd' register that has this 's' register as a sub-register,
337 // and determine the lane number.
338 for (MCPhysReg SR : TRI->superregs(Reg)) {
339 if (!ARM::DPRRegClass.contains(Reg: SR))
340 continue;
341 bool Lane0 = TRI->getSubReg(Reg: SR, Idx: ARM::ssub_0) == Reg;
342 O << ARMInstPrinter::getRegisterName(Reg: SR) << (Lane0 ? "[0]" : "[1]");
343 return false;
344 }
345 }
346 return true;
347 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
348 if (!MI->getOperand(i: OpNum).isImm())
349 return true;
350 O << ~(MI->getOperand(i: OpNum).getImm());
351 return false;
352 case 'L': // The low 16 bits of an immediate constant.
353 if (!MI->getOperand(i: OpNum).isImm())
354 return true;
355 O << (MI->getOperand(i: OpNum).getImm() & 0xffff);
356 return false;
357 case 'M': { // A register range suitable for LDM/STM.
358 if (!MI->getOperand(i: OpNum).isReg())
359 return true;
360 const MachineOperand &MO = MI->getOperand(i: OpNum);
361 Register RegBegin = MO.getReg();
362 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
363 // already got the operands in registers that are operands to the
364 // inline asm statement.
365 O << "{";
366 if (ARM::GPRPairRegClass.contains(Reg: RegBegin)) {
367 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
368 Register Reg0 = TRI->getSubReg(Reg: RegBegin, Idx: ARM::gsub_0);
369 O << ARMInstPrinter::getRegisterName(Reg: Reg0) << ", ";
370 RegBegin = TRI->getSubReg(Reg: RegBegin, Idx: ARM::gsub_1);
371 }
372 O << ARMInstPrinter::getRegisterName(Reg: RegBegin);
373
374 // FIXME: The register allocator not only may not have given us the
375 // registers in sequence, but may not be in ascending registers. This
376 // will require changes in the register allocator that'll need to be
377 // propagated down here if the operands change.
378 unsigned RegOps = OpNum + 1;
379 while (MI->getOperand(i: RegOps).isReg()) {
380 O << ", "
381 << ARMInstPrinter::getRegisterName(Reg: MI->getOperand(i: RegOps).getReg());
382 RegOps++;
383 }
384
385 O << "}";
386
387 return false;
388 }
389 case 'R': // The most significant register of a pair.
390 case 'Q': { // The least significant register of a pair.
391 if (OpNum == 0)
392 return true;
393 const MachineOperand &FlagsOP = MI->getOperand(i: OpNum - 1);
394 if (!FlagsOP.isImm())
395 return true;
396 InlineAsm::Flag F(FlagsOP.getImm());
397
398 // This operand may not be the one that actually provides the register. If
399 // it's tied to a previous one then we should refer instead to that one
400 // for registers and their classes.
401 unsigned TiedIdx;
402 if (F.isUseOperandTiedToDef(Idx&: TiedIdx)) {
403 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
404 unsigned OpFlags = MI->getOperand(i: OpNum).getImm();
405 const InlineAsm::Flag F(OpFlags);
406 OpNum += F.getNumOperandRegisters() + 1;
407 }
408 F = InlineAsm::Flag(MI->getOperand(i: OpNum).getImm());
409
410 // Later code expects OpNum to be pointing at the register rather than
411 // the flags.
412 OpNum += 1;
413 }
414
415 const unsigned NumVals = F.getNumOperandRegisters();
416 unsigned RC;
417 bool FirstHalf;
418 const ARMBaseTargetMachine &ATM =
419 static_cast<const ARMBaseTargetMachine &>(TM);
420
421 // 'Q' should correspond to the low order register and 'R' to the high
422 // order register. Whether this corresponds to the upper or lower half
423 // depends on the endianness mode.
424 if (ExtraCode[0] == 'Q')
425 FirstHalf = ATM.isLittleEndian();
426 else
427 // ExtraCode[0] == 'R'.
428 FirstHalf = !ATM.isLittleEndian();
429 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
430 if (F.hasRegClassConstraint(RC) &&
431 ARM::GPRPairRegClass.hasSubClassEq(RC: TRI->getRegClass(i: RC))) {
432 if (NumVals != 1)
433 return true;
434 const MachineOperand &MO = MI->getOperand(i: OpNum);
435 if (!MO.isReg())
436 return true;
437 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
438 Register Reg =
439 TRI->getSubReg(Reg: MO.getReg(), Idx: FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
440 O << ARMInstPrinter::getRegisterName(Reg);
441 return false;
442 }
443 if (NumVals != 2)
444 return true;
445 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
446 if (RegOp >= MI->getNumOperands())
447 return true;
448 const MachineOperand &MO = MI->getOperand(i: RegOp);
449 if (!MO.isReg())
450 return true;
451 Register Reg = MO.getReg();
452 O << ARMInstPrinter::getRegisterName(Reg);
453 return false;
454 }
455
456 case 'e': // The low doubleword register of a NEON quad register.
457 case 'f': { // The high doubleword register of a NEON quad register.
458 if (!MI->getOperand(i: OpNum).isReg())
459 return true;
460 Register Reg = MI->getOperand(i: OpNum).getReg();
461 if (!ARM::QPRRegClass.contains(Reg))
462 return true;
463 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
464 Register SubReg =
465 TRI->getSubReg(Reg, Idx: ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
466 O << ARMInstPrinter::getRegisterName(Reg: SubReg);
467 return false;
468 }
469
470 // This modifier is not yet supported.
471 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
472 return true;
473 case 'H': { // The highest-numbered register of a pair.
474 const MachineOperand &MO = MI->getOperand(i: OpNum);
475 if (!MO.isReg())
476 return true;
477 const MachineFunction &MF = *MI->getParent()->getParent();
478 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
479 Register Reg = MO.getReg();
480 if(!ARM::GPRPairRegClass.contains(Reg))
481 return false;
482 Reg = TRI->getSubReg(Reg, Idx: ARM::gsub_1);
483 O << ARMInstPrinter::getRegisterName(Reg);
484 return false;
485 }
486 }
487 }
488
489 printOperand(MI, OpNum, O);
490 return false;
491}
492
493bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
494 unsigned OpNum, const char *ExtraCode,
495 raw_ostream &O) {
496 // Does this asm operand have a single letter operand modifier?
497 if (ExtraCode && ExtraCode[0]) {
498 if (ExtraCode[1] != 0) return true; // Unknown modifier.
499
500 switch (ExtraCode[0]) {
501 case 'A': // A memory operand for a VLD1/VST1 instruction.
502 default: return true; // Unknown modifier.
503 case 'm': // The base register of a memory operand.
504 if (!MI->getOperand(i: OpNum).isReg())
505 return true;
506 O << ARMInstPrinter::getRegisterName(Reg: MI->getOperand(i: OpNum).getReg());
507 return false;
508 }
509 }
510
511 const MachineOperand &MO = MI->getOperand(i: OpNum);
512 assert(MO.isReg() && "unexpected inline asm memory operand");
513 O << "[" << ARMInstPrinter::getRegisterName(Reg: MO.getReg()) << "]";
514 return false;
515}
516
517static bool isThumb(const MCSubtargetInfo& STI) {
518 return STI.hasFeature(Feature: ARM::ModeThumb);
519}
520
521void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
522 const MCSubtargetInfo *EndInfo,
523 const MachineInstr *MI) {
524 // If either end mode is unknown (EndInfo == NULL) or different than
525 // the start mode, then restore the start mode.
526 const bool WasThumb = isThumb(STI: StartInfo);
527 if (!EndInfo || WasThumb != isThumb(STI: *EndInfo)) {
528 auto &TS =
529 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
530 if (WasThumb)
531 TS.emitCode16();
532 else
533 TS.emitCode32();
534 }
535}
536
537void ARMAsmPrinter::emitStartOfAsmFile(Module &M) {
538 const Triple &TT = TM.getTargetTriple();
539 auto &TS =
540 static_cast<ARMTargetStreamer &>(*OutStreamer->getTargetStreamer());
541 // Use unified assembler syntax.
542 TS.emitSyntaxUnified();
543
544 // Emit ARM Build Attributes
545 if (TT.isOSBinFormatELF())
546 emitAttributes();
547
548 // Use the triple's architecture and subarchitecture to determine
549 // if we're thumb for the purposes of the top level code16 state.
550 if (!M.getModuleInlineAsm().empty() && TT.isThumb())
551 TS.emitCode16();
552}
553
554static void
555emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
556 MachineModuleInfoImpl::StubValueTy &MCSym) {
557 // L_foo$stub:
558 OutStreamer.emitLabel(Symbol: StubLabel);
559 // .indirect_symbol _foo
560 OutStreamer.emitSymbolAttribute(Symbol: MCSym.getPointer(), Attribute: MCSA_IndirectSymbol);
561
562 if (MCSym.getInt())
563 // External to current translation unit.
564 OutStreamer.emitIntValue(Value: 0, Size: 4/*size*/);
565 else
566 // Internal to current translation unit.
567 //
568 // When we place the LSDA into the TEXT section, the type info
569 // pointers need to be indirect and pc-rel. We accomplish this by
570 // using NLPs; however, sometimes the types are local to the file.
571 // We need to fill in the value for the NLP in those cases.
572 OutStreamer.emitValue(
573 Value: MCSymbolRefExpr::create(Symbol: MCSym.getPointer(), Ctx&: OutStreamer.getContext()),
574 Size: 4 /*size*/);
575}
576
577
578void ARMAsmPrinter::emitEndOfAsmFile(Module &M) {
579 const Triple &TT = TM.getTargetTriple();
580 if (TT.isOSBinFormatMachO()) {
581 // All darwin targets use mach-o.
582 const TargetLoweringObjectFileMachO &TLOFMacho =
583 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
584 MachineModuleInfoMachO &MMIMacho =
585 MMI->getObjFileInfo<MachineModuleInfoMachO>();
586
587 // Output non-lazy-pointers for external and common global variables.
588 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
589
590 if (!Stubs.empty()) {
591 // Switch with ".non_lazy_symbol_pointer" directive.
592 OutStreamer->switchSection(Section: TLOFMacho.getNonLazySymbolPointerSection());
593 emitAlignment(Alignment: Align(4));
594
595 for (auto &Stub : Stubs)
596 emitNonLazySymbolPointer(OutStreamer&: *OutStreamer, StubLabel: Stub.first, MCSym&: Stub.second);
597
598 Stubs.clear();
599 OutStreamer->addBlankLine();
600 }
601
602 Stubs = MMIMacho.GetThreadLocalGVStubList();
603 if (!Stubs.empty()) {
604 // Switch with ".non_lazy_symbol_pointer" directive.
605 OutStreamer->switchSection(Section: TLOFMacho.getThreadLocalPointerSection());
606 emitAlignment(Alignment: Align(4));
607
608 for (auto &Stub : Stubs)
609 emitNonLazySymbolPointer(OutStreamer&: *OutStreamer, StubLabel: Stub.first, MCSym&: Stub.second);
610
611 Stubs.clear();
612 OutStreamer->addBlankLine();
613 }
614
615 // Funny Darwin hack: This flag tells the linker that no global symbols
616 // contain code that falls through to other global symbols (e.g. the obvious
617 // implementation of multiple entry points). If this doesn't occur, the
618 // linker can safely perform dead code stripping. Since LLVM never
619 // generates code that does this, it is always safe to set.
620 OutStreamer->emitSubsectionsViaSymbols();
621 }
622
623 // The last attribute to be emitted is ABI_optimization_goals
624 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
625 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
626
627 if (OptimizationGoals > 0 &&
628 (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI()))
629 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_optimization_goals, Value: OptimizationGoals);
630 OptimizationGoals = -1;
631
632 ATS.finishAttributeSection();
633}
634
635//===----------------------------------------------------------------------===//
636// Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
637// FIXME:
638// The following seem like one-off assembler flags, but they actually need
639// to appear in the .ARM.attributes section in ELF.
640// Instead of subclassing the MCELFStreamer, we do the work here.
641
642// Returns true if all function definitions have the same function attribute
643// value. It also returns true when the module has no functions.
644static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
645 StringRef Value) {
646 return !any_of(Range: M, P: [&](const Function &F) {
647 if (F.isDeclaration())
648 return false;
649 return F.getFnAttribute(Kind: Attr).getValueAsString() != Value;
650 });
651}
652// Returns true if all functions definitions have the same denormal mode.
653// It also returns true when the module has no functions.
654static bool checkDenormalAttributeConsistency(const Module &M,
655 DenormalFPEnv Value) {
656 return !any_of(Range: M, P: [&](const Function &F) {
657 if (F.isDeclaration())
658 return false;
659 return F.getDenormalFPEnv() != Value;
660 });
661}
662
663// Returns true if all functions have different denormal modes.
664static bool checkDenormalAttributeInconsistency(const Module &M) {
665 auto F = M.functions().begin();
666 auto E = M.functions().end();
667 if (F == E)
668 return false;
669 DenormalFPEnv Value = F->getDenormalFPEnv();
670 ++F;
671 return std::any_of(first: F, last: E, pred: [&](const Function &F) {
672 return !F.isDeclaration() && F.getDenormalFPEnv() != Value;
673 });
674}
675
676void ARMAsmPrinter::emitAttributes() {
677 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
678 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
679
680 ATS.emitTextAttribute(Attribute: ARMBuildAttrs::conformance, String: "2.09");
681
682 ATS.switchVendor(Vendor: "aeabi");
683
684 // Compute ARM ELF Attributes based on the default subtarget that
685 // we'd have constructed. The existing ARM behavior isn't LTO clean
686 // anyhow.
687 // FIXME: For ifunc related functions we could iterate over and look
688 // for a feature string that doesn't match the default one.
689 const Triple &TT = TM.getTargetTriple();
690 StringRef CPU = TM.getTargetCPU();
691 StringRef FS = TM.getTargetFeatureString();
692 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
693 if (!FS.empty()) {
694 if (!ArchFS.empty())
695 ArchFS = (Twine(ArchFS) + "," + FS).str();
696 else
697 ArchFS = std::string(FS);
698 }
699 const ARMBaseTargetMachine &ATM =
700 static_cast<const ARMBaseTargetMachine &>(TM);
701 FloatABI::ABIType FloatABI = ATM.getFloatABI(M: *MMI->getModule());
702 ARM::ARMABI ABI = ATM.getEffectiveABI(M: *MMI->getModule());
703 const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
704 ATM.isLittleEndian(), FloatABI, ABI);
705
706 // Emit build attributes for the available hardware.
707 ATS.emitTargetAttributes(STI);
708
709 // RW data addressing.
710 if (isPositionIndependent()) {
711 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RW_data,
712 Value: ARMBuildAttrs::AddressRWPCRel);
713 } else if (STI.isRWPI()) {
714 // RWPI specific attributes.
715 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RW_data,
716 Value: ARMBuildAttrs::AddressRWSBRel);
717 }
718
719 // RO data addressing.
720 if (isPositionIndependent() || STI.isROPI()) {
721 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_RO_data,
722 Value: ARMBuildAttrs::AddressROPCRel);
723 }
724
725 // GOT use.
726 if (isPositionIndependent()) {
727 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_GOT_use,
728 Value: ARMBuildAttrs::AddressGOT);
729 } else {
730 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_GOT_use,
731 Value: ARMBuildAttrs::AddressDirect);
732 }
733
734 // Set FP Denormals.
735 if (auto *DM = mdconst::extract_or_null<ConstantInt>(
736 MD: MMI->getModule()->getModuleFlag(Key: "arm-eabi-fp-denormal"))) {
737 if (unsigned TagVal = DM->getZExtValue())
738 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal, Value: TagVal);
739 } else if (checkDenormalAttributeConsistency(M: *MMI->getModule(),
740 Value: DenormalMode::getPreserveSign()))
741 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
742 Value: ARMBuildAttrs::PreserveFPSign);
743 else if (checkDenormalAttributeConsistency(M: *MMI->getModule(),
744 Value: DenormalMode::getPositiveZero()))
745 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
746 Value: ARMBuildAttrs::PositiveZero);
747 else if (checkDenormalAttributeInconsistency(M: *MMI->getModule()) ||
748 checkDenormalAttributeConsistency(M: *MMI->getModule(),
749 Value: DenormalMode::getIEEE()))
750 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
751 Value: ARMBuildAttrs::IEEEDenormals);
752 else {
753 if (!STI.hasVFP2Base()) {
754 // When the target doesn't have an FPU (by design or
755 // intention), the assumptions made on the software support
756 // mirror that of the equivalent hardware support *if it
757 // existed*. For v7 and better we indicate that denormals are
758 // flushed preserving sign, and for V6 we indicate that
759 // denormals are flushed to positive zero.
760 if (STI.hasV7Ops())
761 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
762 Value: ARMBuildAttrs::PreserveFPSign);
763 } else if (STI.hasVFP3Base()) {
764 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
765 // the sign bit of the zero matches the sign bit of the input or
766 // result that is being flushed to zero.
767 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_denormal,
768 Value: ARMBuildAttrs::PreserveFPSign);
769 }
770 // For VFPv2 implementations it is implementation defined as
771 // to whether denormals are flushed to positive zero or to
772 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
773 // LLVM has chosen to flush this to positive zero (most likely for
774 // GCC compatibility), so that's the chosen value here (the
775 // absence of its emission implies zero).
776 }
777
778 // Set FP exceptions and rounding
779 if (auto *Ex = mdconst::extract_or_null<ConstantInt>(
780 MD: MMI->getModule()->getModuleFlag(Key: "arm-eabi-fp-exceptions"))) {
781 if (unsigned TagVal = Ex->getZExtValue())
782 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions, Value: TagVal);
783 } else if (checkFunctionsAttributeConsistency(M: *MMI->getModule(),
784 Attr: "no-trapping-math", Value: "true") ||
785 TM.Options.NoTrappingFPMath)
786 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions,
787 Value: ARMBuildAttrs::Not_Allowed);
788 else {
789 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_exceptions, Value: ARMBuildAttrs::Allowed);
790
791 // If the user has permitted this code to choose the IEEE 754
792 // rounding at run-time, emit the rounding attribute.
793 if (TM.Options.HonorSignDependentRoundingFPMathOption)
794 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_rounding, Value: ARMBuildAttrs::Allowed);
795 }
796
797 // Generate ABI tags from module flags.
798 if (auto *NumModel = mdconst::extract_or_null<ConstantInt>(
799 MD: MMI->getModule()->getModuleFlag(Key: "arm-eabi-fp-number-model"))) {
800 if (unsigned TagVal = NumModel->getZExtValue())
801 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_number_model, Value: TagVal);
802 } else
803 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_number_model,
804 Value: ARMBuildAttrs::AllowIEEE754);
805
806 // FIXME: add more flags to ARMBuildAttributes.h
807 // 8-bytes alignment stuff.
808 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_align_needed, Value: 1);
809 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_align_preserved, Value: 1);
810
811 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
812 if (STI.isAAPCS_ABI() && STI.isTargetHardFloat())
813 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_VFP_args, Value: ARMBuildAttrs::HardFPAAPCS);
814
815 // FIXME: To support emitting this build attribute as GCC does, the
816 // -mfp16-format option and associated plumbing must be
817 // supported. For now the __fp16 type is exposed by default, so this
818 // attribute should be emitted with value 1.
819 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_FP_16bit_format,
820 Value: ARMBuildAttrs::FP16FormatIEEE);
821
822 if (const Module *SourceModule = MMI->getModule()) {
823 // ABI_PCS_wchar_t to indicate wchar_t width
824 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
825 int WCharWidth = TM.getTargetTriple().getDefaultWCharSize();
826 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
827 MD: SourceModule->getModuleFlag(Key: "wchar_size")))
828 WCharWidth = WCharWidthValue->getZExtValue();
829 assert((WCharWidth == 2 || WCharWidth == 4) &&
830 "wchar_t width must be 2 or 4 bytes");
831 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_wchar_t, Value: WCharWidth);
832
833 // ABI_enum_size to indicate enum width
834 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
835 // (all enums contain a value needing 32 bits to encode).
836 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
837 MD: SourceModule->getModuleFlag(Key: "min_enum_size"))) {
838 int EnumWidth = EnumWidthValue->getZExtValue();
839 assert((EnumWidth == 1 || EnumWidth == 4) &&
840 "Minimum enum width must be 1 or 4 bytes");
841 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
842 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_enum_size, Value: EnumBuildAttr);
843 }
844
845 auto *PACValue = mdconst::extract_or_null<ConstantInt>(
846 MD: SourceModule->getModuleFlag(Key: "sign-return-address"));
847 if (PACValue && PACValue->isOne()) {
848 // If "+pacbti" is used as an architecture extension,
849 // Tag_PAC_extension is emitted in
850 // ARMTargetStreamer::emitTargetAttributes().
851 if (!STI.hasPACBTI()) {
852 ATS.emitAttribute(Attribute: ARMBuildAttrs::PAC_extension,
853 Value: ARMBuildAttrs::AllowPACInNOPSpace);
854 }
855 ATS.emitAttribute(Attribute: ARMBuildAttrs::PACRET_use, Value: ARMBuildAttrs::PACRETUsed);
856 }
857
858 auto *BTIValue = mdconst::extract_or_null<ConstantInt>(
859 MD: SourceModule->getModuleFlag(Key: "branch-target-enforcement"));
860 if (BTIValue && !BTIValue->isZero()) {
861 // If "+pacbti" is used as an architecture extension,
862 // Tag_BTI_extension is emitted in
863 // ARMTargetStreamer::emitTargetAttributes().
864 if (!STI.hasPACBTI()) {
865 ATS.emitAttribute(Attribute: ARMBuildAttrs::BTI_extension,
866 Value: ARMBuildAttrs::AllowBTIInNOPSpace);
867 }
868 ATS.emitAttribute(Attribute: ARMBuildAttrs::BTI_use, Value: ARMBuildAttrs::BTIUsed);
869 }
870 }
871
872 // We currently do not support using R9 as the TLS pointer.
873 if (STI.isRWPI())
874 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
875 Value: ARMBuildAttrs::R9IsSB);
876 else if (STI.isR9Reserved())
877 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
878 Value: ARMBuildAttrs::R9Reserved);
879 else
880 ATS.emitAttribute(Attribute: ARMBuildAttrs::ABI_PCS_R9_use,
881 Value: ARMBuildAttrs::R9IsGPR);
882}
883
884//===----------------------------------------------------------------------===//
885
886static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
887 unsigned LabelId, MCContext &Ctx) {
888
889 MCSymbol *Label = Ctx.getOrCreateSymbol(Name: Twine(Prefix)
890 + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
891 return Label;
892}
893
894static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
895 unsigned LabelId, MCContext &Ctx) {
896
897 MCSymbol *Label = Ctx.getOrCreateSymbol(Name: Twine(Prefix)
898 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
899 return Label;
900}
901
902static uint8_t getModifierSpecifier(ARMCP::ARMCPModifier Modifier) {
903 switch (Modifier) {
904 case ARMCP::no_modifier:
905 return ARM::S_None;
906 case ARMCP::TLSGD:
907 return ARM::S_TLSGD;
908 case ARMCP::TPOFF:
909 return ARM::S_TPOFF;
910 case ARMCP::GOTTPOFF:
911 return ARM::S_GOTTPOFF;
912 case ARMCP::SBREL:
913 return ARM::S_SBREL;
914 case ARMCP::GOT_PREL:
915 return ARM::S_GOT_PREL;
916 case ARMCP::SECREL:
917 return ARM::S_COFF_SECREL;
918 }
919 llvm_unreachable("Invalid ARMCPModifier!");
920}
921
922MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
923 unsigned char TargetFlags) {
924 const Triple &TT = TM.getTargetTriple();
925 if (TT.isOSBinFormatMachO()) {
926 bool IsIndirect =
927 (TargetFlags & ARMII::MO_NONLAZY) && getTM().isGVIndirectSymbol(GV);
928
929 if (!IsIndirect)
930 return getSymbol(GV);
931
932 // FIXME: Remove this when Darwin transition to @GOT like syntax.
933 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, Suffix: "$non_lazy_ptr");
934 MachineModuleInfoMachO &MMIMachO =
935 MMI->getObjFileInfo<MachineModuleInfoMachO>();
936 MachineModuleInfoImpl::StubValueTy &StubSym =
937 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(Sym: MCSym)
938 : MMIMachO.getGVStubEntry(Sym: MCSym);
939
940 if (!StubSym.getPointer())
941 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
942 !GV->hasInternalLinkage());
943 return MCSym;
944 } else if (TT.isOSBinFormatCOFF()) {
945 assert(TT.isOSWindows() && "Windows is the only supported COFF target");
946
947 bool IsIndirect =
948 (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
949 if (!IsIndirect)
950 return getSymbol(GV);
951
952 SmallString<128> Name;
953 if (TargetFlags & ARMII::MO_DLLIMPORT)
954 Name = "__imp_";
955 else if (TargetFlags & ARMII::MO_COFFSTUB)
956 Name = ".refptr.";
957 getNameWithPrefix(Name, GV);
958
959 MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
960
961 if (TargetFlags & ARMII::MO_COFFSTUB) {
962 MachineModuleInfoCOFF &MMICOFF =
963 MMI->getObjFileInfo<MachineModuleInfoCOFF>();
964 MachineModuleInfoImpl::StubValueTy &StubSym =
965 MMICOFF.getGVStubEntry(Sym: MCSym);
966
967 if (!StubSym.getPointer())
968 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
969 }
970
971 return MCSym;
972 } else if (TT.isOSBinFormatELF()) {
973 return getSymbolPreferLocal(GV: *GV);
974 }
975 llvm_unreachable("unexpected target");
976}
977
978void ARMAsmPrinter::emitMachineConstantPoolValue(
979 MachineConstantPoolValue *MCPV) {
980 const DataLayout &DL = getDataLayout();
981 int Size = DL.getTypeAllocSize(Ty: MCPV->getType());
982
983 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
984
985 if (ACPV->isPromotedGlobal()) {
986 // This constant pool entry is actually a global whose storage has been
987 // promoted into the constant pool. This global may be referenced still
988 // by debug information, and due to the way AsmPrinter is set up, the debug
989 // info is immutable by the time we decide to promote globals to constant
990 // pools. Because of this, we need to ensure we emit a symbol for the global
991 // with private linkage (the default) so debug info can refer to it.
992 //
993 // However, if this global is promoted into several functions we must ensure
994 // we don't try and emit duplicate symbols!
995 auto *ACPC = cast<ARMConstantPoolConstant>(Val: ACPV);
996 for (const auto *GV : ACPC->promotedGlobals()) {
997 if (!EmittedPromotedGlobalLabels.count(Ptr: GV)) {
998 MCSymbol *GVSym = getSymbol(GV);
999 OutStreamer->emitLabel(Symbol: GVSym);
1000 EmittedPromotedGlobalLabels.insert(Ptr: GV);
1001 }
1002 }
1003 return emitGlobalConstant(DL, CV: ACPC->getPromotedGlobalInit());
1004 }
1005
1006 MCSymbol *MCSym;
1007 if (ACPV->isLSDA()) {
1008 MCSym = getMBBExceptionSym(MBB: MF->front());
1009 } else if (ACPV->isBlockAddress()) {
1010 const BlockAddress *BA =
1011 cast<ARMConstantPoolConstant>(Val: ACPV)->getBlockAddress();
1012 MCSym = GetBlockAddressSymbol(BA);
1013 } else if (ACPV->isGlobalValue()) {
1014 const GlobalValue *GV = cast<ARMConstantPoolConstant>(Val: ACPV)->getGV();
1015
1016 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
1017 // flag the global as MO_NONLAZY.
1018 unsigned char TF =
1019 TM.getTargetTriple().isOSBinFormatMachO() ? ARMII::MO_NONLAZY : 0;
1020 MCSym = GetARMGVSymbol(GV, TargetFlags: TF);
1021
1022 // For dso_local weak symbols in ELF PIC mode, the assembler would eagerly
1023 // resolve a PC-relative expression like sym-(LPC+8) when the symbol and
1024 // reference are in the same section, preventing the linker from overriding
1025 // a weak definition with a non-weak definition from another section. Use a
1026 // .reloc directive rather than a fixup to force the generation of a
1027 // relocation (R_ARM_REL32) so the linker can perform the override. This is
1028 // restricted to dso_local, non-TLS symbols: a preemptible/external weak
1029 // symbol (e.g. an extern_weak reference) must use the GOT, as R_ARM_REL32
1030 // against an external symbol cannot be used when making a shared object;
1031 // and TLS symbols require TLS-specific relocations, not R_ARM_REL32.
1032 if (GV->isWeakForLinker() && GV->isDSOLocal() && !GV->isThreadLocal() &&
1033 TM.getTargetTriple().isOSBinFormatELF() && TM.isPositionIndependent() &&
1034 ACPV->getPCAdjustment() != 0) {
1035 MCSymbol *CPILabel = OutContext.createTempSymbol();
1036 OutStreamer->emitLabel(Symbol: CPILabel);
1037 // Emit local-only expression: CPILabel - (LPC+PCAdj)
1038 const MCExpr *LocalExpr = MCSymbolRefExpr::create(Symbol: CPILabel, Ctx&: OutContext);
1039 MCSymbol *PCLabel =
1040 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
1041 LabelId: ACPV->getLabelId(), Ctx&: OutContext);
1042 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(Symbol: PCLabel, Ctx&: OutContext);
1043 PCRelExpr = MCBinaryExpr::createAdd(
1044 LHS: PCRelExpr,
1045 RHS: MCConstantExpr::create(Value: ACPV->getPCAdjustment(), Ctx&: OutContext),
1046 Ctx&: OutContext);
1047 LocalExpr = MCBinaryExpr::createSub(LHS: LocalExpr, RHS: PCRelExpr, Ctx&: OutContext);
1048 OutStreamer->emitValue(Value: LocalExpr, Size);
1049 // Emit .reloc to force linker resolution of the weak symbol.
1050 const MCExpr *CPIExpr = MCSymbolRefExpr::create(Symbol: CPILabel, Ctx&: OutContext);
1051 const MCExpr *SymExpr = MCSymbolRefExpr::create(Symbol: MCSym, Ctx&: OutContext);
1052 OutStreamer->emitRelocDirective(Offset: *CPIExpr, Name: "R_ARM_REL32", Expr: SymExpr,
1053 Loc: SMLoc());
1054 return;
1055 }
1056 } else if (ACPV->isMachineBasicBlock()) {
1057 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(Val: ACPV)->getMBB();
1058 MCSym = MBB->getSymbol();
1059 } else {
1060 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
1061 auto Sym = cast<ARMConstantPoolSymbol>(Val: ACPV)->getSymbol();
1062 MCSym = GetExternalSymbolSymbol(Sym);
1063 }
1064
1065 // Create an MCSymbol for the reference.
1066 const MCExpr *Expr = MCSymbolRefExpr::create(
1067 Symbol: MCSym, specifier: getModifierSpecifier(Modifier: ACPV->getModifier()), Ctx&: OutContext);
1068
1069 if (ACPV->getPCAdjustment()) {
1070 MCSymbol *PCLabel =
1071 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
1072 LabelId: ACPV->getLabelId(), Ctx&: OutContext);
1073 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(Symbol: PCLabel, Ctx&: OutContext);
1074 PCRelExpr =
1075 MCBinaryExpr::createAdd(LHS: PCRelExpr,
1076 RHS: MCConstantExpr::create(Value: ACPV->getPCAdjustment(),
1077 Ctx&: OutContext),
1078 Ctx&: OutContext);
1079 if (ACPV->mustAddCurrentAddress()) {
1080 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
1081 // label, so just emit a local label end reference that instead.
1082 MCSymbol *DotSym = OutContext.createTempSymbol();
1083 OutStreamer->emitLabel(Symbol: DotSym);
1084 const MCExpr *DotExpr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
1085 PCRelExpr = MCBinaryExpr::createSub(LHS: PCRelExpr, RHS: DotExpr, Ctx&: OutContext);
1086 }
1087 Expr = MCBinaryExpr::createSub(LHS: Expr, RHS: PCRelExpr, Ctx&: OutContext);
1088 }
1089 OutStreamer->emitValue(Value: Expr, Size);
1090}
1091
1092void ARMAsmPrinter::emitJumpTableAddrs(const MachineInstr *MI) {
1093 const MachineOperand &MO1 = MI->getOperand(i: 1);
1094 unsigned JTI = MO1.getIndex();
1095
1096 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1097 // ARM mode tables.
1098 emitAlignment(Alignment: Align(4));
1099
1100 // Emit a label for the jump table.
1101 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1102 OutStreamer->emitLabel(Symbol: JTISymbol);
1103
1104 // Mark the jump table as data-in-code.
1105 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionJT32);
1106
1107 // Emit each entry of the table.
1108 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1109 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1110 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1111
1112 for (MachineBasicBlock *MBB : JTBBs) {
1113 // Construct an MCExpr for the entry. We want a value of the form:
1114 // (BasicBlockAddr - TableBeginAddr)
1115 //
1116 // For example, a table with entries jumping to basic blocks BB0 and BB1
1117 // would look like:
1118 // LJTI_0_0:
1119 // .word (LBB0 - LJTI_0_0)
1120 // .word (LBB1 - LJTI_0_0)
1121 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(), Ctx&: OutContext);
1122
1123 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1124 if (isPositionIndependent() || STI.isROPI())
1125 Expr = MCBinaryExpr::createSub(LHS: Expr, RHS: MCSymbolRefExpr::create(Symbol: JTISymbol,
1126 Ctx&: OutContext),
1127 Ctx&: OutContext);
1128 // If we're generating a table of Thumb addresses in static relocation
1129 // model, we need to add one to keep interworking correctly.
1130 else if (AFI->isThumbFunction())
1131 Expr = MCBinaryExpr::createAdd(LHS: Expr, RHS: MCConstantExpr::create(Value: 1,Ctx&: OutContext),
1132 Ctx&: OutContext);
1133 OutStreamer->emitValue(Value: Expr, Size: 4);
1134 }
1135 // Mark the end of jump table data-in-code region.
1136 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1137}
1138
1139void ARMAsmPrinter::emitJumpTableInsts(const MachineInstr *MI) {
1140 const MachineOperand &MO1 = MI->getOperand(i: 1);
1141 unsigned JTI = MO1.getIndex();
1142
1143 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1144 // ARM mode tables.
1145 emitAlignment(Alignment: Align(4));
1146
1147 // Emit a label for the jump table.
1148 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1149 OutStreamer->emitLabel(Symbol: JTISymbol);
1150
1151 // Emit each entry of the table.
1152 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1153 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1154 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1155
1156 for (MachineBasicBlock *MBB : JTBBs) {
1157 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(),
1158 Ctx&: OutContext);
1159 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1160 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2B)
1161 .addExpr(Val: MBBSymbolExpr)
1162 .addImm(Val: ARMCC::AL)
1163 .addReg(Reg: 0));
1164 }
1165}
1166
1167void ARMAsmPrinter::emitJumpTableTBInst(const MachineInstr *MI,
1168 unsigned OffsetWidth) {
1169 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1170 const MachineOperand &MO1 = MI->getOperand(i: 1);
1171 unsigned JTI = MO1.getIndex();
1172
1173 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1174 if (STI.isThumb1Only())
1175 emitAlignment(Alignment: Align(4));
1176
1177 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(uid: JTI);
1178 OutStreamer->emitLabel(Symbol: JTISymbol);
1179
1180 // Emit each entry of the table.
1181 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1182 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1183 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1184
1185 // Mark the jump table as data-in-code.
1186 OutStreamer->emitDataRegion(Kind: OffsetWidth == 1 ? MCDR_DataRegionJT8
1187 : MCDR_DataRegionJT16);
1188
1189 for (auto *MBB : JTBBs) {
1190 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(Symbol: MBB->getSymbol(),
1191 Ctx&: OutContext);
1192 // Otherwise it's an offset from the dispatch instruction. Construct an
1193 // MCExpr for the entry. We want a value of the form:
1194 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1195 //
1196 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1197 // would look like:
1198 // LJTI_0_0:
1199 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1200 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1201 // where LCPI0_0 is a label defined just before the TBB instruction using
1202 // this table.
1203 MCSymbol *TBInstPC = GetCPISymbol(CPID: MI->getOperand(i: 0).getImm());
1204 const MCExpr *Expr = MCBinaryExpr::createAdd(
1205 LHS: MCSymbolRefExpr::create(Symbol: TBInstPC, Ctx&: OutContext),
1206 RHS: MCConstantExpr::create(Value: 4, Ctx&: OutContext), Ctx&: OutContext);
1207 Expr = MCBinaryExpr::createSub(LHS: MBBSymbolExpr, RHS: Expr, Ctx&: OutContext);
1208 Expr = MCBinaryExpr::createDiv(LHS: Expr, RHS: MCConstantExpr::create(Value: 2, Ctx&: OutContext),
1209 Ctx&: OutContext);
1210 OutStreamer->emitValue(Value: Expr, Size: OffsetWidth);
1211 }
1212 // Mark the end of jump table data-in-code region. 32-bit offsets use
1213 // actual branch instructions here, so we don't mark those as a data-region
1214 // at all.
1215 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1216
1217 // Make sure the next instruction is 2-byte aligned.
1218 emitAlignment(Alignment: Align(2));
1219}
1220
1221std::tuple<const MCSymbol *, uint64_t, const MCSymbol *,
1222 codeview::JumpTableEntrySize>
1223ARMAsmPrinter::getCodeViewJumpTableInfo(int JTI,
1224 const MachineInstr *BranchInstr,
1225 const MCSymbol *BranchLabel) const {
1226 codeview::JumpTableEntrySize EntrySize;
1227 const MCSymbol *BaseLabel;
1228 uint64_t BaseOffset = 0;
1229 switch (BranchInstr->getOpcode()) {
1230 case ARM::BR_JTadd:
1231 case ARM::BR_JTr:
1232 case ARM::tBR_JTr:
1233 // Word relative to the jump table address.
1234 EntrySize = codeview::JumpTableEntrySize::UInt32;
1235 BaseLabel = GetARMJTIPICJumpTableLabel(uid: JTI);
1236 break;
1237 case ARM::tTBH_JT:
1238 case ARM::t2TBH_JT:
1239 // half-word shifted left, relative to *after* the branch instruction.
1240 EntrySize = codeview::JumpTableEntrySize::UInt16ShiftLeft;
1241 BranchLabel = GetCPISymbol(CPID: BranchInstr->getOperand(i: 3).getImm());
1242 BaseLabel = BranchLabel;
1243 BaseOffset = 4;
1244 break;
1245 case ARM::tTBB_JT:
1246 case ARM::t2TBB_JT:
1247 // byte shifted left, relative to *after* the branch instruction.
1248 EntrySize = codeview::JumpTableEntrySize::UInt8ShiftLeft;
1249 BranchLabel = GetCPISymbol(CPID: BranchInstr->getOperand(i: 3).getImm());
1250 BaseLabel = BranchLabel;
1251 BaseOffset = 4;
1252 break;
1253 case ARM::t2BR_JT:
1254 // Direct jump.
1255 BaseLabel = nullptr;
1256 EntrySize = codeview::JumpTableEntrySize::Pointer;
1257 break;
1258 default:
1259 llvm_unreachable("Unknown jump table instruction");
1260 }
1261
1262 return std::make_tuple(args&: BaseLabel, args&: BaseOffset, args&: BranchLabel, args&: EntrySize);
1263}
1264
1265void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1266 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1267 "Only instruction which are involved into frame setup code are allowed");
1268
1269 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1270 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1271 const MachineFunction &MF = *MI->getParent()->getParent();
1272 const TargetRegisterInfo *TargetRegInfo =
1273 MF.getSubtarget().getRegisterInfo();
1274 const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1275
1276 Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1277 unsigned Opc = MI->getOpcode();
1278 unsigned SrcReg, DstReg;
1279
1280 switch (Opc) {
1281 case ARM::tPUSH:
1282 // special case: tPUSH does not have src/dst regs.
1283 SrcReg = DstReg = ARM::SP;
1284 break;
1285 case ARM::tLDRpci:
1286 case ARM::t2MOVi16:
1287 case ARM::t2MOVTi16:
1288 case ARM::tMOVi8:
1289 case ARM::tADDi8:
1290 case ARM::tLSLri:
1291 // special cases:
1292 // 1) for Thumb1 code we sometimes materialize the constant via constpool
1293 // load.
1294 // 2) for Thumb1 execute only code we materialize the constant via the
1295 // following pattern:
1296 // movs r3, #:upper8_15:<const>
1297 // lsls r3, #8
1298 // adds r3, #:upper0_7:<const>
1299 // lsls r3, #8
1300 // adds r3, #:lower8_15:<const>
1301 // lsls r3, #8
1302 // adds r3, #:lower0_7:<const>
1303 // So we need to special-case MOVS, ADDS and LSLS, and keep track of
1304 // where we are in the sequence with the simplest of state machines.
1305 // 3) for Thumb2 execute only code we materialize the constant via
1306 // immediate constants in 2 separate instructions (MOVW/MOVT).
1307 SrcReg = ~0U;
1308 DstReg = MI->getOperand(i: 0).getReg();
1309 break;
1310 case ARM::VMRS:
1311 SrcReg = ARM::FPSCR;
1312 DstReg = MI->getOperand(i: 0).getReg();
1313 break;
1314 case ARM::VMRS_FPEXC:
1315 SrcReg = ARM::FPEXC;
1316 DstReg = MI->getOperand(i: 0).getReg();
1317 break;
1318 default:
1319 SrcReg = MI->getOperand(i: 1).getReg();
1320 DstReg = MI->getOperand(i: 0).getReg();
1321 break;
1322 }
1323
1324 // Try to figure out the unwinding opcode out of src / dst regs.
1325 if (MI->mayStore()) {
1326 // Register saves.
1327 assert(DstReg == ARM::SP &&
1328 "Only stack pointer as a destination reg is supported");
1329
1330 SmallVector<MCRegister, 4> RegList;
1331 // Skip src & dst reg, and pred ops.
1332 unsigned StartOp = 2 + 2;
1333 // Use all the operands.
1334 unsigned NumOffset = 0;
1335 // Amount of SP adjustment folded into a push, before the
1336 // registers are stored (pad at higher addresses).
1337 unsigned PadBefore = 0;
1338 // Amount of SP adjustment folded into a push, after the
1339 // registers are stored (pad at lower addresses).
1340 unsigned PadAfter = 0;
1341
1342 switch (Opc) {
1343 default:
1344 MI->print(OS&: errs());
1345 llvm_unreachable("Unsupported opcode for unwinding information");
1346 case ARM::tPUSH:
1347 // Special case here: no src & dst reg, but two extra imp ops.
1348 StartOp = 2; NumOffset = 2;
1349 [[fallthrough]];
1350 case ARM::STMDB_UPD:
1351 case ARM::t2STMDB_UPD:
1352 case ARM::VSTMDDB_UPD:
1353 assert(SrcReg == ARM::SP &&
1354 "Only stack pointer as a source reg is supported");
1355 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1356 i != NumOps; ++i) {
1357 const MachineOperand &MO = MI->getOperand(i);
1358 // Actually, there should never be any impdef stuff here. Skip it
1359 // temporary to workaround PR11902.
1360 if (MO.isImplicit())
1361 continue;
1362 // Registers, pushed as a part of folding an SP update into the
1363 // push instruction are marked as undef and should not be
1364 // restored when unwinding, because the function can modify the
1365 // corresponding stack slots.
1366 if (MO.isUndef()) {
1367 assert(RegList.empty() &&
1368 "Pad registers must come before restored ones");
1369 unsigned Width =
1370 TargetRegInfo->getRegSizeInBits(Reg: MO.getReg(), MRI: MachineRegInfo) / 8;
1371 PadAfter += Width;
1372 continue;
1373 }
1374 // Check for registers that are remapped (for a Thumb1 prologue that
1375 // saves high registers).
1376 Register Reg = MO.getReg();
1377 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: Reg))
1378 Reg = RemappedReg;
1379 RegList.push_back(Elt: Reg);
1380 }
1381 break;
1382 case ARM::STR_PRE_IMM:
1383 case ARM::STR_PRE_REG:
1384 case ARM::t2STR_PRE:
1385 assert(MI->getOperand(2).getReg() == ARM::SP &&
1386 "Only stack pointer as a source reg is supported");
1387 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1388 SrcReg = RemappedReg;
1389
1390 RegList.push_back(Elt: SrcReg);
1391 break;
1392 case ARM::t2STRD_PRE:
1393 assert(MI->getOperand(3).getReg() == ARM::SP &&
1394 "Only stack pointer as a source reg is supported");
1395 SrcReg = MI->getOperand(i: 1).getReg();
1396 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1397 SrcReg = RemappedReg;
1398 RegList.push_back(Elt: SrcReg);
1399 SrcReg = MI->getOperand(i: 2).getReg();
1400 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Val: SrcReg))
1401 SrcReg = RemappedReg;
1402 RegList.push_back(Elt: SrcReg);
1403 PadBefore = -MI->getOperand(i: 4).getImm() - 8;
1404 break;
1405 }
1406 if (MAI.getExceptionHandlingType() == ExceptionHandling::ARM) {
1407 if (PadBefore)
1408 ATS.emitPad(Offset: PadBefore);
1409 ATS.emitRegSave(RegList, isVector: Opc == ARM::VSTMDDB_UPD);
1410 // Account for the SP adjustment, folded into the push.
1411 if (PadAfter)
1412 ATS.emitPad(Offset: PadAfter);
1413 }
1414 } else {
1415 // Changes of stack / frame pointer.
1416 if (SrcReg == ARM::SP) {
1417 int64_t Offset = 0;
1418 switch (Opc) {
1419 default:
1420 MI->print(OS&: errs());
1421 llvm_unreachable("Unsupported opcode for unwinding information");
1422 case ARM::tLDRspi:
1423 // Used to restore LR in a prologue which uses it as a temporary, has
1424 // no effect on unwind tables.
1425 return;
1426 case ARM::MOVr:
1427 case ARM::tMOVr:
1428 Offset = 0;
1429 break;
1430 case ARM::ADDri:
1431 case ARM::t2ADDri:
1432 case ARM::t2ADDri12:
1433 case ARM::t2ADDspImm:
1434 case ARM::t2ADDspImm12:
1435 Offset = -MI->getOperand(i: 2).getImm();
1436 break;
1437 case ARM::SUBri:
1438 case ARM::t2SUBri:
1439 case ARM::t2SUBri12:
1440 case ARM::t2SUBspImm:
1441 case ARM::t2SUBspImm12:
1442 Offset = MI->getOperand(i: 2).getImm();
1443 break;
1444 case ARM::tSUBspi:
1445 Offset = MI->getOperand(i: 2).getImm()*4;
1446 break;
1447 case ARM::tADDspi:
1448 case ARM::tADDrSPi:
1449 Offset = -MI->getOperand(i: 2).getImm()*4;
1450 break;
1451 case ARM::tADDhirr:
1452 Offset =
1453 -AFI->EHPrologueOffsetInRegs.lookup(Val: MI->getOperand(i: 2).getReg());
1454 break;
1455 }
1456
1457 if (MAI.getExceptionHandlingType() == ExceptionHandling::ARM) {
1458 if (DstReg == FramePtr && FramePtr != ARM::SP)
1459 // Set-up of the frame pointer. Positive values correspond to "add"
1460 // instruction.
1461 ATS.emitSetFP(FpReg: FramePtr, SpReg: ARM::SP, Offset: -Offset);
1462 else if (DstReg == ARM::SP) {
1463 // Change of SP by an offset. Positive values correspond to "sub"
1464 // instruction.
1465 ATS.emitPad(Offset);
1466 } else {
1467 // Move of SP to a register. Positive values correspond to an "add"
1468 // instruction.
1469 ATS.emitMovSP(Reg: DstReg, Offset: -Offset);
1470 }
1471 }
1472 } else if (DstReg == ARM::SP) {
1473 MI->print(OS&: errs());
1474 llvm_unreachable("Unsupported opcode for unwinding information");
1475 } else {
1476 int64_t Offset = 0;
1477 switch (Opc) {
1478 case ARM::tMOVr:
1479 // If a Thumb1 function spills r8-r11, we copy the values to low
1480 // registers before pushing them. Record the copy so we can emit the
1481 // correct ".save" later.
1482 AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1483 break;
1484 case ARM::VMRS:
1485 case ARM::VMRS_FPEXC:
1486 // If a function spills FPSCR or FPEXC, we copy the values to low
1487 // registers before pushing them. However, we can't issue annotations
1488 // for FP status registers because ".save" requires GPR registers, and
1489 // ".vsave" requires DPR registers, so don't record the copy and simply
1490 // emit annotations for the source registers used for the store.
1491 break;
1492 case ARM::tLDRpci: {
1493 // Grab the constpool index and check, whether it corresponds to
1494 // original or cloned constpool entry.
1495 unsigned CPI = MI->getOperand(i: 1).getIndex();
1496 const MachineConstantPool *MCP = MF.getConstantPool();
1497 if (CPI >= MCP->getConstants().size())
1498 CPI = AFI->getOriginalCPIdx(CloneIdx: CPI);
1499 assert(CPI != -1U && "Invalid constpool index");
1500
1501 // Derive the actual offset.
1502 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1503 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1504 Offset = cast<ConstantInt>(Val: CPE.Val.ConstVal)->getSExtValue();
1505 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1506 break;
1507 }
1508 case ARM::t2MOVi16:
1509 Offset = MI->getOperand(i: 1).getImm();
1510 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1511 break;
1512 case ARM::t2MOVTi16:
1513 Offset = MI->getOperand(i: 2).getImm();
1514 AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1515 break;
1516 case ARM::tMOVi8:
1517 Offset = MI->getOperand(i: 2).getImm();
1518 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1519 break;
1520 case ARM::tLSLri:
1521 assert(MI->getOperand(3).getImm() == 8 &&
1522 "The shift amount is not equal to 8");
1523 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1524 "The source register is not equal to the destination register");
1525 AFI->EHPrologueOffsetInRegs[DstReg] <<= 8;
1526 break;
1527 case ARM::tADDi8:
1528 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1529 "The source register is not equal to the destination register");
1530 Offset = MI->getOperand(i: 3).getImm();
1531 AFI->EHPrologueOffsetInRegs[DstReg] += Offset;
1532 break;
1533 case ARM::t2PAC:
1534 case ARM::t2PACBTI:
1535 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1536 break;
1537 default:
1538 MI->print(OS&: errs());
1539 llvm_unreachable("Unsupported opcode for unwinding information");
1540 }
1541 }
1542 }
1543}
1544
1545// Simple pseudo-instructions have their lowering (with expansion to real
1546// instructions) auto-generated.
1547#include "ARMGenMCPseudoLowering.inc"
1548
1549// Helper function to check if a register is live (used as an implicit operand)
1550// in the given call instruction.
1551static bool isRegisterLiveInCall(const MachineInstr &Call, MCRegister Reg) {
1552 for (const MachineOperand &MO : Call.implicit_operands()) {
1553 if (MO.isReg() && MO.getReg() == Reg && MO.isUse()) {
1554 return true;
1555 }
1556 }
1557 return false;
1558}
1559
1560void ARMAsmPrinter::EmitKCFI_CHECK_ARM32(Register AddrReg, int64_t Type,
1561 const MachineInstr &Call,
1562 int64_t PrefixNops) {
1563 // Choose scratch register: r12 primary, r3 if target is r12.
1564 unsigned ScratchReg = ARM::R12;
1565 if (AddrReg == ARM::R12) {
1566 ScratchReg = ARM::R3;
1567 }
1568
1569 // Calculate ESR for ARM mode (16-bit): 0x8000 | (scratch_reg << 5) | addr_reg
1570 // Note: scratch_reg is always 0x1F since the EOR sequence clobbers it.
1571 const ARMBaseRegisterInfo *TRI = static_cast<const ARMBaseRegisterInfo *>(
1572 MF->getSubtarget().getRegisterInfo());
1573 unsigned AddrIndex = TRI->getEncodingValue(Reg: AddrReg);
1574 unsigned ESR = 0x8000 | (31 << 5) | (AddrIndex & 31);
1575
1576 // Check if r3 is live and needs to be spilled.
1577 bool NeedSpillR3 =
1578 (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, Reg: ARM::R3);
1579
1580 // If we need to spill r3, push it first.
1581 if (NeedSpillR3) {
1582 // push {r3}
1583 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::STMDB_UPD)
1584 .addReg(Reg: ARM::SP)
1585 .addReg(Reg: ARM::SP)
1586 .addImm(Val: ARMCC::AL)
1587 .addReg(Reg: 0)
1588 .addReg(Reg: ARM::R3));
1589 }
1590
1591 // Clear bit 0 of target address to handle Thumb function pointers.
1592 // In 32-bit ARM, function pointers may have the low bit set to indicate
1593 // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later).
1594 // We need to clear it to avoid an alignment fault when loading.
1595 // bic scratch, target, #1
1596 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::BICri)
1597 .addReg(Reg: ScratchReg)
1598 .addReg(Reg: AddrReg)
1599 .addImm(Val: 1)
1600 .addImm(Val: ARMCC::AL)
1601 .addReg(Reg: 0)
1602 .addReg(Reg: 0));
1603
1604 // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)]
1605 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
1606 .addReg(Reg: ScratchReg)
1607 .addReg(Reg: ScratchReg)
1608 .addImm(Val: -(PrefixNops * 4 + 4))
1609 .addImm(Val: ARMCC::AL)
1610 .addReg(Reg: 0));
1611
1612 // Each EOR instruction XORs one byte of the type, shifted to its position.
1613 for (int i = 0; i < 4; i++) {
1614 uint8_t byte = (Type >> (i * 8)) & 0xFF;
1615 uint32_t imm = byte << (i * 8);
1616 bool isLast = (i == 3);
1617
1618 // Encode as ARM modified immediate.
1619 int SOImmVal = ARM_AM::getSOImmVal(Arg: imm);
1620 assert(SOImmVal != -1 &&
1621 "Cannot encode immediate as ARM modified immediate");
1622
1623 // eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
1624 EmitToStreamer(S&: *OutStreamer,
1625 Inst: MCInstBuilder(ARM::EORri)
1626 .addReg(Reg: ScratchReg)
1627 .addReg(Reg: ScratchReg)
1628 .addImm(Val: SOImmVal)
1629 .addImm(Val: ARMCC::AL)
1630 .addReg(Reg: 0)
1631 .addReg(Reg: isLast ? ARM::CPSR : ARM::NoRegister));
1632 }
1633
1634 // If we spilled r3, restore it immediately after the comparison.
1635 // This must happen before the branch so r3 is valid on both paths.
1636 if (NeedSpillR3) {
1637 // pop {r3}
1638 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDMIA_UPD)
1639 .addReg(Reg: ARM::SP)
1640 .addReg(Reg: ARM::SP)
1641 .addImm(Val: ARMCC::AL)
1642 .addReg(Reg: 0)
1643 .addReg(Reg: ARM::R3));
1644 }
1645
1646 // beq .Lpass (branch if types match, i.e., scratch is zero)
1647 MCSymbol *Pass = OutContext.createTempSymbol();
1648 EmitToStreamer(S&: *OutStreamer,
1649 Inst: MCInstBuilder(ARM::Bcc)
1650 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1651 .addImm(Val: ARMCC::EQ)
1652 .addReg(Reg: ARM::CPSR));
1653
1654 // udf #ESR (trap with encoded diagnostic)
1655 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::UDF).addImm(Val: ESR));
1656
1657 OutStreamer->emitLabel(Symbol: Pass);
1658}
1659
1660void ARMAsmPrinter::EmitKCFI_CHECK_Thumb2(Register AddrReg, int64_t Type,
1661 const MachineInstr &Call,
1662 int64_t PrefixNops) {
1663 // Choose scratch register: r12 primary, r3 if target is r12.
1664 unsigned ScratchReg = ARM::R12;
1665 if (AddrReg == ARM::R12) {
1666 ScratchReg = ARM::R3;
1667 }
1668
1669 // Calculate ESR for Thumb mode (8-bit): 0x80 | addr_reg
1670 // Bit 7: KCFI trap indicator
1671 // Bits 6-5: Reserved
1672 // Bits 4-0: Address register encoding
1673 const ARMBaseRegisterInfo *TRI = static_cast<const ARMBaseRegisterInfo *>(
1674 MF->getSubtarget().getRegisterInfo());
1675 unsigned AddrIndex = TRI->getEncodingValue(Reg: AddrReg);
1676 unsigned ESR = 0x80 | (AddrIndex & 0x1F);
1677
1678 // Check if r3 is live and needs to be spilled.
1679 bool NeedSpillR3 =
1680 (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, Reg: ARM::R3);
1681
1682 // If we need to spill r3, push it first.
1683 if (NeedSpillR3) {
1684 // push {r3}
1685 EmitToStreamer(
1686 S&: *OutStreamer,
1687 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1688 }
1689
1690 // Clear bit 0 of target address to handle Thumb function pointers.
1691 // In 32-bit ARM, function pointers may have the low bit set to indicate
1692 // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later).
1693 // We need to clear it to avoid an alignment fault when loading.
1694 // bic scratch, target, #1
1695 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2BICri)
1696 .addReg(Reg: ScratchReg)
1697 .addReg(Reg: AddrReg)
1698 .addImm(Val: 1)
1699 .addImm(Val: ARMCC::AL)
1700 .addReg(Reg: 0)
1701 .addReg(Reg: 0));
1702
1703 // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)]
1704 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi8)
1705 .addReg(Reg: ScratchReg)
1706 .addReg(Reg: ScratchReg)
1707 .addImm(Val: -(PrefixNops * 4 + 4))
1708 .addImm(Val: ARMCC::AL)
1709 .addReg(Reg: 0));
1710
1711 // Each EOR instruction XORs one byte of the type, shifted to its position.
1712 for (int i = 0; i < 4; i++) {
1713 uint8_t byte = (Type >> (i * 8)) & 0xFF;
1714 uint32_t imm = byte << (i * 8);
1715 bool isLast = (i == 3);
1716
1717 // Verify the immediate can be encoded as Thumb2 modified immediate.
1718 assert(ARM_AM::getT2SOImmVal(imm) != -1 &&
1719 "Cannot encode immediate as Thumb2 modified immediate");
1720
1721 // eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
1722 EmitToStreamer(S&: *OutStreamer,
1723 Inst: MCInstBuilder(ARM::t2EORri)
1724 .addReg(Reg: ScratchReg)
1725 .addReg(Reg: ScratchReg)
1726 .addImm(Val: imm)
1727 .addImm(Val: ARMCC::AL)
1728 .addReg(Reg: 0)
1729 .addReg(Reg: isLast ? ARM::CPSR : ARM::NoRegister));
1730 }
1731
1732 // If we spilled r3, restore it immediately after the comparison.
1733 // This must happen before the branch so r3 is valid on both paths.
1734 if (NeedSpillR3) {
1735 // pop {r3}
1736 EmitToStreamer(
1737 S&: *OutStreamer,
1738 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1739 }
1740
1741 // beq .Lpass (branch if types match, i.e., scratch is zero)
1742 MCSymbol *Pass = OutContext.createTempSymbol();
1743 EmitToStreamer(S&: *OutStreamer,
1744 Inst: MCInstBuilder(ARM::t2Bcc)
1745 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1746 .addImm(Val: ARMCC::EQ)
1747 .addReg(Reg: ARM::CPSR));
1748
1749 // udf #ESR (trap with encoded diagnostic)
1750 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tUDF).addImm(Val: ESR));
1751
1752 OutStreamer->emitLabel(Symbol: Pass);
1753}
1754
1755void ARMAsmPrinter::EmitKCFI_CHECK_Thumb1(Register AddrReg, int64_t Type,
1756 const MachineInstr &Call,
1757 int64_t PrefixNops) {
1758 // For Thumb1, use R2 unconditionally as scratch register (a low register
1759 // required for tLDRi). R3 is used for building the type hash.
1760 unsigned ScratchReg = ARM::R2;
1761 unsigned TempReg = ARM::R3;
1762
1763 // Check if r3 is live and needs to be spilled.
1764 bool NeedSpillR3 = isRegisterLiveInCall(Call, Reg: ARM::R3);
1765
1766 // Spill r3 if needed
1767 if (NeedSpillR3) {
1768 EmitToStreamer(
1769 S&: *OutStreamer,
1770 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1771 }
1772
1773 // Check if r2 is live and needs to be spilled.
1774 bool NeedSpillR2 = isRegisterLiveInCall(Call, Reg: ARM::R2);
1775
1776 // Push R2 if it's live
1777 if (NeedSpillR2) {
1778 EmitToStreamer(
1779 S&: *OutStreamer,
1780 Inst: MCInstBuilder(ARM::tPUSH).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R2));
1781 }
1782
1783 // Clear bit 0 from target address
1784 // TempReg (R3) is used first as helper for BIC, then later for building type
1785 // hash.
1786
1787 // movs temp, #1
1788 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
1789 .addReg(Reg: TempReg)
1790 .addReg(Reg: ARM::CPSR)
1791 .addImm(Val: 1)
1792 .addImm(Val: ARMCC::AL)
1793 .addReg(Reg: 0));
1794
1795 // mov scratch, target
1796 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
1797 .addReg(Reg: ScratchReg)
1798 .addReg(Reg: AddrReg)
1799 .addImm(Val: ARMCC::AL));
1800
1801 // bics scratch, temp (scratch = scratch & ~temp)
1802 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBIC)
1803 .addReg(Reg: ScratchReg)
1804 .addReg(Reg: ARM::CPSR)
1805 .addReg(Reg: ScratchReg)
1806 .addReg(Reg: TempReg)
1807 .addImm(Val: ARMCC::AL)
1808 .addReg(Reg: 0));
1809
1810 // Load type hash. Thumb1 doesn't support negative offsets, so subtract.
1811 int offset = PrefixNops * 4 + 4;
1812
1813 // subs scratch, #offset
1814 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tSUBi8)
1815 .addReg(Reg: ScratchReg)
1816 .addReg(Reg: ARM::CPSR)
1817 .addReg(Reg: ScratchReg)
1818 .addImm(Val: offset)
1819 .addImm(Val: ARMCC::AL)
1820 .addReg(Reg: 0));
1821
1822 // ldr scratch, [scratch, #0]
1823 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
1824 .addReg(Reg: ScratchReg)
1825 .addReg(Reg: ScratchReg)
1826 .addImm(Val: 0)
1827 .addImm(Val: ARMCC::AL)
1828 .addReg(Reg: 0));
1829
1830 // Load expected type inline (instead of EOR sequence)
1831 //
1832 // This creates the 32-bit value byte-by-byte in the temp register:
1833 // movs temp, #byte3 (high byte)
1834 // lsls temp, temp, #8
1835 // adds temp, #byte2
1836 // lsls temp, temp, #8
1837 // adds temp, #byte1
1838 // lsls temp, temp, #8
1839 // adds temp, #byte0 (low byte)
1840
1841 uint8_t byte0 = (Type >> 0) & 0xFF;
1842 uint8_t byte1 = (Type >> 8) & 0xFF;
1843 uint8_t byte2 = (Type >> 16) & 0xFF;
1844 uint8_t byte3 = (Type >> 24) & 0xFF;
1845
1846 // movs temp, #byte3 (start with high byte)
1847 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
1848 .addReg(Reg: TempReg)
1849 .addReg(Reg: ARM::CPSR)
1850 .addImm(Val: byte3)
1851 .addImm(Val: ARMCC::AL)
1852 .addReg(Reg: 0));
1853
1854 // lsls temp, temp, #8
1855 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1856 .addReg(Reg: TempReg)
1857 .addReg(Reg: ARM::CPSR)
1858 .addReg(Reg: TempReg)
1859 .addImm(Val: 8)
1860 .addImm(Val: ARMCC::AL)
1861 .addReg(Reg: 0));
1862
1863 // adds temp, #byte2
1864 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1865 .addReg(Reg: TempReg)
1866 .addReg(Reg: ARM::CPSR)
1867 .addReg(Reg: TempReg)
1868 .addImm(Val: byte2)
1869 .addImm(Val: ARMCC::AL)
1870 .addReg(Reg: 0));
1871
1872 // lsls temp, temp, #8
1873 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1874 .addReg(Reg: TempReg)
1875 .addReg(Reg: ARM::CPSR)
1876 .addReg(Reg: TempReg)
1877 .addImm(Val: 8)
1878 .addImm(Val: ARMCC::AL)
1879 .addReg(Reg: 0));
1880
1881 // adds temp, #byte1
1882 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1883 .addReg(Reg: TempReg)
1884 .addReg(Reg: ARM::CPSR)
1885 .addReg(Reg: TempReg)
1886 .addImm(Val: byte1)
1887 .addImm(Val: ARMCC::AL)
1888 .addReg(Reg: 0));
1889
1890 // lsls temp, temp, #8
1891 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
1892 .addReg(Reg: TempReg)
1893 .addReg(Reg: ARM::CPSR)
1894 .addReg(Reg: TempReg)
1895 .addImm(Val: 8)
1896 .addImm(Val: ARMCC::AL)
1897 .addReg(Reg: 0));
1898
1899 // adds temp, #byte0 (low byte)
1900 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi8)
1901 .addReg(Reg: TempReg)
1902 .addReg(Reg: ARM::CPSR)
1903 .addReg(Reg: TempReg)
1904 .addImm(Val: byte0)
1905 .addImm(Val: ARMCC::AL)
1906 .addReg(Reg: 0));
1907
1908 // cmp scratch, temp
1909 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tCMPr)
1910 .addReg(Reg: ScratchReg)
1911 .addReg(Reg: TempReg)
1912 .addImm(Val: ARMCC::AL)
1913 .addReg(Reg: 0));
1914
1915 // Restore registers if spilled (pop in reverse order of push: R2, then R3)
1916 if (NeedSpillR2) {
1917 // pop {r2}
1918 EmitToStreamer(
1919 S&: *OutStreamer,
1920 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R2));
1921 }
1922
1923 // Restore r3 if spilled
1924 if (NeedSpillR3) {
1925 // pop {r3}
1926 EmitToStreamer(
1927 S&: *OutStreamer,
1928 Inst: MCInstBuilder(ARM::tPOP).addImm(Val: ARMCC::AL).addReg(Reg: 0).addReg(Reg: ARM::R3));
1929 }
1930
1931 // beq .Lpass (branch if types match, i.e., scratch == temp)
1932 MCSymbol *Pass = OutContext.createTempSymbol();
1933 EmitToStreamer(S&: *OutStreamer,
1934 Inst: MCInstBuilder(ARM::tBcc)
1935 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
1936 .addImm(Val: ARMCC::EQ)
1937 .addReg(Reg: ARM::CPSR));
1938
1939 // bkpt #0 (trap with encoded diagnostic)
1940 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBKPT).addImm(Val: 0));
1941
1942 OutStreamer->emitLabel(Symbol: Pass);
1943}
1944
1945void ARMAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
1946 Register AddrReg = MI.getOperand(i: 0).getReg();
1947 const int64_t Type = MI.getOperand(i: 1).getImm();
1948
1949 // Get the call instruction that follows this KCFI_CHECK.
1950 assert(std::next(MI.getIterator())->isCall() &&
1951 "KCFI_CHECK not followed by a call instruction");
1952 const MachineInstr &Call = *std::next(x: MI.getIterator());
1953
1954 // Adjust the offset for patchable-function-prefix.
1955 int64_t PrefixNops = MI.getMF()->getFunction().getFnAttributeAsParsedInteger(
1956 Kind: "patchable-function-prefix");
1957
1958 // Emit the appropriate instruction sequence based on the opcode variant.
1959 switch (MI.getOpcode()) {
1960 case ARM::KCFI_CHECK_ARM:
1961 EmitKCFI_CHECK_ARM32(AddrReg, Type, Call, PrefixNops);
1962 break;
1963 case ARM::KCFI_CHECK_Thumb2:
1964 EmitKCFI_CHECK_Thumb2(AddrReg, Type, Call, PrefixNops);
1965 break;
1966 case ARM::KCFI_CHECK_Thumb1:
1967 EmitKCFI_CHECK_Thumb1(AddrReg, Type, Call, PrefixNops);
1968 break;
1969 default:
1970 llvm_unreachable("Unexpected KCFI_CHECK opcode");
1971 }
1972}
1973
1974void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
1975 ARM_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
1976 Features: getSubtargetInfo().getFeatureBits());
1977
1978 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
1979 const DataLayout &DL = getDataLayout();
1980 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1981 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1982
1983 // If we just ended a constant pool, mark it as such.
1984 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1985 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
1986 InConstantPool = false;
1987 }
1988
1989 // Emit unwinding stuff for frame-related instructions
1990 if (TM.getTargetTriple().isTargetEHABICompatible() &&
1991 MI->getFlag(Flag: MachineInstr::FrameSetup))
1992 EmitUnwindingInstruction(MI);
1993
1994 // Do any auto-generated pseudo lowerings.
1995 if (MCInst OutInst; lowerPseudoInstExpansion(MI, Inst&: OutInst)) {
1996 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
1997 return;
1998 }
1999
2000 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
2001 "Pseudo flag setting opcode should be expanded early");
2002
2003 // Check for manual lowerings.
2004 unsigned Opc = MI->getOpcode();
2005 switch (Opc) {
2006 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
2007 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
2008 case ARM::KCFI_CHECK_ARM:
2009 case ARM::KCFI_CHECK_Thumb2:
2010 case ARM::KCFI_CHECK_Thumb1:
2011 LowerKCFI_CHECK(MI: *MI);
2012 return;
2013 case ARM::LEApcrel:
2014 case ARM::tLEApcrel:
2015 case ARM::t2LEApcrel: {
2016 // FIXME: Need to also handle globals and externals
2017 MCSymbol *CPISymbol = GetCPISymbol(CPID: MI->getOperand(i: 1).getIndex());
2018 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(MI->getOpcode() ==
2019 ARM::t2LEApcrel ? ARM::t2ADR
2020 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
2021 : ARM::ADR))
2022 .addReg(Reg: MI->getOperand(i: 0).getReg())
2023 .addExpr(Val: MCSymbolRefExpr::create(Symbol: CPISymbol, Ctx&: OutContext))
2024 // Add predicate operands.
2025 .addImm(Val: MI->getOperand(i: 2).getImm())
2026 .addReg(Reg: MI->getOperand(i: 3).getReg()));
2027 return;
2028 }
2029 case ARM::LEApcrelJT:
2030 case ARM::tLEApcrelJT:
2031 case ARM::t2LEApcrelJT: {
2032 MCSymbol *JTIPICSymbol =
2033 GetARMJTIPICJumpTableLabel(uid: MI->getOperand(i: 1).getIndex());
2034 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(MI->getOpcode() ==
2035 ARM::t2LEApcrelJT ? ARM::t2ADR
2036 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
2037 : ARM::ADR))
2038 .addReg(Reg: MI->getOperand(i: 0).getReg())
2039 .addExpr(Val: MCSymbolRefExpr::create(Symbol: JTIPICSymbol, Ctx&: OutContext))
2040 // Add predicate operands.
2041 .addImm(Val: MI->getOperand(i: 2).getImm())
2042 .addReg(Reg: MI->getOperand(i: 3).getReg()));
2043 return;
2044 }
2045 // Darwin call instructions are just normal call instructions with different
2046 // clobber semantics (they clobber R9).
2047 case ARM::BX_CALL: {
2048 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2049 .addReg(Reg: ARM::LR)
2050 .addReg(Reg: ARM::PC)
2051 // Add predicate operands.
2052 .addImm(Val: ARMCC::AL)
2053 .addReg(Reg: 0)
2054 // Add 's' bit operand (always reg0 for this)
2055 .addReg(Reg: 0));
2056
2057 assert(STI.hasV4TOps() && "Expected V4TOps for BX call");
2058 EmitToStreamer(S&: *OutStreamer,
2059 Inst: MCInstBuilder(ARM::BX).addReg(Reg: MI->getOperand(i: 0).getReg()));
2060 return;
2061 }
2062 case ARM::tBX_CALL: {
2063 assert(!STI.hasV5TOps() && "Expected BLX to be selected for v5t+");
2064
2065 // On ARM v4t, when doing a call from thumb mode, we need to ensure
2066 // that the saved lr has its LSB set correctly (the arch doesn't
2067 // have blx).
2068 // So here we generate a bl to a small jump pad that does bx rN.
2069 // The jump pads are emitted after the function body.
2070
2071 Register TReg = MI->getOperand(i: 0).getReg();
2072 MCSymbol *TRegSym = nullptr;
2073 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
2074 if (TIP.first == TReg) {
2075 TRegSym = TIP.second;
2076 break;
2077 }
2078 }
2079
2080 if (!TRegSym) {
2081 TRegSym = OutContext.createTempSymbol();
2082 ThumbIndirectPads.push_back(Elt: std::make_pair(x&: TReg, y&: TRegSym));
2083 }
2084
2085 // Create a link-saving branch to the Reg Indirect Jump Pad.
2086 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBL)
2087 // Predicate comes first here.
2088 .addImm(Val: ARMCC::AL).addReg(Reg: 0)
2089 .addExpr(Val: MCSymbolRefExpr::create(Symbol: TRegSym, Ctx&: OutContext)));
2090 return;
2091 }
2092 case ARM::BMOVPCRX_CALL: {
2093 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2094 .addReg(Reg: ARM::LR)
2095 .addReg(Reg: ARM::PC)
2096 // Add predicate operands.
2097 .addImm(Val: ARMCC::AL)
2098 .addReg(Reg: 0)
2099 // Add 's' bit operand (always reg0 for this)
2100 .addReg(Reg: 0));
2101
2102 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2103 .addReg(Reg: ARM::PC)
2104 .addReg(Reg: MI->getOperand(i: 0).getReg())
2105 // Add predicate operands.
2106 .addImm(Val: ARMCC::AL)
2107 .addReg(Reg: 0)
2108 // Add 's' bit operand (always reg0 for this)
2109 .addReg(Reg: 0));
2110 return;
2111 }
2112 case ARM::BMOVPCB_CALL: {
2113 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVr)
2114 .addReg(Reg: ARM::LR)
2115 .addReg(Reg: ARM::PC)
2116 // Add predicate operands.
2117 .addImm(Val: ARMCC::AL)
2118 .addReg(Reg: 0)
2119 // Add 's' bit operand (always reg0 for this)
2120 .addReg(Reg: 0));
2121
2122 const MachineOperand &Op = MI->getOperand(i: 0);
2123 const GlobalValue *GV = Op.getGlobal();
2124 const unsigned TF = Op.getTargetFlags();
2125 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2126 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2127 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::Bcc)
2128 .addExpr(Val: GVSymExpr)
2129 // Add predicate operands.
2130 .addImm(Val: ARMCC::AL)
2131 .addReg(Reg: 0));
2132 return;
2133 }
2134 case ARM::MOVi16_ga_pcrel:
2135 case ARM::t2MOVi16_ga_pcrel: {
2136 MCInst TmpInst;
2137 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
2138 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2139
2140 unsigned TF = MI->getOperand(i: 1).getTargetFlags();
2141 const GlobalValue *GV = MI->getOperand(i: 1).getGlobal();
2142 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2143 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2144
2145 MCSymbol *LabelSym =
2146 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2147 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext);
2148 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(Symbol: LabelSym, Ctx&: OutContext);
2149 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
2150 const MCExpr *PCRelExpr = ARM::createLower16(
2151 Expr: MCBinaryExpr::createSub(
2152 LHS: GVSymExpr,
2153 RHS: MCBinaryExpr::createAdd(LHS: LabelSymExpr,
2154 RHS: MCConstantExpr::create(Value: PCAdj, Ctx&: OutContext),
2155 Ctx&: OutContext),
2156 Ctx&: OutContext),
2157 Ctx&: OutContext);
2158 TmpInst.addOperand(Op: MCOperand::createExpr(Val: PCRelExpr));
2159
2160 // Add predicate operands.
2161 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2162 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2163 // Add 's' bit operand (always reg0 for this)
2164 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2165 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2166 return;
2167 }
2168 case ARM::MOVTi16_ga_pcrel:
2169 case ARM::t2MOVTi16_ga_pcrel: {
2170 MCInst TmpInst;
2171 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
2172 ? ARM::MOVTi16 : ARM::t2MOVTi16);
2173 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2174 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 1).getReg()));
2175
2176 unsigned TF = MI->getOperand(i: 2).getTargetFlags();
2177 const GlobalValue *GV = MI->getOperand(i: 2).getGlobal();
2178 MCSymbol *GVSym = GetARMGVSymbol(GV, TargetFlags: TF);
2179 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(Symbol: GVSym, Ctx&: OutContext);
2180
2181 MCSymbol *LabelSym =
2182 getPICLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2183 LabelId: MI->getOperand(i: 3).getImm(), Ctx&: OutContext);
2184 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(Symbol: LabelSym, Ctx&: OutContext);
2185 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
2186 const MCExpr *PCRelExpr = ARM::createUpper16(
2187 Expr: MCBinaryExpr::createSub(
2188 LHS: GVSymExpr,
2189 RHS: MCBinaryExpr::createAdd(LHS: LabelSymExpr,
2190 RHS: MCConstantExpr::create(Value: PCAdj, Ctx&: OutContext),
2191 Ctx&: OutContext),
2192 Ctx&: OutContext),
2193 Ctx&: OutContext);
2194 TmpInst.addOperand(Op: MCOperand::createExpr(Val: PCRelExpr));
2195 // Add predicate operands.
2196 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2197 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2198 // Add 's' bit operand (always reg0 for this)
2199 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2200 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2201 return;
2202 }
2203 case ARM::t2BFi:
2204 case ARM::t2BFic:
2205 case ARM::t2BFLi:
2206 case ARM::t2BFr:
2207 case ARM::t2BFLr: {
2208 // This is a Branch Future instruction.
2209
2210 const MCExpr *BranchLabel = MCSymbolRefExpr::create(
2211 Symbol: getBFLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2212 LabelId: MI->getOperand(i: 0).getIndex(), Ctx&: OutContext),
2213 Ctx&: OutContext);
2214
2215 auto MCInst = MCInstBuilder(Opc).addExpr(Val: BranchLabel);
2216 if (MI->getOperand(i: 1).isReg()) {
2217 // For BFr/BFLr
2218 MCInst.addReg(Reg: MI->getOperand(i: 1).getReg());
2219 } else {
2220 // For BFi/BFLi/BFic
2221 const MCExpr *BranchTarget;
2222 if (MI->getOperand(i: 1).isMBB())
2223 BranchTarget = MCSymbolRefExpr::create(
2224 Symbol: MI->getOperand(i: 1).getMBB()->getSymbol(), Ctx&: OutContext);
2225 else if (MI->getOperand(i: 1).isGlobal()) {
2226 const GlobalValue *GV = MI->getOperand(i: 1).getGlobal();
2227 BranchTarget = MCSymbolRefExpr::create(
2228 Symbol: GetARMGVSymbol(GV, TargetFlags: MI->getOperand(i: 1).getTargetFlags()), Ctx&: OutContext);
2229 } else if (MI->getOperand(i: 1).isSymbol()) {
2230 BranchTarget = MCSymbolRefExpr::create(
2231 Symbol: GetExternalSymbolSymbol(Sym: MI->getOperand(i: 1).getSymbolName()),
2232 Ctx&: OutContext);
2233 } else
2234 llvm_unreachable("Unhandled operand kind in Branch Future instruction");
2235
2236 MCInst.addExpr(Val: BranchTarget);
2237 }
2238
2239 if (Opc == ARM::t2BFic) {
2240 const MCExpr *ElseLabel = MCSymbolRefExpr::create(
2241 Symbol: getBFLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2242 LabelId: MI->getOperand(i: 2).getIndex(), Ctx&: OutContext),
2243 Ctx&: OutContext);
2244 MCInst.addExpr(Val: ElseLabel);
2245 MCInst.addImm(Val: MI->getOperand(i: 3).getImm());
2246 } else {
2247 MCInst.addImm(Val: MI->getOperand(i: 2).getImm())
2248 .addReg(Reg: MI->getOperand(i: 3).getReg());
2249 }
2250
2251 EmitToStreamer(S&: *OutStreamer, Inst: MCInst);
2252 return;
2253 }
2254 case ARM::t2BF_LabelPseudo: {
2255 // This is a pseudo op for a label used by a branch future instruction
2256
2257 // Emit the label.
2258 OutStreamer->emitLabel(
2259 Symbol: getBFLabel(Prefix: DL.getInternalSymbolPrefix(), FunctionNumber: getFunctionNumber(),
2260 LabelId: MI->getOperand(i: 0).getIndex(), Ctx&: OutContext));
2261 return;
2262 }
2263 case ARM::tPICADD: {
2264 // This is a pseudo op for a label + instruction sequence, which looks like:
2265 // LPC0:
2266 // add r0, pc
2267 // This adds the address of LPC0 to r0.
2268
2269 // Emit the label.
2270 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getInternalSymbolPrefix(),
2271 FunctionNumber: getFunctionNumber(),
2272 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2273
2274 // Form and emit the add.
2275 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2276 .addReg(Reg: MI->getOperand(i: 0).getReg())
2277 .addReg(Reg: MI->getOperand(i: 0).getReg())
2278 .addReg(Reg: ARM::PC)
2279 // Add predicate operands.
2280 .addImm(Val: ARMCC::AL)
2281 .addReg(Reg: 0));
2282 return;
2283 }
2284 case ARM::PICADD: {
2285 // This is a pseudo op for a label + instruction sequence, which looks like:
2286 // LPC0:
2287 // add r0, pc, r0
2288 // This adds the address of LPC0 to r0.
2289
2290 // Emit the label.
2291 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getInternalSymbolPrefix(),
2292 FunctionNumber: getFunctionNumber(),
2293 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2294
2295 // Form and emit the add.
2296 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDrr)
2297 .addReg(Reg: MI->getOperand(i: 0).getReg())
2298 .addReg(Reg: ARM::PC)
2299 .addReg(Reg: MI->getOperand(i: 1).getReg())
2300 // Add predicate operands.
2301 .addImm(Val: MI->getOperand(i: 3).getImm())
2302 .addReg(Reg: MI->getOperand(i: 4).getReg())
2303 // Add 's' bit operand (always reg0 for this)
2304 .addReg(Reg: 0));
2305 return;
2306 }
2307 case ARM::PICSTR:
2308 case ARM::PICSTRB:
2309 case ARM::PICSTRH:
2310 case ARM::PICLDR:
2311 case ARM::PICLDRB:
2312 case ARM::PICLDRH:
2313 case ARM::PICLDRSB:
2314 case ARM::PICLDRSH: {
2315 // This is a pseudo op for a label + instruction sequence, which looks like:
2316 // LPC0:
2317 // OP r0, [pc, r0]
2318 // The LCP0 label is referenced by a constant pool entry in order to get
2319 // a PC-relative address at the ldr instruction.
2320
2321 // Emit the label.
2322 OutStreamer->emitLabel(Symbol: getPICLabel(Prefix: DL.getInternalSymbolPrefix(),
2323 FunctionNumber: getFunctionNumber(),
2324 LabelId: MI->getOperand(i: 2).getImm(), Ctx&: OutContext));
2325
2326 // Form and emit the load
2327 unsigned Opcode;
2328 switch (MI->getOpcode()) {
2329 default:
2330 llvm_unreachable("Unexpected opcode!");
2331 case ARM::PICSTR: Opcode = ARM::STRrs; break;
2332 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
2333 case ARM::PICSTRH: Opcode = ARM::STRH; break;
2334 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
2335 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
2336 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
2337 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
2338 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
2339 }
2340 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opcode)
2341 .addReg(Reg: MI->getOperand(i: 0).getReg())
2342 .addReg(Reg: ARM::PC)
2343 .addReg(Reg: MI->getOperand(i: 1).getReg())
2344 .addImm(Val: 0)
2345 // Add predicate operands.
2346 .addImm(Val: MI->getOperand(i: 3).getImm())
2347 .addReg(Reg: MI->getOperand(i: 4).getReg()));
2348
2349 return;
2350 }
2351 case ARM::CONSTPOOL_ENTRY: {
2352 assert(!STI.genExecuteOnly() &&
2353 "execute-only should not generate constant pools");
2354
2355 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
2356 /// in the function. The first operand is the ID# for this instruction, the
2357 /// second is the index into the MachineConstantPool that this is, the third
2358 /// is the size in bytes of this constant pool entry.
2359 /// The required alignment is specified on the basic block holding this MI.
2360 unsigned LabelId = (unsigned)MI->getOperand(i: 0).getImm();
2361 unsigned CPIdx = (unsigned)MI->getOperand(i: 1).getIndex();
2362
2363 // If this is the first entry of the pool, mark it.
2364 if (!InConstantPool) {
2365 OutStreamer->emitDataRegion(Kind: MCDR_DataRegion);
2366 InConstantPool = true;
2367 }
2368
2369 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: LabelId));
2370
2371 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
2372 if (MCPE.isMachineConstantPoolEntry())
2373 emitMachineConstantPoolValue(MCPV: MCPE.Val.MachineCPVal);
2374 else
2375 emitGlobalConstant(DL, CV: MCPE.Val.ConstVal);
2376 return;
2377 }
2378 case ARM::JUMPTABLE_ADDRS:
2379 emitJumpTableAddrs(MI);
2380 return;
2381 case ARM::JUMPTABLE_INSTS:
2382 emitJumpTableInsts(MI);
2383 return;
2384 case ARM::JUMPTABLE_TBB:
2385 case ARM::JUMPTABLE_TBH:
2386 emitJumpTableTBInst(MI, OffsetWidth: MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
2387 return;
2388 case ARM::t2BR_JT: {
2389 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2390 .addReg(Reg: ARM::PC)
2391 .addReg(Reg: MI->getOperand(i: 0).getReg())
2392 // Add predicate operands.
2393 .addImm(Val: ARMCC::AL)
2394 .addReg(Reg: 0));
2395 return;
2396 }
2397 case ARM::t2TBB_JT:
2398 case ARM::t2TBH_JT: {
2399 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
2400 // Lower and emit the PC label, then the instruction itself.
2401 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: MI->getOperand(i: 3).getImm()));
2402 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2403 .addReg(Reg: MI->getOperand(i: 0).getReg())
2404 .addReg(Reg: MI->getOperand(i: 1).getReg())
2405 // Add predicate operands.
2406 .addImm(Val: ARMCC::AL)
2407 .addReg(Reg: 0));
2408 return;
2409 }
2410 case ARM::tTBB_JT:
2411 case ARM::tTBH_JT: {
2412
2413 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
2414 Register Base = MI->getOperand(i: 0).getReg();
2415 Register Idx = MI->getOperand(i: 1).getReg();
2416 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
2417
2418 // Multiply up idx if necessary.
2419 if (!Is8Bit)
2420 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
2421 .addReg(Reg: Idx)
2422 .addReg(Reg: ARM::CPSR)
2423 .addReg(Reg: Idx)
2424 .addImm(Val: 1)
2425 // Add predicate operands.
2426 .addImm(Val: ARMCC::AL)
2427 .addReg(Reg: 0));
2428
2429 if (Base == ARM::PC) {
2430 // TBB [base, idx] =
2431 // ADDS idx, idx, base
2432 // LDRB idx, [idx, #4] ; or LDRH if TBH
2433 // LSLS idx, #1
2434 // ADDS pc, pc, idx
2435
2436 // When using PC as the base, it's important that there is no padding
2437 // between the last ADDS and the start of the jump table. The jump table
2438 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
2439 //
2440 // FIXME: Ideally we could vary the LDRB index based on the padding
2441 // between the sequence and jump table, however that relies on MCExprs
2442 // for load indexes which are currently not supported.
2443 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: getSubtargetInfo());
2444 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2445 .addReg(Reg: Idx)
2446 .addReg(Reg: Idx)
2447 .addReg(Reg: Base)
2448 // Add predicate operands.
2449 .addImm(Val: ARMCC::AL)
2450 .addReg(Reg: 0));
2451
2452 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
2453 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2454 .addReg(Reg: Idx)
2455 .addReg(Reg: Idx)
2456 .addImm(Val: Is8Bit ? 4 : 2)
2457 // Add predicate operands.
2458 .addImm(Val: ARMCC::AL)
2459 .addReg(Reg: 0));
2460 } else {
2461 // TBB [base, idx] =
2462 // LDRB idx, [base, idx] ; or LDRH if TBH
2463 // LSLS idx, #1
2464 // ADDS pc, pc, idx
2465
2466 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
2467 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Opc)
2468 .addReg(Reg: Idx)
2469 .addReg(Reg: Base)
2470 .addReg(Reg: Idx)
2471 // Add predicate operands.
2472 .addImm(Val: ARMCC::AL)
2473 .addReg(Reg: 0));
2474 }
2475
2476 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLSLri)
2477 .addReg(Reg: Idx)
2478 .addReg(Reg: ARM::CPSR)
2479 .addReg(Reg: Idx)
2480 .addImm(Val: 1)
2481 // Add predicate operands.
2482 .addImm(Val: ARMCC::AL)
2483 .addReg(Reg: 0));
2484
2485 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: MI->getOperand(i: 3).getImm()));
2486 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDhirr)
2487 .addReg(Reg: ARM::PC)
2488 .addReg(Reg: ARM::PC)
2489 .addReg(Reg: Idx)
2490 // Add predicate operands.
2491 .addImm(Val: ARMCC::AL)
2492 .addReg(Reg: 0));
2493 return;
2494 }
2495 case ARM::tBR_JTr:
2496 case ARM::BR_JTr: {
2497 // mov pc, target
2498 MCInst TmpInst;
2499 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
2500 ARM::MOVr : ARM::tMOVr;
2501 TmpInst.setOpcode(Opc);
2502 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2503 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2504 // Add predicate operands.
2505 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2506 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2507 // Add 's' bit operand (always reg0 for this)
2508 if (Opc == ARM::MOVr)
2509 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2510 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2511 return;
2512 }
2513 case ARM::BR_JTm_i12: {
2514 // ldr pc, target
2515 MCInst TmpInst;
2516 TmpInst.setOpcode(ARM::LDRi12);
2517 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2518 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2519 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI->getOperand(i: 2).getImm()));
2520 // Add predicate operands.
2521 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2522 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2523 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2524 return;
2525 }
2526 case ARM::BR_JTm_rs: {
2527 // ldr pc, target
2528 MCInst TmpInst;
2529 TmpInst.setOpcode(ARM::LDRrs);
2530 TmpInst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
2531 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 0).getReg()));
2532 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI->getOperand(i: 1).getReg()));
2533 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI->getOperand(i: 2).getImm()));
2534 // Add predicate operands.
2535 TmpInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2536 TmpInst.addOperand(Op: MCOperand::createReg(Reg: 0));
2537 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2538 return;
2539 }
2540 case ARM::BR_JTadd: {
2541 // add pc, target, idx
2542 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDrr)
2543 .addReg(Reg: ARM::PC)
2544 .addReg(Reg: MI->getOperand(i: 0).getReg())
2545 .addReg(Reg: MI->getOperand(i: 1).getReg())
2546 // Add predicate operands.
2547 .addImm(Val: ARMCC::AL)
2548 .addReg(Reg: 0)
2549 // Add 's' bit operand (always reg0 for this)
2550 .addReg(Reg: 0));
2551 return;
2552 }
2553 case ARM::SPACE:
2554 OutStreamer->emitZeros(NumBytes: MI->getOperand(i: 1).getImm());
2555 return;
2556 case ARM::TRAP: {
2557 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2558 // FIXME: Remove this special case when they do.
2559 if (!TM.getTargetTriple().isOSBinFormatMachO()) {
2560 uint32_t Val = 0xe7ffdefeUL;
2561 OutStreamer->AddComment(T: "trap");
2562 ATS.emitInst(Inst: Val);
2563 return;
2564 }
2565 break;
2566 }
2567 case ARM::tTRAP: {
2568 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2569 // FIXME: Remove this special case when they do.
2570 if (!TM.getTargetTriple().isOSBinFormatMachO()) {
2571 uint16_t Val = 0xdefe;
2572 OutStreamer->AddComment(T: "trap");
2573 ATS.emitInst(Inst: Val, Suffix: 'n');
2574 return;
2575 }
2576 break;
2577 }
2578 case ARM::t2Int_eh_sjlj_setjmp:
2579 case ARM::t2Int_eh_sjlj_setjmp_nofp:
2580 case ARM::tInt_eh_sjlj_setjmp: {
2581 // Two incoming args: GPR:$src, GPR:$val
2582 // mov $val, pc
2583 // adds $val, #7
2584 // str $val, [$src, #4]
2585 // movs r0, #0
2586 // b LSJLJEH
2587 // movs r0, #1
2588 // LSJLJEH:
2589 Register SrcReg = MI->getOperand(i: 0).getReg();
2590 Register ValReg = MI->getOperand(i: 1).getReg();
2591 MCSymbol *Label = OutContext.createTempSymbol(Name: "SJLJEH");
2592 OutStreamer->AddComment(T: "eh_setjmp begin");
2593 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2594 .addReg(Reg: ValReg)
2595 .addReg(Reg: ARM::PC)
2596 // Predicate.
2597 .addImm(Val: ARMCC::AL)
2598 .addReg(Reg: 0));
2599
2600 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tADDi3)
2601 .addReg(Reg: ValReg)
2602 // 's' bit operand
2603 .addReg(Reg: ARM::CPSR)
2604 .addReg(Reg: ValReg)
2605 .addImm(Val: 7)
2606 // Predicate.
2607 .addImm(Val: ARMCC::AL)
2608 .addReg(Reg: 0));
2609
2610 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tSTRi)
2611 .addReg(Reg: ValReg)
2612 .addReg(Reg: SrcReg)
2613 // The offset immediate is #4. The operand value is scaled by 4 for the
2614 // tSTR instruction.
2615 .addImm(Val: 1)
2616 // Predicate.
2617 .addImm(Val: ARMCC::AL)
2618 .addReg(Reg: 0));
2619
2620 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
2621 .addReg(Reg: ARM::R0)
2622 .addReg(Reg: ARM::CPSR)
2623 .addImm(Val: 0)
2624 // Predicate.
2625 .addImm(Val: ARMCC::AL)
2626 .addReg(Reg: 0));
2627
2628 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Symbol: Label, Ctx&: OutContext);
2629 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tB)
2630 .addExpr(Val: SymbolExpr)
2631 .addImm(Val: ARMCC::AL)
2632 .addReg(Reg: 0));
2633
2634 OutStreamer->AddComment(T: "eh_setjmp end");
2635 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVi8)
2636 .addReg(Reg: ARM::R0)
2637 .addReg(Reg: ARM::CPSR)
2638 .addImm(Val: 1)
2639 // Predicate.
2640 .addImm(Val: ARMCC::AL)
2641 .addReg(Reg: 0));
2642
2643 OutStreamer->emitLabel(Symbol: Label);
2644 return;
2645 }
2646
2647 case ARM::Int_eh_sjlj_setjmp_nofp:
2648 case ARM::Int_eh_sjlj_setjmp: {
2649 // Two incoming args: GPR:$src, GPR:$val
2650 // add $val, pc, #8
2651 // str $val, [$src, #+4]
2652 // mov r0, #0
2653 // add pc, pc, #0
2654 // mov r0, #1
2655 Register SrcReg = MI->getOperand(i: 0).getReg();
2656 Register ValReg = MI->getOperand(i: 1).getReg();
2657
2658 OutStreamer->AddComment(T: "eh_setjmp begin");
2659 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDri)
2660 .addReg(Reg: ValReg)
2661 .addReg(Reg: ARM::PC)
2662 .addImm(Val: 8)
2663 // Predicate.
2664 .addImm(Val: ARMCC::AL)
2665 .addReg(Reg: 0)
2666 // 's' bit operand (always reg0 for this).
2667 .addReg(Reg: 0));
2668
2669 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::STRi12)
2670 .addReg(Reg: ValReg)
2671 .addReg(Reg: SrcReg)
2672 .addImm(Val: 4)
2673 // Predicate.
2674 .addImm(Val: ARMCC::AL)
2675 .addReg(Reg: 0));
2676
2677 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVi)
2678 .addReg(Reg: ARM::R0)
2679 .addImm(Val: 0)
2680 // Predicate.
2681 .addImm(Val: ARMCC::AL)
2682 .addReg(Reg: 0)
2683 // 's' bit operand (always reg0 for this).
2684 .addReg(Reg: 0));
2685
2686 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::ADDri)
2687 .addReg(Reg: ARM::PC)
2688 .addReg(Reg: ARM::PC)
2689 .addImm(Val: 0)
2690 // Predicate.
2691 .addImm(Val: ARMCC::AL)
2692 .addReg(Reg: 0)
2693 // 's' bit operand (always reg0 for this).
2694 .addReg(Reg: 0));
2695
2696 OutStreamer->AddComment(T: "eh_setjmp end");
2697 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::MOVi)
2698 .addReg(Reg: ARM::R0)
2699 .addImm(Val: 1)
2700 // Predicate.
2701 .addImm(Val: ARMCC::AL)
2702 .addReg(Reg: 0)
2703 // 's' bit operand (always reg0 for this).
2704 .addReg(Reg: 0));
2705 return;
2706 }
2707 case ARM::Int_eh_sjlj_longjmp: {
2708 // ldr sp, [$src, #8]
2709 // ldr $scratch, [$src, #4]
2710 // ldr r7, [$src]
2711 // bx $scratch
2712 Register SrcReg = MI->getOperand(i: 0).getReg();
2713 Register ScratchReg = MI->getOperand(i: 1).getReg();
2714 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2715 .addReg(Reg: ARM::SP)
2716 .addReg(Reg: SrcReg)
2717 .addImm(Val: 8)
2718 // Predicate.
2719 .addImm(Val: ARMCC::AL)
2720 .addReg(Reg: 0));
2721
2722 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2723 .addReg(Reg: ScratchReg)
2724 .addReg(Reg: SrcReg)
2725 .addImm(Val: 4)
2726 // Predicate.
2727 .addImm(Val: ARMCC::AL)
2728 .addReg(Reg: 0));
2729
2730 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2731 // These platforms always use the same frame register
2732 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2733 .addReg(Reg: STI.getFramePointerReg())
2734 .addReg(Reg: SrcReg)
2735 .addImm(Val: 0)
2736 // Predicate.
2737 .addImm(Val: ARMCC::AL)
2738 .addReg(Reg: 0));
2739 } else {
2740 // If the calling code might use either R7 or R11 as
2741 // frame pointer register, restore it into both.
2742 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2743 .addReg(Reg: ARM::R7)
2744 .addReg(Reg: SrcReg)
2745 .addImm(Val: 0)
2746 // Predicate.
2747 .addImm(Val: ARMCC::AL)
2748 .addReg(Reg: 0));
2749 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::LDRi12)
2750 .addReg(Reg: ARM::R11)
2751 .addReg(Reg: SrcReg)
2752 .addImm(Val: 0)
2753 // Predicate.
2754 .addImm(Val: ARMCC::AL)
2755 .addReg(Reg: 0));
2756 }
2757
2758 assert(STI.hasV4TOps());
2759 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::BX)
2760 .addReg(Reg: ScratchReg)
2761 // Predicate.
2762 .addImm(Val: ARMCC::AL)
2763 .addReg(Reg: 0));
2764 return;
2765 }
2766 case ARM::tInt_eh_sjlj_longjmp: {
2767 // ldr $scratch, [$src, #8]
2768 // mov sp, $scratch
2769 // ldr $scratch, [$src, #4]
2770 // ldr r7, [$src]
2771 // bx $scratch
2772 Register SrcReg = MI->getOperand(i: 0).getReg();
2773 Register ScratchReg = MI->getOperand(i: 1).getReg();
2774
2775 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2776 .addReg(Reg: ScratchReg)
2777 .addReg(Reg: SrcReg)
2778 // The offset immediate is #8. The operand value is scaled by 4 for the
2779 // tLDR instruction.
2780 .addImm(Val: 2)
2781 // Predicate.
2782 .addImm(Val: ARMCC::AL)
2783 .addReg(Reg: 0));
2784
2785 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tMOVr)
2786 .addReg(Reg: ARM::SP)
2787 .addReg(Reg: ScratchReg)
2788 // Predicate.
2789 .addImm(Val: ARMCC::AL)
2790 .addReg(Reg: 0));
2791
2792 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2793 .addReg(Reg: ScratchReg)
2794 .addReg(Reg: SrcReg)
2795 .addImm(Val: 1)
2796 // Predicate.
2797 .addImm(Val: ARMCC::AL)
2798 .addReg(Reg: 0));
2799
2800 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2801 // These platforms always use the same frame register
2802 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2803 .addReg(Reg: STI.getFramePointerReg())
2804 .addReg(Reg: SrcReg)
2805 .addImm(Val: 0)
2806 // Predicate.
2807 .addImm(Val: ARMCC::AL)
2808 .addReg(Reg: 0));
2809 } else {
2810 // If the calling code might use either R7 or R11 as
2811 // frame pointer register, restore it into both.
2812 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2813 .addReg(Reg: ARM::R7)
2814 .addReg(Reg: SrcReg)
2815 .addImm(Val: 0)
2816 // Predicate.
2817 .addImm(Val: ARMCC::AL)
2818 .addReg(Reg: 0));
2819 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tLDRi)
2820 .addReg(Reg: ARM::R11)
2821 .addReg(Reg: SrcReg)
2822 .addImm(Val: 0)
2823 // Predicate.
2824 .addImm(Val: ARMCC::AL)
2825 .addReg(Reg: 0));
2826 }
2827
2828 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::tBX)
2829 .addReg(Reg: ScratchReg)
2830 // Predicate.
2831 .addImm(Val: ARMCC::AL)
2832 .addReg(Reg: 0));
2833 return;
2834 }
2835 case ARM::tInt_WIN_eh_sjlj_longjmp: {
2836 // ldr.w r11, [$src, #0]
2837 // ldr.w sp, [$src, #8]
2838 // ldr.w pc, [$src, #4]
2839
2840 Register SrcReg = MI->getOperand(i: 0).getReg();
2841
2842 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2843 .addReg(Reg: ARM::R11)
2844 .addReg(Reg: SrcReg)
2845 .addImm(Val: 0)
2846 // Predicate
2847 .addImm(Val: ARMCC::AL)
2848 .addReg(Reg: 0));
2849 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2850 .addReg(Reg: ARM::SP)
2851 .addReg(Reg: SrcReg)
2852 .addImm(Val: 8)
2853 // Predicate
2854 .addImm(Val: ARMCC::AL)
2855 .addReg(Reg: 0));
2856 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(ARM::t2LDRi12)
2857 .addReg(Reg: ARM::PC)
2858 .addReg(Reg: SrcReg)
2859 .addImm(Val: 4)
2860 // Predicate
2861 .addImm(Val: ARMCC::AL)
2862 .addReg(Reg: 0));
2863 return;
2864 }
2865 case ARM::PATCHABLE_FUNCTION_ENTER:
2866 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI);
2867 return;
2868 case ARM::PATCHABLE_FUNCTION_EXIT:
2869 LowerPATCHABLE_FUNCTION_EXIT(MI: *MI);
2870 return;
2871 case ARM::PATCHABLE_TAIL_CALL:
2872 LowerPATCHABLE_TAIL_CALL(MI: *MI);
2873 return;
2874 case ARM::SpeculationBarrierISBDSBEndBB: {
2875 // Print DSB SYS + ISB
2876 MCInst TmpInstDSB;
2877 TmpInstDSB.setOpcode(ARM::DSB);
2878 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2879 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstDSB);
2880 MCInst TmpInstISB;
2881 TmpInstISB.setOpcode(ARM::ISB);
2882 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2883 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstISB);
2884 return;
2885 }
2886 case ARM::t2SpeculationBarrierISBDSBEndBB: {
2887 // Print DSB SYS + ISB
2888 MCInst TmpInstDSB;
2889 TmpInstDSB.setOpcode(ARM::t2DSB);
2890 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2891 TmpInstDSB.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2892 TmpInstDSB.addOperand(Op: MCOperand::createReg(Reg: 0));
2893 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstDSB);
2894 MCInst TmpInstISB;
2895 TmpInstISB.setOpcode(ARM::t2ISB);
2896 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: 0xf));
2897 TmpInstISB.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
2898 TmpInstISB.addOperand(Op: MCOperand::createReg(Reg: 0));
2899 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstISB);
2900 return;
2901 }
2902 case ARM::SpeculationBarrierSBEndBB: {
2903 // Print SB
2904 MCInst TmpInstSB;
2905 TmpInstSB.setOpcode(ARM::SB);
2906 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstSB);
2907 return;
2908 }
2909 case ARM::t2SpeculationBarrierSBEndBB: {
2910 // Print SB
2911 MCInst TmpInstSB;
2912 TmpInstSB.setOpcode(ARM::t2SB);
2913 EmitToStreamer(S&: *OutStreamer, Inst: TmpInstSB);
2914 return;
2915 }
2916
2917 case ARM::SEH_StackAlloc:
2918 ATS.emitARMWinCFIAllocStack(Size: MI->getOperand(i: 0).getImm(),
2919 Wide: MI->getOperand(i: 1).getImm());
2920 return;
2921
2922 case ARM::SEH_SaveRegs:
2923 case ARM::SEH_SaveRegs_Ret:
2924 ATS.emitARMWinCFISaveRegMask(Mask: MI->getOperand(i: 0).getImm(),
2925 Wide: MI->getOperand(i: 1).getImm());
2926 return;
2927
2928 case ARM::SEH_SaveSP:
2929 ATS.emitARMWinCFISaveSP(Reg: MI->getOperand(i: 0).getImm());
2930 return;
2931
2932 case ARM::SEH_SaveFRegs:
2933 ATS.emitARMWinCFISaveFRegs(First: MI->getOperand(i: 0).getImm(),
2934 Last: MI->getOperand(i: 1).getImm());
2935 return;
2936
2937 case ARM::SEH_SaveLR:
2938 ATS.emitARMWinCFISaveLR(Offset: MI->getOperand(i: 0).getImm());
2939 return;
2940
2941 case ARM::SEH_Nop:
2942 case ARM::SEH_Nop_Ret:
2943 ATS.emitARMWinCFINop(Wide: MI->getOperand(i: 0).getImm());
2944 return;
2945
2946 case ARM::SEH_PrologEnd:
2947 ATS.emitARMWinCFIPrologEnd(/*Fragment=*/false);
2948 return;
2949
2950 case ARM::SEH_EpilogStart:
2951 ATS.emitARMWinCFIEpilogStart(Condition: ARMCC::AL);
2952 return;
2953
2954 case ARM::SEH_EpilogEnd:
2955 ATS.emitARMWinCFIEpilogEnd();
2956 return;
2957 }
2958
2959 MCInst TmpInst;
2960 LowerARMMachineInstrToMCInst(MI, OutMI&: TmpInst, AP&: *this);
2961
2962 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
2963}
2964
2965char ARMAsmPrinter::ID = 0;
2966
2967INITIALIZE_PASS(ARMAsmPrinter, "arm-asm-printer", "ARM Assembly Printer", false,
2968 false)
2969
2970//===----------------------------------------------------------------------===//
2971// Target Registry Stuff
2972//===----------------------------------------------------------------------===//
2973
2974// Force static initialization.
2975extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
2976LLVMInitializeARMAsmPrinter() {
2977 RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
2978 RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
2979 RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
2980 RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
2981}
2982