1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::AVR {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 ADCWRdRr = 334, // AVRInstrInfo.td:397
350 ADDWRdRr = 335, // AVRInstrInfo.td:378
351 ADIWRdKP = 336, // AVRInstrInfo.td:413
352 ADJCALLSTACKDOWN = 337, // AVRInstrInfo.td:346
353 ADJCALLSTACKUP = 338, // AVRInstrInfo.td:356
354 ANDIWRdK = 339, // AVRInstrInfo.td:593
355 ANDWRdRr = 340, // AVRInstrInfo.td:553
356 ASRBNRd = 341, // AVRInstrInfo.td:1367
357 ASRWLoRd = 342, // AVRInstrInfo.td:1374
358 ASRWNRd = 343, // AVRInstrInfo.td:1363
359 ASRWRd = 344, // AVRInstrInfo.td:1371
360 Asr16 = 345, // AVRInstrInfo.td:1641
361 Asr32 = 346, // AVRInstrInfo.td:1645
362 Asr8 = 347, // AVRInstrInfo.td:1637
363 AtomicFence = 348, // AVRInstrInfo.td:1054
364 AtomicLoad16 = 349, // AVRInstrInfo.td:1032
365 AtomicLoad8 = 350, // AVRInstrInfo.td:1031
366 AtomicLoadAdd16 = 351, // AVRInstrInfo.td:1042
367 AtomicLoadAdd8 = 352, // AVRInstrInfo.td:1041
368 AtomicLoadAnd16 = 353, // AVRInstrInfo.td:1046
369 AtomicLoadAnd8 = 354, // AVRInstrInfo.td:1045
370 AtomicLoadOr16 = 355, // AVRInstrInfo.td:1048
371 AtomicLoadOr8 = 356, // AVRInstrInfo.td:1047
372 AtomicLoadSub16 = 357, // AVRInstrInfo.td:1044
373 AtomicLoadSub8 = 358, // AVRInstrInfo.td:1043
374 AtomicLoadXor16 = 359, // AVRInstrInfo.td:1050
375 AtomicLoadXor8 = 360, // AVRInstrInfo.td:1049
376 AtomicStore16 = 361, // AVRInstrInfo.td:1035
377 AtomicStore8 = 362, // AVRInstrInfo.td:1034
378 COMWRd = 363, // AVRInstrInfo.td:623
379 CPCWRdRr = 364, // AVRInstrInfo.td:746
380 CPWRdRr = 365, // AVRInstrInfo.td:731
381 CopyZero = 366, // AVRInstrInfo.td:1653
382 ELPMBRdZ = 367, // AVRInstrInfo.td:1231
383 ELPMBRdZPi = 368, // AVRInstrInfo.td:1243
384 ELPMWRdZ = 369, // AVRInstrInfo.td:1236
385 ELPMWRdZPi = 370, // AVRInstrInfo.td:1247
386 EORWRdRr = 371, // AVRInstrInfo.td:579
387 FRMIDX = 372, // AVRInstrInfo.td:1545
388 FRMSP = 373, // AVRInstrInfo.td:1539
389 INWRdA = 374, // AVRInstrInfo.td:1271
390 LDDWRdPtrQ = 375, // AVRInstrInfo.td:980
391 LDDWRdYQ = 376, // AVRInstrInfo.td:1001
392 LDIWRdK = 377, // AVRInstrInfo.td:884
393 LDSWRdK = 378, // AVRInstrInfo.td:904
394 LDWRdPtr = 379, // AVRInstrInfo.td:927
395 LDWRdPtrPd = 380, // AVRInstrInfo.td:957
396 LDWRdPtrPi = 381, // AVRInstrInfo.td:944
397 LPMBRdZ = 382, // AVRInstrInfo.td:1189
398 LPMWRdZ = 383, // AVRInstrInfo.td:1193
399 LPMWRdZPi = 384, // AVRInstrInfo.td:1208
400 LSLBNRd = 385, // AVRInstrInfo.td:1339
401 LSLWHiRd = 386, // AVRInstrInfo.td:1332
402 LSLWNRd = 387, // AVRInstrInfo.td:1335
403 LSLWRd = 388, // AVRInstrInfo.td:1329
404 LSRBNRd = 389, // AVRInstrInfo.td:1356
405 LSRWLoRd = 390, // AVRInstrInfo.td:1349
406 LSRWNRd = 391, // AVRInstrInfo.td:1352
407 LSRWRd = 392, // AVRInstrInfo.td:1346
408 Lsl16 = 393, // AVRInstrInfo.td:1597
409 Lsl32 = 394, // AVRInstrInfo.td:1601
410 Lsl8 = 395, // AVRInstrInfo.td:1593
411 Lsr16 = 396, // AVRInstrInfo.td:1611
412 Lsr32 = 397, // AVRInstrInfo.td:1615
413 Lsr8 = 398, // AVRInstrInfo.td:1607
414 NEGWRd = 399, // AVRInstrInfo.td:635
415 ORIWRdK = 400, // AVRInstrInfo.td:606
416 ORWRdRr = 401, // AVRInstrInfo.td:566
417 OUTWARr = 402, // AVRInstrInfo.td:1280
418 POPWRd = 403, // AVRInstrInfo.td:1301
419 PUSHWRr = 404, // AVRInstrInfo.td:1292
420 ROLBRdR1 = 405, // AVRInstrInfo.td:1378
421 ROLBRdR17 = 406, // AVRInstrInfo.td:1383
422 ROLWRd = 407, // AVRInstrInfo.td:1392
423 RORBRd = 408, // AVRInstrInfo.td:1387
424 RORWRd = 409, // AVRInstrInfo.td:1398
425 Rol16 = 410, // AVRInstrInfo.td:1625
426 Rol8 = 411, // AVRInstrInfo.td:1621
427 Ror16 = 412, // AVRInstrInfo.td:1633
428 Ror8 = 413, // AVRInstrInfo.td:1629
429 SBCIWRdK = 414, // AVRInstrInfo.td:479
430 SBCWRdRr = 415, // AVRInstrInfo.td:468
431 SEXT = 416, // AVRInstrInfo.td:1532
432 SPREAD = 417, // AVRInstrInfo.td:1574
433 SPWRITE = 418, // AVRInstrInfo.td:1577
434 STDSPQRr = 419, // AVRInstrInfo.td:1561
435 STDWPtrQRr = 420, // AVRInstrInfo.td:1177
436 STDWSPQRr = 421, // AVRInstrInfo.td:1568
437 STSWKRr = 422, // AVRInstrInfo.td:1075
438 STWPtrPdRr = 423, // AVRInstrInfo.td:1147
439 STWPtrPiRr = 424, // AVRInstrInfo.td:1122
440 STWPtrRr = 425, // AVRInstrInfo.td:1098
441 SUBIWRdK = 426, // AVRInstrInfo.td:448
442 SUBWRdRr = 427, // AVRInstrInfo.td:435
443 Select16 = 428, // AVRInstrInfo.td:1587
444 Select8 = 429, // AVRInstrInfo.td:1581
445 ZEXT = 430, // AVRInstrInfo.td:1535
446 ADCRdRr = 431, // AVRInstrInfo.td:385
447 ADDRdRr = 432, // AVRInstrInfo.td:368
448 ADIWRdK = 433, // AVRInstrInfo.td:403
449 ANDIRdK = 434, // AVRInstrInfo.td:584
450 ANDRdRr = 435, // AVRInstrInfo.td:544
451 ASRRd = 436, // AVRInstrInfo.td:1360
452 BCLRs = 437, // AVRInstrInfo.td:1456
453 BLD = 438, // AVRInstrInfo.td:1429
454 BRBCsk = 439, // AVRInstrInfo.td:785
455 BRBSsk = 440, // AVRInstrInfo.td:780
456 BREAK = 441, // AVRInstrInfo.td:1500
457 BREQk = 442, // AVRInstrInfo.td:836
458 BRGEk = 443, // AVRInstrInfo.td:854
459 BRLOk = 444, // AVRInstrInfo.td:845
460 BRLTk = 445, // AVRInstrInfo.td:857
461 BRMIk = 446, // AVRInstrInfo.td:848
462 BRNEk = 447, // AVRInstrInfo.td:839
463 BRPLk = 448, // AVRInstrInfo.td:851
464 BRSHk = 449, // AVRInstrInfo.td:842
465 BSETs = 450, // AVRInstrInfo.td:1455
466 BST = 451, // AVRInstrInfo.td:1426
467 CALLk = 452, // AVRInstrInfo.td:698
468 CBIAb = 453, // AVRInstrInfo.td:1418
469 COMRd = 454, // AVRInstrInfo.td:615
470 CPCRdRr = 455, // AVRInstrInfo.td:736
471 CPIRdK = 456, // AVRInstrInfo.td:752
472 CPRdRr = 457, // AVRInstrInfo.td:722
473 CPSE = 458, // AVRInstrInfo.td:719
474 DECRd = 459, // AVRInstrInfo.td:493
475 DESK = 460, // AVRInstrInfo.td:535
476 EICALL = 461, // AVRInstrInfo.td:688
477 EIJMP = 462, // AVRInstrInfo.td:662
478 ELPM = 463, // AVRInstrInfo.td:1217
479 ELPMRdZ = 464, // AVRInstrInfo.td:1220
480 ELPMRdZPi = 465, // AVRInstrInfo.td:1225
481 EORRdRr = 466, // AVRInstrInfo.td:570
482 FMUL = 467, // AVRInstrInfo.td:519
483 FMULS = 468, // AVRInstrInfo.td:523
484 FMULSU = 469, // AVRInstrInfo.td:527
485 ICALL = 470, // AVRInstrInfo.td:682
486 IJMP = 471, // AVRInstrInfo.td:658
487 INCRd = 472, // AVRInstrInfo.td:489
488 INRdA = 473, // AVRInstrInfo.td:1268
489 JMPk = 474, // AVRInstrInfo.td:665
490 LACZRd = 475, // AVRInstrInfo.td:1314
491 LASZRd = 476, // AVRInstrInfo.td:1311
492 LATZRd = 477, // AVRInstrInfo.td:1317
493 LDDRdPtrQ = 478, // AVRInstrInfo.td:964
494 LDIRdK = 479, // AVRInstrInfo.td:876
495 LDRdPtr = 480, // AVRInstrInfo.td:912
496 LDRdPtrPd = 481, // AVRInstrInfo.td:948
497 LDRdPtrPi = 482, // AVRInstrInfo.td:936
498 LDSRdK = 483, // AVRInstrInfo.td:890
499 LDSRdKTiny = 484, // AVRInstrInfo.td:895
500 LPM = 485, // AVRInstrInfo.td:1184
501 LPMRdZ = 486, // AVRInstrInfo.td:1197
502 LPMRdZPi = 487, // AVRInstrInfo.td:1204
503 LSRRd = 488, // AVRInstrInfo.td:1343
504 MOVRdRr = 489, // AVRInstrInfo.td:866
505 MOVWRdRr = 490, // AVRInstrInfo.td:869
506 MULRdRr = 491, // AVRInstrInfo.td:506
507 MULSRdRr = 492, // AVRInstrInfo.td:510
508 MULSURdRr = 493, // AVRInstrInfo.td:515
509 NEGRd = 494, // AVRInstrInfo.td:626
510 NOP = 495, // AVRInstrInfo.td:1509
511 ORIRdK = 496, // AVRInstrInfo.td:597
512 ORRdRr = 497, // AVRInstrInfo.td:557
513 OUTARr = 498, // AVRInstrInfo.td:1277
514 POPRd = 499, // AVRInstrInfo.td:1298
515 PUSHRr = 500, // AVRInstrInfo.td:1288
516 RCALLk = 501, // AVRInstrInfo.td:676
517 RET = 502, // AVRInstrInfo.td:707
518 RETI = 503, // AVRInstrInfo.td:709
519 RJMPk = 504, // AVRInstrInfo.td:655
520 RORRd = 505, // AVRInstrInfo.td:1395
521 SBCIRdK = 506, // AVRInstrInfo.td:472
522 SBCRdRr = 507, // AVRInstrInfo.td:459
523 SBIAb = 508, // AVRInstrInfo.td:1413
524 SBICAb = 509, // AVRInstrInfo.td:769
525 SBISAb = 510, // AVRInstrInfo.td:772
526 SBIWRdK = 511, // AVRInstrInfo.td:452
527 SBRCRrB = 512, // AVRInstrInfo.td:763
528 SBRSRrB = 513, // AVRInstrInfo.td:766
529 SLEEP = 514, // AVRInstrInfo.td:1516
530 SPM = 515, // AVRInstrInfo.td:1256
531 SPMZPi = 516, // AVRInstrInfo.td:1260
532 STDPtrQRr = 517, // AVRInstrInfo.td:1160
533 STPtrPdRr = 518, // AVRInstrInfo.td:1133
534 STPtrPiRr = 519, // AVRInstrInfo.td:1108
535 STPtrRr = 520, // AVRInstrInfo.td:1083
536 STSKRr = 521, // AVRInstrInfo.td:1059
537 STSKRrTiny = 522, // AVRInstrInfo.td:1064
538 SUBIRdK = 523, // AVRInstrInfo.td:439
539 SUBRdRr = 524, // AVRInstrInfo.td:425
540 SWAPRd = 525, // AVRInstrInfo.td:1406
541 WDR = 526, // AVRInstrInfo.td:1523
542 XCHZRd = 527, // AVRInstrInfo.td:1308
543 INSTRUCTION_LIST_END = 528
544 };
545
546} // namespace llvm::AVR
547
548#endif // GET_INSTRINFO_ENUM
549
550#ifdef GET_INSTRINFO_SCHED_ENUM
551#undef GET_INSTRINFO_SCHED_ENUM
552
553namespace llvm::AVR::Sched {
554
555 enum {
556 NoInstrModel = 0,
557 SCHED_LIST_END = 1
558 };
559
560} // namespace llvm::AVR::Sched
561
562#endif // GET_INSTRINFO_SCHED_ENUM
563
564#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
565
566namespace llvm {
567
568struct AVRInstrTable {
569 MCInstrDesc Insts[528];
570 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
571 MCPhysReg ImplicitOps[41];
572 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
573 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
574 MCOperandInfo OperandInfo[313];
575};
576} // namespace llvm
577
578#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
579
580#ifdef GET_INSTRINFO_MC_DESC
581#undef GET_INSTRINFO_MC_DESC
582
583namespace llvm {
584
585static_assert((sizeof AVRInstrTable::ImplicitOps + sizeof AVRInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
586static constexpr unsigned AVROpInfoBase = (sizeof AVRInstrTable::ImplicitOps + sizeof AVRInstrTable::Padding) / sizeof(MCOperandInfo);
587
588extern const AVRInstrTable AVRDescs = {
589 {
590 { 527, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHZRd
591 { 526, 0, 0, 2, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // WDR
592 { 525, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 238, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWAPRd
593 { 524, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 269, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBRdRr
594 { 523, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 275, 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBIRdK
595 { 522, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 311, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSKRrTiny
596 { 521, 2, 0, 4, 0, 0, 0, AVROpInfoBase + 301, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSKRr
597 { 520, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 188, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STPtrRr
598 { 519, 4, 1, 2, 0, 0, 0, AVROpInfoBase + 307, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STPtrPiRr
599 { 518, 4, 1, 2, 0, 0, 0, AVROpInfoBase + 307, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STPtrPdRr
600 { 517, 3, 0, 2, 0, 0, 0, AVROpInfoBase + 304, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDPtrQRr
601 { 516, 1, 0, 2, 0, 2, 1, AVROpInfoBase + 303, 38, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPMZPi
602 { 515, 0, 0, 2, 0, 1, 0, AVROpInfoBase + 1, 9, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPM
603 { 514, 0, 0, 2, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLEEP
604 { 513, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 283, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBRSRrB
605 { 512, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 283, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBRCRrB
606 { 511, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 272, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBIWRdK
607 { 510, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 32, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBISAb
608 { 509, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 32, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBICAb
609 { 508, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBIAb
610 { 507, 3, 1, 2, 0, 1, 1, AVROpInfoBase + 269, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBCRdRr
611 { 506, 3, 1, 2, 0, 1, 1, AVROpInfoBase + 275, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBCIRdK
612 { 505, 2, 1, 2, 0, 1, 1, AVROpInfoBase + 238, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RORRd
613 { 504, 1, 0, 2, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RJMPk
614 { 503, 0, 0, 2, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETI
615 { 502, 0, 0, 2, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
616 { 501, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 16, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RCALLk
617 { 500, 1, 0, 2, 0, 1, 1, AVROpInfoBase + 192, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSHRr
618 { 499, 1, 1, 2, 0, 1, 1, AVROpInfoBase + 192, 10, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPRd
619 { 498, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 301, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTARr
620 { 497, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 269, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ORRdRr
621 { 496, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 275, 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ORIRdK
622 { 495, 0, 0, 2, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
623 { 494, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 238, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEGRd
624 { 493, 2, 0, 2, 0, 0, 3, AVROpInfoBase + 289, 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MULSURdRr
625 { 492, 2, 0, 2, 0, 0, 3, AVROpInfoBase + 299, 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MULSRdRr
626 { 491, 2, 0, 2, 0, 0, 3, AVROpInfoBase + 285, 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MULRdRr
627 { 490, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVWRdRr
628 { 489, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 285, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVRdRr
629 { 488, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 238, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSRRd
630 { 487, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 223, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LPMRdZPi
631 { 486, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LPMRdZ
632 { 485, 0, 0, 2, 0, 1, 1, AVROpInfoBase + 1, 33, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LPM
633 { 484, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 287, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSRdKTiny
634 { 483, 2, 1, 4, 0, 0, 0, AVROpInfoBase + 291, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSRdK
635 { 482, 3, 2, 2, 0, 0, 0, AVROpInfoBase + 296, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDRdPtrPi
636 { 481, 3, 2, 2, 0, 0, 0, AVROpInfoBase + 296, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDRdPtrPd
637 { 480, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 178, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDRdPtr
638 { 479, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 287, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIRdK
639 { 478, 3, 1, 2, 0, 0, 0, AVROpInfoBase + 293, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDRdPtrQ
640 { 477, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LATZRd
641 { 476, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LASZRd
642 { 475, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LACZRd
643 { 474, 1, 0, 4, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMPk
644 { 473, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 291, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INRdA
645 { 472, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 238, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INCRd
646 { 471, 0, 0, 2, 0, 1, 0, AVROpInfoBase + 1, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IJMP
647 { 470, 0, 0, 2, 0, 2, 0, AVROpInfoBase + 1, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL
648 { 469, 2, 0, 2, 0, 0, 3, AVROpInfoBase + 289, 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FMULSU
649 { 468, 2, 0, 2, 0, 0, 3, AVROpInfoBase + 289, 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FMULS
650 { 467, 2, 0, 2, 0, 0, 3, AVROpInfoBase + 289, 35, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FMUL
651 { 466, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 269, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EORRdRr
652 { 465, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 223, 9, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELPMRdZPi
653 { 464, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELPMRdZ
654 { 463, 0, 0, 2, 0, 1, 1, AVROpInfoBase + 1, 33, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELPM
655 { 462, 0, 0, 2, 0, 1, 0, AVROpInfoBase + 1, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EIJMP
656 { 461, 0, 0, 2, 0, 2, 0, AVROpInfoBase + 1, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EICALL
657 { 460, 1, 0, 2, 0, 0, 16, AVROpInfoBase + 1, 17, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DESK
658 { 459, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 238, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DECRd
659 { 458, 2, 0, 2, 0, 0, 1, AVROpInfoBase + 285, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CPSE
660 { 457, 2, 0, 2, 0, 0, 1, AVROpInfoBase + 285, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CPRdRr
661 { 456, 2, 0, 2, 0, 0, 1, AVROpInfoBase + 287, 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CPIRdK
662 { 455, 2, 0, 2, 0, 1, 1, AVROpInfoBase + 285, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CPCRdRr
663 { 454, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 238, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMRd
664 { 453, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 32, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CBIAb
665 { 452, 1, 0, 4, 0, 1, 0, AVROpInfoBase + 0, 16, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLk
666 { 451, 2, 0, 2, 0, 0, 1, AVROpInfoBase + 283, 2, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BST
667 { 450, 1, 0, 2, 0, 0, 1, AVROpInfoBase + 1, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSETs
668 { 449, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRSHk
669 { 448, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRPLk
670 { 447, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRNEk
671 { 446, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRMIk
672 { 445, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRLTk
673 { 444, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRLOk
674 { 443, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRGEk
675 { 442, 1, 0, 2, 0, 1, 0, AVROpInfoBase + 0, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BREQk
676 { 441, 0, 0, 2, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BREAK
677 { 440, 2, 0, 2, 0, 1, 0, AVROpInfoBase + 281, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBSsk
678 { 439, 2, 0, 2, 0, 1, 0, AVROpInfoBase + 281, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRBCsk
679 { 438, 3, 1, 2, 0, 1, 0, AVROpInfoBase + 278, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLD
680 { 437, 1, 0, 2, 0, 0, 1, AVROpInfoBase + 1, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BCLRs
681 { 436, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 238, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASRRd
682 { 435, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 269, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDRdRr
683 { 434, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 275, 2, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDIRdK
684 { 433, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 272, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADIWRdK
685 { 432, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 269, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDRdRr
686 { 431, 3, 1, 2, 0, 1, 1, AVROpInfoBase + 269, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADCRdRr
687 { 430, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 240, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT
688 { 429, 4, 1, 2, 0, 1, 0, AVROpInfoBase + 265, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select8
689 { 428, 4, 1, 2, 0, 1, 0, AVROpInfoBase + 261, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select16
690 { 427, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 151, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBWRdRr
691 { 426, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 154, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBIWRdK
692 { 425, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWPtrRr
693 { 424, 4, 1, 2, 0, 0, 0, AVROpInfoBase + 257, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWPtrPiRr
694 { 423, 4, 1, 2, 0, 0, 0, AVROpInfoBase + 257, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWPtrPdRr
695 { 422, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STSWKRr
696 { 421, 3, 0, 2, 0, 1, 1, AVROpInfoBase + 252, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDWSPQRr
697 { 420, 3, 0, 2, 0, 0, 0, AVROpInfoBase + 249, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDWPtrQRr
698 { 419, 3, 0, 2, 0, 1, 1, AVROpInfoBase + 246, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDSPQRr
699 { 418, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 244, 16, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPWRITE
700 { 417, 2, 1, 2, 0, 1, 0, AVROpInfoBase + 242, 16, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPREAD
701 { 416, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 240, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT
702 { 415, 3, 1, 2, 0, 1, 1, AVROpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBCWRdRr
703 { 414, 3, 1, 2, 0, 1, 1, AVROpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SBCIWRdK
704 { 413, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 173, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Ror8
705 { 412, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 165, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Ror16
706 { 411, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 173, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rol8
707 { 410, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 165, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rol16
708 { 409, 2, 1, 2, 0, 1, 1, AVROpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RORWRd
709 { 408, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 238, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RORBRd
710 { 407, 2, 1, 2, 0, 1, 1, AVROpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROLWRd
711 { 406, 2, 1, 2, 0, 1, 1, AVROpInfoBase + 238, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROLBRdR17
712 { 405, 2, 1, 2, 0, 1, 1, AVROpInfoBase + 238, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROLBRdR1
713 { 404, 1, 0, 2, 0, 1, 1, AVROpInfoBase + 237, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSHWRr
714 { 403, 1, 1, 2, 0, 1, 1, AVROpInfoBase + 237, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPWRd
715 { 402, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OUTWARr
716 { 401, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 151, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ORWRdRr
717 { 400, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 154, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ORIWRdK
718 { 399, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 232, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEGWRd
719 { 398, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 173, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Lsr8
720 { 397, 5, 2, 2, 0, 0, 1, AVROpInfoBase + 168, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Lsr32
721 { 396, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 165, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Lsr16
722 { 395, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 173, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Lsl8
723 { 394, 5, 2, 2, 0, 0, 1, AVROpInfoBase + 168, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Lsl32
724 { 393, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 165, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Lsl16
725 { 392, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 160, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSRWRd
726 { 391, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 229, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSRWNRd
727 { 390, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 160, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSRWLoRd
728 { 389, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 157, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSRBNRd
729 { 388, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 160, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSLWRd
730 { 387, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 229, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSLWNRd
731 { 386, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 160, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSLWHiRd
732 { 385, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 157, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LSLBNRd
733 { 384, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 227, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LPMWRdZPi
734 { 383, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 225, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LPMWRdZ
735 { 382, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 223, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LPMBRdZ
736 { 381, 3, 2, 2, 0, 0, 0, AVROpInfoBase + 220, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWRdPtrPi
737 { 380, 3, 2, 2, 0, 0, 0, AVROpInfoBase + 220, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWRdPtrPd
738 { 379, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 218, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWRdPtr
739 { 378, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 216, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDSWRdK
740 { 377, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 206, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIWRdK
741 { 376, 3, 1, 2, 0, 0, 0, AVROpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDWRdYQ
742 { 375, 3, 1, 2, 0, 0, 0, AVROpInfoBase + 210, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDWRdPtrQ
743 { 374, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 208, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INWRdA
744 { 373, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 206, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRMSP
745 { 372, 4, 1, 2, 0, 0, 1, AVROpInfoBase + 202, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FRMIDX
746 { 371, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 151, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EORWRdRr
747 { 370, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 199, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELPMWRdZPi
748 { 369, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 196, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELPMWRdZ
749 { 368, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 193, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELPMBRdZPi
750 { 367, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 193, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELPMBRdZ
751 { 366, 1, 1, 2, 0, 0, 0, AVROpInfoBase + 192, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CopyZero
752 { 365, 2, 0, 2, 0, 0, 1, AVROpInfoBase + 190, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CPWRdRr
753 { 364, 2, 0, 2, 0, 1, 1, AVROpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CPCWRdRr
754 { 363, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 160, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMWRd
755 { 362, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 188, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicStore8
756 { 361, 2, 0, 2, 0, 0, 0, AVROpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicStore16
757 { 360, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 183, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadXor8
758 { 359, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 180, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadXor16
759 { 358, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 183, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadSub8
760 { 357, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 180, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadSub16
761 { 356, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 183, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadOr8
762 { 355, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 180, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadOr16
763 { 354, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 183, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadAnd8
764 { 353, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 180, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadAnd16
765 { 352, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 183, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadAdd8
766 { 351, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 180, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoadAdd16
767 { 350, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 178, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoad8
768 { 349, 2, 1, 2, 0, 0, 0, AVROpInfoBase + 176, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicLoad16
769 { 348, 0, 0, 2, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AtomicFence
770 { 347, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 173, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Asr8
771 { 346, 5, 2, 2, 0, 0, 1, AVROpInfoBase + 168, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Asr32
772 { 345, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 165, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Asr16
773 { 344, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 160, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASRWRd
774 { 343, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 162, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASRWNRd
775 { 342, 2, 1, 2, 0, 0, 1, AVROpInfoBase + 160, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASRWLoRd
776 { 341, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 157, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASRBNRd
777 { 340, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 151, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDWRdRr
778 { 339, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 154, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDIWRdK
779 { 338, 2, 0, 2, 0, 1, 1, AVROpInfoBase + 20, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
780 { 337, 2, 0, 2, 0, 1, 2, AVROpInfoBase + 20, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
781 { 336, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 154, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADIWRdKP
782 { 335, 3, 1, 2, 0, 0, 1, AVROpInfoBase + 151, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDWRdRr
783 { 334, 3, 1, 2, 0, 1, 1, AVROpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADCWRdRr
784 { 333, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
785 { 332, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
786 { 331, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
787 { 330, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
788 { 329, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
789 { 328, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
790 { 327, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
791 { 326, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
792 { 325, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
793 { 324, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
794 { 323, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
795 { 322, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
796 { 321, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
797 { 320, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
798 { 319, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
799 { 318, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
800 { 317, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
801 { 316, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
802 { 315, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
803 { 314, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
804 { 313, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
805 { 312, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
806 { 311, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
807 { 310, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
808 { 309, 3, 0, 0, 0, 0, 0, AVROpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
809 { 308, 3, 0, 0, 0, 0, 0, AVROpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
810 { 307, 4, 0, 0, 0, 0, 0, AVROpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
811 { 306, 4, 0, 0, 0, 0, 0, AVROpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
812 { 305, 3, 0, 0, 0, 0, 0, AVROpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
813 { 304, 4, 0, 0, 0, 0, 0, AVROpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
814 { 303, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
815 { 302, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
816 { 301, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
817 { 300, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
818 { 299, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
819 { 298, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
820 { 297, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
821 { 296, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
822 { 295, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
823 { 294, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
824 { 293, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
825 { 292, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
826 { 291, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
827 { 290, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
828 { 289, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
829 { 288, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
830 { 287, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
831 { 286, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
832 { 285, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
833 { 284, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
834 { 283, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
835 { 282, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
836 { 281, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
837 { 280, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
838 { 279, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
839 { 278, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
840 { 277, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
841 { 276, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
842 { 275, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
843 { 274, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
844 { 273, 3, 2, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
845 { 272, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
846 { 271, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
847 { 270, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
848 { 269, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
849 { 268, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
850 { 267, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
851 { 266, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
852 { 265, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
853 { 264, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
854 { 263, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
855 { 262, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
856 { 261, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
857 { 260, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
858 { 259, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
859 { 258, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
860 { 257, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
861 { 256, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
862 { 255, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
863 { 254, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
864 { 253, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
865 { 252, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
866 { 251, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
867 { 250, 3, 0, 0, 0, 0, 0, AVROpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
868 { 249, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
869 { 248, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
870 { 247, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
871 { 246, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
872 { 245, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
873 { 244, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
874 { 243, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
875 { 242, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
876 { 241, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
877 { 240, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
878 { 239, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
879 { 238, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
880 { 237, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
881 { 236, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
882 { 235, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
883 { 234, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
884 { 233, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
885 { 232, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
886 { 231, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
887 { 230, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
888 { 229, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
889 { 228, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
890 { 227, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
891 { 226, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
892 { 225, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
893 { 224, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
894 { 223, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
895 { 222, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
896 { 221, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
897 { 220, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
898 { 219, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
899 { 218, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
900 { 217, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
901 { 216, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
902 { 215, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
903 { 214, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
904 { 213, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
905 { 212, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
906 { 211, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
907 { 210, 3, 2, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
908 { 209, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
909 { 208, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
910 { 207, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
911 { 206, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
912 { 205, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
913 { 204, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
914 { 203, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
915 { 202, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
916 { 201, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
917 { 200, 3, 2, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
918 { 199, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
919 { 198, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
920 { 197, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
921 { 196, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
922 { 195, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
923 { 194, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
924 { 193, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
925 { 192, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
926 { 191, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
927 { 190, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
928 { 189, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
929 { 188, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
930 { 187, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
931 { 186, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
932 { 185, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
933 { 184, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
934 { 183, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
935 { 182, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
936 { 181, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
937 { 180, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
938 { 179, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
939 { 178, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
940 { 177, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
941 { 176, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
942 { 175, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
943 { 174, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
944 { 173, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
945 { 172, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
946 { 171, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
947 { 170, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
948 { 169, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
949 { 168, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
950 { 167, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
951 { 166, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
952 { 165, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
953 { 164, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
954 { 163, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
955 { 162, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
956 { 161, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
957 { 160, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
958 { 159, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
959 { 158, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
960 { 157, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
961 { 156, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
962 { 155, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
963 { 154, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
964 { 153, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
965 { 152, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
966 { 151, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
967 { 150, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
968 { 149, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
969 { 148, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
970 { 147, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
971 { 146, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
972 { 145, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
973 { 144, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
974 { 143, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
975 { 142, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
976 { 141, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
977 { 140, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
978 { 139, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
979 { 138, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
980 { 137, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
981 { 136, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
982 { 135, 4, 0, 0, 0, 0, 0, AVROpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
983 { 134, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
984 { 133, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
985 { 132, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
986 { 131, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
987 { 130, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
988 { 129, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
989 { 128, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
990 { 127, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
991 { 126, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
992 { 125, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
993 { 124, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
994 { 123, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
995 { 122, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
996 { 121, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
997 { 120, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
998 { 119, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
999 { 118, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1000 { 117, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1001 { 116, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1002 { 115, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1003 { 114, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1004 { 113, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1005 { 112, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1006 { 111, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1007 { 110, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1008 { 109, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1009 { 108, 5, 1, 0, 0, 0, 0, AVROpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1010 { 107, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1011 { 106, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1012 { 105, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1013 { 104, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1014 { 103, 5, 2, 0, 0, 0, 0, AVROpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1015 { 102, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1016 { 101, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1017 { 100, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1018 { 99, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1019 { 98, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1020 { 97, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1021 { 96, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1022 { 95, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1023 { 94, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1024 { 93, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1025 { 92, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1026 { 91, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1027 { 90, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1028 { 89, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1029 { 88, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1030 { 87, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1031 { 86, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1032 { 85, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1033 { 84, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1034 { 83, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1035 { 82, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1036 { 81, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1037 { 80, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1038 { 79, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1039 { 78, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1040 { 77, 5, 1, 0, 0, 0, 0, AVROpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1041 { 76, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1042 { 75, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1043 { 74, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1044 { 73, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1045 { 72, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1046 { 71, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1047 { 70, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1048 { 69, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1049 { 68, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1050 { 67, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1051 { 66, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1052 { 65, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1053 { 64, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1054 { 63, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1055 { 62, 4, 2, 0, 0, 0, 0, AVROpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1056 { 61, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1057 { 60, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1058 { 59, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1059 { 58, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1060 { 57, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1061 { 56, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1062 { 55, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1063 { 54, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1064 { 53, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1065 { 52, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1066 { 51, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1067 { 50, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1068 { 49, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1069 { 48, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1070 { 47, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1071 { 46, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1072 { 45, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1073 { 44, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1074 { 43, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1075 { 42, 3, 0, 0, 0, 0, 0, AVROpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15082
1076 { 41, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15081
1077 { 40, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1078 { 39, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1079 { 38, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1080 { 37, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1081 { 36, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1082 { 35, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1083 { 34, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1084 { 33, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1085 { 32, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15080
1086 { 31, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1087 { 30, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348
1088 { 29, 6, 1, 0, 0, 0, 0, AVROpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1089 { 28, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1090 { 27, 2, 0, 0, 0, 0, 0, AVROpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1091 { 26, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1092 { 25, 4, 0, 0, 0, 0, 0, AVROpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1093 { 24, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1094 { 23, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1095 { 22, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1096 { 21, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1097 { 20, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1098 { 19, 2, 1, 0, 0, 0, 0, AVROpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1099 { 18, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1100 { 17, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1101 { 16, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1102 { 15, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1103 { 14, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1104 { 13, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1105 { 12, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1106 { 11, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1107 { 10, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1108 { 9, 4, 1, 0, 0, 0, 0, AVROpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1109 { 8, 3, 1, 0, 0, 0, 0, AVROpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1110 { 7, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1111 { 6, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1112 { 5, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1113 { 4, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1114 { 3, 1, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1115 { 2, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1116 { 1, 0, 0, 0, 0, 0, 0, AVROpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1117 { 0, 1, 1, 0, 0, 0, 0, AVROpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1118 }, {
1119 /* 0 */
1120 /* 0 */ AVR::SREG, AVR::SREG,
1121 /* 2 */ AVR::SREG,
1122 /* 3 */ AVR::SP, AVR::SP, AVR::SREG,
1123 /* 6 */ AVR::SP, AVR::R31R30,
1124 /* 8 */ AVR::R0,
1125 /* 9 */ AVR::R31R30,
1126 /* 10 */ AVR::SP, AVR::SP,
1127 /* 12 */ AVR::R1, AVR::SREG,
1128 /* 14 */ AVR::R17, AVR::SREG,
1129 /* 16 */ AVR::SP,
1130 /* 17 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
1131 /* 33 */ AVR::R31R30, AVR::R0,
1132 /* 35 */ AVR::R1, AVR::R0, AVR::SREG,
1133 /* 38 */ AVR::R1, AVR::R0, AVR::R31R30,
1134 }, {
1135 0
1136 }, {
1137 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1138 /* 1 */
1139 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1140 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1141 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1142 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1143 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1144 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1145 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1146 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1147 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1148 /* 28 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1149 /* 29 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1150 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1151 /* 34 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1152 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1153 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1154 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1155 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1156 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1157 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1158 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1159 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1160 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1161 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1162 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1163 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1164 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1165 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1166 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1167 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1168 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1169 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1170 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1171 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1172 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1173 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1174 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1175 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1176 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1177 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1178 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1179 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1180 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1181 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1182 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1183 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1184 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1185 /* 151 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1186 /* 154 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1187 /* 157 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1188 /* 160 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1189 /* 162 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1190 /* 165 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1191 /* 168 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1192 /* 173 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1193 /* 176 */ { AVR::DREGSNOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1194 /* 178 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1195 /* 180 */ { AVR::DREGSNOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSNOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1196 /* 183 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1197 /* 186 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSNOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1198 /* 188 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1199 /* 190 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1200 /* 192 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1201 /* 193 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1202 /* 196 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1203 /* 199 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1204 /* 202 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1205 /* 206 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1206 /* 208 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1207 /* 210 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1208 /* 213 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1209 /* 216 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1210 /* 218 */ { AVR::DREGSNOZRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1211 /* 220 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
1212 /* 223 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1213 /* 225 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1214 /* 227 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1215 /* 229 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1216 /* 232 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1217 /* 235 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1218 /* 237 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1219 /* 238 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1220 /* 240 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1221 /* 242 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1222 /* 244 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1223 /* 246 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8NOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1224 /* 249 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1225 /* 252 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSNOZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1226 /* 255 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1227 /* 257 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1228 /* 261 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1229 /* 265 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1230 /* 269 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1231 /* 272 */ { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1232 /* 275 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1233 /* 278 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1234 /* 281 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1235 /* 283 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1236 /* 285 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1237 /* 287 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1238 /* 289 */ { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1239 /* 291 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1240 /* 293 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1241 /* 296 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
1242 /* 299 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1243 /* 301 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1244 /* 303 */ { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1245 /* 304 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1246 /* 307 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1247 /* 311 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1248 }
1249};
1250
1251
1252#ifdef __GNUC__
1253#pragma GCC diagnostic push
1254#pragma GCC diagnostic ignored "-Woverlength-strings"
1255#endif
1256extern const char AVRInstrNameData[] = {
1257 /* 0 */ "G_FLOG10\000"
1258 /* 9 */ "G_FEXP10\000"
1259 /* 18 */ "ROLBRdR1\000"
1260 /* 27 */ "Lsl32\000"
1261 /* 33 */ "Asr32\000"
1262 /* 39 */ "Lsr32\000"
1263 /* 45 */ "G_FLOG2\000"
1264 /* 53 */ "G_FATAN2\000"
1265 /* 62 */ "G_FEXP2\000"
1266 /* 70 */ "AtomicLoadSub16\000"
1267 /* 86 */ "AtomicLoad16\000"
1268 /* 99 */ "AtomicLoadAdd16\000"
1269 /* 115 */ "AtomicLoadAnd16\000"
1270 /* 131 */ "AtomicStore16\000"
1271 /* 145 */ "Rol16\000"
1272 /* 151 */ "Lsl16\000"
1273 /* 157 */ "AtomicLoadOr16\000"
1274 /* 172 */ "Ror16\000"
1275 /* 178 */ "AtomicLoadXor16\000"
1276 /* 194 */ "Asr16\000"
1277 /* 200 */ "Lsr16\000"
1278 /* 206 */ "Select16\000"
1279 /* 215 */ "ROLBRdR17\000"
1280 /* 225 */ "AtomicLoadSub8\000"
1281 /* 240 */ "AtomicLoad8\000"
1282 /* 252 */ "AtomicLoadAdd8\000"
1283 /* 267 */ "AtomicLoadAnd8\000"
1284 /* 282 */ "AtomicStore8\000"
1285 /* 295 */ "Rol8\000"
1286 /* 300 */ "Lsl8\000"
1287 /* 305 */ "AtomicLoadOr8\000"
1288 /* 319 */ "Ror8\000"
1289 /* 324 */ "AtomicLoadXor8\000"
1290 /* 339 */ "Asr8\000"
1291 /* 344 */ "Lsr8\000"
1292 /* 349 */ "Select8\000"
1293 /* 357 */ "G_FMA\000"
1294 /* 363 */ "G_STRICT_FMA\000"
1295 /* 376 */ "INRdA\000"
1296 /* 382 */ "INWRdA\000"
1297 /* 389 */ "G_FSUB\000"
1298 /* 396 */ "G_STRICT_FSUB\000"
1299 /* 410 */ "G_ATOMICRMW_FSUB\000"
1300 /* 427 */ "G_SUB\000"
1301 /* 433 */ "G_ATOMICRMW_SUB\000"
1302 /* 449 */ "SBRCRrB\000"
1303 /* 457 */ "SBRSRrB\000"
1304 /* 465 */ "G_INTRINSIC\000"
1305 /* 477 */ "G_FPTRUNC\000"
1306 /* 487 */ "G_INTRINSIC_TRUNC\000"
1307 /* 505 */ "G_TRUNC\000"
1308 /* 513 */ "G_BUILD_VECTOR_TRUNC\000"
1309 /* 534 */ "G_DYN_STACKALLOC\000"
1310 /* 551 */ "SPREAD\000"
1311 /* 558 */ "G_FMAD\000"
1312 /* 565 */ "G_FPEXTLOAD\000"
1313 /* 577 */ "G_INDEXED_SEXTLOAD\000"
1314 /* 596 */ "G_SEXTLOAD\000"
1315 /* 607 */ "G_INDEXED_ZEXTLOAD\000"
1316 /* 626 */ "G_ZEXTLOAD\000"
1317 /* 637 */ "G_INDEXED_LOAD\000"
1318 /* 652 */ "G_LOAD\000"
1319 /* 659 */ "G_VECREDUCE_FADD\000"
1320 /* 676 */ "G_FADD\000"
1321 /* 683 */ "G_VECREDUCE_SEQ_FADD\000"
1322 /* 704 */ "G_STRICT_FADD\000"
1323 /* 718 */ "G_ATOMICRMW_FADD\000"
1324 /* 735 */ "G_VECREDUCE_ADD\000"
1325 /* 751 */ "G_ADD\000"
1326 /* 757 */ "G_PTR_ADD\000"
1327 /* 767 */ "G_ATOMICRMW_ADD\000"
1328 /* 783 */ "BLD\000"
1329 /* 787 */ "G_ATOMICRMW_NAND\000"
1330 /* 804 */ "G_VECREDUCE_AND\000"
1331 /* 820 */ "G_AND\000"
1332 /* 826 */ "G_ATOMICRMW_AND\000"
1333 /* 842 */ "LIFETIME_END\000"
1334 /* 855 */ "G_BRCOND\000"
1335 /* 864 */ "G_ATOMICRMW_USUB_COND\000"
1336 /* 886 */ "G_LLROUND\000"
1337 /* 896 */ "G_LROUND\000"
1338 /* 905 */ "G_INTRINSIC_ROUND\000"
1339 /* 923 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1340 /* 949 */ "LOAD_STACK_GUARD\000"
1341 /* 966 */ "PSEUDO_PROBE\000"
1342 /* 979 */ "G_SSUBE\000"
1343 /* 987 */ "G_USUBE\000"
1344 /* 995 */ "G_FENCE\000"
1345 /* 1003 */ "ARITH_FENCE\000"
1346 /* 1015 */ "REG_SEQUENCE\000"
1347 /* 1028 */ "G_SADDE\000"
1348 /* 1036 */ "G_UADDE\000"
1349 /* 1044 */ "G_GET_FPMODE\000"
1350 /* 1057 */ "G_RESET_FPMODE\000"
1351 /* 1072 */ "G_SET_FPMODE\000"
1352 /* 1085 */ "G_FMINNUM_IEEE\000"
1353 /* 1100 */ "G_FMAXNUM_IEEE\000"
1354 /* 1115 */ "G_VSCALE\000"
1355 /* 1124 */ "G_JUMP_TABLE\000"
1356 /* 1137 */ "BUNDLE\000"
1357 /* 1144 */ "G_MEMSET_INLINE\000"
1358 /* 1160 */ "G_MEMCPY_INLINE\000"
1359 /* 1176 */ "RELOC_NONE\000"
1360 /* 1187 */ "LOCAL_ESCAPE\000"
1361 /* 1200 */ "G_FPTRUNCSTORE\000"
1362 /* 1215 */ "G_STACKRESTORE\000"
1363 /* 1230 */ "G_INDEXED_STORE\000"
1364 /* 1246 */ "G_STORE\000"
1365 /* 1254 */ "CPSE\000"
1366 /* 1259 */ "G_BITREVERSE\000"
1367 /* 1272 */ "FAKE_USE\000"
1368 /* 1281 */ "SPWRITE\000"
1369 /* 1289 */ "DBG_VALUE\000"
1370 /* 1299 */ "G_GLOBAL_VALUE\000"
1371 /* 1314 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1372 /* 1337 */ "CONVERGENCECTRL_GLUE\000"
1373 /* 1358 */ "G_STACKSAVE\000"
1374 /* 1370 */ "G_MEMMOVE\000"
1375 /* 1380 */ "G_FREEZE\000"
1376 /* 1389 */ "G_FCANONICALIZE\000"
1377 /* 1405 */ "G_FMODF\000"
1378 /* 1413 */ "INIT_UNDEF\000"
1379 /* 1424 */ "G_IMPLICIT_DEF\000"
1380 /* 1439 */ "DBG_INSTR_REF\000"
1381 /* 1453 */ "G_FNEG\000"
1382 /* 1460 */ "EXTRACT_SUBREG\000"
1383 /* 1475 */ "INSERT_SUBREG\000"
1384 /* 1489 */ "G_SEXT_INREG\000"
1385 /* 1502 */ "SUBREG_TO_REG\000"
1386 /* 1516 */ "G_ATOMIC_CMPXCHG\000"
1387 /* 1533 */ "G_ATOMICRMW_XCHG\000"
1388 /* 1550 */ "G_GET_ROUNDING\000"
1389 /* 1565 */ "G_SET_ROUNDING\000"
1390 /* 1580 */ "G_FLOG\000"
1391 /* 1587 */ "G_VAARG\000"
1392 /* 1595 */ "PREALLOCATED_ARG\000"
1393 /* 1612 */ "G_PREFETCH\000"
1394 /* 1623 */ "G_CLMULH\000"
1395 /* 1632 */ "G_SMULH\000"
1396 /* 1640 */ "G_UMULH\000"
1397 /* 1648 */ "G_FTANH\000"
1398 /* 1656 */ "G_FSINH\000"
1399 /* 1664 */ "G_FCOSH\000"
1400 /* 1672 */ "DBG_PHI\000"
1401 /* 1680 */ "G_FPTOSI\000"
1402 /* 1689 */ "RETI\000"
1403 /* 1694 */ "G_FPTOUI\000"
1404 /* 1703 */ "G_FPOWI\000"
1405 /* 1711 */ "BREAK\000"
1406 /* 1717 */ "COPY_LANEMASK\000"
1407 /* 1731 */ "G_PTRMASK\000"
1408 /* 1741 */ "DESK\000"
1409 /* 1746 */ "SUBIRdK\000"
1410 /* 1754 */ "SBCIRdK\000"
1411 /* 1762 */ "LDIRdK\000"
1412 /* 1769 */ "ANDIRdK\000"
1413 /* 1777 */ "CPIRdK\000"
1414 /* 1784 */ "ORIRdK\000"
1415 /* 1791 */ "LDSRdK\000"
1416 /* 1798 */ "SBIWRdK\000"
1417 /* 1806 */ "SUBIWRdK\000"
1418 /* 1815 */ "SBCIWRdK\000"
1419 /* 1824 */ "ADIWRdK\000"
1420 /* 1832 */ "LDIWRdK\000"
1421 /* 1840 */ "ANDIWRdK\000"
1422 /* 1849 */ "ORIWRdK\000"
1423 /* 1857 */ "LDSWRdK\000"
1424 /* 1865 */ "GC_LABEL\000"
1425 /* 1874 */ "DBG_LABEL\000"
1426 /* 1884 */ "EH_LABEL\000"
1427 /* 1893 */ "ANNOTATION_LABEL\000"
1428 /* 1910 */ "ICALL_BRANCH_FUNNEL\000"
1429 /* 1930 */ "G_FSHL\000"
1430 /* 1937 */ "G_SHL\000"
1431 /* 1943 */ "G_FCEIL\000"
1432 /* 1951 */ "G_SAVGCEIL\000"
1433 /* 1962 */ "G_UAVGCEIL\000"
1434 /* 1973 */ "EICALL\000"
1435 /* 1980 */ "PATCHABLE_TAIL_CALL\000"
1436 /* 2000 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1437 /* 2027 */ "PATCHABLE_EVENT_CALL\000"
1438 /* 2048 */ "FENTRY_CALL\000"
1439 /* 2060 */ "KILL\000"
1440 /* 2065 */ "G_CONSTANT_POOL\000"
1441 /* 2081 */ "G_ROTL\000"
1442 /* 2088 */ "G_VECREDUCE_FMUL\000"
1443 /* 2105 */ "G_FMUL\000"
1444 /* 2112 */ "G_VECREDUCE_SEQ_FMUL\000"
1445 /* 2133 */ "G_STRICT_FMUL\000"
1446 /* 2147 */ "G_CLMUL\000"
1447 /* 2155 */ "G_VECREDUCE_MUL\000"
1448 /* 2171 */ "G_MUL\000"
1449 /* 2177 */ "G_FREM\000"
1450 /* 2184 */ "G_STRICT_FREM\000"
1451 /* 2198 */ "G_SREM\000"
1452 /* 2205 */ "G_UREM\000"
1453 /* 2212 */ "G_SDIVREM\000"
1454 /* 2222 */ "G_UDIVREM\000"
1455 /* 2232 */ "ELPM\000"
1456 /* 2237 */ "SPM\000"
1457 /* 2241 */ "INLINEASM\000"
1458 /* 2251 */ "G_VECREDUCE_FMINIMUM\000"
1459 /* 2272 */ "G_FMINIMUM\000"
1460 /* 2283 */ "G_ATOMICRMW_FMINIMUM\000"
1461 /* 2304 */ "G_VECREDUCE_FMAXIMUM\000"
1462 /* 2325 */ "G_FMAXIMUM\000"
1463 /* 2336 */ "G_ATOMICRMW_FMAXIMUM\000"
1464 /* 2357 */ "G_VECREDUCE_FMINIMUMNUM\000"
1465 /* 2381 */ "G_FMINIMUMNUM\000"
1466 /* 2395 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1467 /* 2419 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1468 /* 2443 */ "G_FMAXIMUMNUM\000"
1469 /* 2457 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1470 /* 2481 */ "G_FMINNUM\000"
1471 /* 2491 */ "G_FMAXNUM\000"
1472 /* 2501 */ "G_FATAN\000"
1473 /* 2509 */ "G_FTAN\000"
1474 /* 2516 */ "G_INTRINSIC_ROUNDEVEN\000"
1475 /* 2538 */ "G_ASSERT_ALIGN\000"
1476 /* 2553 */ "G_FCOPYSIGN\000"
1477 /* 2565 */ "G_VECREDUCE_FMIN\000"
1478 /* 2582 */ "G_ATOMICRMW_FMIN\000"
1479 /* 2599 */ "G_VECREDUCE_SMIN\000"
1480 /* 2616 */ "G_SMIN\000"
1481 /* 2623 */ "G_VECREDUCE_UMIN\000"
1482 /* 2640 */ "G_UMIN\000"
1483 /* 2647 */ "G_ATOMICRMW_UMIN\000"
1484 /* 2664 */ "G_ATOMICRMW_MIN\000"
1485 /* 2680 */ "G_FASIN\000"
1486 /* 2688 */ "G_FSIN\000"
1487 /* 2695 */ "CFI_INSTRUCTION\000"
1488 /* 2711 */ "G_CTLZ_ZERO_POISON\000"
1489 /* 2730 */ "G_CTTZ_ZERO_POISON\000"
1490 /* 2749 */ "ADJCALLSTACKDOWN\000"
1491 /* 2766 */ "G_SSUBO\000"
1492 /* 2774 */ "G_USUBO\000"
1493 /* 2782 */ "G_SADDO\000"
1494 /* 2790 */ "G_UADDO\000"
1495 /* 2798 */ "JUMP_TABLE_DEBUG_INFO\000"
1496 /* 2820 */ "G_SMULO\000"
1497 /* 2828 */ "G_UMULO\000"
1498 /* 2836 */ "G_BZERO\000"
1499 /* 2844 */ "STACKMAP\000"
1500 /* 2853 */ "G_DEBUGTRAP\000"
1501 /* 2865 */ "G_UBSANTRAP\000"
1502 /* 2877 */ "G_TRAP\000"
1503 /* 2884 */ "G_ATOMICRMW_UDEC_WRAP\000"
1504 /* 2906 */ "G_ATOMICRMW_UINC_WRAP\000"
1505 /* 2928 */ "G_BSWAP\000"
1506 /* 2936 */ "SLEEP\000"
1507 /* 2942 */ "G_SITOFP\000"
1508 /* 2951 */ "G_UITOFP\000"
1509 /* 2960 */ "ADIWRdKP\000"
1510 /* 2969 */ "G_FCMP\000"
1511 /* 2976 */ "G_STRICT_FCMP\000"
1512 /* 2990 */ "G_ICMP\000"
1513 /* 2997 */ "G_SCMP\000"
1514 /* 3004 */ "G_UCMP\000"
1515 /* 3011 */ "EIJMP\000"
1516 /* 3017 */ "NOP\000"
1517 /* 3021 */ "CONVERGENCECTRL_LOOP\000"
1518 /* 3042 */ "G_CTPOP\000"
1519 /* 3050 */ "PATCHABLE_OP\000"
1520 /* 3063 */ "FAULTING_OP\000"
1521 /* 3075 */ "FRMSP\000"
1522 /* 3081 */ "ADJCALLSTACKUP\000"
1523 /* 3096 */ "PREALLOCATED_SETUP\000"
1524 /* 3115 */ "G_FLDEXP\000"
1525 /* 3124 */ "G_STRICT_FLDEXP\000"
1526 /* 3140 */ "G_FEXP\000"
1527 /* 3147 */ "G_FFREXP\000"
1528 /* 3156 */ "LDDWRdYQ\000"
1529 /* 3165 */ "LDDRdPtrQ\000"
1530 /* 3175 */ "LDDWRdPtrQ\000"
1531 /* 3186 */ "G_BR\000"
1532 /* 3191 */ "INLINEASM_BR\000"
1533 /* 3204 */ "G_BLOCK_ADDR\000"
1534 /* 3217 */ "WDR\000"
1535 /* 3221 */ "MEMBARRIER\000"
1536 /* 3232 */ "G_CONSTANT_FOLD_BARRIER\000"
1537 /* 3256 */ "PATCHABLE_FUNCTION_ENTER\000"
1538 /* 3281 */ "G_READCYCLECOUNTER\000"
1539 /* 3300 */ "G_READSTEADYCOUNTER\000"
1540 /* 3320 */ "G_READ_REGISTER\000"
1541 /* 3336 */ "G_WRITE_REGISTER\000"
1542 /* 3353 */ "G_ASHR\000"
1543 /* 3360 */ "G_FSHR\000"
1544 /* 3367 */ "G_LSHR\000"
1545 /* 3374 */ "CONVERGENCECTRL_ANCHOR\000"
1546 /* 3397 */ "G_FFLOOR\000"
1547 /* 3406 */ "G_SAVGFLOOR\000"
1548 /* 3418 */ "G_UAVGFLOOR\000"
1549 /* 3430 */ "G_EXTRACT_SUBVECTOR\000"
1550 /* 3450 */ "G_INSERT_SUBVECTOR\000"
1551 /* 3469 */ "G_BUILD_VECTOR\000"
1552 /* 3484 */ "G_SHUFFLE_VECTOR\000"
1553 /* 3501 */ "G_STEP_VECTOR\000"
1554 /* 3515 */ "G_SPLAT_VECTOR\000"
1555 /* 3530 */ "G_VECREDUCE_XOR\000"
1556 /* 3546 */ "G_XOR\000"
1557 /* 3552 */ "G_ATOMICRMW_XOR\000"
1558 /* 3568 */ "G_VECREDUCE_OR\000"
1559 /* 3583 */ "G_OR\000"
1560 /* 3588 */ "G_ATOMICRMW_OR\000"
1561 /* 3603 */ "G_ROTR\000"
1562 /* 3610 */ "G_INTTOPTR\000"
1563 /* 3621 */ "G_FABS\000"
1564 /* 3628 */ "G_ABS\000"
1565 /* 3634 */ "G_ABDS\000"
1566 /* 3641 */ "G_UNMERGE_VALUES\000"
1567 /* 3658 */ "G_MERGE_VALUES\000"
1568 /* 3673 */ "G_CTLS\000"
1569 /* 3680 */ "FMULS\000"
1570 /* 3686 */ "G_FACOS\000"
1571 /* 3694 */ "G_FCOS\000"
1572 /* 3701 */ "G_FSINCOS\000"
1573 /* 3711 */ "G_STRICT_FCMPS\000"
1574 /* 3726 */ "G_CONCAT_VECTORS\000"
1575 /* 3743 */ "COPY_TO_REGCLASS\000"
1576 /* 3760 */ "G_IS_FPCLASS\000"
1577 /* 3773 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1578 /* 3803 */ "G_VECTOR_COMPRESS\000"
1579 /* 3821 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1580 /* 3848 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1581 /* 3886 */ "G_TRUNC_SSAT_S\000"
1582 /* 3901 */ "G_SSUBSAT\000"
1583 /* 3911 */ "G_USUBSAT\000"
1584 /* 3921 */ "G_SADDSAT\000"
1585 /* 3931 */ "G_UADDSAT\000"
1586 /* 3941 */ "G_SSHLSAT\000"
1587 /* 3951 */ "G_USHLSAT\000"
1588 /* 3961 */ "G_SMULFIXSAT\000"
1589 /* 3974 */ "G_UMULFIXSAT\000"
1590 /* 3987 */ "G_SDIVFIXSAT\000"
1591 /* 4000 */ "G_UDIVFIXSAT\000"
1592 /* 4013 */ "G_ATOMICRMW_USUB_SAT\000"
1593 /* 4034 */ "G_FPTOSI_SAT\000"
1594 /* 4047 */ "G_FPTOUI_SAT\000"
1595 /* 4060 */ "G_EXTRACT\000"
1596 /* 4070 */ "G_SELECT\000"
1597 /* 4079 */ "G_BRINDIRECT\000"
1598 /* 4092 */ "PATCHABLE_RET\000"
1599 /* 4106 */ "G_MEMSET\000"
1600 /* 4115 */ "PATCHABLE_FUNCTION_EXIT\000"
1601 /* 4139 */ "G_BRJT\000"
1602 /* 4146 */ "G_EXTRACT_VECTOR_ELT\000"
1603 /* 4167 */ "G_INSERT_VECTOR_ELT\000"
1604 /* 4187 */ "G_FCONSTANT\000"
1605 /* 4199 */ "G_CONSTANT\000"
1606 /* 4210 */ "G_INTRINSIC_CONVERGENT\000"
1607 /* 4233 */ "STATEPOINT\000"
1608 /* 4244 */ "PATCHPOINT\000"
1609 /* 4255 */ "G_PTRTOINT\000"
1610 /* 4266 */ "G_FRINT\000"
1611 /* 4274 */ "G_INTRINSIC_LLRINT\000"
1612 /* 4293 */ "G_INTRINSIC_LRINT\000"
1613 /* 4311 */ "G_FNEARBYINT\000"
1614 /* 4324 */ "G_VASTART\000"
1615 /* 4334 */ "LIFETIME_START\000"
1616 /* 4349 */ "G_INVOKE_REGION_START\000"
1617 /* 4371 */ "G_INSERT\000"
1618 /* 4380 */ "G_FSQRT\000"
1619 /* 4388 */ "G_STRICT_FSQRT\000"
1620 /* 4403 */ "G_BITCAST\000"
1621 /* 4413 */ "G_ADDRSPACE_CAST\000"
1622 /* 4430 */ "BST\000"
1623 /* 4434 */ "DBG_VALUE_LIST\000"
1624 /* 4449 */ "G_FPEXT\000"
1625 /* 4457 */ "G_SEXT\000"
1626 /* 4464 */ "G_ASSERT_SEXT\000"
1627 /* 4478 */ "G_ANYEXT\000"
1628 /* 4487 */ "G_ZEXT\000"
1629 /* 4494 */ "G_ASSERT_ZEXT\000"
1630 /* 4508 */ "G_ABDU\000"
1631 /* 4515 */ "FMULSU\000"
1632 /* 4522 */ "G_TRUNC_SSAT_U\000"
1633 /* 4537 */ "G_TRUNC_USAT_U\000"
1634 /* 4552 */ "G_FDIV\000"
1635 /* 4559 */ "G_STRICT_FDIV\000"
1636 /* 4573 */ "G_SDIV\000"
1637 /* 4580 */ "G_UDIV\000"
1638 /* 4587 */ "G_GET_FPENV\000"
1639 /* 4599 */ "G_RESET_FPENV\000"
1640 /* 4613 */ "G_SET_FPENV\000"
1641 /* 4625 */ "G_FPOW\000"
1642 /* 4632 */ "G_VECREDUCE_FMAX\000"
1643 /* 4649 */ "G_ATOMICRMW_FMAX\000"
1644 /* 4666 */ "G_VECREDUCE_SMAX\000"
1645 /* 4683 */ "G_SMAX\000"
1646 /* 4690 */ "G_VECREDUCE_UMAX\000"
1647 /* 4707 */ "G_UMAX\000"
1648 /* 4714 */ "G_ATOMICRMW_UMAX\000"
1649 /* 4731 */ "G_ATOMICRMW_MAX\000"
1650 /* 4747 */ "FRMIDX\000"
1651 /* 4754 */ "G_FRAME_INDEX\000"
1652 /* 4768 */ "G_SBFX\000"
1653 /* 4775 */ "G_UBFX\000"
1654 /* 4782 */ "G_SMULFIX\000"
1655 /* 4792 */ "G_UMULFIX\000"
1656 /* 4802 */ "G_SDIVFIX\000"
1657 /* 4812 */ "G_UDIVFIX\000"
1658 /* 4822 */ "G_MEMCPY\000"
1659 /* 4831 */ "COPY\000"
1660 /* 4836 */ "CONVERGENCECTRL_ENTRY\000"
1661 /* 4858 */ "G_CTLZ\000"
1662 /* 4865 */ "G_CTTZ\000"
1663 /* 4872 */ "ELPMBRdZ\000"
1664 /* 4881 */ "ELPMRdZ\000"
1665 /* 4889 */ "ELPMWRdZ\000"
1666 /* 4898 */ "SBICAb\000"
1667 /* 4905 */ "CBIAb\000"
1668 /* 4911 */ "SBIAb\000"
1669 /* 4917 */ "SBISAb\000"
1670 /* 4924 */ "LDRdPtrPd\000"
1671 /* 4934 */ "LDWRdPtrPd\000"
1672 /* 4945 */ "RORBRd\000"
1673 /* 4952 */ "DECRd\000"
1674 /* 4958 */ "INCRd\000"
1675 /* 4964 */ "NEGRd\000"
1676 /* 4970 */ "COMRd\000"
1677 /* 4976 */ "LSLBNRd\000"
1678 /* 4984 */ "ASRBNRd\000"
1679 /* 4992 */ "LSRBNRd\000"
1680 /* 5000 */ "LSLWNRd\000"
1681 /* 5008 */ "ASRWNRd\000"
1682 /* 5016 */ "LSRWNRd\000"
1683 /* 5024 */ "SWAPRd\000"
1684 /* 5031 */ "POPRd\000"
1685 /* 5037 */ "RORRd\000"
1686 /* 5043 */ "ASRRd\000"
1687 /* 5049 */ "LSRRd\000"
1688 /* 5055 */ "NEGWRd\000"
1689 /* 5062 */ "ROLWRd\000"
1690 /* 5069 */ "LSLWRd\000"
1691 /* 5076 */ "COMWRd\000"
1692 /* 5083 */ "POPWRd\000"
1693 /* 5090 */ "RORWRd\000"
1694 /* 5097 */ "ASRWRd\000"
1695 /* 5104 */ "LSRWRd\000"
1696 /* 5111 */ "LACZRd\000"
1697 /* 5118 */ "XCHZRd\000"
1698 /* 5125 */ "LASZRd\000"
1699 /* 5132 */ "LATZRd\000"
1700 /* 5139 */ "LSLWHiRd\000"
1701 /* 5148 */ "ASRWLoRd\000"
1702 /* 5157 */ "LSRWLoRd\000"
1703 /* 5166 */ "AtomicFence\000"
1704 /* 5178 */ "SPMZPi\000"
1705 /* 5185 */ "ELPMBRdZPi\000"
1706 /* 5196 */ "ELPMRdZPi\000"
1707 /* 5206 */ "ELPMWRdZPi\000"
1708 /* 5217 */ "LDRdPtrPi\000"
1709 /* 5227 */ "LDWRdPtrPi\000"
1710 /* 5238 */ "BRGEk\000"
1711 /* 5244 */ "BRNEk\000"
1712 /* 5250 */ "BRSHk\000"
1713 /* 5256 */ "BRMIk\000"
1714 /* 5262 */ "RCALLk\000"
1715 /* 5269 */ "BRPLk\000"
1716 /* 5275 */ "BRLOk\000"
1717 /* 5281 */ "RJMPk\000"
1718 /* 5287 */ "BREQk\000"
1719 /* 5293 */ "BRLTk\000"
1720 /* 5299 */ "BRBCsk\000"
1721 /* 5306 */ "BRBSsk\000"
1722 /* 5313 */ "CopyZero\000"
1723 /* 5322 */ "OUTARr\000"
1724 /* 5329 */ "OUTWARr\000"
1725 /* 5337 */ "PUSHRr\000"
1726 /* 5344 */ "STSKRr\000"
1727 /* 5351 */ "STSWKRr\000"
1728 /* 5359 */ "STDSPQRr\000"
1729 /* 5368 */ "STDWSPQRr\000"
1730 /* 5378 */ "STDPtrQRr\000"
1731 /* 5388 */ "STDWPtrQRr\000"
1732 /* 5399 */ "PUSHWRr\000"
1733 /* 5407 */ "STPtrPdRr\000"
1734 /* 5417 */ "STWPtrPdRr\000"
1735 /* 5428 */ "SUBRdRr\000"
1736 /* 5436 */ "SBCRdRr\000"
1737 /* 5444 */ "ADCRdRr\000"
1738 /* 5452 */ "CPCRdRr\000"
1739 /* 5460 */ "ADDRdRr\000"
1740 /* 5468 */ "ANDRdRr\000"
1741 /* 5476 */ "MULRdRr\000"
1742 /* 5484 */ "CPRdRr\000"
1743 /* 5491 */ "EORRdRr\000"
1744 /* 5499 */ "MULSRdRr\000"
1745 /* 5508 */ "MULSURdRr\000"
1746 /* 5518 */ "MOVRdRr\000"
1747 /* 5526 */ "SUBWRdRr\000"
1748 /* 5535 */ "SBCWRdRr\000"
1749 /* 5544 */ "ADCWRdRr\000"
1750 /* 5553 */ "CPCWRdRr\000"
1751 /* 5562 */ "ADDWRdRr\000"
1752 /* 5571 */ "ANDWRdRr\000"
1753 /* 5580 */ "CPWRdRr\000"
1754 /* 5588 */ "EORWRdRr\000"
1755 /* 5597 */ "MOVWRdRr\000"
1756 /* 5606 */ "STPtrPiRr\000"
1757 /* 5616 */ "STWPtrPiRr\000"
1758 /* 5627 */ "STPtrRr\000"
1759 /* 5635 */ "STWPtrRr\000"
1760 /* 5644 */ "LDRdPtr\000"
1761 /* 5652 */ "LDWRdPtr\000"
1762 /* 5661 */ "BCLRs\000"
1763 /* 5667 */ "BSETs\000"
1764 /* 5673 */ "LDSRdKTiny\000"
1765 /* 5684 */ "STSKRrTiny\000"
1766};
1767#ifdef __GNUC__
1768#pragma GCC diagnostic pop
1769#endif
1770
1771extern const unsigned AVRInstrNameIndices[] = {
1772 1676U, 2241U, 3191U, 2695U, 1884U, 1865U, 1893U, 2060U,
1773 1460U, 1475U, 1426U, 1413U, 1502U, 3743U, 1289U, 4434U,
1774 1439U, 1672U, 1874U, 1015U, 4831U, 1717U, 1137U, 4334U,
1775 842U, 966U, 1003U, 2844U, 2048U, 4244U, 949U, 3096U,
1776 1595U, 4233U, 1187U, 3063U, 3050U, 3256U, 4092U, 4115U,
1777 1980U, 2027U, 2000U, 1910U, 1272U, 3221U, 2798U, 1176U,
1778 4836U, 3374U, 3021U, 1337U, 4464U, 4494U, 2538U, 751U,
1779 427U, 2171U, 4573U, 4580U, 2198U, 2205U, 2212U, 2222U,
1780 820U, 3583U, 3546U, 3634U, 4508U, 3418U, 1962U, 3406U,
1781 1951U, 1424U, 1674U, 4754U, 1299U, 1314U, 2065U, 4060U,
1782 3641U, 4371U, 3658U, 3469U, 513U, 3726U, 4255U, 3610U,
1783 4403U, 1380U, 3232U, 923U, 487U, 905U, 4293U, 4274U,
1784 2516U, 3281U, 3300U, 652U, 596U, 626U, 565U, 637U,
1785 577U, 607U, 1246U, 1200U, 1230U, 3773U, 1516U, 1533U,
1786 767U, 433U, 826U, 787U, 3588U, 3552U, 4731U, 2664U,
1787 4714U, 2647U, 718U, 410U, 4649U, 2582U, 2336U, 2283U,
1788 2457U, 2395U, 2906U, 2884U, 864U, 4013U, 995U, 1612U,
1789 855U, 4079U, 4349U, 465U, 3821U, 4210U, 3848U, 4478U,
1790 505U, 3886U, 4522U, 4537U, 4199U, 4187U, 4324U, 1587U,
1791 4457U, 1489U, 4487U, 1937U, 3367U, 3353U, 1930U, 3360U,
1792 3603U, 2081U, 2990U, 2969U, 2997U, 3004U, 4070U, 2790U,
1793 1036U, 2774U, 987U, 2782U, 1028U, 2766U, 979U, 2828U,
1794 2820U, 1640U, 1632U, 3931U, 3921U, 3911U, 3901U, 3951U,
1795 3941U, 4782U, 4792U, 3961U, 3974U, 4802U, 4812U, 3987U,
1796 4000U, 676U, 389U, 2105U, 357U, 558U, 4552U, 2177U,
1797 1405U, 4625U, 1703U, 3140U, 62U, 9U, 1580U, 45U,
1798 0U, 3115U, 3147U, 1453U, 4449U, 477U, 1680U, 1694U,
1799 2942U, 2951U, 4034U, 4047U, 3621U, 2553U, 3760U, 1389U,
1800 2481U, 2491U, 1085U, 1100U, 2272U, 2325U, 2381U, 2443U,
1801 4587U, 4613U, 4599U, 1044U, 1072U, 1057U, 1550U, 1565U,
1802 757U, 1731U, 2616U, 4683U, 2640U, 4707U, 3628U, 896U,
1803 886U, 3186U, 4139U, 1115U, 3450U, 3430U, 4167U, 4146U,
1804 3484U, 3515U, 3501U, 3803U, 4865U, 2730U, 4858U, 2711U,
1805 3673U, 3042U, 2928U, 1259U, 2147U, 1623U, 1943U, 3694U,
1806 2688U, 3701U, 2509U, 3686U, 2680U, 2501U, 53U, 1664U,
1807 1656U, 1648U, 4380U, 3397U, 4266U, 4311U, 4413U, 3204U,
1808 1124U, 534U, 1358U, 1215U, 704U, 396U, 2133U, 4559U,
1809 2184U, 363U, 4388U, 3124U, 2976U, 3711U, 3320U, 3336U,
1810 4822U, 1160U, 1370U, 4106U, 2836U, 1144U, 2877U, 2853U,
1811 2865U, 683U, 2112U, 659U, 2088U, 4632U, 2565U, 2304U,
1812 2251U, 2419U, 2357U, 735U, 2155U, 804U, 3568U, 3530U,
1813 4666U, 2599U, 4690U, 2623U, 4768U, 4775U, 5544U, 5562U,
1814 2960U, 2749U, 3081U, 1840U, 5571U, 4984U, 5148U, 5008U,
1815 5097U, 194U, 33U, 339U, 5166U, 86U, 240U, 99U,
1816 252U, 115U, 267U, 157U, 305U, 70U, 225U, 178U,
1817 324U, 131U, 282U, 5076U, 5553U, 5580U, 5313U, 4872U,
1818 5185U, 4889U, 5206U, 5588U, 4747U, 3075U, 382U, 3175U,
1819 3156U, 1832U, 1857U, 5652U, 4934U, 5227U, 4873U, 4890U,
1820 5207U, 4976U, 5139U, 5000U, 5069U, 4992U, 5157U, 5016U,
1821 5104U, 151U, 27U, 300U, 200U, 39U, 344U, 5055U,
1822 1849U, 5589U, 5329U, 5083U, 5399U, 18U, 215U, 5062U,
1823 4945U, 5090U, 145U, 295U, 172U, 319U, 1815U, 5535U,
1824 4459U, 551U, 1281U, 5359U, 5388U, 5368U, 5351U, 5417U,
1825 5616U, 5635U, 1806U, 5526U, 206U, 349U, 4489U, 5444U,
1826 5460U, 1824U, 1769U, 5468U, 5043U, 5661U, 783U, 5299U,
1827 5306U, 1711U, 5287U, 5238U, 5275U, 5293U, 5256U, 5244U,
1828 5269U, 5250U, 5667U, 4430U, 5263U, 4905U, 4970U, 5452U,
1829 1777U, 5484U, 1254U, 4952U, 1741U, 1973U, 3011U, 2232U,
1830 4881U, 5196U, 5491U, 2100U, 3680U, 4515U, 1974U, 3012U,
1831 4958U, 376U, 5282U, 5111U, 5125U, 5132U, 3165U, 1762U,
1832 5644U, 4924U, 5217U, 1791U, 5673U, 2233U, 4882U, 5197U,
1833 5049U, 5518U, 5597U, 5476U, 5499U, 5508U, 4964U, 3017U,
1834 1784U, 5492U, 5322U, 5031U, 5337U, 5262U, 4102U, 1689U,
1835 5281U, 5037U, 1754U, 5436U, 4911U, 4898U, 4917U, 1798U,
1836 449U, 457U, 2936U, 2237U, 5178U, 5378U, 5407U, 5606U,
1837 5627U, 5344U, 5684U, 1746U, 5428U, 5024U, 3217U, 5118U,
1838};
1839
1840static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
1841 II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 528, nullptr, 0);
1842}
1843
1844
1845} // namespace llvm
1846
1847#endif // GET_INSTRINFO_MC_DESC
1848
1849#ifdef GET_INSTRINFO_HEADER
1850#undef GET_INSTRINFO_HEADER
1851
1852namespace llvm {
1853
1854struct AVRGenInstrInfo : public TargetInstrInfo {
1855 explicit AVRGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1856 ~AVRGenInstrInfo() override = default;
1857};
1858
1859} // namespace llvm
1860
1861namespace llvm::AVR {
1862
1863
1864} // namespace llvm::AVR
1865
1866#endif // GET_INSTRINFO_HEADER
1867
1868#ifdef GET_INSTRINFO_HELPER_DECLS
1869#undef GET_INSTRINFO_HELPER_DECLS
1870
1871
1872#endif // GET_INSTRINFO_HELPER_DECLS
1873
1874#ifdef GET_INSTRINFO_HELPERS
1875#undef GET_INSTRINFO_HELPERS
1876
1877
1878#endif // GET_INSTRINFO_HELPERS
1879
1880#ifdef GET_INSTRINFO_CTOR_DTOR
1881#undef GET_INSTRINFO_CTOR_DTOR
1882
1883namespace llvm {
1884
1885extern const AVRInstrTable AVRDescs;
1886extern const unsigned AVRInstrNameIndices[];
1887extern const char AVRInstrNameData[];
1888AVRGenInstrInfo::AVRGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1889 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1890 InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 528);
1891}
1892
1893} // namespace llvm
1894
1895#endif // GET_INSTRINFO_CTOR_DTOR
1896
1897#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1898#undef GET_INSTRINFO_MC_HELPER_DECLS
1899
1900namespace llvm {
1901
1902class MCInst;
1903class FeatureBitset;
1904
1905namespace AVR_MC {
1906
1907void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1908
1909} // namespace AVR_MC
1910
1911} // namespace llvm
1912
1913#endif // GET_INSTRINFO_MC_HELPER_DECLS
1914
1915#ifdef GET_INSTRINFO_MC_HELPERS
1916#undef GET_INSTRINFO_MC_HELPERS
1917
1918namespace llvm::AVR_MC {
1919
1920
1921} // namespace llvm::AVR_MC
1922
1923#endif // GET_INSTRINFO_MC_HELPERS
1924
1925#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1926 defined(GET_AVAILABLE_OPCODE_CHECKER)
1927#define GET_COMPUTE_FEATURES
1928#endif
1929#ifdef GET_COMPUTE_FEATURES
1930#undef GET_COMPUTE_FEATURES
1931
1932namespace llvm::AVR_MC {
1933
1934// Bits for subtarget features that participate in instruction matching.
1935enum SubtargetFeatureBits : uint8_t {
1936 Feature_HasSRAMBit = 14,
1937 Feature_HasJMPCALLBit = 7,
1938 Feature_HasIJMPCALLBit = 6,
1939 Feature_HasEIJMPCALLBit = 3,
1940 Feature_HasADDSUBIWBit = 0,
1941 Feature_HasSmallStackBit = 15,
1942 Feature_HasMOVWBit = 10,
1943 Feature_HasLPMBit = 8,
1944 Feature_HasLPMXBit = 9,
1945 Feature_HasELPMBit = 4,
1946 Feature_HasELPMXBit = 5,
1947 Feature_HasSPMBit = 12,
1948 Feature_HasSPMXBit = 13,
1949 Feature_HasDESBit = 2,
1950 Feature_SupportsRMWBit = 18,
1951 Feature_SupportsMultiplicationBit = 17,
1952 Feature_HasBREAKBit = 1,
1953 Feature_HasTinyEncodingBit = 16,
1954 Feature_HasNonTinyEncodingBit = 11,
1955};
1956
1957inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1958 FeatureBitset Features;
1959 if (FB[AVR::FeatureSRAM])
1960 Features.set(Feature_HasSRAMBit);
1961 if (FB[AVR::FeatureJMPCALL])
1962 Features.set(Feature_HasJMPCALLBit);
1963 if (FB[AVR::FeatureIJMPCALL])
1964 Features.set(Feature_HasIJMPCALLBit);
1965 if (FB[AVR::FeatureEIJMPCALL])
1966 Features.set(Feature_HasEIJMPCALLBit);
1967 if (FB[AVR::FeatureADDSUBIW])
1968 Features.set(Feature_HasADDSUBIWBit);
1969 if (FB[AVR::FeatureSmallStack])
1970 Features.set(Feature_HasSmallStackBit);
1971 if (FB[AVR::FeatureMOVW])
1972 Features.set(Feature_HasMOVWBit);
1973 if (FB[AVR::FeatureLPM])
1974 Features.set(Feature_HasLPMBit);
1975 if (FB[AVR::FeatureLPMX])
1976 Features.set(Feature_HasLPMXBit);
1977 if (FB[AVR::FeatureELPM])
1978 Features.set(Feature_HasELPMBit);
1979 if (FB[AVR::FeatureELPMX])
1980 Features.set(Feature_HasELPMXBit);
1981 if (FB[AVR::FeatureSPM])
1982 Features.set(Feature_HasSPMBit);
1983 if (FB[AVR::FeatureSPMX])
1984 Features.set(Feature_HasSPMXBit);
1985 if (FB[AVR::FeatureDES])
1986 Features.set(Feature_HasDESBit);
1987 if (FB[AVR::FeatureRMW])
1988 Features.set(Feature_SupportsRMWBit);
1989 if (FB[AVR::FeatureMultiplication])
1990 Features.set(Feature_SupportsMultiplicationBit);
1991 if (FB[AVR::FeatureBREAK])
1992 Features.set(Feature_HasBREAKBit);
1993 if (FB[AVR::FeatureTinyEncoding])
1994 Features.set(Feature_HasTinyEncodingBit);
1995 if (!(FB[AVR::FeatureTinyEncoding]))
1996 Features.set(Feature_HasNonTinyEncodingBit);
1997 return Features;
1998}
1999
2000inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2001 enum : uint8_t {
2002 CEFBS_None,
2003 CEFBS_HasADDSUBIW,
2004 CEFBS_HasBREAK,
2005 CEFBS_HasDES,
2006 CEFBS_HasEIJMPCALL,
2007 CEFBS_HasELPM,
2008 CEFBS_HasELPMX,
2009 CEFBS_HasIJMPCALL,
2010 CEFBS_HasJMPCALL,
2011 CEFBS_HasLPM,
2012 CEFBS_HasLPMX,
2013 CEFBS_HasMOVW,
2014 CEFBS_HasNonTinyEncoding,
2015 CEFBS_HasSPM,
2016 CEFBS_HasSPMX,
2017 CEFBS_HasSRAM,
2018 CEFBS_HasTinyEncoding,
2019 CEFBS_SupportsMultiplication,
2020 CEFBS_SupportsRMW,
2021 CEFBS_HasSRAM_HasNonTinyEncoding,
2022 CEFBS_HasSRAM_HasTinyEncoding,
2023 };
2024
2025 static constexpr FeatureBitset FeatureBitsets[] = {
2026 {}, // CEFBS_None
2027 {Feature_HasADDSUBIWBit, },
2028 {Feature_HasBREAKBit, },
2029 {Feature_HasDESBit, },
2030 {Feature_HasEIJMPCALLBit, },
2031 {Feature_HasELPMBit, },
2032 {Feature_HasELPMXBit, },
2033 {Feature_HasIJMPCALLBit, },
2034 {Feature_HasJMPCALLBit, },
2035 {Feature_HasLPMBit, },
2036 {Feature_HasLPMXBit, },
2037 {Feature_HasMOVWBit, },
2038 {Feature_HasNonTinyEncodingBit, },
2039 {Feature_HasSPMBit, },
2040 {Feature_HasSPMXBit, },
2041 {Feature_HasSRAMBit, },
2042 {Feature_HasTinyEncodingBit, },
2043 {Feature_SupportsMultiplicationBit, },
2044 {Feature_SupportsRMWBit, },
2045 {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
2046 {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
2047 };
2048 static constexpr uint8_t RequiredFeaturesRefs[] = {
2049 CEFBS_None, // PHI
2050 CEFBS_None, // INLINEASM
2051 CEFBS_None, // INLINEASM_BR
2052 CEFBS_None, // CFI_INSTRUCTION
2053 CEFBS_None, // EH_LABEL
2054 CEFBS_None, // GC_LABEL
2055 CEFBS_None, // ANNOTATION_LABEL
2056 CEFBS_None, // KILL
2057 CEFBS_None, // EXTRACT_SUBREG
2058 CEFBS_None, // INSERT_SUBREG
2059 CEFBS_None, // IMPLICIT_DEF
2060 CEFBS_None, // INIT_UNDEF
2061 CEFBS_None, // SUBREG_TO_REG
2062 CEFBS_None, // COPY_TO_REGCLASS
2063 CEFBS_None, // DBG_VALUE
2064 CEFBS_None, // DBG_VALUE_LIST
2065 CEFBS_None, // DBG_INSTR_REF
2066 CEFBS_None, // DBG_PHI
2067 CEFBS_None, // DBG_LABEL
2068 CEFBS_None, // REG_SEQUENCE
2069 CEFBS_None, // COPY
2070 CEFBS_None, // COPY_LANEMASK
2071 CEFBS_None, // BUNDLE
2072 CEFBS_None, // LIFETIME_START
2073 CEFBS_None, // LIFETIME_END
2074 CEFBS_None, // PSEUDO_PROBE
2075 CEFBS_None, // ARITH_FENCE
2076 CEFBS_None, // STACKMAP
2077 CEFBS_None, // FENTRY_CALL
2078 CEFBS_None, // PATCHPOINT
2079 CEFBS_None, // LOAD_STACK_GUARD
2080 CEFBS_None, // PREALLOCATED_SETUP
2081 CEFBS_None, // PREALLOCATED_ARG
2082 CEFBS_None, // STATEPOINT
2083 CEFBS_None, // LOCAL_ESCAPE
2084 CEFBS_None, // FAULTING_OP
2085 CEFBS_None, // PATCHABLE_OP
2086 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2087 CEFBS_None, // PATCHABLE_RET
2088 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2089 CEFBS_None, // PATCHABLE_TAIL_CALL
2090 CEFBS_None, // PATCHABLE_EVENT_CALL
2091 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2092 CEFBS_None, // ICALL_BRANCH_FUNNEL
2093 CEFBS_None, // FAKE_USE
2094 CEFBS_None, // MEMBARRIER
2095 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2096 CEFBS_None, // RELOC_NONE
2097 CEFBS_None, // CONVERGENCECTRL_ENTRY
2098 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2099 CEFBS_None, // CONVERGENCECTRL_LOOP
2100 CEFBS_None, // CONVERGENCECTRL_GLUE
2101 CEFBS_None, // G_ASSERT_SEXT
2102 CEFBS_None, // G_ASSERT_ZEXT
2103 CEFBS_None, // G_ASSERT_ALIGN
2104 CEFBS_None, // G_ADD
2105 CEFBS_None, // G_SUB
2106 CEFBS_None, // G_MUL
2107 CEFBS_None, // G_SDIV
2108 CEFBS_None, // G_UDIV
2109 CEFBS_None, // G_SREM
2110 CEFBS_None, // G_UREM
2111 CEFBS_None, // G_SDIVREM
2112 CEFBS_None, // G_UDIVREM
2113 CEFBS_None, // G_AND
2114 CEFBS_None, // G_OR
2115 CEFBS_None, // G_XOR
2116 CEFBS_None, // G_ABDS
2117 CEFBS_None, // G_ABDU
2118 CEFBS_None, // G_UAVGFLOOR
2119 CEFBS_None, // G_UAVGCEIL
2120 CEFBS_None, // G_SAVGFLOOR
2121 CEFBS_None, // G_SAVGCEIL
2122 CEFBS_None, // G_IMPLICIT_DEF
2123 CEFBS_None, // G_PHI
2124 CEFBS_None, // G_FRAME_INDEX
2125 CEFBS_None, // G_GLOBAL_VALUE
2126 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2127 CEFBS_None, // G_CONSTANT_POOL
2128 CEFBS_None, // G_EXTRACT
2129 CEFBS_None, // G_UNMERGE_VALUES
2130 CEFBS_None, // G_INSERT
2131 CEFBS_None, // G_MERGE_VALUES
2132 CEFBS_None, // G_BUILD_VECTOR
2133 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2134 CEFBS_None, // G_CONCAT_VECTORS
2135 CEFBS_None, // G_PTRTOINT
2136 CEFBS_None, // G_INTTOPTR
2137 CEFBS_None, // G_BITCAST
2138 CEFBS_None, // G_FREEZE
2139 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2140 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2141 CEFBS_None, // G_INTRINSIC_TRUNC
2142 CEFBS_None, // G_INTRINSIC_ROUND
2143 CEFBS_None, // G_INTRINSIC_LRINT
2144 CEFBS_None, // G_INTRINSIC_LLRINT
2145 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2146 CEFBS_None, // G_READCYCLECOUNTER
2147 CEFBS_None, // G_READSTEADYCOUNTER
2148 CEFBS_None, // G_LOAD
2149 CEFBS_None, // G_SEXTLOAD
2150 CEFBS_None, // G_ZEXTLOAD
2151 CEFBS_None, // G_FPEXTLOAD
2152 CEFBS_None, // G_INDEXED_LOAD
2153 CEFBS_None, // G_INDEXED_SEXTLOAD
2154 CEFBS_None, // G_INDEXED_ZEXTLOAD
2155 CEFBS_None, // G_STORE
2156 CEFBS_None, // G_FPTRUNCSTORE
2157 CEFBS_None, // G_INDEXED_STORE
2158 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2159 CEFBS_None, // G_ATOMIC_CMPXCHG
2160 CEFBS_None, // G_ATOMICRMW_XCHG
2161 CEFBS_None, // G_ATOMICRMW_ADD
2162 CEFBS_None, // G_ATOMICRMW_SUB
2163 CEFBS_None, // G_ATOMICRMW_AND
2164 CEFBS_None, // G_ATOMICRMW_NAND
2165 CEFBS_None, // G_ATOMICRMW_OR
2166 CEFBS_None, // G_ATOMICRMW_XOR
2167 CEFBS_None, // G_ATOMICRMW_MAX
2168 CEFBS_None, // G_ATOMICRMW_MIN
2169 CEFBS_None, // G_ATOMICRMW_UMAX
2170 CEFBS_None, // G_ATOMICRMW_UMIN
2171 CEFBS_None, // G_ATOMICRMW_FADD
2172 CEFBS_None, // G_ATOMICRMW_FSUB
2173 CEFBS_None, // G_ATOMICRMW_FMAX
2174 CEFBS_None, // G_ATOMICRMW_FMIN
2175 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2176 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2177 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2178 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2179 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2180 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2181 CEFBS_None, // G_ATOMICRMW_USUB_COND
2182 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2183 CEFBS_None, // G_FENCE
2184 CEFBS_None, // G_PREFETCH
2185 CEFBS_None, // G_BRCOND
2186 CEFBS_None, // G_BRINDIRECT
2187 CEFBS_None, // G_INVOKE_REGION_START
2188 CEFBS_None, // G_INTRINSIC
2189 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2190 CEFBS_None, // G_INTRINSIC_CONVERGENT
2191 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2192 CEFBS_None, // G_ANYEXT
2193 CEFBS_None, // G_TRUNC
2194 CEFBS_None, // G_TRUNC_SSAT_S
2195 CEFBS_None, // G_TRUNC_SSAT_U
2196 CEFBS_None, // G_TRUNC_USAT_U
2197 CEFBS_None, // G_CONSTANT
2198 CEFBS_None, // G_FCONSTANT
2199 CEFBS_None, // G_VASTART
2200 CEFBS_None, // G_VAARG
2201 CEFBS_None, // G_SEXT
2202 CEFBS_None, // G_SEXT_INREG
2203 CEFBS_None, // G_ZEXT
2204 CEFBS_None, // G_SHL
2205 CEFBS_None, // G_LSHR
2206 CEFBS_None, // G_ASHR
2207 CEFBS_None, // G_FSHL
2208 CEFBS_None, // G_FSHR
2209 CEFBS_None, // G_ROTR
2210 CEFBS_None, // G_ROTL
2211 CEFBS_None, // G_ICMP
2212 CEFBS_None, // G_FCMP
2213 CEFBS_None, // G_SCMP
2214 CEFBS_None, // G_UCMP
2215 CEFBS_None, // G_SELECT
2216 CEFBS_None, // G_UADDO
2217 CEFBS_None, // G_UADDE
2218 CEFBS_None, // G_USUBO
2219 CEFBS_None, // G_USUBE
2220 CEFBS_None, // G_SADDO
2221 CEFBS_None, // G_SADDE
2222 CEFBS_None, // G_SSUBO
2223 CEFBS_None, // G_SSUBE
2224 CEFBS_None, // G_UMULO
2225 CEFBS_None, // G_SMULO
2226 CEFBS_None, // G_UMULH
2227 CEFBS_None, // G_SMULH
2228 CEFBS_None, // G_UADDSAT
2229 CEFBS_None, // G_SADDSAT
2230 CEFBS_None, // G_USUBSAT
2231 CEFBS_None, // G_SSUBSAT
2232 CEFBS_None, // G_USHLSAT
2233 CEFBS_None, // G_SSHLSAT
2234 CEFBS_None, // G_SMULFIX
2235 CEFBS_None, // G_UMULFIX
2236 CEFBS_None, // G_SMULFIXSAT
2237 CEFBS_None, // G_UMULFIXSAT
2238 CEFBS_None, // G_SDIVFIX
2239 CEFBS_None, // G_UDIVFIX
2240 CEFBS_None, // G_SDIVFIXSAT
2241 CEFBS_None, // G_UDIVFIXSAT
2242 CEFBS_None, // G_FADD
2243 CEFBS_None, // G_FSUB
2244 CEFBS_None, // G_FMUL
2245 CEFBS_None, // G_FMA
2246 CEFBS_None, // G_FMAD
2247 CEFBS_None, // G_FDIV
2248 CEFBS_None, // G_FREM
2249 CEFBS_None, // G_FMODF
2250 CEFBS_None, // G_FPOW
2251 CEFBS_None, // G_FPOWI
2252 CEFBS_None, // G_FEXP
2253 CEFBS_None, // G_FEXP2
2254 CEFBS_None, // G_FEXP10
2255 CEFBS_None, // G_FLOG
2256 CEFBS_None, // G_FLOG2
2257 CEFBS_None, // G_FLOG10
2258 CEFBS_None, // G_FLDEXP
2259 CEFBS_None, // G_FFREXP
2260 CEFBS_None, // G_FNEG
2261 CEFBS_None, // G_FPEXT
2262 CEFBS_None, // G_FPTRUNC
2263 CEFBS_None, // G_FPTOSI
2264 CEFBS_None, // G_FPTOUI
2265 CEFBS_None, // G_SITOFP
2266 CEFBS_None, // G_UITOFP
2267 CEFBS_None, // G_FPTOSI_SAT
2268 CEFBS_None, // G_FPTOUI_SAT
2269 CEFBS_None, // G_FABS
2270 CEFBS_None, // G_FCOPYSIGN
2271 CEFBS_None, // G_IS_FPCLASS
2272 CEFBS_None, // G_FCANONICALIZE
2273 CEFBS_None, // G_FMINNUM
2274 CEFBS_None, // G_FMAXNUM
2275 CEFBS_None, // G_FMINNUM_IEEE
2276 CEFBS_None, // G_FMAXNUM_IEEE
2277 CEFBS_None, // G_FMINIMUM
2278 CEFBS_None, // G_FMAXIMUM
2279 CEFBS_None, // G_FMINIMUMNUM
2280 CEFBS_None, // G_FMAXIMUMNUM
2281 CEFBS_None, // G_GET_FPENV
2282 CEFBS_None, // G_SET_FPENV
2283 CEFBS_None, // G_RESET_FPENV
2284 CEFBS_None, // G_GET_FPMODE
2285 CEFBS_None, // G_SET_FPMODE
2286 CEFBS_None, // G_RESET_FPMODE
2287 CEFBS_None, // G_GET_ROUNDING
2288 CEFBS_None, // G_SET_ROUNDING
2289 CEFBS_None, // G_PTR_ADD
2290 CEFBS_None, // G_PTRMASK
2291 CEFBS_None, // G_SMIN
2292 CEFBS_None, // G_SMAX
2293 CEFBS_None, // G_UMIN
2294 CEFBS_None, // G_UMAX
2295 CEFBS_None, // G_ABS
2296 CEFBS_None, // G_LROUND
2297 CEFBS_None, // G_LLROUND
2298 CEFBS_None, // G_BR
2299 CEFBS_None, // G_BRJT
2300 CEFBS_None, // G_VSCALE
2301 CEFBS_None, // G_INSERT_SUBVECTOR
2302 CEFBS_None, // G_EXTRACT_SUBVECTOR
2303 CEFBS_None, // G_INSERT_VECTOR_ELT
2304 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2305 CEFBS_None, // G_SHUFFLE_VECTOR
2306 CEFBS_None, // G_SPLAT_VECTOR
2307 CEFBS_None, // G_STEP_VECTOR
2308 CEFBS_None, // G_VECTOR_COMPRESS
2309 CEFBS_None, // G_CTTZ
2310 CEFBS_None, // G_CTTZ_ZERO_POISON
2311 CEFBS_None, // G_CTLZ
2312 CEFBS_None, // G_CTLZ_ZERO_POISON
2313 CEFBS_None, // G_CTLS
2314 CEFBS_None, // G_CTPOP
2315 CEFBS_None, // G_BSWAP
2316 CEFBS_None, // G_BITREVERSE
2317 CEFBS_None, // G_CLMUL
2318 CEFBS_None, // G_CLMULH
2319 CEFBS_None, // G_FCEIL
2320 CEFBS_None, // G_FCOS
2321 CEFBS_None, // G_FSIN
2322 CEFBS_None, // G_FSINCOS
2323 CEFBS_None, // G_FTAN
2324 CEFBS_None, // G_FACOS
2325 CEFBS_None, // G_FASIN
2326 CEFBS_None, // G_FATAN
2327 CEFBS_None, // G_FATAN2
2328 CEFBS_None, // G_FCOSH
2329 CEFBS_None, // G_FSINH
2330 CEFBS_None, // G_FTANH
2331 CEFBS_None, // G_FSQRT
2332 CEFBS_None, // G_FFLOOR
2333 CEFBS_None, // G_FRINT
2334 CEFBS_None, // G_FNEARBYINT
2335 CEFBS_None, // G_ADDRSPACE_CAST
2336 CEFBS_None, // G_BLOCK_ADDR
2337 CEFBS_None, // G_JUMP_TABLE
2338 CEFBS_None, // G_DYN_STACKALLOC
2339 CEFBS_None, // G_STACKSAVE
2340 CEFBS_None, // G_STACKRESTORE
2341 CEFBS_None, // G_STRICT_FADD
2342 CEFBS_None, // G_STRICT_FSUB
2343 CEFBS_None, // G_STRICT_FMUL
2344 CEFBS_None, // G_STRICT_FDIV
2345 CEFBS_None, // G_STRICT_FREM
2346 CEFBS_None, // G_STRICT_FMA
2347 CEFBS_None, // G_STRICT_FSQRT
2348 CEFBS_None, // G_STRICT_FLDEXP
2349 CEFBS_None, // G_STRICT_FCMP
2350 CEFBS_None, // G_STRICT_FCMPS
2351 CEFBS_None, // G_READ_REGISTER
2352 CEFBS_None, // G_WRITE_REGISTER
2353 CEFBS_None, // G_MEMCPY
2354 CEFBS_None, // G_MEMCPY_INLINE
2355 CEFBS_None, // G_MEMMOVE
2356 CEFBS_None, // G_MEMSET
2357 CEFBS_None, // G_BZERO
2358 CEFBS_None, // G_MEMSET_INLINE
2359 CEFBS_None, // G_TRAP
2360 CEFBS_None, // G_DEBUGTRAP
2361 CEFBS_None, // G_UBSANTRAP
2362 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2363 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2364 CEFBS_None, // G_VECREDUCE_FADD
2365 CEFBS_None, // G_VECREDUCE_FMUL
2366 CEFBS_None, // G_VECREDUCE_FMAX
2367 CEFBS_None, // G_VECREDUCE_FMIN
2368 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2369 CEFBS_None, // G_VECREDUCE_FMINIMUM
2370 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2371 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2372 CEFBS_None, // G_VECREDUCE_ADD
2373 CEFBS_None, // G_VECREDUCE_MUL
2374 CEFBS_None, // G_VECREDUCE_AND
2375 CEFBS_None, // G_VECREDUCE_OR
2376 CEFBS_None, // G_VECREDUCE_XOR
2377 CEFBS_None, // G_VECREDUCE_SMAX
2378 CEFBS_None, // G_VECREDUCE_SMIN
2379 CEFBS_None, // G_VECREDUCE_UMAX
2380 CEFBS_None, // G_VECREDUCE_UMIN
2381 CEFBS_None, // G_SBFX
2382 CEFBS_None, // G_UBFX
2383 CEFBS_None, // ADCWRdRr
2384 CEFBS_None, // ADDWRdRr
2385 CEFBS_None, // ADIWRdKP
2386 CEFBS_None, // ADJCALLSTACKDOWN
2387 CEFBS_None, // ADJCALLSTACKUP
2388 CEFBS_None, // ANDIWRdK
2389 CEFBS_None, // ANDWRdRr
2390 CEFBS_None, // ASRBNRd
2391 CEFBS_None, // ASRWLoRd
2392 CEFBS_None, // ASRWNRd
2393 CEFBS_None, // ASRWRd
2394 CEFBS_None, // Asr16
2395 CEFBS_None, // Asr32
2396 CEFBS_None, // Asr8
2397 CEFBS_None, // AtomicFence
2398 CEFBS_None, // AtomicLoad16
2399 CEFBS_None, // AtomicLoad8
2400 CEFBS_None, // AtomicLoadAdd16
2401 CEFBS_None, // AtomicLoadAdd8
2402 CEFBS_None, // AtomicLoadAnd16
2403 CEFBS_None, // AtomicLoadAnd8
2404 CEFBS_None, // AtomicLoadOr16
2405 CEFBS_None, // AtomicLoadOr8
2406 CEFBS_None, // AtomicLoadSub16
2407 CEFBS_None, // AtomicLoadSub8
2408 CEFBS_None, // AtomicLoadXor16
2409 CEFBS_None, // AtomicLoadXor8
2410 CEFBS_None, // AtomicStore16
2411 CEFBS_None, // AtomicStore8
2412 CEFBS_None, // COMWRd
2413 CEFBS_None, // CPCWRdRr
2414 CEFBS_None, // CPWRdRr
2415 CEFBS_None, // CopyZero
2416 CEFBS_HasELPM, // ELPMBRdZ
2417 CEFBS_HasELPMX, // ELPMBRdZPi
2418 CEFBS_HasELPM, // ELPMWRdZ
2419 CEFBS_HasELPMX, // ELPMWRdZPi
2420 CEFBS_None, // EORWRdRr
2421 CEFBS_None, // FRMIDX
2422 CEFBS_None, // FRMSP
2423 CEFBS_None, // INWRdA
2424 CEFBS_HasSRAM, // LDDWRdPtrQ
2425 CEFBS_HasSRAM, // LDDWRdYQ
2426 CEFBS_None, // LDIWRdK
2427 CEFBS_HasSRAM_HasNonTinyEncoding, // LDSWRdK
2428 CEFBS_HasSRAM, // LDWRdPtr
2429 CEFBS_HasSRAM, // LDWRdPtrPd
2430 CEFBS_HasSRAM, // LDWRdPtrPi
2431 CEFBS_HasLPM, // LPMBRdZ
2432 CEFBS_HasLPM, // LPMWRdZ
2433 CEFBS_HasLPMX, // LPMWRdZPi
2434 CEFBS_None, // LSLBNRd
2435 CEFBS_None, // LSLWHiRd
2436 CEFBS_None, // LSLWNRd
2437 CEFBS_None, // LSLWRd
2438 CEFBS_None, // LSRBNRd
2439 CEFBS_None, // LSRWLoRd
2440 CEFBS_None, // LSRWNRd
2441 CEFBS_None, // LSRWRd
2442 CEFBS_None, // Lsl16
2443 CEFBS_None, // Lsl32
2444 CEFBS_None, // Lsl8
2445 CEFBS_None, // Lsr16
2446 CEFBS_None, // Lsr32
2447 CEFBS_None, // Lsr8
2448 CEFBS_None, // NEGWRd
2449 CEFBS_None, // ORIWRdK
2450 CEFBS_None, // ORWRdRr
2451 CEFBS_None, // OUTWARr
2452 CEFBS_HasSRAM, // POPWRd
2453 CEFBS_HasSRAM, // PUSHWRr
2454 CEFBS_HasNonTinyEncoding, // ROLBRdR1
2455 CEFBS_HasTinyEncoding, // ROLBRdR17
2456 CEFBS_None, // ROLWRd
2457 CEFBS_None, // RORBRd
2458 CEFBS_None, // RORWRd
2459 CEFBS_None, // Rol16
2460 CEFBS_None, // Rol8
2461 CEFBS_None, // Ror16
2462 CEFBS_None, // Ror8
2463 CEFBS_None, // SBCIWRdK
2464 CEFBS_None, // SBCWRdRr
2465 CEFBS_None, // SEXT
2466 CEFBS_None, // SPREAD
2467 CEFBS_None, // SPWRITE
2468 CEFBS_None, // STDSPQRr
2469 CEFBS_HasSRAM, // STDWPtrQRr
2470 CEFBS_None, // STDWSPQRr
2471 CEFBS_HasSRAM_HasNonTinyEncoding, // STSWKRr
2472 CEFBS_HasSRAM, // STWPtrPdRr
2473 CEFBS_HasSRAM, // STWPtrPiRr
2474 CEFBS_HasSRAM, // STWPtrRr
2475 CEFBS_None, // SUBIWRdK
2476 CEFBS_None, // SUBWRdRr
2477 CEFBS_None, // Select16
2478 CEFBS_None, // Select8
2479 CEFBS_None, // ZEXT
2480 CEFBS_None, // ADCRdRr
2481 CEFBS_None, // ADDRdRr
2482 CEFBS_HasADDSUBIW, // ADIWRdK
2483 CEFBS_None, // ANDIRdK
2484 CEFBS_None, // ANDRdRr
2485 CEFBS_None, // ASRRd
2486 CEFBS_None, // BCLRs
2487 CEFBS_None, // BLD
2488 CEFBS_None, // BRBCsk
2489 CEFBS_None, // BRBSsk
2490 CEFBS_HasBREAK, // BREAK
2491 CEFBS_None, // BREQk
2492 CEFBS_None, // BRGEk
2493 CEFBS_None, // BRLOk
2494 CEFBS_None, // BRLTk
2495 CEFBS_None, // BRMIk
2496 CEFBS_None, // BRNEk
2497 CEFBS_None, // BRPLk
2498 CEFBS_None, // BRSHk
2499 CEFBS_None, // BSETs
2500 CEFBS_None, // BST
2501 CEFBS_HasJMPCALL, // CALLk
2502 CEFBS_None, // CBIAb
2503 CEFBS_None, // COMRd
2504 CEFBS_None, // CPCRdRr
2505 CEFBS_None, // CPIRdK
2506 CEFBS_None, // CPRdRr
2507 CEFBS_None, // CPSE
2508 CEFBS_None, // DECRd
2509 CEFBS_HasDES, // DESK
2510 CEFBS_HasEIJMPCALL, // EICALL
2511 CEFBS_HasEIJMPCALL, // EIJMP
2512 CEFBS_HasELPM, // ELPM
2513 CEFBS_HasELPMX, // ELPMRdZ
2514 CEFBS_HasELPMX, // ELPMRdZPi
2515 CEFBS_None, // EORRdRr
2516 CEFBS_SupportsMultiplication, // FMUL
2517 CEFBS_SupportsMultiplication, // FMULS
2518 CEFBS_SupportsMultiplication, // FMULSU
2519 CEFBS_HasIJMPCALL, // ICALL
2520 CEFBS_HasIJMPCALL, // IJMP
2521 CEFBS_None, // INCRd
2522 CEFBS_None, // INRdA
2523 CEFBS_HasJMPCALL, // JMPk
2524 CEFBS_SupportsRMW, // LACZRd
2525 CEFBS_SupportsRMW, // LASZRd
2526 CEFBS_SupportsRMW, // LATZRd
2527 CEFBS_HasSRAM_HasNonTinyEncoding, // LDDRdPtrQ
2528 CEFBS_None, // LDIRdK
2529 CEFBS_HasSRAM, // LDRdPtr
2530 CEFBS_HasSRAM, // LDRdPtrPd
2531 CEFBS_HasSRAM, // LDRdPtrPi
2532 CEFBS_HasSRAM_HasNonTinyEncoding, // LDSRdK
2533 CEFBS_HasSRAM_HasTinyEncoding, // LDSRdKTiny
2534 CEFBS_HasLPM, // LPM
2535 CEFBS_HasLPMX, // LPMRdZ
2536 CEFBS_HasLPMX, // LPMRdZPi
2537 CEFBS_None, // LSRRd
2538 CEFBS_None, // MOVRdRr
2539 CEFBS_HasMOVW, // MOVWRdRr
2540 CEFBS_SupportsMultiplication, // MULRdRr
2541 CEFBS_SupportsMultiplication, // MULSRdRr
2542 CEFBS_SupportsMultiplication, // MULSURdRr
2543 CEFBS_None, // NEGRd
2544 CEFBS_None, // NOP
2545 CEFBS_None, // ORIRdK
2546 CEFBS_None, // ORRdRr
2547 CEFBS_None, // OUTARr
2548 CEFBS_HasSRAM, // POPRd
2549 CEFBS_HasSRAM, // PUSHRr
2550 CEFBS_None, // RCALLk
2551 CEFBS_None, // RET
2552 CEFBS_None, // RETI
2553 CEFBS_None, // RJMPk
2554 CEFBS_None, // RORRd
2555 CEFBS_None, // SBCIRdK
2556 CEFBS_None, // SBCRdRr
2557 CEFBS_None, // SBIAb
2558 CEFBS_None, // SBICAb
2559 CEFBS_None, // SBISAb
2560 CEFBS_HasADDSUBIW, // SBIWRdK
2561 CEFBS_None, // SBRCRrB
2562 CEFBS_None, // SBRSRrB
2563 CEFBS_None, // SLEEP
2564 CEFBS_HasSPM, // SPM
2565 CEFBS_HasSPMX, // SPMZPi
2566 CEFBS_HasSRAM_HasNonTinyEncoding, // STDPtrQRr
2567 CEFBS_HasSRAM, // STPtrPdRr
2568 CEFBS_HasSRAM, // STPtrPiRr
2569 CEFBS_HasSRAM, // STPtrRr
2570 CEFBS_HasSRAM_HasNonTinyEncoding, // STSKRr
2571 CEFBS_HasSRAM_HasTinyEncoding, // STSKRrTiny
2572 CEFBS_None, // SUBIRdK
2573 CEFBS_None, // SUBRdRr
2574 CEFBS_None, // SWAPRd
2575 CEFBS_None, // WDR
2576 CEFBS_SupportsRMW, // XCHZRd
2577 };
2578
2579 assert(Opcode < 528);
2580 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2581}
2582
2583
2584} // namespace llvm::AVR_MC
2585
2586#endif // GET_COMPUTE_FEATURES
2587
2588#ifdef GET_AVAILABLE_OPCODE_CHECKER
2589#undef GET_AVAILABLE_OPCODE_CHECKER
2590
2591namespace llvm::AVR_MC {
2592
2593bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2594 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2595 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2596 FeatureBitset MissingFeatures =
2597 (AvailableFeatures & RequiredFeatures) ^
2598 RequiredFeatures;
2599 return !MissingFeatures.any();
2600}
2601
2602} // namespace llvm::AVR_MC
2603
2604#endif // GET_AVAILABLE_OPCODE_CHECKER
2605
2606#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2607#undef ENABLE_INSTR_PREDICATE_VERIFIER
2608
2609#include <sstream>
2610
2611namespace llvm::AVR_MC {
2612
2613#ifndef NDEBUG
2614static const char *SubtargetFeatureNames[] = {
2615 "Feature_HasADDSUBIW",
2616 "Feature_HasBREAK",
2617 "Feature_HasDES",
2618 "Feature_HasEIJMPCALL",
2619 "Feature_HasELPM",
2620 "Feature_HasELPMX",
2621 "Feature_HasIJMPCALL",
2622 "Feature_HasJMPCALL",
2623 "Feature_HasLPM",
2624 "Feature_HasLPMX",
2625 "Feature_HasMOVW",
2626 "Feature_HasNonTinyEncoding",
2627 "Feature_HasSPM",
2628 "Feature_HasSPMX",
2629 "Feature_HasSRAM",
2630 "Feature_HasSmallStack",
2631 "Feature_HasTinyEncoding",
2632 "Feature_SupportsMultiplication",
2633 "Feature_SupportsRMW",
2634 nullptr
2635};
2636
2637#endif // NDEBUG
2638
2639void verifyInstructionPredicates(
2640 unsigned Opcode, const FeatureBitset &Features) {
2641#ifndef NDEBUG
2642 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2643 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2644 FeatureBitset MissingFeatures =
2645 (AvailableFeatures & RequiredFeatures) ^
2646 RequiredFeatures;
2647 if (MissingFeatures.any()) {
2648 std::ostringstream Msg;
2649 Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
2650 << " instruction but the ";
2651 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2652 if (MissingFeatures.test(i))
2653 Msg << SubtargetFeatureNames[i] << " ";
2654 Msg << "predicate(s) are not met";
2655 report_fatal_error(Msg.str().c_str());
2656 }
2657#endif // NDEBUG
2658}
2659
2660} // namespace llvm::AVR_MC
2661
2662#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2663
2664