1//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_AVR_INSTR_INFO_H
14#define LLVM_AVR_INSTR_INFO_H
15
16#include "llvm/CodeGen/TargetInstrInfo.h"
17
18#include "AVRRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "AVRGenInstrInfo.inc"
22#undef GET_INSTRINFO_HEADER
23
24namespace llvm {
25
26class AVRSubtarget;
27
28namespace AVRCC {
29
30/// AVR specific condition codes.
31/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
32/// They must be kept in synch.
33enum CondCodes {
34 COND_EQ, //!< Equal
35 COND_NE, //!< Not equal
36 COND_GE, //!< Greater than or equal
37 COND_LT, //!< Less than
38 COND_SH, //!< Unsigned same or higher
39 COND_LO, //!< Unsigned lower
40 COND_MI, //!< Minus
41 COND_PL, //!< Plus
42 COND_INVALID
43};
44
45} // end of namespace AVRCC
46
47namespace AVRII {
48
49/// Specifies a target operand flag.
50enum TOF {
51 MO_NO_FLAG,
52
53 /// On a symbol operand, this represents the lo part.
54 MO_LO = (1 << 1),
55
56 /// On a symbol operand, this represents the hi part.
57 MO_HI = (1 << 2),
58
59 /// On a symbol operand, this represents it has to be negated.
60 MO_NEG = (1 << 3)
61};
62
63} // end of namespace AVRII
64
65/// Utilities related to the AVR instruction set.
66class AVRInstrInfo : public AVRGenInstrInfo {
67public:
68 explicit AVRInstrInfo(const AVRSubtarget &STI);
69
70 const AVRRegisterInfo &getRegisterInfo() const { return RI; }
71
72 const TargetRegisterClass *getInlineAsmMemoryOperandRegClass(
73 InlineAsm::ConstraintCode C) const override {
74 return &AVR::PTRDISPREGSRegClass;
75 }
76
77 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
78 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
79 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
80 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
81
82 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
83 const DebugLoc &DL, Register DestReg, Register SrcReg,
84 bool KillSrc, bool RenamableDest = false,
85 bool RenamableSrc = false) const override;
86 void storeRegToStackSlot(
87 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
88 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
89 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
90 void loadRegFromStackSlot(
91 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
92 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
93 unsigned SubReg = 0,
94 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
95 Register isLoadFromStackSlot(const MachineInstr &MI,
96 int &FrameIndex) const override;
97 Register isStoreToStackSlot(const MachineInstr &MI,
98 int &FrameIndex) const override;
99
100 // Branch analysis.
101 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
102 MachineBasicBlock *&FBB,
103 SmallVectorImpl<MachineOperand> &Cond,
104 bool AllowModify = false) const override;
105 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
106 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
107 const DebugLoc &DL,
108 int *BytesAdded = nullptr) const override;
109 unsigned removeBranch(MachineBasicBlock &MBB,
110 int *BytesRemoved = nullptr) const override;
111 bool
112 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
113
114 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
115
116 bool isBranchOffsetInRange(unsigned BranchOpc,
117 int64_t BrOffset) const override;
118
119 void insertIndirectBranch(MachineBasicBlock &MBB,
120 MachineBasicBlock &NewDestBB,
121 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
122 int64_t BrOffset, RegScavenger *RS) const override;
123
124private:
125 const AVRRegisterInfo RI;
126
127protected:
128 const AVRSubtarget &STI;
129};
130
131} // end namespace llvm
132
133#endif // LLVM_AVR_INSTR_INFO_H
134